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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
Data Fields | |
| union { | |
| __OM uint8_t u8 | |
| __OM uint16_t u16 | |
| __OM uint32_t u32 | |
| } | PORT [32U] |
| __IOM uint32_t | TER |
| __IOM uint32_t | TPR |
| __IOM uint32_t | TCR |
| __OM uint32_t | IWR |
| __IM uint32_t | IRR |
| __IOM uint32_t | IMCR |
| __OM uint32_t | LAR |
| __IM uint32_t | LSR |
| __IM uint32_t | DEVARCH |
| __IM uint32_t | PID4 |
| __IM uint32_t | PID5 |
| __IM uint32_t | PID6 |
| __IM uint32_t | PID7 |
| __IM uint32_t | PID0 |
| __IM uint32_t | PID1 |
| __IM uint32_t | PID2 |
| __IM uint32_t | PID3 |
| __IM uint32_t | CID0 |
| __IM uint32_t | CID1 |
| __IM uint32_t | CID2 |
| __IM uint32_t | CID3 |
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
| __IM uint32_t ITM_Type::CID0 |
Offset: 0xFF0 (R/ ) ITM Component Identification Register #0
| __IM uint32_t ITM_Type::CID1 |
Offset: 0xFF4 (R/ ) ITM Component Identification Register #1
| __IM uint32_t ITM_Type::CID2 |
Offset: 0xFF8 (R/ ) ITM Component Identification Register #2
| __IM uint32_t ITM_Type::CID3 |
Offset: 0xFFC (R/ ) ITM Component Identification Register #3
| __IM uint32_t ITM_Type::DEVARCH |
Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only)
| __IOM uint32_t ITM_Type::IMCR |
Offset: 0xF00 (R/W) ITM Integration Mode Control Register
| __IM uint32_t ITM_Type::IRR |
Offset: 0xEFC (R/ ) ITM Integration Read Register
| __OM uint32_t ITM_Type::IWR |
Offset: 0xEF8 ( /W) ITM Integration Write Register
| __OM uint32_t ITM_Type::LAR |
Offset: 0xFB0 ( /W) ITM Lock Access Register
| __IM uint32_t ITM_Type::LSR |
Offset: 0xFB4 (R/ ) ITM Lock Status Register
| __IM uint32_t ITM_Type::PID0 |
Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0
| __IM uint32_t ITM_Type::PID1 |
Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1
| __IM uint32_t ITM_Type::PID2 |
Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2
| __IM uint32_t ITM_Type::PID3 |
Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3
| __IM uint32_t ITM_Type::PID4 |
Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4
| __IM uint32_t ITM_Type::PID5 |
Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5
| __IM uint32_t ITM_Type::PID6 |
Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6
| __IM uint32_t ITM_Type::PID7 |
Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7
| __OM { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
| __IOM uint32_t ITM_Type::TCR |
Offset: 0xE80 (R/W) ITM Trace Control Register
| __IOM uint32_t ITM_Type::TER |
Offset: 0xE00 (R/W) ITM Trace Enable Register
| __IOM uint32_t ITM_Type::TPR |
Offset: 0xE40 (R/W) ITM Trace Privilege Register
| __OM uint16_t ITM_Type::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
| __OM uint32_t ITM_Type::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
| __OM uint8_t ITM_Type::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
