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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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Structure type to access the Floating Point Unit (FPU). More...
Data Fields | |
| uint32_t | RESERVED0 [1] |
| Reserved. More... | |
| __IOM uint32_t | FPCCR |
| Offset: 0x004 (R/W) Floating-Point Context Control Register. More... | |
| __IOM uint32_t | FPCAR |
| Offset: 0x008 (R/W) Floating-Point Context Address Register. More... | |
| __IOM uint32_t | FPDSCR |
| Offset: 0x00C (R/W) Floating-Point Default Status Control Register. More... | |
| __IM uint32_t | MVFR0 |
| Offset: 0x010 (R/ ) Media and FP Feature Register 0. More... | |
| __IM uint32_t | MVFR1 |
| Offset: 0x014 (R/ ) Media and FP Feature Register 1. More... | |
Structure type to access the Floating Point Unit (FPU).
| __IOM uint32_t FPU_Type::FPCAR |
Offset: 0x008 (R/W) Floating-Point Context Address Register.
| __IOM uint32_t FPU_Type::FPCCR |
Offset: 0x004 (R/W) Floating-Point Context Control Register.
| __IOM uint32_t FPU_Type::FPDSCR |
Offset: 0x00C (R/W) Floating-Point Default Status Control Register.
| __IM uint32_t FPU_Type::MVFR0 |
Offset: 0x010 (R/ ) Media and FP Feature Register 0.
| __IM uint32_t FPU_Type::MVFR1 |
Offset: 0x014 (R/ ) Media and FP Feature Register 1.
| uint32_t FPU_Type::RESERVED0[1] |
Reserved.
