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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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CMSIS-Core (Cortex-M)
Version 5.6.0
CMSIS-Core support for Cortex-M processor-based devices
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Structure type to access the Core Debug Register (CoreDebug). More...
Data Fields | |
| __IOM uint32_t | DHCSR |
| Offset: 0x000 (R/W) Debug Halting Control and Status Register. More... | |
| __OM uint32_t | DCRSR |
| Offset: 0x004 ( /W) Debug Core Register Selector Register. More... | |
| __IOM uint32_t | DCRDR |
| Offset: 0x008 (R/W) Debug Core Register Data Register. More... | |
| __IOM uint32_t | DEMCR |
| Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. More... | |
Structure type to access the Core Debug Register (CoreDebug).
| __IOM uint32_t CoreDebug_Type::DCRDR |
Offset: 0x008 (R/W) Debug Core Register Data Register.
| __OM uint32_t CoreDebug_Type::DCRSR |
Offset: 0x004 ( /W) Debug Core Register Selector Register.
| __IOM uint32_t CoreDebug_Type::DEMCR |
Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.
| __IOM uint32_t CoreDebug_Type::DHCSR |
Offset: 0x000 (R/W) Debug Halting Control and Status Register.
