CMSIS-Core (Cortex-M)  Version 5.2.1
CMSIS-Core support for Cortex-M processor-based devices
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Here is a list of all modules:
[detail level 12]
oVersion ControlVersion #define symbols for CMSIS release specific C/C++ source code
oCompiler ControlCompiler agnostic #define symbols for generic C/C++ source code
oPeripheral AccessNaming conventions and optional features for accessing peripherals
oSystem and Clock ConfigurationFunctions for system and clock setup available in system_device.c
oInterrupts and Exceptions (NVIC)Functions to access the Nested Vector Interrupt Controller (NVIC)
oCore Register AccessFunctions to access the Cortex-M core registers
oIntrinsic Functions for CPU InstructionsFunctions that generate specific Cortex-M CPU Instructions
oIntrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]Access to dedicated SIMD instructions
oFPU FunctionsFunctions that relate to the Floating-Point Arithmetic Unit
oMPU Functions for Armv6-M/v7-MFunctions that relate to the Memory Protection Unit
|\Define valuesDefine values for MPU region setup
oMPU Functions for Armv8-MFunctions that relate to the Memory Protection Unit
oSystick Timer (SYSTICK)Initialize and start the SysTick timer
oDebug AccessDebug Access to the Instrumented Trace Macrocell (ITM)
oTrustZone for Armv8-M/v8.1-MFunctions that related to optional Armv8-M and Armv8.1-M security extension
|oCore Register Access FunctionsCore register Access functions related to TrustZone for Armv8-M
|oNVIC FunctionsNested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M
|oSysTick FunctionsSysTick functions related to TrustZone for Armv8-M
|oSAU FunctionsSecure Attribution Unit (SAU) functions related to TrustZone for Armv8-M
|\RTOS Context ManagementRTOS Thread Context Management for Armv8-M TrustZone
\Cache Functions (only Cortex-M7)Functions for Instruction and Data Cache
 oI-Cache FunctionsFunctions for the instruction cache
 \D-Cache FunctionsFunctions for the data cache