CMSIS-Core (Cortex-M)  Version 5.4.0
CMSIS-Core support for Cortex-M processor-based devices
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Revision History of CMSIS-Core (Cortex-M)
Version Description
V5.4.0 Added: Cortex-M55 cpu support Enhanced: MVE support for Armv8.1-MML Fixed: Device config define checks Added: L1 Cache functions for Armv7-M and later
V5.3.0 Added: Provisions for compiler-independent C startup code.
V5.2.1 Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0
V5.2.0 Added: Cortex-M35P support.
Added: Cortex-M1 support.
Added: Armv8.1 architecture support.
Added: __RESTRICT and __STATIC_FORCEINLINE compiler control macros.
V5.1.2 Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.
Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.
Added support for Cortex-M1 (beta).
Removed usage of register keyword.
Added defines for EXC_RETURN, FNC_RETURN and integrity signature values.
Enhanced MPUv7 API with defines for memory access attributes.
V5.1.1 Aligned MSPLIM and PSPLIM access functions along supported compilers.
V5.1.0 Added MPU Functions for ARMv8-M for Cortex-M23/M33.
Moved __SSAT and __USAT intrinsics to CMSIS-Core.
Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.
V5.0.2 Added macros __UNALIGNED_UINT16_READ, __UNALIGNED_UINT16_WRITE.
Added macros __UNALIGNED_UINT32_READ, __UNALIGNED_UINT32_WRITE.
Deprecated macro __UNALIGNED_UINT32.
Changed Version Control macros to be core agnostic.
Added MPU Functions for Armv6-M/v7-M for Cortex-M0+/M3/M4/M7.
V5.0.1 Added: macro __PACKED_STRUCT.
Added: uVisor support.
V5.00 Added: Cortex-M23, Cortex-M33 support.
Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT.
Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT.
Reworked: SAU register and functions.
Added: macro __ALIGNED.
Updated: function SCB_EnableICache.
Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions.
Added: macro __PACKED.
Updated: compiler specific include files.
Updated: core dependant include files.
Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.
V5.00
Beta 6
Added: SCB_CFSR register bit definitions.
Added: function NVIC_GetEnableIRQ.
Updated: core instruction macros __NOP, __WFI, __WFE, __SEV for toolchain GCC.
V5.00
Beta 5
Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.
Added: DSP libraries build projects to CMSIS pack.
V5.00
Beta 4
Updated: ARMv8M device files.
Corrected: ARMv8MBL interrupts.
Reworked: NVIC functions.
V5.00
Beta 2
Changed: ARMv8M SAU regions to 8.
Changed: moved function TZ_SAU_Setup to file partition_<device>.h.
Changed: license under Apache-2.0.
Added: check if macro is defined before use.
Corrected: function SCB_DisableDCache.
Corrected: macros _VAL2FLD, _FLD2VAL.
Added: NVIC function virtualization with macros CMSIS_NVIC_VIRTUAL and CMSIS_VECTAB_VIRTUAL.
V5.00
Beta 1
Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.
Renamed: core_*.h to lower case.
Added: function SCB_GetFPUType to all CMSIS cores.
Added: ARMv8-M support.
V4.30 Corrected: DoxyGen function parameter comments.
Corrected: IAR toolchain: removed for NVIC_SystemReset the attribute(noreturn).
Corrected: GCC toolchain: suppressed irrelevant compiler warnings.
Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).
V4.20 Corrected: MISRA-C:2004 violations.
Corrected: predefined macro for TI CCS Compiler.
Corrected: function __SHADD16 in arm_math.h.
Updated: cache functions for Cortex-M7.
Added: macros _VAL2FLD, _FLD2VAL to core_*.h.
Updated: functions __QASX, __QSAX, __SHASX, __SHSAX.
Corrected: potential bug in function __SHADD16.
V4.10 Corrected: MISRA-C:2004 violations.
Corrected: intrinsic functions __DSB, __DMB, __ISB.
Corrected: register definitions for ITCMCR register.
Corrected: register definitions for CONTROL_Type register.
Added: functions SCB_GetFPUType, SCB_InvalidateDCache_by_Addr to core_cm7.h.
Added: register definitions for APSR_Type, IPSR_Type, xPSR_Type register.
Added: __set_BASEPRI_MAX function to core_cmFunc.h.
Added: intrinsic functions __RBIT, __CLZ for Cortex-M0/CortexM0+.
V4.00 Added: Cortex-M7 support.
Added: intrinsic functions for __RRX, __LDRBT, __LDRHT, __LDRT, __STRBT, __STRHT, and __STRT
V3.40 Corrected: C++ include guard settings.
V3.30 Added: COSMIC tool chain support.
Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.
Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.
Corrected: GCC/CLang warnings.
V3.20 Added: __BKPT instruction intrinsic.
Added: __SMMLA instruction intrinsic for Cortex-M4.
Corrected: ITM_SendChar.
Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000.
Corrected: rework of in-line assembly functions to remove potential compiler warnings.
V3.01 Added support for Cortex-M0+ processor.
V3.00 Added support for GNU GCC ARM Embedded Compiler.
Added function __ROR.
Added Register Mapping for TPIU, DWT.
Added support for SC000 and SC300 processors.
Corrected ITM_SendChar function.
Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
Documentation restructured.
V2.10 Updated documentation.
Updated CMSIS core include files.
Changed CMSIS/Device folder structure.
Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
Reworked CMSIS DSP library examples.
V2.00 Added support for Cortex-M4 processor.
V1.30 Reworked Startup Concept.
Added additional Debug Functionality.
Changed folder structure.
Added doxygen comments.
Added definitions for bit.
V1.01 Added support for Cortex-M0 processor.
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
V1.00 Initial Release for Cortex-M3 processor.