S32 SDK

Detailed Description

Modules

 FTM Register Masks
 

Data Structures

struct  FTM_Type
 

Macros

#define FTM_CONTROLS_COUNT   8u
 
#define FTM_INSTANCE_COUNT   (4u)
 
#define FTM0_BASE   (0x40038000u)
 
#define FTM0   ((FTM_Type *)FTM0_BASE)
 
#define FTM1_BASE   (0x40039000u)
 
#define FTM1   ((FTM_Type *)FTM1_BASE)
 
#define FTM2_BASE   (0x4003A000u)
 
#define FTM2   ((FTM_Type *)FTM2_BASE)
 
#define FTM3_BASE   (0x40026000u)
 
#define FTM3   ((FTM_Type *)FTM3_BASE)
 
#define FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
 
#define FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }
 
#define FTM_IRQS_ARR_COUNT   (4u)
 
#define FTM_IRQS_CH_COUNT   (8u)
 
#define FTM_Fault_IRQS_CH_COUNT   (1u)
 
#define FTM_Overflow_IRQS_CH_COUNT   (1u)
 
#define FTM_Reload_IRQS_CH_COUNT   (1u)
 
#define FTM_IRQS
 
#define FTM_Fault_IRQS   { FTM0_Fault_IRQn, FTM1_Fault_IRQn, FTM2_Fault_IRQn, FTM3_Fault_IRQn }
 
#define FTM_Overflow_IRQS   { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn }
 
#define FTM_Reload_IRQS   { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn }
 

Typedefs

typedef struct FTM_TypeFTM_MemMapPtr
 

Macro Definition Documentation

#define FTM0   ((FTM_Type *)FTM0_BASE)

Peripheral FTM0 base pointer

Definition at line 4028 of file S32K144.h.

#define FTM0_BASE   (0x40038000u)

Peripheral FTM0 base address

Definition at line 4026 of file S32K144.h.

#define FTM1   ((FTM_Type *)FTM1_BASE)

Peripheral FTM1 base pointer

Definition at line 4032 of file S32K144.h.

#define FTM1_BASE   (0x40039000u)

Peripheral FTM1 base address

Definition at line 4030 of file S32K144.h.

#define FTM2   ((FTM_Type *)FTM2_BASE)

Peripheral FTM2 base pointer

Definition at line 4036 of file S32K144.h.

#define FTM2_BASE   (0x4003A000u)

Peripheral FTM2 base address

Definition at line 4034 of file S32K144.h.

#define FTM3   ((FTM_Type *)FTM3_BASE)

Peripheral FTM3 base pointer

Definition at line 4040 of file S32K144.h.

#define FTM3_BASE   (0x40026000u)

Peripheral FTM3 base address

Definition at line 4038 of file S32K144.h.

#define FTM_BASE_ADDRS   { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }

Array initializer of FTM peripheral base addresses

Definition at line 4042 of file S32K144.h.

#define FTM_BASE_PTRS   { FTM0, FTM1, FTM2, FTM3 }

Array initializer of FTM peripheral base pointers

Definition at line 4044 of file S32K144.h.

#define FTM_CONTROLS_COUNT   8u

FTM - Size of Registers Arrays

Definition at line 3979 of file S32K144.h.

#define FTM_Fault_IRQS   { FTM0_Fault_IRQn, FTM1_Fault_IRQn, FTM2_Fault_IRQn, FTM3_Fault_IRQn }

Definition at line 4060 of file S32K144.h.

#define FTM_Fault_IRQS_CH_COUNT   (1u)

Number of interrupt channels for the Fault type of FTM module.

Definition at line 4050 of file S32K144.h.

#define FTM_INSTANCE_COUNT   (4u)

Number of instances of the FTM module.

Definition at line 4021 of file S32K144.h.

#define FTM_IRQS_ARR_COUNT   (4u)

Number of interrupt vector arrays for the FTM module.

Definition at line 4046 of file S32K144.h.

#define FTM_IRQS_CH_COUNT   (8u)

Number of interrupt channels for the FTM module.

Definition at line 4048 of file S32K144.h.

Definition at line 4061 of file S32K144.h.

#define FTM_Overflow_IRQS_CH_COUNT   (1u)

Number of interrupt channels for the Overflow type of FTM module.

Definition at line 4052 of file S32K144.h.

Definition at line 4062 of file S32K144.h.

#define FTM_Reload_IRQS_CH_COUNT   (1u)

Number of interrupt channels for the Reload type of FTM module.

Definition at line 4054 of file S32K144.h.

Typedef Documentation

typedef struct FTM_Type * FTM_MemMapPtr