S32 SDK
adc_hal.c
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
30 #include "adc_hal.h"
31 
32 /*******************************************************************************
33  * Code
34  ******************************************************************************/
35 
36 /*FUNCTION**********************************************************************
37  *
38  * Function Name : ADC_HAL_Init
39  * Description : This function initializes the ADC instance to a known
40  * state (the register are written with their reset values from the Reference
41  * Manual).
42  *
43  * Implements : ADC_HAL_Init_Activity
44  *END**************************************************************************/
45 void ADC_HAL_Init(ADC_Type * const baseAddr)
46 {
47  baseAddr->SC1[0U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
48  baseAddr->SC1[1U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
49  baseAddr->SC1[2U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
50  baseAddr->SC1[3U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
51  baseAddr->SC1[4U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
52  baseAddr->SC1[5U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
53  baseAddr->SC1[6U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
54  baseAddr->SC1[7U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
55  baseAddr->SC1[8U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
56  baseAddr->SC1[9U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
57  baseAddr->SC1[10U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
58  baseAddr->SC1[11U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
59  baseAddr->SC1[12U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
60  baseAddr->SC1[13U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
61  baseAddr->SC1[14U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
62  baseAddr->SC1[15U] = ADC_SC1_ADCH(ADC_INPUTCHAN_DISABLED) | ADC_SC1_AIEN(0x00U);
64  baseAddr->CFG2 = ADC_CFG2_SMPLTS(0x0CU);
65  baseAddr->CV[0U] = ADC_CV_CV(0U);
66  baseAddr->CV[1U] = ADC_CV_CV(0U);
67  baseAddr->SC2 = ADC_SC2_REFSEL(ADC_VOLTAGEREF_VREF) | ADC_SC2_DMAEN(0x00U) | ADC_SC2_ACREN(0x00U) | ADC_SC2_ACFGT(0x00U) | ADC_SC2_ACFE(0x00U) |
68  ADC_SC2_ADTRG(0x00U);
69  baseAddr->SC3 = ADC_SC3_AVGS(ADC_AVERAGE_4) | ADC_SC3_AVGE(0x00U) | ADC_SC3_ADCO(0x00U) | ADC_SC3_CAL(0x00U);
70  baseAddr->USR_OFS = ADC_USR_OFS_USR_OFS(0U);
71  baseAddr->UG = ADC_UG_UG(4U);
72 }
73 
74 /*******************************************************************************
75  * EOF
76  ******************************************************************************/
#define ADC_INPUTCHAN_DISABLED
#define ADC_USR_OFS_USR_OFS(x)
Definition: S32K144.h:590
__IO uint32_t CFG1
Definition: S32K144.h:411
__IO uint32_t USR_OFS
Definition: S32K144.h:419
#define ADC_SC3_ADCO(x)
Definition: S32K144.h:571
#define ADC_SC2_ACREN(x)
Definition: S32K144.h:530
#define ADC_SC1_ADCH(x)
Definition: S32K144.h:477
#define ADC_SC2_REFSEL(x)
Definition: S32K144.h:522
#define ADC_CFG2_SMPLTS(x)
Definition: S32K144.h:507
#define ADC_SC2_DMAEN(x)
Definition: S32K144.h:526
#define ADC_SC3_AVGE(x)
Definition: S32K144.h:567
__IO uint32_t SC3
Definition: S32K144.h:416
__IO uint32_t CFG2
Definition: S32K144.h:412
#define ADC_SC2_ACFGT(x)
Definition: S32K144.h:534
#define ADC_SC2_ADTRG(x)
Definition: S32K144.h:542
#define ADC_CFG1_MODE(x)
Definition: S32K144.h:494
#define ADC_SC1_AIEN(x)
Definition: S32K144.h:481
#define ADC_CFG1_ADICLK(x)
Definition: S32K144.h:490
#define ADC_SC3_CAL(x)
Definition: S32K144.h:575
__IO uint32_t UG
Definition: S32K144.h:423
#define ADC_CV_CV(x)
Definition: S32K144.h:517
__IO uint32_t CV[ADC_CV_COUNT]
Definition: S32K144.h:414
__IO uint32_t SC2
Definition: S32K144.h:415
void ADC_HAL_Init(ADC_Type *const baseAddr)
Initializes the ADC instance to reset values.
Definition: adc_hal.c:45
#define ADC_SC3_AVGS(x)
Definition: S32K144.h:563
#define ADC_SC2_ACFE(x)
Definition: S32K144.h:538
__IO uint32_t SC1[ADC_SC1_COUNT]
Definition: S32K144.h:410
#define ADC_UG_UG(x)
Definition: S32K144.h:610
#define ADC_CFG1_ADIV(x)
Definition: S32K144.h:498