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S32 SDK
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FlexTimer Peripheral Driver.
The FTM of the S32K144 is based on a 16 bits counter and supports: input capture, output compare, PWM and some instances include quadrature decoder. The main features are:
•FTM source clock is selectable (Source clock can be the system clock, the fixed frequency clock, or an external clock)
•Prescaler: 1, 2, 4, 8, 16, 32, 64, 128
•16 bit counter (up and up-down counting)
•Each channel can be configured for input capture, output compare, or edge-aligned PWM mode.
•Input Capture mode (single edge, dual edge)
•Output Compare mode (set, cleared or toggle on match)
•All channels can be configured for center-aligned PWM mode.
•Each pair of channels can be combined to generate a PWM signal with independent control of both edges of PWM signal and with dead-time insertion.
•Up to 4 fault inputs for global fault control
•Dual edge capture for pulse and period width measurement
•Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event.
For all operation modes (without Quadrature Decoder mode) the user need to configure ftm_user_config_t. This structure will be used for initialization (FTM_DRV_Init). The next functions used are specific for each operation mode.
For this mode the user needs to configure maximum counter value, number of channels used and output mode for each channel (toggle/clear/set on match). This information is stored in ftm_output_cmp_param_t data type and are used in FTM_DRV_InitOutputCompare. Next step is to set a value for comparison with FTM_DRV_UpdateOutputCompareChannel.
Example:
For this mode the user needs to configure parameters such: number of PWM channels, frequency, dead time, fault channels and duty cycle, alignment (edge or center). All this information is included in ftm_pwm_param_t data type.
FTM_DRV_UpdatePwmChannel can be used to update duty cycles at run time. If the type of update in the duty cycle when the duty cycle can have value between 0x0 (0%) and 0x8000 (100%). If the type of update in ticks when the firstEdge and secondEdge variables can have value between 0 and ftmPeriod which is stored in the state structure.
Example:
For this mode the user needs to configure parameters such: number of PWM channels, frequency, dead time, fault channels and duty cycle, alignment (edge or center). All this information is included in ftm_pwm_param_t data type. The Modified Combine PWM mode is intended to support the generation of PWM signals where the period is not modified while the signal is being generated, but the duty cycle will be varied. FTM_DRV_UpdatePwmChannel can be used to update duty cycles at run time. If the type of update in the duty cycle when the duty cycle can have value between 0x0 (0%) and 0x8000 (100%). If the type of update in ticks when the firstEdge and secondEdge variables can have value between 0 and ftmPeriod which is stored in the state structure.In this mode, an even channel (n) and adjacent odd channel (n+1) are combined to generate a PWM signal in the channel (n) output. Thus, the channel (n) match edge is fixed and the channel (n+1) match edge can be varied.
Example:
For this mode the user needs to configure parameters such: maximum counter value, number of channels, input capture operation mode (for single edge input are used edge detect mode) and edge alignment. All this information is included in ftm_input_param_t.
Example:
FTM_DRV_GetInputCaptureMeasurement is now used in interrupt mode and this function is used to save time stamps in internal buffers.
For this mode the user needs to configure parameters like: counter mode (up-counting or up-down counting), maximum counter value, initial counter value. All this information is included in ftm_timer_param_t.
Example:
For this mode the user needs to configure parameters like: maximum counter value, initial counter value, mode (Count and Direction Encoding mode, Count and Direction Encoding mode), and for both input phases polarity and filtering. All this information is included in ftm_quad_decode_config_t. In this mode the counter is clocked by the phase A and phase B. The current state of the decoder can be obtained using FTM_DRV_QuadGetState.
In count and direction mode if initial value of the PHASE_A is HIGH the counter will be incremented.
Example:
Modules | |
FTM Driver | |
FlexTimer Peripheral Driver. | |
FTM HAL | |
FlexTimer Module Hardware Abstraction Level. FTM HAL provides low level APIs for reading and writing to all hardware features of the FlexTimer module. | |