38 #define SCG_SPLL_MULT_BASE 16U
44 #define SCG_SPLL_PREDIV_BASE 1U
50 #define SCG_SPLL_REF_MIN 8000000U
56 #define SCG_SPLL_REF_MAX 32000000U
59 #if FEATURE_SOC_SCG_COUNT
99 freq /= (regValue + 1U);
107 regValue = base->
CSR;
109 freq /= (regValue + 1U);
112 regValue = base->
CSR;
114 freq /= (regValue + 1U);
136 volatile uint32_t *regAddr = NULL;
137 uint32_t srcFreq = 0U;
145 uint32_t maxFreqRunMode = 0U;
146 const uint32_t sysFreqMul = ((uint32_t)config->
divCore) + 1UL;
147 const uint32_t busFreqMul = (((uint32_t)config->
divCore) + 1UL) * (((uint32_t)config->
divBus) + 1UL);
148 const uint32_t slowFreqMul = (((uint32_t)config->
divCore) + 1UL) * (((uint32_t)config->
divSlow) + 1UL);
176 regAddr = &base->
RCCR;
182 regAddr = &base->
VCCR;
186 regAddr = &base->
VCCR;
197 if ((srcFreq > (sysFreqMul * maxClocksFreq[maxFreqRunMode][
MAX_FREQ_SYS_CLK])) ||
198 (srcFreq > (busFreqMul * maxClocksFreq[maxFreqRunMode][
MAX_FREQ_BUS_CLK])) ||
347 regValue = (uint32_t)base->
SOSCCSR;
350 base->
SOSCCSR = (uint32_t)regValue;
418 uint32_t regValue, retValue, oscFreq, divider = 0U;
445 retValue = (oscFreq >> (divider-1U));
513 regValue = (uint32_t)base->
SIRCCSR;
516 base->
SIRCCSR = (uint32_t)regValue;
584 uint32_t regValue, retValue, sircFreq, divider = 0U;
611 retValue = (sircFreq >> (divider-1U));
693 regValue = (uint32_t)base->
FIRCCSR;
696 base->
FIRCCSR = (uint32_t)regValue;
745 static const uint32_t fircFreq[] = {
754 uint32_t regValue = base->
FIRCCFG;
756 retValue = fircFreq[regValue];
776 uint32_t regValue, retValue, divider = 0U;
801 retValue = (fircFreq >> (divider-1U));
846 uint32_t srcFreq, regValue;
889 regValue = (uint32_t)base->
SPLLCSR;
892 base->
SPLLCSR = (uint32_t)regValue;
933 uint32_t freq, regValue, retValue;
973 uint32_t regValue, retValue, divider = 0U;
998 retValue = (pllFreq >> (divider-1U));
status_t SCG_HAL_InitSirc(SCG_Type *base, const scg_sirc_config_t *config)
Initialize SCG slow IRC clock.
#define SCG_SIRCDIV_SIRCDIV1(x)
void SCG_HAL_GetSystemClockConfig(const SCG_Type *base, scg_system_clock_mode_t mode, scg_system_clock_config_t *config)
Get the system clock configuration for specified mode.
scg_async_clock_div_t div1
scg_async_clock_div_t div2
#define SCG_SPLLCFG_MULT_MASK
#define SCG_SIRCCSR_LK(x)
#define SCG_CSR_DIVBUS_MASK
scg_async_clock_div_t div1
status_t SCG_HAL_InitSysOsc(SCG_Type *base, scg_sosc_config_t const *config)
Initialize SCG system OSC.
#define SCG_SPLLDIV_SPLLDIV2_SHIFT
#define SCG_SPLLCSR_LK_MASK
#define SCG_FIRCCSR_LK_MASK
#define SCG_SPLLCSR_SPLLCM_MASK
#define SCG_SPLLCSR_SPLLVLD_MASK
scg_async_clock_div_t div2
scg_system_clock_mode_t
SCG system clock modes. Implements scg_system_clock_mode_t_Class.
#define SCG_FIRCCSR_FIRCVLD_MASK
scg_system_clock_type_t
SCG system clock type. Implements scg_system_clock_type_t_Class.
status_t SCG_HAL_DeinitFirc(SCG_Type *base)
De-initialize SCG fast IRC.
#define SCG_FIRCCFG_RANGE_SHIFT
#define MAX_FREQ_SLOW_CLK
#define SCG_FIRCCSR_FIRCERR(x)
uint32_t SCG_HAL_GetRtcClkInFreq(SCG_Type *base)
Get SCG RTC CLKIN clock frequency.
void SCG_HAL_SetRtcClkInFreq(SCG_Type *base, uint32_t frequency)
Set SCG RTC CLKIN clock frequency.
#define SCG_SOSCCSR_LK_MASK
status_t SCG_HAL_InitFirc(SCG_Type *base, const scg_firc_config_t *config)
Initialize SCG fast IRC clock.
uint32_t SCG_HAL_GetFircFreq(const SCG_Type *base)
Get SCG FIRC clock frequency.
#define SCG_FIRCCSR_FIRCREGOFF_MASK
#define SCG_SIRCCSR_SIRCLPEN(x)
#define SCG_SOSCDIV_SOSCDIV1_SHIFT
#define SCG_SIRCDIV_SIRCDIV1_SHIFT
#define SCG_SIRCCSR_SIRCSEL_SHIFT
#define CLOCK_MAX_FREQUENCIES
#define SCG_SPLLCFG_PREDIV(x)
#define SCG_FIRCCSR_FIRCVLD_SHIFT
#define SCG_CSR_DIVSLOW_SHIFT
#define SCG_SOSCDIV_SOSCDIV2_MASK
#define MAX_FREQ_VLPR
Maximum frequencies of core, bus and flash clocks. Each entry represents the maximum frequency of SYS...
#define SCG_FIRCDIV_FIRCDIV1_MASK
#define SCG_SIRCCSR_SIRCSEL_MASK
scg_spll_monitor_mode_t monitorMode
scg_async_clock_div_t div2
#define SCG_SPLLDIV_SPLLDIV1_SHIFT
#define SCG_SOSCCFG_HGO(x)
#define SCG_SIRCDIV_SIRCDIV1_MASK
#define SCG_SPLLCSR_LK_SHIFT
#define SCG_SIRCCSR_SIRCVLD_SHIFT
#define SCG_SOSCCFG_EREFS(x)
void SCG_HAL_GetSircDefaultConfig(scg_sirc_config_t *config)
Get the default slow IRC clock configuration.
#define SCG_FIRCDIV_FIRCDIV2_SHIFT
#define SCG_FIRCCFG_RANGE_MASK
static scg_system_clock_src_t SCG_HAL_GetSystemClockSrc(const SCG_Type *base)
Get SCG system clock source.
status_t SCG_HAL_DeinitSirc(SCG_Type *base)
De-initialize SCG slow IRC.
#define SCG_SPLLCSR_LK(x)
#define SCG_FIRCCFG_RANGE(x)
#define FEATURE_SCG_FIRC_FREQ1
#define SCG_SOSCCSR_SOSCERR_MASK
#define SCG_CSR_DIVCORE_SHIFT
scg_sosc_ext_ref_t extRef
#define SCG_CSR_DIVSLOW_MASK
uint32_t SCG_HAL_GetSysOscAsyncFreq(const SCG_Type *base, scg_async_clock_type_t type)
Get SCG asynchronous clock frequency from system OSC.
void SCG_HAL_GetSysPllDefaultConfig(scg_spll_config_t *config)
Get the default system PLL configuration.
#define SCG_SOSCCSR_SOSCSEL_SHIFT
#define SCG_SPLLCSR_SPLLSEL_SHIFT
uint32_t SCG_HAL_GetSircFreq(const SCG_Type *base)
Get SCG SIRC clock frequency.
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
uint32_t SCG_HAL_GetSysOscFreq(const SCG_Type *base)
Get SCG system OSC clock frequency (SYSOSC).
SCG system PLL configuration. Implements scg_spll_config_t_Class.
SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class.
#define SCG_SIRCCSR_SIRCSTEN(x)
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
#define SCG_CSR_DIVCORE_MASK
#define SCG_SOSCCSR_SOSCEN(x)
#define SCG_FIRCCSR_FIRCEN_MASK
#define SCG_SIRCCFG_RANGE(x)
#define FEATURE_SCG_FIRC_FREQ0
#define MAX_FREQ_MODES_NO
status_t SCG_HAL_DeinitSysPll(SCG_Type *base)
De-initialize SCG system PLL.
status_t SCG_HAL_SetSystemClockConfig(SCG_Type *base, scg_system_clock_mode_t mode, scg_system_clock_config_t const *config)
Set the system clock configuration in specified mode.
#define SCG_CSR_SCS_SHIFT
#define SCG_SOSCDIV_SOSCDIV2(x)
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
scg_async_clock_div_t div1
void SCG_HAL_GetFircDefaultConfig(scg_firc_config_t *config)
Get the default fast IRC clock configuration.
SCG system clock configuration. Implements scg_system_clock_config_t_Class.
#define SCG_SPLLDIV_SPLLDIV1(x)
uint32_t SCG_HAL_GetSysPllAsyncFreq(const SCG_Type *base, scg_async_clock_type_t type)
Get SCG asynchronous clock frequency from system PLL.
#define SCG_SOSCCSR_LK_SHIFT
#define SCG_SPLL_MULT_BASE
#define SCG_FIRCDIV_FIRCDIV2(x)
#define FEATURE_SCG_SIRC_LOW_RANGE_FREQ
#define SCG_SIRCCSR_LK_MASK
#define SCG_SOSCCSR_SOSCVLD_MASK
#define SCG_SPLLCSR_SPLLSEL_MASK
#define SCG_SPLLCFG_MULT(x)
#define SCG_SPLLCSR_SPLLERR_MASK
scg_system_clock_div_t divCore
#define SCG_SPLLDIV_SPLLDIV2_MASK
scg_async_clock_div_t div2
#define SCG_SPLLCFG_PREDIV_MASK
scg_system_clock_div_t divSlow
#define SCG_FIRCCSR_FIRCSEL_SHIFT
status_t SCG_HAL_InitSysPll(SCG_Type *base, scg_spll_config_t const *config)
Initialize SCG system PLL.
#define SCG_SOSCCSR_LK(x)
#define SCG_SOSCCSR_SOSCCMRE_MASK
scg_system_clock_src_t
SCG system clock source. Implements scg_system_clock_src_t_Class.
status_t SCG_HAL_DeinitSysOsc(SCG_Type *base)
De-initialize SCG system OSC.
scg_async_clock_type_t
SCG asynchronous clock type. Implements scg_async_clock_type_t_Class.
#define SCG_SIRCDIV_SIRCDIV2_MASK
scg_async_clock_div_t div1
#define SCG_FIRCDIV_FIRCDIV1_SHIFT
#define SCG_SIRCCSR_LK_SHIFT
#define SCG_SOSCDIV_SOSCDIV2_SHIFT
uint32_t SCG_HAL_GetSysPllFreq(const SCG_Type *base)
Get SCG system PLL clock frequency.
#define FEATURE_SCG_FIRC_FREQ2
uint32_t SCG_HAL_GetSircAsyncFreq(const SCG_Type *base, scg_async_clock_type_t type)
Get SCG asynchronous clock frequency from SIRC.
#define SCG_SIRCCFG_RANGE_SHIFT
scg_sosc_monitor_mode_t monitorMode
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
#define SCG_FIRCCSR_FIRCEN(x)
#define SCG_SIRCDIV_SIRCDIV2_SHIFT
#define FEATURE_SCG_FIRC_FREQ3
#define SCG_FIRCCSR_LK_SHIFT
#define SCG_SIRCCSR_SIRCVLD_MASK
#define SCG_SIRCCSR_SIRCEN(x)
#define SCG_SOSCCSR_SOSCVLD_SHIFT
#define SCG_SPLLCSR_SPLLCMRE_MASK
#define SCG_SOSCCSR_SOSCCM_MASK
#define SCG_SOSCDIV_SOSCDIV1_MASK
#define SCG_SPLLDIV_SPLLDIV1_MASK
scg_system_clock_div_t
SCG system clock divider value. Implements scg_system_clock_div_t_Class.
#define SCG_FIRCCSR_FIRCERR_SHIFT
#define SCG_SPLLCFG_MULT_SHIFT
void SCG_HAL_GetSysOscDefaultConfig(scg_sosc_config_t *config)
Get the default system OSC configuration.
#define SCG_SPLLCFG_PREDIV_SHIFT
#define SCG_FIRCCSR_FIRCSEL_MASK
scg_system_clock_src_t src
#define SCG_FIRCDIV_FIRCDIV2_MASK
#define SCG_FIRCCSR_FIRCERR_MASK
#define SCG_FIRCCSR_LK(x)
#define SCG_FIRCDIV_FIRCDIV1(x)
uint32_t SCG_HAL_GetFircAsyncFreq(const SCG_Type *base, scg_async_clock_type_t type)
Get SCG asynchronous clock frequency from FIRC.
#define SCG_SIRCCSR_SIRCEN_MASK
#define SCG_CSR_DIVBUS_SHIFT
#define SCG_SIRCCFG_RANGE_MASK
#define SCG_SOSCCFG_RANGE(x)
#define SCG_SOSCCSR_SOSCSEL_MASK
#define SCG_SOSCDIV_SOSCDIV1(x)
uint32_t SCG_HAL_GetSystemClockFreq(const SCG_Type *base, scg_system_clock_type_t type)
Get SCG system clock frequency.
#define SCG_SPLLCSR_SPLLVLD_SHIFT
#define SCG_SPLLDIV_SPLLDIV2(x)
#define SCG_SPLL_PREDIV_BASE
#define SCG_FIRCCSR_FIRCREGOFF(x)
#define SCG_SPLLCSR_SPLLEN(x)
scg_system_clock_div_t divBus
#define SCG_SIRCDIV_SIRCDIV2(x)