S32 SDK
port_hal.h
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 #ifndef PORT_HAL_H
19 #define PORT_HAL_H
20 
21 #include "device_registers.h"
22 #include <stdbool.h>
23 
56 /*******************************************************************************
57  * Definitions
58  ******************************************************************************/
59 #if FEATURE_PORT_HAS_PULL_SELECTION
60 
64 typedef enum {
69 #endif
70 
71 #if FEATURE_PORT_HAS_SLEW_RATE
72 
76 typedef enum {
77  PORT_FAST_SLEW_RATE = 0U,
78  PORT_SLOW_SLEW_RATE = 1U
79 } port_slew_rate_t;
80 #endif
81 
82 #if FEATURE_PORT_HAS_DRIVE_STRENGTH
83 
87 typedef enum {
91 #endif
92 
97 typedef enum {
106 } port_mux_t;
107 
108 #if FEATURE_PORT_HAS_DIGITAL_FILTER
109 
113 typedef enum {
117 #endif
118 
123 typedef enum {
125  #if FEATURE_PORT_HAS_DMA_REQUEST
129  #endif
136 
137 /*******************************************************************************
138  * API
139  ******************************************************************************/
140 
141 #if defined(__cplusplus)
142 extern "C" {
143 #endif
144 
150 #if FEATURE_PORT_HAS_PULL_SELECTION
151 
164 static inline void PORT_HAL_SetPullSel(PORT_Type* const base,
165  const uint32_t pin,
166  const port_pull_config_t pullConfig)
167 {
168  DEV_ASSERT(pin < PORT_PCR_COUNT);
169  switch(pullConfig)
170  {
172  {
173  base->PCR[pin] &= ~(PORT_PCR_PE_MASK);
174  }
175  break;
177  {
178  uint32_t regValue = base->PCR[pin];
179  regValue &= ~(PORT_PCR_PS_MASK);
180  regValue |= PORT_PCR_PE(1U);
181  base->PCR[pin] = regValue;
182  }
183  break;
185  {
186  uint32_t regValue = base->PCR[pin];
187  regValue |= PORT_PCR_PE(1U);
188  regValue |= PORT_PCR_PS(1U);
189  base->PCR[pin] = regValue;
190  }
191  break;
192  default:
193  /* invalid command */
194  DEV_ASSERT(false);
195  break;
196  }
197 }
198 #endif
199 
200 #if FEATURE_PORT_HAS_SLEW_RATE
201 
210 static inline void PORT_HAL_SetSlewRateMode(PORT_Type* const base,
211  const uint32_t pin,
212  const port_slew_rate_t rateSelect)
213 {
214  DEV_ASSERT(pin < PORT_PCR_COUNT);
215  /* Rate select value */
216  uint32_t rateSelectValue = (uint32_t)rateSelect;
217  uint32_t regValue = base->PCR[pin];
218  regValue &= ~(PORT_PCR_SRE_MASK);
219  regValue |= PORT_PCR_SRE(rateSelectValue);
220  base->PCR[pin] = regValue;
221 }
222 #endif
223 
224 #if FEATURE_PORT_HAS_PASSIVE_FILTER
225 
239 static inline void PORT_HAL_SetPassiveFilterMode(PORT_Type* const base,
240  const uint32_t pin,
241  const bool isPassiveFilterEnabled)
242 {
243  DEV_ASSERT(pin < PORT_PCR_COUNT);
244  uint32_t regValue = base->PCR[pin];
245  regValue &= ~(PORT_PCR_PFE_MASK);
246  regValue |= PORT_PCR_PFE(isPassiveFilterEnabled);
247  base->PCR[pin] = regValue;
248 }
249 #endif
250 
251 #if FEATURE_PORT_HAS_OPEN_DRAIN
252 
261 static inline void PORT_HAL_SetOpenDrainMode(PORT_Type* const base,
262  const uint32_t pin,
263  const bool isOpenDrainEnabled)
264 {
265  DEV_ASSERT(pin < PORT_PCR_COUNT);
266  uint32_t regValue = base->PCR[pin];
267  regValue &= ~(PORT_PCR_ODE_MASK);
268  regValue |= PORT_PCR_ODE(isOpenDrainEnabled);
269  base->PCR[pin] = regValue;
270 }
271 #endif
272 
273 #if FEATURE_PORT_HAS_DRIVE_STRENGTH
274 
284 static inline void PORT_HAL_SetDriveStrengthMode(PORT_Type* const base,
285  const uint32_t pin,
286  const port_drive_strength_t driveSelect)
287 {
288  DEV_ASSERT(pin < PORT_PCR_COUNT);
289  /* Drive select value */
290  uint32_t driveSelectValue = (uint32_t)driveSelect;
291  uint32_t regValue = base->PCR[pin];
292  regValue &= ~(PORT_PCR_DSE_MASK);
293  regValue |= PORT_PCR_DSE(driveSelectValue);
294  base->PCR[pin] = regValue;
295 }
296 #endif
297 
309 static inline void PORT_HAL_SetMuxModeSel(PORT_Type* const base,
310  const uint32_t pin,
311  const port_mux_t mux)
312 {
313  DEV_ASSERT(pin < PORT_PCR_COUNT);
314  uint32_t regValue = base->PCR[pin];
315  regValue &= ~(PORT_PCR_MUX_MASK);
316  regValue |= PORT_PCR_MUX(mux);
317  base->PCR[pin] = regValue;
318 }
319 
320 #if FEATURE_PORT_HAS_PIN_CONTROL_LOCK
321 
331 static inline void PORT_HAL_SetPinCtrlLockMode(PORT_Type* const base,
332  const uint32_t pin,
333  const bool isPinLockEnabled)
334 {
335  DEV_ASSERT(pin < PORT_PCR_COUNT);
336  uint32_t regValue = base->PCR[pin];
337  regValue &= ~(PORT_PCR_LK_MASK);
338  regValue |= PORT_PCR_LK(isPinLockEnabled);
339  base->PCR[pin] = regValue;
340 }
341 #endif
342 
343 #if FEATURE_PORT_HAS_DIGITAL_FILTER
344 
355 static inline void PORT_HAL_SetDigitalFilterMode(PORT_Type* const base,
356  const uint32_t pin,
357  const bool isDigitalFilterEnabled)
358 {
359  DEV_ASSERT(pin < PORT_PCR_COUNT);
360  /* Digital filter value */
361  uint32_t digitalFilterValue = (isDigitalFilterEnabled == true) ? 1UL : 0UL;
362  uint32_t regValue = base->DFER;
363  regValue &= ~(1U << pin);
364  regValue |= (digitalFilterValue << pin);
365  base->DFER = regValue;
366 }
367 
379 static inline void PORT_HAL_SetDigitalFilterClock(PORT_Type* const base,
380  const port_digital_filter_clock_source_t clockSource)
381 {
382  base->DFCR = (uint32_t)clockSource;
383 }
384 
396 static inline void PORT_HAL_SetDigitalFilterWidth(PORT_Type* const base, const uint8_t width)
397 {
398  base->DFWR = width;
399 }
400 #endif /* FEATURE_PORT_HAS_DIGITAL_FILTER*/
401 
412 void PORT_HAL_SetLowGlobalPinCtrlCmd(PORT_Type* const base, const uint16_t lowPinSelect, const uint16_t config);
413 
424 void PORT_HAL_SetHighGlobalPinCtrlCmd(PORT_Type* const base, const uint16_t highPinSelect, const uint16_t config);
425 
450 static inline void PORT_HAL_SetPinIntSel(PORT_Type* const base,
451  const uint32_t pin,
453 {
454  DEV_ASSERT(pin < PORT_PCR_COUNT);
455  uint32_t regValue = base->PCR[pin];
456  regValue &= ~(PORT_PCR_IRQC_MASK);
457  regValue |= PORT_PCR_IRQC(intConfig);
458  base->PCR[pin] = regValue;
459 }
460 
478 static inline port_interrupt_config_t PORT_HAL_GetPinIntSel(const PORT_Type* const base, const uint32_t pin)
479 {
480  DEV_ASSERT(pin < PORT_PCR_COUNT);
481  uint32_t regValue = base->PCR[pin];
482  regValue = (regValue & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT;
483  return (port_interrupt_config_t)regValue;
484 }
485 
502 static inline bool PORT_HAL_GetPinIntMode(const PORT_Type* const base, const uint32_t pin)
503 {
504  DEV_ASSERT(pin < PORT_PCR_COUNT);
505  uint32_t regValue = base->PCR[pin];
506  regValue = (regValue & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT;
507  return (bool)regValue;
508 }
509 
517 static inline void PORT_HAL_ClearPinIntFlagCmd(PORT_Type* const base, const uint32_t pin)
518 {
519  DEV_ASSERT(pin < PORT_PCR_COUNT);
520  uint32_t regValue = base->PCR[pin];
521  regValue &= ~(PORT_PCR_ISF_MASK);
522  regValue |= PORT_PCR_ISF(1U);
523  base->PCR[pin] = regValue;
524 }
525 
535 static inline uint32_t PORT_HAL_GetPortIntFlag(const PORT_Type* const base)
536 {
537  uint32_t regValue = base->ISFR;
538  return regValue;
539 }
540 
547 static inline void PORT_HAL_ClearPortIntFlagCmd(PORT_Type* const base)
548 {
549  base->ISFR = ~0U;
550 }
551 
554 #if defined(__cplusplus)
555 }
556 #endif
557 
560 #endif /* PORT_HAL_H*/
561 /*******************************************************************************
562  * EOF
563  ******************************************************************************/
564 
__IO uint32_t DFCR
Definition: S32K144.h:8557
rtc_interrupt_config_t * intConfig
Definition: rtc_driver.c:78
static void PORT_HAL_SetDigitalFilterClock(PORT_Type *const base, const port_digital_filter_clock_source_t clockSource)
Configures the clock source for the digital input filters. Changing the filter clock source should on...
Definition: port_hal.h:379
#define PORT_PCR_COUNT
Definition: S32K144.h:8546
static port_interrupt_config_t PORT_HAL_GetPinIntSel(const PORT_Type *const base, const uint32_t pin)
Gets the current port pin interrupt/DMA request configuration.
Definition: port_hal.h:478
__IO uint32_t DFER
Definition: S32K144.h:8556
#define PORT_PCR_PE(x)
Definition: S32K144.h:8614
#define PORT_PCR_PFE_MASK
Definition: S32K144.h:8615
#define PORT_PCR_PS_MASK
Definition: S32K144.h:8607
static void PORT_HAL_SetPassiveFilterMode(PORT_Type *const base, const uint32_t pin, const bool isPassiveFilterEnabled)
Configures the passive filter if the pin is used as a digital input.
Definition: port_hal.h:239
#define PORT_PCR_LK(x)
Definition: S32K144.h:8630
static void PORT_HAL_SetDriveStrengthMode(PORT_Type *const base, const uint32_t pin, const port_drive_strength_t driveSelect)
Configures the drive strength if the pin is used as a digital output.
Definition: port_hal.h:284
static bool PORT_HAL_GetPinIntMode(const PORT_Type *const base, const uint32_t pin)
Reads the individual pin-interrupt status flag.
Definition: port_hal.h:502
static void PORT_HAL_SetDigitalFilterWidth(PORT_Type *const base, const uint8_t width)
Configures the maximum size of the glitches (in clock cycles) that the digital filter absorbs for ena...
Definition: port_hal.h:396
#define PORT_PCR_IRQC_MASK
Definition: S32K144.h:8631
#define PORT_PCR_LK_MASK
Definition: S32K144.h:8627
void PORT_HAL_SetHighGlobalPinCtrlCmd(PORT_Type *const base, const uint16_t highPinSelect, const uint16_t config)
Configures the high half of pin control register for the same settings. This function operates pin 16...
#define PORT_PCR_PE_MASK
Definition: S32K144.h:8611
#define DEV_ASSERT(x)
Definition: devassert.h:78
__IO uint32_t ISFR
Definition: S32K144.h:8554
static void PORT_HAL_ClearPortIntFlagCmd(PORT_Type *const base)
Clears the entire port interrupt status flag.
Definition: port_hal.h:547
#define PORT_PCR_IRQC(x)
Definition: S32K144.h:8634
#define PORT_PCR_DSE_MASK
Definition: S32K144.h:8619
static void PORT_HAL_ClearPinIntFlagCmd(PORT_Type *const base, const uint32_t pin)
Clears the individual pin-interrupt status flag.
Definition: port_hal.h:517
__IO uint32_t DFWR
Definition: S32K144.h:8558
port_pull_config_t
Internal resistor pull feature selection Implements : port_pull_config_t_Class.
Definition: port_hal.h:64
port_interrupt_config_t
Configures the interrupt generation condition. Implements : port_interrupt_config_t_Class.
Definition: port_hal.h:123
#define PORT_PCR_MUX(x)
Definition: S32K144.h:8626
#define PORT_PCR_IRQC_SHIFT
Definition: S32K144.h:8632
static void PORT_HAL_SetPinCtrlLockMode(PORT_Type *const base, const uint32_t pin, const bool isPinLockEnabled)
Locks or unlocks the pin control register bits[15:0].
Definition: port_hal.h:331
port_drive_strength_t
Configures the drive strength. Implements : port_drive_strength_t_Class.
Definition: port_hal.h:87
#define PORT_PCR_PFE(x)
Definition: S32K144.h:8618
#define PORT_PCR_ISF_MASK
Definition: S32K144.h:8635
static void PORT_HAL_SetMuxModeSel(PORT_Type *const base, const uint32_t pin, const port_mux_t mux)
Configures the pin muxing.
Definition: port_hal.h:309
void PORT_HAL_SetLowGlobalPinCtrlCmd(PORT_Type *const base, const uint16_t lowPinSelect, const uint16_t config)
Configures the low half of the pin control register for the same settings. This function operates pin...
#define PORT_PCR_PS(x)
Definition: S32K144.h:8610
#define PORT_PCR_MUX_MASK
Definition: S32K144.h:8623
port_digital_filter_clock_source_t
Digital filter clock source selection Implements : port_digital_filter_clock_source_t_Class.
Definition: port_hal.h:113
__IO uint32_t PCR[PORT_PCR_COUNT]
Definition: S32K144.h:8550
#define PORT_PCR_ISF(x)
Definition: S32K144.h:8638
#define PORT_PCR_ISF_SHIFT
Definition: S32K144.h:8636
static void PORT_HAL_SetPinIntSel(PORT_Type *const base, const uint32_t pin, const port_interrupt_config_t intConfig)
Configures the port pin interrupt/DMA request.
Definition: port_hal.h:450
port_mux_t
Pin mux selection Implements : port_mux_t_Class.
Definition: port_hal.h:97
static void PORT_HAL_SetPullSel(PORT_Type *const base, const uint32_t pin, const port_pull_config_t pullConfig)
Configures the internal resistor.
Definition: port_hal.h:164
static uint32_t PORT_HAL_GetPortIntFlag(const PORT_Type *const base)
Reads the entire port interrupt status flag.
Definition: port_hal.h:535
static void PORT_HAL_SetDigitalFilterMode(PORT_Type *const base, const uint32_t pin, const bool isDigitalFilterEnabled)
Enables or disables the digital filter in one single port. Each bit of the 32-bit register represents...
Definition: port_hal.h:355
#define PORT_PCR_DSE(x)
Definition: S32K144.h:8622