S32 SDK
eim_hal.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
23 #ifndef EIM_HAL_H
24 #define EIM_HAL_H
25 
26 #include <stdbool.h>
27 #include "device_registers.h"
28 
39 /*******************************************************************************
40  * Definitions
41  *****************************************************************************/
42 
44 #define POS_MSB_EIM_EICHEN (31U)
45 
46 /*******************************************************************************
47  * API
48  ******************************************************************************/
54 #if defined(__cplusplus)
55 extern "C" {
56 #endif
57 
66 void EIM_HAL_Init(EIM_Type * const base);
67 
76 static inline void EIM_HAL_Enable(EIM_Type * const base)
77 {
78  base->EIMCR |= EIM_EIMCR_GEIEN_MASK;
79 }
80 
89 static inline void EIM_HAL_Disable(EIM_Type * const base)
90 {
91  base->EIMCR &= ~EIM_EIMCR_GEIEN_MASK;
92 }
93 
106 static inline void EIM_HAL_EnableChannelCmd(EIM_Type * const base,
107  uint8_t channel,
108  bool enable)
109 {
110  uint32_t temp;
111 
112  DEV_ASSERT(channel < EIM_EICHDn_COUNT);
113 
114  temp = base->EICHEN;
115  temp &= ~(1UL << (POS_MSB_EIM_EICHEN - channel));
116  temp |= (enable ? 1UL : 0UL) << (POS_MSB_EIM_EICHEN - channel);
117  base->EICHEN = temp;
118 }
119 
132 static inline bool EIM_HAL_IsChannelEnabled(const EIM_Type * const base,
133  uint8_t channel)
134 {
135  DEV_ASSERT(channel < EIM_EICHDn_COUNT);
136 
137  return ((base->EICHEN & (1UL << (POS_MSB_EIM_EICHEN - channel))) != 0UL);
138 }
139 
150 static inline void EIM_HAL_SetCheckBitMask(EIM_Type * const base,
151  uint8_t channel,
152  uint8_t checkBitMask)
153 {
154  DEV_ASSERT(channel < EIM_EICHDn_COUNT);
155  DEV_ASSERT(checkBitMask < (1U << EIM_EICHDn_WORD0_CHKBIT_MASK_WIDTH));
156 
157  base->EICHDn[channel].WORD0 = EIM_EICHDn_WORD0_CHKBIT_MASK(checkBitMask);
158 }
159 
170 static inline uint8_t EIM_HAL_GetCheckBitMask(const EIM_Type * const base,
171  uint8_t channel)
172 {
173  DEV_ASSERT(channel < EIM_EICHDn_COUNT);
174 
175  return ((uint8_t)((base->EICHDn[channel].WORD0) >> EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT));
176 }
177 
178 
189 static inline void EIM_HAL_SetDataMask(EIM_Type * const base,
190  uint8_t channel,
191  uint32_t dataMask)
192 {
193  DEV_ASSERT(channel < EIM_EICHDn_COUNT);
194 
195  base->EICHDn[channel].WORD1 = dataMask;
196 }
197 
208 static inline uint32_t EIM_HAL_GetDataMask(const EIM_Type * const base,
209  uint8_t channel)
210 {
211  DEV_ASSERT(channel < EIM_EICHDn_COUNT);
212 
213  return (base->EICHDn[channel].WORD1);
214 }
215 
218 #if defined(__cplusplus)
219 }
220 #endif
221 
224 #endif /* EIM_HAL_H */
225 /*******************************************************************************
226  * EOF
227  *******************************************************************************/
__IO uint32_t WORD1
Definition: S32K144.h:3181
__IO uint32_t EIMCR
Definition: S32K144.h:3176
#define EIM_EICHDn_COUNT
Definition: S32K144.h:3172
#define EIM_EICHDn_WORD0_CHKBIT_MASK_WIDTH
Definition: S32K144.h:3226
static uint32_t EIM_HAL_GetDataMask(const EIM_Type *const base, uint8_t channel)
Gets data mask of EIM channel.
Definition: eim_hal.h:208
static void EIM_HAL_Disable(EIM_Type *const base)
Disables the EIM module.
Definition: eim_hal.h:89
struct EIM_Type::@10 EICHDn[EIM_EICHDn_COUNT]
static void EIM_HAL_SetDataMask(EIM_Type *const base, uint8_t channel, uint32_t dataMask)
Sets data mask for EIM channel.
Definition: eim_hal.h:189
#define EIM_EIMCR_GEIEN_MASK
Definition: S32K144.h:3210
#define DEV_ASSERT(x)
Definition: devassert.h:78
void EIM_HAL_Init(EIM_Type *const base)
Resets for the registers of EIM descriptor.
Definition: eim_hal.c:43
static void EIM_HAL_Enable(EIM_Type *const base)
Enables EIM module.
Definition: eim_hal.h:76
__IO uint32_t EICHEN
Definition: S32K144.h:3177
static uint8_t EIM_HAL_GetCheckBitMask(const EIM_Type *const base, uint8_t channel)
Gets check bit mask of EIM channel.
Definition: eim_hal.h:170
#define EIM_EICHDn_WORD0_CHKBIT_MASK(x)
Definition: S32K144.h:3227
static void EIM_HAL_EnableChannelCmd(EIM_Type *const base, uint8_t channel, bool enable)
Enables or disables EIM channel operation.
Definition: eim_hal.h:106
static bool EIM_HAL_IsChannelEnabled(const EIM_Type *const base, uint8_t channel)
Checks whether EIM channel is enabled.
Definition: eim_hal.h:132
#define POS_MSB_EIM_EICHEN
The position of the most significant bit in Error Injection Channel Enable register.
Definition: eim_hal.h:44
static void EIM_HAL_SetCheckBitMask(EIM_Type *const base, uint8_t channel, uint8_t checkBitMask)
Sets check bit mask for EIM channel.
Definition: eim_hal.h:150
#define EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT
Definition: S32K144.h:3225
__IO uint32_t WORD0
Definition: S32K144.h:3180