92 #define DIVIDER_MAX_VALUE 0xFFU
96 #define TX_SHIFTER(x) (x)
97 #define RX_SHIFTER(x) (x)
98 #define TX_TIMER(x) (x)
99 #define RX_TIMER(x) (x)
121 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 1U;
123 if (tmpDiv > DIVIDER_MAX_VALUE)
125 tmpDiv = DIVIDER_MAX_VALUE;
128 *divider = (uint16_t)tmpDiv;
145 uint8_t resourceIndex;
148 resourceIndex = state->flexioCommon.resourceIndex;
151 FLEXIO_UART_DRV_ComputeBaudRateDivider(state, userConfigPtr->
baudRate, ÷r, inputClock);
156 TX_SHIFTER(resourceIndex),
161 TX_SHIFTER(resourceIndex),
166 TX_TIMER(resourceIndex),
172 TX_TIMER(resourceIndex),
181 TX_TIMER(resourceIndex),
182 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
208 uint8_t resourceIndex;
211 resourceIndex = state->flexioCommon.resourceIndex;
214 FLEXIO_UART_DRV_ComputeBaudRateDivider(state, userConfigPtr->
baudRate, ÷r, inputClock);
219 RX_SHIFTER(resourceIndex),
224 RX_SHIFTER(resourceIndex),
229 RX_TIMER(resourceIndex),
235 RX_TIMER(resourceIndex),
244 RX_TIMER(resourceIndex),
264 uint8_t resourceIndex;
267 resourceIndex = state->flexioCommon.resourceIndex;
270 switch (state->driverType)
295 state->driverIdle =
true;
297 if (state->blocking ==
true)
313 uint8_t resourceIndex;
315 resourceIndex = state->flexioCommon.resourceIndex;
344 uint8_t resourceIndex;
346 resourceIndex = state->flexioCommon.resourceIndex;
357 FLEXIO_UART_DRV_EndTransfer(state);
371 switch (state->driverType)
391 state->blocking =
false;
396 FLEXIO_UART_DRV_StopTransfer(state);
399 return state->status;
413 uint8_t resourceIndex;
419 resourceIndex = state->flexioCommon.resourceIndex;
423 data >>= 32U - (uint32_t)(state->bitCount);
425 if (state->bitCount <= 8U)
427 *(uint8_t *)state->data = (uint8_t)data;
430 state->remainingBytes -= 1U;
435 *(uint16_t *)state->data = (uint16_t)data;
437 state->data = &state->data[2U];
438 state->remainingBytes -= 2U;
453 uint8_t resourceIndex;
458 resourceIndex = state->flexioCommon.resourceIndex;
460 if (state->remainingBytes == 0U)
466 if (state->bitCount <= 8U)
468 data = (uint32_t)(*(uint8_t *)state->data);
470 state->remainingBytes -= 1U;
475 data = (uint32_t)(*(uint16_t *)state->data);
476 state->data = &state->data[2U];
477 state->remainingBytes -= 2U;
492 static void FLEXIO_UART_DRV_CheckStatusTx(
void *stateStruct)
495 uint8_t resourceIndex;
502 resourceIndex = state->flexioCommon.resourceIndex;
506 if (state->remainingBytes == 0U)
513 if (state->txFlush == 0U)
521 FLEXIO_UART_DRV_StopTransfer(state);
523 if (state->callback != NULL)
547 FLEXIO_UART_DRV_WriteData(state);
548 if (state->remainingBytes == 0U)
551 if (state->callback != NULL)
556 if (state->remainingBytes == 0U)
586 static void FLEXIO_UART_DRV_CheckStatusRx(
void *stateStruct)
589 uint8_t resourceIndex;
596 resourceIndex = state->flexioCommon.resourceIndex;
603 state->remainingBytes = 0U;
609 FLEXIO_UART_DRV_ReadData(state);
610 if (state->remainingBytes == 0U)
613 if (state->callback != NULL)
624 if (state->remainingBytes == 0U)
634 FLEXIO_UART_DRV_StopTransfer(state);
636 if (state->callback != NULL)
651 static void FLEXIO_UART_DRV_CheckStatus(
void *stateStruct)
660 FLEXIO_UART_DRV_CheckStatusTx(stateStruct);
664 FLEXIO_UART_DRV_CheckStatusRx(stateStruct);
675 static void FLEXIO_UART_DRV_EndDmaTxTransfer(
void *stateStruct,
edma_chn_status_t status)
690 if (state->callback != NULL)
694 if (state->remainingBytes == 0U)
705 dmaChn = state->dmaChannel;
707 if (state->bitCount <= 8U)
718 state->remainingBytes = 0U;
731 static void FLEXIO_UART_DRV_EndDmaRxTransfer(
void *stateStruct,
edma_chn_status_t status)
744 if (state->callback != NULL)
748 if (state->remainingBytes == 0U)
752 FLEXIO_UART_DRV_StopTransfer(state);
754 if (state->callback != NULL)
763 dmaChn = state->dmaChannel;
765 if (state->bitCount <= 8U)
776 state->remainingBytes = 0U;
797 shifter = TX_SHIFTER(state->flexioCommon.resourceIndex);
798 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter]));
816 if (state->bitCount <= 8U)
825 shifter = RX_SHIFTER(state->flexioCommon.resourceIndex);
826 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter])) + (
sizeof(uint32_t) - byteCount);
839 uint8_t resourceIndex;
846 resourceIndex = state->flexioCommon.resourceIndex;
849 if (state->bitCount <= 8U)
861 (uint32_t)(state->data),
862 FLEXIO_UART_DRV_ComputeTxRegAddr(state),
868 state->remainingBytes = 0U;
890 uint8_t resourceIndex;
897 resourceIndex = state->flexioCommon.resourceIndex;
900 if (state->bitCount <= 8U)
912 FLEXIO_UART_DRV_ComputeRxRegAddr(state),
913 (uint32_t)(state->data),
919 state->remainingBytes = 0U;
967 state->flexioCommon.resourceCount = 1U;
983 state->remainingBytes = 0U;
984 state->callback = userConfigPtr->
callback;
986 state->blocking =
false;
987 state->driverType = userConfigPtr->
driverType;
988 state->direction = userConfigPtr->
direction;
990 state->driverIdle =
true;
991 state->bitCount = userConfigPtr->
bitCount;
996 FLEXIO_UART_DRV_ConfigureTx(state, userConfigPtr, inputClock);
1001 FLEXIO_UART_DRV_ConfigureRx(state, userConfigPtr, inputClock);
1005 switch (state->driverType)
1010 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusTx;
1014 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusRx;
1022 state->dmaChannel = userConfigPtr->
dmaChannel;
1024 dmaReq =
g_flexioDMASrc[instance][TX_SHIFTER(state->flexioCommon.resourceIndex)];
1029 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusTx;
1080 uint32_t inputClock;
1082 uint8_t resourceIndex;
1092 resourceIndex = state->flexioCommon.resourceIndex;
1102 FLEXIO_UART_DRV_ComputeBaudRateDivider(state, baudRate, ÷r, inputClock);
1107 FLEXIO_HAL_SetTimerCompare(baseAddr, TX_TIMER(resourceIndex), (uint16_t)(((((uint16_t)bitCount << 1U) - 1U) << 8U) + divider));
1112 FLEXIO_HAL_SetTimerCompare(baseAddr, RX_TIMER(resourceIndex), (uint16_t)(((((uint16_t)bitCount << 1U) - 1U) << 8U) + divider));
1115 state->bitCount = bitCount;
1132 uint32_t inputClock;
1136 uint8_t resourceIndex;
1141 resourceIndex = state->flexioCommon.resourceIndex;
1150 divider = (uint16_t)(timerCmp & 0x00FFU);
1153 *baudRate = (inputClock + (uint32_t)divider + 1U) / (2U * ((uint32_t)divider + 1U));
1169 const uint8_t * txBuff,
1173 uint8_t resourceIndex;
1181 resourceIndex = state->flexioCommon.resourceIndex;
1186 state->data = (uint8_t *)txBuff;
1187 state->remainingBytes = txSize;
1189 state->driverIdle =
false;
1191 state->txFlush = (uint8_t)((txSize == 1U) ? 1U : 2U);
1194 FLEXIO_UART_DRV_EnableTransfer(state);
1196 switch (state->driverType)
1205 FLEXIO_UART_DRV_CheckStatus(state);
1208 FLEXIO_UART_DRV_StartTxDmaTransfer(state);
1227 const uint8_t * txBuff,
1236 state->blocking =
true;
1243 state->blocking =
false;
1248 return FLEXIO_UART_DRV_WaitTransferEnd(state, timeout);
1264 uint8_t resourceIndex;
1272 resourceIndex = state->flexioCommon.resourceIndex;
1277 state->data = rxBuff;
1278 state->remainingBytes = rxSize;
1280 state->driverIdle =
false;
1283 FLEXIO_UART_DRV_EnableTransfer(state);
1285 switch (state->driverType)
1294 FLEXIO_UART_DRV_CheckStatus(state);
1297 FLEXIO_UART_DRV_StartRxDmaTransfer(state);
1325 state->blocking =
true;
1332 state->blocking =
false;
1337 return FLEXIO_UART_DRV_WaitTransferEnd(state, timeout);
1353 FLEXIO_UART_DRV_StopTransfer(state);
1373 FLEXIO_UART_DRV_CheckStatus(state);
1376 if (bytesRemaining != NULL)
1378 *bytesRemaining = state->remainingBytes;
1381 if (!state->driverIdle)
1387 return state->status;
1407 state->data = rxBuff;
1408 state->remainingBytes = rxSize;
1422 const uint8_t * txBuff,
1429 state->data = (uint8_t *)txBuff;
1430 state->remainingBytes = txSize;
static void EDMA_HAL_TCDSetSrcAddr(DMA_Type *base, uint32_t channel, uint32_t address)
Configures the source address for the hardware TCD.
__IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT]
static void FLEXIO_HAL_SetShifterInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the shifter interrupts.
static void FLEXIO_HAL_SetShifterMode(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_mode_t mode)
Sets the mode of the specified shifter.
static uint16_t FLEXIO_HAL_GetTimerCompare(const FLEXIO_Type *baseAddr, uint8_t timer)
Returns the compare value of the specified timer.
DMAMUX_Type *const g_dmamuxBase[DMAMUX_INSTANCE_COUNT]
Array for DMAMUX module register base address.
static void FLEXIO_HAL_SetTimerControl(FLEXIO_Type *baseAddr, uint8_t timer, uint8_t trigger, flexio_trigger_polarity_t triggerPolarity, flexio_trigger_source_t triggerSource, uint8_t pin, flexio_pin_polarity_t pinPolarity, flexio_pin_config_t pinConfig, flexio_timer_mode_t mode)
Sets all control settings for specified timer.
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
static bool FLEXIO_HAL_GetTimerStatus(const FLEXIO_Type *baseAddr, uint8_t timer)
Returns the current status of the specified timer.
static void FLEXIO_HAL_SetTimerMode(FLEXIO_Type *baseAddr, uint8_t timer, flexio_timer_mode_t mode)
Sets the mode of the specified timer.
status_t FLEXIO_UART_DRV_ReceiveData(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking UART reception.
FLEXIO_Type *const g_flexioBase[FLEXIO_INSTANCE_COUNT]
status_t FLEXIO_UART_DRV_SetTxBuffer(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
#define FLEXIO_INSTANCE_COUNT
void EDMA_HAL_TCDSetMajorCount(DMA_Type *base, uint32_t channel, uint32_t count)
Sets the major iteration count according to minor loop channel link setting.
static void FLEXIO_HAL_WriteShifterBuffer(FLEXIO_Type *baseAddr, uint8_t shifter, uint32_t value, flexio_shifter_buffer_mode_t mode)
Writes a value in the specified shifter buffer.
static void FLEXIO_HAL_SetShifterStartBit(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_start_t start)
Configures the start bit of the specified shifter.
static void FLEXIO_HAL_ClearTimerStatus(FLEXIO_Type *baseAddr, uint8_t timer)
Clears the status of the specified timer.
status_t FLEXIO_UART_DRV_SetConfig(flexio_uart_state_t *state, uint32_t baudRate, uint8_t bitCount)
Set the baud rate and bit width for any subsequent UART communication.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
static void FLEXIO_HAL_SetTimerInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the timer interrupts.
static void FLEXIO_HAL_SetShifterConfig(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_start_t start, flexio_shifter_stop_t stop, flexio_shifter_source_t source)
Sets all configuration settings for specified shifter.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
flexio_callback_t callback
static uint32_t FLEXIO_HAL_ReadShifterBuffer(const FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_buffer_mode_t mode)
Reads the value from the specified shifter buffer.
status_t FLEXIO_UART_DRV_SendData(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking UART transmission.
status_t FLEXIO_UART_DRV_SendDataBlocking(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking UART transmission.
edma_chn_status_t
Channel status for eDMA channel.
static void EDMA_HAL_TCDSetDestAddr(DMA_Type *base, uint32_t channel, uint32_t address)
Configures the destination address for the TCD.
flexio_uart_driver_direction_t direction
status_t FLEXIO_UART_DRV_ReceiveDataBlocking(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking UART reception.
status_t FLEXIO_UART_DRV_GetBaudRate(flexio_uart_state_t *state, uint32_t *baudRate)
Get the currently configured baud rate.
static void FLEXIO_HAL_SetShifterControl(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_mode_t mode, uint8_t pin, flexio_pin_polarity_t pinPolarity, flexio_pin_config_t pinConfig, uint8_t timer, flexio_timer_polarity_t timerPolarity)
Sets all control settings for the specified shifter.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
status_t FLEXIO_UART_DRV_GetStatus(flexio_uart_state_t *state, uint32_t *bytesRemaining)
Get the status of the current non-blocking UART transfer.
status_t FLEXIO_UART_DRV_SetRxBuffer(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
const uint8_t g_flexioDMASrc[FLEXIO_INSTANCE_COUNT][FEATURE_FLEXIO_MAX_SHIFTER_COUNT]
Driver internal context structure.
status_t FLEXIO_UART_DRV_Deinit(flexio_uart_state_t *state)
De-initialize the FLEXIO_UART driver.
static void FLEXIO_HAL_SetTimerCompare(FLEXIO_Type *baseAddr, uint8_t timer, uint16_t value)
Configures the compare value for the specified timer.
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
status_t FLEXIO_UART_DRV_TransferAbort(flexio_uart_state_t *state)
Aborts a non-blocking UART transfer.
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
static void FLEXIO_HAL_SetTimerConfig(FLEXIO_Type *baseAddr, uint8_t timer, flexio_timer_start_t start, flexio_timer_stop_t stop, flexio_timer_enable_t enable, flexio_timer_disable_t disable, flexio_timer_reset_t reset, flexio_timer_decrement_t decrement, flexio_timer_output_t output)
Sets all configuration settings for specified timer.
static void EDMA_HAL_TCDSetDisableDmaRequestAfterTCDDoneCmd(DMA_Type *base, uint32_t channel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
flexio_device_state_t * g_flexioDeviceStatePtr[FLEXIO_INSTANCE_COUNT]
DMA_Type *const g_edmaBase[DMA_INSTANCE_COUNT]
Array for the eDMA module register base address.
static bool FLEXIO_HAL_GetShifterStatus(const FLEXIO_Type *baseAddr, uint8_t shifter)
Returns the current status of the specified shifter.
static void FLEXIO_HAL_ClearShifterErrorStatus(FLEXIO_Type *baseAddr, uint8_t shifter)
Clears the error status of the specified shifter.
static void DMAMUX_HAL_SetChannelSource(DMAMUX_Type *base, uint32_t channel, uint8_t source)
Configures the DMA request for the DMAMUX channel.
static void FLEXIO_HAL_SetShifterErrorInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the shifter error interrupts.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
static bool FLEXIO_HAL_GetShifterErrorStatus(const FLEXIO_Type *baseAddr, uint8_t shifter)
Returns the current error status of the specified shifter.
const clock_names_t g_flexioClock[FLEXIO_INSTANCE_COUNT]
status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t dataBufferSize)
Configures a simple single block data transfer with DMA.
flexio_driver_type_t driverType
Driver configuration structure.
status_t FLEXIO_UART_DRV_Init(uint32_t instance, const flexio_uart_user_config_t *userConfigPtr, flexio_uart_state_t *state)
Initialize the FLEXIO_UART driver.
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
static void FLEXIO_HAL_ClearShifterStatus(FLEXIO_Type *baseAddr, uint8_t shifter)
Clears the status of the specified shifter.
static void FLEXIO_HAL_SetShifterDMARequest(FLEXIO_Type *baseAddr, uint8_t requestMask, bool enable)
Enables or disables the shifter DMA requests.