S32 SDK
mpu_hal.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
23 #ifndef MPU_HAL_H
24 #define MPU_HAL_H
25 
26 #include <stdint.h>
27 #include <stdbool.h>
28 #include "device_registers.h"
29 
40 /*******************************************************************************
41  * Definitions
42  *******************************************************************************/
47 typedef enum
48 {
52 
57 typedef enum
58 {
64 
69 typedef enum
70 {
76 
81 typedef enum
82 {
92 
97 typedef struct
98 {
99  uint8_t master;
102  uint16_t accessCtr;
103  uint32_t addr;
104 #if FEATURE_MPU_HAS_PROCESS_IDENTIFIER
106 #endif
108 
114 typedef struct
115 {
118 #if FEATURE_MPU_HAS_PROCESS_IDENTIFIER
120 #endif
122 
127 typedef struct
128 {
129  bool writeEnable;
130  bool readEnable;
132 
133 /*******************************************************************************
134  * API
135  *******************************************************************************/
136 #if defined(__cplusplus)
137 extern "C" {
138 #endif
139 
146 static inline void MPU_HAL_Enable(MPU_Type * const base)
147 {
148  base->CESR |= MPU_CESR_VLD_MASK;
149 }
150 
157 static inline void MPU_HAL_Disable(MPU_Type * const base)
158 {
159  base->CESR &= ~MPU_CESR_VLD_MASK;
160 }
161 
171 static inline bool MPU_HAL_IsEnable(const MPU_Type * const base)
172 {
173  return (((base->CESR & MPU_CESR_VLD_MASK) >> MPU_CESR_VLD_SHIFT) != 0U);
174 }
175 
183 static inline uint8_t MPU_HAL_GetHardwareRevision(const MPU_Type * const base)
184 {
185  return (uint8_t)((base->CESR & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT);
186 }
187 
197 bool MPU_HAL_GetSlavePortErrorStatus(const MPU_Type * const base,
198  uint8_t slaveNum);
199 
208  uint8_t slaveNum,
209  mpu_access_err_info_t *errInfoPtr);
210 
221 void MPU_HAL_SetRegionAddr(MPU_Type * const base,
222  uint8_t regionNum,
223  uint32_t startAddr,
224  uint32_t endAddr);
225 
239  uint8_t regionNum,
240  uint8_t masterNum,
241  const mpu_low_masters_access_rights_t *accessRightsPtr);
242 
255  uint8_t regionNum,
256  uint8_t masterNum,
257  const mpu_high_masters_access_rights_t *accessRightsPtr);
258 
268 static inline void MPU_HAL_SetRegionValidCmd(MPU_Type * const base,
269  uint8_t regionNum,
270  bool enable)
271 {
272  DEV_ASSERT(regionNum < MPU_RGD_COUNT);
273 
274  base->RGD[regionNum].WORD3 = ((base->RGD[regionNum].WORD3 & ~MPU_RGD_WORD3_VLD_MASK) | MPU_RGD_WORD3_VLD(enable ? 1UL : 0UL));
275 }
276 
277 #if FEATURE_MPU_HAS_PROCESS_IDENTIFIER
278 
286 static inline void MPU_HAL_SetProcessIdentifierMask(MPU_Type * const base,
287  uint8_t regionNum,
288  uint8_t processIdentifierMask)
289 {
290  uint32_t temp;
291 
292  DEV_ASSERT(regionNum < MPU_RGD_COUNT);
293 
294  temp = base->RGD[regionNum].WORD3;
295  temp &= ~(MPU_RGD_WORD3_PIDMASK_MASK);
296  temp |= MPU_RGD_WORD3_PIDMASK(processIdentifierMask);
297  base->RGD[regionNum].WORD3 = temp;
298 }
299 
308 static inline void MPU_HAL_SetProcessIdentifier(MPU_Type * const base,
309  uint8_t regionNum,
310  uint8_t processIdentifier)
311 {
312  uint32_t temp;
313 
314  DEV_ASSERT(regionNum < MPU_RGD_COUNT);
315 
316  temp = base->RGD[regionNum].WORD3;
317  temp &= ~(MPU_RGD_WORD3_PID_MASK);
318  temp |= MPU_RGD_WORD3_PID(processIdentifier);
319  base->RGD[regionNum].WORD3 = temp;
320 }
321 #endif
322 
333  uint8_t regionNum,
334  uint8_t masterNum,
335  const mpu_low_masters_access_rights_t *accessRightsPtr);
336 
347  uint8_t regionNum,
348  uint8_t masterNum,
349  const mpu_high_masters_access_rights_t *accessRightsPtr);
350 
357 void MPU_HAL_Init(MPU_Type * const base);
358 
361 #if defined(__cplusplus)
362 }
363 #endif
364 
367 #endif /* MPU_HAL_H*/
368 /*******************************************************************************
369  * EOF
370  *******************************************************************************/
static void MPU_HAL_SetProcessIdentifierMask(MPU_Type *const base, uint8_t regionNum, uint8_t processIdentifierMask)
Sets the process identifier mask.
Definition: mpu_hal.h:286
void MPU_HAL_SetAlternateHighMasterAccessRights(MPU_Type *const base, uint8_t regionNum, uint8_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr)
Sets access permission for master which has only read and write permissions in a specific region by a...
Definition: mpu_hal.c:305
MPU access rights for master which have only read and write permissions Implements : mpu_high_masters...
Definition: mpu_hal.h:127
#define MPU_CESR_VLD_SHIFT
Definition: S32K144.h:7584
struct MPU_Type::@15 RGD[MPU_RGD_COUNT]
void MPU_HAL_SetHighMasterAccessRights(MPU_Type *const base, uint8_t regionNum, uint8_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr)
Sets access permission for master which has only read and write permissions in a specific region...
Definition: mpu_hal.c:220
bool MPU_HAL_GetSlavePortErrorStatus(const MPU_Type *const base, uint8_t slaveNum)
Gets the error status of a specified slave port.
Definition: mpu_hal.c:65
#define MPU_CESR_VLD_MASK
Definition: S32K144.h:7583
#define MPU_RGD_WORD3_PID(x)
Definition: S32K144.h:7736
#define MPU_RGD_WORD3_PIDMASK(x)
Definition: S32K144.h:7732
mpu_err_access_type_t accessType
Definition: mpu_hal.h:101
mpu_user_access_rights_t userAccessRights
Definition: mpu_hal.h:116
static void MPU_HAL_Disable(MPU_Type *const base)
Disables the MPU module.
Definition: mpu_hal.h:157
#define DEV_ASSERT(x)
Definition: devassert.h:78
static uint8_t MPU_HAL_GetHardwareRevision(const MPU_Type *const base)
Gets MPU hardware revision level.
Definition: mpu_hal.h:183
uint8_t processorIdentification
Definition: mpu_hal.h:105
static void MPU_HAL_Enable(MPU_Type *const base)
Enables the MPU module.
Definition: mpu_hal.h:146
void MPU_HAL_SetAlternateLowMasterAccessRights(MPU_Type *const base, uint8_t regionNum, uint8_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr)
Sets access permission for master which has separated privilege rights for user and supervisor mode a...
Definition: mpu_hal.c:258
mpu_supervisor_access_rights_t
MPU access rights in supervisor mode Implements : mpu_supervisor_access_rights_t_Class.
Definition: mpu_hal.h:69
void MPU_HAL_SetLowMasterAccessRights(MPU_Type *const base, uint8_t regionNum, uint8_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr)
Sets access permission for master which has separated privilege rights for user and supervisor mode a...
Definition: mpu_hal.c:170
void MPU_HAL_Init(MPU_Type *const base)
Initializes the MPU module and all regions will be invalid after cleared access permission.
Definition: mpu_hal.c:342
#define MPU_RGD_WORD3_PIDMASK_MASK
Definition: S32K144.h:7729
#define MPU_RGD_WORD3_PID_MASK
Definition: S32K144.h:7733
static void MPU_HAL_SetRegionValidCmd(MPU_Type *const base, uint8_t regionNum, bool enable)
Sets the region valid value. When a region changed not by alternating registers should set the valid ...
Definition: mpu_hal.h:268
#define MPU_CESR_HRL_SHIFT
Definition: S32K144.h:7596
#define MPU_RGD_COUNT
Definition: S32K144.h:7531
mpu_supervisor_access_rights_t superAccessRights
Definition: mpu_hal.h:117
mpu_err_attributes_t
MPU access error attributes Implements : mpu_err_attributes_t_Class.
Definition: mpu_hal.h:57
mpu_err_attributes_t attributes
Definition: mpu_hal.h:100
mpu_user_access_rights_t
MPU access rights in user mode Implements : mpu_user_access_rights_t_Class.
Definition: mpu_hal.h:81
MPU detail error access info Implements : mpu_access_err_info_t_Class.
Definition: mpu_hal.h:97
#define MPU_RGD_WORD3_VLD_MASK
Definition: S32K144.h:7725
MPU access rights for masters which have separated privilege rights for user and supervisor mode acce...
Definition: mpu_hal.h:114
void MPU_HAL_SetRegionAddr(MPU_Type *const base, uint8_t regionNum, uint32_t startAddr, uint32_t endAddr)
Sets region start and end address. Please note that using this function will clear the valid bit of t...
Definition: mpu_hal.c:144
#define MPU_RGD_WORD3_VLD(x)
Definition: S32K144.h:7728
__IO uint32_t CESR
Definition: S32K144.h:7536
#define MPU_CESR_HRL_MASK
Definition: S32K144.h:7595
void MPU_HAL_GetDetailErrorAccessInfo(MPU_Type *const base, uint8_t slaveNum, mpu_access_err_info_t *errInfoPtr)
Gets MPU detail error access info.
Definition: mpu_hal.c:91
static void MPU_HAL_SetProcessIdentifier(MPU_Type *const base, uint8_t regionNum, uint8_t processIdentifier)
Sets the process identifier.
Definition: mpu_hal.h:308
static bool MPU_HAL_IsEnable(const MPU_Type *const base)
Checks whether the MPU module is enabled.
Definition: mpu_hal.h:171
uint16_t accessCtr
Definition: mpu_hal.h:102
__IO uint32_t WORD3
Definition: S32K144.h:7551
mpu_err_access_type_t
MPU access error Implements : mpu_err_access_type_t_Class.
Definition: mpu_hal.h:47