S32 SDK
S32K144_features.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015 Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
40 #if !defined(S32K144_FEATURES_H)
41 #define S32K144_FEATURES_H
42 
43 /* ERRATA sections*/
44 
45 /* @brief ARM Errata 838869: Store immediate overlapping exception return operation might vector to
46  * incorrect interrupt. */
47 #define ERRATA_E9005
48 
49 /* @brief ARM Errata 709718: VDIV or VSQRT instructions might not complete correctly when very
50  * short ISRs are used. */
51 #define ERRATA_E6940
52 
53 /* @brief E10655: When using LPSPI in master mode and the SR[MBF] bit is read as a one, then, the
54  * flag is set. If it is read as a zero, it must be read second time and this second read will be
55  * the correct state of the bit.​ */
56 #define ERRATA_E10655
57 
58 /* @brief E10792: LPI2C: Slave Transmit Data Flag may incorrectly read as one when TXCFG is zero.
59  * Interrupts for transfer data should be enabled after the address valid event is detected and
60  * disabled at the end of the transfer. */
61 #define ERRATA_E10792
62 
63 /* PCC module features */
64 
65 /* @brief Has InUse feature (register bit PCC[INUSE]). */
66 #define FEATURE_PCC_HAS_IN_USE_FEATURE (0)
67 
68 /* PORT module features */
69 
70 /* @brief Has control lock (register bit PCR[LK]). */
71 #define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
72 /* @brief Has open drain control (register bit PCR[ODE]). */
73 #define FEATURE_PORT_HAS_OPEN_DRAIN (0)
74 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
75 #define FEATURE_PORT_HAS_DIGITAL_FILTER (1)
76 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
77 #define FEATURE_PORT_HAS_DMA_REQUEST (1)
78 /* @brief Has pull resistor selection available. */
79 #define FEATURE_PORT_HAS_PULL_SELECTION (1)
80 /* @brief Has slew rate control (register bit PCR[SRE]). */
81 #define FEATURE_PORT_HAS_SLEW_RATE (0)
82 /* @brief Has passive filter (register bit field PCR[PFE]). */
83 #define FEATURE_PORT_HAS_PASSIVE_FILTER (1)
84 /* @brief Has drive strength control (register bit PCR[DSE]). */
85 #define FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
86 
87 /* SOC module features */
88 
89 /* @brief PORT availability on the SoC. */
90 #define FEATURE_SOC_PORT_COUNT (5)
91 
92 #define FEATURE_SOC_SCG_COUNT (1)
93 /* @brief Slow IRC low range clock frequency. */
94 #define FEATURE_SCG_SIRC_LOW_RANGE_FREQ (2000000U)
95 /* @brief Slow IRC high range clock frequency. */
96 #define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U)
97 
98 /* @brief Fast IRC trimmed clock frequency(48MHz). */
99 #define FEATURE_SCG_FIRC_FREQ0 (48000000U)
100 /* @brief Fast IRC trimmed clock frequency(52MHz). */
101 #define FEATURE_SCG_FIRC_FREQ1 (52000000U)
102 /* @brief Fast IRC trimmed clock frequency(56MHz). */
103 #define FEATURE_SCG_FIRC_FREQ2 (56000000U)
104 /* @brief Fast IRC trimmed clock frequency(60MHz). */
105 #define FEATURE_SCG_FIRC_FREQ3 (60000000U)
106 
107 /* FLASH module features */
108 
109 /* @brief Is of type FTFA. */
110 #define FEATURE_FLS_IS_FTFA (0u)
111 /* @brief Is of type FTFC. */
112 #define FEATURE_FLS_IS_FTFC (1u)
113 /* @brief Is of type FTFE. */
114 #define FEATURE_FLS_IS_FTFE (0u)
115 /* @brief Is of type FTFL. */
116 #define FEATURE_FLS_IS_FTFL (0u)
117 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
118 #define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u)
119 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
120 #define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u)
121 /* @brief Has EEPROM region protection (register FEPROT). */
122 #define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u)
123 /* @brief Has data flash region protection (register FDPROT). */
124 #define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u)
125 /* @brief P-Flash block count. */
126 #define FEATURE_FLS_PF_BLOCK_COUNT (1u)
127 /* @brief P-Flash block size. */
128 #define FEATURE_FLS_PF_BLOCK_SIZE (524288u)
129 /* @brief P-Flash sector size. */
130 #define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (4096u)
131 /* @brief P-Flash write unit size. */
132 #define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u)
133 /* @brief P-Flash block swap feature. */
134 #define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u)
135 /* @brief Has FlexNVM memory. */
136 #define FEATURE_FLS_HAS_FLEX_NVM (1u)
137 /* @brief FlexNVM block count. */
138 #define FEATURE_FLS_DF_BLOCK_COUNT (1u)
139 /* @brief FlexNVM block size. */
140 #define FEATURE_FLS_DF_BLOCK_SIZE (65536u)
141 /* @brief FlexNVM sector size. */
142 #define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (2048u)
143 /* @brief FlexNVM write unit size. */
144 #define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u)
145 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
146 #define FEATURE_FLS_DF_START_ADDRESS (0x10000000u)
147 /* @brief Has FlexRAM memory. */
148 #define FEATURE_FLS_HAS_FLEX_RAM (1u)
149 /* @brief FlexRAM size. */
150 #define FEATURE_FLS_FLEX_RAM_SIZE (4096u)
151 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
152 #define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u)
153 /* @brief Has 0x00 Read 1s Block command. */
154 #define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u)
155 /* @brief Has 0x01 Read 1s Section command. */
156 #define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u)
157 /* @brief Has 0x02 Program Check command. */
158 #define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u)
159 /* @brief Has 0x03 Read Resource command. */
160 #define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u)
161 /* @brief Has 0x06 Program Longword command. */
162 #define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u)
163 /* @brief Has 0x07 Program Phrase command. */
164 #define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u)
165 /* @brief Has 0x08 Erase Flash Block command. */
166 #define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u)
167 /* @brief Has 0x09 Erase Flash Sector command. */
168 #define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u)
169 /* @brief Has 0x0B Program Section command. */
170 #define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u)
171 /* @brief Has 0x40 Read 1s All Blocks command. */
172 #define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u)
173 /* @brief Has 0x41 Read Once command. */
174 #define FEATURE_FLS_HAS_READ_ONCE_CMD (1u)
175 /* @brief Has 0x43 Program Once command. */
176 #define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u)
177 /* @brief Has 0x44 Erase All Blocks command. */
178 #define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u)
179 /* @brief Has 0x45 Verify Backdoor Access Key command. */
180 #define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u)
181 /* @brief Has 0x46 Swap Control command. */
182 #define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u)
183 /* @brief Has 0x49 Erase All Blocks unsecure command. */
184 #define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u)
185 /* @brief Has 0x80 Program Partition command. */
186 #define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u)
187 /* @brief Has 0x81 Set FlexRAM Function command. */
188 #define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u)
189 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
190 #define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (16u)
191 /* @brief P-Flash Erase sector command address alignment. */
192 #define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (16u)
193 /* @brief P-Flash Program/Verify section command address alignment. */
194 #define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (16u)
195 /* @brief P-Flash Read resource command address alignment. */
196 #define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
197 /* @brief P-Flash Program check command address alignment. */
198 #define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
199 /* @brief P-Flash Program check command address alignment. */
200 #define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u)
201 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
202 #define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
203 /* @brief FlexNVM Erase sector command address alignment. */
204 #define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
205 /* @brief FlexNVM Program/Verify section command address alignment. */
206 #define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
207 /* @brief FlexNVM Read resource command address alignment. */
208 #define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
209 /* @brief FlexNVM Program check command address alignment. */
210 #define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
211 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
212 #define FEATURE_FLS_DF_SIZE_0000 (0x00010000u)
213 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
214 #define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu)
215 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
216 #define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu)
217 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
218 #define FEATURE_FLS_DF_SIZE_0011 (0x00008000u)
219 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
220 #define FEATURE_FLS_DF_SIZE_0100 (0x00000000u)
221 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
222 #define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu)
223 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
224 #define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu)
225 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
226 #define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu)
227 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
228 #define FEATURE_FLS_DF_SIZE_1000 (0x00000000u)
229 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
230 #define FEATURE_FLS_DF_SIZE_1001 (0xFFFFFFFFu)
231 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
232 #define FEATURE_FLS_DF_SIZE_1010 (0x00004000u)
233 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
234 #define FEATURE_FLS_DF_SIZE_1011 (0x00008000u)
235 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
236 #define FEATURE_FLS_DF_SIZE_1100 (0x00010000u)
237 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
238 #define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu)
239 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
240 #define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu)
241 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
242 #define FEATURE_FLS_DF_SIZE_1111 (0x00010000u)
243 /* @brief Emulated EEPROM size code 0000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
244 #define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu)
245 /* @brief Emulated EEPROM size code 0001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
246 #define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu)
247 /* @brief Emulated EEPROM size code 0010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
248 #define FEATURE_FLS_EE_SIZE_0010 (0x1000u)
249 /* @brief Emulated EEPROM size code 0011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
250 #define FEATURE_FLS_EE_SIZE_0011 (0x0800u)
251 /* @brief Emulated EEPROM size code 0100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
252 #define FEATURE_FLS_EE_SIZE_0100 (0x0400u)
253 /* @brief Emulated EEPROM size code 0101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
254 #define FEATURE_FLS_EE_SIZE_0101 (0x0200u)
255 /* @brief Emulated EEPROM size code 0110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
256 #define FEATURE_FLS_EE_SIZE_0110 (0x0100u)
257 /* @brief Emulated EEPROM size code 0111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
258 #define FEATURE_FLS_EE_SIZE_0111 (0x0080u)
259 /* @brief Emulated EEPROM size code 1000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
260 #define FEATURE_FLS_EE_SIZE_1000 (0x0040u)
261 /* @brief Emulated EEPROM size code 1001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
262 #define FEATURE_FLS_EE_SIZE_1001 (0x0020u)
263 /* @brief Emulated EEPROM size code 1010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
264 #define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu)
265 /* @brief Emulated EEPROM size code 1011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
266 #define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu)
267 /* @brief Emulated EEPROM size code 1100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
268 #define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu)
269 /* @brief Emulated EEPROM size code 1101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
270 #define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu)
271 /* @brief Emulated EEPROM size code 1110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
272 #define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu)
273 /* @brief Emulated EEPROM size code 1111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
274 #define FEATURE_FLS_EE_SIZE_1111 (0x0000u)
275 
276 /* CAN module features */
277 
278 /* @brief Frames available in Rx FIFO flag shift */
279 #define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U)
280 /* @brief Rx FIFO warning flag shift */
281 #define FEATURE_CAN_RXFIFO_WARNING (6U)
282 /* @brief Rx FIFO overflow flag shift */
283 #define FEATURE_CAN_RXFIFO_OVERFLOW (7U)
284 /* @brief Has Flexible Data Rate for CAN0 */
285 #define FEATURE_CAN0_HAS_FD (1)
286 /* @brief Has Flexible Data Rate for CAN1 */
287 #define FEATURE_CAN1_HAS_FD (0)
288 /* @brief Has Flexible Data Rate for CAN2 */
289 #define FEATURE_CAN2_HAS_FD (0)
290 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */
291 #define FEATURE_CAN0_MAX_MB_NUM (32U)
292 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN1 */
293 #define FEATURE_CAN1_MAX_MB_NUM (16U)
294 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN2 */
295 #define FEATURE_CAN2_MAX_MB_NUM (16U)
296 /* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */
297 #define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1)
298 /* @brief Has DMA enable (bit field MCR[DMA]). */
299 #define FEATURE_CAN_HAS_DMA_ENABLE (1)
300 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
301 #define FEATURE_CAN_MAX_MB_NUM (32U)
302 /* @brief Has Pretending Networking mode */
303 #define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1)
304 /* @brief Has Stuff Bit Count Enable Bit */
305 #define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0)
306 /* @brief Has ISO CAN FD Enable Bit */
307 #define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1)
308 /* @brief Has Message Buffer Data Size Region 1 */
309 #define FEATURE_CAN_HAS_MBDSR1 (0)
310 /* @brief Maximum number of Message Buffers IRQs */
311 #define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U)
312 /* @brief Message Buffers IRQs */
313 #define FEATURE_CAN_MB_IRQS { { CAN0_ORed_0_15_MB_IRQn, CAN0_ORed_16_31_MB_IRQn }, \
314  { CAN1_ORed_0_15_MB_IRQn, NotAvail_IRQn }, \
315  { CAN2_ORed_0_15_MB_IRQn, NotAvail_IRQn } }
316 
317 /* LPUART module features */
318 
319 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
320 #define FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
321 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
322 #define FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
323 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
324 #define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
325 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
326 #define FEATURE_LPUART_HAS_FIFO (0)
327 /* @brief Has 32-bit register MODIR */
328 #define FEATURE_LPUART_HAS_MODIR (1)
329 /* @brief Hardware flow control (RTS, CTS) is supported. */
330 #define FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
331 /* @brief Infrared (modulation) is supported. */
332 #define FEATURE_LPUART_HAS_IR_SUPPORT (1)
333 /* @brief 2 bits long stop bit is available. */
334 #define FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
335 /* @brief Maximal data width without parity bit. */
336 #define FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
337 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
338 #define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
339 /* @brief Baud rate oversampling is available. */
340 #define FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
341 /* @brief Baud rate oversampling is available. */
342 #define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
343 /* @brief Peripheral type. */
344 #define FEATURE_LPUART_IS_SCI (1)
345 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
346 #define FEATURE_LPUART_FIFO_SIZE (4U)
347 /* @brief Supports two match addresses to filter incoming frames. */
348 #define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
349 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
350 #define FEATURE_LPUART_HAS_DMA_ENABLE (1)
351 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
352 #define FEATURE_LPUART_HAS_DMA_SELECT (0)
353 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
354 #define FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
355 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
356 #define FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
357 /* @brief Has improved smart card (ISO7816 protocol) support. */
358 #define FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
359 /* @brief Has local operation network (CEA709.1-B protocol) support. */
360 #define FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
361 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
362 #define FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
363 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
364 #define FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0)
365 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
366 #define FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
367 /* @brief Flag clearance mask for STAT register. */
368 #define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U)
369 /* @brief Flag clearance mask for FIFO register. */
370 #define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U)
371 /* @brief Default oversampling ratio. */
372 #define FEATURE_LPUART_DEFAULT_OSR (0x0FUL)
373 /* @brief Default baud rate modulo divisor. */
374 #define FEATURE_LPUART_DEFAULT_SBR (0x04UL)
375 
376 /* FLEXIO module features */
377 
378 /* @brief Define the maximum number of shifters for any FlexIO instance. */
379 #define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U)
380 
381 /* LPSPI module features */
382 
383 /* @brief DMA instance used for LPSPI module */
384 #define LPSPI_DMA_INSTANCE 0U
385 
386 /* @brief DMA instance used for LPI2C module */
387 #define LPI2C_DMA_INSTANCE 0U
388 
389 /* PDB module features */
390 
391 /* @brief Define the count of supporting ADC channels per each PDB. */
392 #define FEATURE_PDB_ADC_CHANNEL_COUNT (2U)
393 /* @brief Define the count of supporting ADC pre-trigger for each channel. */
394 #define FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (8U)
395 /* @brief Define the count of supporting Pulse-Out outputs per each PDB. */
396 #define FEATURE_PDB_PODLY_COUNT (1U)
397 
398 /* Interrupt module features */
399 
400 /* @brief Lowest interrupt request number. */
401 #define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn)
402 /* @brief Highest interrupt request number. */
403 #define FEATURE_INTERRUPT_IRQ_MAX (FTM3_Ovf_Reload_IRQn)
404 
405 #define FEATURE_NVIC_PRIO_BITS (4U)
406 
407 
408 /* System Control Block module features */
409 
410 /* @brief VECTKEY value so that AIRCR register write is not ignored. */
411 #define FEATURE_SCB_VECTKEY (0x05FAU)
412 
413 
414 /* SMC module features */
415 
416 /* @brief Has stop option (register bit STOPCTRL[STOPO]). */
417 #define FEATURE_SMC_HAS_STOPO (1)
418 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
419 #define FEATURE_SMC_HAS_PSTOPO (0)
420 /* @brief Has WAIT and VLPW options. */
421 #define FEATURE_SMC_HAS_WAIT_VLPW (0)
422 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
423 #define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
424 
425 
426 /* MPU module features */
427 
428 /* @brief Has process identifier support. */
429 #define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U)
430 /* @brief Specifies total number of bus masters. */
431 #define FEATURE_MPU_MASTER_COUNT (3U)
432 /* @brief Specifies maximum number of masters which have separated
433 privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K144).
434 */
435 #define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U)
436 /* @brief Specifies maximum number of masters which have only
437 read and write permissions (e.g. master4~7 in S32K144).
438 */
439 #define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U)
440 
441 /* @brief Specifies number of set access control right bits for
442  masters which have separated privilege rights for user and
443  supervisor mode accesses (e.g. master0~3 in S32K144).
444 */
445 #define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U)
446 /* @brief Specifies number of set access control right bits for
447  masters which have only read and write permissions(e.g. master4~7 in S32K144).
448 */
449 #define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U)
450 
451 /* @brief The MPU Logical Bus Master Number for core bus master. */
452 #define FEATURE_MPU_MASTER_CORE (0U)
453 /* @brief The MPU Logical Bus Master Number for Debugger master. */
454 #define FEATURE_MPU_MASTER_DEBUGGER (1U)
455 /* @brief The MPU Logical Bus Master Number for DMA master. */
456 #define FEATURE_MPU_MASTER_DMA (2U)
457 
458 /* @brief Specifies total number of slave ports. */
459 #define FEATURE_MPU_SLAVE_COUNT (4U)
460 /* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */
461 #define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U)
462 /* @brief The MPU Slave Port Assignment for SRAM back door. */
463 #define FEATURE_MPU_SLAVE_SRAM_BACKDOOR (1U)
464 /* @brief The MPU Slave Port Assignment for SRAM_L front door. */
465 #define FEATURE_MPU_SLAVE_SRAM_L_FRONTDOOR (2U)
466 /* @brief The MPU Slave Port Assignment for SRAM_U front door. */
467 #define FEATURE_MPU_SLAVE_SRAM_U_FRONTDOOR (3U)
468 /* @brief The MPU Slave Port mask. */
469 #define FEATURE_MPU_SLAVE_MASK (0xF0000000U)
470 
471 /* WDOG module features */
472 
473 /* @brief The 32-bit value used for unlocking the WDOG. */
474 #define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U)
475 /* @brief The 32-bit value used for resetting the WDOG counter. */
476 #define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U)
477 /* @brief The reset value of the timeout register. */
478 #define FEATURE_WDOG_TO_RESET_VALUE (0x400U)
479 /* @brief The reset value of the window register. */
480 #define FEATURE_WDOG_WIN_RESET_VALUE (0x0U)
481 /* @brief The mask of the reserved bit in the CS register. */
482 #define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U)
483 /* @brief The value used to set WDOG source clock from LPO. */
484 #define FEATURE_WDOG_CLK_FROM_LPO (0x1UL)
485 /* @brief The first 16-bit value used for unlocking the WDOG. */
486 #define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U)
487 /* @brief The second 16-bit value used for unlocking the WDOG. */
488 #define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U)
489 /* @brief The first 16-bit value used for resetting the WDOG counter. */
490 #define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U)
491 /* @brief The second 16-bit value used for resetting the WDOG counter. */
492 #define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U)
493 
494 
495 /* EDMA module features */
496 
497 /* @brief Number of EDMA channels. */
498 #define FEATURE_EDMA_MODULE_CHANNELS (16U)
499 /* @brief Number of EDMA channel interrupt lines. */
500 #define FEATURE_CHANNEL_INTERRUPT_LINES (16U)
501 /* @brief Number of EDMA error interrupt lines. */
502 #define FEATURE_ERROR_INTERRUPT_LINES (1U)
503 /* @brief eDMA module has error interrupt. */
504 #define FEATURE_EDMA_HAS_ERROR_IRQ
505 /* @brief eDMA module has separate interrupt lines for each channel. */
506 #define FEATURE_EDMA_SEPARATE_IRQ_LINES_PER_CHN
507 /* @brief Conversion from channel index to DCHPRI index. */
508 #define FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(x) ((x) ^ 3U)
509 /* @brief eDMA channel groups count. */
510 #define FEATURE_EDMA_CHANNEL_GROUP_COUNT (1U)
511 /* @brief Number of eDMA channels with asynchronous request capability. */
512 #define FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16U)
513 /* @brief Clock names for eDMA. */
514 #define EDMA_CLOCK_NAMES {SIM_DMA_CLOCK}
515 
516 /* DMAMUX module features */
517 
518 /* @brief Number of DMA channels. */
519 #define FEATURE_DMAMUX_MODULE_CHANNELS (16U)
520 /* @brief Has the periodic trigger capability */
521 #define FEATURE_DMAMUX_HAS_TRIG (1)
522 /* @brief Conversion from request source to the actual DMAMUX channel */
523 #define FEATURE_DMAMUX_REQ_SRC_TO_CHN(x) (x)
524 /* @brief Mapping between request source and DMAMUX instance */
525 #define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U)
526 /* @brief Conversion from eDMA channel index to DMAMUX channel. */
527 #define FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(x) (x)
528 /* @brief Conversion from DMAMUX channel DMAMUX register index. */
529 #define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x)
530 /* @brief Clock names for DMAMUX. */
531 #define DMAMUX_CLOCK_NAMES {PCC_DMAMUX0_CLOCK}
532 
540 typedef enum {
595 
596 /* LPI2C module features */
597 
598 /* @brief Disable high-speed and ultra-fast operating modes for S32K144. */
599 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
600 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
601 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
602 
603 /* FTM module features */
604 /* @brief Number of PWM channels */
605 #define FEATURE_FTM_CHANNEL_COUNT (8U)
606 /* @brief Number of fault channels */
607 #define FTM_FEATURE_FAULT_CHANNELS (4U)
608 /* @brief Width of control channel */
609 #define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U)
610 /* @brief Output channel offset */
611 #define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U)
612 /* @brief Max counter value */
613 #define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU)
614 /* @brief Input capture for single shot */
615 #define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U)
616 
617 /* EWM module features */
618 
619 /* @brief First byte of the EWM Service key */
620 #define FEATURE_EWM_KEY_FIRST_BYTE (0xB4U)
621 /* @brief Second byte of the EWM Service key */
622 #define FEATURE_EWM_KEY_SECOND_BYTE (0x2CU)
623 /* @brief EWM Compare High register maximum value */
624 #define FEATURE_EWM_CMPH_MAX_VALUE (0xFEU)
625 /* @brief EWM Compare Low register minimum value */
626 #define FEATURE_EWM_CMPL_MIN_VALUE (0x00U)
627 
628 /* CLOCK names */
629 
631 typedef enum {
632 
633  /* Main clocks */
634  CORE_CLOCK = 0u,
635  BUS_CLOCK = 1u,
636  SLOW_CLOCK = 2u,
639  /* Other internal clocks used by peripherals. */
640  SIRC_CLOCK = 4u,
641  FIRC_CLOCK = 5u,
642  SOSC_CLOCK = 6u,
643  SPLL_CLOCK = 7u,
648  /* SIM clocks */
666  /* PCC clocks */
707 } clock_names_t;
708 
709 #define PCC_INVALID_INDEX 0
710 
716 #define PCC_CLOCK_NAME_MAPPINGS \
717 { \
718 PCC_INVALID_INDEX, \
719 PCC_INVALID_INDEX, \
720 PCC_INVALID_INDEX, \
721 PCC_INVALID_INDEX, \
722 PCC_INVALID_INDEX, \
723 PCC_INVALID_INDEX, \
724 PCC_INVALID_INDEX, \
725 PCC_INVALID_INDEX, \
726 PCC_INVALID_INDEX, \
727 PCC_INVALID_INDEX, \
728 PCC_INVALID_INDEX, \
729 PCC_INVALID_INDEX, \
730 PCC_INVALID_INDEX, \
731 PCC_INVALID_INDEX, \
732 PCC_INVALID_INDEX, \
733 PCC_INVALID_INDEX, \
734 PCC_INVALID_INDEX, \
735 PCC_INVALID_INDEX, \
736 PCC_INVALID_INDEX, \
737 PCC_INVALID_INDEX, \
738 PCC_INVALID_INDEX, \
739 PCC_INVALID_INDEX, \
740 PCC_INVALID_INDEX, \
741 PCC_INVALID_INDEX, \
742 PCC_INVALID_INDEX, \
743 PCC_INVALID_INDEX, \
744 PCC_INVALID_INDEX, \
745 PCC_INVALID_INDEX, \
746 PCC_INVALID_INDEX, \
747 PCC_INVALID_INDEX, \
748 PCC_INVALID_INDEX, \
749 PCC_INVALID_INDEX, \
750 PCC_INVALID_INDEX, \
751 PCC_INVALID_INDEX, \
752 PCC_INVALID_INDEX, \
753 PCC_INVALID_INDEX, \
754 PCC_INVALID_INDEX, \
755 PCC_INVALID_INDEX, \
756 PCC_INVALID_INDEX, \
757 PCC_INVALID_INDEX, \
758 PCC_INVALID_INDEX, \
759 PCC_DMAMUX_INDEX, \
760 PCC_CRC_INDEX, \
761 PCC_RTC_INDEX, \
762 PCC_PORTA_INDEX, \
763 PCC_PORTB_INDEX, \
764 PCC_PORTC_INDEX, \
765 PCC_PORTD_INDEX, \
766 PCC_PORTE_INDEX, \
767 PCC_EWM_INDEX, \
768 PCC_CMP0_INDEX, \
769 PCC_INVALID_INDEX, \
770 PCC_FlexCAN0_INDEX, \
771 PCC_FlexCAN1_INDEX, \
772 PCC_FlexCAN2_INDEX, \
773 PCC_PDB1_INDEX, \
774 PCC_PDB0_INDEX, \
775 PCC_INVALID_INDEX, \
776 PCC_FTFC_INDEX, \
777 PCC_INVALID_INDEX, \
778 PCC_FTM3_INDEX, \
779 PCC_FTM0_INDEX, \
780 PCC_FTM1_INDEX, \
781 PCC_FTM2_INDEX, \
782 PCC_INVALID_INDEX, \
783 PCC_ADC1_INDEX, \
784 PCC_LPSPI0_INDEX, \
785 PCC_LPSPI1_INDEX, \
786 PCC_LPSPI2_INDEX, \
787 PCC_LPIT_INDEX, \
788 PCC_ADC0_INDEX, \
789 PCC_LPTMR0_INDEX, \
790 PCC_FLEXIO_INDEX, \
791 PCC_LPI2C0_INDEX, \
792 PCC_LPUART0_INDEX, \
793 PCC_LPUART1_INDEX, \
794 PCC_LPUART2_INDEX, \
795 PCC_INVALID_INDEX, \
796 PCC_INVALID_INDEX, \
797 }
798 
799 /* Time to wait for SIRC to stabilize (number of
800  * cycles when core runs at maximum speed - 112 MHz */
801 #define SIRC_STABILIZATION_TIMEOUT 26U;
802 
803 /* Time to wait for FIRC to stabilize (number of
804  * cycles when core runs at maximum speed - 112 MHz */
805 #define FIRC_STABILIZATION_TIMEOUT 10U;
806 
807 /* Time to wait for SOSC to stabilize (number of
808  * cycles when core runs at maximum speed - 112 MHz */
809 #define SOSC_STABILIZATION_TIMEOUT 3205000U;
810 
811 /* Time to wait for SPLL to stabilize (number of
812  * cycles when core runs at maximum speed - 112 MHz */
813 #define SPLL_STABILIZATION_TIMEOUT 1000U;
814 
825 #define MAX_FREQ_VLPR 0U
826 #define MAX_FREQ_RUN 1U
827 #define MAX_FREQ_HSRUN 2U
828 
829 #define MAX_FREQ_SYS_CLK 0U
830 #define MAX_FREQ_BUS_CLK 1U
831 #define MAX_FREQ_SLOW_CLK 2U
832 
833 #define MAX_FREQ_MODES_NO 3U
834 #define MAX_FREQ_CLK_NO 3U
835 
836 #define CLOCK_MAX_FREQUENCIES \
837 {/* SYS_CLK BUS_CLK SLOW_CLK */ \
838 { 4000000, 4000000, 1000000}, \
839 { 80000000,40000000,26670000}, \
840 {112000000,56000000,28000000}, \
841 }
842 
843 
854 #define TMP_SIRC_CLK 0U
855 #define TMP_FIRC_CLK 1U
856 #define TMP_SOSC_CLK 2U
857 #define TMP_SPLL_CLK 3U
858 
859 #define TMP_SYS_DIV 0U
860 #define TMP_BUS_DIV 1U
861 #define TMP_SLOW_DIV 2U
862 
863 #define TMP_SYS_CLK_NO 4U
864 #define TMP_SYS_DIV_NO 3U
865 
866 #define TMP_SYSTEM_CLOCK_CONFIGS \
867 { /* SYS_CLK BUS_CLK SLOW_CLK */ \
868 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1}, \
869 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, \
870 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
871 { SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
872 }
873 
874 /* Do not use the old names of the renamed symbols */
875 /* #define DO_NOT_USE_DEPRECATED_SYMBOLS */
876 
882 #if !defined(DO_NOT_USE_DEPRECATED_SYMBOLS)
883 #define PCC_FLASH0_CLOCK PCC_FTFE0_CLOCK
884 #define PCC_DMA_CH_MUX0_CLOCK PCC_DMAMUX0_CLOCK
885 #define PCC_SRTC0_CLOCK PCC_RTC0_CLOCK
886 #define PCC_RGPIO0_CLOCK PCC_PORTA_CLOCK
887 #define PCC_RGPIO1_CLOCK PCC_PORTB_CLOCK
888 #define PCC_RGPIO2_CLOCK PCC_PORTC_CLOCK
889 #define PCC_RGPIO3_CLOCK PCC_PORTD_CLOCK
890 #define PCC_RGPIO4_CLOCK PCC_PORTE_CLOCK
891 #define PCC_CAN0_CLOCK PCC_FLEXCAN0_CLOCK
892 #define PCC_CAN1_CLOCK PCC_FLEXCAN1_CLOCK
893 #define PCC_CAN2_CLOCK PCC_FLEXCAN2_CLOCK
894 #define PCC_FLEXTMR3_CLOCK PCC_FTM3_CLOCK
895 #define PCC_FLEXTMR0_CLOCK PCC_FTM0_CLOCK
896 #define PCC_FLEXTMR1_CLOCK PCC_FTM1_CLOCK
897 #define PCC_FLEXTMR2_CLOCK PCC_FTM2_CLOCK
898 #define PCC_PIT0_CLOCK PCC_LPIT0_CLOCK
899 #define PCC_LPTIMER0_CLOCK PCC_LPTMR0_CLOCK
900 #define PCC_LPIIC0_CLOCK PCC_LPI2C0_CLOCK
901 #define PCC_FTFE0_CLOCK PCC_FTFC0_CLOCK
902 #endif /* !DO_NOT_USE_DEPRECATED_SYMBOLS */
903 
904 
905 /* CSEc module features */
906 
909 #define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU)
910 
912 #define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU)
913 
915 #define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U)
916 
918 #define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU)
919 
921 #define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU)
922 
924 #define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U)
925 
927 #define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U)
928 
929 #define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U)
930 
932 #define FEATURE_CSEC_SREG_OFFSET (0x2FU)
933 
935 #define FEATURE_CSEC_PAGE_0_OFFSET (0x0U)
936 
937 #define FEATURE_CSEC_PAGE_1_OFFSET (0x10U)
938 
939 #define FEATURE_CSEC_PAGE_2_OFFSET (0x20U)
940 
941 #define FEATURE_CSEC_PAGE_3_OFFSET (0x30U)
942 
943 #define FEATURE_CSEC_PAGE_4_OFFSET (0x40U)
944 
945 #define FEATURE_CSEC_PAGE_5_OFFSET (0x50U)
946 
947 #define FEATURE_CSEC_PAGE_6_OFFSET (0x60U)
948 
949 #define FEATURE_CSEC_PAGE_7_OFFSET (0x70U)
950 
951 
952 /* ADC module features */
953 
957 #define ADC_INPUTCHAN_TEMP ADC_INPUTCHAN_AD26
958 #define ADC_INPUTCHAN_BANDGAP ADC_INPUTCHAN_AD27
959 #define ADC_INPUTCHAN_VREFSH ADC_INPUTCHAN_AD29
960 #define ADC_INPUTCHAN_VREFSL ADC_INPUTCHAN_AD30
961 #define ADC_INPUTCHAN_DISABLED ADC_INPUTCHAN_AD31
962 
963 /* MSCM module features */
964 
965 /* @brief Has interrupt router control registers (IRSPRCn). */
966 #define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0)
967 /* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */
968 #define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0)
969 
970 
971 #endif /* S32K144_FEATURES_H */
972 
973 /*******************************************************************************
974  * EOF
975  ******************************************************************************/
dma_request_source_t
Structure for the DMA hardware request.
clock_names_t
Clock names.