S32 SDK
lpit_hal.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
23 #ifndef LPIT_HAL_H
24 #define LPIT_HAL_H
25 
26 #include "device_registers.h"
27 #include <stdbool.h>
28 #include <stddef.h>
29 
35 /*******************************************************************************
36  * Definitions
37  *****************************************************************************/
38 
43 typedef struct
44 {
45  uint32_t majorVersionNumber;
46  uint32_t minorVersionNumber;
47  uint32_t featureNumber;
51 
52 /*******************************************************************************
53  * Enumerations
54  ******************************************************************************/
55 
60 typedef enum
61 {
67 
75 typedef enum
76 {
80 
81 /*******************************************************************************
82  * API
83  ******************************************************************************/
84 
85 #if defined(__cplusplus)
86 extern "C" {
87 #endif
88 
105 void LPIT_HAL_GetModuleInformation(const LPIT_Type * base,
106  lpit_module_information_t * moduleInfomation);
107 
118 static inline void LPIT_HAL_Enable(LPIT_Type * const base)
119 {
120  base->MCR |= LPIT_MCR_M_CEN_MASK;
121 }
122 
132 static inline void LPIT_HAL_Disable(LPIT_Type * const base)
133 {
134  base->MCR &= ~LPIT_MCR_M_CEN_MASK;
135 }
136 
146 static inline void LPIT_HAL_Reset(LPIT_Type * const base)
147 {
148  base->MCR |= LPIT_MCR_SW_RST_MASK;
149  base->MCR &= ~LPIT_MCR_SW_RST_MASK;
150 }
151 
175 static inline void LPIT_HAL_StartTimerChannels(LPIT_Type * const base,
176  uint32_t mask)
177 {
178  base->SETTEN |= mask;
179 }
180 
198 static inline void LPIT_HAL_StopTimerChannels(LPIT_Type * const base,
199  uint32_t mask)
200 {
201  base->CLRTEN |= mask;
202 }
203 
216 static inline bool LPIT_HAL_IsTimerChannelRunning(const LPIT_Type * base,
217  uint32_t channel)
218 {
219  return (((base->TMR[channel].TCTRL & LPIT_TMR_TCTRL_T_EN_MASK) >> \
221 }
222 
248 static inline void LPIT_HAL_SetTimerPeriodByCount(LPIT_Type * const base,
249  uint32_t channel,
250  uint32_t count)
251 {
252  base->TMR[channel].TVAL = count;
253 }
254 
265 static inline uint32_t LPIT_HAL_GetTimerPeriodByCount(const LPIT_Type * base,
266  uint32_t channel)
267 {
268  return (base->TMR[channel].TVAL);
269 }
270 
283 static inline uint32_t LPIT_HAL_GetCurrentTimerCount(const LPIT_Type * base,
284  uint32_t channel)
285 {
286  return (base->TMR[channel].CVAL);
287 }
288 
310 static inline void LPIT_HAL_EnableInterruptTimerChannels(LPIT_Type * const base,
311  uint32_t mask)
312 {
313  base->MIER |= mask;
314 }
315 
330 static inline void LPIT_HAL_DisableInterruptTimerChannels(LPIT_Type * const base,
331  uint32_t mask)
332 {
333  base->MIER &= ~mask;
334 }
335 
351 static inline uint32_t LPIT_HAL_GetInterruptFlagTimerChannels(const LPIT_Type * base,
352  uint32_t mask)
353 {
354  return (base->MSR) & mask;
355 }
356 
371 static inline void LPIT_HAL_ClearInterruptFlagTimerChannels(LPIT_Type * const base,
372  uint32_t mask)
373 {
374  /* Write 1 to clear the interrupt flag. */
375  base->MSR = mask;
376 #ifdef ERRATA_E9005
377  /* Read-after-write sequence to guarantee required serialization of memory operations */
378  base->MSR;
379 #endif
380 }
381 
400 static inline void LPIT_HAL_SetTimerChannelModeCmd(LPIT_Type * const base,
401  uint32_t channel,
402  lpit_timer_modes_t mode)
403 {
404  base->TMR[channel].TCTRL &= ~LPIT_TMR_TCTRL_MODE_MASK;
405  base->TMR[channel].TCTRL |= LPIT_TMR_TCTRL_MODE(mode);
406 }
407 
419  uint32_t channel)
420 {
421  uint32_t tmp;
422  lpit_timer_modes_t mode;
423 
424  tmp = (((base->TMR[channel].TCTRL) & LPIT_TMR_TCTRL_MODE_MASK)
426  switch (tmp)
427  {
428  case 0x00U:
429  mode = LPIT_PERIODIC_COUNTER;
430  break;
431  case 0x01U:
433  break;
434  case 0x02U:
436  break;
437  case 0x03U:
438  mode = LPIT_INPUT_CAPTURE;
439  break;
440  default:
441  mode = LPIT_PERIODIC_COUNTER;
442  break;
443  }
444  return mode;
445 }
446 
459 static inline void LPIT_HAL_SetTriggerSelectCmd(LPIT_Type * const base,
460  uint32_t channel,
461  uint32_t triggerChannelSelect)
462 {
463  base->TMR[channel].TCTRL &= ~LPIT_TMR_TCTRL_TRG_SEL_MASK;
464  base->TMR[channel].TCTRL |= LPIT_TMR_TCTRL_TRG_SEL(triggerChannelSelect);
465 }
466 
477 static inline void LPIT_HAL_SetTriggerSourceCmd(LPIT_Type * const base,
478  uint32_t channel,
479  lpit_trigger_source_t triggerSource)
480 {
481  base->TMR[channel].TCTRL &= ~LPIT_TMR_TCTRL_TRG_SRC_MASK;
482  base->TMR[channel].TCTRL |= LPIT_TMR_TCTRL_TRG_SRC(triggerSource);
483 }
484 
497 static inline void LPIT_HAL_SetReloadOnTriggerCmd(LPIT_Type * const base,
498  uint32_t channel,
499  bool isReloadOnTrigger)
500 {
501  base->TMR[channel].TCTRL &= ~LPIT_TMR_TCTRL_TROT_MASK;
502  base->TMR[channel].TCTRL |= LPIT_TMR_TCTRL_TROT(isReloadOnTrigger ? 1UL : 0UL);
503 }
504 
517 static inline void LPIT_HAL_SetStopOnInterruptCmd(LPIT_Type * const base,
518  uint32_t channel,
519  bool isStopOnInterrupt)
520 {
521  base->TMR[channel].TCTRL &= ~LPIT_TMR_TCTRL_TSOI_MASK;
522  base->TMR[channel].TCTRL |= LPIT_TMR_TCTRL_TSOI(isStopOnInterrupt ? 1UL : 0UL);
523 }
524 
538 static inline void LPIT_HAL_SetStartOnTriggerCmd(LPIT_Type * const base,
539  uint32_t channel,
540  bool isStartOnTrigger)
541 {
542  base->TMR[channel].TCTRL &= ~LPIT_TMR_TCTRL_TSOT_MASK;
543  base->TMR[channel].TCTRL |= LPIT_TMR_TCTRL_TSOT(isStartOnTrigger ? 1UL : 0UL);
544 }
545 
558 static inline void LPIT_HAL_SetTimerChannelChainCmd(LPIT_Type * const base,
559  uint32_t channel,
560  bool isChannelChained)
561 {
562  base->TMR[channel].TCTRL &= ~LPIT_TMR_TCTRL_CHAIN_MASK;
563  base->TMR[channel].TCTRL |= LPIT_TMR_TCTRL_CHAIN(isChannelChained ? 1UL : 0UL);
564 }
565 
580 static inline void LPIT_HAL_SetTimerRunInDebugCmd(LPIT_Type * const base,
581  bool isRunInDebug)
582 {
583  base->MCR &= ~LPIT_MCR_DBG_EN_MASK;
584  base->MCR |= LPIT_MCR_DBG_EN(isRunInDebug ? 1UL: 0UL);
585 }
586 
600 static inline void LPIT_HAL_SetTimerRunInDozeCmd(LPIT_Type * const base,
601  bool isRunInDoze)
602 {
603  base->MCR &= ~LPIT_MCR_DOZE_EN_MASK;
604  base->MCR |= LPIT_MCR_DOZE_EN(isRunInDoze ? 1UL : 0UL);
605 }
606 
609 #if defined(__cplusplus)
610 }
611 #endif
612 
615 #endif /* LPIT_HAL_H*/
616 /*******************************************************************************
617  * EOF
618  *******************************************************************************/
#define LPIT_MCR_DBG_EN_MASK
Definition: S32K144.h:6029
#define LPIT_MCR_DOZE_EN_MASK
Definition: S32K144.h:6025
__IO uint32_t SETTEN
Definition: S32K144.h:5954
static void LPIT_HAL_SetStartOnTriggerCmd(LPIT_Type *const base, uint32_t channel, bool isStartOnTrigger)
Sets timer channel start on trigger.
Definition: lpit_hal.h:538
static void LPIT_HAL_SetStopOnInterruptCmd(LPIT_Type *const base, uint32_t channel, bool isStopOnInterrupt)
Sets timer channel stop on interrupt.
Definition: lpit_hal.h:517
#define LPIT_TMR_TCTRL_TROT(x)
Definition: S32K144.h:6135
#define LPIT_TMR_TCTRL_CHAIN_MASK
Definition: S32K144.h:6116
Hardware information of LPIT module Implements : lpit_module_information_t_Class. ...
Definition: lpit_hal.h:43
lpit_timer_modes_t
Mode options available for the LPIT timer Implements : lpit_timer_modes_t_Class.
Definition: lpit_hal.h:60
#define LPIT_MCR_M_CEN_MASK
Definition: S32K144.h:6017
static void LPIT_HAL_SetReloadOnTriggerCmd(LPIT_Type *const base, uint32_t channel, bool isReloadOnTrigger)
Sets timer channel reload on trigger.
Definition: lpit_hal.h:497
static void LPIT_HAL_SetTimerChannelModeCmd(LPIT_Type *const base, uint32_t channel, lpit_timer_modes_t mode)
Sets operation mode of timer channel.
Definition: lpit_hal.h:400
static uint32_t LPIT_HAL_GetInterruptFlagTimerChannels(const LPIT_Type *base, uint32_t mask)
Gets the interrupt flag of timer channels.
Definition: lpit_hal.h:351
static void LPIT_HAL_SetTriggerSourceCmd(LPIT_Type *const base, uint32_t channel, lpit_trigger_source_t triggerSource)
Sets trigger source of timer channel.
Definition: lpit_hal.h:477
#define LPIT_TMR_TCTRL_TSOI_MASK
Definition: S32K144.h:6128
#define LPIT_TMR_TCTRL_MODE(x)
Definition: S32K144.h:6123
static void LPIT_HAL_EnableInterruptTimerChannels(LPIT_Type *const base, uint32_t mask)
Enables the interrupt generation for timer channels.
Definition: lpit_hal.h:310
#define LPIT_MCR_SW_RST_MASK
Definition: S32K144.h:6021
static void LPIT_HAL_SetTimerRunInDebugCmd(LPIT_Type *const base, bool isRunInDebug)
Sets operation of LPIT in debug mode.
Definition: lpit_hal.h:580
#define LPIT_MCR_DOZE_EN(x)
Definition: S32K144.h:6028
static void LPIT_HAL_DisableInterruptTimerChannels(LPIT_Type *const base, uint32_t mask)
Disables the interrupt generation for timer channels.
Definition: lpit_hal.h:330
__IO uint32_t TVAL
Definition: S32K144.h:5958
#define LPIT_TMR_TCTRL_T_EN_MASK
Definition: S32K144.h:6112
#define LPIT_TMR_TCTRL_CHAIN(x)
Definition: S32K144.h:6119
uint32_t numberOfExternalTriggerInputs
Definition: lpit_hal.h:48
static uint32_t LPIT_HAL_GetCurrentTimerCount(const LPIT_Type *base, uint32_t channel)
Gets the current timer channel counting value.
Definition: lpit_hal.h:283
static void LPIT_HAL_StopTimerChannels(LPIT_Type *const base, uint32_t mask)
Stops the timer channel from counting.
Definition: lpit_hal.h:198
__I uint32_t CVAL
Definition: S32K144.h:5959
#define LPIT_TMR_TCTRL_MODE_SHIFT
Definition: S32K144.h:6121
static void LPIT_HAL_SetTriggerSelectCmd(LPIT_Type *const base, uint32_t channel, uint32_t triggerChannelSelect)
Sets internal trigger source for timer channel.
Definition: lpit_hal.h:459
#define LPIT_TMR_TCTRL_TRG_SRC(x)
Definition: S32K144.h:6139
#define LPIT_TMR_TCTRL_T_EN_SHIFT
Definition: S32K144.h:6113
__IO uint32_t MIER
Definition: S32K144.h:5953
#define LPIT_MCR_DBG_EN(x)
Definition: S32K144.h:6032
static void LPIT_HAL_SetTimerChannelChainCmd(LPIT_Type *const base, uint32_t channel, bool isChannelChained)
Sets timer channel chaining.
Definition: lpit_hal.h:558
#define LPIT_TMR_TCTRL_TRG_SEL_MASK
Definition: S32K144.h:6140
#define LPIT_TMR_TCTRL_TRG_SRC_MASK
Definition: S32K144.h:6136
static void LPIT_HAL_Enable(LPIT_Type *const base)
Enables the LPIT module.
Definition: lpit_hal.h:118
#define LPIT_TMR_TCTRL_TSOT_MASK
Definition: S32K144.h:6124
uint32_t majorVersionNumber
Definition: lpit_hal.h:45
void LPIT_HAL_GetModuleInformation(const LPIT_Type *base, lpit_module_information_t *moduleInfomation)
Gets the information of LPIT module.
Definition: lpit_hal.c:42
lpit_trigger_source_t
Trigger source options.
Definition: lpit_hal.h:75
__IO uint32_t MCR
Definition: S32K144.h:5951
static void LPIT_HAL_Disable(LPIT_Type *const base)
Disables the LPIT module.
Definition: lpit_hal.h:132
static uint32_t LPIT_HAL_GetTimerPeriodByCount(const LPIT_Type *base, uint32_t channel)
Gets the timer channel period in count unit.
Definition: lpit_hal.h:265
__IO uint32_t CLRTEN
Definition: S32K144.h:5955
#define LPIT_TMR_TCTRL_TROT_MASK
Definition: S32K144.h:6132
#define LPIT_TMR_TCTRL_TSOT(x)
Definition: S32K144.h:6127
#define LPIT_TMR_TCTRL_MODE_MASK
Definition: S32K144.h:6120
__IO uint32_t MSR
Definition: S32K144.h:5952
static void LPIT_HAL_SetTimerRunInDozeCmd(LPIT_Type *const base, bool isRunInDoze)
Sets operation of LPIT in DOZE mode.
Definition: lpit_hal.h:600
#define LPIT_TMR_TCTRL_TRG_SEL(x)
Definition: S32K144.h:6143
static void LPIT_HAL_ClearInterruptFlagTimerChannels(LPIT_Type *const base, uint32_t mask)
Clears the interrupt flag of timer channels.
Definition: lpit_hal.h:371
static void LPIT_HAL_StartTimerChannels(LPIT_Type *const base, uint32_t mask)
Starts the timer channel counting.
Definition: lpit_hal.h:175
static void LPIT_HAL_Reset(LPIT_Type *const base)
Resets the LPIT module.
Definition: lpit_hal.h:146
uint32_t numberOfTimerChannels
Definition: lpit_hal.h:49
uint32_t minorVersionNumber
Definition: lpit_hal.h:46
static lpit_timer_modes_t LPIT_HAL_GetTimerChannelModeCmd(const LPIT_Type *base, uint32_t channel)
Gets current operation mode of timer channel.
Definition: lpit_hal.h:418
static void LPIT_HAL_SetTimerPeriodByCount(LPIT_Type *const base, uint32_t channel, uint32_t count)
Sets the timer channel period in count unit.
Definition: lpit_hal.h:248
#define LPIT_TMR_TCTRL_TSOI(x)
Definition: S32K144.h:6131
static bool LPIT_HAL_IsTimerChannelRunning(const LPIT_Type *base, uint32_t channel)
Checks timer channel operation status.
Definition: lpit_hal.h:216
struct LPIT_Type::@13 TMR[LPIT_TMR_COUNT]
__IO uint32_t TCTRL
Definition: S32K144.h:5960