S32 SDK
ftm_hal.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016 -2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
44 #ifndef FTM_HAL_H
45 #define FTM_HAL_H
46 
47 #include <stdbool.h>
48 #include <stddef.h>
49 #include "device_registers.h"
50 
61 /*
62  * S32K144 FTM
63  *
64  * FlexTimer Module
65  *
66  * Registers defined in this header file:
67  * - FTM_SC - Status And Control
68  * - FTM_CNT - Counter
69  * - FTM_MOD - Modulo
70  * - FTM_C0SC - Channel (n) Status And Control
71  * - FTM_C0V - Channel (n) Value
72  * - FTM_C1SC - Channel (n) Status And Control
73  * - FTM_C1V - Channel (n) Value
74  * - FTM_C2SC - Channel (n) Status And Control
75  * - FTM_C2V - Channel (n) Value
76  * - FTM_C3SC - Channel (n) Status And Control
77  * - FTM_C3V - Channel (n) Value
78  * - FTM_C4SC - Channel (n) Status And Control
79  * - FTM_C4V - Channel (n) Value
80  * - FTM_C5SC - Channel (n) Status And Control
81  * - FTM_C5V - Channel (n) Value
82  * - FTM_C6SC - Channel (n) Status And Control
83  * - FTM_C6V - Channel (n) Value
84  * - FTM_C7SC - Channel (n) Status And Control
85  * - FTM_C7V - Channel (n) Value
86  * - FTM_CNTIN - Counter Initial Value
87  * - FTM_STATUS - Capture And Compare Status
88  * - FTM_MODE - Features Mode Selection
89  * - FTM_SYNC - Synchronization
90  * - FTM_OUTINIT - Initial State For Channels Output
91  * - FTM_OUTMASK - Output Mask
92  * - FTM_COMBINE - Function For Linked Channels
93  * - FTM_DEADTIME - Dead-time Insertion Control
94  * - FTM_EXTTRIG - FTM External Trigger
95  * - FTM_POL - Channels Polarity
96  * - FTM_FMS - Fault Mode Status
97  * - FTM_FILTER - Input Capture Filter Control
98  * - FTM_FLTCTRL - Fault Control
99  * - FTM_QDCTRL - Quadrature Decoder Control And Status
100  * - FTM_CONF - Configuration
101  * - FTM_FLTPOL - FTM Fault Input Polarity
102  * - FTM_SYNCONF - Synchronization Configuration
103  * - FTM_INVCTRL - FTM Inverting Control
104  * - FTM_SWOCTRL - FTM Software Output Control
105  * - FTM_PWMLOAD - FTM PWM Load
106  * - FTM_HCR - Half Cycle Register
107  */
108 
109 /*******************************************************************************
110  * Definitions
111  ******************************************************************************/
112 
118 #define FTM0_IDX (0U)
119 
120 #define FTM1_IDX (1U)
121 
122 #define FTM2_IDX (2U)
123 
124 #define FTM3_IDX (3U)
125 
130 #define FTM_RMW_SC(base, mask, value) (((base)->SC) = ((((base)->SC) & ~(mask)) | (value)))
131 
135 #define FTM_RMW_CNT(base, mask, value) (((base)->CNT) = ((((base)->CNT) & ~(mask)) | (value)))
136 
140 #define FTM_RMW_MOD(base, mask, value) (((base)->MOD) = ((((base)->MOD) & ~(mask)) | (value)))
141 
145 #define FTM_RMW_CNTIN(base, mask, value) (((base)->CNTIN) = ((((base)->CNTIN) & ~(mask)) | (value)))
146 
150 #define FTM_RMW_STATUS(base, mask, value) (((base)->STATUS) = ((((base)->STATUS) & ~(mask)) | (value)))
151 
155 #define FTM_RMW_MODE(base, mask, value) (((base)->MODE) = ((((base)->MODE) & ~(mask)) | (value)))
156 
160 #define FTM_RMW_CnSCV_REG(base, channel, mask, value) (((base)->CONTROLS[channel].CnSC) = ((((base)->CONTROLS[channel].CnSC) & ~(mask)) | (value)))
161 
165 #define FTM_RMW_DEADTIME(base, mask, value) (((base)->DEADTIME) = ((((base)->DEADTIME) & ~(mask)) | (value)))
166 
169 #define FTM_RMW_EXTTRIG_REG(base, mask, value) (((base)->EXTTRIG) = ((((base)->EXTTRIG) & ~(mask)) | (value)))
170 
174 #define FTM_RMW_FLTCTRL(base, mask, value) (((base)->FLTCTRL) = ((((base)->FLTCTRL) & ~(mask)) | (value)))
175 
179 #define FTM_RMW_FMS(base, mask, value) (((base)->FMS) = ((((base)->FMS) & ~(mask)) | (value)))
180 
184 #define FTM_RMW_CONF(base, mask, value) (((base)->CONF) = ((((base)->CONF) & ~(mask)) | (value)))
185 
189 #define FTM_RMW_POL(base, mask, value) (((base)->POL) = ((((base)->POL) & ~(mask)) | (value)))
190 
194 #define FTM_RMW_FILTER(base, mask, value) (((base)->FILTER) = ((((base)->FILTER) & ~(mask)) | (value)))
195 
199 #define FTM_RMW_SYNC(base, mask, value) (((base)->SYNC) = ((((base)->SYNC) & ~(mask)) | (value)))
200 
204 #define FTM_RMW_QDCTRL(base, mask, value) (((base)->QDCTRL) = ((((base)->QDCTRL) & ~(mask)) | (value)))
205 
209 #define FTM_RMW_PAIR0DEADTIME(base, mask, value) (((base)->PAIR0DEADTIME) = ((((base)->PAIR0DEADTIME) & ~(mask)) | (value)))
210 
214 #define FTM_RMW_PAIR1DEADTIME(base, mask, value) (((base)->PAIR1DEADTIME) = ((((base)->PAIR1DEADTIME) & ~(mask)) | (value)))
215 
219 #define FTM_RMW_PAIR2DEADTIME(base, mask, value) (((base)->PAIR2DEADTIME) = ((((base)->PAIR2DEADTIME) & ~(mask)) | (value)))
220 
224 #define FTM_RMW_PAIR3DEADTIME(base, mask, value) (((base)->PAIR3DEADTIME) = ((((base)->PAIR3DEADTIME) & ~(mask)) | (value)))
225 
227 #define CHAN0_IDX (0U)
228 
229 #define CHAN1_IDX (1U)
230 
231 #define CHAN2_IDX (2U)
232 
233 #define CHAN3_IDX (3U)
234 
235 #define CHAN4_IDX (4U)
236 
237 #define CHAN5_IDX (5U)
238 
239 #define CHAN6_IDX (6U)
240 
241 #define CHAN7_IDX (7U)
242 
243 /*******************************************************************************
244  * Enumerations
245  ******************************************************************************/
246 
252 typedef enum
253 {
266 typedef enum
267 {
269  FTM_CLOCK_DIVID_BY_2 = 0x01U,
283 typedef enum
284 {
286  FTM_DEADTIME_DIVID_BY_4 = 0x02U,
295 typedef enum
296 {
298  FTM_POLARITY_HIGH = 0x01U
306 typedef enum
307 {
313 
319 typedef enum
320 {
322  FTM_QUAD_COUNT_AND_DIR = 0x01U
330 typedef enum
331 {
337 
343 typedef enum
344 {
345  FTM_BDM_MODE_00 = 0x00U,
348  FTM_BDM_MODE_01 = 0x01U,
351  FTM_BDM_MODE_10 = 0x02U,
354  FTM_BDM_MODE_11 = 0x03U
358 
364 typedef enum
365 {
370  FTM_FAULT_CONTROL_MAN_ALL = 0x02U,
375 
381 typedef enum
382 {
388 
394 typedef enum
395 {
397  FTM_UPDATE_NOW = 1U
400 /*******************************************************************************
401  * API
402  ******************************************************************************/
403 
404 #if defined(__cplusplus)
405 extern "C" {
406 #endif
407 
416 static inline void FTM_HAL_SetHalfCycleValue(FTM_Type * const ftmBase,
417  uint16_t value)
418 {
419  ((ftmBase)->HCR) = value;
420 }
421 
430 static inline void FTM_HAL_SetClockFilterPs(FTM_Type * const ftmBase,
431  uint8_t filterPrescale)
432 {
433  FTM_RMW_SC(ftmBase, FTM_SC_FLTPS_MASK, FTM_SC_FLTPS(filterPrescale));
434 }
435 
445 static inline uint8_t FTM_HAL_GetClockFilterPs(const FTM_Type * ftmBase)
446 {
447  return (uint8_t)((((ftmBase)->SC) & FTM_SC_FLTPS_MASK) >> FTM_SC_FLTPS_SHIFT);
448 }
449 
462 static inline void FTM_HAL_SetClockSource(FTM_Type * const ftmBase,
463  ftm_clock_source_t clock)
464 {
465  FTM_RMW_SC(ftmBase, FTM_SC_CLKS_MASK, FTM_SC_CLKS(clock));
466 }
467 
481 static inline uint8_t FTM_HAL_GetClockSource(const FTM_Type * ftmBase)
482 {
483  return (uint8_t)((((ftmBase)->SC) & FTM_SC_CLKS_MASK) >> FTM_SC_CLKS_SHIFT);
484 }
485 
494 static inline void FTM_HAL_SetClockPs(FTM_Type * const ftmBase,
495  ftm_clock_ps_t ps)
496 {
497  FTM_RMW_SC(ftmBase, FTM_SC_PS_MASK, FTM_SC_PS(ps));
498 }
499 
509 static inline uint8_t FTM_HAL_GetClockPs(const FTM_Type * ftmBase)
510 {
511  return (uint8_t)((((ftmBase)->SC) & FTM_SC_PS_MASK) >> FTM_SC_PS_SHIFT);
512 }
513 
523 static inline void FTM_HAL_SetTimerOverflowInt(FTM_Type * const ftmBase,
524  bool state)
525 {
526  FTM_RMW_SC(ftmBase, FTM_SC_TOIE_MASK, FTM_SC_TOIE(state));
527 }
528 
540 static inline bool FTM_HAL_IsOverflowIntEnabled(const FTM_Type * ftmBase)
541 {
542  return ((ftmBase->SC & FTM_SC_TOIE_MASK) >> FTM_SC_TOIE_SHIFT) != 0U;
543 }
544 
553 static inline void FTM_HAL_EnablePwmChannelOutputs(FTM_Type * const ftmBase,
554  uint8_t channel)
555 {
556  FTM_RMW_SC(ftmBase, (1UL << (channel + FTM_FEATURE_OUTPUT_CHANNEL_OFFSET)), (1UL << (channel + FTM_FEATURE_OUTPUT_CHANNEL_OFFSET)));
557 }
558 
567 static inline void FTM_HAL_DisablePwmChannelOutputs(FTM_Type * const ftmBase,
568  uint8_t channel)
569 {
570  uint32_t regValue = ((ftmBase)->SC);
571  regValue = regValue & (~(1UL << (channel + FTM_FEATURE_OUTPUT_CHANNEL_OFFSET)));
572  ((ftmBase)->SC) = (regValue);
573 }
574 
582 static inline void FTM_HAL_ClearTimerOverflow(FTM_Type * const ftmBase)
583 {
585 #ifdef ERRATA_E9005
586  /* Read-after-write sequence to guarantee required serialization of memory operations */
587  ftmBase->SC;
588 #endif
589 }
590 
602 static inline bool FTM_HAL_HasTimerOverflowed(const FTM_Type * ftmBase)
603 {
604  return ((ftmBase->SC & FTM_SC_TOF_MASK) >> FTM_SC_TOF_SHIFT) != 0U;
605 }
606 
617 static inline void FTM_HAL_SetCpwms(FTM_Type * const ftmBase,
618  bool mode)
619 {
620  FTM_RMW_SC(ftmBase, FTM_SC_CPWMS_MASK, FTM_SC_CPWMS(mode));
621 }
622 
634 static inline bool FTM_HAL_GetCpwms(const FTM_Type * ftmBase)
635 {
636  return ((ftmBase->SC & FTM_SC_CPWMS_MASK) >> FTM_SC_CPWMS_SHIFT) != 0U;
637 }
638 
648 static inline void FTM_HAL_SetReIntEnabledCmd(FTM_Type * const ftmBase,
649  bool enable)
650 {
651  FTM_RMW_SC(ftmBase, FTM_SC_RIE_MASK, FTM_SC_RIE(enable));
652 }
653 
665 static inline bool FTM_HAL_GetReloadFlag(const FTM_Type * ftmBase)
666 {
667  return ((ftmBase->SC & FTM_SC_RF_MASK) >> FTM_SC_RF_SHIFT) != 0U;
668 }
669 
677 static inline void FTM_HAL_ClearReloadFlag(FTM_Type * const ftmBase)
678 {
680 #ifdef ERRATA_E9005
681  /* Read-after-write sequence to guarantee required serialization of memory operations */
682  ftmBase->SC;
683 #endif
684 }
685 
694 static inline void FTM_HAL_SetCounter(FTM_Type * const ftmBase,
695  uint16_t value)
696 {
697  FTM_RMW_CNT(ftmBase, FTM_CNT_COUNT_MASK, FTM_CNT_COUNT(value));
698 }
699 
709 static inline uint16_t FTM_HAL_GetCounter(const FTM_Type * ftmBase)
710 {
711  return (uint16_t)((((ftmBase)->CNT) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT);
712 }
713 
722 static inline void FTM_HAL_SetMod(FTM_Type * const ftmBase,
723  uint16_t value)
724 {
725  FTM_RMW_MOD(ftmBase, FTM_MOD_MOD_MASK, FTM_MOD_MOD(value));
726 }
727 
737 static inline uint16_t FTM_HAL_GetMod(const FTM_Type * ftmBase)
738 {
739  return (uint16_t)((((ftmBase)->MOD) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT);
740 }
741 
750 static inline void FTM_HAL_SetCounterInitVal(FTM_Type * const ftmBase,
751  uint16_t value)
752 {
754 }
755 
765 static inline uint16_t FTM_HAL_GetCounterInitVal(const FTM_Type * ftmBase)
766 {
767  return (uint16_t)((((ftmBase)->CNTIN) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT);
768 }
769 
779 static inline void FTM_HAL_SetChnMSnBAMode(FTM_Type * const ftmBase,
780  uint8_t channel,
781  uint8_t selection)
782 {
784 
785  /* write MSA bit */
786  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_MSA_MASK, FTM_CnSC_MSA((uint32_t)selection & 0x01U));
787 
788  /* write MSB bit */
789  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_MSB_MASK, FTM_CnSC_MSB(((uint32_t)selection & 0x02U) >> 1U));
790 }
791 
801 static inline void FTM_HAL_SetChnEdgeLevel(FTM_Type * const ftmBase,
802  uint8_t channel,
803  uint8_t level)
804 {
806 
807  /* write MSA bit */
808  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_ELSA_MASK, FTM_CnSC_ELSA((uint32_t)level & 0x01U));
809 
810  /* write MSB bit */
811  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_ELSB_MASK, FTM_CnSC_ELSB(((uint32_t)level & 0x02U) >> 1U));
812 }
813 
822 static inline void FTM_HAL_ClearChSC(FTM_Type * const ftmBase,
823  uint8_t channel)
824 {
826 
827  ((ftmBase)->CONTROLS[channel].CnSC) = 0U;
828 #ifdef ERRATA_E9005
829  /* Read-after-write sequence to guarantee required serialization of memory operations */
830  ftmBase->CONTROLS[channel].CnSC;
831 #endif
832 }
833 
844 static inline uint8_t FTM_HAL_GetChnMode(const FTM_Type * ftmBase,
845  uint8_t channel)
846 {
848  uint8_t retValue;
849 
850  retValue = (uint8_t)((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_MSA_MASK) >> FTM_CnSC_MSA_SHIFT);
851 
852  retValue |= (uint8_t)(((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_MSB_MASK) >> FTM_CnSC_MSB_SHIFT) << 1U);
853 
854  return retValue;
855 }
856 
867 static inline uint8_t FTM_HAL_GetChnEdgeLevel(const FTM_Type * ftmBase,
868  uint8_t channel)
869 {
871  uint8_t retValue;
872 
873  retValue = (uint8_t)((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT);
874 
875  retValue |= (uint8_t)(((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT) << 1U);
876 
877  return retValue;
878 }
879 
891 static inline void FTM_HAL_SetChnIcrstCmd(FTM_Type * const ftmBase,
892  uint8_t channel,
893  bool enable)
894 {
896 
897  /* Write ICRST bit */
898  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_ICRST_MASK, FTM_CnSC_ICRST(enable));
899 }
900 
912 static inline bool FTM_HAL_IsChnIcrst(const FTM_Type * ftmBase,
913  uint8_t channel)
914 {
916 
917  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ICRST_MASK) != 0U;
918 }
919 
931 static inline void FTM_HAL_SetChnDmaCmd(FTM_Type * const ftmBase,
932  uint8_t channel,
933  bool enable)
934 {
936 
937  /* Write DMA bit */
938  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(enable));
939 }
940 
952 static inline bool FTM_HAL_IsChnDma(const FTM_Type * ftmBase,
953  uint8_t channel)
954 {
956 
957  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_DMA_MASK) != 0U;
958 }
959 
967 static inline bool FTM_HAL_IsChnIntEnabled(const FTM_Type * ftmBase,
968  uint8_t channel)
969 {
971 
972  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHIE_MASK) != 0U;
973 }
974 
983 static inline void FTM_HAL_EnableChnInt(FTM_Type * const ftmBase,
984  uint8_t channel)
985 {
987 
988  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_CHIE_MASK, FTM_CnSC_CHIE(1U));
989 }
990 
999 static inline void FTM_HAL_DisableChnInt(FTM_Type * const ftmBase,
1000  uint8_t channel)
1003 
1004  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_CHIE_MASK, FTM_CnSC_CHIE(0U));
1005 }
1006 
1019 static inline bool FTM_HAL_HasChnEventOccurred(const FTM_Type * ftmBase,
1020  uint8_t channel)
1023 
1024  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHF_MASK) != 0U;
1025 }
1026 
1035 static inline void FTM_HAL_ClearChnEventFlag(FTM_Type * const ftmBase,
1036  uint8_t channel)
1039 
1040  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_CHF_MASK, FTM_CnSC_CHF(0U));
1041 #ifdef ERRATA_E9005
1042  /* Read-after-write sequence to guarantee required serialization of memory operations */
1043  ftmBase->CONTROLS[channel].CnSC;
1044 #endif
1045 }
1046 
1058 static inline void FTM_HAL_SetTrigModeControlCmd(FTM_Type * const ftmBase,
1059  uint8_t channel,
1060  bool enable)
1061 {
1063 
1064  /* Write TRIGMODE bit */
1065  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_TRIGMODE_MASK, FTM_CnSC_TRIGMODE((enable)));
1066 }
1067 
1079 static inline bool FTM_HAL_GetTriggerControled(const FTM_Type * ftmBase,
1080  uint8_t channel)
1083 
1084  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_TRIGMODE_MASK) != 0U;
1085 }
1086 
1098 static inline bool FTM_HAL_GetChInputState(const FTM_Type * ftmBase,
1099  uint8_t channel)
1102 
1103  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHIS_MASK) != 0U;
1104 }
1105 
1117 static inline bool FTM_HAL_GetChOutputValue(const FTM_Type * ftmBase,
1118  uint8_t channel)
1121 
1122  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHOV_MASK) != 0U;
1123 }
1124 
1125 /*FTM channel control*/
1135 static inline void FTM_HAL_SetChnCountVal(FTM_Type * const ftmBase,
1136  uint8_t channel,
1137  uint16_t value)
1138 {
1140 
1141  ((ftmBase)->CONTROLS[channel].CnV) = value;
1142 }
1143 
1154 static inline uint16_t FTM_HAL_GetChnCountVal(const FTM_Type * ftmBase,
1155  uint8_t channel)
1158 
1159  return (uint16_t)((ftmBase)->CONTROLS[channel].CnV);
1160 }
1161 
1174 static inline bool FTM_HAL_GetChnEventStatus(const FTM_Type * ftmBase,
1175  uint8_t channel)
1178 
1179  return (((ftmBase)->STATUS) & (1UL << channel)) != 0U;
1180 }
1181 
1191 static inline uint32_t FTM_HAL_GetEventStatus(const FTM_Type * ftmBase)
1192 {
1193  return ((ftmBase)->STATUS) & (0xFFU);
1194 }
1195 
1204 static inline void FTM_HAL_ClearChnEventStatus(FTM_Type * const ftmBase,
1205  uint8_t channel)
1208 
1209  ((ftmBase)->STATUS) &= (~(1UL << channel));
1210 #ifdef ERRATA_E9005
1211  /* Read-after-write sequence to guarantee required serialization of memory operations */
1212  ftmBase->STATUS;
1213 #endif
1214 }
1215 
1226 static inline void FTM_HAL_SetOutmaskReg(FTM_Type * const ftmBase,
1227  uint32_t regVal)
1229  ((ftmBase)->OUTMASK) = regVal;
1230 }
1231 
1243 static inline void FTM_HAL_SetChnOutputMask(FTM_Type * const ftmBase,
1244  uint8_t channel,
1245  bool mask)
1246 {
1248 
1249  if (mask)
1250  {
1251  ((ftmBase)->OUTMASK) |= (1UL << channel);
1252  }
1253  else
1254  {
1255  ((ftmBase)->OUTMASK) &= ~(1UL << channel);
1256  }
1257 }
1258 
1270 static inline void FTM_HAL_SetChnOutputInitStateCmd(FTM_Type * const ftmBase,
1271  uint8_t channel,
1272  bool state)
1273 {
1275 
1276  if (state)
1277  {
1278  ((ftmBase)->OUTINIT) |= (1UL << channel);
1279  }
1280  else
1281  {
1282  ((ftmBase)->OUTINIT) &= ~(1UL << channel);
1283  }
1284 }
1285 
1297 static inline void FTM_HAL_SetChnOutputPolarityCmd(FTM_Type * const ftmBase,
1298  uint8_t channel,
1299  ftm_polarity_t polarity)
1300 {
1302 
1303  if (FTM_POLARITY_HIGH == polarity)
1304  {
1305  ((ftmBase)->POL) &= ~(1UL << channel);
1306  }
1307  else
1308  {
1309  ((ftmBase)->POL) |= (1UL << channel);
1310  }
1311 }
1312 
1324 static inline void FTM_HAL_SetChnFaultInputPolarityCmd(FTM_Type * const ftmBase,
1325  uint8_t fltChannel,
1326  ftm_polarity_t polarity)
1327 {
1328  DEV_ASSERT(fltChannel < FTM_FEATURE_FAULT_CHANNELS);
1329 
1330  if (FTM_POLARITY_HIGH == polarity)
1331  {
1332  ((ftmBase)->FLTPOL) &= ~(1UL << fltChannel);
1333  }
1334  else
1335  {
1336  ((ftmBase)->FLTPOL) |= (1UL << fltChannel);
1337  }
1338 }
1339 
1350 static inline void FTM_HAL_SetFaultInt(FTM_Type * const ftmBase,
1351  bool state)
1354 }
1355 
1363 static inline void FTM_HAL_DisableFaultInt(FTM_Type * const ftmBase)
1364 {
1366 }
1367 
1375 static inline bool FTM_HAL_IsFaultIntEnabled(const FTM_Type * ftmBase)
1376 {
1377  return ((ftmBase->MODE & FTM_MODE_FAULTIE_MASK) >> FTM_MODE_FAULTIE_SHIFT) != 0U;
1378 }
1379 
1387 static inline void FTM_HAL_ClearFaultsIsr(FTM_Type * const ftmBase)
1388 {
1393 #ifdef ERRATA_E9005
1394  /* Read-after-write sequence to guarantee required serialization of memory operations */
1395  ftmBase->FMS;
1396 #endif
1397 }
1398 
1411 static inline void FTM_HAL_SetFaultControlMode(FTM_Type * const ftmBase,
1412  ftm_fault_mode_t mode)
1414  FTM_RMW_MODE(ftmBase, FTM_MODE_FAULTM_MASK, FTM_MODE_FAULTM((uint32_t)mode));
1415 }
1416 
1427 static inline void FTM_HAL_SetCaptureTestCmd(FTM_Type * const ftmBase,
1428  bool enable)
1431 }
1432 
1443 static inline void FTM_HAL_SetWriteProtectionCmd(FTM_Type * const ftmBase,
1444  bool enable)
1446  if (enable)
1447  {
1448  ftmBase->FMS = (ftmBase->FMS & ~FTM_FMS_WPEN_MASK) | FTM_FMS_WPEN(1U);
1449  }
1450  else
1451  {
1452  ftmBase->MODE = (ftmBase->MODE & ~FTM_MODE_WPDIS_MASK) | FTM_MODE_WPDIS(1U);
1453  }
1454 }
1455 
1466 static inline void FTM_HAL_Enable(FTM_Type * const ftmBase,
1467  bool enable)
1469  FTM_RMW_MODE(ftmBase, FTM_MODE_FTMEN_MASK, FTM_MODE_FTMEN(enable));
1470 }
1471 
1482 static inline bool FTM_HAL_IsFtmEnable(const FTM_Type * ftmBase)
1483 {
1484  return ((ftmBase->MODE & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT) != 0U;
1485 }
1486 
1497 static inline void FTM_HAL_SetInitChnOutputCmd(FTM_Type * const ftmBase,
1498  bool enable)
1500  FTM_RMW_MODE(ftmBase, FTM_MODE_INIT_MASK, FTM_MODE_INIT(enable));
1501 }
1502 
1514 static inline void FTM_HAL_SetPwmSyncMode(FTM_Type * const ftmBase,
1515  bool enable)
1518 }
1519 
1530 static inline void FTM_HAL_SetSoftwareTriggerCmd(FTM_Type * const ftmBase,
1531  bool enable)
1534 }
1535 
1550 static inline void FTM_HAL_SetHardwareSyncTriggerSrc(FTM_Type * const ftmBase,
1551  uint8_t trigger_num,
1552  bool enable)
1553 {
1554  DEV_ASSERT(trigger_num < 3U);
1555 
1556  if (enable)
1557  {
1558  ((ftmBase)->SYNC) |= ((uint32_t)(FTM_SYNC_TRIG0_MASK) << trigger_num);
1559  }
1560  else
1561  {
1562  ((ftmBase)->SYNC) &= ~((uint32_t)(FTM_SYNC_TRIG0_MASK) << trigger_num);
1563  }
1564 }
1565 
1576 static inline void FTM_HAL_SetOutmaskPwmSyncModeCmd(FTM_Type * const ftmBase,
1577  bool enable)
1580 }
1581 
1593 static inline void FTM_HAL_SetCountReinitSyncCmd(FTM_Type * const ftmBase,
1594  bool enable)
1597 }
1598 
1609 static inline void FTM_HAL_SetMaxLoadingCmd(FTM_Type * const ftmBase,
1610  bool enable)
1613 }
1614 
1625 static inline void FTM_HAL_SetMinLoadingCmd(FTM_Type * const ftmBase,
1626  bool enable)
1629 }
1630 
1642 static inline void FTM_HAL_SetDualChnMofCombineCmd(FTM_Type * const ftmBase,
1643  uint8_t chnlPairNum,
1644  bool enable)
1645 {
1646  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1647 
1648  if (enable)
1649  {
1650  ((ftmBase)->COMBINE) |= ((uint32_t)FTM_COMBINE_MCOMBINE0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1651  }
1652  else
1653  {
1654  ((ftmBase)->COMBINE) &= ~((uint32_t)FTM_COMBINE_MCOMBINE0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1655  }
1656 }
1657 
1669 static inline void FTM_HAL_SetDualChnFaultCmd(FTM_Type * const ftmBase,
1670  uint8_t chnlPairNum,
1671  bool enable)
1672 {
1673  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1674 
1675  if (enable)
1676  {
1677  ((ftmBase)->COMBINE) |= ((uint32_t)FTM_COMBINE_FAULTEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1678  }
1679  else
1680  {
1681  ((ftmBase)->COMBINE) &= ~((uint32_t)FTM_COMBINE_FAULTEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1682  }
1683 }
1684 
1696 static inline void FTM_HAL_SetDualChnPwmSyncCmd(FTM_Type * const ftmBase,
1697  uint8_t chnlPairNum,
1698  bool enable)
1699 {
1700  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1701 
1702  if (enable)
1703  {
1704  ((ftmBase)->COMBINE) |= ((uint32_t)FTM_COMBINE_SYNCEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1705  }
1706  else
1707  {
1708  ((ftmBase)->COMBINE) &= ~((uint32_t)FTM_COMBINE_SYNCEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1709  }
1710 }
1711 
1723 static inline void FTM_HAL_SetDualChnDeadtimeCmd(FTM_Type * const ftmBase,
1724  uint8_t chnlPairNum,
1725  bool enable)
1726 {
1727  DEV_ASSERT(chnlPairNum < FEATURE_FTM_CHANNEL_COUNT);
1728 
1729  if (enable)
1730  {
1731  ((ftmBase)->COMBINE) |= ((uint32_t)FTM_COMBINE_DTEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1732  }
1733  else
1734  {
1735  ((ftmBase)->COMBINE) &= ~((uint32_t)FTM_COMBINE_DTEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1736  }
1737 }
1738 
1750 static inline void FTM_HAL_SetDualChnDecapCmd(FTM_Type * const ftmBase,
1751  uint8_t chnlPairNum,
1752  bool enable)
1753 {
1754  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1755 
1756  if (enable)
1757  {
1758  ((ftmBase)->COMBINE) |= ((uint32_t)FTM_COMBINE_DECAP0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1759  }
1760  else
1761  {
1762  ((ftmBase)->COMBINE) &= ~((uint32_t)FTM_COMBINE_DECAP0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1763  }
1764 }
1765 
1777 static inline void FTM_HAL_SetDualEdgeCaptureCmd(FTM_Type * const ftmBase,
1778  uint8_t chnlPairNum,
1779  bool enable)
1780 {
1781  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1782 
1783  if (enable)
1784  {
1785  ((ftmBase)->COMBINE) |= ((uint32_t)FTM_COMBINE_DECAPEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1786  }
1787  else
1788  {
1789  ((ftmBase)->COMBINE) &= ~((uint32_t)FTM_COMBINE_DECAPEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1790  }
1791 }
1792 
1805 static inline bool FTM_HAL_GetDualEdgeCaptureBit(const FTM_Type * ftmBase,
1806  uint8_t chnlPairNum)
1808  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1809 
1810  return (((ftmBase)->COMBINE) & ((uint32_t)FTM_COMBINE_DECAPEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH))) != 0U;
1811 }
1812 
1824 static inline void FTM_HAL_SetDualChnCompCmd(FTM_Type * const ftmBase,
1825  uint8_t chnlPairNum,
1827 {
1828  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1829 
1830  if (polarity == FTM_MAIN_INVERTED)
1831  {
1832  ((ftmBase)->COMBINE) |= (FTM_COMBINE_COMP0_MASK << ((uint32_t)(chnlPairNum) * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1833  }
1834  else
1835  {
1836  ((ftmBase)->COMBINE) &= ~(FTM_COMBINE_COMP0_MASK << ((uint32_t)(chnlPairNum) * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1837  }
1838 }
1839 
1851 static inline void FTM_HAL_SetDualChnCombineCmd(FTM_Type * const ftmBase,
1852  uint8_t chnlPairNum,
1853  bool enable)
1854 {
1855  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1856 
1857  if (enable)
1858  {
1859  ((ftmBase)->COMBINE) |= (FTM_COMBINE_COMBINE0_MASK << ((uint32_t)(chnlPairNum) * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1860  }
1861  else
1862  {
1863  ((ftmBase)->COMBINE) &= ~(FTM_COMBINE_COMBINE0_MASK << ((uint32_t)(chnlPairNum) * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH));
1864  }
1865 }
1866 
1879 static inline bool FTM_HAL_GetDualChnCombineCmd(const FTM_Type * ftmBase,
1880  uint8_t chnlPairNum)
1882  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1883 
1884  return (((ftmBase)->COMBINE) & (FTM_COMBINE_COMBINE0_MASK << ((uint32_t)(chnlPairNum) * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH))) != 0U;
1885 }
1886 
1899 static inline bool FTM_HAL_GetDualChnMofCombineCmd(const FTM_Type * ftmBase,
1900  uint8_t chnlPairNum)
1902  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1903 
1904  return (((ftmBase)->COMBINE) & (FTM_COMBINE_MCOMBINE0_MASK << ((uint32_t)(chnlPairNum) * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH))) != 0U;
1905 }
1914 static inline void FTM_HAL_SetExtDeadtimeValue(FTM_Type * const ftmBase,
1915  uint8_t value)
1917  DEV_ASSERT(value < 16U);
1918 
1920 }
1921 
1933 static inline void FTM_HAL_SetDeadtimePrescale(FTM_Type * const ftmBase,
1934  ftm_deadtime_ps_t divider)
1936  FTM_RMW_DEADTIME(ftmBase, FTM_DEADTIME_DTPS_MASK, FTM_DEADTIME_DTPS((uint8_t)divider));
1937 }
1938 
1951 static inline void FTM_HAL_SetDeadtimeCount(FTM_Type * const ftmBase,
1952  uint8_t count)
1954  DEV_ASSERT(count < 64U);
1955 
1957 }
1958 
1959 /*FTM external trigger */
1971 static inline void FTM_HAL_SetInitTriggerCmd(FTM_Type * const ftmBase,
1972  bool enable)
1974  ftmBase->EXTTRIG = (ftmBase->EXTTRIG & ~FTM_EXTTRIG_INITTRIGEN_MASK) | FTM_EXTTRIG_INITTRIGEN(enable);
1975 }
1976 
1987 static inline bool FTM_HAL_IsChnTriggerGenerated(const FTM_Type * ftmBase)
1988 {
1989  return (ftmBase->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK) != 0U;
1990 }
1991 
1999 static inline void FTM_HAL_ClearChnTriggerFlag(FTM_Type * const ftmBase)
2000 {
2002 }
2003 
2004 /*Fault mode status*/
2018 static inline bool FTM_HAL_GetDetectedFaultInput(const FTM_Type * ftmBase)
2019 {
2020  return (ftmBase->FMS & FTM_FMS_FAULTF_MASK) != 0U;
2021 }
2022 
2034 static inline bool FTM_HAL_IsWriteProtectionEnabled(const FTM_Type * ftmBase)
2035 {
2036  return (ftmBase->FMS & FTM_FMS_WPEN_MASK) != 0U;
2037 }
2038 
2050 static inline bool FTM_HAL_IsFaultInputEnabled(const FTM_Type * ftmBase)
2051 {
2052  return (ftmBase->FMS & FTM_FMS_FAULTIN_MASK) != 0U;
2053 }
2054 
2067 static inline bool FTM_HAL_IsFaultFlagDetected(const FTM_Type * ftmBase,
2068  uint8_t channel)
2070  DEV_ASSERT(channel < CHAN4_IDX);
2071 
2072  return (ftmBase->FMS & (FTM_FMS_FAULTF0_MASK << channel)) != 0U;
2073 }
2074 
2083 static inline void FTM_HAL_ClearFaultFlagDetected(FTM_Type * const ftmBase,
2084  uint8_t channel)
2086  DEV_ASSERT(channel < CHAN4_IDX);
2087 
2088  ((ftmBase)->FMS) &= (~(1UL << channel));
2089 #ifdef ERRATA_E9005
2090  /* Read-after-write sequence to guarantee required serialization of memory operations */
2091  ftmBase->FMS;
2092 #endif
2093 }
2094 
2095 /* Quadrature decoder control */
2106 static inline void FTM_HAL_SetQuadDecoderCmd(FTM_Type * const ftmBase,
2107  bool enable)
2109  if (enable)
2110  {
2111  ((ftmBase)->QDCTRL) |= (1UL << FTM_QDCTRL_QUADEN_SHIFT);
2112  }
2113  else
2114  {
2115  ((ftmBase)->QDCTRL) &= ~(1UL << FTM_QDCTRL_QUADEN_SHIFT);
2116  }
2117 }
2118 
2129 static inline void FTM_HAL_SetQuadPhaseAFilterCmd(FTM_Type * const ftmBase,
2130  bool enable)
2132  if (enable)
2133  {
2134  ((ftmBase)->QDCTRL) |= (1UL << FTM_QDCTRL_PHAFLTREN_SHIFT);
2135  }
2136  else
2137  {
2138  ((ftmBase)->QDCTRL) &= ~(1UL << FTM_QDCTRL_PHAFLTREN_SHIFT);
2139  }
2140 }
2141 
2152 static inline void FTM_HAL_SetQuadPhaseBFilterCmd(FTM_Type * const ftmBase,
2153  bool enable)
2155  if (enable)
2156  {
2157  ((ftmBase)->QDCTRL) |= (1UL << FTM_QDCTRL_PHBFLTREN_SHIFT);
2158  }
2159  else
2160  {
2161  ((ftmBase)->QDCTRL) &= ~(1UL << FTM_QDCTRL_PHBFLTREN_SHIFT);
2162  }
2163 }
2164 
2175 static inline void FTM_HAL_SetQuadPhaseAPolarity(FTM_Type * const ftmBase,
2179 }
2180 
2191 static inline void FTM_HAL_SetQuadPhaseBPolarity(FTM_Type * const ftmBase,
2195 }
2196 
2207 static inline void FTM_HAL_SetQuadMode(FTM_Type * const ftmBase,
2208  ftm_quad_decode_mode_t quadMode)
2211 }
2212 
2224 static inline bool FTM_HAL_GetQuadDir(const FTM_Type * ftmBase)
2225 {
2226  return (ftmBase->QDCTRL & FTM_QDCTRL_QUADIR_MASK) != 0U;
2227 }
2228 
2240 static inline bool FTM_HAL_GetQuadTimerOverflowDir(const FTM_Type * ftmBase)
2241 {
2242  return (ftmBase->QDCTRL & FTM_QDCTRL_TOFDIR_MASK) != 0U;
2243 }
2244 
2253 static inline void FTM_HAL_SetFaultInputFilterVal(FTM_Type * const ftmBase,
2254  uint32_t value)
2257 }
2258 
2270 static inline void FTM_HAL_SetFaultInputFilterCmd(FTM_Type * const ftmBase,
2271  uint8_t inputNum,
2272  bool enable)
2273 {
2274  DEV_ASSERT(inputNum < CHAN4_IDX);
2275 
2276  if (enable)
2277  {
2278  ((ftmBase)->FLTCTRL) |= (1UL << (inputNum + FTM_FLTCTRL_FFLTR0EN_SHIFT));
2279  }
2280  else
2281  {
2282  ((ftmBase)->FLTCTRL) &= ~(1UL << (inputNum + FTM_FLTCTRL_FFLTR0EN_SHIFT));
2283  }
2284 }
2285 
2293 static inline void FTM_HAL_ClearFaultControl(FTM_Type * const ftmBase)
2294 {
2295  ((ftmBase)->FLTCTRL) = 0U;
2296 }
2297 
2309 static inline void FTM_HAL_SetFaultInputCmd(FTM_Type * const ftmBase,
2310  uint8_t inputNum,
2311  bool enable)
2312 {
2313  DEV_ASSERT(inputNum < CHAN4_IDX);
2314 
2315  if (enable)
2316  {
2317  ((ftmBase)->FLTCTRL) |= (1UL << inputNum);
2318  }
2319  else
2320  {
2321  ((ftmBase)->FLTCTRL) &= ~(1UL << inputNum);
2322  }
2323 }
2324 
2335 static inline void FTM_HAL_SetPwmFaultBehavior(FTM_Type * const ftmBase,
2336  bool enable)
2338  if (enable)
2339  {
2340  ((ftmBase)->FLTCTRL) |= (1UL << FTM_FLTCTRL_FSTATE_SHIFT);
2341  }
2342  else
2343  {
2344  ((ftmBase)->FLTCTRL) &= ~(1UL << FTM_FLTCTRL_FSTATE_SHIFT);
2345  }
2346 }
2347 
2359 static inline void FTM_HAL_SetDualChnInvertCmd(FTM_Type * const ftmBase,
2360  uint8_t chnlPairNum,
2361  bool enable)
2362 {
2363  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
2364 
2365  if (enable)
2366  {
2367  ((ftmBase)->INVCTRL) |= (1UL << chnlPairNum);
2368  }
2369  else
2370  {
2371  ((ftmBase)->INVCTRL) &= ~(1UL << chnlPairNum);
2372  }
2373 }
2374 
2385 static inline void FTM_HAL_SetInvctrlReg(FTM_Type * const ftmBase,
2386  uint32_t regVal)
2388  ((ftmBase)->INVCTRL) = regVal;
2389 }
2390 
2391 /*FTM software output control*/
2402 static inline void FTM_HAL_SetChnSoftwareCtrlCmd(FTM_Type * const ftmBase,
2403  uint8_t channel,
2404  bool enable)
2405 {
2407 
2408  if (enable)
2409  {
2410  ((ftmBase)->SWOCTRL) |= (1UL << channel);
2411  }
2412  else
2413  {
2414  ((ftmBase)->SWOCTRL) &= ~(1UL << channel);
2415  }
2416 }
2417 
2418 /*FTM software output control*/
2428 static inline void FTM_HAL_SetAllChnSoftwareCtrlCmd(FTM_Type * const ftmBase,
2429  uint8_t channelsMask)
2434  ((ftmBase)->SWOCTRL) = (((ftmBase)->SWOCTRL) & (~(mask))) | channelsMask;
2435 }
2436 
2448 static inline void FTM_HAL_SetChnSoftwareCtrlVal(FTM_Type * const ftmBase,
2449  uint8_t channel,
2450  bool enable)
2451 {
2453 
2454  if (enable)
2455  {
2456  ((ftmBase)->SWOCTRL) |= (1UL << (channel + FTM_SWOCTRL_CH0OCV_SHIFT));
2457  }
2458  else
2459  {
2460  ((ftmBase)->SWOCTRL) &= ~(1UL << (channel + FTM_SWOCTRL_CH0OCV_SHIFT));
2461  }
2462 }
2463 
2472 static inline void FTM_HAL_SetAllChnSoftwareCtrlVal(FTM_Type * const ftmBase,
2473  uint8_t channelsValues)
2478  ((ftmBase)->SWOCTRL) = (((ftmBase)->SWOCTRL) & (~(mask))) | ((uint32_t)channelsValues << FTM_SWOCTRL_CH0OCV_SHIFT);
2479 }
2480 
2481 /*FTM PWM load control*/
2491 static inline void FTM_HAL_SetGlobalLoadCmd(FTM_Type * const ftmBase)
2492 {
2493  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_GLDOK_SHIFT);
2494 }
2495 
2506 static inline void FTM_HAL_SetLoadCmd(FTM_Type * const ftmBase,
2507  bool enable)
2509  if (enable)
2510  {
2511  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_GLEN_SHIFT);
2512  }
2513  else
2514  {
2515  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_GLEN_SHIFT);
2516  }
2517 }
2518 
2529 static inline void FTM_HAL_SetHalfCycleCmd(FTM_Type * const ftmBase,
2530  bool enable)
2532  if (enable)
2533  {
2534  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_HCSEL_SHIFT);
2535  }
2536  else
2537  {
2538  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_HCSEL_SHIFT);
2539  }
2540 }
2541 
2552 static inline void FTM_HAL_SetPwmLoadCmd(FTM_Type * const ftmBase,
2553  bool enable)
2555  if (enable)
2556  {
2557  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_LDOK_SHIFT);
2558  }
2559  else
2560  {
2561  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_LDOK_SHIFT);
2562  }
2563 }
2564 
2576 static inline void FTM_HAL_SetPwmLoadChnSelCmd(FTM_Type * const ftmBase,
2577  uint8_t channel,
2578  bool enable)
2579 {
2581 
2582  if (enable)
2583  {
2584  ((ftmBase)->PWMLOAD) |= (1UL << channel);
2585  }
2586  else
2587  {
2588  ((ftmBase)->PWMLOAD) &= ~(1UL << channel);
2589  }
2590 }
2591 
2592 /*FTM configuration*/
2603 static inline void FTM_HAL_SetInitTrigOnReloadCmd(FTM_Type * const ftmBase,
2604  bool enable)
2606  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_ITRIGR_MASK) | FTM_CONF_ITRIGR(enable);
2607 }
2608 
2619 static inline void FTM_HAL_SetGlobalTimeBaseOutputCmd(FTM_Type * const ftmBase,
2620  bool enable)
2622  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_GTBEOUT_MASK) | FTM_CONF_GTBEOUT(enable);
2623 }
2624 
2635 static inline void FTM_HAL_SetGlobalTimeBaseCmd(FTM_Type * const ftmBase,
2636  bool enable)
2638  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_GTBEEN_MASK) | FTM_CONF_GTBEEN(enable);
2639 }
2640 
2661 static inline void FTM_HAL_SetBdmMode(FTM_Type * const ftmBase,
2662  ftm_bdm_mode_t val)
2665 }
2666 
2675 static inline void FTM_HAL_SetLoadFreq(FTM_Type * const ftmBase,
2676  uint8_t val)
2679 }
2680 
2681 /*FTM Synchronization configuration*/
2692 static inline void FTM_HAL_SetSwoctrlHardwareSyncModeCmd(FTM_Type * const ftmBase,
2693  bool enable)
2695  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_HWSOC_MASK) | FTM_SYNCONF_HWSOC(enable);
2696 }
2697 
2708 static inline void FTM_HAL_SetInvctrlHardwareSyncModeCmd(FTM_Type * const ftmBase,
2709  bool enable)
2711  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_HWINVC_MASK) | FTM_SYNCONF_HWINVC(enable);
2712 }
2713 
2724 static inline void FTM_HAL_SetOutmaskHardwareSyncModeCmd(FTM_Type * const ftmBase,
2725  bool enable)
2727  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_HWOM_MASK) | FTM_SYNCONF_HWOM(enable);
2728 }
2729 
2740 static inline void FTM_HAL_SetModCntinCvHardwareSyncModeCmd(FTM_Type * const ftmBase,
2741  bool enable)
2743  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_HWWRBUF_MASK) | FTM_SYNCONF_HWWRBUF(enable);
2744 }
2745 
2756 static inline void FTM_HAL_SetCounterHardwareSyncModeCmd(FTM_Type * const ftmBase,
2757  bool enable)
2759  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_HWRSTCNT_MASK) | FTM_SYNCONF_HWRSTCNT(enable);
2760 }
2761 
2772 static inline void FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(FTM_Type * const ftmBase,
2773  bool enable)
2775  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_SWSOC_MASK) | FTM_SYNCONF_SWSOC(enable);
2776 }
2777 
2788 static inline void FTM_HAL_SetInvctrlSoftwareSyncModeCmd(FTM_Type * const ftmBase,
2789  bool enable)
2791  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_SWINVC_MASK) | FTM_SYNCONF_SWINVC(enable);
2792 }
2793 
2804 static inline void FTM_HAL_SetOutmaskSoftwareSyncModeCmd(FTM_Type * const ftmBase,
2805  bool enable)
2807  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_SWOM_MASK) | FTM_SYNCONF_SWOM(enable);
2808 }
2809 
2820 static inline void FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(FTM_Type * const ftmBase,
2821  bool enable)
2823  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_SWWRBUF_MASK) | FTM_SYNCONF_SWWRBUF(enable);
2824 }
2825 
2836 static inline void FTM_HAL_SetHwTriggerSyncModeCmd(FTM_Type * const ftmBase,
2837  bool enable)
2839  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_HWTRIGMODE_MASK) | FTM_SYNCONF_HWTRIGMODE(enable);
2840 }
2841 
2852 static inline void FTM_HAL_SetCounterSoftwareSyncModeCmd(FTM_Type * const ftmBase,
2853  ftm_pwm_sync_mode_t update_mode)
2855  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_SWRSTCNT_MASK) | FTM_SYNCONF_SWRSTCNT(update_mode);
2856 }
2857 
2868 static inline void FTM_HAL_SetPwmSyncModeCmd(FTM_Type * const ftmBase,
2869  bool mode)
2871  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_SYNCMODE_MASK) | FTM_SYNCONF_SYNCMODE(mode);
2872 }
2873 
2884 static inline void FTM_HAL_SetSwoctrlPwmSyncModeCmd(FTM_Type * const ftmBase,
2885  ftm_reg_update_t mode)
2887  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_SWOC_MASK) | FTM_SYNCONF_SWOC(mode);
2888 }
2889 
2900 static inline void FTM_HAL_SetInvctrlPwmSyncModeCmd(FTM_Type * const ftmBase,
2901  ftm_reg_update_t mode)
2903  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_INVC_MASK) | FTM_SYNCONF_INVC(mode);
2904 }
2905 
2916 static inline void FTM_HAL_SetCntinPwmSyncModeCmd(FTM_Type * const ftmBase,
2917  ftm_reg_update_t mode)
2919  ftmBase->SYNCONF = (ftmBase->SYNCONF & ~FTM_SYNCONF_CNTINC_MASK) | FTM_SYNCONF_CNTINC(mode);
2920 }
2921 
2931 static inline void FTM_HAL_SetExtPairDeadtimeValue(FTM_Type * const ftmBase,
2932  uint8_t channelPair,
2933  uint8_t value)
2934 {
2935  DEV_ASSERT(value < 16U);
2936  DEV_ASSERT(channelPair < CHAN4_IDX);
2937 
2938  switch (channelPair)
2939  {
2940  case CHAN0_IDX:
2942  break;
2943  case CHAN1_IDX:
2945  break;
2946  case CHAN2_IDX:
2948  break;
2949  case CHAN3_IDX:
2951  break;
2952  default:
2953  /* Nothing to do */
2954  break;
2955  }
2956 }
2957 
2970 static inline void FTM_HAL_SetPairDeadtimePrescale(FTM_Type * const ftmBase,
2971  uint8_t channelPair,
2973 {
2974  DEV_ASSERT(channelPair < CHAN4_IDX);
2975 
2976  switch (channelPair)
2977  {
2978  case CHAN0_IDX:
2980  break;
2981  case CHAN1_IDX:
2983  break;
2984  case CHAN2_IDX:
2986  break;
2987  case CHAN3_IDX:
2989  break;
2990  default:
2991  /* Nothing to do */
2992  break;
2993  }
2994 }
2995 
3009 static inline void FTM_HAL_SetPairDeadtimeCount(FTM_Type * const ftmBase,
3010  uint8_t channelPair,
3011  uint8_t count)
3012 {
3013  DEV_ASSERT(channelPair < CHAN4_IDX);
3014  DEV_ASSERT(count < 64U);
3015 
3016  switch (channelPair)
3017  {
3018  case CHAN0_IDX:
3020  break;
3021  case CHAN1_IDX:
3023  break;
3024  case CHAN2_IDX:
3026  break;
3027  case CHAN3_IDX:
3029  break;
3030  default:
3031  /* Nothing to do */
3032  break;
3033  }
3034 }
3035 
3036 /*HAL functionality*/
3043 void FTM_HAL_Reset(FTM_Type * const ftmBase);
3044 
3051 void FTM_HAL_Init(FTM_Type * const ftmBase,
3052  ftm_clock_ps_t ftmClockPrescaler);
3053 
3064 void FTM_HAL_SetChnTriggerCmd(FTM_Type * const ftmBase,
3065  uint8_t channel,
3066  bool enable);
3067 
3074 void FTM_HAL_SetChnInputCaptureFilter(FTM_Type * const ftmBase,
3075  uint8_t channel,
3076  uint8_t value);
3077 
3078 #if defined(__cplusplus)
3079 }
3080 #endif
3081 
3085 #endif /* FTM_HAL_H */
3086 /*******************************************************************************
3087  * EOF
3088  ******************************************************************************/
__IO uint32_t CnSC
Definition: S32K144.h:3987
static void FTM_HAL_SetGlobalTimeBaseOutputCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM global time base signal generation to other FTM's.
Definition: ftm_hal.h:2621
static bool FTM_HAL_IsFtmEnable(const FTM_Type *ftmBase)
Get status of the FTMEN bit in the FTM_MODE register.
Definition: ftm_hal.h:1484
#define FTM_QDCTRL_QUADEN_SHIFT
Definition: S32K144.h:4669
static void FTM_HAL_SetInitTriggerCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the generation of the trigger when the FTM counter is equal to the CNTIN register...
Definition: ftm_hal.h:1973
__IO uint32_t SYNCONF
Definition: S32K144.h:4006
#define FTM_QDCTRL_TOFDIR_MASK
Definition: S32K144.h:4672
#define FTM_SC_RIE_MASK
Definition: S32K144.h:4086
#define FTM_QDCTRL_QUADMODE_MASK
Definition: S32K144.h:4680
#define FTM_FMS_FAULTF0_MASK
Definition: S32K144.h:4581
static void FTM_HAL_SetDualChnPwmSyncCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the FTM peripheral timer channel pair counter PWM sync.
Definition: ftm_hal.h:1698
#define FTM_SYNCONF_HWINVC_MASK
Definition: S32K144.h:4791
#define FTM_SC_CLKS_SHIFT
Definition: S32K144.h:4079
#define FTM_CNTIN_INIT(x)
Definition: S32K144.h:4202
static void FTM_HAL_SetSwoctrlPwmSyncModeCmd(FTM_Type *const ftmBase, ftm_reg_update_t mode)
Sets the SWOCTRL register PWM synchronization mode.
Definition: ftm_hal.h:2886
static void FTM_HAL_ClearChnTriggerFlag(FTM_Type *const ftmBase)
Clear the channel trigger flag.
Definition: ftm_hal.h:2001
ftm_fault_mode_t
FlexTimer fault control.
Definition: ftm_hal.h:366
static void FTM_HAL_SetExtDeadtimeValue(FTM_Type *const ftmBase, uint8_t value)
Sets the FTM extended dead-time value.
Definition: ftm_hal.h:1916
static void FTM_HAL_SetClockFilterPs(FTM_Type *const ftmBase, uint8_t filterPrescale)
Sets the filter Pre-scaler divider.
Definition: ftm_hal.h:432
#define FTM_CONF_GTBEOUT_MASK
Definition: S32K144.h:4713
#define FTM_SWOCTRL_CH1OC_MASK
Definition: S32K144.h:4821
#define FTM_SC_RF(x)
Definition: S32K144.h:4093
#define FTM_SYNCONF_HWTRIGMODE(x)
Definition: S32K144.h:4742
#define FTM_SYNCONF_HWOM(x)
Definition: S32K144.h:4790
static void FTM_HAL_SetQuadDecoderCmd(FTM_Type *const ftmBase, bool enable)
Enables the channel quadrature decoder.
Definition: ftm_hal.h:2108
#define FTM_SYNCONF_CNTINC_MASK
Definition: S32K144.h:4743
#define FTM_SC_TOIE_SHIFT
Definition: S32K144.h:4095
static void FTM_HAL_SetChnSoftwareCtrlVal(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Sets the channel software output control value.
Definition: ftm_hal.h:2450
#define FTM_SC_TOIE(x)
Definition: S32K144.h:4097
static void FTM_HAL_SetChnOutputPolarityCmd(FTM_Type *const ftmBase, uint8_t channel, ftm_polarity_t polarity)
Sets the FTM peripheral timer channel output polarity.
Definition: ftm_hal.h:1299
static void FTM_HAL_DisableChnInt(FTM_Type *const ftmBase, uint8_t channel)
Disables the FTM peripheral timer channel(n) interrupt.
Definition: ftm_hal.h:1001
#define FTM_PWMLOAD_GLEN_SHIFT
Definition: S32K144.h:4923
static bool FTM_HAL_GetDetectedFaultInput(const FTM_Type *ftmBase)
Gets the FTM detected fault input.
Definition: ftm_hal.h:2020
static bool FTM_HAL_IsOverflowIntEnabled(const FTM_Type *ftmBase)
Reads the bit that controls enabling the FTM timer overflow interrupt.
Definition: ftm_hal.h:542
ftm_polarity_t
FlexTimer PWM output pulse mode, high-true or low-true on match up.
Definition: ftm_hal.h:297
#define FTM_CnSC_MSA(x)
Definition: S32K144.h:4168
#define FTM_RMW_SC(base, mask, value)
FTM_SC - Read and modify and write to Status And Control (RW)
Definition: ftm_hal.h:130
#define FTM_CnSC_ELSB_SHIFT
Definition: S32K144.h:4162
static void FTM_HAL_SetDualChnMofCombineCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables the FTM peripheral timer channel modified combine mode.
Definition: ftm_hal.h:1644
#define FTM_FMS_FAULTF_MASK
Definition: S32K144.h:4605
#define FTM_PAIR3DEADTIME_DTVALEX_MASK
Definition: S32K144.h:4983
static void FTM_HAL_SetQuadPhaseAFilterCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the phase A input filter.
Definition: ftm_hal.h:2131
#define FTM_PWMLOAD_HCSEL_SHIFT
Definition: S32K144.h:4915
#define FTM_SYNCONF_SWINVC_MASK
Definition: S32K144.h:4771
#define FTM_COMBINE_COMBINE0_MASK
Definition: S32K144.h:4365
#define FTM_FMS_FAULTF1_MASK
Definition: S32K144.h:4585
#define FTM_MOD_MOD_MASK
Definition: S32K144.h:4144
static void FTM_HAL_SetOutmaskPwmSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Determines when the OUTMASK register is updated with the value of its buffer.
Definition: ftm_hal.h:1578
#define FTM_SYNCONF_SWINVC(x)
Definition: S32K144.h:4774
static void FTM_HAL_SetChnSoftwareCtrlCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the channel software output control.
Definition: ftm_hal.h:2404
#define FTM_SYNCONF_HWOM_MASK
Definition: S32K144.h:4787
#define FTM_COMBINE_FAULTEN0_MASK
Definition: S32K144.h:4389
static void FTM_HAL_SetPairDeadtimeCount(FTM_Type *const ftmBase, uint8_t channelPair, uint8_t count)
Sets the FTM dead-time value for the channel pair.
Definition: ftm_hal.h:3011
#define FTM_CONF_BDMMODE(x)
Definition: S32K144.h:4708
static void FTM_HAL_EnablePwmChannelOutputs(FTM_Type *const ftmBase, uint8_t channel)
Enable PWM channel Outputs.
Definition: ftm_hal.h:555
void FTM_HAL_SetChnTriggerCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the generation of the FTM peripheral timer channel trigger when the FTM counter i...
Definition: ftm_hal.c:106
#define FTM_SWOCTRL_CH0OCV_MASK
Definition: S32K144.h:4849
static void FTM_HAL_SetDualChnFaultCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables the FTM peripheral timer channel pair fault control.
Definition: ftm_hal.h:1671
#define FTM_SYNCONF_INVC_MASK
Definition: S32K144.h:4747
#define FTM_RMW_FLTCTRL(base, mask, value)
FTM_FLTCTRL - Read and modify and write Fault Control (RW)
Definition: ftm_hal.h:174
#define FTM_RMW_CNT(base, mask, value)
FTM_CNT - Read and modify and write to Counter (RW)
Definition: ftm_hal.h:135
static void FTM_HAL_SetPwmSyncMode(FTM_Type *const ftmBase, bool enable)
Sets the FTM peripheral timer sync mode.
Definition: ftm_hal.h:1516
#define FTM_MODE_FAULTM_MASK
Definition: S32K144.h:4257
#define FTM_SC_CPWMS(x)
Definition: S32K144.h:4085
static bool FTM_HAL_GetTriggerControled(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the trigger mode is enabled.
Definition: ftm_hal.h:1081
static void FTM_HAL_SetBdmMode(FTM_Type *const ftmBase, ftm_bdm_mode_t val)
Sets the BDM mode.
Definition: ftm_hal.h:2663
static void FTM_HAL_SetSwoctrlHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets the sync mode for the FTM SWOCTRL register when using a hardware trigger.
Definition: ftm_hal.h:2694
#define FTM_CnSC_CHIE(x)
Definition: S32K144.h:4176
#define FTM_PAIR1DEADTIME_DTPS_MASK
Definition: S32K144.h:4953
static void FTM_HAL_SetChnEdgeLevel(FTM_Type *const ftmBase, uint8_t channel, uint8_t level)
Sets the FTM peripheral timer channel edge level.
Definition: ftm_hal.h:803
#define FTM_COMBINE_SYNCEN0_MASK
Definition: S32K144.h:4385
#define FTM_RMW_CONF(base, mask, value)
FTM_CONF - Read and modify and write Configuration (RW)
Definition: ftm_hal.h:184
#define FTM_DEADTIME_DTVALEX(x)
Definition: S32K144.h:4505
#define FTM_SC_FLTPS_MASK
Definition: S32K144.h:4134
static void FTM_HAL_Enable(FTM_Type *const ftmBase, bool enable)
Enables the FTM peripheral timer group.
Definition: ftm_hal.h:1468
#define FTM_SWOCTRL_CH0OCV_SHIFT
Definition: S32K144.h:4850
static void FTM_HAL_ClearFaultFlagDetected(FTM_Type *const ftmBase, uint8_t channel)
Clear a fault condition is detected at the fault input.
Definition: ftm_hal.h:2085
static uint32_t FTM_HAL_GetEventStatus(const FTM_Type *ftmBase)
Gets the FTM peripheral timer status info for all channels.
Definition: ftm_hal.h:1193
#define FTM_FMS_FAULTF3(x)
Definition: S32K144.h:4596
#define FTM_SC_CLKS(x)
Definition: S32K144.h:4081
static void FTM_HAL_SetChnCountVal(FTM_Type *const ftmBase, uint8_t channel, uint16_t value)
Sets the FTM peripheral timer channel counter value.
Definition: ftm_hal.h:1137
static bool FTM_HAL_GetChInputState(const FTM_Type *ftmBase, uint8_t channel)
Get the state of channel input.
Definition: ftm_hal.h:1100
#define FTM_SWOCTRL_CH3OC_MASK
Definition: S32K144.h:4829
#define FTM_CONF_BDMMODE_MASK
Definition: S32K144.h:4705
static uint8_t FTM_HAL_GetChnEdgeLevel(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel edge level.
Definition: ftm_hal.h:869
#define FTM_PAIR3DEADTIME_DTVAL(x)
Definition: S32K144.h:4978
#define FTM_EXTTRIG_INITTRIGEN(x)
Definition: S32K144.h:4534
static void FTM_HAL_SetChnOutputInitStateCmd(FTM_Type *const ftmBase, uint8_t channel, bool state)
Sets the FTM peripheral timer channel output initial state 0 or 1.
Definition: ftm_hal.h:1272
static void FTM_HAL_SetInvctrlReg(FTM_Type *const ftmBase, uint32_t regVal)
Writes the provided value to the Inverting control register.
Definition: ftm_hal.h:2387
static bool FTM_HAL_GetReloadFlag(const FTM_Type *ftmBase)
Get the state whether the FTM counter reached a reload point.
Definition: ftm_hal.h:667
static void FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM SWOCTRL register when using a software trigger.
Definition: ftm_hal.h:2774
static void FTM_HAL_ClearChSC(FTM_Type *const ftmBase, uint8_t channel)
Clears the content of Channel (n) Status And Control.
Definition: ftm_hal.h:824
#define FTM_SYNCONF_HWSOC(x)
Definition: S32K144.h:4798
#define FTM_CONF_GTBEEN_MASK
Definition: S32K144.h:4709
static bool FTM_HAL_GetQuadTimerOverflowDir(const FTM_Type *ftmBase)
Gets the Timer overflow direction in quadrature mode.
Definition: ftm_hal.h:2242
#define FTM_PAIR3DEADTIME_DTPS_MASK
Definition: S32K144.h:4979
#define FTM_SC_TOF_MASK
Definition: S32K144.h:4098
#define FTM_QDCTRL_PHAPOL(x)
Definition: S32K144.h:4691
#define FTM_SYNCONF_HWRSTCNT_MASK
Definition: S32K144.h:4779
#define FTM_SWOCTRL_CH4OCV_MASK
Definition: S32K144.h:4865
static void FTM_HAL_SetWriteProtectionCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM write protection.
Definition: ftm_hal.h:1445
#define FTM_SC_CLKS_MASK
Definition: S32K144.h:4078
static bool FTM_HAL_IsChnIcrst(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the FTM FTM counter is reset.
Definition: ftm_hal.h:914
#define FTM_CnSC_TRIGMODE(x)
Definition: S32K144.h:4184
#define FTM_SWOCTRL_CH2OC_MASK
Definition: S32K144.h:4825
static bool FTM_HAL_IsChnTriggerGenerated(const FTM_Type *ftmBase)
Checks whether any channel trigger event has occurred.
Definition: ftm_hal.h:1989
#define FTM_SWOCTRL_CH5OC_MASK
Definition: S32K144.h:4837
#define FTM_SWOCTRL_CH3OCV_MASK
Definition: S32K144.h:4861
#define FTM_SC_TOF_SHIFT
Definition: S32K144.h:4099
static void FTM_HAL_SetQuadPhaseBFilterCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the phase B input filter.
Definition: ftm_hal.h:2154
ftm_reg_update_t
FTM sync source.
Definition: ftm_hal.h:383
#define FTM_CONF_GTBEOUT(x)
Definition: S32K144.h:4716
static bool FTM_HAL_GetCpwms(const FTM_Type *ftmBase)
Gets the FTM count direction bit.
Definition: ftm_hal.h:636
#define FTM_CNTIN_INIT_MASK
Definition: S32K144.h:4199
#define FTM_PAIR2DEADTIME_DTVALEX_MASK
Definition: S32K144.h:4970
#define FTM_SYNC_SYNCHOM_MASK
Definition: S32K144.h:4278
#define FTM_CNTIN_INIT_SHIFT
Definition: S32K144.h:4200
#define FTM_SYNCONF_SWSOC(x)
Definition: S32K144.h:4778
#define FTM_MODE_FAULTIE_MASK
Definition: S32K144.h:4261
#define FTM_DEADTIME_DTPS_MASK
Definition: S32K144.h:4498
ftm_quad_phase_polarity_t
FlexTimer quadrature phase polarities, normal or inverted polarity.
Definition: ftm_hal.h:332
static uint8_t FTM_HAL_GetClockFilterPs(const FTM_Type *ftmBase)
Reads the FTM filter clock divider.
Definition: ftm_hal.h:447
#define DEV_ASSERT(x)
Definition: devassert.h:78
#define FTM_MODE_PWMSYNC(x)
Definition: S32K144.h:4252
static void FTM_HAL_SetTimerOverflowInt(FTM_Type *const ftmBase, bool state)
Enables the FTM peripheral timer overflow interrupt.
Definition: ftm_hal.h:525
#define FTM_RMW_PAIR3DEADTIME(base, mask, value)
FTM_PAIR3DEADTIME - Read and modify and write Dead-time Insertion Control for the pair 3 (RW) ...
Definition: ftm_hal.h:224
#define FTM_COMBINE_MCOMBINE0_MASK
Definition: S32K144.h:4393
static bool FTM_HAL_IsFaultFlagDetected(const FTM_Type *ftmBase, uint8_t channel)
Checks whether a fault condition is detected at the fault input.
Definition: ftm_hal.h:2069
static void FTM_HAL_DisablePwmChannelOutputs(FTM_Type *const ftmBase, uint8_t channel)
Disable PWM channel Outputs.
Definition: ftm_hal.h:569
__IO uint32_t MODE
Definition: S32K144.h:3992
#define FTM_MODE_INIT_MASK
Definition: S32K144.h:4241
#define FTM_MODE_FAULTIE(x)
Definition: S32K144.h:4264
#define FTM_COMBINE_DTEN0_MASK
Definition: S32K144.h:4381
static void FTM_HAL_ClearChnEventStatus(FTM_Type *const ftmBase, uint8_t channel)
Clears the FTM peripheral timer all channel event status.
Definition: ftm_hal.h:1206
static bool FTM_HAL_HasTimerOverflowed(const FTM_Type *ftmBase)
Returns the FTM peripheral timer overflow interrupt flag.
Definition: ftm_hal.h:604
#define FTM_RMW_QDCTRL(base, mask, value)
QDCTRL - Read and modify and write Quadrature Decoder Control And Status (RW)
Definition: ftm_hal.h:204
#define FTM_SC_PS_SHIFT
Definition: S32K144.h:4075
static void FTM_HAL_SetFaultInputFilterCmd(FTM_Type *const ftmBase, uint8_t inputNum, bool enable)
Enables or disables the fault input filter.
Definition: ftm_hal.h:2272
static void FTM_HAL_SetTrigModeControlCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the trigger generation on FTM channel outputs.
Definition: ftm_hal.h:1060
#define FTM_MODE_PWMSYNC_MASK
Definition: S32K144.h:4249
#define FTM_SYNCONF_SWRSTCNT(x)
Definition: S32K144.h:4762
#define FTM_DEADTIME_DTVAL_MASK
Definition: S32K144.h:4494
static void FTM_HAL_SetFaultInt(FTM_Type *const ftmBase, bool state)
Enables/disables the FTM peripheral timer fault interrupt.
Definition: ftm_hal.h:1352
#define FTM_COMBINE_COMP0_MASK
Definition: S32K144.h:4369
static bool FTM_HAL_IsFaultInputEnabled(const FTM_Type *ftmBase)
Checks whether the logic OR of the fault inputs is enabled.
Definition: ftm_hal.h:2052
#define FTM_PAIR1DEADTIME_DTVAL(x)
Definition: S32K144.h:4952
static bool FTM_HAL_GetQuadDir(const FTM_Type *ftmBase)
Gets the FTM counter direction in quadrature mode.
Definition: ftm_hal.h:2226
#define FTM_PWMLOAD_GLDOK_SHIFT
Definition: S32K144.h:4927
static void FTM_HAL_ClearReloadFlag(FTM_Type *const ftmBase)
Clears the reload flag bit.
Definition: ftm_hal.h:679
#define FTM_MODE_INIT(x)
Definition: S32K144.h:4244
__IO uint32_t EXTTRIG
Definition: S32K144.h:3998
#define FTM_SYNCONF_HWTRIGMODE_MASK
Definition: S32K144.h:4739
static void FTM_HAL_SetHalfCycleValue(FTM_Type *const ftmBase, uint16_t value)
Sets the value for the half cycle reload register.
Definition: ftm_hal.h:418
#define FTM_FMS_WPEN_MASK
Definition: S32K144.h:4601
__IO uint32_t STATUS
Definition: S32K144.h:3991
#define FTM_PAIR1DEADTIME_DTPS(x)
Definition: S32K144.h:4956
#define FTM_SYNCONF_INVC(x)
Definition: S32K144.h:4750
#define FTM_SYNCONF_HWWRBUF(x)
Definition: S32K144.h:4786
#define FTM_PAIR1DEADTIME_DTVAL_MASK
Definition: S32K144.h:4949
#define FTM_CnSC_MSB_SHIFT
Definition: S32K144.h:4170
#define FTM_PAIR2DEADTIME_DTPS(x)
Definition: S32K144.h:4969
#define FTM_QDCTRL_QUADIR_MASK
Definition: S32K144.h:4676
static uint8_t FTM_HAL_GetChnMode(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel mode.
Definition: ftm_hal.h:846
#define FTM_CnSC_ELSA_MASK
Definition: S32K144.h:4157
ftm_deadtime_ps_t
FlexTimer pre-scaler factor for the dead-time insertion.
Definition: ftm_hal.h:285
#define FTM_QDCTRL_QUADMODE(x)
Definition: S32K144.h:4683
#define FTM_MODE_FAULTIE_SHIFT
Definition: S32K144.h:4262
static void FTM_HAL_SetDualChnDeadtimeCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disabled the FTM peripheral timer channel pair deadtime insertion.
Definition: ftm_hal.h:1725
static uint16_t FTM_HAL_GetCounterInitVal(const FTM_Type *ftmBase)
Returns the FTM peripheral counter initial value.
Definition: ftm_hal.h:767
#define FTM_SYNC_CNTMIN_MASK
Definition: S32K144.h:4266
#define FTM_SYNC_CNTMAX(x)
Definition: S32K144.h:4273
static bool FTM_HAL_IsChnIntEnabled(const FTM_Type *ftmBase, uint8_t channel)
Get FTM channel(n) interrupt enabled or not.
Definition: ftm_hal.h:969
static bool FTM_HAL_IsFaultIntEnabled(const FTM_Type *ftmBase)
Return true/false whether the Fault interrupt was enabled or not.
Definition: ftm_hal.h:1377
static void FTM_HAL_SetModCntinCvHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM MOD, CNTIN and CV registers when using a hardware trigger. ...
Definition: ftm_hal.h:2742
#define FTM_MODE_WPDIS(x)
Definition: S32K144.h:4248
#define FTM_RMW_PAIR1DEADTIME(base, mask, value)
FTM_PAIR1DEADTIME - Read and modify and write Dead-time Insertion Control for the pair 1 (RW) ...
Definition: ftm_hal.h:214
#define FTM_FMS_FAULTF0(x)
Definition: S32K144.h:4584
#define FTM_RMW_MOD(base, mask, value)
FTM_MOD - Read and modify and write Modulo (RW)
Definition: ftm_hal.h:140
static void FTM_HAL_SetFaultInputFilterVal(FTM_Type *const ftmBase, uint32_t value)
Sets the fault input filter value.
Definition: ftm_hal.h:2255
#define FTM_EXTTRIG_TRIGF_MASK
Definition: S32K144.h:4535
#define FTM_PAIR0DEADTIME_DTVALEX_MASK
Definition: S32K144.h:4944
#define FTM_SYNC_SYNCHOM(x)
Definition: S32K144.h:4281
static void FTM_HAL_ClearFaultsIsr(FTM_Type *const ftmBase)
Clears all fault interrupt flags that are active.
Definition: ftm_hal.h:1389
#define FTM_COMBINE_DECAP0_MASK
Definition: S32K144.h:4377
#define FTM_CnSC_CHF_MASK
Definition: S32K144.h:4177
#define FTM_RMW_FMS(base, mask, value)
FTM_FMS - Read and modify and write Fault Mode Status (RW)
Definition: ftm_hal.h:179
__IO uint32_t CONF
Definition: S32K144.h:4004
#define CHAN1_IDX
Channel number for CHAN2.
Definition: ftm_hal.h:231
#define FTM_QDCTRL_PHBFLTREN_SHIFT
Definition: S32K144.h:4693
static void FTM_HAL_SetDualChnDecapCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the FTM peripheral timer channel dual edge capture.
Definition: ftm_hal.h:1752
#define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET
#define FTM_MODE_WPDIS_MASK
Definition: S32K144.h:4245
#define FTM_CnSC_CHF(x)
Definition: S32K144.h:4180
static void FTM_HAL_SetChnDmaCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the FTM peripheral timer channel DMA.
Definition: ftm_hal.h:933
#define FTM_DEADTIME_DTPS(x)
Definition: S32K144.h:4501
#define FEATURE_FTM_CHANNEL_COUNT
static void FTM_HAL_SetChnOutputMask(FTM_Type *const ftmBase, uint8_t channel, bool mask)
Sets the FTM peripheral timer channel output mask.
Definition: ftm_hal.h:1245
static void FTM_HAL_SetGlobalLoadCmd(FTM_Type *const ftmBase)
Set the global load mechanism.
Definition: ftm_hal.h:2493
#define FTM_MOD_MOD_SHIFT
Definition: S32K144.h:4145
static void FTM_HAL_SetInvctrlHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM INVCTRL register when using a hardware trigger.
Definition: ftm_hal.h:2710
#define FTM_CnSC_CHIE_MASK
Definition: S32K144.h:4173
static bool FTM_HAL_GetChOutputValue(const FTM_Type *ftmBase, uint8_t channel)
Get the value of channel output.
Definition: ftm_hal.h:1119
#define FTM_QDCTRL_PHAFLTREN_SHIFT
Definition: S32K144.h:4697
static void FTM_HAL_SetAllChnSoftwareCtrlCmd(FTM_Type *const ftmBase, uint8_t channelsMask)
Enables or disables the channel software output control.The main difference between this function and...
Definition: ftm_hal.h:2430
#define FTM_SC_FLTPS(x)
Definition: S32K144.h:4137
#define FTM_SC_CPWMS_MASK
Definition: S32K144.h:4082
static void FTM_HAL_DisableFaultInt(FTM_Type *const ftmBase)
Disables the FTM peripheral timer fault interrupt.
Definition: ftm_hal.h:1365
#define FTM_SYNCONF_SWWRBUF_MASK
Definition: S32K144.h:4763
#define FTM_CnSC_ELSB_MASK
Definition: S32K144.h:4161
#define FTM_SC_TOF(x)
Definition: S32K144.h:4101
#define FTM_SC_PS_MASK
Definition: S32K144.h:4074
#define FTM_SWOCTRL_CH2OCV_MASK
Definition: S32K144.h:4857
struct FTM_Type::@12 CONTROLS[FTM_CONTROLS_COUNT]
#define FTM_QDCTRL_PHBPOL_MASK
Definition: S32K144.h:4684
static void FTM_HAL_EnableChnInt(FTM_Type *const ftmBase, uint8_t channel)
Enables the FTM peripheral timer channel(n) interrupt.
Definition: ftm_hal.h:985
#define FTM_SWOCTRL_CH1OCV_MASK
Definition: S32K144.h:4853
void FTM_HAL_SetChnInputCaptureFilter(FTM_Type *const ftmBase, uint8_t channel, uint8_t value)
Sets the FTM peripheral timer channel input capture filter value.
Definition: ftm_hal.c:143
static void FTM_HAL_SetLoadCmd(FTM_Type *const ftmBase, bool enable)
Enable the global load.
Definition: ftm_hal.h:2508
#define FTM_MODE_CAPTEST_MASK
Definition: S32K144.h:4253
static void FTM_HAL_SetDualChnCombineCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the FTM peripheral timer channel pair output combine mode.
Definition: ftm_hal.h:1853
#define FTM_CNT_COUNT(x)
Definition: S32K144.h:4142
#define FTM_SWOCTRL_CH6OC_MASK
Definition: S32K144.h:4841
static void FTM_HAL_SetInitTrigOnReloadCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM initialization trigger on Reload Point.
Definition: ftm_hal.h:2605
#define FTM_CnSC_ELSA(x)
Definition: S32K144.h:4160
static void FTM_HAL_SetCntinPwmSyncModeCmd(FTM_Type *const ftmBase, ftm_reg_update_t mode)
Sets the CNTIN register PWM synchronization mode.
Definition: ftm_hal.h:2918
static void FTM_HAL_SetGlobalTimeBaseCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM timer global time base.
Definition: ftm_hal.h:2637
#define CHAN4_IDX
Channel number for CHAN5.
Definition: ftm_hal.h:237
static bool FTM_HAL_IsChnDma(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the FTM peripheral timer channel DMA is enabled.
Definition: ftm_hal.h:954
#define FTM_FLTCTRL_FFLTR0EN_SHIFT
Definition: S32K144.h:4644
ftm_second_channel_polarity_t
FlexTimer PWM channel (n+1) polarity for combine mode.
Definition: ftm_hal.h:308
static void FTM_HAL_SetPairDeadtimePrescale(FTM_Type *const ftmBase, uint8_t channelPair, ftm_deadtime_ps_t divider)
Sets the FTM dead time divider for the channel pair.
Definition: ftm_hal.h:2972
#define FTM_SC_RF_MASK
Definition: S32K144.h:4090
#define CHAN3_IDX
Channel number for CHAN4.
Definition: ftm_hal.h:235
#define FTM_SYNC_TRIG0_MASK
Definition: S32K144.h:4282
#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH
static void FTM_HAL_SetPwmLoadCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the loading of MOD, CNTIN and CV with values of their write buffer.
Definition: ftm_hal.h:2554
static uint16_t FTM_HAL_GetMod(const FTM_Type *ftmBase)
Returns the FTM peripheral counter modulo value.
Definition: ftm_hal.h:739
static void FTM_HAL_SetMinLoadingCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer minimum loading points.
Definition: ftm_hal.h:1627
static void FTM_HAL_SetCpwms(FTM_Type *const ftmBase, bool mode)
Sets the FTM count direction bit.
Definition: ftm_hal.h:619
static void FTM_HAL_ClearChnEventFlag(FTM_Type *const ftmBase, uint8_t channel)
Clear the channel flag by writing a 0 to the CHF bit.
Definition: ftm_hal.h:1037
#define FTM_PAIR0DEADTIME_DTVAL_MASK
Definition: S32K144.h:4936
#define FTM_CONF_ITRIGR_MASK
Definition: S32K144.h:4717
#define FTM_SWOCTRL_CH6OCV_MASK
Definition: S32K144.h:4873
#define FTM_SWOCTRL_CH4OC_MASK
Definition: S32K144.h:4833
#define FTM_PAIR3DEADTIME_DTVAL_MASK
Definition: S32K144.h:4975
static void FTM_HAL_SetExtPairDeadtimeValue(FTM_Type *const ftmBase, uint8_t channelPair, uint8_t value)
Sets the FTM extended dead-time value for the channel pair.
Definition: ftm_hal.h:2933
#define FTM_CnSC_ELSA_SHIFT
Definition: S32K144.h:4158
#define FTM_PAIR0DEADTIME_DTPS_MASK
Definition: S32K144.h:4940
#define FTM_PAIR3DEADTIME_DTPS(x)
Definition: S32K144.h:4982
static void FTM_HAL_SetCaptureTestCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer capture test mode.
Definition: ftm_hal.h:1429
ftm_quad_decode_mode_t
FlexTimer quadrature decode modes, phase encode or count and direction mode.
Definition: ftm_hal.h:321
#define FTM_RMW_CnSCV_REG(base, channel, mask, value)
FTM_CnSCV - Read and modify and write Channel (n) Status And Control (RW)
Definition: ftm_hal.h:160
#define FTM_RMW_SYNC(base, mask, value)
SYNC - Read and modify and write Synchronization (RW)
Definition: ftm_hal.h:199
static void FTM_HAL_SetDeadtimePrescale(FTM_Type *const ftmBase, ftm_deadtime_ps_t divider)
Sets the FTM dead time divider.
Definition: ftm_hal.h:1935
ftm_pwm_sync_mode_t
FTM update register.
Definition: ftm_hal.h:396
#define FTM_FEATURE_FAULT_CHANNELS
static void FTM_HAL_SetHardwareSyncTriggerSrc(FTM_Type *const ftmBase, uint8_t trigger_num, bool enable)
Sets the FTM hardware synchronization trigger.
Definition: ftm_hal.h:1552
static void FTM_HAL_SetReIntEnabledCmd(FTM_Type *const ftmBase, bool enable)
Set the FTM reload interrupt enable.
Definition: ftm_hal.h:650
#define FTM_SYNC_CNTMAX_MASK
Definition: S32K144.h:4270
static void FTM_HAL_SetCounterSoftwareSyncModeCmd(FTM_Type *const ftmBase, ftm_pwm_sync_mode_t update_mode)
Sets sync mode for FTM counter register when using a software trigger.
Definition: ftm_hal.h:2854
#define FTM_MOD_MOD(x)
Definition: S32K144.h:4147
#define FTM_SYNCONF_SWOM(x)
Definition: S32K144.h:4770
#define FTM_PAIR1DEADTIME_DTVALEX(x)
Definition: S32K144.h:4960
static void FTM_HAL_SetPwmLoadChnSelCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Includes or excludes the channel in the matching process.
Definition: ftm_hal.h:2578
#define FTM_SC_TOIE_MASK
Definition: S32K144.h:4094
static void FTM_HAL_SetPwmFaultBehavior(FTM_Type *const ftmBase, bool enable)
Configures the behavior of the PWM outputs when a fault is detected.
Definition: ftm_hal.h:2337
static void FTM_HAL_SetInvctrlPwmSyncModeCmd(FTM_Type *const ftmBase, ftm_reg_update_t mode)
Sets the INVCTRL register PWM synchronization mode.
Definition: ftm_hal.h:2902
static void FTM_HAL_ClearTimerOverflow(FTM_Type *const ftmBase)
Clears the timer overflow interrupt flag.
Definition: ftm_hal.h:584
#define FTM_QDCTRL_PHBPOL(x)
Definition: S32K144.h:4687
static bool FTM_HAL_GetDualChnCombineCmd(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Verify if an channels pair is used in combine mode or not.
Definition: ftm_hal.h:1881
static void FTM_HAL_SetCountReinitSyncCmd(FTM_Type *const ftmBase, bool enable)
Determines if the FTM counter is re-initialized when the selected trigger for synchronization is dete...
Definition: ftm_hal.h:1595
#define FTM_SYNCONF_SWOC_MASK
Definition: S32K144.h:4751
#define FTM_SYNC_SWSYNC(x)
Definition: S32K144.h:4297
#define FTM_CnSC_DMA(x)
Definition: S32K144.h:4152
#define FTM_MODE_CAPTEST(x)
Definition: S32K144.h:4256
#define FTM_EXTTRIG_INITTRIGEN_MASK
Definition: S32K144.h:4531
ftm_bdm_mode_t
Options for the FlexTimer behavior in BDM Mode.
Definition: ftm_hal.h:345
static void FTM_HAL_SetClockPs(FTM_Type *const ftmBase, ftm_clock_ps_t ps)
Sets the FTM clock divider.
Definition: ftm_hal.h:496
#define FTM_SYNCONF_SYNCMODE_MASK
Definition: S32K144.h:4755
static void FTM_HAL_ClearFaultControl(FTM_Type *const ftmBase)
Clears the entire content value of the Fault control register.
Definition: ftm_hal.h:2295
#define FTM_PAIR3DEADTIME_DTVALEX(x)
Definition: S32K144.h:4986
#define FTM_CnSC_ELSB(x)
Definition: S32K144.h:4164
#define FTM_CnSC_CHOV_MASK
Definition: S32K144.h:4189
#define FTM_SYNCONF_HWSOC_MASK
Definition: S32K144.h:4795
#define FTM_SYNCONF_SWOM_MASK
Definition: S32K144.h:4767
#define FTM_CnSC_MSA_SHIFT
Definition: S32K144.h:4166
void FTM_HAL_Init(FTM_Type *const ftmBase, ftm_clock_ps_t ftmClockPrescaler)
Initializes the FTM. This function will enable the flexTimer module and selects one pre-scale factor ...
Definition: ftm_hal.c:43
static void FTM_HAL_SetFaultInputCmd(FTM_Type *const ftmBase, uint8_t inputNum, bool enable)
Enables or disables the fault input.
Definition: ftm_hal.h:2311
#define FTM_FMS_FAULTF2(x)
Definition: S32K144.h:4592
#define FTM_SC_PS(x)
Definition: S32K144.h:4077
#define FTM_COMBINE_DECAPEN0_MASK
Definition: S32K144.h:4373
static bool FTM_HAL_GetDualEdgeCaptureBit(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Enables the FTM peripheral timer dual edge capture mode.
Definition: ftm_hal.h:1807
#define FTM_CnSC_MSB(x)
Definition: S32K144.h:4172
#define FTM_SYNCONF_CNTINC(x)
Definition: S32K144.h:4746
#define FTM_SC_CPWMS_SHIFT
Definition: S32K144.h:4083
static void FTM_HAL_SetOutmaskReg(FTM_Type *const ftmBase, uint32_t regVal)
Writes the provided value to the OUTMASK register.
Definition: ftm_hal.h:1228
static void FTM_HAL_SetFaultControlMode(FTM_Type *const ftmBase, ftm_fault_mode_t mode)
Defines the FTM fault control mode.
Definition: ftm_hal.h:1413
static void FTM_HAL_SetDualChnInvertCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the channel invert for a channel pair.
Definition: ftm_hal.h:2361
#define FTM_SYNC_REINIT_MASK
Definition: S32K144.h:4274
#define FTM_SYNCONF_SWSOC_MASK
Definition: S32K144.h:4775
static void FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM MOD, CNTIN and CV registers when using a software trigger. ...
Definition: ftm_hal.h:2822
static void FTM_HAL_SetLoadFreq(FTM_Type *const ftmBase, uint8_t val)
Sets the FTM timer TOF Frequency.
Definition: ftm_hal.h:2677
static void FTM_HAL_SetInvctrlSoftwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM INVCTRL register when using a software trigger.
Definition: ftm_hal.h:2790
#define FTM_FMS_FAULTF3_MASK
Definition: S32K144.h:4593
static void FTM_HAL_SetSoftwareTriggerCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer software trigger.
Definition: ftm_hal.h:1532
#define FTM_SYNC_CNTMIN(x)
Definition: S32K144.h:4269
#define FTM_FMS_FAULTF1(x)
Definition: S32K144.h:4588
#define FTM_CnSC_CHIS_MASK
Definition: S32K144.h:4185
#define FTM_PAIR0DEADTIME_DTPS(x)
Definition: S32K144.h:4943
#define FTM_CONF_GTBEEN(x)
Definition: S32K144.h:4712
static void FTM_HAL_SetMod(FTM_Type *const ftmBase, uint16_t value)
Sets the FTM peripheral timer modulo value.
Definition: ftm_hal.h:724
#define FTM_SYNCONF_SWRSTCNT_MASK
Definition: S32K144.h:4759
#define FTM_CnSC_TRIGMODE_MASK
Definition: S32K144.h:4181
__IO uint32_t FMS
Definition: S32K144.h:4000
#define FTM_CONF_ITRIGR(x)
Definition: S32K144.h:4720
static void FTM_HAL_SetDualChnCompCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, ftm_second_channel_polarity_t polarity)
Enables or disables the FTM peripheral timer channel pair output complement mode. ...
Definition: ftm_hal.h:1826
static void FTM_HAL_SetCounterInitVal(FTM_Type *const ftmBase, uint16_t value)
Sets the FTM peripheral timer counter initial value.
Definition: ftm_hal.h:752
static void FTM_HAL_SetCounterHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM counter register when using a hardware trigger.
Definition: ftm_hal.h:2758
static void FTM_HAL_SetChnMSnBAMode(FTM_Type *const ftmBase, uint8_t channel, uint8_t selection)
Sets the FTM peripheral timer channel mode.
Definition: ftm_hal.h:781
static void FTM_HAL_SetOutmaskSoftwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM OUTMASK register when using a software trigger.
Definition: ftm_hal.h:2806
#define FTM_CONF_LDFQ_MASK
Definition: S32K144.h:4701
#define FTM_DEADTIME_DTVALEX_MASK
Definition: S32K144.h:4502
#define FTM_RMW_PAIR2DEADTIME(base, mask, value)
FTM_PAIR2DEADTIME - Read and modify and write Dead-time Insertion Control for the pair 2 (RW) ...
Definition: ftm_hal.h:219
static void FTM_HAL_SetQuadMode(FTM_Type *const ftmBase, ftm_quad_decode_mode_t quadMode)
Sets the encoding mode used in quadrature decoding mode.
Definition: ftm_hal.h:2209
#define FTM_FLTCTRL_FFVAL(x)
Definition: S32K144.h:4662
ftm_clock_source_t
FlexTimer clock source selection.
Definition: ftm_hal.h:254
#define FTM_FMS_FAULTIN_MASK
Definition: S32K144.h:4597
#define FTM_CnSC_ICRST(x)
Definition: S32K144.h:4156
#define FTM_EXTTRIG_TRIGF(x)
Definition: S32K144.h:4538
static bool FTM_HAL_GetDualChnMofCombineCmd(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Verify if an channels pair is used in the modified combine mode or not.
Definition: ftm_hal.h:1901
#define FTM_SC_RIE(x)
Definition: S32K144.h:4089
#define FTM_PAIR2DEADTIME_DTVAL(x)
Definition: S32K144.h:4965
#define FTM_SYNC_REINIT(x)
Definition: S32K144.h:4277
#define FTM_CnSC_ICRST_MASK
Definition: S32K144.h:4153
#define FTM_PAIR1DEADTIME_DTVALEX_MASK
Definition: S32K144.h:4957
#define FTM_MODE_FTMEN_SHIFT
Definition: S32K144.h:4238
static void FTM_HAL_SetChnIcrstCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Configure the feature of FTM counter reset by the selected input capture event.
Definition: ftm_hal.h:893
static void FTM_HAL_SetDeadtimeCount(FTM_Type *const ftmBase, uint8_t count)
Sets the FTM deadtime value.
Definition: ftm_hal.h:1953
#define FTM_MODE_FAULTM(x)
Definition: S32K144.h:4260
#define FTM_FMS_WPEN(x)
Definition: S32K144.h:4604
static uint8_t FTM_HAL_GetClockSource(const FTM_Type *ftmBase)
Reads the FTM clock source.
Definition: ftm_hal.h:483
static void FTM_HAL_SetChnFaultInputPolarityCmd(FTM_Type *const ftmBase, uint8_t fltChannel, ftm_polarity_t polarity)
Sets the FTM peripheral timer channel fault input polarity.
Definition: ftm_hal.h:1326
#define FTM_CnSC_DMA_MASK
Definition: S32K144.h:4149
#define FTM_SWOCTRL_CH7OCV_MASK
Definition: S32K144.h:4877
static bool FTM_HAL_GetChnEventStatus(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel event status.
Definition: ftm_hal.h:1176
#define FTM_CnSC_MSA_MASK
Definition: S32K144.h:4165
#define FTM_SC_RF_SHIFT
Definition: S32K144.h:4091
#define FTM_SWOCTRL_CH5OCV_MASK
Definition: S32K144.h:4869
static void FTM_HAL_SetOutmaskHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM OUTMASK register when using a hardware trigger.
Definition: ftm_hal.h:2726
void FTM_HAL_Reset(FTM_Type *const ftmBase)
Resets the FTM registers. All the register use in the driver should be reset to default value of each...
Definition: ftm_hal.c:59
#define FTM_SYNCONF_SYNCMODE(x)
Definition: S32K144.h:4758
__IO uint32_t QDCTRL
Definition: S32K144.h:4003
#define FTM_SYNCONF_HWRSTCNT(x)
Definition: S32K144.h:4782
#define FTM_PAIR2DEADTIME_DTVALEX(x)
Definition: S32K144.h:4973
#define FTM_DEADTIME_DTVAL(x)
Definition: S32K144.h:4497
#define FTM_RMW_EXTTRIG_REG(base, mask, value)
FTM_EXTTRIG - Read and modify and write External Trigger Control (RW)
Definition: ftm_hal.h:169
#define FTM_FLTCTRL_FFVAL_MASK
Definition: S32K144.h:4659
static bool FTM_HAL_IsWriteProtectionEnabled(const FTM_Type *ftmBase)
Checks whether the write protection is enabled.
Definition: ftm_hal.h:2036
static void FTM_HAL_SetHalfCycleCmd(FTM_Type *const ftmBase, bool enable)
Enable the half cycle reload.
Definition: ftm_hal.h:2531
#define FTM_PAIR0DEADTIME_DTVAL(x)
Definition: S32K144.h:4939
#define FTM_RMW_DEADTIME(base, mask, value)
FTM_DEADTIME - Read and modify and write Dead-time Insertion Control (RW)
Definition: ftm_hal.h:165
static void FTM_HAL_SetMaxLoadingCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer maximum loading points.
Definition: ftm_hal.h:1611
#define FTM_CNT_COUNT_SHIFT
Definition: S32K144.h:4140
#define FTM_RMW_PAIR0DEADTIME(base, mask, value)
FTM_PAIR0DEADTIME - Read and modify and write Dead-time Insertion Control for the pair 0 (RW) ...
Definition: ftm_hal.h:209
#define CHAN2_IDX
Channel number for CHAN3.
Definition: ftm_hal.h:233
static void FTM_HAL_SetInitChnOutputCmd(FTM_Type *const ftmBase, bool enable)
Initializes the channels output.
Definition: ftm_hal.h:1499
#define FTM_QDCTRL_PHAPOL_MASK
Definition: S32K144.h:4688
#define FTM_SWOCTRL_CH0OC_MASK
Definition: S32K144.h:4817
#define FTM_CONF_LDFQ(x)
Definition: S32K144.h:4704
#define FTM_PWMLOAD_LDOK_SHIFT
Definition: S32K144.h:4919
static void FTM_HAL_SetAllChnSoftwareCtrlVal(FTM_Type *const ftmBase, uint8_t channelsValues)
Sets the channel software output control value.
Definition: ftm_hal.h:2474
#define FTM_MODE_FTMEN_MASK
Definition: S32K144.h:4237
#define FTM_SWOCTRL_CH7OC_MASK
Definition: S32K144.h:4845
#define FTM_SYNCONF_HWINVC(x)
Definition: S32K144.h:4794
static void FTM_HAL_SetPwmSyncModeCmd(FTM_Type *const ftmBase, bool mode)
Sets the PWM synchronization mode to enhanced or legacy.
Definition: ftm_hal.h:2870
__IO uint32_t SC
Definition: S32K144.h:3983
#define FTM_PAIR2DEADTIME_DTPS_MASK
Definition: S32K144.h:4966
static uint8_t FTM_HAL_GetClockPs(const FTM_Type *ftmBase)
Reads the FTM clock divider.
Definition: ftm_hal.h:511
static uint16_t FTM_HAL_GetChnCountVal(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel counter value.
Definition: ftm_hal.h:1156
#define FTM_FLTCTRL_FSTATE_SHIFT
Definition: S32K144.h:4664
#define FTM_PAIR2DEADTIME_DTVAL_MASK
Definition: S32K144.h:4962
#define FTM_SYNCONF_HWWRBUF_MASK
Definition: S32K144.h:4783
static void FTM_HAL_SetHwTriggerSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets hardware trigger mode.
Definition: ftm_hal.h:2838
#define FTM_RMW_MODE(base, mask, value)
FTM_MODE - Read and modify and write Counter Features Mode Selection (RW)
Definition: ftm_hal.h:155
#define FTM_FMS_FAULTF(x)
Definition: S32K144.h:4608
#define CHAN0_IDX
Channel number for CHAN1.
Definition: ftm_hal.h:229
static void FTM_HAL_SetQuadPhaseAPolarity(FTM_Type *const ftmBase, ftm_quad_phase_polarity_t mode)
Selects polarity for the quadrature decode phase A input.
Definition: ftm_hal.h:2177
#define FTM_CnSC_MSB_MASK
Definition: S32K144.h:4169
#define FTM_CNT_COUNT_MASK
Definition: S32K144.h:4139
#define FTM_MODE_FTMEN(x)
Definition: S32K144.h:4240
static bool FTM_HAL_HasChnEventOccurred(const FTM_Type *ftmBase, uint8_t channel)
Returns whether any event for the FTM peripheral timer channel has occurred.
Definition: ftm_hal.h:1021
#define FTM_RMW_CNTIN(base, mask, value)
FTM_CNTIN - Read and modify and write Counter Initial Value (RW)
Definition: ftm_hal.h:145
static void FTM_HAL_SetQuadPhaseBPolarity(FTM_Type *const ftmBase, ftm_quad_phase_polarity_t mode)
Selects polarity for the quadrature decode phase B input.
Definition: ftm_hal.h:2193
static void FTM_HAL_SetClockSource(FTM_Type *const ftmBase, ftm_clock_source_t clock)
Sets the FTM clock source.
Definition: ftm_hal.h:464
#define FTM_SC_FLTPS_SHIFT
Definition: S32K144.h:4135
static uint16_t FTM_HAL_GetCounter(const FTM_Type *ftmBase)
Returns the FTM peripheral current counter value.
Definition: ftm_hal.h:711
#define FTM_SYNC_SWSYNC_MASK
Definition: S32K144.h:4294
#define FTM_SYNCONF_SWOC(x)
Definition: S32K144.h:4754
static void FTM_HAL_SetCounter(FTM_Type *const ftmBase, uint16_t value)
Sets the FTM peripheral current counter value.
Definition: ftm_hal.h:696
ftm_clock_ps_t
FlexTimer pre-scaler factor selection for the clock source. In quadrature decoder mode set FTM_CLOCK_...
Definition: ftm_hal.h:268
#define FTM_SYNCONF_SWWRBUF(x)
Definition: S32K144.h:4766
#define FTM_FMS_FAULTF2_MASK
Definition: S32K144.h:4589
static void FTM_HAL_SetDualEdgeCaptureCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables the FTM peripheral timer dual edge capture mode.
Definition: ftm_hal.h:1779
#define FTM_PAIR0DEADTIME_DTVALEX(x)
Definition: S32K144.h:4947