S32 SDK
scg_spll_config_t Struct Reference

SCG system PLL configuration. Implements scg_spll_config_t_Class. More...

#include <scg_hal.h>

Data Fields

scg_spll_monitor_mode_t monitorMode
 
uint8_t prediv
 
uint8_t mult
 
uint8_t src
 
scg_async_clock_div_t div1
 
scg_async_clock_div_t div2
 
bool enableInStop
 
bool locked
 
bool initialize
 

Detailed Description

SCG system PLL configuration. Implements scg_spll_config_t_Class.

Definition at line 324 of file scg_hal.h.

Field Documentation

Divider for platform asynchronous clock.

Definition at line 332 of file scg_hal.h.

Divider for bus asynchronous clock.

Definition at line 333 of file scg_hal.h.

bool enableInStop

System PLL clock is enable or not in stop mode.

Definition at line 335 of file scg_hal.h.

bool initialize

Initialize or not the System PLL module.

Definition at line 338 of file scg_hal.h.

bool locked

System PLL Control Register can be written.

Definition at line 337 of file scg_hal.h.

Clock monitor mode selected.

Definition at line 326 of file scg_hal.h.

uint8_t mult

System PLL multiplier.

Definition at line 329 of file scg_hal.h.

uint8_t prediv

PLL reference clock divider.

Definition at line 328 of file scg_hal.h.

uint8_t src

System PLL source.

Definition at line 330 of file scg_hal.h.


The documentation for this struct was generated from the following file: