S32 SDK
edma_hal.h
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1 /*
2  * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
35 #ifndef EDMA_HAL_H
36 #define EDMA_HAL_H
37 
38 #include <stdint.h>
39 #include <stdbool.h>
40 #include "device_registers.h"
41 
47 /*******************************************************************************
48  * Definitions
49  ******************************************************************************/
50 
54 typedef enum {
58 
62 typedef enum {
81 
82 #if FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U
83 
86 typedef enum {
87  EDMA_GRP0_PRIO_LOW_GRP1_PRIO_HIGH = 0U,
88  EDMA_GRP0_PRIO_HIGH_GRP1_PRIO_LOW = 1U
89 } edma_group_priority_t;
90 #endif
91 
94 typedef enum {
127 } edma_modulo_t;
128 
132 typedef enum {
139 
143 typedef enum {
148 
149 /*******************************************************************************
150  * API
151  ******************************************************************************/
152 
153 #if defined(__cplusplus)
154 extern "C" {
155 #endif
156 
167 void EDMA_HAL_Init(DMA_Type * base);
168 
180 void EDMA_HAL_CancelTransfer(DMA_Type * base);
181 
195 
206 static inline void EDMA_HAL_SetHaltCmd(DMA_Type * base, bool halt)
207 {
208  uint32_t regValTemp;
209  regValTemp = base->CR;
210  regValTemp &= ~(DMA_CR_HALT_MASK);
211  regValTemp |= DMA_CR_HALT(halt ? 1UL : 0UL);
212  base->CR = regValTemp;
213 }
214 
225 static inline void EDMA_HAL_SetHaltOnErrorCmd(DMA_Type * base, bool haltOnError)
226 {
227  uint32_t regValTemp;
228  regValTemp = base->CR;
229  regValTemp &= ~(DMA_CR_HOE_MASK);
230  regValTemp |= DMA_CR_HOE(haltOnError ? 1UL : 0UL);
231  base->CR = regValTemp;
232 }
233 
246 static inline void EDMA_HAL_SetDebugCmd(DMA_Type * base, bool enable)
247 {
248  uint32_t regValTemp;
249  regValTemp = base->CR;
250  regValTemp &= ~(DMA_CR_EDBG_MASK);
251  regValTemp |= DMA_CR_EDBG(enable ? 1UL : 0UL);
252  base->CR = regValTemp;
253 }
254 /* @} */
255 
270 static inline bool EDMA_HAL_GetValidErrorNotCleared(const DMA_Type * base)
271 {
272  return (((base->ES & DMA_ES_VLD_MASK) >> DMA_ES_VLD_SHIFT) != 0U);
273 }
274 
285 static inline bool EDMA_HAL_GetTransferCancelledError(const DMA_Type * base)
286 {
287  return (((base->ES & DMA_ES_ECX_MASK) >> DMA_ES_ECX_SHIFT) != 0U);
288 }
289 
300 static inline bool EDMA_HAL_GetChannelPriorityError(const DMA_Type * base)
301 {
302  return (((base->ES & DMA_ES_CPE_MASK) >> DMA_ES_CPE_SHIFT) != 0U);
303 }
304 
314 static inline bool EDMA_HAL_GetSourceAddressError(const DMA_Type * base)
315 {
316  return (((base->ES & DMA_ES_SAE_MASK) >> DMA_ES_SAE_SHIFT) != 0U);
317 }
318 
328 static inline bool EDMA_HAL_GetSourceOffsetError(const DMA_Type * base)
329 {
330  return (((base->ES & DMA_ES_SOE_MASK) >> DMA_ES_SOE_SHIFT) != 0U);
331 }
332 
342 static inline bool EDMA_HAL_GetDestinationAddressError(const DMA_Type * base)
343 {
344  return (((base->ES & DMA_ES_DAE_MASK) >> DMA_ES_DAE_SHIFT) != 0U);
345 }
346 
356 static inline bool EDMA_HAL_GetDestinationOffsetError(const DMA_Type * base)
357 {
358  return (((base->ES & DMA_ES_DOE_MASK) >> DMA_ES_DOE_SHIFT) != 0U);
359 }
360 
370 static inline bool EDMA_HAL_GetMinorMajorLoopConfigError(const DMA_Type * base)
371 {
372  return (((base->ES & DMA_ES_NCE_MASK) >> DMA_ES_NCE_SHIFT) != 0U);
373 }
374 
384 static inline bool EDMA_HAL_GetScatterGatherError(const DMA_Type * base)
385 {
386  return (((base->ES & DMA_ES_SGE_MASK) >> DMA_ES_SGE_SHIFT) != 0U);
387 }
388 
398 static inline bool EDMA_HAL_GetSourceBusError(const DMA_Type * base)
399 {
400  return (((base->ES & DMA_ES_SBE_MASK) >> DMA_ES_SBE_SHIFT) != 0U);
401 }
402 
412 static inline bool EDMA_HAL_GetDestinationBusError(const DMA_Type * base)
413 {
414  return (((base->ES & DMA_ES_DBE_MASK) >> DMA_ES_DBE_SHIFT) != 0U);
415 }
416 
426 static inline uint8_t EDMA_HAL_GetChannelWithError(const DMA_Type * base)
427 {
428  return (uint8_t)(((base->ES >> DMA_ES_ERRCHN_SHIFT) & 0xFU));
429 }
430 /* @} */
431 
450 static inline void EDMA_HAL_SetChannelPreemptMode(DMA_Type * base, uint32_t channel, bool preemptive, bool preemptible)
451 {
452 #ifdef DEV_ERROR_DETECT
454 #endif
455 
456  uint8_t regValTemp;
457  uint32_t index = FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(channel);
458  regValTemp = base->DCHPRI[index];
459  regValTemp &= (uint8_t)~(DMA_DCHPRI_DPA_MASK);
460  regValTemp |= (uint8_t)DMA_DCHPRI_DPA(preemptive ? 0UL : 1UL);
461  regValTemp &= (uint8_t)~(DMA_DCHPRI_ECP_MASK);
462  regValTemp |= (uint8_t)DMA_DCHPRI_ECP(preemptible ? 1UL : 0UL);
463  base->DCHPRI[index] = regValTemp;
464 }
465 
475 static inline void EDMA_HAL_SetChannelPriority(DMA_Type * base, uint32_t channel, edma_channel_priority_t priority)
476 {
477 #ifdef DEV_ERROR_DETECT
479 #endif
480 
481  uint8_t regValTemp;
482  uint32_t index = FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(channel);
483  regValTemp = base->DCHPRI[index];
484  regValTemp &= (uint8_t)~(DMA_DCHPRI_CHPRI_MASK);
485  regValTemp |= (uint8_t)DMA_DCHPRI_CHPRI(priority);
486  base->DCHPRI[index] = regValTemp;
487 }
488 
496 static inline void EDMA_HAL_SetChannelArbitrationMode(DMA_Type * base, edma_arbitration_algorithm_t channelArbitration)
497 {
498  uint32_t regValTemp;
499  regValTemp = base->CR;
500  regValTemp &= ~(DMA_CR_ERCA_MASK);
501  regValTemp |= DMA_CR_ERCA(channelArbitration);
502  base->CR = regValTemp;
503 }
504 
513 {
515 }
516 
517 #if FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U
518 
524 void EDMA_HAL_SetGroupPriority(DMA_Type * base, edma_group_priority_t priority);
525 
533 static inline edma_group_priority_t EDMA_HAL_GetGroupPriority(DMA_Type * base)
534 {
535  return (edma_group_priority_t)(((base->CR & DMA_CR_GRP0PRI_MASK) > 0) ? \
536  EDMA_GRP0_PRIO_HIGH_GRP1_PRIO_LOW : EDMA_GRP0_PRIO_LOW_GRP1_PRIO_HIGH);
537 }
538 
546 static inline void EDMA_HAL_SetGroupArbitrationMode(DMA_Type * base, edma_arbitration_algorithm_t groupArbitration)
547 {
548  uint32_t regValTemp;
549  regValTemp = base->CR;
550  regValTemp &= ~(DMA_CR_ERGA_MASK);
551  regValTemp |= DMA_CR_ERGA(groupArbitration);
552  base->CR = regValTemp;
553 }
554 
562 static inline edma_arbitration_algorithm_t EDMA_HAL_GetGroupArbitrationMode(DMA_Type * base)
563 {
565 }
566 #endif
567 
584 static inline void EDMA_HAL_SetMinorLoopMappingCmd(DMA_Type * base, bool enable)
585 {
586  uint32_t regValTemp;
587  regValTemp = base->CR;
588  regValTemp &= ~(DMA_CR_EMLM_MASK);
589  regValTemp |= DMA_CR_EMLM(enable ? 1UL : 0UL);
590  base->CR = regValTemp;
591 }
592 
605 static inline void EDMA_HAL_SetContinuousLinkCmd(DMA_Type * base, bool continuous)
606 {
607  uint32_t regValTemp;
608  regValTemp = base->CR;
609  regValTemp &= ~(DMA_CR_CLM_MASK);
610  regValTemp |= DMA_CR_CLM(continuous ? 1UL : 0UL);
611  base->CR = regValTemp;
612 }
613 
622 void EDMA_HAL_SetErrorIntCmd(DMA_Type * base, uint8_t channel, bool enable);
623 
632 static inline uint32_t EDMA_HAL_GetErrorIntStatusFlag(const DMA_Type * base)
633 {
634  return base->ERR;
635 }
636 
645 static inline void EDMA_HAL_ClearErrorIntStatusFlag(DMA_Type * base, uint8_t channel)
646 {
647 #ifdef DEV_ERROR_DETECT
649 #endif
650  base->CERR = (uint8_t)channel;
651 }
652 
661 void EDMA_HAL_SetDmaRequestCmd(DMA_Type * base, uint8_t channel,bool enable);
662 
672 static inline bool EDMA_HAL_GetDmaRequestStatusFlag(const DMA_Type * base, uint32_t channel)
673 {
674 #ifdef DEV_ERROR_DETECT
676 #endif
677  return (((base->HRS >> channel) & 1U) != 0U);
678 }
679 
688 static inline void EDMA_HAL_ClearDoneStatusFlag(DMA_Type * base, uint8_t channel)
689 {
690 #ifdef DEV_ERROR_DETECT
692 #endif
693  base->CDNE = (uint8_t)channel;
694 }
695 
703 static inline void EDMA_HAL_TriggerChannelStart(DMA_Type * base, uint8_t channel)
704 {
705 #ifdef DEV_ERROR_DETECT
707 #endif
708  base->SSRT = (uint8_t)channel;
709 }
710 
720 static inline bool EDMA_HAL_GetIntStatusFlag(const DMA_Type * base, uint32_t channel)
721 {
722 #ifdef DEV_ERROR_DETECT
724 #endif
725 
726  return (((base->INT >> channel) & 1U) != 0U);
727 }
728 
737 static inline void EDMA_HAL_ClearIntStatusFlag(DMA_Type * base, uint8_t channel)
738 {
739 #ifdef DEV_ERROR_DETECT
741 #endif
742  base->CINT = (uint8_t)channel;
743 }
744 
745 #ifdef FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT
746 #if (FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U)
747 
755 static inline void EDMA_HAL_SetAsyncRequestInStopModeCmd(DMA_Type * base, uint32_t channel, bool enable)
756 {
757 #ifdef DEV_ERROR_DETECT
759 #endif
760  uint32_t regValTemp;
761  uint32_t channelMask;
762  regValTemp = base->EARS;
763  channelMask = (uint32_t)(1U << channel);
764  regValTemp &= ~(channelMask);
765  regValTemp |= (((uint32_t)((enable ? 1U : 0U) << channel)) & channelMask);
766  base->EARS = regValTemp;
767 }
768 #endif
769 #endif
770 
771 /* @} */
772 
784 void EDMA_HAL_TCDClearReg(DMA_Type * base, uint32_t channel);
785 
794 static inline void EDMA_HAL_TCDSetSrcAddr(DMA_Type * base, uint32_t channel, uint32_t address)
795 {
796 #ifdef DEV_ERROR_DETECT
798 #endif
799  base->TCD[channel].SADDR = address;
800 }
801 
813 static inline void EDMA_HAL_TCDSetSrcOffset(DMA_Type * base, uint32_t channel, int16_t offset)
814 {
815 #ifdef DEV_ERROR_DETECT
817 #endif
818  base->TCD[channel].SOFF = (uint16_t)offset;
819 }
820 
840  DMA_Type * base, uint32_t channel,
841  edma_modulo_t srcModulo, edma_modulo_t destModulo,
842  edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize);
843 
854 void EDMA_HAL_TCDSetNbytes(DMA_Type * base, uint32_t channel, uint32_t nbytes);
855 
866 uint32_t EDMA_HAL_TCDGetNbytes(const DMA_Type * base, uint32_t channel);
867 
881 static inline void EDMA_HAL_TCDSetSrcMinorLoopOffsetCmd(DMA_Type * base, uint32_t channel, bool enable)
882 {
883 #ifdef DEV_ERROR_DETECT
885 #endif
886 
887  if (((base->CR >> DMA_CR_EMLM_SHIFT) & 1U) != 0U)
888  {
889  uint32_t regValTemp;
890  regValTemp = base->TCD[channel].NBYTES.MLOFFYES;
891  regValTemp &= ~(DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK);
892  regValTemp |= DMA_TCD_NBYTES_MLOFFYES_SMLOE(enable ? 1UL : 0UL);
893  base->TCD[channel].NBYTES.MLOFFYES = regValTemp;
894  }
895 }
896 
910 static inline void EDMA_HAL_TCDSetDestMinorLoopOffsetCmd(DMA_Type * base, uint32_t channel, bool enable)
911 {
912 #ifdef DEV_ERROR_DETECT
914 #endif
915 
916  if (((base->CR >> DMA_CR_EMLM_SHIFT) & 1U) != 0U)
917  {
918  uint32_t regValTemp;
919  regValTemp = base->TCD[channel].NBYTES.MLOFFYES;
920  regValTemp &= ~(DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK);
921  regValTemp |= DMA_TCD_NBYTES_MLOFFYES_DMLOE(enable ? 1UL : 0UL);
922  base->TCD[channel].NBYTES.MLOFFYES = regValTemp;
923  }
924 }
925 
938 void EDMA_HAL_TCDSetMinorLoopOffset(DMA_Type * base, uint32_t channel, int32_t offset);
939 
952 static inline void EDMA_HAL_TCDSetSrcLastAdjust(DMA_Type * base, uint32_t channel, int32_t size)
953 {
954 #ifdef DEV_ERROR_DETECT
956 #endif
957  base->TCD[channel].SLAST = (uint32_t)size;
958 }
959 
968 static inline void EDMA_HAL_TCDSetDestAddr(DMA_Type * base, uint32_t channel, uint32_t address)
969 {
970 #ifdef DEV_ERROR_DETECT
972 #endif
973  base->TCD[channel].DADDR = address;
974 }
975 
987 static inline void EDMA_HAL_TCDSetDestOffset(DMA_Type * base, uint32_t channel, int16_t offset)
988 {
989 #ifdef DEV_ERROR_DETECT
991 #endif
992  base->TCD[channel].DOFF = (uint16_t)offset;
993 }
994 
1007 static inline void EDMA_HAL_TCDSetDestLastAdjust(DMA_Type * base, uint32_t channel, int32_t adjust)
1008 {
1009 #ifdef DEV_ERROR_DETECT
1011 #endif
1012  base->TCD[channel].DLASTSGA = (uint32_t)adjust;
1013 }
1014 
1029 void EDMA_HAL_TCDSetScatterGatherLink(DMA_Type * base, uint32_t channel, uint32_t nextTCDAddr);
1030 
1044 static inline void EDMA_HAL_TCDSetBandwidth(DMA_Type * base, uint32_t channel, edma_bandwidth_config_t bandwidth)
1045 {
1046 #ifdef DEV_ERROR_DETECT
1048 #endif
1049  uint16_t regValTemp;
1050  regValTemp = base->TCD[channel].CSR;
1051  regValTemp &= (uint16_t)~(DMA_TCD_CSR_BWC_MASK);
1052  regValTemp |= (uint16_t)DMA_TCD_CSR_BWC(bandwidth);
1053  base->TCD[channel].CSR = regValTemp;
1054 }
1055 
1069 static inline void EDMA_HAL_TCDSetChannelMajorLink(DMA_Type * base, uint32_t channel, uint32_t majorLinkChannel, bool enable)
1070 {
1071 #ifdef DEV_ERROR_DETECT
1073 #endif
1074  uint16_t regValTemp;
1075  regValTemp = base->TCD[channel].CSR;
1076  regValTemp &= (uint16_t)~(DMA_TCD_CSR_MAJORLINKCH_MASK);
1077  regValTemp |= (uint16_t)DMA_TCD_CSR_MAJORLINKCH(majorLinkChannel);
1078  base->TCD[channel].CSR = regValTemp;
1079 
1080  regValTemp = base->TCD[channel].CSR;
1081  regValTemp &= (uint16_t)~(DMA_TCD_CSR_MAJORELINK_MASK);
1082  regValTemp |= (uint16_t)DMA_TCD_CSR_MAJORELINK(enable ? 1UL : 0UL);
1083  base->TCD[channel].CSR = regValTemp;
1084 }
1085 
1094 static inline void EDMA_HAL_TCDSetScatterGatherCmd(DMA_Type * base, uint32_t channel, bool enable)
1095 {
1096 #ifdef DEV_ERROR_DETECT
1098 #endif
1099  uint16_t regValTemp;
1100  regValTemp = base->TCD[channel].CSR;
1101  regValTemp &= (uint16_t)~(DMA_TCD_CSR_ESG_MASK);
1102  regValTemp |= (uint16_t)DMA_TCD_CSR_ESG(enable ? 1UL : 0UL);
1103  base->TCD[channel].CSR = regValTemp;
1104 }
1105 
1117 static inline void EDMA_HAL_TCDSetDisableDmaRequestAfterTCDDoneCmd(DMA_Type * base, uint32_t channel, bool disable)
1118 {
1119 #ifdef DEV_ERROR_DETECT
1121 #endif
1122  uint16_t regValTemp;
1123  regValTemp = base->TCD[channel].CSR;
1124  regValTemp &= (uint16_t)~(DMA_TCD_CSR_DREQ_MASK);
1125  regValTemp |= (uint16_t)DMA_TCD_CSR_DREQ(disable ? 1UL : 0UL);
1126  base->TCD[channel].CSR = regValTemp;
1127 }
1128 
1143 static inline void EDMA_HAL_TCDSetHalfCompleteIntCmd(DMA_Type * base, uint32_t channel, bool enable)
1144 {
1145 #ifdef DEV_ERROR_DETECT
1147 #endif
1148  uint16_t regValTemp;
1149  regValTemp = base->TCD[channel].CSR;
1150  regValTemp &= (uint16_t)~(DMA_TCD_CSR_INTHALF_MASK);
1151  regValTemp |= (uint16_t)DMA_TCD_CSR_INTHALF(enable ? 1UL : 0UL);
1152  base->TCD[channel].CSR = regValTemp;
1153 }
1154 
1166 static inline void EDMA_HAL_TCDSetIntCmd(DMA_Type * base, uint32_t channel, bool enable)
1167 {
1168 #ifdef DEV_ERROR_DETECT
1170 #endif
1171  uint16_t regValTemp;
1172  regValTemp = base->TCD[channel].CSR;
1173  regValTemp &= (uint16_t)~(DMA_TCD_CSR_INTMAJOR_MASK);
1174  regValTemp |= (uint16_t)DMA_TCD_CSR_INTMAJOR(enable ? 1UL : 0UL);
1175  base->TCD[channel].CSR = regValTemp;
1176 }
1177 
1187 static inline void EDMA_HAL_TCDTriggerChannelStart(DMA_Type * base, uint32_t channel)
1188 {
1189 #ifdef DEV_ERROR_DETECT
1191 #endif
1192  uint32_t regValTemp;
1193  regValTemp = base->TCD[channel].CSR;
1194  regValTemp &= ~(DMA_TCD_CSR_START_MASK);
1195  regValTemp |= DMA_TCD_CSR_START(1U);
1196  base->TCD[channel].CSR = (uint16_t) regValTemp;
1197 }
1198 
1207 static inline bool EDMA_HAL_TCDGetChannelActiveStatus(const DMA_Type * base, uint32_t channel)
1208 {
1209 #ifdef DEV_ERROR_DETECT
1211 #endif
1212  return (((base->TCD[channel].CSR & DMA_TCD_CSR_ACTIVE_MASK) >> DMA_TCD_CSR_ACTIVE_SHIFT) != 0U);
1213 }
1214 
1223 void EDMA_HAL_TCDSetChannelMinorLink(DMA_Type * base, uint32_t channel, uint32_t linkChannel, bool enable);
1224 
1235 void EDMA_HAL_TCDSetMajorCount(DMA_Type * base, uint32_t channel, uint32_t count);
1236 
1246 uint32_t EDMA_HAL_TCDGetBeginMajorCount(const DMA_Type * base, uint32_t channel);
1247 
1257 uint32_t EDMA_HAL_TCDGetCurrentMajorCount(const DMA_Type * base, uint32_t channel);
1258 
1266 uint32_t EDMA_HAL_TCDGetFinishedBytes(const DMA_Type * base, uint32_t channel);
1267 
1275 uint32_t EDMA_HAL_TCDGetUnfinishedBytes(const DMA_Type * base, uint32_t channel);
1276 
1285 static inline bool EDMA_HAL_TCDGetDoneStatusFlag(const DMA_Type * base, uint32_t channel)
1286 {
1287 #ifdef DEV_ERROR_DETECT
1289 #endif
1290  return (((base->TCD[channel].CSR & DMA_TCD_CSR_DONE_MASK) >> DMA_TCD_CSR_DONE_SHIFT) != 0U);
1291 }
1292 
1295 #if defined(__cplusplus)
1296 }
1297 #endif
1298 
1301 #endif /* EDMA_HAL_H */
1302 
1303 /*******************************************************************************
1304  * EOF
1305  ******************************************************************************/
1306 
1307 
static void EDMA_HAL_TCDSetSrcAddr(DMA_Type *base, uint32_t channel, uint32_t address)
Configures the source address for the hardware TCD.
Definition: edma_hal.h:794
#define DMA_TCD_CSR_BWC(x)
Definition: S32K144.h:3062
static void EDMA_HAL_TCDSetChannelMajorLink(DMA_Type *base, uint32_t channel, uint32_t majorLinkChannel, bool enable)
Configures the major channel link the TCD.
Definition: edma_hal.h:1069
void EDMA_HAL_TCDSetScatterGatherLink(DMA_Type *base, uint32_t channel, uint32_t nextTCDAddr)
Configures the memory address for the next transfer TCD for the TCD.
Definition: edma_hal.c:332
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
Definition: S32K144.h:2972
#define DMA_CR_EMLM_SHIFT
Definition: S32K144.h:2351
#define DMA_ES_SGE_SHIFT
Definition: S32K144.h:2372
static void EDMA_HAL_SetContinuousLinkCmd(DMA_Type *base, bool continuous)
Enables or disables the continuous transfer mode.
Definition: edma_hal.h:605
#define DMA_DCHPRI_CHPRI_MASK
Definition: S32K144.h:2906
#define DMA_TCD_CSR_INTHALF_MASK
Definition: S32K144.h:3031
#define DMA_TCD_CSR_DONE_MASK
Definition: S32K144.h:3051
#define DMA_TCD_CSR_BWC_MASK
Definition: S32K144.h:3059
#define DMA_CR_EMLM_MASK
Definition: S32K144.h:2350
#define DMA_ES_DAE_SHIFT
Definition: S32K144.h:2384
__IO uint32_t SADDR
Definition: S32K144.h:2273
__O uint8_t SSRT
Definition: S32K144.h:2258
static bool EDMA_HAL_GetSourceAddressError(const DMA_Type *base)
Checks for source address errors.
Definition: edma_hal.h:314
__I uint32_t HRS
Definition: S32K144.h:2266
static bool EDMA_HAL_GetTransferCancelledError(const DMA_Type *base)
Checks for cancelled transfers.
Definition: edma_hal.h:285
#define DMA_ES_SOE_MASK
Definition: S32K144.h:2387
#define DMA_ES_DBE_MASK
Definition: S32K144.h:2363
#define DMA_DCHPRI_ECP(x)
Definition: S32K144.h:2917
#define DMA_TCD_CSR_MAJORLINKCH(x)
Definition: S32K144.h:3058
#define DMA_TCD_CSR_ESG(x)
Definition: S32K144.h:3042
static bool EDMA_HAL_TCDGetChannelActiveStatus(const DMA_Type *base, uint32_t channel)
Checks whether the channel is running for the TCD.
Definition: edma_hal.h:1207
#define DMA_ES_DAE_MASK
Definition: S32K144.h:2383
void EDMA_HAL_TCDClearReg(DMA_Type *base, uint32_t channel)
Clears all registers to 0 for the hardware TCD.
Definition: edma_hal.c:172
static bool EDMA_HAL_GetIntStatusFlag(const DMA_Type *base, uint32_t channel)
Gets the eDMA channel interrupt request status.
Definition: edma_hal.h:720
uint32_t EDMA_HAL_TCDGetUnfinishedBytes(const DMA_Type *base, uint32_t channel)
Gets the number of bytes haven't transferred for the TCD.
Definition: edma_hal.c:480
static void EDMA_HAL_SetChannelPreemptMode(DMA_Type *base, uint32_t channel, bool preemptive, bool preemptible)
Sets the preemption feature for the eDMA channel.
Definition: edma_hal.h:450
static void EDMA_HAL_TCDSetDestMinorLoopOffsetCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/disables the destination minor loop offset feature for the TCD.
Definition: edma_hal.h:910
__IO uint16_t CSR
Definition: S32K144.h:2289
#define FEATURE_EDMA_MODULE_CHANNELS
#define DMA_ES_DOE_SHIFT
Definition: S32K144.h:2380
static void EDMA_HAL_TCDSetSrcLastAdjust(DMA_Type *base, uint32_t channel, int32_t size)
Configures the last source address adjustment for the TCD.
Definition: edma_hal.h:952
void EDMA_HAL_TCDSetMajorCount(DMA_Type *base, uint32_t channel, uint32_t count)
Sets the major iteration count according to minor loop channel link setting.
Definition: edma_hal.c:388
static void EDMA_HAL_TCDTriggerChannelStart(DMA_Type *base, uint32_t channel)
Triggers the start bits for the TCD.
Definition: edma_hal.h:1187
#define DMA_CR_EMLM(x)
Definition: S32K144.h:2353
__O uint8_t CERR
Definition: S32K144.h:2259
static void EDMA_HAL_TCDSetSrcMinorLoopOffsetCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/disables the source minor loop offset feature for the TCD.
Definition: edma_hal.h:881
#define DMA_TCD_CSR_INTMAJOR(x)
Definition: S32K144.h:3030
__IO uint32_t SLAST
Definition: S32K144.h:2281
#define DMA_ES_SBE_MASK
Definition: S32K144.h:2367
#define DMA_CR_HOE_MASK
Definition: S32K144.h:2338
static bool EDMA_HAL_GetDestinationBusError(const DMA_Type *base)
Checks for destination bus errors.
Definition: edma_hal.h:412
static void EDMA_HAL_ClearIntStatusFlag(DMA_Type *base, uint8_t channel)
Clears the interrupt status for the eDMA channel or all channels.
Definition: edma_hal.h:737
uint32_t EDMA_HAL_TCDGetCurrentMajorCount(const DMA_Type *base, uint32_t channel)
Returns the current major iteration count.
Definition: edma_hal.c:454
#define DMA_ES_SBE_SHIFT
Definition: S32K144.h:2368
__IO uint32_t CR
Definition: S32K144.h:2247
void EDMA_HAL_CancelTransferWithError(DMA_Type *base)
Cancels the remaining data transfer and treats it as an error condition.
Definition: edma_hal.c:88
#define DMA_CR_ERCA_MASK
Definition: S32K144.h:2334
#define DMA_TCD_CSR_ACTIVE_MASK
Definition: S32K144.h:3047
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
Definition: S32K144.h:2976
#define DMA_ES_VLD_SHIFT
Definition: S32K144.h:2408
static void EDMA_HAL_TCDSetScatterGatherCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/Disables the scatter/gather feature for the TCD.
Definition: edma_hal.h:1094
void EDMA_HAL_SetErrorIntCmd(DMA_Type *base, uint8_t channel, bool enable)
Enables/Disables the error interrupt for channels.
Definition: edma_hal.c:106
static bool EDMA_HAL_GetMinorMajorLoopConfigError(const DMA_Type *base)
Checks for minor/major loop configuration errors.
Definition: edma_hal.h:370
#define DEV_ASSERT(x)
Definition: devassert.h:78
#define DMA_ES_SGE_MASK
Definition: S32K144.h:2371
#define DMA_TCD_CSR_DONE_SHIFT
Definition: S32K144.h:3052
#define DMA_TCD_CSR_MAJORLINKCH_MASK
Definition: S32K144.h:3055
static void EDMA_HAL_TCDSetSrcOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the source address signed offset for the hardware TCD.
Definition: edma_hal.h:813
#define DMA_DCHPRI_DPA(x)
Definition: S32K144.h:2913
static void EDMA_HAL_TCDSetDestAddr(DMA_Type *base, uint32_t channel, uint32_t address)
Configures the destination address for the TCD.
Definition: edma_hal.h:968
static void EDMA_HAL_SetHaltCmd(DMA_Type *base, bool halt)
Halts/Un-halts the DMA Operations.
Definition: edma_hal.h:206
__I uint32_t ES
Definition: S32K144.h:2248
static uint8_t EDMA_HAL_GetChannelWithError(const DMA_Type *base)
Error channel number.
Definition: edma_hal.h:426
static void EDMA_HAL_TCDSetDestLastAdjust(DMA_Type *base, uint32_t channel, int32_t adjust)
Configures the last source address adjustment.
Definition: edma_hal.h:1007
static void EDMA_HAL_SetChannelPriority(DMA_Type *base, uint32_t channel, edma_channel_priority_t priority)
Sets the eDMA channel priority.
Definition: edma_hal.h:475
edma_arbitration_algorithm_t
eDMA channel arbitration algorithm used for selection among channels. Implements : edma_arbitration_a...
Definition: edma_hal.h:54
static void EDMA_HAL_SetHaltOnErrorCmd(DMA_Type *base, bool haltOnError)
Halts or does not halt the eDMA module when an error occurs.
Definition: edma_hal.h:225
static bool EDMA_HAL_GetScatterGatherError(const DMA_Type *base)
Checks for scatter/gather configuration errors.
Definition: edma_hal.h:384
void EDMA_HAL_CancelTransfer(DMA_Type *base)
Cancels the remaining data transfer.
Definition: edma_hal.c:70
static bool EDMA_HAL_GetValidErrorNotCleared(const DMA_Type *base)
Checks for valid errors.
Definition: edma_hal.h:270
#define DMA_ES_CPE_MASK
Definition: S32K144.h:2399
__IO uint16_t SOFF
Definition: S32K144.h:2274
void EDMA_HAL_TCDSetMinorLoopOffset(DMA_Type *base, uint32_t channel, int32_t offset)
Configures the minor loop offset for the TCD.
Definition: edma_hal.c:297
#define DMA_TCD_CSR_INTMAJOR_MASK
Definition: S32K144.h:3027
void EDMA_HAL_TCDSetChannelMinorLink(DMA_Type *base, uint32_t channel, uint32_t linkChannel, bool enable)
Sets the channel minor link for the TCD.
Definition: edma_hal.c:347
#define DMA_ES_ECX_SHIFT
Definition: S32K144.h:2404
static void EDMA_HAL_SetMinorLoopMappingCmd(DMA_Type *base, bool enable)
Enables/Disables the minor loop mapping.
Definition: edma_hal.h:584
void EDMA_HAL_TCDSetAttribute(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo, edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize)
Configures the transfer attribute for the eDMA channel.
Definition: edma_hal.c:194
__O uint8_t CDNE
Definition: S32K144.h:2257
#define DMA_ES_SOE_SHIFT
Definition: S32K144.h:2388
#define DMA_TCD_CSR_INTHALF(x)
Definition: S32K144.h:3034
__IO uint32_t ERR
Definition: S32K144.h:2264
#define DMA_CR_CLM(x)
Definition: S32K144.h:2349
#define DMA_TCD_CSR_START_MASK
Definition: S32K144.h:3023
__IO uint32_t DADDR
Definition: S32K144.h:2282
#define DMA_CR_EDBG(x)
Definition: S32K144.h:2333
#define DMA_TCD_CSR_ACTIVE_SHIFT
Definition: S32K144.h:3048
#define DMA_CR_HOE(x)
Definition: S32K144.h:2341
#define DMA_TCD_CSR_MAJORELINK_MASK
Definition: S32K144.h:3043
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
Definition: edma_hal.h:132
union DMA_Type::@6::@7 NBYTES
edma_bandwidth_config_t
Bandwidth control configuration Implements : edma_bandwidth_config_t_Class.
Definition: edma_hal.h:143
__O uint8_t CINT
Definition: S32K144.h:2260
static bool EDMA_HAL_TCDGetDoneStatusFlag(const DMA_Type *base, uint32_t channel)
Gets the channel done status.
Definition: edma_hal.h:1285
static bool EDMA_HAL_GetSourceOffsetError(const DMA_Type *base)
Checks for source offset errors.
Definition: edma_hal.h:328
static void EDMA_HAL_ClearErrorIntStatusFlag(DMA_Type *base, uint8_t channel)
Clears the error interrupt status for the eDMA channel or channels.
Definition: edma_hal.h:645
#define DMA_CR_HALT_MASK
Definition: S32K144.h:2342
__IO uint16_t DOFF
Definition: S32K144.h:2283
static void EDMA_HAL_TCDSetDisableDmaRequestAfterTCDDoneCmd(DMA_Type *base, uint32_t channel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
Definition: edma_hal.h:1117
#define DMA_ES_ERRCHN_SHIFT
Definition: S32K144.h:2396
__IO uint8_t DCHPRI[DMA_DCHPRI_COUNT]
Definition: S32K144.h:2270
edma_modulo_t
eDMA modulo configuration Implements : edma_modulo_t_Class
Definition: edma_hal.h:94
#define DMA_ES_SAE_SHIFT
Definition: S32K144.h:2392
__IO uint32_t INT
Definition: S32K144.h:2262
#define DMA_TCD_CSR_START(x)
Definition: S32K144.h:3026
__IO uint32_t EARS
Definition: S32K144.h:2268
#define DMA_TCD_CSR_DREQ_MASK
Definition: S32K144.h:3035
#define FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(x)
#define DMA_CR_ERCA_SHIFT
Definition: S32K144.h:2335
#define DMA_CR_ERCA(x)
Definition: S32K144.h:2337
#define DMA_ES_ECX_MASK
Definition: S32K144.h:2403
static void EDMA_HAL_TCDSetDestOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the destination address signed offset for the TCD.
Definition: edma_hal.h:987
#define DMA_ES_NCE_MASK
Definition: S32K144.h:2375
#define DMA_TCD_CSR_MAJORELINK(x)
Definition: S32K144.h:3046
#define DMA_DCHPRI_DPA_MASK
Definition: S32K144.h:2910
static void EDMA_HAL_TCDSetBandwidth(DMA_Type *base, uint32_t channel, edma_bandwidth_config_t bandwidth)
Configures the bandwidth for the TCD.
Definition: edma_hal.h:1044
static uint32_t EDMA_HAL_GetErrorIntStatusFlag(const DMA_Type *base)
Gets the eDMA error interrupt status.
Definition: edma_hal.h:632
#define DMA_CR_EDBG_MASK
Definition: S32K144.h:2330
#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
Definition: S32K144.h:2975
#define DMA_ES_CPE_SHIFT
Definition: S32K144.h:2400
edma_channel_priority_t
eDMA channel priority setting Implements : edma_channel_priority_t_Class
Definition: edma_hal.h:62
static void EDMA_HAL_SetAsyncRequestInStopModeCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/Disables an asynchronous request in stop mode.
Definition: edma_hal.h:755
void EDMA_HAL_SetDmaRequestCmd(DMA_Type *base, uint8_t channel, bool enable)
Enables/Disables the DMA request for the channel or all channels.
Definition: edma_hal.c:125
static bool EDMA_HAL_GetDestinationOffsetError(const DMA_Type *base)
Checks for destination offset errors.
Definition: edma_hal.h:356
static void EDMA_HAL_TCDSetIntCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/Disables the interrupt after the major loop completes for the TCD.
Definition: edma_hal.h:1166
uint32_t EDMA_HAL_TCDGetFinishedBytes(const DMA_Type *base, uint32_t channel)
Gets the number of bytes already transferred for the TCD.
Definition: edma_hal.c:510
static void EDMA_HAL_ClearDoneStatusFlag(DMA_Type *base, uint8_t channel)
Clears the done status for a channel or all channels.
Definition: edma_hal.h:688
#define DMA_CR_HALT(x)
Definition: S32K144.h:2345
#define DMA_ES_DOE_MASK
Definition: S32K144.h:2379
#define DMA_DCHPRI_ECP_MASK
Definition: S32K144.h:2914
static void EDMA_HAL_TriggerChannelStart(DMA_Type *base, uint8_t channel)
Triggers the eDMA channel.
Definition: edma_hal.h:703
#define DMA_ES_NCE_SHIFT
Definition: S32K144.h:2376
static bool EDMA_HAL_GetDestinationAddressError(const DMA_Type *base)
Checks for destination address errors.
Definition: edma_hal.h:342
struct DMA_Type::@6 TCD[DMA_TCD_COUNT]
static edma_arbitration_algorithm_t EDMA_HAL_GetChannelArbitrationMode(const DMA_Type *base)
Gets the channel arbitration algorithm.
Definition: edma_hal.h:512
void EDMA_HAL_Init(DMA_Type *base)
Initializes eDMA module to known state.
Definition: edma_hal.c:42
void EDMA_HAL_TCDSetNbytes(DMA_Type *base, uint32_t channel, uint32_t nbytes)
Configures the nbytes for the eDMA channel.
Definition: edma_hal.c:215
#define DMA_DCHPRI_CHPRI(x)
Definition: S32K144.h:2909
static void EDMA_HAL_TCDSetHalfCompleteIntCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/Disables the half complete interrupt for the TCD.
Definition: edma_hal.h:1143
static bool EDMA_HAL_GetDmaRequestStatusFlag(const DMA_Type *base, uint32_t channel)
Gets the eDMA channel DMA request status.
Definition: edma_hal.h:672
uint32_t EDMA_HAL_TCDGetNbytes(const DMA_Type *base, uint32_t channel)
Gets the nbytes configuration data for the TCD.
Definition: edma_hal.c:256
#define DMA_ES_SAE_MASK
Definition: S32K144.h:2391
#define DMA_TCD_CSR_ESG_MASK
Definition: S32K144.h:3039
#define DMA_ES_DBE_SHIFT
Definition: S32K144.h:2364
static void EDMA_HAL_SetDebugCmd(DMA_Type *base, bool enable)
Enables/Disables the eDMA DEBUG mode.
Definition: edma_hal.h:246
static void EDMA_HAL_SetChannelArbitrationMode(DMA_Type *base, edma_arbitration_algorithm_t channelArbitration)
Sets the channel arbitration algorithm.
Definition: edma_hal.h:496
#define DMA_CR_CLM_MASK
Definition: S32K144.h:2346
uint32_t EDMA_HAL_TCDGetBeginMajorCount(const DMA_Type *base, uint32_t channel)
Returns the begin major iteration count.
Definition: edma_hal.c:429
__IO uint32_t DLASTSGA
Definition: S32K144.h:2288
#define DMA_ES_VLD_MASK
Definition: S32K144.h:2407
#define DMA_TCD_CSR_DREQ(x)
Definition: S32K144.h:3038
static bool EDMA_HAL_GetChannelPriorityError(const DMA_Type *base)
Checks for channel priority errors.
Definition: edma_hal.h:300
static bool EDMA_HAL_GetSourceBusError(const DMA_Type *base)
Checks for source bus errors.
Definition: edma_hal.h:398
#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
Definition: S32K144.h:2979