S32 SDK
lpspi_slave_driver.c
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1 /*
2  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
82 #include <string.h>
83 #include "lpspi_slave_driver.h"
84 #include "clock_manager.h"
85 #include "interrupt_manager.h"
86 #include "lpspi_shared_function.h"
87 #include "S32K144_features.h"
88 
89 
90 /*******************************************************************************
91  * Definitions
92  ******************************************************************************/
93 
94 /* Callback for DMA transfer done.*/
95 static void LPSPI_DRV_SlaveCompleteDMATransfer(void* parameter, edma_chn_status_t status);
96 
97 /*******************************************************************************
98  * Code
99  ******************************************************************************/
100  /*
101  * Implements : LPSPI_DRV_SlaveInit_Activity
102  */
103 status_t LPSPI_DRV_SlaveInit(uint32_t instance,
104  lpspi_state_t * lpspiState,
105  const lpspi_slave_config_t * slaveConfig)
106 {
107  DEV_ASSERT(lpspiState != NULL);
108  DEV_ASSERT(slaveConfig != NULL);
109  DEV_ASSERT(instance < LPSPI_INSTANCE_COUNT);
110  LPSPI_Type * base = g_lpspiBase[instance];
111  status_t errorCode = STATUS_SUCCESS;
112 
113  lpspiState->lsb = slaveConfig->lsbFirst;
114  lpspiState->bitsPerFrame = slaveConfig->bitcount;
115  lpspiState->transferType = slaveConfig->transferType;
116  lpspiState->isBlocking = false;
117  /* Store DMA channels numbers used for DMA transfer */
118  lpspiState->rxDMAChannel = slaveConfig->rxDMAChannel;
119  lpspiState->txDMAChannel = slaveConfig->txDMAChannel;
120  /* Calculate the bytes/frame for lpspiState->bytesPerFrame. */
121  lpspiState->bytesPerFrame = (uint16_t)((lpspiState->bitsPerFrame + 7U) / 8U);
122  /* For DMA transfers bytes per frame must be equal to 1, 2 or multiple of 4. */
123  if ((lpspiState->transferType == LPSPI_USING_DMA) && (!(((lpspiState->bytesPerFrame % 4U) == 0U) ||
124  (lpspiState->bytesPerFrame <= 2U))))
125  {
126  return STATUS_ERROR;
127  }
128  lpspiState->isTransferInProgress = false;
129  /* Initialize the semaphore */
130  errorCode = OSIF_SemaCreate(&(lpspiState->lpspiSemaphore), 0);
131  DEV_ASSERT(errorCode == STATUS_SUCCESS);
132  g_lpspiStatePtr[instance] = lpspiState;
133 
134  /* Configure registers */
135  LPSPI_HAL_Init(base);
136 
137  /* Configure lpspi to slave mode */
139  /* Set Pin settings */
141  /* Calculate the FIFO size for the LPSPI */
142  LPSPI_HAL_GetFifoSizes(base, &(lpspiState->fifoSize), NULL);
143 
144  /* Set polarity */
145  (void)LPSPI_HAL_SetPcsPolarityMode(base, LPSPI_PCS0,slaveConfig->pcsPolarity);
146 
147  /* Write the TCR for this transfer */
148  lpspi_tx_cmd_config_t txCmdCfg = {
149  .frameSize = lpspiState->bitsPerFrame,
150  .width = LPSPI_SINGLE_BIT_XFER,
151  .txMask = false,
152  .rxMask = false,
153  .byteSwap = false,
154  .lsbFirst = slaveConfig->lsbFirst,
155  .clkPhase = slaveConfig->clkPhase,
156  .clkPolarity = slaveConfig->clkPolarity,
157  .whichPcs = slaveConfig->whichPcs
158  };
159 
160  /* Write to the TX CMD register */
161  LPSPI_HAL_SetTxCommandReg(base, &txCmdCfg);
162  LPSPI_HAL_Enable(base);
163  /* Enable the interrupt source */
164  INT_SYS_EnableIRQ(g_lpspiIrqId[instance]);
165 
166  return errorCode;
167 }
168 
169  /*
170  * Implements : LPSPI_DRV_SlaveDeinit_Activity
171  */
172 status_t LPSPI_DRV_SlaveDeinit(uint32_t instance)
173 {
174  DEV_ASSERT(instance < LPSPI_INSTANCE_COUNT);
175  /* Instantiate local variable of type lpspi_master_state_t and point to global state */
176  const lpspi_state_t * lpspiState = (lpspi_state_t *)g_lpspiStatePtr[instance];
177  LPSPI_Type *base = g_lpspiBase[instance];
178  status_t errorCode = STATUS_SUCCESS;
179 
180  /* Check if a transfer is still in progress */
181  DEV_ASSERT(lpspiState->isTransferInProgress == false);
182  /* Destroy the semaphore */
183  errorCode = OSIF_SemaDestroy(&(lpspiState->lpspiSemaphore));
184  DEV_ASSERT(errorCode == STATUS_SUCCESS);
185  /* Reset the LPSPI registers to their default state, including disabling the LPSPI */
186  LPSPI_HAL_Init(base);
187 
188  /* Disable the interrupt*/
189  INT_SYS_DisableIRQ(g_lpspiIrqId[instance]);
190 
191  /* Clear the state pointer. */
192  g_lpspiStatePtr[instance] = NULL;
193 
194  return errorCode;
195 }
196 
197  /*
198  * Implements : LPSPI_DRV_SlaveTransferBlocking_Activity
199  */
201  const uint8_t *sendBuffer,
202  uint8_t *receiveBuffer,
203  uint16_t transferByteCount,
204  uint32_t timeout)
205 {
206  DEV_ASSERT(instance < LPSPI_INSTANCE_COUNT);
207  lpspi_state_t * state = (lpspi_state_t *)g_lpspiStatePtr[instance];
208  status_t error;
209  status_t osifError;
210  state->isBlocking = true;
211  error = LPSPI_DRV_SlaveTransfer(instance, sendBuffer, receiveBuffer, transferByteCount);
212  if(error != STATUS_SUCCESS)
213  {
215  return error;
216  }
217 
218  /* As this is a synchronous transfer, wait until the transfer is complete.*/
219  osifError = OSIF_SemaWait(&(state->lpspiSemaphore), timeout);
220 
221  if (osifError == STATUS_TIMEOUT)
222  {
223  /* Set isBlocking variable to false to avoid dummy semaphore post. */
224  state->isBlocking = false;
225  /* Complete transfer. */
226  (void)LPSPI_DRV_SlaveAbortTransfer(instance);
227  return(STATUS_TIMEOUT);
228  }
229 
231 
232  return STATUS_SUCCESS;
233 }
234 
235  /*
236  * Implements : LPSPI_DRV_SlaveTransfer_Activity
237  */
239  const uint8_t *sendBuffer,
240  uint8_t *receiveBuffer,
241  uint16_t transferByteCount)
242 {
243  DEV_ASSERT(instance < LPSPI_INSTANCE_COUNT);
244  DEV_ASSERT(!((sendBuffer == NULL) && (receiveBuffer == NULL)));
245  LPSPI_Type * base = g_lpspiBase[instance];
247  lpspi_state_t * state = (lpspi_state_t *)g_lpspiStatePtr[instance];
249  /* Check if a transfer is still in progress */
250  DEV_ASSERT(state->isTransferInProgress == false);
251  /* The number of transferred bytes should be divisible by frame size */
252  if ((uint16_t)(transferByteCount % state->bytesPerFrame) != (uint16_t)0)
253  {
254  return STATUS_ERROR;
255  }
256  /* Check if LPSPI module isn't busy */
258  {
259  return STATUS_BUSY;
260  }
261  /* Initialize the status of the current transfer */
262  state->status = LPSPI_TRANSFER_OK;
263  /* Clear all interrupts sources */
265  /* Enable fault interrupts sources */
268  if (state->transferType == LPSPI_USING_INTERRUPTS)
269  {
270  state->rxBuff = receiveBuffer;
271  state->txBuff = sendBuffer;
272  state->txCount = transferByteCount;
273  state->rxCount = transferByteCount;
274  state->txFrameCnt = 0;
275  state->rxFrameCnt = 0;
276  state->isPcsContinuous = false;
277  /* Configure watermarks */
278  LPSPI_HAL_SetRxWatermarks(base, 0U);
279  LPSPI_HAL_SetTxWatermarks(base, 2U);
280 
281  /* Clean RX and TX buffers */
282  LPSPI_HAL_SetFlushFifoCmd(base, true, true);
283  /* The second flush command is used to avoid the case when one word is still in shifter. */
284  LPSPI_HAL_SetFlushFifoCmd(base, true, true);
285  state->isTransferInProgress = true;
286  /* Enable interrupts for RX and TX only if it's necessary */
287  if(state->txBuff != NULL)
288  {
290  }
291  else
292  {
293  state->txCount = 0;
294  }
295  if(state->rxBuff != NULL)
296  {
298  }
299  else
300  {
301  state->rxCount = 0;
302  }
303  }
304  else
305  {
306  /* Configure watermarks */
307  LPSPI_HAL_SetRxWatermarks(base, 0U);
308  LPSPI_HAL_SetTxWatermarks(base, 3U);
309  /* When LPSPI use DMA frames with 3 bytes size are not accepted. */
310  switch(state->bytesPerFrame)
311  {
312  case 1: dmaTransferSize = EDMA_TRANSFER_SIZE_1B; break;
313  case 2: dmaTransferSize = EDMA_TRANSFER_SIZE_2B; break;
314  case 4: dmaTransferSize = EDMA_TRANSFER_SIZE_4B; break;
315  default: dmaTransferSize = EDMA_TRANSFER_SIZE_1B; break;
316  }
317  if(receiveBuffer != NULL)
318  {
320  (uint32_t)(&(base->RDR)),(uint32_t)receiveBuffer, dmaTransferSize, (uint32_t)1U<<(uint8_t)(dmaTransferSize));
321  EDMA_HAL_TCDSetMajorCount(baseDma, state->rxDMAChannel, (uint32_t)transferByteCount/(uint32_t)((uint32_t)1U <<(uint8_t)(dmaTransferSize)));
322  /* Disable DMA requests for RX channel when transfer is done. */
324  state->rxCount = transferByteCount;
325  /* Start RX channel */
326  (void)EDMA_DRV_StartChannel(state->rxDMAChannel);
327  }
328  else
329  {
330  state->rxCount = 0;
331  }
332  if(sendBuffer != NULL)
333  {
335  (uint32_t)sendBuffer, (uint32_t)(&(base->TDR)), dmaTransferSize, (uint32_t)1U<<(uint8_t)(dmaTransferSize));
336  EDMA_HAL_TCDSetMajorCount(baseDma, state->txDMAChannel, (uint32_t)transferByteCount/(uint32_t)((uint32_t)1U <<(uint8_t)(dmaTransferSize)));
337  /* Disable DMA requests for RX channel when transfer is done. */
339  state->txCount = transferByteCount;
340  /* Start TX channel */
341  (void)EDMA_DRV_StartChannel(state->txDMAChannel);
342  }
343  else
344  {
345  state->txCount = 0;
346  }
347  /* Configure which channel will generate transfer complete */
348  /* If current transfer uses both buffers (RX and TX) RX transfer done will generate transfer complete
349  * interrupt. Otherwise transfer complete will be generate by available channel(RX or TX).
350  */
351  if(receiveBuffer != NULL)
352  {
354  }
355  else
356  {
358  }
359  state->isTransferInProgress = true;
360  /* Enable LPSPI DMA request */
361  if (receiveBuffer != NULL)
362  {
363  LPSPI_HAL_SetRxDmaCmd(base, true);
364  }
365  if (sendBuffer != NULL)
366  {
367  LPSPI_HAL_SetTxDmaCmd(base, true);
368  }
369  }
370  return STATUS_SUCCESS;
371 }
372 
373 void LPSPI_DRV_SlaveIRQHandler(uint32_t instance)
374 {
375  LPSPI_Type * base = g_lpspiBase[instance];
376  lpspi_state_t * lpspiState = (lpspi_state_t *)g_lpspiStatePtr[instance];
377  uint16_t txCount, rxCount;
378 
379  /* If an error is detected the transfer will be aborted */
381  {
382  lpspiState->status = LPSPI_TRANSMIT_FAIL;
383  (void)LPSPI_DRV_SlaveAbortTransfer(instance);
384  return;
385  }
387  {
388  lpspiState->status = LPSPI_RECEIVE_FAIL;
389  (void)LPSPI_DRV_SlaveAbortTransfer(instance);
390  return;
391  }
392 
393  /* Receive data */
395  {
396  LPSPI_DRV_ReadRXBuffer(instance);
397  }
398  /* Transmit data */
399  txCount = lpspiState->txCount;
400  if (LPSPI_HAL_GetStatusFlag(base,LPSPI_TX_DATA_FLAG) && ((txCount != (uint8_t)0)))
401  {
402  LPSPI_DRV_FillupTxBuffer(instance);
403  }
404  txCount = lpspiState->txCount;
405  rxCount = lpspiState->rxCount;
406  /* If all bytes are sent disable interrupt TDF */
407  if (txCount == (uint8_t)0)
408  {
410  }
411  /* If all bytes are received disable interrupt RDF */
412  if (rxCount == (uint8_t)0)
413  {
415  }
416  if ((rxCount == (uint8_t)0) && (txCount == (uint8_t)0))
417  {
418  lpspiState->isTransferInProgress = false;
419  if(lpspiState->isBlocking == true)
420  {
421  (void)OSIF_SemaPost(&(lpspiState->lpspiSemaphore));
422  lpspiState->isBlocking = false;
423  }
424  }
425 }
426 
427  /*
428  * Implements : LPSPI_DRV_SlaveAbortTransfer_Activity
429  */
431 {
432  LPSPI_Type * base = g_lpspiBase[instance];
433  lpspi_state_t * state = (lpspi_state_t *)g_lpspiStatePtr[instance];
434 
435  if (state->transferType == LPSPI_USING_INTERRUPTS)
436  {
437  /* Disable interrupts */
440  }
441  else
442  {
443  /* Disable LPSPI DMA request */
444  LPSPI_HAL_SetRxDmaCmd(base, false);
445  LPSPI_HAL_SetTxDmaCmd(base, false);
446  }
447 
449 
450  state->isTransferInProgress = false;
451  /* Clean RX and TX buffers */
452  LPSPI_HAL_SetFlushFifoCmd(base, true, true);
453  /* The second flush command is used to avoid the case when one word is still in shifter. */
454  LPSPI_HAL_SetFlushFifoCmd(base, true, true);
455  if(state->isBlocking == true)
456  {
457  (void)OSIF_SemaPost(&(state->lpspiSemaphore));
458  state->isBlocking = false;
459  }
460  return STATUS_SUCCESS;
461 }
462 
463  /*
464  * Implements : LPSPI_DRV_SlaveGetTransferStatus_Activity
465  */
466 status_t LPSPI_DRV_SlaveGetTransferStatus(uint32_t instance,uint32_t * bytesRemained)
467 {
468  const lpspi_state_t * lpspiState = (lpspi_state_t *)g_lpspiStatePtr[instance];
469 
470  /* Fill in the bytes transferred.*/
471  if (bytesRemained != NULL)
472  {
473  *bytesRemained = lpspiState->txCount;
474  }
475  if (lpspiState->status == LPSPI_TRANSFER_OK)
476  {
477  return (status_t)(lpspiState->isTransferInProgress ? STATUS_BUSY : STATUS_SUCCESS);
478  }
479  else
480  {
481  return STATUS_ERROR;
482  }
483 }
484 
489 static void LPSPI_DRV_SlaveCompleteDMATransfer(void* parameter, edma_chn_status_t status)
490 {
491  uint32_t instance = (uint32_t)parameter;
492 
493  (void)status;
494  (void)LPSPI_DRV_SlaveAbortTransfer(instance);
495 }
volatile uint16_t rxFrameCnt
#define LPSPI_INSTANCE_COUNT
Definition: S32K144.h:6194
volatile uint16_t txFrameCnt
Runtime state structure for the LPSPI master driver.
static void LPSPI_HAL_SetTxWatermarks(LPSPI_Type *base, uint32_t txWater)
Sets the TX FIFO watermark values.
Definition: lpspi_hal.h:433
void LPSPI_DRV_ReadRXBuffer(uint32_t instance)
The function LPSPI_DRV_ReadRXBuffer reads data from RX hardware buffer and writes this data in RX sof...
void LPSPI_HAL_GetFifoSizes(const LPSPI_Type *base, uint8_t *txFifoSize, uint8_t *rxFifoSize)
Gets the TX and RX FIFO sizes of the LPSPI module.
Definition: lpspi_hal.c:230
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
Chip specific module features.
lpspi_transfer_type transferType
#define LPSPI_DMA_INSTANCE
lpspi_signal_polarity_t pcsPolarity
lpspi_state_t * g_lpspiStatePtr[LPSPI_INSTANCE_COUNT]
void LPSPI_HAL_SetFlushFifoCmd(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo)
Flushes the LPSPI FIFOs.
Definition: lpspi_hal.c:250
void EDMA_HAL_TCDSetMajorCount(DMA_Type *base, uint32_t channel, uint32_t count)
Sets the major iteration count according to minor loop channel link setting.
Definition: edma_hal.c:388
lpspi_which_pcs_t whichPcs
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
status_t LPSPI_HAL_SetPinConfigMode(LPSPI_Type *base, lpspi_pin_config_t pinCfg, lpspi_data_out_config_t dataOutConfig, bool pcs3and2Enable)
Configures the LPSPI SDO/SDI pin configuration mode.
Definition: lpspi_hal.c:426
static void LPSPI_HAL_SetTxDmaCmd(LPSPI_Type *base, bool enable)
Sets the LPSPI Transmit Data DMA configuration (enable or disable).
Definition: lpspi_hal.h:533
void LPSPI_DRV_FillupTxBuffer(uint32_t instance)
The function LPSPI_DRV_FillupTxBuffer writes data in TX hardware buffer depending on driver state and...
status_t LPSPI_DRV_SlaveTransfer(uint32_t instance, const uint8_t *sendBuffer, uint8_t *receiveBuffer, uint16_t transferByteCount)
Starts the transfer data on LPSPI bus using an interrupt and a non-blocking call. ...
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
lpspi_clock_phase_t clkPhase
#define DEV_ASSERT(x)
Definition: devassert.h:78
volatile uint16_t rxCount
edma_chn_status_t
Channel status for eDMA channel.
Definition: edma_driver.h:125
status_t LPSPI_DRV_SlaveTransferBlocking(uint32_t instance, const uint8_t *sendBuffer, uint8_t *receiveBuffer, uint16_t transferByteCount, uint32_t timeout)
Transfers data on LPSPI bus using interrupt and a blocking call.
status_t LPSPI_HAL_SetPcsPolarityMode(LPSPI_Type *base, lpspi_which_pcs_t whichPcs, lpspi_signal_polarity_t pcsPolarity)
Configures the desired LPSPI PCS polarity.
Definition: lpspi_hal.c:340
volatile uint16_t txCount
lpspi_sck_polarity_t clkPolarity
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:31
IRQn_Type g_lpspiIrqId[LPSPI_INSTANCE_COUNT]
Table to save LPSPI IRQ enumeration numbers defined in the CMSIS header file.
status_t LPSPI_DRV_SlaveInit(uint32_t instance, lpspi_state_t *lpspiState, const lpspi_slave_config_t *slaveConfig)
Initializes a LPSPI instance for a slave mode operation, using interrupt mechanism.
static void LPSPI_HAL_Enable(LPSPI_Type *base)
Enables the LPSPI module.
Definition: lpspi_hal.h:340
User configuration structure for the SPI slave driver. Implements : lpspi_slave_config_t_Class.
void LPSPI_DRV_DisableTEIEInterrupts(uint32_t instance)
Disable the TEIE interrupts at the end of a transfer. Disable the interrupts and clear the status for...
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
Definition: edma_hal.h:132
static void LPSPI_DRV_SlaveCompleteDMATransfer(void *parameter, edma_chn_status_t status)
Finish up a transfer DMA. The main purpose of this function is to create a function compatible with D...
static void LPSPI_HAL_SetRxDmaCmd(LPSPI_Type *base, bool enable)
Sets the LPSPI Receive Data DMA configuration (enable or disable).
Definition: lpspi_hal.h:545
static void LPSPI_HAL_SetIntMode(LPSPI_Type *base, lpspi_status_flag_t interruptSrc, bool enable)
Configures the LPSPI interrupts.
Definition: lpspi_hal.h:492
static void EDMA_HAL_TCDSetDisableDmaRequestAfterTCDDoneCmd(DMA_Type *base, uint32_t channel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
Definition: edma_hal.h:1117
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
void LPSPI_HAL_Init(LPSPI_Type *base)
Resets the LPSPI internal logic and registers to their default settings.
Definition: lpspi_hal.c:84
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
Definition: edma_driver.c:765
status_t LPSPI_HAL_ClearStatusFlag(LPSPI_Type *base, lpspi_status_flag_t statusFlag)
Clears the LPSPI status flag.
Definition: lpspi_hal.c:278
static void LPSPI_HAL_SetRxWatermarks(LPSPI_Type *base, uint32_t rxWater)
Sets the RX FIFO watermark values.
Definition: lpspi_hal.h:416
volatile bool isTransferInProgress
status_t LPSPI_DRV_SlaveAbortTransfer(uint32_t instance)
Aborts the transfer that started by a non-blocking call transfer function.
LPSPI Transmit Command Register configuration structure.
Definition: lpspi_hal.h:215
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
DMA_Type *const g_edmaBase[DMA_INSTANCE_COUNT]
Array for the eDMA module register base address.
Definition: edma_common.c:47
lpspi_transfer_type transferType
status_t LPSPI_DRV_SlaveGetTransferStatus(uint32_t instance, uint32_t *bytesRemained)
Returns whether the previous transfer is finished.
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
__O uint32_t TDR
Definition: S32K144.h:6187
status_t LPSPI_DRV_SlaveDeinit(uint32_t instance)
Shuts down an LPSPI instance interrupt mechanism.
LPSPI_Type * g_lpspiBase[LPSPI_INSTANCE_COUNT]
Table of base pointers for SPI instances.
status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t dataBufferSize)
Configures a simple single block data transfer with DMA.
Definition: edma_driver.c:487
const uint8_t * txBuff
void LPSPI_HAL_SetTxCommandReg(LPSPI_Type *base, const lpspi_tx_cmd_config_t *txCmdCfgSet)
Sets the Transmit Command Register (TCR) parameters.
Definition: lpspi_hal.c:663
void LPSPI_DRV_SlaveIRQHandler(uint32_t instance)
Interrupt handler for LPSPI slave mode. This handler uses the buffers stored in the lpspi_master_stat...
__I uint32_t RDR
Definition: S32K144.h:6190
status_t LPSPI_HAL_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode)
Configures the LPSPI for master or slave.
Definition: lpspi_hal.c:208
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
Definition: edma_driver.c:285
semaphore_t lpspiSemaphore
static bool LPSPI_HAL_GetStatusFlag(const LPSPI_Type *base, lpspi_status_flag_t statusFlag)
Gets the LPSPI status flag state.
Definition: lpspi_hal.h:459
transfer_status_t status