S32 SDK
flexcan_hal.h
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1 /*
2  * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
30 #ifndef FLEXCAN_HAL_H
31 #define FLEXCAN_HAL_H
32 
33 #include <assert.h>
34 #include <stdint.h>
35 #include <stdbool.h>
36 #include <stddef.h>
37 #include "device_registers.h"
38 #include "status.h"
39 
47 /*******************************************************************************
48  * Definitions
49  ******************************************************************************/
50 
54 typedef enum {
61 
63 enum {
73 };
74 
76 enum {
79  FLEXCAN_TX_DATA = 0x0C,
84 };
85 
87 enum {
94 };
95 
99 typedef enum {
105 
109 typedef enum {
118 
122 typedef struct {
125  uint32_t *idFilter;
127 
131 typedef enum {
135 
139 typedef enum {
143 
144 #if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
145 
148 typedef enum {
152 #endif
153 
157 typedef enum {
163 
167 typedef struct {
168  uint16_t txerr;
169  uint16_t rxerr;
171 
175 typedef struct {
176  uint32_t code;
179  uint32_t dataLen;
180  bool fd_enable;
181  uint8_t fd_padding;
182  bool enable_brs; /* Enable bit rate switch*/
184 
188 typedef struct {
189  uint32_t cs;
190  uint32_t msgId;
191  uint8_t data[64];
192  uint8_t dataLen;
194 
198 typedef struct {
199  uint32_t propSeg;
200  uint32_t phaseSeg1;
201  uint32_t phaseSeg2;
202  uint32_t preDivider;
203  uint32_t rJumpwidth;
205 
206 #if FEATURE_CAN_HAS_PRETENDED_NETWORKING
207 
209 typedef struct {
210  bool extendedId;
211  bool remoteFrame;
212  uint32_t id;
214 
216 typedef struct {
217  uint8_t dlcLow;
218  uint8_t dlcHigh;
219  uint8_t payload1[8U];
221  uint8_t payload2[8U];
223 
225 typedef enum {
231 
233 typedef enum {
240 
244 typedef struct {
246  bool wakeUpMatch;
247  uint16_t numMatches;
248  uint16_t matchTimeout;
256 
257 #endif /* FEATURE_CAN_HAS_PRETENDED_NETWORKING */
258 
259 #define CAN_ID_EXT_MASK 0x3FFFFu
260 #define CAN_ID_EXT_SHIFT 0
261 #define CAN_ID_EXT_WIDTH 18
262 
263 #define CAN_ID_STD_MASK 0x1FFC0000u
264 #define CAN_ID_STD_SHIFT 18
265 #define CAN_ID_STD_WIDTH 11
266 
267 #define CAN_ID_PRIO_MASK 0xE0000000u
268 #define CAN_ID_PRIO_SHIFT 29
269 #define CAN_ID_PRIO_WIDTH 3
270 /* CS Bit Fields */
271 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
272 #define CAN_CS_TIME_STAMP_SHIFT 0
273 #define CAN_CS_TIME_STAMP_WIDTH 16
274 
275 #define CAN_CS_DLC_MASK 0xF0000u
276 #define CAN_CS_DLC_SHIFT 16
277 #define CAN_CS_DLC_WIDTH 4
278 
279 #define CAN_CS_RTR_MASK 0x100000u
280 #define CAN_CS_RTR_SHIFT 20
281 #define CAN_CS_RTR_WIDTH 1
282 
283 #define CAN_CS_IDE_MASK 0x200000u
284 #define CAN_CS_IDE_SHIFT 21
285 #define CAN_CS_IDE_WIDTH 1
286 
287 #define CAN_CS_SRR_MASK 0x400000u
288 #define CAN_CS_SRR_SHIFT 22
289 #define CAN_CS_SRR_WIDTH 1
290 
291 #define CAN_CS_CODE_MASK 0xF000000u
292 #define CAN_CS_CODE_SHIFT 24
293 #define CAN_CS_CODE_WIDTH 4
294 
295 #define CAN_MB_EDL_MASK 0x80000000u
296 #define CAN_MB_BRS_MASK 0x40000000u
297 
298 
299 /*******************************************************************************
300  * API
301  ******************************************************************************/
302 
303 #if defined(__cplusplus)
304 extern "C" {
305 #endif
306 
317 void FLEXCAN_HAL_Enable(CAN_Type * base);
318 
324 void FLEXCAN_HAL_Disable(CAN_Type * base);
325 
326 #if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
327 
334 
342 static inline bool FLEXCAN_HAL_GetClock(const CAN_Type * base)
343 {
344  return (((base->CTRL1 & CAN_CTRL1_CLKSRC_MASK) >> CAN_CTRL1_CLKSRC_SHIFT) != 0U);
345 }
346 #endif
347 
353 void FLEXCAN_HAL_Init(CAN_Type * base);
354 
361 void FLEXCAN_HAL_SetTimeSegments(CAN_Type * base, const flexcan_time_segment_t *timeSeg);
362 
363 
371 
378 void FLEXCAN_HAL_GetTimeSegments(const CAN_Type * base, flexcan_time_segment_t *timeSeg);
379 
386 
393 
401  CAN_Type * base,
403 
411  CAN_Type * base,
413 
420 void FLEXCAN_HAL_SetFDEnabled(CAN_Type * base, bool enable);
421 
428 bool FLEXCAN_HAL_IsFDEnabled(const CAN_Type * base);
429 
437  CAN_Type * base,
438  flexcan_fd_payload_size_t payloadSize);
439 
446 uint8_t FLEXCAN_HAL_GetPayloadSize(const CAN_Type * base);
447 
468  CAN_Type * base,
469  uint32_t msgBuffIdx,
471  uint32_t msgId,
472  const uint8_t *msgData);
473 
486  CAN_Type * base,
487  uint32_t msgBuffIdx,
489  uint32_t msgId);
490 
502  CAN_Type * base,
503  uint32_t msgBuffIdx,
504  flexcan_msgbuff_t *msgBuff);
505 
516  CAN_Type * base,
517  uint32_t msgBuffIdx);
518 
525 static inline void FLEXCAN_HAL_UnlockRxMsgBuff(const CAN_Type * base)
526 {
527  /* Unlock the mailbox by reading the free running timer */
528  (void)base->TIMER;
529 }
530 
541 status_t FLEXCAN_HAL_EnableRxFifo(CAN_Type * base, uint32_t numOfFilters);
542 
549 
557 static inline bool FLEXCAN_HAL_IsRxFifoEnabled(const CAN_Type * base)
558 {
559  return (((base->MCR & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT) != 0U);
560 }
561 
568 void FLEXCAN_HAL_SetRxFifoFilterNum(CAN_Type * base, uint32_t number);
569 
580  CAN_Type * base,
581  uint32_t maxMsgBuffNum);
582 
592  CAN_Type * base,
594  const flexcan_id_table_t *idFilterTable);
595 
603  const CAN_Type * base,
604  flexcan_msgbuff_t *rxFifo);
605 
624  CAN_Type * base,
625  uint32_t msgBuffIdx, bool enable);
626 
633 void FLEXCAN_HAL_SetErrIntCmd(CAN_Type * base, flexcan_int_type_t errType, bool enable);
634 
649 static inline uint32_t FLEXCAN_HAL_GetFreezeAck(const CAN_Type * base)
650 {
651  return ((base->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT);
652 }
653 
662  const CAN_Type * base,
663  uint32_t msgBuffIdx);
664 
672 static inline uint32_t FLEXCAN_HAL_GetAllMsgBuffIntStatusFlag(const CAN_Type * base)
673 {
674  uint32_t mask = base->IMASK1 & CAN_IMASK1_BUF31TO0M_MASK;
675 
676  return (base->IFLAG1 & mask);
677 }
678 
687  CAN_Type * base,
688  uint32_t flag)
689 {
690  /* Clear the corresponding message buffer interrupt flag*/
691  (base->IFLAG1) = (flag);
692 }
693 
701  const CAN_Type * base,
702  flexcan_buserr_counter_t *errCount);
703 
711 static inline uint32_t FLEXCAN_HAL_GetErrStatus(const CAN_Type * base)
712 {
713  return (base->ESR1);
714 }
715 
722 
737 
745  CAN_Type * base,
746  uint32_t stdMask);
747 
755  CAN_Type * base,
756  uint32_t extMask);
757 
769  CAN_Type * base,
770  uint32_t msgBuffIdx,
771  uint32_t stdMask);
772 
784  CAN_Type * base,
785  uint32_t msgBuffIdx,
786  uint32_t extMask);
787 
795  CAN_Type * base,
796  uint32_t stdMask);
797 
805  CAN_Type * base,
806  uint32_t stdMask);
807 
815  CAN_Type * base,
816  uint32_t stdMask);
817 
825  CAN_Type * base,
826  uint32_t extMask);
827 
835  CAN_Type * base,
836  uint32_t extMask);
837 
845  CAN_Type * base,
846  uint32_t extMask);
847 
855 static inline uint32_t FLEXCAN_HAL_GetRxFifoHitIdAcceptanceFilter(const CAN_Type * base)
856 {
857  return ((((base)->RXFIR) & CAN_RXFIR_IDHIT_MASK) >> CAN_RXFIR_IDHIT_SHIFT);
858 }
859 
872 void FLEXCAN_HAL_SetStuffBitCount(CAN_Type * base, bool enable);
873 
882 void FLEXCAN_HAL_SetSelfReception(CAN_Type * base, bool enable);
883 
884 #if FEATURE_CAN_HAS_DMA_ENABLE
885 
893 status_t FLEXCAN_HAL_SetRxFifoDMA(CAN_Type * base, bool enable);
894 #endif
895 
906 void FLEXCAN_HAL_SetTDCOffset(CAN_Type * base, bool enable, uint8_t offset);
907 
917 static inline uint8_t FLEXCAN_HAL_GetTDCValue(const CAN_Type * base)
918 {
919  return (uint8_t)((base->FDCTRL & CAN_FDCTRL_TDCVAL_MASK) >> CAN_FDCTRL_TDCVAL_SHIFT);
920 }
921 
931 static inline bool FLEXCAN_HAL_GetTDCFail(const CAN_Type * base)
932 {
933  return (((base->FDCTRL & CAN_FDCTRL_TDCFAIL_MASK) >> CAN_FDCTRL_TDCFAIL_SHIFT) != 0U);
934 }
935 
942 static inline void FLEXCAN_HAL_ClearTDCFail(CAN_Type * base)
943 {
944  base->FDCTRL = base->FDCTRL | CAN_FDCTRL_TDCFAIL_MASK;
945 }
946 
947 #if FEATURE_CAN_HAS_PRETENDED_NETWORKING
948 
955 void FLEXCAN_HAL_ConfigPN(CAN_Type * base, const flexcan_pn_config_t *pnConfig);
956 
964 void FLEXCAN_HAL_GetWMB(const CAN_Type * base, uint8_t wmbIndex, flexcan_msgbuff_t *wmb);
965 
973 static inline void FLEXCAN_HAL_SetPN(CAN_Type * base, bool enable)
974 {
975  base->MCR = (base->MCR & ~CAN_MCR_PNET_EN_MASK) | CAN_MCR_PNET_EN(enable ? 1UL : 0UL);
976 }
977 
978 #endif /* FEATURE_CAN_HAS_PRETENDED_NETWORKING */
979 
982 #if defined(__cplusplus)
983 }
984 #endif
985 
988 #endif /* FLEXCAN_HAL_H */
989 
990 /*******************************************************************************
991  * EOF
992  ******************************************************************************/
status_t FLEXCAN_HAL_SetRxFifoDMA(CAN_Type *base, bool enable)
Enables/Disables the DMA support for RxFIFO.
void FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX Message Buffer global extended mask.
Definition: flexcan_hal.c:1607
void FLEXCAN_HAL_SetTimeSegmentsCbt(CAN_Type *base, const flexcan_time_segment_t *timeSeg)
Sets the FlexCAN time segments for setting up bit rate for FD BRS.
Definition: flexcan_hal.c:547
void FLEXCAN_HAL_ClearErrIntStatusFlag(CAN_Type *base)
Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup).
Definition: flexcan_hal.c:1337
Pretended Networking ID filter.
Definition: flexcan_hal.h:209
void FLEXCAN_HAL_ConfigPN(CAN_Type *base, const flexcan_pn_config_t *pnConfig)
Configures the Pretended Networking mode.
void FLEXCAN_HAL_SetTimeSegments(CAN_Type *base, const flexcan_time_segment_t *timeSeg)
Sets the FlexCAN time segments for setting up bit rate.
Definition: flexcan_hal.c:493
void FLEXCAN_HAL_GetTimeSegments(const CAN_Type *base, flexcan_time_segment_t *timeSeg)
Gets the FlexCAN time segments to calculate the bit rate.
Definition: flexcan_hal.c:578
void FLEXCAN_HAL_SetTDCOffset(CAN_Type *base, bool enable, uint8_t offset)
Enables/Disables the Transceiver Delay Compensation feature and sets the Transceiver Delay Compensati...
Definition: flexcan_hal.c:1925
void FLEXCAN_HAL_DisableRxFifo(CAN_Type *base)
Disables the Rx FIFO.
Definition: flexcan_hal.c:991
#define CAN_IMASK1_BUF31TO0M_MASK
Definition: S32K144.h:1321
void FLEXCAN_HAL_ExitFreezeMode(CAN_Type *base)
Un freezes the FlexCAN module.
Definition: flexcan_hal.c:1272
void FLEXCAN_HAL_Enable(CAN_Type *base)
Enables FlexCAN controller.
Definition: flexcan_hal.c:386
FlexCAN bus error counters Implements : flexcan_buserr_counter_t_Class.
Definition: flexcan_hal.h:167
status_t FLEXCAN_HAL_EnableRxFifo(CAN_Type *base, uint32_t numOfFilters)
Enables the Rx FIFO.
Definition: flexcan_hal.c:947
bool FLEXCAN_HAL_IsFDEnabled(const CAN_Type *base)
Checks if the Flexible Data rate feature is enabled.
Definition: flexcan_hal.c:1790
#define CAN_RXFIR_IDHIT_MASK
Definition: S32K144.h:1423
static uint32_t FLEXCAN_HAL_GetAllMsgBuffIntStatusFlag(const CAN_Type *base)
Gets all FlexCAN Message Buffer interrupt flags.
Definition: flexcan_hal.h:672
uint8_t FLEXCAN_HAL_GetPayloadSize(const CAN_Type *base)
Gets the payload size of the MBs.
Definition: flexcan_hal.c:1836
status_t FLEXCAN_HAL_GetMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, flexcan_msgbuff_t *msgBuff)
Gets the FlexCAN message buffer fields.
Definition: flexcan_hal.c:838
status_t FLEXCAN_HAL_SetMsgBuffIntCmd(CAN_Type *base, uint32_t msgBuffIdx, bool enable)
Enables/Disables the FlexCAN Message Buffer interrupt.
Definition: flexcan_hal.c:1210
__IO uint32_t FDCTRL
Definition: S32K144.h:980
void FLEXCAN_HAL_Disable(CAN_Type *base)
Disables FlexCAN controller.
Definition: flexcan_hal.c:408
flexcan_pn_filter_combination_t filterComb
Definition: flexcan_hal.h:249
status_t FLEXCAN_HAL_LockRxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx)
Locks the FlexCAN Rx message buffer.
Definition: flexcan_hal.c:918
__IO uint32_t CTRL1
Definition: S32K144.h:938
#define CAN_CTRL1_CLKSRC_MASK
Definition: S32K144.h:1154
uint8_t FLEXCAN_HAL_GetMsgBuffIntStatusFlag(const CAN_Type *base, uint32_t msgBuffIdx)
Gets the individual FlexCAN MB interrupt flag.
Definition: flexcan_hal.c:1304
void FLEXCAN_HAL_SetRxFifoGlobalStdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN RX FIFO global standard mask.
Definition: flexcan_hal.c:1434
static uint32_t FLEXCAN_HAL_GetErrStatus(const CAN_Type *base)
Gets error and status.
Definition: flexcan_hal.h:711
void FLEXCAN_HAL_EnterFreezeMode(CAN_Type *base)
Freezes the FlexCAN module.
Definition: flexcan_hal.c:1288
#define CAN_FDCTRL_TDCFAIL_MASK
Definition: S32K144.h:1685
__IO uint32_t IFLAG1
Definition: S32K144.h:949
void FLEXCAN_HAL_SetSelfReception(CAN_Type *base, bool enable)
Enables/Disables the Self Reception feature.
Definition: flexcan_hal.c:1882
__IO uint32_t MCR
Definition: S32K144.h:937
static bool FLEXCAN_HAL_GetClock(const CAN_Type *base)
Reads the clock source for FlexCAN Protocol Engine (PE).
Definition: flexcan_hal.h:342
#define CAN_MCR_RFEN_MASK
Definition: S32K144.h:1105
#define CAN_MCR_PNET_EN_MASK
Definition: S32K144.h:1061
void FLEXCAN_HAL_SetErrIntCmd(CAN_Type *base, flexcan_int_type_t errType, bool enable)
Enables error interrupt of the FlexCAN module.
Definition: flexcan_hal.c:1247
flexcan_int_type_t
FlexCAN error interrupt types Implements : flexcan_int_type_t_Class.
Definition: flexcan_hal.h:157
flexcan_pn_id_filter_t idFilter2
Definition: flexcan_hal.h:251
void FLEXCAN_HAL_SetRxMsgBuff15StdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN Rx Message Buffer BUF15 standard mask.
Definition: flexcan_hal.c:1586
flexcan_pn_payload_filter_t payloadFilter
Definition: flexcan_hal.h:254
void FLEXCAN_HAL_SetOperationMode(CAN_Type *base, flexcan_operation_modes_t mode)
Set operation mode.
Definition: flexcan_hal.c:1671
void FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN Rx Message Buffer global standard mask.
Definition: flexcan_hal.c:1543
FlexCAN timing related structures Implements : flexcan_time_segment_t_Class.
Definition: flexcan_hal.h:198
void FLEXCAN_HAL_SetRxMaskType(CAN_Type *base, flexcan_rx_mask_type_t type)
Sets the Rx masking type.
Definition: flexcan_hal.c:1404
flexcan_pn_filter_combination_t
Pretended Networking filtering combinations.
Definition: flexcan_hal.h:225
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:31
__IO uint32_t TIMER
Definition: S32K144.h:939
static void FLEXCAN_HAL_UnlockRxMsgBuff(const CAN_Type *base)
Unlocks the FlexCAN Rx message buffer.
Definition: flexcan_hal.h:525
flexcan_operation_modes_t
FlexCAN operation modes Implements : flexcan_operation_modes_t_Class.
Definition: flexcan_hal.h:54
#define CAN_CTRL1_TWRNMSK_MASK
Definition: S32K144.h:1146
void FLEXCAN_HAL_SetRxFifoFilter(CAN_Type *base, flexcan_rx_fifo_id_element_format_t idFormat, const flexcan_id_table_t *idFilterTable)
Sets the FlexCAN Rx FIFO fields.
Definition: flexcan_hal.c:1090
static bool FLEXCAN_HAL_IsRxFifoEnabled(const CAN_Type *base)
Checks if Rx FIFO is enabled.
Definition: flexcan_hal.h:557
void FLEXCAN_HAL_SetRxFifoFilterNum(CAN_Type *base, uint32_t number)
Sets the number of the Rx FIFO filters.
Definition: flexcan_hal.c:1011
flexcan_rx_fifo_id_element_format_t
ID formats for RxFIFO Implements : flexcan_rx_fifo_id_element_format_t_Class.
Definition: flexcan_hal.h:109
void FLEXCAN_HAL_ReadRxFifo(const CAN_Type *base, flexcan_msgbuff_t *rxFifo)
Gets the FlexCAN Rx FIFO data.
Definition: flexcan_hal.c:1358
status_t FLEXCAN_HAL_SetRxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, const flexcan_msgbuff_code_status_t *cs, uint32_t msgId)
Sets the FlexCAN message buffer fields for receiving.
Definition: flexcan_hal.c:752
FlexCAN message buffer structure Implements : flexcan_msgbuff_t_Class.
Definition: flexcan_hal.h:188
#define CAN_CTRL1_ERRMSK_MASK
Definition: S32K144.h:1158
flexcan_msgbuff_id_type_t msgIdType
Definition: flexcan_hal.h:178
#define CAN_FDCTRL_TDCVAL_MASK
Definition: S32K144.h:1677
FlexCAN RX FIFO ID filter table structure Implements : flexcan_id_table_t_Class.
Definition: flexcan_hal.h:122
flexcan_pn_filter_selection_t
Pretended Networking matching schemes.
Definition: flexcan_hal.h:233
static void FLEXCAN_HAL_SetPN(CAN_Type *base, bool enable)
Enables/Disables the Pretended Networking mode.
Definition: flexcan_hal.h:973
#define CAN_CTRL1_RWRNMSK_MASK
Definition: S32K144.h:1142
status_t FLEXCAN_HAL_SetRxIndividualStdMask(CAN_Type *base, uint32_t msgBuffIdx, uint32_t stdMask)
Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO...
Definition: flexcan_hal.c:1476
Pretended Networking configuration structure Implements : flexcan_pn_config_t_Class.
Definition: flexcan_hal.h:244
#define CAN_RXFIR_IDHIT_SHIFT
Definition: S32K144.h:1424
void FLEXCAN_HAL_Init(CAN_Type *base)
Initializes the FlexCAN controller.
Definition: flexcan_hal.c:450
uint32_t * idFilter
Definition: flexcan_hal.h:125
status_t FLEXCAN_HAL_SetTxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, const flexcan_msgbuff_code_status_t *cs, uint32_t msgId, const uint8_t *msgData)
Sets the FlexCAN message buffer fields for transmitting.
Definition: flexcan_hal.c:603
#define CAN_FDCTRL_TDCFAIL_SHIFT
Definition: S32K144.h:1686
static void FLEXCAN_HAL_ClearTDCFail(CAN_Type *base)
Clears the TDC Fail flag.
Definition: flexcan_hal.h:942
status_t FLEXCAN_HAL_SetMaxMsgBuffNum(CAN_Type *base, uint32_t maxMsgBuffNum)
Sets the maximum number of Message Buffers.
Definition: flexcan_hal.c:1033
__IO uint32_t IMASK1
Definition: S32K144.h:947
void FLEXCAN_HAL_GetWMB(const CAN_Type *base, uint8_t wmbIndex, flexcan_msgbuff_t *wmb)
Extracts one of the frames which triggered the wake up event.
void FLEXCAN_HAL_ExitOperationMode(CAN_Type *base, flexcan_operation_modes_t mode)
Exit operation mode.
Definition: flexcan_hal.c:1722
void FLEXCAN_HAL_SelectClock(CAN_Type *base, flexcan_clk_source_t clk)
Selects the clock source for FlexCAN.
flexcan_msgbuff_id_type_t
FlexCAN Message Buffer ID type Implements : flexcan_msgbuff_id_type_t_Class.
Definition: flexcan_hal.h:139
flexcan_clk_source_t
FlexCAN clock source Implements : flexcan_clk_source_t_Class.
Definition: flexcan_hal.h:148
static uint8_t FLEXCAN_HAL_GetTDCValue(const CAN_Type *base)
Gets the value of the Transceiver Delay Compensation.
Definition: flexcan_hal.h:917
void FLEXCAN_HAL_SetRxMsgBuff14ExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX Message Buffer BUF14 extended mask.
Definition: flexcan_hal.c:1628
void FLEXCAN_HAL_SetRxMsgBuff15ExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX MB BUF15 extended mask.
Definition: flexcan_hal.c:1649
void FLEXCAN_HAL_SetPayloadSize(CAN_Type *base, flexcan_fd_payload_size_t payloadSize)
Sets the payload size of the MBs.
Definition: flexcan_hal.c:1802
#define CAN_CTRL1_CLKSRC_SHIFT
Definition: S32K144.h:1155
static void FLEXCAN_HAL_ClearMsgBuffIntStatusFlag(CAN_Type *base, uint32_t flag)
Clears the interrupt flag of the message buffers.
Definition: flexcan_hal.h:686
static uint32_t FLEXCAN_HAL_GetFreezeAck(const CAN_Type *base)
Gets the value of FlexCAN freeze ACK.
Definition: flexcan_hal.h:649
void FLEXCAN_HAL_SetStuffBitCount(CAN_Type *base, bool enable)
Enables/Disables the Stuff Bit Count for CAN FD frames.
Definition: flexcan_hal.c:1861
flexcan_fd_payload_size_t
FlexCAN payload sizes Implements : flexcan_fd_payload_size_t_Class.
Definition: flexcan_hal.h:99
static uint32_t FLEXCAN_HAL_GetRxFifoHitIdAcceptanceFilter(const CAN_Type *base)
Gets the FlexCAN ID acceptance filter hit indicator on Rx FIFO.
Definition: flexcan_hal.h:855
#define CAN_MCR_FRZACK_SHIFT
Definition: S32K144.h:1090
flexcan_rx_mask_type_t
FlexCAN RX mask type. Implements : flexcan_rx_mask_type_t_Class.
Definition: flexcan_hal.h:131
#define CAN_MCR_RFEN_SHIFT
Definition: S32K144.h:1106
void FLEXCAN_HAL_GetErrCounter(const CAN_Type *base, flexcan_buserr_counter_t *errCount)
Gets the transmit error counter and receives the error counter.
Definition: flexcan_hal.c:1319
#define CAN_CTRL1_BOFFMSK_MASK
Definition: S32K144.h:1162
void FLEXCAN_HAL_SetRxFifoGlobalExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN Rx FIFO global extended mask.
Definition: flexcan_hal.c:1455
Pretended Networking payload filter.
Definition: flexcan_hal.h:216
flexcan_pn_filter_selection_t idFilterType
Definition: flexcan_hal.h:252
flexcan_pn_id_filter_t idFilter1
Definition: flexcan_hal.h:250
#define CAN_FDCTRL_TDCVAL_SHIFT
Definition: S32K144.h:1678
FlexCAN Message Buffer code and status for transmit and receive Implements : flexcan_msgbuff_code_sta...
Definition: flexcan_hal.h:175
#define CAN_MCR_PNET_EN(x)
Definition: S32K144.h:1064
#define CAN_MCR_FRZACK_MASK
Definition: S32K144.h:1089
flexcan_pn_filter_selection_t payloadFilterType
Definition: flexcan_hal.h:253
status_t FLEXCAN_HAL_SetRxIndividualExtMask(CAN_Type *base, uint32_t msgBuffIdx, uint32_t extMask)
Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx Message Buffers and the Rx FI...
Definition: flexcan_hal.c:1510
static bool FLEXCAN_HAL_GetTDCFail(const CAN_Type *base)
Gets the value of the TDC Fail flag.
Definition: flexcan_hal.h:931
void FLEXCAN_HAL_SetFDEnabled(CAN_Type *base, bool enable)
Enables/Disables Flexible Data rate (if supported).
Definition: flexcan_hal.c:1771
void FLEXCAN_HAL_SetRxMsgBuff14StdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN RX Message Buffer BUF14 standard mask.
Definition: flexcan_hal.c:1565
__IO uint32_t ESR1
Definition: S32K144.h:945