S32 SDK
rcm_hal.h
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1 /*
2  * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 #if !defined(RCM_HAL_H)
19 #define RCM_HAL_H
20 
21 #include "device_registers.h"
22 #include <stdbool.h>
23 
24 
37 /*******************************************************************************
38  * Definitions
39  ******************************************************************************/
40 
45 typedef enum {
46  RCM_WAKEUP, /* Wakeup */
47  RCM_LOW_VOLT_DETECT, /* Low voltage detect reset */
48  RCM_LOSS_OF_CLK, /* Loss of clock reset */
49  RCM_LOSS_OF_LOCK, /* Loss of lock reset */
50  RCM_WATCH_DOG, /* Watch dog reset */
51  RCM_EXTERNAL_PIN, /* External pin reset */
52  RCM_POWER_ON, /* Power on reset */
53  RCM_SJTAG, /* JTAG generated reset */
54  RCM_CORE_LOCKUP, /* core lockup reset */
55  RCM_SOFTWARE, /* Software reset */
56  RCM_SMDM_AP, /* MDM-AP system reset */
57  RCM_STOP_MODE_ACK_ERR, /* Stop mode ack error reset */
58  RCM_TAMPERR, /* Tamperr */
59  RCM_CORE1, /* Core1 */
62 
67 typedef enum
68 {
69  RCM_FILTER_DISABLED, /* All filtering disabled */
70  RCM_FILTER_BUS_CLK, /* Bus clock filter enabled */
71  RCM_FILTER_LPO_CLK, /* LPO clock filter enabled */
72  RCM_FILTER_RESERVED /* Reserved setting */
74 
75 
80 typedef enum
81 {
82  RCM_10LPO_CYCLES_DELAY, /* reset delay time 10 LPO cycles */
83  RCM_34LPO_CYCLES_DELAY, /* reset delay time 34 LPO cycles */
84  RCM_130LPO_CYCLES_DELAY, /* reset delay time 130 LPO cycles */
85  RCM_514LPO_CYCLES_DELAY /* reset delay time 514 LPO cycles */
87 
92 typedef struct
93 {
94  uint32_t majorNumber;
95  uint32_t minorNumber;
96  uint32_t featureNumber;
98 
99 
100 /*******************************************************************************
101  * API
102  ******************************************************************************/
103 #if defined(__cplusplus)
104 extern "C" {
105 #endif /* __cplusplus*/
106 
109 
116 void RCM_HAL_GetVersion(const RCM_Type* const baseAddr, rcm_version_info_t* const versionInfo);
117 
127 bool RCM_HAL_GetSrcIndicationFeatureAvailability(const RCM_Type* const baseAddr, const rcm_source_names_t srcName);
128 
138 bool RCM_HAL_GetSrcStatusCmd(const RCM_Type* const baseAddr, const rcm_source_names_t srcName);
139 
149 void RCM_HAL_SetResetIntCmd(RCM_Type* const baseAddr, const rcm_source_names_t resetInterrupt, const bool enable);
150 
151 
161 static inline void RCM_HAL_SetAllResetIntCmd(RCM_Type* const baseAddr, const bool enable)
162 {
163  uint32_t regValue = (uint32_t)baseAddr->SRIE;
164  regValue &= (uint32_t)(~(RCM_SRIE_GIE_MASK));
165  regValue |= RCM_SRIE_GIE(enable?1UL:0UL);
166  baseAddr->SRIE = (uint32_t)regValue;
167 }
168 
179 bool RCM_HAL_GetStickySrcStatusCmd(const RCM_Type* const baseAddr, const rcm_source_names_t srcName);
180 
188 void RCM_HAL_ClearStickySrcStatus(RCM_Type* const baseAddr);
189 
199 static inline void RCM_HAL_SetFilterStopModeCmd(RCM_Type* const baseAddr, const bool enable)
200 {
201  uint32_t regValue = (uint32_t)baseAddr->RPC;
202  regValue &= (uint32_t)(~(RCM_RPC_RSTFLTSS_MASK));
203  regValue |= RCM_RPC_RSTFLTSS(enable?1UL:0UL);
204  baseAddr->RPC = (uint32_t)regValue;
205 }
206 
216 static inline bool RCM_HAL_GetFilterStopModeCmd(const RCM_Type* const baseAddr)
217 {
218  uint32_t regValue = (uint32_t)baseAddr->RPC;
219  regValue = (regValue & RCM_RPC_RSTFLTSS_MASK) >> RCM_RPC_RSTFLTSS_SHIFT;
220  return (regValue == 0UL) ? false : true;
221 }
222 
232 static inline void RCM_HAL_SetFilterRunWaitMode(RCM_Type* const baseAddr, const rcm_filter_run_wait_modes_t mode)
233 {
234  uint32_t regValue = baseAddr->RPC;
235  regValue &= ~(RCM_RPC_RSTFLTSRW_MASK);
236  regValue |= RCM_RPC_RSTFLTSRW(mode);
237  baseAddr->RPC = regValue;
238 }
239 
250 {
252  uint32_t regValue = baseAddr->RPC;
253  regValue = (regValue & RCM_RPC_RSTFLTSRW_MASK) >> RCM_RPC_RSTFLTSRW_SHIFT;
254  switch(regValue)
255  {
256  case 0UL:
257  retValue = RCM_FILTER_DISABLED;
258  break;
259  case 1UL:
260  retValue = RCM_FILTER_BUS_CLK;
261  break;
262  case 2UL:
263  retValue = RCM_FILTER_LPO_CLK;
264  break;
265  case 3UL:
266  default:
267  retValue = RCM_FILTER_RESERVED;
268  break;
269  }
270  return retValue;
271 }
272 
282 static inline void RCM_HAL_SetFilterWidth(RCM_Type* const baseAddr, const uint32_t width)
283 {
284  uint32_t regValue = baseAddr->RPC;
285  regValue &= ~(RCM_RPC_RSTFLTSEL_MASK);
286  regValue |= RCM_RPC_RSTFLTSEL(width);
287  baseAddr->RPC = regValue;
288 }
289 
299 static inline uint32_t RCM_HAL_GetFilterWidth(const RCM_Type* const baseAddr)
300 {
301  uint32_t regValue = baseAddr->RPC;
302  regValue = (regValue & RCM_RPC_RSTFLTSEL_MASK) >> RCM_RPC_RSTFLTSEL_SHIFT;
303  return (uint32_t)regValue;
304 }
305 
315 static inline void RCM_HAL_SetResetDelayTimeValue(RCM_Type* const baseAddr,
316  const rcm_reset_delay_time_t value)
317 {
318  uint32_t regValue = baseAddr->SRIE;
319  regValue &= ~(RCM_SRIE_DELAY_MASK);
320  regValue |= RCM_SRIE_DELAY(value);
321  baseAddr->SRIE = regValue;
322 }
323 
326 #if defined(__cplusplus)
327 }
328 #endif /* __cplusplus*/
329 
332 #endif /* RCM_HAL_H */
333 /*******************************************************************************
334  * EOF
335  ******************************************************************************/
336 
rcm_source_names_t
System Reset Source Name definitions Implements rcm_source_names_t_Class.
Definition: rcm_hal.h:45
static void RCM_HAL_SetFilterRunWaitMode(RCM_Type *const baseAddr, const rcm_filter_run_wait_modes_t mode)
Sets the reset pin filter in run and wait mode.
Definition: rcm_hal.h:232
#define RCM_RPC_RSTFLTSEL_MASK
Definition: S32K144.h:8864
uint32_t featureNumber
Definition: rcm_hal.h:96
#define RCM_RPC_RSTFLTSRW_MASK
Definition: S32K144.h:8856
static void RCM_HAL_SetFilterStopModeCmd(RCM_Type *const baseAddr, const bool enable)
Sets the reset pin filter in stop mode.
Definition: rcm_hal.h:199
__IO uint32_t SRIE
Definition: S32K144.h:8708
static rcm_filter_run_wait_modes_t RCM_HAL_GetFilterRunWaitMode(const RCM_Type *const baseAddr)
Gets the reset pin filter for stop mode.
Definition: rcm_hal.h:249
rcm_filter_run_wait_modes_t
Reset pin filter select in Run and Wait modes Implements rcm_filter_run_wait_modes_t_Class.
Definition: rcm_hal.h:67
void RCM_HAL_ClearStickySrcStatus(RCM_Type *const baseAddr)
Clear the sticky reset source status.
Definition: rcm_hal.c:331
#define RCM_RPC_RSTFLTSS(x)
Definition: S32K144.h:8863
bool RCM_HAL_GetStickySrcStatusCmd(const RCM_Type *const baseAddr, const rcm_source_names_t srcName)
Gets the sticky reset source status.
Definition: rcm_hal.c:269
static uint32_t RCM_HAL_GetFilterWidth(const RCM_Type *const baseAddr)
Gets the reset pin filter for stop mode.
Definition: rcm_hal.h:299
#define RCM_RPC_RSTFLTSRW_SHIFT
Definition: S32K144.h:8857
bool RCM_HAL_GetSrcStatusCmd(const RCM_Type *const baseAddr, const rcm_source_names_t srcName)
Gets the reset source status.
Definition: rcm_hal.c:143
static bool RCM_HAL_GetFilterStopModeCmd(const RCM_Type *const baseAddr)
Gets the reset pin filter in stop mode.
Definition: rcm_hal.h:216
#define RCM_SRIE_DELAY_MASK
Definition: S32K144.h:8914
__IO uint32_t RPC
Definition: S32K144.h:8705
#define RCM_SRIE_GIE_MASK
Definition: S32K144.h:8934
RCM module version number Implements rcm_version_info_t_Class.
Definition: rcm_hal.h:92
#define RCM_RPC_RSTFLTSEL_SHIFT
Definition: S32K144.h:8865
#define RCM_RPC_RSTFLTSRW(x)
Definition: S32K144.h:8859
uint32_t majorNumber
Definition: rcm_hal.h:94
void RCM_HAL_GetVersion(const RCM_Type *const baseAddr, rcm_version_info_t *const versionInfo)
Get the version of the RCM module.
Definition: rcm_hal.c:49
#define RCM_RPC_RSTFLTSEL(x)
Definition: S32K144.h:8867
bool RCM_HAL_GetSrcIndicationFeatureAvailability(const RCM_Type *const baseAddr, const rcm_source_names_t srcName)
Checks the existence of the status indication feature for a reset source.
Definition: rcm_hal.c:75
#define RCM_RPC_RSTFLTSS_MASK
Definition: S32K144.h:8860
#define RCM_SRIE_DELAY(x)
Definition: S32K144.h:8917
static void RCM_HAL_SetAllResetIntCmd(RCM_Type *const baseAddr, const bool enable)
Enables/disables all system reset interrupts.
Definition: rcm_hal.h:161
uint32_t minorNumber
Definition: rcm_hal.h:95
#define RCM_SRIE_GIE(x)
Definition: S32K144.h:8937
rcm_reset_delay_time_t
Reset delay time Implements rcm_reset_delay_time_t_Class.
Definition: rcm_hal.h:80
static void RCM_HAL_SetResetDelayTimeValue(RCM_Type *const baseAddr, const rcm_reset_delay_time_t value)
Sets reset delay time.
Definition: rcm_hal.h:315
void RCM_HAL_SetResetIntCmd(RCM_Type *const baseAddr, const rcm_source_names_t resetInterrupt, const bool enable)
Enables/disables a specified system reset interrupt.
Definition: rcm_hal.c:203
#define RCM_RPC_RSTFLTSS_SHIFT
Definition: S32K144.h:8861
static void RCM_HAL_SetFilterWidth(RCM_Type *const baseAddr, const uint32_t width)
Sets the reset pin filter width.
Definition: rcm_hal.h:282