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S32 SDK
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Modules | |
LPSPI Register Masks | |
Data Structures | |
struct | LPSPI_Type |
Macros | |
#define | LPSPI_INSTANCE_COUNT (3u) |
#define | LPSPI0_BASE (0x4002C000u) |
#define | LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) |
#define | LPSPI1_BASE (0x4002D000u) |
#define | LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) |
#define | LPSPI2_BASE (0x4002E000u) |
#define | LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) |
#define | LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE } |
#define | LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2 } |
#define | LPSPI_IRQS_ARR_COUNT (1u) |
#define | LPSPI_IRQS_CH_COUNT (1u) |
#define | LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn } |
Typedefs | |
typedef struct LPSPI_Type * | LPSPI_MemMapPtr |
#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) |
#define LPSPI0_BASE (0x4002C000u) |
#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) |
#define LPSPI1_BASE (0x4002D000u) |
#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) |
#define LPSPI2_BASE (0x4002E000u) |
#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE } |
#define LPSPI_INSTANCE_COUNT (3u) |
#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn } |
#define LPSPI_IRQS_ARR_COUNT (1u) |
#define LPSPI_IRQS_CH_COUNT (1u) |
typedef struct LPSPI_Type * LPSPI_MemMapPtr |