S32 SDK
ftm_hal.c
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016 -2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
28 #include "ftm_hal.h"
29 
30 
31 /*******************************************************************************
32  * Definitions
33  ******************************************************************************/
34 
35 /*FUNCTION**********************************************************************
36  *
37  * Function Name : FTM_HAL_Init
38  * Description : Initializes the FTM. This function will enable the flexTimer module
39  * and selects one pre-scale factor for the FTM clock source.
40  *
41  * Implements : FTM_HAL_Init_Activity
42  *END**************************************************************************/
43 void FTM_HAL_Init(FTM_Type * const ftmBase,
44  ftm_clock_ps_t ftmClockPrescaler)
45 {
46  /* Use FTM mode */
47  FTM_HAL_Enable(ftmBase, true);
48  FTM_HAL_SetClockPs(ftmBase, ftmClockPrescaler);
49 }
50 
51 /*FUNCTION**********************************************************************
52  *
53  * Function Name : FTM_HAL_Reset
54  * Description : Resets the FTM registers. All the register use in the driver should be
55  * reset to default value of each register.
56  *
57  * Implements : FTM_HAL_Reset_Activity
58  *END**************************************************************************/
59 void FTM_HAL_Reset(FTM_Type * const ftmBase)
60 {
61  uint8_t chnIndex;
62 
63  /* WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS */
64  ((ftmBase)->FMS) &= 0U;
65  /* This is the reset value for MODE register. WPDIS bit is set to disable write protection */
66  ((ftmBase)->MODE) = 0x00000004U;
67  ((ftmBase)->SC) &= 0U;
68  ((ftmBase)->CNT) = 0U;
69  ((ftmBase)->MOD) = 0U;
70  ((ftmBase)->CNTIN) = 0U;
71  ((ftmBase)->STATUS) &= 0U;
72  ((ftmBase)->SYNC) = 0U;
73  ((ftmBase)->OUTINIT) = 0U;
74  ((ftmBase)->OUTMASK) = 0U;
75  ((ftmBase)->COMBINE) = 0U;
76  ((ftmBase)->DEADTIME) = 0U;
77  ((ftmBase)->EXTTRIG) &= 0U;
78  ((ftmBase)->POL) = 0U;
79  ((ftmBase)->FILTER) = 0U;
80  ((ftmBase)->FLTCTRL) = 0U;
81  ((ftmBase)->QDCTRL) = 0U;
82  ((ftmBase)->CONF) = 0U;
83  ((ftmBase)->FLTPOL) = 0U;
84  ((ftmBase)->SYNCONF) = 0U;
85  ((ftmBase)->INVCTRL) = 0U;
86  ((ftmBase)->SWOCTRL) = 0U;
87  ((ftmBase)->PWMLOAD) = 0U;
88  ((ftmBase)->HCR) = 0U;
89  /* Set to reset value all CnV and CnSC registers */
90  for (chnIndex = 0; chnIndex < FEATURE_FTM_CHANNEL_COUNT; chnIndex++)
91  {
92  ((ftmBase)->CONTROLS[chnIndex].CnSC) &= 0U;
93  ((ftmBase)->CONTROLS[chnIndex].CnV) = 0U;
94  }
95 }
96 
97 /*FUNCTION**********************************************************************
98  *
99  * Function Name : FTM_HAL_SetChnTriggerCmd
100  * Description : Enables or disables the generation of the FTM peripheral timer channel trigger.
101  * Enables or disables the generation of the FTM peripheral timer channel trigger when the
102  * FTM counter is equal to its initial value.
103  *
104  * Implements : FTM_HAL_SetChnTriggerCmd_Activity
105  *END**************************************************************************/
106 void FTM_HAL_SetChnTriggerCmd(FTM_Type * const ftmBase,
107  uint8_t channel,
108  bool enable)
109 {
111  uint32_t value = 0U;
112 
113  if (channel < 2U)
114  {
115  value = (uint32_t)FTM_EXTTRIG_CH0TRIG_MASK << (uint32_t)channel;
116  }
117  else if (channel < 6U)
118  {
119  value = (uint32_t)FTM_EXTTRIG_CH2TRIG_MASK << ((uint32_t)(channel) - 2U);
120  }
121  else
122  {
123  value = (uint32_t)FTM_EXTTRIG_CH6TRIG_MASK << ((uint32_t)(channel) - 6U);
124  }
125 
126  if (true == enable)
127  {
128  ((ftmBase)->EXTTRIG) |= value;
129  }
130  else
131  {
132  ((ftmBase)->EXTTRIG) &= ~value;
133  }
134 }
135 
136 /*FUNCTION**********************************************************************
137  *
138  * Function Name : FTM_HAL_SetChnInputCaptureFilter
139  * Description : Sets the FTM peripheral timer channel input capture filter value.
140  *
141  * Implements : FTM_HAL_SetChnInputCaptureFilter_Activity
142  *END**************************************************************************/
144  uint8_t channel,
145  uint8_t value)
146 {
147  DEV_ASSERT(CHAN4_IDX > channel);
148 
149  switch (channel)
150  {
151  case CHAN0_IDX:
153  break;
154  case CHAN1_IDX:
156  break;
157  case CHAN2_IDX:
159  break;
160  case CHAN3_IDX:
162  break;
163  default:
164  /* Nothing to do */
165  break;
166  }
167 }
168 
169 /*******************************************************************************
170  * EOF
171  ******************************************************************************/
#define FTM_FILTER_CH3FVAL(x)
Definition: S32K144.h:4625
#define FTM_EXTTRIG_CH6TRIG_MASK
Definition: S32K144.h:4539
void FTM_HAL_SetChnTriggerCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the generation of the FTM peripheral timer channel trigger when the FTM counter i...
Definition: ftm_hal.c:106
#define FTM_FILTER_CH2FVAL_MASK
Definition: S32K144.h:4618
static void FTM_HAL_Enable(FTM_Type *const ftmBase, bool enable)
Enables the FTM peripheral timer group.
Definition: ftm_hal.h:1468
#define FTM_FILTER_CH3FVAL_MASK
Definition: S32K144.h:4622
#define FTM_EXTTRIG_CH2TRIG_MASK
Definition: S32K144.h:4507
#define FTM_FILTER_CH1FVAL(x)
Definition: S32K144.h:4617
#define DEV_ASSERT(x)
Definition: devassert.h:78
#define CHAN1_IDX
Channel number for CHAN2.
Definition: ftm_hal.h:231
#define FEATURE_FTM_CHANNEL_COUNT
#define FTM_FILTER_CH0FVAL(x)
Definition: S32K144.h:4613
void FTM_HAL_SetChnInputCaptureFilter(FTM_Type *const ftmBase, uint8_t channel, uint8_t value)
Sets the FTM peripheral timer channel input capture filter value.
Definition: ftm_hal.c:143
#define FTM_EXTTRIG_CH0TRIG_MASK
Definition: S32K144.h:4523
#define CHAN4_IDX
Channel number for CHAN5.
Definition: ftm_hal.h:237
#define CHAN3_IDX
Channel number for CHAN4.
Definition: ftm_hal.h:235
static void FTM_HAL_SetClockPs(FTM_Type *const ftmBase, ftm_clock_ps_t ps)
Sets the FTM clock divider.
Definition: ftm_hal.h:496
void FTM_HAL_Init(FTM_Type *const ftmBase, ftm_clock_ps_t ftmClockPrescaler)
Initializes the FTM. This function will enable the flexTimer module and selects one pre-scale factor ...
Definition: ftm_hal.c:43
#define FTM_FILTER_CH1FVAL_MASK
Definition: S32K144.h:4614
#define FTM_FILTER_CH2FVAL(x)
Definition: S32K144.h:4621
void FTM_HAL_Reset(FTM_Type *const ftmBase)
Resets the FTM registers. All the register use in the driver should be reset to default value of each...
Definition: ftm_hal.c:59
#define FTM_FILTER_CH0FVAL_MASK
Definition: S32K144.h:4610
#define FTM_RMW_FILTER(base, mask, value)
FILTER - Read and modify and write Filter (RW)
Definition: ftm_hal.h:194
#define CHAN2_IDX
Channel number for CHAN3.
Definition: ftm_hal.h:233
#define CHAN0_IDX
Channel number for CHAN1.
Definition: ftm_hal.h:229
ftm_clock_ps_t
FlexTimer pre-scaler factor selection for the clock source. In quadrature decoder mode set FTM_CLOCK_...
Definition: ftm_hal.h:268