S32 SDK
pcc_hal.h
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 #ifndef PCC_HAL_H
19 #define PCC_HAL_H
20 
21 #include "device_registers.h"
22 #include <stdbool.h>
23 
103 /*******************************************************************************
104  * Definitions
105  ******************************************************************************/
106 
112 extern const uint16_t clockNameMappings[CLOCK_NAME_COUNT];
113 
114 
118 typedef enum
119 {
120  CLK_SRC_OFF = 0x00U, /* Clock is off */
121  CLK_SRC_SOSC = 0x01U, /* OSCCLK - System Oscillator Bus Clock */
122  CLK_SRC_SIRC = 0x02U, /* SCGIRCLK - Slow IRC Clock */
123  CLK_SRC_FIRC = 0x03U, /* SCGFIRCLK - Fast IRC Clock */
124  CLK_SRC_SPLL = 0x06U /* SCGPCLK System PLL clock */
125 
127 
131 typedef enum
132 {
133  MULTIPLY_BY_ONE = 0x00U, /* Fractional value is zero */
134  MULTIPLY_BY_TWO = 0x01U /* Fractional value is one */
135 
137 
141 typedef enum
142 {
143  DIVIDE_BY_ONE = 0x00U, /* Divide by 1 (pass-through, no clock divide) */
144  DIVIDE_BY_TWO = 0x01U, /* Divide by 2 */
145  DIVIDE_BY_THREE = 0x02U, /* Divide by 3 */
146  DIVIDE_BY_FOUR = 0x03U, /* Divide by 4 */
147  DIVIDE_BY_FIVE = 0x04U, /* Divide by 5 */
148  DIVIDE_BY_SIX = 0x05U, /* Divide by 6 */
149  DIVIDE_BY_SEVEN = 0x06U, /* Divide by 7 */
150  DIVIDE_BY_EIGTH = 0x07U /* Divide by 8 */
151 
153 
157 typedef struct
158 {
159  /* clockName is the name of the peripheral clock
160  * must be one of the following values (see the clock_names_t type from S32K144_clock_names.h)
161  * PCC_DMA0_CLOCK
162  * PCC_MPU0_CLOCK
163  * ...
164  * PCC_LPUART3_CLOCK
165  */
167  bool clkGate;
172 
176 typedef struct
177 {
178  uint32_t count;
181 } pcc_config_t;
182 
183 
184 /*******************************************************************************
185  * API
186  ******************************************************************************/
187 
188 #if defined(__cplusplus)
189 extern "C" {
190 #endif
191 
212  const pcc_config_t* const config);
230 static inline void PCC_HAL_SetClockMode(PCC_Type* const base,
231  const clock_names_t clockName,
232  const bool isClockEnabled)
233 {
234  uint32_t regValue = (uint32_t)base->PCCn[clockNameMappings[clockName]];
235  regValue &= (uint32_t)(~(PCC_PCCn_CGC_MASK));
236  regValue |= PCC_PCCn_CGC((isClockEnabled == true) ? 1UL : 0UL);
237  base->PCCn[clockNameMappings[clockName]] = (uint32_t)regValue;
238 }
239 
257 static inline void PCC_HAL_SetClockSourceSel(PCC_Type* const base,
258  const clock_names_t clockName,
259  const peripheral_clock_source_t clockSource)
260 {
261  uint32_t clkSource, regValue;
262 
263  switch(clockSource)
264  {
265  case CLK_SRC_SPLL:
266  clkSource = 6U;
267  break;
268  case CLK_SRC_FIRC:
269  clkSource = 3U;
270  break;
271  case CLK_SRC_SIRC:
272  clkSource = 2U;
273  break;
274  case CLK_SRC_SOSC:
275  clkSource = 1U;
276  break;
277  case CLK_SRC_OFF:
278  /* Pass-thourgh */
279  default:
280  clkSource = 0U;
281  break;
282  }
283 
284  regValue = base->PCCn[clockNameMappings[clockName]];
285  regValue &= ~(PCC_PCCn_PCS_MASK);
286  regValue |= PCC_PCCn_PCS(clkSource);
287  base->PCCn[clockNameMappings[clockName]] = regValue;
288 }
289 
307 static inline void PCC_HAL_SetFracValueSel(PCC_Type* const base,
308  const clock_names_t clockName,
309  const peripheral_clock_frac_t fracValue)
310 {
311  uint32_t fractionalValue, regValue;
312 
313  switch (fracValue)
314  {
315  case MULTIPLY_BY_TWO:
316  fractionalValue = 1U;
317  break;
318  case MULTIPLY_BY_ONE:
319  /* Pass-through */
320  default:
321  fractionalValue = 0U;
322  break;
323  }
324 
325  regValue = (uint32_t)base->PCCn[clockNameMappings[clockName]];
326  regValue &= (uint32_t)(~(PCC_PCCn_FRAC_MASK));
327  regValue |= PCC_PCCn_FRAC(fractionalValue);
328  base->PCCn[clockNameMappings[clockName]] = regValue;
329 }
330 
348 static inline void PCC_HAL_SetDividerValueSel(PCC_Type* const base,
349  const clock_names_t clockName,
350  const peripheral_clock_divider_t divValue)
351 {
352  uint32_t dividerValue, regValue;
353 
354  switch(divValue)
355  {
356  case DIVIDE_BY_EIGTH:
357  dividerValue = 7U;
358  break;
359  case DIVIDE_BY_SEVEN:
360  dividerValue = 6U;
361  break;
362  case DIVIDE_BY_SIX:
363  dividerValue = 5U;
364  break;
365  case DIVIDE_BY_FIVE:
366  dividerValue = 4U;
367  break;
368  case DIVIDE_BY_FOUR :
369  dividerValue = 3U;
370  break;
371  case DIVIDE_BY_THREE:
372  dividerValue = 2U;
373  break;
374  case DIVIDE_BY_TWO:
375  dividerValue = 1U;
376  break;
377  case DIVIDE_BY_ONE:
378  /* Pass-thourgh */
379  default:
380  dividerValue = 0U;
381  break;
382  }
383 
384  regValue = base->PCCn[clockNameMappings[clockName]];
385  regValue &= ~(PCC_PCCn_PCD_MASK);
386  regValue |= PCC_PCCn_PCD(dividerValue);
387  base->PCCn[clockNameMappings[clockName]] = regValue;
388 }
389 
405 static inline bool PCC_HAL_GetClockMode(const PCC_Type* const base,
406  const clock_names_t clockName)
407 {
408  uint32_t regValue = (uint32_t)base->PCCn[clockNameMappings[clockName]];
409  regValue = (regValue & PCC_PCCn_CGC_MASK) >> PCC_PCCn_CGC_SHIFT;
410  return (regValue == 0U) ? false : true;
411 }
412 
432  const clock_names_t clockName)
433 {
434  peripheral_clock_source_t retValue;
435  uint32_t regValue = base->PCCn[clockNameMappings[clockName]];
436  regValue = (regValue & PCC_PCCn_PCS_MASK) >> PCC_PCCn_PCS_SHIFT;
437 
438  switch(regValue)
439  {
440  case 6U:
441  retValue = CLK_SRC_SPLL;
442  break;
443  case 3U:
444  retValue = CLK_SRC_FIRC;
445  break;
446  case 2U:
447  retValue = CLK_SRC_SIRC;
448  break;
449  case 1U:
450  retValue = CLK_SRC_SOSC;
451  break;
452  case 0U:
453  /* Pass-thourgh */
454  default:
455  retValue = CLK_SRC_OFF;
456  break;
457  }
458  return retValue;
459 }
460 
477  const clock_names_t clockName)
478 {
479  peripheral_clock_frac_t retValue;
480  uint32_t regValue = (uint32_t)base->PCCn[clockNameMappings[clockName]];
481  regValue = (regValue & PCC_PCCn_FRAC_MASK) >> PCC_PCCn_FRAC_SHIFT;
482 
483  switch(regValue)
484  {
485  case 1U:
486  retValue = MULTIPLY_BY_TWO;
487  break;
488  case 0U:
489  /* Pass-thourgh */
490  default:
491  retValue = MULTIPLY_BY_ONE;
492  break;
493  }
494  return retValue;
495 }
496 
519  const clock_names_t clockName)
520 {
522  uint32_t regValue = base->PCCn[clockNameMappings[clockName]];
523  regValue = (regValue & PCC_PCCn_PCD_MASK) >> PCC_PCCn_PCD_SHIFT;
524 
525  switch(regValue)
526  {
527  case 7U:
528  retValue = DIVIDE_BY_EIGTH;
529  break;
530  case 6U:
531  retValue = DIVIDE_BY_SEVEN;
532  break;
533  case 5U:
534  retValue = DIVIDE_BY_SIX;
535  break;
536  case 4U:
537  retValue = DIVIDE_BY_FIVE;
538  break;
539  case 3U:
540  retValue = DIVIDE_BY_FOUR;
541  break;
542  case 2U:
543  retValue = DIVIDE_BY_THREE;
544  break;
545  case 1U:
546  retValue = DIVIDE_BY_TWO;
547  break;
548  case 0U:
549  /* Pass-thourgh */
550  default:
551  retValue = DIVIDE_BY_ONE;
552  break;
553  }
554  return retValue;
555 }
556 
572 static inline bool PCC_HAL_GetPeripheralMode(const PCC_Type* const base,
573  const clock_names_t clockName)
574 {
575  uint32_t regValue = (uint32_t)base->PCCn[clockNameMappings[clockName]];
576  regValue = (regValue & PCC_PCCn_PR_MASK) >> PCC_PCCn_PR_SHIFT;
577  return (regValue == 0U) ? false : true;
578 }
579 
580 #if FEATURE_PCC_HAS_IN_USE_FEATURE
581 
596 static inline bool PCC_HAL_GetPeripheralInUseMode(const PCC_Type* const base,
597  const clock_names_t clockName)
598 {
599  uint32_t regValue = (uint32_t)base->PCCn[clockNameMappings[clockName]];
600  regValue = (regValue & PCC_PCCn_INUSE_MASK) >> PCC_PCCn_INUSE_SHIFT;
601  return (regValue == 0U) ? false : true;
602 }
603 #endif /* FEATURE_PCC_HAS_IN_USE_FEATURE */
604 
605 
608 #if defined(__cplusplus)
609 }
610 #endif
611 
614 #endif /* PCC_HAL_H */
615 /*******************************************************************************
616  * EOF
617  ******************************************************************************/
618 
PCC peripheral instance clock configuration. Implements peripheral_clock_config_t_Class.
Definition: pcc_hal.h:157
static void PCC_HAL_SetClockSourceSel(PCC_Type *const base, const clock_names_t clockName, const peripheral_clock_source_t clockSource)
Selects the clock source for a given peripheral For example, to select the FIRC source for ADC clock...
Definition: pcc_hal.h:257
static void PCC_HAL_SetFracValueSel(PCC_Type *const base, const clock_names_t clockName, const peripheral_clock_frac_t fracValue)
Selects the fractional value for a given peripheral For example, to configure MULTIPLY_BY_ONE as frac...
Definition: pcc_hal.h:307
#define PCC_PCCn_PCS_MASK
Definition: S32K144.h:8199
#define PCC_PCCn_FRAC_SHIFT
Definition: S32K144.h:8196
#define PCC_PCCn_CGC_MASK
Definition: S32K144.h:8203
static peripheral_clock_divider_t PCC_HAL_GetDividerSel(const PCC_Type *const base, const clock_names_t clockName)
Gets the selection of the divider value for a specific peripheral.
Definition: pcc_hal.h:518
#define PCC_PCCn_PCD(x)
Definition: S32K144.h:8194
peripheral_clock_source_t clkSrc
Definition: pcc_hal.h:168
#define PCC_PCCn_PCS_SHIFT
Definition: S32K144.h:8200
static void PCC_HAL_SetDividerValueSel(PCC_Type *const base, const clock_names_t clockName, const peripheral_clock_divider_t divValue)
Selects the divider value for a given peripheral For example, to configure DIVIDE_BY_ONE as divider v...
Definition: pcc_hal.h:348
#define PCC_PCCn_PCD_SHIFT
Definition: S32K144.h:8192
#define PCC_PCCn_FRAC(x)
Definition: S32K144.h:8198
peripheral_clock_config_t * peripheralClocks
Definition: pcc_hal.h:179
peripheral_clock_source_t
PCC clock source select Implements peripheral_clock_source_t_Class.
Definition: pcc_hal.h:118
#define PCC_PCCn_PR_MASK
Definition: S32K144.h:8207
static bool PCC_HAL_GetClockMode(const PCC_Type *const base, const clock_names_t clockName)
Gets the clock gate control mode.
Definition: pcc_hal.h:405
peripheral_clock_divider_t
PCC divider value select Implements peripheral_clock_divider_t_Class.
Definition: pcc_hal.h:141
clock_names_t
Clock names.
static void PCC_HAL_SetClockMode(PCC_Type *const base, const clock_names_t clockName, const bool isClockEnabled)
Enables/disables the clock for a given peripheral. For example, to enable the ADC0 clock...
Definition: pcc_hal.h:230
uint32_t count
Definition: pcc_hal.h:178
static peripheral_clock_source_t PCC_HAL_GetClockSourceSel(const PCC_Type *const base, const clock_names_t clockName)
Gets the selection of a clock source for a specific peripheral.
Definition: pcc_hal.h:431
static peripheral_clock_frac_t PCC_HAL_GetFracValueSel(const PCC_Type *const base, const clock_names_t clockName)
Gets the selection of the fractional value for a specific peripheral.
Definition: pcc_hal.h:476
peripheral_clock_divider_t divider
Definition: pcc_hal.h:170
const uint16_t clockNameMappings[CLOCK_NAME_COUNT]
Clock name mappings Constant array storing the mappings between clock names and peripheral clock cont...
Definition: pcc_hal.c:43
clock_names_t clockName
Definition: pcc_hal.h:166
#define PCC_PCCn_FRAC_MASK
Definition: S32K144.h:8195
#define PCC_PCCn_PR_SHIFT
Definition: S32K144.h:8208
peripheral_clock_frac_t frac
Definition: pcc_hal.h:169
static bool PCC_HAL_GetPeripheralMode(const PCC_Type *const base, const clock_names_t clockName)
Tells whether a given peripheral is present or not.
Definition: pcc_hal.h:572
void PCC_HAL_SetPeripheralClockConfig(PCC_Type *const base, const pcc_config_t *const config)
Set the peripheral clock configuration.
Definition: pcc_hal.c:56
#define PCC_PCCn_PCD_MASK
Definition: S32K144.h:8191
#define PCC_PCCn_PCS(x)
Definition: S32K144.h:8202
peripheral_clock_frac_t
PCC fractional value select Implements peripheral_clock_frac_t_Class.
Definition: pcc_hal.h:131
#define PCC_PCCn_CGC(x)
Definition: S32K144.h:8206
#define PCC_PCCn_CGC_SHIFT
Definition: S32K144.h:8204
__IO uint32_t PCCn[PCC_PCCn_COUNT]
Definition: S32K144.h:8130
PCC configuration. Implements pcc_config_t_Class.
Definition: pcc_hal.h:176