100 #define DIVIDER_MIN_VALUE 1U
101 #define DIVIDER_MAX_VALUE 0xFFU
105 #define TX_SHIFTER(x) (x)
106 #define RX_SHIFTER(x) (uint8_t)((x) + 1U)
107 #define SCK_TIMER(x) (x)
108 #define WS_TIMER(x) (uint8_t)((x) + 1U)
120 static uint8_t FLEXIO_I2S_DRV_ComputeByteWidth(uint8_t bitsWidth)
128 else if (bitsWidth <= 16U)
155 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 1U;
157 if (tmpDiv < DIVIDER_MIN_VALUE)
159 tmpDiv = DIVIDER_MIN_VALUE;
161 if (tmpDiv > DIVIDER_MAX_VALUE)
163 tmpDiv = DIVIDER_MAX_VALUE;
166 *divider = (uint16_t)tmpDiv;
183 uint8_t resourceIndex;
186 resourceIndex = master->flexioCommon.resourceIndex;
189 FLEXIO_I2S_DRV_MasterComputeBaudRateDivider(master, userConfigPtr->
baudRate, ÷r, inputClock);
194 TX_SHIFTER(resourceIndex),
199 TX_SHIFTER(resourceIndex),
201 userConfigPtr->
txPin,
204 SCK_TIMER(resourceIndex),
209 RX_SHIFTER(resourceIndex),
214 RX_SHIFTER(resourceIndex),
216 userConfigPtr->
rxPin,
219 SCK_TIMER(resourceIndex),
225 SCK_TIMER(resourceIndex),
234 SCK_TIMER(resourceIndex),
235 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
247 WS_TIMER(resourceIndex),
256 WS_TIMER(resourceIndex),
260 userConfigPtr->
wsPin,
278 uint8_t resourceIndex;
281 resourceIndex = slave->flexioCommon.resourceIndex;
287 TX_SHIFTER(resourceIndex),
292 TX_SHIFTER(resourceIndex),
294 userConfigPtr->
txPin,
297 WS_TIMER(resourceIndex),
302 RX_SHIFTER(resourceIndex),
307 RX_SHIFTER(resourceIndex),
309 userConfigPtr->
rxPin,
312 WS_TIMER(resourceIndex),
318 SCK_TIMER(resourceIndex),
327 SCK_TIMER(resourceIndex),
328 (uint8_t)(userConfigPtr->
sckPin << 1U),
331 userConfigPtr->
wsPin,
339 WS_TIMER(resourceIndex),
348 WS_TIMER(resourceIndex),
349 (uint8_t)((SCK_TIMER(resourceIndex) << 2U) + 3U),
368 uint8_t resourceIndex;
371 resourceIndex = master->flexioCommon.resourceIndex;
374 switch (master->driverType)
379 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
382 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
400 master->driverIdle =
true;
401 master->txData = NULL;
402 master->rxData = NULL;
403 master->txRemainingBytes = 0U;
404 master->rxRemainingBytes = 0U;
407 if (master->blocking ==
true)
423 uint8_t resourceIndex;
425 resourceIndex = master->flexioCommon.resourceIndex;
452 uint8_t resourceIndex;
454 resourceIndex = master->flexioCommon.resourceIndex;
472 FLEXIO_I2S_DRV_MasterEndTransfer(master);
486 switch (master->driverType)
490 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
497 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
505 master->blocking =
false;
510 FLEXIO_I2S_DRV_MasterStopTransfer(master);
513 return master->status;
527 uint8_t resourceIndex;
530 resourceIndex = master->flexioCommon.resourceIndex;
535 if (master->rxRemainingBytes > 0U)
537 if (master->rxData != NULL)
539 switch (master->byteWidth)
542 *(uint8_t *)master->rxData = (uint8_t)data;
545 *(uint16_t *)master->rxData = (uint16_t)data;
548 *(uint32_t *)master->rxData = (uint32_t)data;
552 master->rxData = &master->rxData[master->byteWidth];
555 master->rxRemainingBytes -= (uint32_t)(master->byteWidth);
574 uint8_t resourceIndex;
577 resourceIndex = master->flexioCommon.resourceIndex;
579 if (master->txRemainingBytes == 0U)
586 switch (master->byteWidth)
589 data = (uint32_t)(*(
const uint8_t *)master->txData);
592 data = (uint32_t)(*(
const uint16_t *)master->txData);
595 data = (uint32_t)(*(
const uint32_t *)master->txData);
598 master->txData = &master->txData[master->byteWidth];
599 master->txRemainingBytes -= (uint32_t)(master->byteWidth);
603 data <<= 32U - (uint32_t)(master->bitsWidth);
616 static void FLEXIO_I2S_DRV_MasterCheckStatus(
void *stateStruct)
619 uint8_t resourceIndex;
626 resourceIndex = master->flexioCommon.resourceIndex;
629 if (master->txData != NULL)
638 if (master->rxData != NULL)
650 FLEXIO_I2S_DRV_ReadData(master);
651 if ((master->rxData != NULL) && (master->rxRemainingBytes == 0U))
654 if (master->callback != NULL)
661 if (master->txData != NULL)
665 FLEXIO_I2S_DRV_WriteData(master);
666 if (master->txRemainingBytes == 0U)
669 if (master->callback != NULL)
673 if (master->txRemainingBytes == 0U)
684 master->txData = NULL;
691 if (master->rxRemainingBytes == 0U)
699 FLEXIO_I2S_DRV_MasterStopTransfer(master);
701 if (master->callback != NULL)
715 static void FLEXIO_I2S_DRV_MasterEndDmaTxTransfer(
void *stateStruct,
edma_chn_status_t status)
727 if (master->callback != NULL)
731 if (master->txRemainingBytes == 0U)
734 master->txData = NULL;
740 dmaChn = master->txDMAChannel;
745 master->txRemainingBytes = 0U;
758 static void FLEXIO_I2S_DRV_MasterEndDmaRxTransfer(
void *stateStruct,
edma_chn_status_t status)
771 if ((master->rxData != NULL) && (master->callback != NULL))
775 if (master->rxRemainingBytes == 0U)
780 FLEXIO_I2S_DRV_MasterStopTransfer(master);
782 if (master->callback != NULL)
791 dmaChn = master->rxDMAChannel;
793 if (master->rxData != NULL)
795 addr = (uint32_t)(master->rxData);
800 addr = (uint32_t)(&(master->dummyDmaData));
805 master->rxRemainingBytes = 0U;
825 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
826 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter])) + (
sizeof(uint32_t) - master->byteWidth);
844 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
845 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter]));
858 uint8_t resourceIndex;
862 uint8_t requestMask = 0U;
869 resourceIndex = master->flexioCommon.resourceIndex;
872 if (master->txData != NULL)
877 (uint32_t)(master->txData),
878 FLEXIO_I2S_DRV_MasterComputeTxRegAddr(master),
879 dmaTransferSize[master->byteWidth - 1U],
884 master->txRemainingBytes = 0U;
892 requestMask = (uint8_t)(1U << TX_SHIFTER(resourceIndex));
895 if (master->rxData != NULL)
897 addr = (uint32_t)(master->rxData);
902 addr = (uint32_t)(&(master->dummyDmaData));
907 FLEXIO_I2S_DRV_MasterComputeRxRegAddr(master),
909 dmaTransferSize[master->byteWidth - 1U],
911 if (master->rxData == NULL)
919 master->rxRemainingBytes = 0U;
927 requestMask |= (uint8_t)(1U << RX_SHIFTER(resourceIndex));
968 master->flexioCommon.resourceCount = 2U;
983 master->driverType = userConfigPtr->
driverType;
984 master->bitsWidth = userConfigPtr->
bitsWidth;
985 master->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(userConfigPtr->
bitsWidth);
986 master->driverIdle =
true;
987 master->callback = userConfigPtr->
callback;
989 master->blocking =
false;
990 master->txData = NULL;
991 master->txRemainingBytes = 0U;
992 master->rxData = NULL;
993 master->rxRemainingBytes = 0U;
994 master->master =
true;
998 FLEXIO_I2S_DRV_MasterConfigure(master, userConfigPtr, inputClock);
1001 switch (master->driverType)
1004 master->flexioCommon.isr = FLEXIO_I2S_DRV_MasterCheckStatus;
1014 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(master->flexioCommon.resourceIndex)];
1015 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(master->flexioCommon.resourceIndex)];
1066 uint32_t inputClock;
1068 uint8_t resourceIndex;
1074 (bitsWidth != 8U) && (bitsWidth != 16U) && (bitsWidth != 32U)
1077 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1078 resourceIndex = master->flexioCommon.resourceIndex;
1088 FLEXIO_I2S_DRV_MasterComputeBaudRateDivider(master, baudRate, ÷r, inputClock);
1091 FLEXIO_HAL_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)(((((uint16_t)bitsWidth << 1U) - 1U) << 8U) + divider));
1095 master->bitsWidth = bitsWidth;
1096 master->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(bitsWidth);
1113 uint32_t inputClock;
1117 uint8_t resourceIndex;
1121 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1122 resourceIndex = master->flexioCommon.resourceIndex;
1131 divider = (uint16_t)(timerCmp & 0x00FFU);
1134 *baudRate = (inputClock + (uint32_t)divider + 1U) / (2U * ((uint32_t)divider + 1U));
1150 const uint8_t * txBuff,
1154 uint8_t resourceIndex;
1160 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1161 resourceIndex = master->flexioCommon.resourceIndex;
1166 master->txData = txBuff;
1167 master->txRemainingBytes = txSize;
1169 master->rxRemainingBytes = txSize;
1170 master->rxData = NULL;
1172 master->driverIdle =
false;
1177 FLEXIO_I2S_DRV_MasterEnableTransfer(master);
1179 switch (master->driverType)
1184 (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
1187 (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
1192 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1195 FLEXIO_I2S_DRV_MasterStartDmaTransfer(master);
1214 const uint8_t * txBuff,
1223 master->blocking =
true;
1230 master->blocking =
false;
1235 return FLEXIO_I2S_DRV_MasterWaitTransferEnd(master, timeout);
1251 uint8_t resourceIndex;
1257 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1258 resourceIndex = master->flexioCommon.resourceIndex;
1263 master->rxData = rxBuff;
1264 master->rxRemainingBytes = rxSize;
1265 master->txData = NULL;
1266 master->txRemainingBytes = 0U;
1268 master->driverIdle =
false;
1271 FLEXIO_I2S_DRV_MasterEnableTransfer(master);
1274 switch (master->driverType)
1279 (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
1282 (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
1287 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1290 FLEXIO_I2S_DRV_MasterStartDmaTransfer(master);
1322 master->blocking =
true;
1329 master->blocking =
false;
1334 return FLEXIO_I2S_DRV_MasterWaitTransferEnd(master, timeout);
1350 FLEXIO_I2S_DRV_MasterStopTransfer(master);
1370 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1373 if (bytesRemaining != NULL)
1377 *bytesRemaining = master->rxRemainingBytes;
1380 if (!master->driverIdle)
1386 return master->status;
1406 master->rxData = rxBuff;
1407 master->rxRemainingBytes = rxSize;
1421 const uint8_t * txBuff,
1428 master->txData = txBuff;
1429 master->txRemainingBytes = txSize;
1431 master->rxRemainingBytes += txSize;
1459 slave->flexioCommon.resourceCount = 2U;
1473 slave->driverType = userConfigPtr->
driverType;
1474 slave->bitsWidth = userConfigPtr->
bitsWidth;
1475 slave->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(userConfigPtr->
bitsWidth);
1476 slave->driverIdle =
true;
1477 slave->callback = userConfigPtr->
callback;
1479 slave->blocking =
false;
1480 slave->txData = NULL;
1481 slave->txRemainingBytes = 0U;
1482 slave->rxData = NULL;
1483 slave->rxRemainingBytes = 0U;
1484 slave->master =
false;
1488 FLEXIO_I2S_DRV_SlaveConfigure(slave, userConfigPtr);
1491 switch (slave->driverType)
1494 slave->flexioCommon.isr = FLEXIO_I2S_DRV_MasterCheckStatus;
1504 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(slave->flexioCommon.resourceIndex)];
1505 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(slave->flexioCommon.resourceIndex)];
1530 uint8_t resourceIndex;
1536 (bitsWidth != 8U) && (bitsWidth != 16U) && (bitsWidth != 32U)
1540 resourceIndex = slave->flexioCommon.resourceIndex;
1545 slave->bitsWidth = bitsWidth;
1546 slave->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(bitsWidth);
static void EDMA_HAL_TCDSetSrcAddr(DMA_Type *base, uint32_t channel, uint32_t address)
Configures the source address for the hardware TCD.
static void FLEXIO_HAL_SetShifterInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the shifter interrupts.
static void FLEXIO_HAL_SetShifterMode(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_mode_t mode)
Sets the mode of the specified shifter.
status_t FLEXIO_I2S_DRV_MasterReceiveDataBlocking(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking receive transaction on the I2S bus.
static uint16_t FLEXIO_HAL_GetTimerCompare(const FLEXIO_Type *baseAddr, uint8_t timer)
Returns the compare value of the specified timer.
DMAMUX_Type *const g_dmamuxBase[DMAMUX_INSTANCE_COUNT]
Array for DMAMUX module register base address.
status_t FLEXIO_I2S_DRV_MasterReceiveData(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking receive transaction on the I2S bus.
static void FLEXIO_HAL_SetTimerControl(FLEXIO_Type *baseAddr, uint8_t timer, uint8_t trigger, flexio_trigger_polarity_t triggerPolarity, flexio_trigger_source_t triggerSource, uint8_t pin, flexio_pin_polarity_t pinPolarity, flexio_pin_config_t pinConfig, flexio_timer_mode_t mode)
Sets all control settings for specified timer.
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
static void FLEXIO_HAL_SetTimerMode(FLEXIO_Type *baseAddr, uint8_t timer, flexio_timer_mode_t mode)
Sets the mode of the specified timer.
status_t FLEXIO_I2S_DRV_MasterSetTxBuffer(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
FLEXIO_Type *const g_flexioBase[FLEXIO_INSTANCE_COUNT]
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
#define FLEXIO_INSTANCE_COUNT
void EDMA_HAL_TCDSetMajorCount(DMA_Type *base, uint32_t channel, uint32_t count)
Sets the major iteration count according to minor loop channel link setting.
status_t FLEXIO_I2S_DRV_MasterSendData(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking send transaction on the I2S bus.
Master internal context structure.
static void FLEXIO_HAL_WriteShifterBuffer(FLEXIO_Type *baseAddr, uint8_t shifter, uint32_t value, flexio_shifter_buffer_mode_t mode)
Writes a value in the specified shifter buffer.
static void FLEXIO_HAL_SetShifterPinConfig(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_pin_config_t config)
Configures the pin assigned to the specified shifter.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
Slave configuration structure.
static void FLEXIO_HAL_SetShifterConfig(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_start_t start, flexio_shifter_stop_t stop, flexio_shifter_source_t source)
Sets all configuration settings for specified shifter.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
status_t FLEXIO_I2S_DRV_MasterDeinit(flexio_i2s_master_state_t *master)
De-initialize the FLEXIO_I2S master mode driver.
static uint32_t FLEXIO_HAL_ReadShifterBuffer(const FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_buffer_mode_t mode)
Reads the value from the specified shifter buffer.
status_t FLEXIO_I2S_DRV_SlaveInit(uint32_t instance, const flexio_i2s_slave_user_config_t *userConfigPtr, flexio_i2s_slave_state_t *slave)
Initialize the FLEXIO_I2S slave mode driver.
edma_chn_status_t
Channel status for eDMA channel.
static void EDMA_HAL_TCDSetDestAddr(DMA_Type *base, uint32_t channel, uint32_t address)
Configures the destination address for the TCD.
__IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT]
flexio_callback_t callback
static void FLEXIO_HAL_SetShifterControl(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_mode_t mode, uint8_t pin, flexio_pin_polarity_t pinPolarity, flexio_pin_config_t pinConfig, uint8_t timer, flexio_timer_polarity_t timerPolarity)
Sets all control settings for the specified shifter.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
status_t FLEXIO_I2S_DRV_MasterSendDataBlocking(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking send transaction on the I2S bus.
status_t FLEXIO_I2S_DRV_MasterSetConfig(flexio_i2s_master_state_t *master, uint32_t baudRate, uint8_t bitsWidth)
Set the baud rate and bit width for any subsequent I2S communication.
status_t FLEXIO_I2S_DRV_MasterGetStatus(flexio_i2s_master_state_t *master, uint32_t *bytesRemaining)
Get the status of the current non-blocking I2S master transaction.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
const uint8_t g_flexioDMASrc[FLEXIO_INSTANCE_COUNT][FEATURE_FLEXIO_MAX_SHIFTER_COUNT]
static void FLEXIO_HAL_SetTimerCompare(FLEXIO_Type *baseAddr, uint8_t timer, uint16_t value)
Configures the compare value for the specified timer.
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
flexio_driver_type_t driverType
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
static void FLEXIO_HAL_SetTimerConfig(FLEXIO_Type *baseAddr, uint8_t timer, flexio_timer_start_t start, flexio_timer_stop_t stop, flexio_timer_enable_t enable, flexio_timer_disable_t disable, flexio_timer_reset_t reset, flexio_timer_decrement_t decrement, flexio_timer_output_t output)
Sets all configuration settings for specified timer.
static void EDMA_HAL_TCDSetDisableDmaRequestAfterTCDDoneCmd(DMA_Type *base, uint32_t channel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
status_t FLEXIO_I2S_DRV_MasterInit(uint32_t instance, const flexio_i2s_master_user_config_t *userConfigPtr, flexio_i2s_master_state_t *master)
Initialize the FLEXIO_I2S master mode driver.
static void EDMA_HAL_TCDSetDestOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the destination address signed offset for the TCD.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
flexio_driver_type_t driverType
flexio_device_state_t * g_flexioDeviceStatePtr[FLEXIO_INSTANCE_COUNT]
DMA_Type *const g_edmaBase[DMA_INSTANCE_COUNT]
Array for the eDMA module register base address.
static bool FLEXIO_HAL_GetShifterStatus(const FLEXIO_Type *baseAddr, uint8_t shifter)
Returns the current status of the specified shifter.
static void FLEXIO_HAL_ClearShifterErrorStatus(FLEXIO_Type *baseAddr, uint8_t shifter)
Clears the error status of the specified shifter.
status_t FLEXIO_I2S_DRV_MasterSetRxBuffer(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
Master configuration structure.
static void DMAMUX_HAL_SetChannelSource(DMAMUX_Type *base, uint32_t channel, uint8_t source)
Configures the DMA request for the DMAMUX channel.
static void FLEXIO_HAL_SetShifterErrorInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the shifter error interrupts.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
static bool FLEXIO_HAL_GetShifterErrorStatus(const FLEXIO_Type *baseAddr, uint8_t shifter)
Returns the current error status of the specified shifter.
status_t FLEXIO_I2S_DRV_MasterGetBaudRate(flexio_i2s_master_state_t *master, uint32_t *baudRate)
Get the currently configured baud rate.
status_t FLEXIO_I2S_DRV_MasterTransferAbort(flexio_i2s_master_state_t *master)
Aborts a non-blocking I2S master transaction.
const clock_names_t g_flexioClock[FLEXIO_INSTANCE_COUNT]
status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t dataBufferSize)
Configures a simple single block data transfer with DMA.
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
static void FLEXIO_HAL_ClearShifterStatus(FLEXIO_Type *baseAddr, uint8_t shifter)
Clears the status of the specified shifter.
flexio_callback_t callback
static void FLEXIO_HAL_SetShifterDMARequest(FLEXIO_Type *baseAddr, uint8_t requestMask, bool enable)
Enables or disables the shifter DMA requests.
status_t FLEXIO_I2S_DRV_SlaveSetConfig(flexio_i2s_slave_state_t *slave, uint8_t bitsWidth)
Set the bit width for any subsequent I2S communication.