S32 SDK
lptmr_hal.h
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1 /*
2  * Copyright (c) 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #ifndef LPTMR_HAL_H
20 #define LPTMR_HAL_H
21 
36 #include <stdint.h>
37 #include <stdbool.h>
38 #include <stddef.h>
39 #include "device_registers.h"
40 
41 
47  /*******************************************************************************
48  * Definitions
49  ******************************************************************************/
53 typedef enum {
59 
63 typedef enum {
67 
71 typedef enum {
75 
79 typedef enum {
80  LPTMR_PRESCALE_2 = 0x00u,
97 
101 typedef enum {
107 /*******************************************************************************
108  * API
109  ******************************************************************************/
115 #if defined(__cplusplus)
116 extern "C" {
117 #endif
118 
128 void LPTMR_HAL_Init(LPTMR_Type* const base);
129 
130 
146 static inline bool LPTMR_HAL_GetDmaRequest(const LPTMR_Type* const base)
147 {
148  DEV_ASSERT(base != NULL);
149 
150  uint32_t tmp = base->CSR;
151 
152  tmp = (tmp & LPTMR_CSR_TDRE_MASK) >> LPTMR_CSR_TDRE_SHIFT;
153 
154  return ((tmp == 1u) ? true : false);
155 }
156 
157 
173 static inline void LPTMR_HAL_SetDmaRequest(LPTMR_Type* const base,
174  bool enable)
175 {
176  DEV_ASSERT(base != NULL);
177 
178  uint32_t tmp = base->CSR;
179  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
181  tmp |= LPTMR_CSR_TDRE(enable ? (uint32_t)1u : (uint32_t)0u);
182  base->CSR = tmp;
183 }
184 
185 
199 static inline bool LPTMR_HAL_GetCompareFlag(const LPTMR_Type* const base)
200 {
201  DEV_ASSERT(base != NULL);
202 
203  uint32_t tmp = base -> CSR;
204  tmp = (tmp & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT;
205 
206  return ((tmp == 1u) ? true : false);
207 }
208 
209 
219 static inline void LPTMR_HAL_ClearCompareFlag(LPTMR_Type* const base)
220 {
221  DEV_ASSERT(base != NULL);
222 
223  uint32_t tmp = base->CSR;
224  tmp |= (LPTMR_CSR_TCF_MASK);
225  base->CSR = tmp;
226 #ifdef ERRATA_E9005
227  /* Read-after-write sequence to guarantee required serialization of memory operations */
228  (void)base->CSR;
229 #endif
230 }
231 
232 
246 static inline bool LPTMR_HAL_GetInterruptEnable(const LPTMR_Type* const base)
247 {
248  DEV_ASSERT(base != NULL);
249 
250  uint32_t tmp = base->CSR;
251  tmp = (tmp & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT;
252 
253  return ((tmp == 1u) ? true : false);
254 }
255 
256 
270 static inline void LPTMR_HAL_SetInterrupt(LPTMR_Type* const base,
271  bool enable)
272 {
273  DEV_ASSERT(base != NULL);
274 
275  uint32_t tmp = base->CSR;
276  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
278  tmp |= LPTMR_CSR_TIE(enable ? (uint32_t)1u : (uint32_t)0u);
279  base->CSR = tmp;
280 }
281 
282 
297 static inline lptmr_pinselect_t LPTMR_HAL_GetPinSelect(const LPTMR_Type* const base)
298 {
299  DEV_ASSERT(base != NULL);
300 
301  uint32_t tmp = base->CSR;
302  tmp = (tmp & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT;
303  return (lptmr_pinselect_t)(tmp);
304 }
305 
306 
322 static inline void LPTMR_HAL_SetPinSelect(LPTMR_Type* const base,
323  const lptmr_pinselect_t pinsel)
324 {
325  DEV_ASSERT(base != NULL);
326 
327  uint32_t tmp = base->CSR;
328  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
330  tmp |= LPTMR_CSR_TPS(pinsel);
331  base->CSR = tmp;
332 }
333 
334 
349 {
350  DEV_ASSERT(base != NULL);
351 
352  uint32_t tmp = base->CSR;
353  tmp = (tmp & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT;
354 
356 }
357 
358 
372 static inline void LPTMR_HAL_SetPinPolarity(LPTMR_Type* const base,
373  const lptmr_pinpolarity_t pol)
374 {
375  DEV_ASSERT(base != NULL);
376 
377  uint32_t tmp = base->CSR;
378  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
380  tmp |= LPTMR_CSR_TPP(pol);
381  base->CSR = tmp;
382 }
383 
384 
398 static inline bool LPTMR_HAL_GetFreeRunning(const LPTMR_Type* const base)
399 {
400  DEV_ASSERT(base != NULL);
401 
402  uint32_t tmp = base->CSR;
403  tmp = (tmp & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT;
404 
405  return ((tmp == 1u) ? true : false);
406 }
407 
408 
422 static inline void LPTMR_HAL_SetFreeRunning(LPTMR_Type* const base,
423  const bool enable)
424 {
425  DEV_ASSERT(base != NULL);
426 
427  uint32_t tmp = base->CSR;
428  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
430  tmp |= LPTMR_CSR_TFC(enable ? (uint32_t)1u : (uint32_t)0u);
431  base->CSR = tmp;
432 }
433 
434 
448 static inline lptmr_workmode_t LPTMR_HAL_GetWorkMode(const LPTMR_Type* const base)
449 {
450  DEV_ASSERT(base != NULL);
451 
452  uint32_t tmp = base->CSR;
453  tmp = (tmp & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT;
454 
456 }
457 
458 
472 static inline void LPTMR_HAL_SetWorkMode(LPTMR_Type* const base,
473  const lptmr_workmode_t mode)
474 {
475  DEV_ASSERT(base != NULL);
476 
477  uint32_t tmp = base->CSR;
478  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
480  tmp |= LPTMR_CSR_TMS(mode);
481  base->CSR = tmp;
482 }
483 
484 
497 static inline bool LPTMR_HAL_GetEnable(const LPTMR_Type* const base)
498 {
499  DEV_ASSERT(base != NULL);
500 
501  uint32_t tmp = base->CSR;
502  tmp = (tmp & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT;
503 
504  return ((tmp == 1u) ? true : false);
505 }
506 
507 
518 static inline void LPTMR_HAL_Enable(LPTMR_Type* const base)
519 {
520  DEV_ASSERT(base != NULL);
521 
522  uint32_t tmp = base->CSR;
523  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
525  tmp |= LPTMR_CSR_TEN(1u);
526  base->CSR = tmp;
527 }
528 
529 
539 static inline void LPTMR_HAL_Disable(LPTMR_Type* const base)
540 {
541  DEV_ASSERT(base != NULL);
542 
543  uint32_t tmp = base->CSR;
544  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
546  tmp |= LPTMR_CSR_TEN(0u);
547  base->CSR = tmp;
548 }
549 
550 
578 static inline lptmr_prescaler_t LPTMR_HAL_GetPrescaler(const LPTMR_Type* const base)
579 {
580  DEV_ASSERT(base != NULL);
581 
582  uint32_t tmp = base->PSR;
584  return (lptmr_prescaler_t)(tmp);
585 }
586 
587 
615 static inline void LPTMR_HAL_SetPrescaler(LPTMR_Type* const base,
616  const lptmr_prescaler_t presc)
617 {
618  DEV_ASSERT(base != NULL);
619 
620  uint32_t tmp = base->PSR;
621  tmp &= ~(LPTMR_PSR_PRESCALE_MASK);
622  tmp |= LPTMR_PSR_PRESCALE(presc);
623  base->PSR = tmp;
624 }
625 
626 
639 static inline bool LPTMR_HAL_GetBypass(const LPTMR_Type* const base)
640 {
641  DEV_ASSERT(base != NULL);
642 
643  uint32_t tmp = base->PSR;
644  tmp = (tmp & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT;
645 
646  return ((tmp == 1u) ? true : false);
647 }
648 
649 
663 static inline void LPTMR_HAL_SetBypass(LPTMR_Type* const base,
664  const bool enable)
665 {
666  DEV_ASSERT(base != NULL);
667 
668  uint32_t tmp = base->PSR;
669  tmp &= ~(LPTMR_PSR_PBYP_MASK);
670  tmp |= LPTMR_PSR_PBYP(enable ? (uint32_t)1u : (uint32_t)0u);
671  base->PSR = tmp;
672 }
673 
689 {
690  DEV_ASSERT(base != NULL);
691 
692  uint32_t tmp = base->PSR;
693  tmp = (tmp & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT;
694  return (lptmr_clocksource_t)(tmp);
695 }
696 
697 
713 static inline void LPTMR_HAL_SetClockSelect(LPTMR_Type* const base,
714  const lptmr_clocksource_t clocksel)
715 {
716  DEV_ASSERT(base != NULL);
717 
718  uint32_t tmp = base->PSR;
719  tmp &= ~(LPTMR_PSR_PCS_MASK);
720  tmp |= LPTMR_PSR_PCS(clocksel);
721  base->PSR = tmp;
722 }
723 
724 
735 static inline uint16_t LPTMR_HAL_GetCompareValue(const LPTMR_Type* const base)
736 {
737  DEV_ASSERT(base != NULL);
738 
739  uint32_t tmp = base->CMR;
741  return (uint16_t)(tmp);
742 }
743 
744 
757 static inline void LPTMR_HAL_SetCompareValue(LPTMR_Type* const base,
758  const uint16_t compval)
759 {
760  DEV_ASSERT(base != NULL);
761 
762  uint32_t tmp = base->CMR;
763  tmp &= ~(LPTMR_CMR_COMPARE_MASK);
764  tmp |= LPTMR_CMR_COMPARE(compval);
765  base->CMR = tmp;
766 }
767 
768 
779 static inline uint16_t LPTMR_HAL_GetCounterValue(LPTMR_Type* const base)
780 {
781  DEV_ASSERT(base != NULL);
782 
783  /* Write dummy value before reading register */
784  base->CNR = LPTMR_CNR_COUNTER(0u);
785  uint16_t cnr = (uint16_t)base->CNR;
786  return cnr;
787 }
788 
789 
791 #if defined(__cplusplus)
792 }
793 #endif
794 
797 #endif /* LPTMR_HAL_H */
798 /*******************************************************************************
799  * EOF
800  ******************************************************************************/
#define LPTMR_CSR_TFC_MASK
Definition: S32K144.h:6596
void LPTMR_HAL_Init(LPTMR_Type *const base)
Initialize the LPTMR instance to reset values.
Definition: lptmr_hal.c:43
#define LPTMR_PSR_PRESCALE(x)
Definition: S32K144.h:6632
lptmr_pinselect_t
Pulse Counter Input selection Implements : lptmr_pinselect_t_Class.
Definition: lptmr_hal.h:53
#define LPTMR_PSR_PCS_MASK
Definition: S32K144.h:6621
#define LPTMR_CMR_COMPARE(x)
Definition: S32K144.h:6637
#define LPTMR_PSR_PRESCALE_SHIFT
Definition: S32K144.h:6630
#define LPTMR_CSR_TMS(x)
Definition: S32K144.h:6595
static void LPTMR_HAL_SetPinSelect(LPTMR_Type *const base, const lptmr_pinselect_t pinsel)
Configure the Pin selection for Pulse Counter Mode.
Definition: lptmr_hal.h:322
#define LPTMR_CMR_COMPARE_SHIFT
Definition: S32K144.h:6635
static lptmr_pinselect_t LPTMR_HAL_GetPinSelect(const LPTMR_Type *const base)
Get the Pin select for Counter Mode.
Definition: lptmr_hal.h:297
#define LPTMR_CSR_TMS_SHIFT
Definition: S32K144.h:6593
#define LPTMR_CSR_TCF_SHIFT
Definition: S32K144.h:6613
static lptmr_prescaler_t LPTMR_HAL_GetPrescaler(const LPTMR_Type *const base)
Get Prescaler/Glitch Filter divider value.
Definition: lptmr_hal.h:578
#define LPTMR_CSR_TDRE_SHIFT
Definition: S32K144.h:6617
#define LPTMR_CSR_TPS_SHIFT
Definition: S32K144.h:6605
#define LPTMR_CMR_COMPARE_MASK
Definition: S32K144.h:6634
static bool LPTMR_HAL_GetEnable(const LPTMR_Type *const base)
Get the Enable state.
Definition: lptmr_hal.h:497
static lptmr_pinpolarity_t LPTMR_HAL_GetPinPolarity(const LPTMR_Type *const base)
Get Pin Polarity for Pulse Counter Mode.
Definition: lptmr_hal.h:348
lptmr_clocksource_t
Clock Source selection Implements : lptmr_clocksource_t_Class.
Definition: lptmr_hal.h:101
__IO uint32_t CSR
Definition: S32K144.h:6552
static void LPTMR_HAL_SetBypass(LPTMR_Type *const base, const bool enable)
Configure the Prescaler/Glitch Filter Bypass enable state.
Definition: lptmr_hal.h:663
#define LPTMR_PSR_PCS(x)
Definition: S32K144.h:6624
#define LPTMR_PSR_PRESCALE_MASK
Definition: S32K144.h:6629
#define DEV_ASSERT(x)
Definition: devassert.h:78
#define LPTMR_CSR_TFC_SHIFT
Definition: S32K144.h:6597
#define LPTMR_PSR_PBYP_SHIFT
Definition: S32K144.h:6626
static void LPTMR_HAL_SetPinPolarity(LPTMR_Type *const base, const lptmr_pinpolarity_t pol)
Configure Pin Polarity for Pulse Counter Mode.
Definition: lptmr_hal.h:372
static void LPTMR_HAL_ClearCompareFlag(LPTMR_Type *const base)
Clear the Compare Flag.
Definition: lptmr_hal.h:219
__IO uint32_t CNR
Definition: S32K144.h:6555
lptmr_pinpolarity_t
Pulse Counter input polarity Implements : lptmr_pinpolarity_t_Class.
Definition: lptmr_hal.h:63
static bool LPTMR_HAL_GetDmaRequest(const LPTMR_Type *const base)
Get the DMA Request Enable Flag.
Definition: lptmr_hal.h:146
#define LPTMR_CSR_TDRE_MASK
Definition: S32K144.h:6616
static void LPTMR_HAL_SetWorkMode(LPTMR_Type *const base, const lptmr_workmode_t mode)
Configure the Work Mode.
Definition: lptmr_hal.h:472
#define LPTMR_CSR_TPP(x)
Definition: S32K144.h:6603
static void LPTMR_HAL_SetDmaRequest(LPTMR_Type *const base, bool enable)
Configure the DMA Request Enable Flag state.
Definition: lptmr_hal.h:173
#define LPTMR_CSR_TIE(x)
Definition: S32K144.h:6611
__IO uint32_t PSR
Definition: S32K144.h:6553
static uint16_t LPTMR_HAL_GetCounterValue(LPTMR_Type *const base)
Get the current Counter Value.
Definition: lptmr_hal.h:779
#define LPTMR_CSR_TMS_MASK
Definition: S32K144.h:6592
static void LPTMR_HAL_Disable(LPTMR_Type *const base)
Disable the LPTMR.
Definition: lptmr_hal.h:539
static void LPTMR_HAL_Enable(LPTMR_Type *const base)
Enable the LPTMR.
Definition: lptmr_hal.h:518
#define LPTMR_CSR_TIE_MASK
Definition: S32K144.h:6608
lptmr_workmode_t
Work Mode Implements : lptmr_workmode_t_Class.
Definition: lptmr_hal.h:71
#define LPTMR_PSR_PBYP(x)
Definition: S32K144.h:6628
#define LPTMR_CSR_TPS(x)
Definition: S32K144.h:6607
__IO uint32_t CMR
Definition: S32K144.h:6554
static void LPTMR_HAL_SetCompareValue(LPTMR_Type *const base, const uint16_t compval)
Configure the Compare Value.
Definition: lptmr_hal.h:757
static void LPTMR_HAL_SetFreeRunning(LPTMR_Type *const base, const bool enable)
Configure the Free Running state.
Definition: lptmr_hal.h:422
static bool LPTMR_HAL_GetBypass(const LPTMR_Type *const base)
Get the Prescaler/Glitch Filter Bypass enable state.
Definition: lptmr_hal.h:639
#define LPTMR_CSR_TEN(x)
Definition: S32K144.h:6591
static void LPTMR_HAL_SetClockSelect(LPTMR_Type *const base, const lptmr_clocksource_t clocksel)
Configure the LPTMR input Clock selection.
Definition: lptmr_hal.h:713
static bool LPTMR_HAL_GetCompareFlag(const LPTMR_Type *const base)
Get the Compare Flag state.
Definition: lptmr_hal.h:199
static lptmr_clocksource_t LPTMR_HAL_GetClockSelect(const LPTMR_Type *const base)
Get the LPTMR input Clock selection.
Definition: lptmr_hal.h:688
static void LPTMR_HAL_SetPrescaler(LPTMR_Type *const base, const lptmr_prescaler_t presc)
Configure the Prescaler/Glitch Filter divider value.
Definition: lptmr_hal.h:615
#define LPTMR_CSR_TPP_MASK
Definition: S32K144.h:6600
#define LPTMR_CSR_TIE_SHIFT
Definition: S32K144.h:6609
#define LPTMR_CSR_TCF_MASK
Definition: S32K144.h:6612
lptmr_prescaler_t
Prescaler Selection Implements : lptmr_prescaler_t_Class.
Definition: lptmr_hal.h:79
#define LPTMR_CNR_COUNTER(x)
Definition: S32K144.h:6642
#define LPTMR_CSR_TDRE(x)
Definition: S32K144.h:6619
#define LPTMR_CSR_TEN_MASK
Definition: S32K144.h:6588
static bool LPTMR_HAL_GetFreeRunning(const LPTMR_Type *const base)
Get the Free Running state.
Definition: lptmr_hal.h:398
static void LPTMR_HAL_SetInterrupt(LPTMR_Type *const base, bool enable)
Configure the Interrupt Enable state.
Definition: lptmr_hal.h:270
#define LPTMR_PSR_PCS_SHIFT
Definition: S32K144.h:6622
#define LPTMR_CSR_TFC(x)
Definition: S32K144.h:6599
#define LPTMR_CSR_TEN_SHIFT
Definition: S32K144.h:6589
#define LPTMR_PSR_PBYP_MASK
Definition: S32K144.h:6625
#define LPTMR_CSR_TPP_SHIFT
Definition: S32K144.h:6601
static uint16_t LPTMR_HAL_GetCompareValue(const LPTMR_Type *const base)
Get the Compare Value.
Definition: lptmr_hal.h:735
#define LPTMR_CSR_TPS_MASK
Definition: S32K144.h:6604
static lptmr_workmode_t LPTMR_HAL_GetWorkMode(const LPTMR_Type *const base)
Get current Work Mode.
Definition: lptmr_hal.h:448
static bool LPTMR_HAL_GetInterruptEnable(const LPTMR_Type *const base)
Get the Interrupt Enable state.
Definition: lptmr_hal.h:246