S32 SDK
flexcan_hal.c
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1 /*
2  * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
82 #include "flexcan_hal.h"
83 
84 
85 /*******************************************************************************
86  * Variables
87  ******************************************************************************/
88 
89 /*******************************************************************************
90  * Definitions
91  ******************************************************************************/
92 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT (31U)
94 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT (30U)
96 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT (15U)
98 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT (14U)
100 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK (0x3FFFFFFFU)
102 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT (1U)
104 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK (0x3FF80000U)
106 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT (19U)
108 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK (0x3FFFU)
110 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1 (16U)
112 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2 (0U)
114 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK (0x7FFU)
116 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1 (19U)
118 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2 (3U)
120 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK (0xFFU)
122 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1 (24U)
124 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2 (16U)
126 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3 (8U)
128 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4 (0U)
130 #define FLEXCAN_ALL_INT (0x0007U)
133 /* CAN FD extended data length DLC encoding */
134 #define CAN_DLC_VALUE_12_BYTES 9U
135 #define CAN_DLC_VALUE_16_BYTES 10U
136 #define CAN_DLC_VALUE_20_BYTES 11U
137 #define CAN_DLC_VALUE_24_BYTES 12U
138 #define CAN_DLC_VALUE_32_BYTES 13U
139 #define CAN_DLC_VALUE_48_BYTES 14U
140 #define CAN_DLC_VALUE_64_BYTES 15U
141 
142 #define RxFifoFilterTableOffset 0x18U
143 
144 #define FlexCanRxFifoAcceptRemoteFrame 1UL
145 #define FlexCanRxFifoAcceptExtFrame 1UL
146 
147 #define FLEXCAN_8_BYTE_PAYLOAD_MB_SIZE 16U
148 #define FLEXCAN_ARBITRATION_FIELD_SIZE 8U
149 
150 /*******************************************************************************
151  * Private Functions
152  ******************************************************************************/
153 
154 static volatile uint32_t* FLEXCAN_HAL_GetMsgBuffRegion(CAN_Type * base, uint32_t msgBuffIdx);
155 static uint8_t FLEXCAN_HAL_ComputeDLCValue(uint8_t payloadSize);
156 static uint8_t FLEXCAN_HAL_ComputePayloadSize(uint8_t dlcValue);
157 static uint32_t FLEXCAN_HAL_MaxMbRAMSize(const CAN_Type * base);
158 static void FLEXCAN_HAL_ClearRAM(CAN_Type * base);
159 
160 static inline uint32_t RxFifoOcuppiedLastMsgBuff(uint32_t x)
161 {
162  return (5U + ((((x) + 1U) * 8U) / 4U));
163 }
164 
165 /* Converts the index in an array of bytes to an index in an array of bytes with
166  * reversed endianness. */
167 #define FlexcanSwapBytesInWordIndex(index) (((index) & ~3U) + (3U - ((index) & 3U)))
168 
169 /* Determines the RxFIFO Filter element number */
170 #define RxFifoFilterElementNum(x) (((x) + 1U) * 8U)
171 
172 
173 
174 /*FUNCTION**********************************************************************
175  *
176  * Function Name : FLEXCAN_HAL_GetMsgBuffRegion
177  * Description : Returns the start of a MB area, based on its index.
178  *
179  *END**************************************************************************/
180 static volatile uint32_t* FLEXCAN_HAL_GetMsgBuffRegion(
181  CAN_Type * base,
182  uint32_t msgBuffIdx)
183 {
184  uint8_t payload_size = FLEXCAN_HAL_GetPayloadSize(base);
185  uint8_t arbitration_field_size = 8U;
186 
187  uint8_t mb_size = (uint8_t)(payload_size + arbitration_field_size);
188  /* Multiply the MB index by the MB size (in words) */
189  uint32_t mb_index = msgBuffIdx * ((uint32_t)mb_size >> 2U);
190 
191  return &(base->RAMn[mb_index]);
192 }
193 
194 /*FUNCTION**********************************************************************
195  *
196  * Function Name: FLEXCAN_HAL_ComputeDLCValue
197  * Description : Computes the DLC field value, given a payload size (in bytes).
198  *
199  *END**************************************************************************/
201  uint8_t payloadSize)
202 {
203  uint8_t ret;
204 
205  if (payloadSize <= 8U)
206  {
207  ret = payloadSize;
208  }
209  else if ((payloadSize > 8U) && (payloadSize <= 12U))
210  {
212  }
213  else if ((payloadSize > 12U) && (payloadSize <= 16U))
214  {
216  }
217  else if ((payloadSize > 16U) && (payloadSize <= 20U))
218  {
220  }
221  else if ((payloadSize > 20U) && (payloadSize <= 24U))
222  {
224  }
225  else if ((payloadSize > 24U) && (payloadSize <= 32U))
226  {
228  }
229  else if ((payloadSize > 32U) && (payloadSize <= 48U))
230  {
232  }
233  else if ((payloadSize > 48U) && (payloadSize <= 64U))
234  {
236  }
237  else
238  {
239  /* The argument is not a valid payload size */
240  ret = 0xFFU;
241  }
242 
243  return ret;
244 }
245 
246 /*FUNCTION**********************************************************************
247  *
248  * Function Name : FLEXCAN_HAL_ComputePayloadSize
249  * Description : Computes the maximum payload size (in bytes), given a DLC
250  * field value.
251  *
252  *END**************************************************************************/
254  uint8_t dlcValue)
255 {
256  uint8_t ret;
257 
258  if (dlcValue <= 8U)
259  {
260  ret = dlcValue;
261  }
262  else
263  {
264  switch (dlcValue) {
266  ret = 12U;
267  break;
269  ret = 16U;
270  break;
272  ret = 20U;
273  break;
275  ret = 24U;
276  break;
278  ret = 32U;
279  break;
281  ret = 48U;
282  break;
284  ret = 64U;
285  break;
286  default:
287  /* The argument is not a valid DLC size */
288  ret = 0xFFU;
289  break;
290  }
291  }
292 
293  return ret;
294 }
295 
296 /*FUNCTION**********************************************************************
297  *
298  * Function Name : FLEXCAN_HAL_MaxMbRAMSize
299  * Description : Computes the maximum RAM size occupied by MBs.
300  *
301  *END**************************************************************************/
302 static uint32_t FLEXCAN_HAL_MaxMbRAMSize(const CAN_Type * base)
303 {
304  uint32_t ret = 0;
305 
306  if (base == CAN0)
307  {
309  }
310 
311 #if (CAN_INSTANCE_COUNT > 1U)
312  if (base == CAN1)
313  {
315  }
316 #endif
317 
318 #if (CAN_INSTANCE_COUNT > 2U)
319  if (base == CAN2)
320  {
322  }
323 #endif
324 
325  return ret;
326 }
327 
328 /*FUNCTION**********************************************************************
329  *
330  * Function Name : FLEXCAN_HAL_ClearRAM
331  * Description : Clears FlexCAN memory positions that require initialization.
332  *
333  *END**************************************************************************/
334 static void FLEXCAN_HAL_ClearRAM(CAN_Type * base)
335 {
336  uint32_t databyte;
337  uint32_t RAM_size = FLEXCAN_HAL_MaxMbRAMSize(base) / 4U;
338  volatile uint32_t *RAM = base->RAMn;
339 
340  /* Clear MB region */
341  for (databyte = 0; databyte < RAM_size; databyte++) {
342  RAM[databyte] = 0;
343  }
344 
345  RAM = base->RXIMR;
346 
348 
349  /* Clear RXIMR region */
350  for (databyte = 0; databyte < CAN_RXIMR_COUNT; databyte++) {
351  RAM[databyte] = 0;
352  }
353 
354 #if defined(CPU_S32V234)
355 
356  /* Set WRMFRZ bit in CTRL2 Register to grant write access to memory */
357  base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_WRMFRZ_MASK) | CAN_CTRL2_WRMFRZ(1U);
358 
359  RAM = base->RAMn;
360 
361  /* Clear SMB FD region */
362  for (databyte = FEATURE_CAN_SMB_FD_START_ADDRESS_OFFSET; databyte < FEATURE_CAN_SMB_FD_END_ADDRESS_OFFSET; databyte++) {
363  RAM[databyte] = 0;
364  }
365 
366  /* Clear WRMFRZ bit in CTRL2 Register to restrict write access to memory */
367  base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_WRMFRZ_MASK) | CAN_CTRL2_WRMFRZ(0U);
368 
369 #endif
370 
372 }
373 
374 /*******************************************************************************
375  * Code
376  ******************************************************************************/
377 
378 /*FUNCTION**********************************************************************
379  *
380  * Function Name : FLEXCAN_HAL_Enable
381  * Description : Enable FlexCAN module.
382  * This function will enable FlexCAN module.
383  *
384  * Implements : FLEXCAN_HAL_Enable_Activity
385  *END**************************************************************************/
387 {
388  /* Check for low power mode */
389  if(((base->MCR & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT) == 1U)
390  {
391  /* Enable clock */
392  base->MCR = (base->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U);
393  base->MCR = (base->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U);
394  base->MCR = (base->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U);
395  /* Wait until enabled */
396  while (((base->MCR & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT) != 0U) {}
397  }
398 }
399 
400 /*FUNCTION**********************************************************************
401  *
402  * Function Name : FLEXCAN_HAL_Disable
403  * Description : Disable FlexCAN module.
404  * This function will disable FlexCAN module.
405  *
406  * Implements : FLEXCAN_HAL_Disable_Activity
407  *END**************************************************************************/
409 {
410  /* To access the memory mapped registers */
411  /* Entre disable mode (hard reset). */
412  if(((base->MCR & CAN_MCR_MDIS_MASK) >> CAN_MCR_MDIS_SHIFT) == 0U)
413  {
414  /* Clock disable (module) */
415  base->MCR = (base->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U);
416 
417  /* Wait until disable mode acknowledged */
418  while (((base->MCR & CAN_MCR_LPMACK_MASK) >> CAN_MCR_LPMACK_SHIFT) == 0U) {}
419  }
420 }
421 
422 #if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
423 /*FUNCTION**********************************************************************
424  *
425  * Function Name : FLEXCAN_HAL_SelectClock
426  * Description : Select FlexCAN clock source.
427  * This function will select either internal sys clock or external clock as
428  * FlexCAN clock source.
429  *
430  * Implements : FLEXCAN_HAL_SelectClock_Activity
431  *END**************************************************************************/
433  CAN_Type * base,
435 {
436  base->CTRL1 = (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) | CAN_CTRL1_CLKSRC(clk);
437 }
438 #endif
439 
440 /*FUNCTION**********************************************************************
441  *
442  * Function Name : FLEXCAN_HAL_Init
443  * Description : Initialize FlexCAN module.
444  * This function will reset FlexCAN module, set maximum number of message
445  * buffers, initialize all message buffers as inactive, enable RX FIFO
446  * if needed, mask all mask bits, and disable all MB interrupts.
447  *
448  * Implements : FLEXCAN_HAL_Init_Activity
449  *END**************************************************************************/
451 {
452  /* Reset the FLEXCAN */
453  base->MCR = (base->MCR & ~CAN_MCR_SOFTRST_MASK) | CAN_MCR_SOFTRST(1U);
454 
455  /* Wait for reset cycle to complete */
456  while (((base->MCR & CAN_MCR_SOFTRST_MASK) >> CAN_MCR_SOFTRST_SHIFT) != 0U) {}
457 
458  /* Clear FlexCAN memory */
459  FLEXCAN_HAL_ClearRAM(base);
460 
461  /* Set Freeze, Halt*/
463 
464  /* Rx global mask*/
465  (base->RXMGMASK) = (((uint32_t)(((uint32_t)(CAN_RXMGMASK_MG_MASK)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
466 
467  /* Rx reg 14 mask*/
468  (base->RX14MASK) = (((uint32_t)(((uint32_t)(CAN_RX14MASK_RX14M_MASK)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
469 
470  /* Rx reg 15 mask*/
471  (base->RX15MASK) = (((uint32_t)(((uint32_t)(CAN_RX15MASK_RX15M_MASK)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
472 
473  /* De-assert Freeze Mode*/
475 
476  /* Disable all MB interrupts*/
477  (base->IMASK1) = 0x0;
478 }
479 
480 /*FUNCTION**********************************************************************
481  *
482  * Function Name : FLEXCAN_HAL_SetTimeSegments
483  * Description : Set FlexCAN time segments.
484  * This function will set all FlexCAN time segments which define the length of
485  * Propagation Segment in the bit time, the length of Phase Buffer Segment 2 in
486  * the bit time, the length of Phase Buffer Segment 1 in the bit time, the ratio
487  * between the PE clock frequency and the Serial Clock (Sclock) frequency, and
488  * the maximum number of time quanta that a bit time can be changed by one
489  * resynchronization. (One time quantum is equal to the Sclock period.)
490  *
491  * Implements : FLEXCAN_HAL_SetTimeSegments_Activity
492  *END**************************************************************************/
494  CAN_Type * base,
495  const flexcan_time_segment_t *timeSeg)
496 {
497  DEV_ASSERT(timeSeg != NULL);
498 
499  /* Set Freeze mode*/
501 
502  /* Set FlexCAN time segments*/
503  if ((base->CBT & CAN_CBT_BTF_MASK) != 0U)
504  {
505  /* If extended bit time definitions are enabled, use CBT register */
506  (base->CBT) = ((base->CBT) & ~((CAN_CBT_EPROPSEG_MASK | CAN_CBT_EPSEG2_MASK |
509 
510  (base->CBT) = ((base->CBT) | (CAN_CBT_EPROPSEG(timeSeg->propSeg) |
511  CAN_CBT_EPSEG2(timeSeg->phaseSeg2) |
512  CAN_CBT_EPSEG1(timeSeg->phaseSeg1) |
513  CAN_CBT_EPRESDIV(timeSeg->preDivider) |
514  CAN_CBT_ERJW(timeSeg->rJumpwidth)));
515  }
516  else
517  {
518  /* If extended bit time definitions are disabled, use CTRL1 register */
519  (base->CTRL1) = ((base->CTRL1) & ~((CAN_CTRL1_PROPSEG_MASK | CAN_CTRL1_PSEG2_MASK |
522 
523  (base->CTRL1) = ((base->CTRL1) | (CAN_CTRL1_PROPSEG(timeSeg->propSeg) |
524  CAN_CTRL1_PSEG2(timeSeg->phaseSeg2) |
525  CAN_CTRL1_PSEG1(timeSeg->phaseSeg1) |
526  CAN_CTRL1_PRESDIV(timeSeg->preDivider) |
527  CAN_CTRL1_RJW(timeSeg->rJumpwidth)));
528  }
529 
530  /* De-assert Freeze mode*/
532 }
533 
534 /*FUNCTION**********************************************************************
535  *
536  * Function Name : FLEXCAN_HAL_SetTimeSegmentsCbt
537  * Description : Set FlexCAN time segments for the data phase of FD frames.
538  * This function will set all FlexCAN time segments which define the length of
539  * Propagation Segment in the bit time, the length of Phase Buffer Segment 2 in
540  * the bit time, the length of Phase Buffer Segment 1 in the bit time, the ratio
541  * between the PE clock frequency and the Serial Clock (Sclock) frequency, and
542  * the maximum number of time quanta that a bit time can be changed by one
543  * resynchronization. (One time quantum is equal to the Sclock period.)
544  *
545  * Implements : FLEXCAN_HAL_SetTimeSegmentsCbt_Activity
546  *END**************************************************************************/
548  CAN_Type * base,
549  const flexcan_time_segment_t *timeSeg)
550 {
551  DEV_ASSERT(timeSeg != NULL);
552 
553  /* Set Freeze mode*/
555  /* Set FlexCAN time segments*/
556  (base->FDCBT) = ((base->FDCBT) & ~((CAN_FDCBT_FPROPSEG_MASK | CAN_FDCBT_FPSEG2_MASK |
559 
560  (base->FDCBT) = ((base->FDCBT) | (CAN_FDCBT_FPROPSEG(timeSeg->propSeg) |
561  CAN_FDCBT_FPSEG2(timeSeg->phaseSeg2) |
562  CAN_FDCBT_FPSEG1(timeSeg->phaseSeg1) |
563  CAN_FDCBT_FPRESDIV(timeSeg->preDivider) |
564  CAN_FDCBT_FRJW(timeSeg->rJumpwidth)));
565 
566  /* De-assert Freeze mode*/
568 }
569 
570 /*FUNCTION**********************************************************************
571  *
572  * Function Name : FLEXCAN_HAL_GetTimeSegments
573  * Description : Get FlexCAN time segments.
574  * This function will get all FlexCAN time segments defined.
575  *
576  * Implements : FLEXCAN_HAL_GetTimeSegments_Activity
577  *END**************************************************************************/
579  const CAN_Type * base,
580  flexcan_time_segment_t *timeSeg)
581 {
582  DEV_ASSERT(timeSeg != NULL);
583 
586  timeSeg->phaseSeg1 = ((base->CTRL1) & CAN_CTRL1_PSEG1_MASK) >> CAN_CTRL1_PSEG1_SHIFT;
587  timeSeg->phaseSeg2 = ((base->CTRL1) & CAN_CTRL1_PSEG2_MASK) >> CAN_CTRL1_PSEG2_SHIFT;
588  timeSeg->rJumpwidth = ((base->CTRL1) & CAN_CTRL1_RJW_MASK) >> CAN_CTRL1_RJW_SHIFT;
589 }
590 
591 /*FUNCTION**********************************************************************
592  *
593  * Function Name : FLEXCAN_HAL_SetTxMsgBuff
594  * Description : Configure a message buffer for transmission.
595  * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
596  * the function will make sure if the MB requested is not occupied by RX FIFO
597  * and ID filter table. Then this function will copy user's buffer into the
598  * message buffer data area and configure the message buffer as required for
599  * transmission.
600  *
601  * Implements : FLEXCAN_HAL_SetTxMsgBuff_Activity
602  *END**************************************************************************/
604  CAN_Type * base,
605  uint32_t msgBuffIdx,
607  uint32_t msgId,
608  const uint8_t *msgData)
609 {
610  DEV_ASSERT(cs != NULL);
611 
612  uint32_t val1, val2 = 1;
613  uint32_t flexcan_mb_config = 0;
614  uint32_t databyte;
615  uint8_t dlc_value;
616  status_t stat = STATUS_SUCCESS;
617 
618  volatile uint32_t *flexcan_mb = FLEXCAN_HAL_GetMsgBuffRegion(base, msgBuffIdx);
619 
620  volatile uint32_t *flexcan_mb_id = &flexcan_mb[1];
621  volatile uint8_t *flexcan_mb_data = (volatile uint8_t *)(&flexcan_mb[2]);
622  volatile uint32_t *flexcan_mb_data_32 = &flexcan_mb[2];
623  const uint32_t *msgData_32 = (const uint32_t *)msgData;
624 
625  if (msgBuffIdx >= (((base->MCR) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT) )
626  {
628  }
629 
630  /* Check if RX FIFO is enabled*/
631  if (((base->MCR & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT) != 0U)
632  {
633  /* Get the number of RX FIFO Filters*/
634  val1 = (((base->CTRL2) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
635  /* Get the number if MBs occupied by RX FIFO and ID filter table*/
636  /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
637  /* Every number of RFFN means 8 number of RX FIFO filters*/
638  /* and every 4 number of RX FIFO filters occupied one MB*/
639  val2 = RxFifoOcuppiedLastMsgBuff(val1);
640 
641  if (msgBuffIdx <= val2) {
643  }
644  }
645 
646  if (stat == STATUS_SUCCESS)
647  {
648  /* Make sure the BRS bit will not be ignored */
649  if (FLEXCAN_HAL_IsFDEnabled(base) && cs->enable_brs)
650  {
651  base->FDCTRL = (base->FDCTRL & ~CAN_FDCTRL_FDRATE_MASK) | CAN_FDCTRL_FDRATE(1U);
652  }
653 
654  /* Compute the value of the DLC field */
655  dlc_value = FLEXCAN_HAL_ComputeDLCValue((uint8_t)cs->dataLen);
656 
657  /* Copy user's buffer into the message buffer data area */
658  if (msgData != NULL)
659  {
660  uint8_t payload_size = FLEXCAN_HAL_ComputePayloadSize(dlc_value);
661  for (databyte = 0; databyte < cs->dataLen; databyte += 4U)
662  {
663  REV_BYTES_32(msgData_32[databyte >> 2U], flexcan_mb_data_32[databyte >> 2U]);
664  }
665  for ( ; databyte < cs->dataLen; databyte++)
666  {
667  flexcan_mb_data[FlexcanSwapBytesInWordIndex(databyte)] = msgData[databyte];
668  }
669  /* Add padding, if needed */
670  for (databyte = cs->dataLen; databyte < payload_size; databyte++)
671  {
672  flexcan_mb_data[FlexcanSwapBytesInWordIndex(databyte)] = cs->fd_padding;
673  }
674  }
675 
676  /* Clean up the arbitration field area */
677  *flexcan_mb = 0;
678  *flexcan_mb_id = 0;
679 
680  /* Set the ID according the format structure */
681  if (cs->msgIdType == FLEXCAN_MSG_ID_EXT)
682  {
683  /* ID [28-0] */
684  *flexcan_mb_id &= ~(CAN_ID_STD_MASK | CAN_ID_EXT_MASK);
685  *flexcan_mb_id |= (msgId & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
686 
687  /* Set IDE */
688  flexcan_mb_config |= CAN_CS_IDE_MASK;
689 
690  /* Clear SRR bit */
691  flexcan_mb_config &= ~CAN_CS_SRR_MASK;
692  }
693  if(cs->msgIdType == FLEXCAN_MSG_ID_STD)
694  {
695  /* ID[28-18] */
696  *flexcan_mb_id &= ~CAN_ID_STD_MASK;
697  *flexcan_mb_id |= (msgId << CAN_ID_STD_SHIFT) & CAN_ID_STD_MASK;
698 
699  /* make sure IDE and SRR are not set */
700  flexcan_mb_config &= ~(CAN_CS_IDE_MASK | CAN_CS_SRR_MASK);
701  }
702 
703  /* Set the length of data in bytes */
704  flexcan_mb_config &= ~CAN_CS_DLC_MASK;
705  flexcan_mb_config |= ((uint32_t)dlc_value << CAN_CS_DLC_SHIFT) & CAN_CS_DLC_MASK;
706 
707  /* Set MB CODE */
708  if (cs->code != (uint32_t)FLEXCAN_TX_NOT_USED)
709  {
710  if (cs->code == (uint32_t)FLEXCAN_TX_REMOTE)
711  {
712  /* Set RTR bit */
713  flexcan_mb_config |= CAN_CS_RTR_MASK;
714  }
715 
716  /* Reset the code */
717  flexcan_mb_config &= ~CAN_CS_CODE_MASK;
718 
719  /* Set the code */
720  if (cs->fd_enable)
721  {
722  flexcan_mb_config |= ((cs->code << CAN_CS_CODE_SHIFT) & CAN_CS_CODE_MASK) | CAN_MB_EDL_MASK;
723  }
724  else
725  {
726  flexcan_mb_config |= (cs->code << CAN_CS_CODE_SHIFT) & CAN_CS_CODE_MASK;
727  }
728 
729  if (cs->enable_brs)
730  {
731  flexcan_mb_config |= CAN_MB_BRS_MASK;
732  }
733 
734  *flexcan_mb |= flexcan_mb_config;
735  }
736  }
737 
738  return stat;
739 }
740 
741 /*FUNCTION**********************************************************************
742  *
743  * Function Name : FLEXCAN_HAL_SetRxMsgBuff
744  * Description : Configure a message buffer for receiving.
745  * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
746  * the function will make sure if the MB requested is not occupied by RX FIFO
747  * and ID filter table. Then this function will configure the message buffer as
748  * required for receiving.
749  *
750  * Implements : FLEXCAN_HAL_SetRxMsgBuff_Activity
751  *END**************************************************************************/
753  CAN_Type * base,
754  uint32_t msgBuffIdx,
756  uint32_t msgId)
757 {
758  DEV_ASSERT(cs != NULL);
759 
760  uint32_t val1, val2 = 1;
761 
762  volatile uint32_t *flexcan_mb = FLEXCAN_HAL_GetMsgBuffRegion(base, msgBuffIdx);
763  volatile uint32_t *flexcan_mb_id = &flexcan_mb[1];
764  status_t stat = STATUS_SUCCESS;
765 
766  if (msgBuffIdx >= (((base->MCR) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT))
767  {
769  }
770 
771  /* Check if RX FIFO is enabled */
772  if (((base->MCR & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT) != 0U)
773  {
774  /* Get the number of RX FIFO Filters*/
775  val1 = (((base->CTRL2) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
776  /* Get the number if MBs occupied by RX FIFO and ID filter table*/
777  /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
778  /* Every number of RFFN means 8 number of RX FIFO filters*/
779  /* and every 4 number of RX FIFO filters occupied one MB*/
780  val2 = RxFifoOcuppiedLastMsgBuff(val1);
781 
782  if (msgBuffIdx <= val2) {
784  }
785  }
786 
787  if (stat == STATUS_SUCCESS)
788  {
789  /* Clean up the arbitration field area */
790  *flexcan_mb = 0;
791  *flexcan_mb_id = 0;
792 
793  /* Set the ID according the format structure */
794  if (cs->msgIdType == FLEXCAN_MSG_ID_EXT)
795  {
796  /* Set IDE */
797  *flexcan_mb |= CAN_CS_IDE_MASK;
798 
799  /* Clear SRR bit */
800  *flexcan_mb &= ~CAN_CS_SRR_MASK;
801 
802  /* ID [28-0] */
803  *flexcan_mb_id &= ~(CAN_ID_STD_MASK | CAN_ID_EXT_MASK);
804  *flexcan_mb_id |= (msgId & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
805  }
806  if (cs->msgIdType == FLEXCAN_MSG_ID_STD)
807  {
808  /* Make sure IDE and SRR are not set */
809  *flexcan_mb &= ~(CAN_CS_IDE_MASK | CAN_CS_SRR_MASK);
810 
811  /* ID[28-18] */
812  *flexcan_mb_id &= ~CAN_ID_STD_MASK;
813  *flexcan_mb_id |= (msgId << CAN_ID_STD_SHIFT) & CAN_ID_STD_MASK;
814  }
815 
816  /* Set MB CODE */
817  if (cs->code != (uint32_t)FLEXCAN_RX_NOT_USED)
818  {
819  *flexcan_mb &= ~CAN_CS_CODE_MASK;
820  *flexcan_mb |= (cs->code << CAN_CS_CODE_SHIFT) & CAN_CS_CODE_MASK;
821  }
822  }
823 
824  return stat;
825 }
826 
827 /*FUNCTION**********************************************************************
828  *
829  * Function Name : FLEXCAN_HAL_GetMsgBuff
830  * Description : Get a message buffer field values.
831  * This function will first check if RX FIFO is enabled. If RX FIFO is enabled,
832  * the function will make sure if the MB requested is not occupied by RX FIFO
833  * and ID filter table. Then this function will get the message buffer field
834  * values and copy the MB data field into user's buffer.
835  *
836  * Implements : FLEXCAN_HAL_GetMsgBuff_Activity
837  *END**************************************************************************/
839  CAN_Type * base,
840  uint32_t msgBuffIdx,
841  flexcan_msgbuff_t *msgBuff)
842 {
843  DEV_ASSERT(msgBuff != NULL);
844 
845  uint32_t i;
846  uint32_t val1, val2 = 1;
847  status_t stat = STATUS_SUCCESS;
848 
849  volatile const uint32_t *flexcan_mb = FLEXCAN_HAL_GetMsgBuffRegion(base, msgBuffIdx);
850  volatile const uint32_t *flexcan_mb_id = &flexcan_mb[1];
851  volatile const uint8_t *flexcan_mb_data = (volatile const uint8_t *)(&flexcan_mb[2]);
852  volatile const uint32_t *flexcan_mb_data_32 = &flexcan_mb[2];
853  uint32_t *msgBuff_data_32 = (uint32_t *)(msgBuff->data);
854  uint32_t mbWord;
855 
856  uint8_t flexcan_mb_dlc_value = (uint8_t)(((*flexcan_mb) & CAN_CS_DLC_MASK) >> 16);
857  uint8_t payload_size = FLEXCAN_HAL_ComputePayloadSize(flexcan_mb_dlc_value);
858 
859  msgBuff->dataLen = payload_size;
860 
861  if (msgBuffIdx >= (((base->MCR) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT))
862  {
864  }
865 
866  /* Check if RX FIFO is enabled */
867  if (((base->MCR & CAN_MCR_RFEN_MASK) >> CAN_MCR_RFEN_SHIFT) != 0U)
868  {
869  /* Get the number of RX FIFO Filters*/
870  val1 = (((base->CTRL2) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
871  /* Get the number if MBs occupied by RX FIFO and ID filter table*/
872  /* the Rx FIFO occupies the memory space originally reserved for MB0-5*/
873  /* Every number of RFFN means 8 number of RX FIFO filters*/
874  /* and every 4 number of RX FIFO filters occupied one MB*/
875  val2 = RxFifoOcuppiedLastMsgBuff(val1);
876 
877  if (msgBuffIdx <= val2) {
879  }
880  }
881 
882  if (stat == STATUS_SUCCESS)
883  {
884  /* Get a MB field values */
885  msgBuff->cs = *flexcan_mb;
886  if ((msgBuff->cs & CAN_CS_IDE_MASK) != 0U)
887  {
888  msgBuff->msgId = (*flexcan_mb_id);
889  }
890  else
891  {
892  msgBuff->msgId = (*flexcan_mb_id) >> CAN_ID_STD_SHIFT;
893  }
894 
895  /* Copy MB data field into user's buffer */
896  for (i = 0 ; i < payload_size ; i += 4U)
897  {
898  mbWord = flexcan_mb_data_32[i >> 2U];
899  REV_BYTES_32(mbWord, msgBuff_data_32[i >> 2U]);
900  }
901  for ( ; i < payload_size ; i++)
902  {
903  msgBuff->data[i] = flexcan_mb_data[FlexcanSwapBytesInWordIndex(i)];
904  }
905  }
906 
907  return stat;
908 }
909 
910 /*FUNCTION**********************************************************************
911  *
912  * Function Name : FLEXCAN_HAL_LockRxMsgBuff
913  * Description : Lock the RX message buffer.
914  * This function will lock the RX message buffer.
915  *
916  * Implements : FLEXCAN_HAL_LockRxMsgBuff_Activity
917  *END**************************************************************************/
919  CAN_Type * base,
920  uint32_t msgBuffIdx)
921 {
922  volatile const uint32_t *flexcan_mb = FLEXCAN_HAL_GetMsgBuffRegion(base, msgBuffIdx);
923  status_t stat = STATUS_SUCCESS;
924 
925  if (msgBuffIdx >= (((base->MCR) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT))
926  {
928  }
929 
930  if (stat == STATUS_SUCCESS)
931  {
932  /* Lock the mailbox by reading it */
933  (void)*flexcan_mb;
934  }
935 
936  return stat;
937 }
938 
939 /*FUNCTION**********************************************************************
940  *
941  * Function Name : FLEXCAN_HAL_EnableRxFifo
942  * Description : Enable Rx FIFO feature.
943  * This function will enable the Rx FIFO feature.
944  *
945  * Implements : FLEXCAN_HAL_EnableRxFifo_Activity
946  *END**************************************************************************/
947 status_t FLEXCAN_HAL_EnableRxFifo(CAN_Type * base, uint32_t numOfFilters)
948 {
949  uint32_t i;
950  status_t stat = STATUS_SUCCESS;
951 
952  /* RxFIFO cannot be enabled if FD is enabled */
953  if (FLEXCAN_HAL_IsFDEnabled(base))
954  {
955  stat = STATUS_ERROR;
956  }
957 
958  if (stat == STATUS_SUCCESS)
959  {
960  /* Set Freeze mode */
962 
963  /* Enable RX FIFO */
964  base->MCR = (base->MCR & ~CAN_MCR_RFEN_MASK) | CAN_MCR_RFEN(1U);
965  /* Set the number of the RX FIFO filters needed */
966  base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | ((numOfFilters << CAN_CTRL2_RFFN_SHIFT) & CAN_CTRL2_RFFN_MASK);
967  /* RX FIFO global mask */
969 
970  for (i = 0; i < CAN_RXIMR_COUNT; i++)
971  {
972  /* RX individual mask */
974  }
975 
976  /* De-assert Freeze Mode */
978  }
979 
980  return stat;
981 }
982 
983 /*FUNCTION**********************************************************************
984  *
985  * Function Name : FLEXCAN_HAL_DisableRxFifo
986  * Description : Disable Rx FIFO feature.
987  * This function will disable the Rx FIFO feature.
988  *
989  * Implements : FLEXCAN_HAL_DisableRxFifo_Activity
990  *END**************************************************************************/
992 {
993  /* Set Freeze mode*/
995 
996  /* Disable RX FIFO */
997  base->MCR = (base->MCR & ~CAN_MCR_RFEN_MASK) | CAN_MCR_RFEN(0U);
998 
999  /* De-assert Freeze Mode*/
1001 }
1002 
1003 /*FUNCTION**********************************************************************
1004  *
1005  * Function Name : FLEXCAN_HAL_SetRxFifoFilterNum
1006  * Description : Set the number of Rx FIFO filters.
1007  * This function will define the number of Rx FIFO filters.
1008  *
1009  * Implements : FLEXCAN_HAL_SetRxFifoFilterNum_Activity
1010  *END**************************************************************************/
1012  CAN_Type * base,
1013  uint32_t number)
1014 {
1015  /* Set Freeze mode*/
1017 
1018  /* Set the number of RX FIFO ID filters*/
1019  (base->CTRL2) = (((base->CTRL2) & ~(CAN_CTRL2_RFFN_MASK)) | (((uint32_t)(((uint32_t)(number))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK));
1020 
1021  /* De-assert Freeze Mode*/
1023 }
1024 
1025 /*FUNCTION**********************************************************************
1026  *
1027  * Function Name : FLEXCAN_HAL_SetMaxMsgBuffNum
1028  * Description : Set the number of the last Message Buffers.
1029  * This function will define the number of the last Message Buffers
1030  *
1031  * Implements : FLEXCAN_HAL_SetMaxMsgBuffNum_Activity
1032  *END**************************************************************************/
1034  CAN_Type * base,
1035  uint32_t maxMsgBuffNum)
1036 {
1037  uint8_t msgBuffIdx;
1038  uint32_t databyte;
1039  uint8_t can_real_payload = FLEXCAN_HAL_GetPayloadSize(base);
1040  uint8_t max_mb_num = (uint8_t)(FLEXCAN_HAL_MaxMbRAMSize(base) /
1041  ((uint32_t)FLEXCAN_ARBITRATION_FIELD_SIZE + can_real_payload));
1042  status_t status = STATUS_SUCCESS;
1043 
1044  /* Set Freeze mode*/
1046 
1047  /* Check that the number of MBs is supported */
1048  if (maxMsgBuffNum > max_mb_num)
1049  {
1051  }
1052 
1053  if (status == STATUS_SUCCESS)
1054  {
1055  /* Set the maximum number of MBs*/
1056  base->MCR = (base->MCR & ~CAN_MCR_MAXMB_MASK) | ((maxMsgBuffNum << CAN_MCR_MAXMB_SHIFT) & CAN_MCR_MAXMB_MASK);
1057 
1058  if (!FLEXCAN_HAL_IsRxFifoEnabled(base))
1059  {
1060  /* Initialize all message buffers as inactive */
1061  for (msgBuffIdx = 0; msgBuffIdx < maxMsgBuffNum; msgBuffIdx++)
1062  {
1063  volatile uint32_t *flexcan_mb = FLEXCAN_HAL_GetMsgBuffRegion(base, msgBuffIdx);
1064  volatile uint32_t *flexcan_mb_id = &flexcan_mb[1];
1065  volatile uint8_t *flexcan_mb_data = (volatile uint8_t *)(&flexcan_mb[2]);
1066 
1067  *flexcan_mb = 0x0;
1068  *flexcan_mb_id = 0x0;
1069  for (databyte = 0; databyte < can_real_payload; databyte++)
1070  {
1071  flexcan_mb_data[databyte] = 0x0;
1072  }
1073  }
1074  }
1075  }
1076 
1077  /* De-assert Freeze Mode*/
1079 
1080  return status;
1081 }
1082 
1083 /*FUNCTION**********************************************************************
1084  *
1085  * Function Name : FLEXCAN_HAL_SetRxFifoFilter
1086  * Description : Confgure RX FIFO ID filter table elements.
1087  *
1088  * Implements : FLEXCAN_HAL_SetRxFifoFilter_Activity
1089  *END**************************************************************************/
1091  CAN_Type * base,
1093  const flexcan_id_table_t *idFilterTable)
1094 {
1095  DEV_ASSERT(idFilterTable != NULL);
1096 
1097  /* Set RX FIFO ID filter table elements*/
1098  uint32_t i, j, numOfFilters;
1099  uint32_t val1 = 0, val2 = 0, val = 0;
1100 
1101  volatile uint32_t *filterTable = &base->RAMn[RxFifoFilterTableOffset];
1102 
1103  numOfFilters = (((base->CTRL2) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT);
1104 
1105  switch(idFormat)
1106  {
1108  /* One full ID (standard and extended) per ID Filter Table element.*/
1109  (base->MCR) = (((base->MCR) & ~(CAN_MCR_IDAM_MASK)) | ( (((uint32_t)(((uint32_t)(FLEXCAN_RX_FIFO_ID_FORMAT_A))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)));
1110  if (idFilterTable->isRemoteFrame)
1111  {
1113  }
1114  if (idFilterTable->isExtendedFrame)
1115  {
1117  }
1118  for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++)
1119  {
1120  if(idFilterTable->isExtendedFrame)
1121  {
1122  filterTable[i] = val + ((idFilterTable->idFilter[i] <<
1125  }
1126  else
1127  {
1128  filterTable[i] = val + ((idFilterTable->idFilter[i] <<
1131  }
1132  }
1133  break;
1135  /* Two full standard IDs or two partial 14-bit (standard and extended) IDs*/
1136  /* per ID Filter Table element.*/
1137  (base->MCR) = (((base->MCR) & ~(CAN_MCR_IDAM_MASK)) | ( (((uint32_t)(((uint32_t)(FLEXCAN_RX_FIFO_ID_FORMAT_B))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)));
1138  if (idFilterTable->isRemoteFrame)
1139  {
1142  }
1143  if (idFilterTable->isExtendedFrame)
1144  {
1147  }
1148  j = 0;
1149  for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++)
1150  {
1151  if (idFilterTable->isExtendedFrame)
1152  {
1153  filterTable[i] = val1 + ((idFilterTable->idFilter[j] &
1156  filterTable[i] |= val2 + ((idFilterTable->idFilter[j + 1U] &
1159  }
1160  else
1161  {
1162  filterTable[i] = val1 + ((idFilterTable->idFilter[j] &
1165  filterTable[i] |= val2 + ((idFilterTable->idFilter[j + 1U] &
1168  }
1169  j = j + 2U;
1170  }
1171  break;
1173  /* Four partial 8-bit Standard IDs per ID Filter Table element.*/
1174  (base->MCR) = (((base->MCR) & ~(CAN_MCR_IDAM_MASK)) | ( (((uint32_t)(((uint32_t)(FLEXCAN_RX_FIFO_ID_FORMAT_C))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)));
1175  j = 0;
1176  for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++)
1177  {
1178  filterTable[i] = ((idFilterTable->idFilter[j] &
1181  filterTable[i] = ((idFilterTable->idFilter[j + 1U] &
1184  filterTable[i] = ((idFilterTable->idFilter[j + 2U] &
1187  filterTable[i] = ((idFilterTable->idFilter[j + 3U] &
1190  j = j + 4U;
1191  }
1192  break;
1194  /* All frames rejected.*/
1195  (base->MCR) = (((base->MCR) & ~(CAN_MCR_IDAM_MASK)) | ( (((uint32_t)(((uint32_t)(FLEXCAN_RX_FIFO_ID_FORMAT_D))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)));
1196  break;
1197  default:
1198  /* Should not get here */
1199  break;
1200  }
1201 }
1202 
1203 /*FUNCTION**********************************************************************
1204  *
1205  * Function Name : FLEXCAN_HAL_SetMsgBuffIntCmd
1206  * Description : Enable/Disable the corresponding Message Buffer interrupt.
1207  *
1208  * Implements : FLEXCAN_HAL_SetMsgBuffIntCmd_Activity
1209  *END**************************************************************************/
1211  CAN_Type * base,
1212  uint32_t msgBuffIdx, bool enable)
1213 {
1214  uint32_t temp;
1215  status_t stat = STATUS_SUCCESS;
1216 
1217  if (msgBuffIdx >= (((base->MCR) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT))
1218  {
1220  }
1221 
1222  if (stat == STATUS_SUCCESS)
1223  {
1224  /* Enable the corresponding message buffer Interrupt */
1225  temp = 1UL << msgBuffIdx;
1226  if(enable)
1227  {
1228  (base->IMASK1) = ((base ->IMASK1) | (temp));
1229  }
1230  else
1231  {
1232  (base->IMASK1) = ((base->IMASK1) & ~(temp));
1233  }
1234  }
1235 
1236  return stat;
1237 }
1238 
1239 /*FUNCTION**********************************************************************
1240  *
1241  * Function Name : FLEXCAN_HAL_SetErrIntCmd
1242  * Description : Enable the error interrupts.
1243  * This function will enable Error interrupt.
1244  *
1245  * Implements : FLEXCAN_HAL_SetErrIntCmd_Activity
1246  *END**************************************************************************/
1247 void FLEXCAN_HAL_SetErrIntCmd(CAN_Type * base, flexcan_int_type_t errType, bool enable)
1248 {
1249  uint32_t temp = (uint32_t)errType;
1250  if (enable)
1251  {
1252  if((errType == FLEXCAN_INT_RX_WARNING)||(errType == FLEXCAN_INT_TX_WARNING))
1253  {
1254  base->MCR = (base->MCR & ~CAN_MCR_WRNEN_MASK) | CAN_MCR_WRNEN(1U);
1255  }
1256  (base->CTRL1) = ((base->CTRL1) | (temp));
1257  }
1258  else
1259  {
1260  (base->CTRL1) = ((base->CTRL1) & ~(temp));
1261  }
1262 }
1263 
1264 
1265 /*FUNCTION**********************************************************************
1266  *
1267  * Function Name : FLEXCAN_HAL_ExitFreezeMode
1268  * Description : Exit of freeze mode.
1269  *
1270  * Implements : FLEXCAN_HAL_ExitFreezeMode_Activity
1271  *END**************************************************************************/
1273 {
1274  base->MCR = (base->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(0U);
1275  base->MCR = (base->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(0U);
1276 
1277  /* Wait till exit freeze mode */
1278  while (((base->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) != 0U) {}
1279 }
1280 
1281 /*FUNCTION**********************************************************************
1282  *
1283  * Function Name : FLEXCAN_HAL_EnterFreezeMode
1284  * Description : Enter the freeze mode.
1285  *
1286  * Implements : FLEXCAN_HAL_EnterFreezeMode_Activity
1287  *END**************************************************************************/
1289 {
1290  base->MCR = (base->MCR & ~CAN_MCR_FRZ_MASK) | CAN_MCR_FRZ(1U);
1291  base->MCR = (base->MCR & ~CAN_MCR_HALT_MASK) | CAN_MCR_HALT(1U);
1292 
1293  /* Wait for entering the freeze mode */
1294  while (((base->MCR & CAN_MCR_FRZACK_MASK) >> CAN_MCR_FRZACK_SHIFT) == 0U) {}
1295 }
1296 
1297 /*FUNCTION**********************************************************************
1298  *
1299  * Function Name : FLEXCAN_HAL_GetMsgBuffIntStatusFlag
1300  * Description : Get the corresponding message buffer interrupt flag.
1301  *
1302  * Implements : FLEXCAN_HAL_GetMsgBuffIntStatusFlag_Activity
1303  *END**************************************************************************/
1305  const CAN_Type * base,
1306  uint32_t msgBuffIdx)
1307 {
1308  /* Get the corresponding message buffer interrupt flag */
1309  return (uint8_t)((base->IFLAG1 >> msgBuffIdx) & 1U);
1310 }
1311 
1312 /*FUNCTION**********************************************************************
1313  *
1314  * Function Name : FLEXCAN_HAL_GetErrCounter
1315  * Description : Get transmit error counter and receive error counter.
1316  *
1317  * Implements : FLEXCAN_HAL_GetErrCounter_Activity
1318  *END**************************************************************************/
1320  const CAN_Type * base,
1321  flexcan_buserr_counter_t *errCount)
1322 {
1323  DEV_ASSERT(errCount != NULL);
1324 
1325  /* Get transmit error counter and receive error counter */
1326  errCount->rxerr = (uint16_t)(((base->ECR) & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT);
1327  errCount->txerr = (uint16_t)(((base->ECR) & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT);
1328 }
1329 
1330 /*FUNCTION**********************************************************************
1331  *
1332  * Function Name : FLEXCAN_HAL_ClearErrIntStatusFlag
1333  * Description : Clear all error interrupt status.
1334  *
1335  * Implements : FLEXCAN_HAL_ClearErrIntStatusFlag_Activity
1336  *END**************************************************************************/
1338 {
1339  if((base->ESR1 & FLEXCAN_ALL_INT) != 0U)
1340  {
1341  (base->ESR1) = FLEXCAN_ALL_INT;
1342 #ifdef ERRATA_E9005
1343  /* Dummy read as a workaround for errata e9005 to ensure the flags are
1344  cleared before continuing. */
1345  (void)(base->ESR1);
1346 #endif
1347  }
1348 }
1349 
1350 /*FUNCTION**********************************************************************
1351  *
1352  * Function Name : FLEXCAN_HAL_ReadRxFifo
1353  * Description : Read Rx FIFO data.
1354  * This function will copy MB[0] data field into user's buffer.
1355  *
1356  * Implements : FLEXCAN_HAL_ReadRxFifo_Activity
1357  *END**************************************************************************/
1359  const CAN_Type * base,
1360  flexcan_msgbuff_t *rxFifo)
1361 {
1362  DEV_ASSERT(rxFifo != NULL);
1363 
1364  uint32_t databyte;
1365  uint32_t mbWord;
1366 
1367  volatile const uint32_t *flexcan_mb = base->RAMn;
1368  volatile const uint32_t *flexcan_mb_id = &base->RAMn[1];
1369  volatile const uint32_t *flexcan_mb_data_32 = &flexcan_mb[2];
1370  uint32_t *msgData_32 = (uint32_t *)(rxFifo->data);
1371 
1372  uint8_t flexcan_mb_dlc_value = (uint8_t)(((*flexcan_mb) & CAN_CS_DLC_MASK) >> 16);
1373  uint8_t can_real_payload = FLEXCAN_HAL_ComputePayloadSize(flexcan_mb_dlc_value);
1374 
1375  rxFifo->dataLen = can_real_payload;
1376  rxFifo->cs = *flexcan_mb;
1377 
1378  if ((rxFifo->cs & CAN_CS_IDE_MASK) != 0U)
1379  {
1380  rxFifo->msgId = *flexcan_mb_id;
1381  }
1382  else
1383  {
1384  rxFifo->msgId = (*flexcan_mb_id) >> CAN_ID_STD_SHIFT;
1385  }
1386 
1387  /* Copy MB[0] data field into user's buffer */
1388  for (databyte = 0; databyte < can_real_payload; databyte += 4U)
1389  {
1390  mbWord = flexcan_mb_data_32[databyte >> 2U];
1391  REV_BYTES_32(mbWord, msgData_32[databyte >> 2U]);
1392  }
1393 }
1394 
1395 /*FUNCTION**********************************************************************
1396  *
1397  * Function Name : FLEXCAN_HAL_SetMaskType
1398  * Description : Set RX masking type.
1399  * This function will set RX masking type as RX global mask or RX individual
1400  * mask.
1401  *
1402  * Implements : FLEXCAN_HAL_SetRxMaskType_Activity
1403  *END**************************************************************************/
1405  CAN_Type * base,
1407 {
1408  /* Set Freeze mode*/
1410 
1411  /* Set RX masking type (RX global mask or RX individual mask)*/
1412  if (type == FLEXCAN_RX_MASK_GLOBAL)
1413  {
1414  /* Enable Global RX masking */
1415  base->MCR = (base->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(0U);
1416  }
1417  else
1418  {
1419  /* Enable Individual Rx Masking and Queue */
1420  base->MCR = (base->MCR & ~CAN_MCR_IRMQ_MASK) | CAN_MCR_IRMQ(1U);
1421  }
1422 
1423  /* De-assert Freeze Mode*/
1425 }
1426 
1427 /*FUNCTION**********************************************************************
1428  *
1429  * Function Name : FLEXCAN_HAL_SetRxFifoGlobalStdMask
1430  * Description : Set Rx FIFO global mask as the 11-bit standard mask.
1431  *
1432  * Implements : FLEXCAN_HAL_SetRxFifoGlobalStdMask_Activity
1433  *END**************************************************************************/
1435  CAN_Type * base,
1436  uint32_t stdMask)
1437 {
1438  /* Set Freeze mode*/
1440 
1441  /* 11 bit standard mask*/
1442  (base->RXFGMASK) = (((uint32_t)(((uint32_t)(stdMask))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK);
1443 
1444  /* De-assert Freeze Mode*/
1446 }
1447 
1448 /*FUNCTION**********************************************************************
1449  *
1450  * Function Name : FLEXCAN_HAL_SetRxFifoGlobalExtMask
1451  * Description : Set Rx FIFO global mask as the 29-bit extended mask.
1452  *
1453  * Implements : FLEXCAN_HAL_SetRxFifoGlobalExtMask_Activity
1454  *END**************************************************************************/
1456  CAN_Type * base,
1457  uint32_t extMask)
1458 {
1459  /* Set Freeze mode*/
1461 
1462  /* 29-bit extended mask*/
1463  (base->RXFGMASK) = (((uint32_t)(((uint32_t)(extMask)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
1464 
1465  /* De-assert Freeze Mode*/
1467 }
1468 
1469 /*FUNCTION**********************************************************************
1470  *
1471  * Function Name : FLEXCAN_HAL_SetRxIndividualStdMask
1472  * Description : Set Rx individual mask as the 11-bit standard mask.
1473  *
1474  * Implements : FLEXCAN_HAL_SetRxIndividualStdMask_Activity
1475  *END**************************************************************************/
1477  CAN_Type * base,
1478  uint32_t msgBuffIdx,
1479  uint32_t stdMask)
1480 {
1481  status_t stat = STATUS_SUCCESS;
1482 
1483  if (msgBuffIdx >= ((((base->MCR) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT)))
1484  {
1486  }
1487 
1488  if (stat == STATUS_SUCCESS)
1489  {
1490  /* Set Freeze mode */
1492 
1493  /* 11 bit standard mask*/
1494  (base->RXIMR[msgBuffIdx]) = (stdMask << CAN_ID_STD_SHIFT) & CAN_ID_STD_MASK;
1495 
1496  /* De-assert Freeze Mode */
1498  }
1499 
1500  return stat;
1501 }
1502 
1503 /*FUNCTION**********************************************************************
1504  *
1505  * Function Name : FLEXCAN_HAL_SetRxIndividualExtMask
1506  * Description : Set Rx individual mask as the 29-bit extended mask.
1507  *
1508  * Implements : FLEXCAN_HAL_SetRxIndividualExtMask_Activity
1509  *END**************************************************************************/
1511  CAN_Type * base,
1512  uint32_t msgBuffIdx,
1513  uint32_t extMask)
1514 {
1515  status_t stat = STATUS_SUCCESS;
1516 
1517  if (msgBuffIdx >= (((base->MCR) & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT))
1518  {
1520  }
1521 
1522  if (stat == STATUS_SUCCESS)
1523  {
1524  /* Set Freeze mode */
1526 
1527  /* 29-bit extended mask */
1528  base->RXIMR[msgBuffIdx] = (extMask << CAN_ID_EXT_SHIFT) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK);
1529  /* De-assert Freeze Mode */
1531  }
1532 
1533  return stat;
1534 }
1535 
1536 /*FUNCTION**********************************************************************
1537  *
1538  * Function Name : FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask
1539  * Description : Set Rx Message Buffer global mask as the 11-bit standard mask.
1540  *
1541  * Implements : FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask_Activity
1542  *END**************************************************************************/
1544  CAN_Type * base,
1545  uint32_t stdMask)
1546 {
1547  /* Set Freeze mode*/
1549 
1550  /* 11 bit standard mask*/
1551 
1552  (base->RXMGMASK) = (((uint32_t)(((uint32_t)(stdMask))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK);
1553 
1554  /* De-assert Freeze Mode*/
1556 }
1557 
1558 /*FUNCTION**********************************************************************
1559  *
1560  * Function Name : FLEXCAN_HAL_SetRxMsgBuff14StdMask
1561  * Description : Set Rx Message Buffer 14 mask as the 11-bit standard mask.
1562  *
1563  * Implements : FLEXCAN_HAL_SetRxMsgBuff14StdMask_Activity
1564  *END**************************************************************************/
1566  CAN_Type * base,
1567  uint32_t stdMask)
1568 {
1569  /* Set Freeze mode*/
1571 
1572  /* 11 bit standard mask*/
1573  (base->RX14MASK) = (((uint32_t)(((uint32_t)(stdMask))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK);
1574 
1575  /* De-assert Freeze Mode*/
1577 }
1578 
1579 /*FUNCTION**********************************************************************
1580  *
1581  * Function Name : FLEXCAN_HAL_SetRxMsgBuff15StdMask
1582  * Description : Set Rx Message Buffer 15 mask as the 11-bit standard mask.
1583  *
1584  * Implements : FLEXCAN_HAL_SetRxMsgBuff15StdMask_Activity
1585  *END**************************************************************************/
1587  CAN_Type * base,
1588  uint32_t stdMask)
1589 {
1590  /* Set Freeze mode*/
1592 
1593  /* 11 bit standard mask*/
1594  (base->RX15MASK) = (((uint32_t)(((uint32_t)(stdMask))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK);
1595 
1596  /* De-assert Freeze Mode*/
1598 }
1599 
1600 /*FUNCTION**********************************************************************
1601  *
1602  * Function Name : FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask
1603  * Description : Set Rx Message Buffer global mask as the 29-bit extended mask.
1604  *
1605  * Implements : FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask_Activity
1606  *END**************************************************************************/
1608  CAN_Type * base,
1609  uint32_t extMask)
1610 {
1611  /* Set Freeze mode*/
1613 
1614  /* 29-bit extended mask*/
1615  (base->RXMGMASK) = (((uint32_t)(((uint32_t)(extMask)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
1616 
1617  /* De-assert Freeze Mode*/
1619 }
1620 
1621 /*FUNCTION**********************************************************************
1622  *
1623  * Function Name : FLEXCAN_HAL_SetRxMsgBuff14ExtMask
1624  * Description : Set Rx Message Buffer 14 mask as the 29-bit extended mask.
1625  *
1626  * Implements : FLEXCAN_HAL_SetRxMsgBuff14ExtMask_Activity
1627  *END**************************************************************************/
1629  CAN_Type * base,
1630  uint32_t extMask)
1631 {
1632  /* Set Freeze mode*/
1634 
1635  /* 29-bit extended mask*/
1636  (base->RX14MASK) = (((uint32_t)(((uint32_t)(extMask)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
1637 
1638  /* De-assert Freeze Mode*/
1640 }
1641 
1642 /*FUNCTION**********************************************************************
1643  *
1644  * Function Name : FLEXCAN_HAL_SetRxMsgBuff15ExtMask
1645  * Description : Set Rx Message Buffer 15 mask as the 29-bit extended mask.
1646  *
1647  * Implements : FLEXCAN_HAL_SetRxMsgBuff15ExtMask_Activity
1648  *END**************************************************************************/
1650  CAN_Type * base,
1651  uint32_t extMask)
1652 {
1653  /* Set Freeze mode*/
1655 
1656  /* 29-bit extended mask*/
1657  (base->RX15MASK) = (((uint32_t)(((uint32_t)(extMask)) << CAN_ID_EXT_SHIFT)) & (CAN_ID_STD_MASK | CAN_ID_EXT_MASK));
1658 
1659  /* De-assert Freeze Mode*/
1661 }
1662 
1663 /*FUNCTION**********************************************************************
1664  *
1665  * Function Name : FLEXCAN_HAL_SetOperationMode
1666  * Description : Enable a FlexCAN operation mode.
1667  * This function will enable one of the modes listed in flexcan_operation_modes_t.
1668  *
1669  * Implements : FLEXCAN_HAL_SetOperationMode_Activity
1670  *END**************************************************************************/
1672  CAN_Type * base,
1674 {
1675 
1676  if (mode == FLEXCAN_FREEZE_MODE)
1677  {
1678  /* Debug mode, Halt and Freeze*/
1680  }
1681  else if (mode == FLEXCAN_DISABLE_MODE)
1682  {
1683  /* Debug mode, Halt and Freeze */
1684  base->MCR = (base->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(1U);
1685  }
1686  else {
1687  /* Set Freeze mode */
1689 
1690  if (mode == FLEXCAN_NORMAL_MODE)
1691  {
1692  base->MCR = (base->MCR & ~CAN_MCR_SUPV_MASK) | CAN_MCR_SUPV(0U);
1693  base->CTRL1 = (base->CTRL1 & ~CAN_CTRL1_LOM_MASK) | CAN_CTRL1_LOM(0U);
1694  base->CTRL1 = (base->CTRL1 & ~CAN_CTRL1_LPB_MASK) | CAN_CTRL1_LPB(0U);
1695  }
1696  else if (mode == FLEXCAN_LISTEN_ONLY_MODE)
1697  {
1698  base->CTRL1 = (base->CTRL1 & ~CAN_CTRL1_LOM_MASK) | CAN_CTRL1_LOM(1U);
1699  }
1700  else if (mode == FLEXCAN_LOOPBACK_MODE)
1701  {
1702  base->CTRL1 = (base->CTRL1 & ~CAN_CTRL1_LPB_MASK) | CAN_CTRL1_LPB(1U);
1703  base->CTRL1 = (base->CTRL1 & ~CAN_CTRL1_LOM_MASK) | CAN_CTRL1_LOM(0U);
1704  }
1705  else {
1706  /* Should not get here */
1707  }
1708 
1709  /* De-assert Freeze Mode */
1711  }
1712 }
1713 
1714 /*FUNCTION**********************************************************************
1715  *
1716  * Function Name : FLEXCAN_HAL_ExitOperationMode
1717  * Description : Disable a FlexCAN operation mode.
1718  * This function will disable one of the modes listed in flexcan_operation_modes_t.
1719  *
1720  * Implements : FLEXCAN_HAL_ExitOperationMode_Activity
1721  *END**************************************************************************/
1723  CAN_Type * base,
1725 {
1726 
1727  if (mode == FLEXCAN_FREEZE_MODE)
1728  {
1729  /* De-assert Freeze Mode*/
1731  }
1732  else if (mode == FLEXCAN_DISABLE_MODE)
1733  {
1734  /* Disable module mode*/
1735  base->MCR = (base->MCR & ~CAN_MCR_MDIS_MASK) | CAN_MCR_MDIS(0U);
1736  }
1737  else
1738  {
1739  /* Set Freeze mode */
1741 
1742  if (mode == FLEXCAN_NORMAL_MODE)
1743  {
1744  base->MCR = (base->MCR & ~CAN_MCR_SUPV_MASK) | CAN_MCR_SUPV(1U);
1745  }
1746  else if (mode == FLEXCAN_LISTEN_ONLY_MODE)
1747  {
1748  base->CTRL1 = (base->CTRL1 & ~CAN_CTRL1_LOM_MASK) | CAN_CTRL1_LOM(0U);
1749  }
1750  else if (mode == FLEXCAN_LOOPBACK_MODE)
1751  {
1752  base->CTRL1 = (base->CTRL1 & ~CAN_CTRL1_LPB_MASK) | CAN_CTRL1_LPB(0U);
1753  }
1754  else
1755  {
1756  /* Should not get here */
1757  }
1758 
1759  /* De-assert Freeze Mode */
1761  }
1762 }
1763 
1764 /*FUNCTION**********************************************************************
1765  *
1766  * Function Name : FLEXCAN_HAL_SetFDEnabled
1767  * Description : Enables/Disables Flexible Data rate (if supported).
1768  *
1769  * Implements : FLEXCAN_HAL_SetFDEnabled_Activity
1770  *END**************************************************************************/
1771 void FLEXCAN_HAL_SetFDEnabled(CAN_Type * base, bool enable)
1772 {
1774 
1775  base->MCR = (base->MCR & ~CAN_MCR_FDEN_MASK) | CAN_MCR_FDEN(enable? 1UL : 0UL);
1776 
1777  /* Enable the use of extended bit time definitions */
1778  base->CBT = base->CBT | CAN_CBT_BTF(1U);
1779 
1781 }
1782 
1783 /*FUNCTION**********************************************************************
1784  *
1785  * Function Name : FLEXCAN_HAL_IsFDEnabled
1786  * Description : Checks if the Flexible Data rate feature is enabled.
1787  *
1788  * Implements : FLEXCAN_HAL_IsFDEnabled_Activity
1789  *END**************************************************************************/
1791 {
1792  return (((base->MCR & CAN_MCR_FDEN_MASK) >> CAN_MCR_FDEN_SHIFT) != 0U);
1793 }
1794 
1795 /*FUNCTION**********************************************************************
1796  *
1797  * Function Name : FLEXCAN_HAL_SetPayloadSize
1798  * Description : Sets the payload size of the MBs.
1799  *
1800  * Implements : FLEXCAN_HAL_SetPayloadSize_Activity
1801  *END**************************************************************************/
1803  CAN_Type * base,
1804  flexcan_fd_payload_size_t payloadSize)
1805 {
1806  uint32_t tmp;
1807 
1808  DEV_ASSERT(FLEXCAN_HAL_IsFDEnabled(base) || (payloadSize == FLEXCAN_PAYLOAD_SIZE_8));
1809 
1810  /* If FD is not enabled, only 8 bytes payload is supported */
1811  if (FLEXCAN_HAL_IsFDEnabled(base))
1812  {
1814 
1815  tmp = base->FDCTRL;
1816  tmp &= ~(CAN_FDCTRL_MBDSR0_MASK);
1817  tmp |= ((uint32_t)payloadSize) << CAN_FDCTRL_MBDSR0_SHIFT;
1818 #if FEATURE_CAN_HAS_MBDSR1
1819  tmp &= ~(CAN_FDCTRL_MBDSR1_MASK);
1820  tmp |= ((uint32_t)payloadSize) << CAN_FDCTRL_MBDSR1_SHIFT;
1821 #endif
1822 
1823  base->FDCTRL = tmp;
1824 
1826  }
1827 }
1828 
1829 /*FUNCTION**********************************************************************
1830  *
1831  * Function Name : FLEXCAN_HAL_GetPayloadSize
1832  * Description : Returns the payload size of the MBs (in bytes).
1833  *
1834  * Implements : FLEXCAN_HAL_GetPayloadSize_Activity
1835  *END**************************************************************************/
1837 {
1838  uint32_t payloadSize;
1839 
1840  /* The standard payload size is 8 bytes */
1841  if (!FLEXCAN_HAL_IsFDEnabled(base))
1842  {
1843  payloadSize = 8U;
1844  }
1845  else
1846  {
1847  payloadSize = 1UL << (((base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT) + 3U);
1848  }
1849 
1850  return (uint8_t)payloadSize;
1851 }
1852 
1853 
1854 /*FUNCTION**********************************************************************
1855  *
1856  * Function Name : FLEXCAN_HAL_SetStuffBitCount
1857  * Description : Enables/Disables the Stuff Bit Count for CAN FD frames.
1858  *
1859  * Implements : FLEXCAN_HAL_SetStuffBitCount_Activity
1860  *END**************************************************************************/
1861 void FLEXCAN_HAL_SetStuffBitCount(CAN_Type * base, bool enable)
1862 {
1864 
1865 #if FEATURE_CAN_HAS_STFCNTEN_ENABLE
1866  base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_STFCNTEN_MASK) | CAN_CTRL2_STFCNTEN(enable? 1UL : 0UL);
1867 #elif FEATURE_CAN_HAS_ISOCANFDEN_ENABLE
1868  base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_ISOCANFDEN_MASK) |
1869  CAN_CTRL2_ISOCANFDEN(enable? 1UL : 0UL);
1870 #endif
1871 
1873 }
1874 
1875 /*FUNCTION**********************************************************************
1876  *
1877  * Function Name : FLEXCAN_HAL_SetSelfReception
1878  * Description : Enables/Disables the Self Reception feature.
1879  *
1880  * Implements : FLEXCAN_HAL_SetSelfReception_Activity
1881  *END**************************************************************************/
1882 void FLEXCAN_HAL_SetSelfReception(CAN_Type * base, bool enable)
1883 {
1885 
1886  base->MCR = (base->MCR & ~CAN_MCR_SRXDIS_MASK) | CAN_MCR_SRXDIS(enable? 0UL : 1UL);
1887 
1889 }
1890 
1891 #if FEATURE_CAN_HAS_DMA_ENABLE
1892 /*FUNCTION**********************************************************************
1893  *
1894  * Function Name : FLEXCAN_HAL_SetRxFifoDMA
1895  * Description : Enables/Disables the DMA support for RxFIFO.
1896  *
1897  * Implements : FLEXCAN_HAL_SetRxFifoDMA_Activity
1898  *END**************************************************************************/
1899 status_t FLEXCAN_HAL_SetRxFifoDMA(CAN_Type * base, bool enable)
1900 {
1901  uint32_t rxFifoEnabled = (base->MCR & CAN_MCR_RFEN_MASK);
1902  if (enable && (rxFifoEnabled == 0U))
1903  {
1904  return STATUS_ERROR;
1905  }
1906 
1908 
1909  base->MCR = (base->MCR & ~CAN_MCR_DMA_MASK) | CAN_MCR_DMA(enable? 1UL : 0UL);
1910 
1912 
1913  return STATUS_SUCCESS;
1914 }
1915 #endif
1916 
1917 /*FUNCTION**********************************************************************
1918  *
1919  * Function Name : FLEXCAN_HAL_SetTDCOffset
1920  * Description : Enables/Disables the Transceiver Delay Compensation feature
1921  * and sets the Transceiver Delay Compensation Offset.
1922  *
1923  * Implements : FLEXCAN_HAL_SetTDCOffset_Activity
1924  *END**************************************************************************/
1925 void FLEXCAN_HAL_SetTDCOffset(CAN_Type * base, bool enable, uint8_t offset)
1926 {
1927  uint32_t tmp;
1928 
1930 
1931  tmp = base->FDCTRL;
1932 
1933  if (enable)
1934  {
1935  tmp = tmp | CAN_FDCTRL_TDCEN_MASK;
1936  tmp = tmp & ~CAN_FDCTRL_TDCOFF_MASK;
1937  tmp = tmp | CAN_FDCTRL_TDCOFF(offset);
1938  }
1939  else
1940  {
1941  tmp = tmp & ~CAN_FDCTRL_TDCEN_MASK;
1942  }
1943 
1944  base->FDCTRL = tmp;
1945 
1947 }
1948 
1949 #if FEATURE_CAN_HAS_PRETENDED_NETWORKING
1950 
1951 /*FUNCTION**********************************************************************
1952  *
1953  * Function Name : FLEXCAN_HAL_ConfigPN
1954  * Description : Configures the Pretended Networking mode.
1955  *
1956  * Implements : FLEXCAN_HAL_ConfigPN_Activity
1957  *END**************************************************************************/
1958 void FLEXCAN_HAL_ConfigPN(CAN_Type * base, const flexcan_pn_config_t *pnConfig)
1959 {
1960  DEV_ASSERT(pnConfig != NULL);
1961 
1962  uint32_t tmp;
1963 
1964  /* Configure specific pretended networking settings */
1965  tmp = base->CTRL1_PN;
1968  tmp |= CAN_CTRL1_PN_WTOF_MSK(pnConfig->wakeUpTimeout ? 1UL : 0UL);
1969  tmp |= CAN_CTRL1_PN_WUMF_MSK(pnConfig->wakeUpMatch ? 1UL : 0UL);
1970  tmp |= CAN_CTRL1_PN_NMATCH(pnConfig->numMatches);
1971  tmp |= CAN_CTRL1_PN_FCS(pnConfig->filterComb);
1972  tmp |= CAN_CTRL1_PN_IDFS(pnConfig->idFilterType);
1973  tmp |= CAN_CTRL1_PN_PLFS(pnConfig->payloadFilterType);
1974  base->CTRL1_PN = tmp;
1975 
1976  tmp = base->CTRL2_PN;
1977  tmp &= ~CAN_CTRL2_PN_MATCHTO_MASK;
1978  tmp |= CAN_CTRL2_PN_MATCHTO(pnConfig->matchTimeout);
1979  base->CTRL2_PN = tmp;
1980 
1981  /* Configure ID filtering */
1982  tmp = base->FLT_ID1;
1984  tmp |= CAN_FLT_ID1_FLT_IDE(pnConfig->idFilter1.extendedId ? 1UL : 0UL);
1985  tmp |= CAN_FLT_ID1_FLT_RTR(pnConfig->idFilter1.remoteFrame ? 1UL : 0UL);
1986  if (pnConfig->idFilter1.extendedId)
1987  {
1988  tmp |= CAN_FLT_ID1_FLT_ID1(pnConfig->idFilter1.id);
1989  }
1990  else
1991  {
1992  tmp |= CAN_FLT_ID1_FLT_ID1(pnConfig->idFilter1.id << CAN_ID_STD_SHIFT);
1993  }
1994  base->FLT_ID1 = tmp;
1995 
1996  /* Configure the second ID, if needed (as mask for exact matching or higher limit for range matching) */
1998  {
1999  tmp = base->FLT_ID2_IDMASK;
2001  tmp |= CAN_FLT_ID2_IDMASK_IDE_MSK(pnConfig->idFilter2.extendedId ? 1UL : 0UL);
2002  tmp |= CAN_FLT_ID2_IDMASK_RTR_MSK(pnConfig->idFilter2.remoteFrame ? 1UL : 0UL);
2003  if (pnConfig->idFilter2.extendedId)
2004  {
2006  }
2007  else
2008  {
2010  }
2011  base->FLT_ID2_IDMASK = tmp;
2012  }
2013 
2014  /* Configure payload filtering, if requested */
2016  {
2017  tmp = base->FLT_DLC;
2019  tmp |= CAN_FLT_DLC_FLT_DLC_HI(pnConfig->payloadFilter.dlcHigh);
2020  tmp |= CAN_FLT_DLC_FLT_DLC_LO(pnConfig->payloadFilter.dlcLow);
2021  base->FLT_DLC = tmp;
2022 
2023  tmp = CAN_PL1_HI_Data_byte_4(pnConfig->payloadFilter.payload1[4]);
2024  tmp |= CAN_PL1_HI_Data_byte_5(pnConfig->payloadFilter.payload1[5]);
2025  tmp |= CAN_PL1_HI_Data_byte_6(pnConfig->payloadFilter.payload1[6]);
2026  tmp |= CAN_PL1_HI_Data_byte_7(pnConfig->payloadFilter.payload1[7]);
2027  base->PL1_HI = tmp;
2028 
2029  tmp = CAN_PL1_LO_Data_byte_0(pnConfig->payloadFilter.payload1[0]);
2030  tmp |= CAN_PL1_LO_Data_byte_1(pnConfig->payloadFilter.payload1[1]);
2031  tmp |= CAN_PL1_LO_Data_byte_2(pnConfig->payloadFilter.payload1[2]);
2032  tmp |= CAN_PL1_LO_Data_byte_3(pnConfig->payloadFilter.payload1[3]);
2033  base->PL1_LO = tmp;
2034 
2035  /* Configure the second payload, if needed (as mask for exact matching or higher limit for range matching) */
2037  {
2042  base->PL2_PLMASK_HI = tmp;
2043 
2048  base->PL2_PLMASK_LO = tmp;
2049  }
2050  }
2051 }
2052 
2053 /*FUNCTION**********************************************************************
2054  *
2055  * Function Name : FLEXCAN_HAL_GetWMB
2056  * Description : Extracts one of the frames which triggered the wake up event.
2057  *
2058  * Implements : FLEXCAN_HAL_GetWMB_Activity
2059  *END**************************************************************************/
2060 void FLEXCAN_HAL_GetWMB(const CAN_Type * base, uint8_t wmbIndex, flexcan_msgbuff_t *wmb)
2061 {
2062  DEV_ASSERT(wmb != NULL);
2063 
2064  uint32_t *tmp, wmbData;
2065 
2066  tmp = (uint32_t *)&wmb->data[0];
2067  wmbData = base->WMB[wmbIndex].WMBn_D03;
2068  REV_BYTES_32(wmbData, *tmp);
2069 
2070  tmp = (uint32_t *)&wmb->data[4];
2071  wmbData = base->WMB[wmbIndex].WMBn_D47;
2072  REV_BYTES_32(wmbData, *tmp);
2073 
2074  wmb->cs = base->WMB[wmbIndex].WMBn_CS;
2075 
2076  if ((wmb->cs & CAN_CS_IDE_MASK) != 0U)
2077  {
2078  wmb->msgId = base->WMB[wmbIndex].WMBn_ID;
2079  }
2080  else
2081  {
2082  wmb->msgId = base->WMB[wmbIndex].WMBn_ID >> CAN_ID_STD_SHIFT;
2083  }
2084 
2085  wmb->dataLen = (uint8_t)((wmb->cs & CAN_CS_DLC_MASK) >> 16);
2086 }
2087 
2088 #endif /* FEATURE_CAN_HAS_PRETENDED_NETWORKING */
2089 
2090 /*******************************************************************************
2091  * EOF
2092  ******************************************************************************/
#define CAN_PL1_LO_Data_byte_1(x)
Definition: S32K144.h:1551
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2
Definition: flexcan_hal.c:112
#define CAN_CTRL1_RJW(x)
Definition: S32K144.h:1177
#define CAN_MCR_SRXDIS(x)
Definition: S32K144.h:1076
status_t FLEXCAN_HAL_SetRxFifoDMA(CAN_Type *base, bool enable)
Enables/Disables the DMA support for RxFIFO.
#define CAN_PL2_PLMASK_HI_Data_byte_7(x)
Definition: S32K144.h:1607
void FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX Message Buffer global extended mask.
Definition: flexcan_hal.c:1607
#define CAN_MCR_IRMQ(x)
Definition: S32K144.h:1072
void FLEXCAN_HAL_SetTimeSegmentsCbt(CAN_Type *base, const flexcan_time_segment_t *timeSeg)
Sets the FlexCAN time segments for setting up bit rate for FD BRS.
Definition: flexcan_hal.c:547
void FLEXCAN_HAL_ClearErrIntStatusFlag(CAN_Type *base)
Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup).
Definition: flexcan_hal.c:1337
#define CAN_MB_EDL_MASK
Definition: flexcan_hal.h:295
#define CAN_MCR_FDEN(x)
Definition: S32K144.h:1052
#define CAN_DLC_VALUE_20_BYTES
Definition: flexcan_hal.c:136
#define CAN_CS_SRR_MASK
Definition: flexcan_hal.h:287
#define CAN_FLT_DLC_FLT_DLC_HI(x)
Definition: S32K144.h:1534
#define CAN_MCR_MDIS(x)
Definition: S32K144.h:1116
#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK
Definition: S32K144.h:1574
#define CAN_PL1_HI_Data_byte_7(x)
Definition: S32K144.h:1560
void FLEXCAN_HAL_ConfigPN(CAN_Type *base, const flexcan_pn_config_t *pnConfig)
Configures the Pretended Networking mode.
#define CAN_CTRL2_ISOCANFDEN(x)
Definition: S32K144.h:1358
void FLEXCAN_HAL_SetTimeSegments(CAN_Type *base, const flexcan_time_segment_t *timeSeg)
Sets the FlexCAN time segments for setting up bit rate.
Definition: flexcan_hal.c:493
void FLEXCAN_HAL_GetTimeSegments(const CAN_Type *base, flexcan_time_segment_t *timeSeg)
Gets the FlexCAN time segments to calculate the bit rate.
Definition: flexcan_hal.c:578
void FLEXCAN_HAL_SetTDCOffset(CAN_Type *base, bool enable, uint8_t offset)
Enables/Disables the Transceiver Delay Compensation feature and sets the Transceiver Delay Compensati...
Definition: flexcan_hal.c:1925
void FLEXCAN_HAL_DisableRxFifo(CAN_Type *base)
Disables the Rx FIFO.
Definition: flexcan_hal.c:991
#define CAN_MCR_SOFTRST_SHIFT
Definition: S32K144.h:1094
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT
Definition: flexcan_hal.c:92
static volatile uint32_t * FLEXCAN_HAL_GetMsgBuffRegion(CAN_Type *base, uint32_t msgBuffIdx)
Definition: flexcan_hal.c:180
void FLEXCAN_HAL_ExitFreezeMode(CAN_Type *base)
Un freezes the FlexCAN module.
Definition: flexcan_hal.c:1272
#define CAN_CTRL1_PN_FCS_MASK
Definition: S32K144.h:1475
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1
Definition: flexcan_hal.c:110
void FLEXCAN_HAL_Enable(CAN_Type *base)
Enables FlexCAN controller.
Definition: flexcan_hal.c:386
__IO uint32_t PL2_PLMASK_LO
Definition: S32K144.h:970
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK
Definition: flexcan_hal.c:104
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK
Definition: flexcan_hal.c:114
#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK
Definition: S32K144.h:1582
#define CAN_CTRL2_PN_MATCHTO(x)
Definition: S32K144.h:1503
#define CAN_DLC_VALUE_48_BYTES
Definition: flexcan_hal.c:139
#define FEATURE_CAN0_MAX_MB_NUM
__IO uint32_t RXMGMASK
Definition: S32K144.h:941
#define CAN_FDCBT_FRJW(x)
Definition: S32K144.h:1717
#define CAN_DLC_VALUE_12_BYTES
Definition: flexcan_hal.c:134
#define CAN_CTRL2_PN_MATCHTO_MASK
Definition: S32K144.h:1500
FlexCAN bus error counters Implements : flexcan_buserr_counter_t_Class.
Definition: flexcan_hal.h:167
#define CAN_CTRL1_LPB_MASK
Definition: S32K144.h:1150
#define CAN_CTRL1_PN_IDFS(x)
Definition: S32K144.h:1482
#define CAN_CTRL1_PSEG2_MASK
Definition: S32K144.h:1166
status_t FLEXCAN_HAL_EnableRxFifo(CAN_Type *base, uint32_t numOfFilters)
Enables the Rx FIFO.
Definition: flexcan_hal.c:947
#define CAN_CBT_EPRESDIV_MASK
Definition: S32K144.h:1444
#define CAN_FLT_ID2_IDMASK_RTR_MSK(x)
Definition: S32K144.h:1581
__IO uint32_t RAMn[CAN_RAMn_COUNT]
Definition: S32K144.h:958
bool FLEXCAN_HAL_IsFDEnabled(const CAN_Type *base)
Checks if the Flexible Data rate feature is enabled.
Definition: flexcan_hal.c:1790
#define CAN_PL1_LO_Data_byte_3(x)
Definition: S32K144.h:1543
#define CAN_CBT_BTF(x)
Definition: S32K144.h:1451
#define CAN_MCR_WRNEN(x)
Definition: S32K144.h:1084
__IO uint32_t FLT_ID2_IDMASK
Definition: S32K144.h:969
#define CAN_FLT_ID1_FLT_RTR(x)
Definition: S32K144.h:1525
#define CAN_CTRL1_PSEG1(x)
Definition: S32K144.h:1173
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2
Definition: flexcan_hal.c:118
uint8_t FLEXCAN_HAL_GetPayloadSize(const CAN_Type *base)
Gets the payload size of the MBs.
Definition: flexcan_hal.c:1836
#define CAN_MCR_IDAM_MASK
Definition: S32K144.h:1045
__IO uint32_t RX14MASK
Definition: S32K144.h:942
#define CAN_MCR_WRNEN_MASK
Definition: S32K144.h:1081
#define CAN_FDCTRL_FDRATE_MASK
Definition: S32K144.h:1697
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1
Definition: flexcan_hal.c:122
status_t FLEXCAN_HAL_GetMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, flexcan_msgbuff_t *msgBuff)
Gets the FlexCAN message buffer fields.
Definition: flexcan_hal.c:838
status_t FLEXCAN_HAL_SetMsgBuffIntCmd(CAN_Type *base, uint32_t msgBuffIdx, bool enable)
Enables/Disables the FlexCAN Message Buffer interrupt.
Definition: flexcan_hal.c:1210
#define FlexcanSwapBytesInWordIndex(index)
Definition: flexcan_hal.c:167
__IO uint32_t FDCTRL
Definition: S32K144.h:980
void FLEXCAN_HAL_Disable(CAN_Type *base)
Disables FlexCAN controller.
Definition: flexcan_hal.c:408
#define CAN_MCR_IDAM_SHIFT
Definition: S32K144.h:1046
static uint32_t RxFifoOcuppiedLastMsgBuff(uint32_t x)
Definition: flexcan_hal.c:160
#define CAN_CTRL1_PN_IDFS_MASK
Definition: S32K144.h:1479
#define CAN_MCR_MDIS_SHIFT
Definition: S32K144.h:1114
#define CAN_FLT_DLC_FLT_DLC_HI_MASK
Definition: S32K144.h:1531
#define CAN_CBT_ERJW_MASK
Definition: S32K144.h:1440
flexcan_pn_filter_combination_t filterComb
Definition: flexcan_hal.h:249
#define CAN_DLC_VALUE_32_BYTES
Definition: flexcan_hal.c:138
status_t FLEXCAN_HAL_LockRxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx)
Locks the FlexCAN Rx message buffer.
Definition: flexcan_hal.c:918
#define CAN_FDCTRL_TDCEN_MASK
Definition: S32K144.h:1689
#define CAN_CS_IDE_MASK
Definition: flexcan_hal.h:283
#define CAN_MCR_LPMACK_SHIFT
Definition: S32K144.h:1078
uint8_t data[64]
Definition: flexcan_hal.h:191
__IO uint32_t CTRL1
Definition: S32K144.h:938
#define CAN_CTRL1_CLKSRC_MASK
Definition: S32K144.h:1154
#define CAN_CBT_EPRESDIV(x)
Definition: S32K144.h:1447
#define CAN_RX14MASK_RX14M_MASK
Definition: S32K144.h:1193
#define CAN_MCR_FRZ(x)
Definition: S32K144.h:1112
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT
Definition: flexcan_hal.c:102
uint8_t FLEXCAN_HAL_GetMsgBuffIntStatusFlag(const CAN_Type *base, uint32_t msgBuffIdx)
Gets the individual FlexCAN MB interrupt flag.
Definition: flexcan_hal.c:1304
void FLEXCAN_HAL_SetRxFifoGlobalStdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN RX FIFO global standard mask.
Definition: flexcan_hal.c:1434
static uint32_t FLEXCAN_HAL_MaxMbRAMSize(const CAN_Type *base)
Definition: flexcan_hal.c:302
#define CAN_FDCBT_FPROPSEG(x)
Definition: S32K144.h:1713
#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK
Definition: S32K144.h:1578
void FLEXCAN_HAL_EnterFreezeMode(CAN_Type *base)
Freezes the FlexCAN module.
Definition: flexcan_hal.c:1288
#define CAN_MCR_FDEN_SHIFT
Definition: S32K144.h:1050
#define CAN_PL2_PLMASK_HI_Data_byte_4(x)
Definition: S32K144.h:1619
#define CAN_ECR_TXERRCNT_MASK
Definition: S32K144.h:1203
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2
Definition: flexcan_hal.c:124
__IO uint32_t IFLAG1
Definition: S32K144.h:949
#define CAN_FLT_ID1_FLT_IDE(x)
Definition: S32K144.h:1529
#define CAN_CTRL2_ISOCANFDEN_MASK
Definition: S32K144.h:1355
#define CAN_CTRL2_RFFN_MASK
Definition: S32K144.h:1383
#define CAN_FDCBT_FPSEG1(x)
Definition: S32K144.h:1709
#define CAN0
Definition: S32K144.h:993
#define CAN_PL1_LO_Data_byte_0(x)
Definition: S32K144.h:1555
void FLEXCAN_HAL_SetSelfReception(CAN_Type *base, bool enable)
Enables/Disables the Self Reception feature.
Definition: flexcan_hal.c:1882
#define CAN_CTRL1_PSEG2_SHIFT
Definition: S32K144.h:1167
__IO uint32_t MCR
Definition: S32K144.h:937
#define CAN_FLT_ID2_IDMASK_IDE_MSK(x)
Definition: S32K144.h:1585
#define CAN_CTRL1_PN_PLFS(x)
Definition: S32K144.h:1486
#define CAN_FDCBT_FPRESDIV(x)
Definition: S32K144.h:1721
#define CAN_CTRL1_PN_WTOF_MSK_MASK
Definition: S32K144.h:1495
#define REV_BYTES_32(a, b)
Reverse byte order in a word.
Definition: s32_core_cm4.h:112
#define CAN_RX15MASK_RX15M_MASK
Definition: S32K144.h:1198
#define CAN_FLT_ID1_FLT_IDE_MASK
Definition: S32K144.h:1526
#define CAN_MCR_RFEN_MASK
Definition: S32K144.h:1105
#define CAN_ID_STD_SHIFT
Definition: flexcan_hal.h:264
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT
Definition: flexcan_hal.c:94
#define CAN_FDCBT_FRJW_MASK
Definition: S32K144.h:1714
void FLEXCAN_HAL_SetErrIntCmd(CAN_Type *base, flexcan_int_type_t errType, bool enable)
Enables error interrupt of the FlexCAN module.
Definition: flexcan_hal.c:1247
#define CAN_CTRL1_LOM(x)
Definition: S32K144.h:1125
flexcan_int_type_t
FlexCAN error interrupt types Implements : flexcan_int_type_t_Class.
Definition: flexcan_hal.h:157
#define CAN_CBT_EPSEG1(x)
Definition: S32K144.h:1435
__I uint32_t WMBn_CS
Definition: S32K144.h:974
#define CAN_DLC_VALUE_24_BYTES
Definition: flexcan_hal.c:137
#define CAN_PL2_PLMASK_LO_Data_byte_3(x)
Definition: S32K144.h:1590
#define DEV_ASSERT(x)
Definition: devassert.h:78
flexcan_pn_id_filter_t idFilter2
Definition: flexcan_hal.h:251
#define CAN_CTRL1_PSEG1_SHIFT
Definition: S32K144.h:1171
#define CAN_ECR_RXERRCNT_SHIFT
Definition: S32K144.h:1208
#define CAN_FDCTRL_FDRATE(x)
Definition: S32K144.h:1700
void FLEXCAN_HAL_SetRxMsgBuff15StdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN Rx Message Buffer BUF15 standard mask.
Definition: flexcan_hal.c:1586
#define CAN_MCR_SOFTRST(x)
Definition: S32K144.h:1096
__IO uint32_t CBT
Definition: S32K144.h:956
#define FEATURE_CAN1_MAX_MB_NUM
__I uint32_t WMBn_D03
Definition: S32K144.h:976
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK
Definition: flexcan_hal.c:120
flexcan_pn_payload_filter_t payloadFilter
Definition: flexcan_hal.h:254
#define CAN_MB_BRS_MASK
Definition: flexcan_hal.h:296
__IO uint32_t CTRL2
Definition: S32K144.h:950
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT
Definition: flexcan_hal.c:106
#define CAN2
Definition: S32K144.h:1001
#define CAN_ID_STD_MASK
Definition: flexcan_hal.h:263
#define CAN_PL2_PLMASK_HI_Data_byte_5(x)
Definition: S32K144.h:1615
#define CAN_MCR_DMA(x)
Definition: S32K144.h:1068
__IO uint32_t FLT_DLC
Definition: S32K144.h:966
#define CAN_CTRL1_PN_PLFS_MASK
Definition: S32K144.h:1483
#define CAN_CS_DLC_SHIFT
Definition: flexcan_hal.h:276
void FLEXCAN_HAL_SetOperationMode(CAN_Type *base, flexcan_operation_modes_t mode)
Set operation mode.
Definition: flexcan_hal.c:1671
void FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN Rx Message Buffer global standard mask.
Definition: flexcan_hal.c:1543
#define CAN_CTRL1_PN_FCS(x)
Definition: S32K144.h:1478
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT
Definition: flexcan_hal.c:96
__IO uint32_t CTRL1_PN
Definition: S32K144.h:962
#define CAN_PL2_PLMASK_HI_Data_byte_6(x)
Definition: S32K144.h:1611
FlexCAN timing related structures Implements : flexcan_time_segment_t_Class.
Definition: flexcan_hal.h:198
#define CAN_CBT_EPSEG2_MASK
Definition: S32K144.h:1428
void FLEXCAN_HAL_SetRxMaskType(CAN_Type *base, flexcan_rx_mask_type_t type)
Sets the Rx masking type.
Definition: flexcan_hal.c:1404
#define CAN_FLT_ID1_FLT_ID1_MASK
Definition: S32K144.h:1518
static void FLEXCAN_HAL_ClearRAM(CAN_Type *base)
Definition: flexcan_hal.c:334
#define CAN_CS_DLC_MASK
Definition: flexcan_hal.h:275
#define CAN_MCR_SUPV_MASK
Definition: S32K144.h:1085
#define CAN_CTRL2_RFFN_SHIFT
Definition: S32K144.h:1384
__IO uint32_t PL1_HI
Definition: S32K144.h:968
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:31
#define CAN_FDCTRL_MBDSR0_SHIFT
Definition: S32K144.h:1694
#define CAN_CS_RTR_MASK
Definition: flexcan_hal.h:279
#define CAN1
Definition: S32K144.h:997
#define FLEXCAN_ALL_INT
Definition: flexcan_hal.c:130
flexcan_operation_modes_t
FlexCAN operation modes Implements : flexcan_operation_modes_t_Class.
Definition: flexcan_hal.h:54
#define CAN_CBT_EPROPSEG(x)
Definition: S32K144.h:1439
void FLEXCAN_HAL_SetRxFifoFilter(CAN_Type *base, flexcan_rx_fifo_id_element_format_t idFormat, const flexcan_id_table_t *idFilterTable)
Sets the FlexCAN Rx FIFO fields.
Definition: flexcan_hal.c:1090
#define CAN_MCR_MAXMB_SHIFT
Definition: S32K144.h:1042
#define CAN_CTRL1_PN_NMATCH_MASK
Definition: S32K144.h:1487
#define CAN_CBT_EPSEG2(x)
Definition: S32K144.h:1431
__IO uint32_t RXIMR[CAN_RXIMR_COUNT]
Definition: S32K144.h:960
static bool FLEXCAN_HAL_IsRxFifoEnabled(const CAN_Type *base)
Checks if Rx FIFO is enabled.
Definition: flexcan_hal.h:557
void FLEXCAN_HAL_SetRxFifoFilterNum(CAN_Type *base, uint32_t number)
Sets the number of the Rx FIFO filters.
Definition: flexcan_hal.c:1011
flexcan_rx_fifo_id_element_format_t
ID formats for RxFIFO Implements : flexcan_rx_fifo_id_element_format_t_Class.
Definition: flexcan_hal.h:109
#define CAN_FDCBT_FPROPSEG_MASK
Definition: S32K144.h:1710
void FLEXCAN_HAL_ReadRxFifo(const CAN_Type *base, flexcan_msgbuff_t *rxFifo)
Gets the FlexCAN Rx FIFO data.
Definition: flexcan_hal.c:1358
__IO uint32_t FLT_ID1
Definition: S32K144.h:965
#define CAN_PL1_HI_Data_byte_5(x)
Definition: S32K144.h:1568
#define RxFifoFilterTableOffset
Definition: flexcan_hal.c:142
status_t FLEXCAN_HAL_SetRxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, const flexcan_msgbuff_code_status_t *cs, uint32_t msgId)
Sets the FlexCAN message buffer fields for receiving.
Definition: flexcan_hal.c:752
#define CAN_CTRL1_RJW_SHIFT
Definition: S32K144.h:1175
static uint8_t FLEXCAN_HAL_ComputePayloadSize(uint8_t dlcValue)
Definition: flexcan_hal.c:253
#define CAN_ECR_RXERRCNT_MASK
Definition: S32K144.h:1207
FlexCAN message buffer structure Implements : flexcan_msgbuff_t_Class.
Definition: flexcan_hal.h:188
#define CAN_CTRL1_RJW_MASK
Definition: S32K144.h:1174
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK
Definition: flexcan_hal.c:100
flexcan_msgbuff_id_type_t msgIdType
Definition: flexcan_hal.h:178
#define CAN_CTRL1_PN_NMATCH(x)
Definition: S32K144.h:1490
#define CAN_CTRL1_PROPSEG(x)
Definition: S32K144.h:1121
#define FLEXCAN_ARBITRATION_FIELD_SIZE
Definition: flexcan_hal.c:148
#define FLEXCAN_8_BYTE_PAYLOAD_MB_SIZE
Definition: flexcan_hal.c:147
#define CAN_ECR_TXERRCNT_SHIFT
Definition: S32K144.h:1204
#define CAN_FDCTRL_MBDSR0_MASK
Definition: S32K144.h:1693
#define FlexCanRxFifoAcceptRemoteFrame
Definition: flexcan_hal.c:144
FlexCAN RX FIFO ID filter table structure Implements : flexcan_id_table_t_Class.
Definition: flexcan_hal.h:122
#define CAN_CBT_EPSEG1_MASK
Definition: S32K144.h:1432
#define CAN_MCR_RFEN(x)
Definition: S32K144.h:1108
status_t FLEXCAN_HAL_SetRxIndividualStdMask(CAN_Type *base, uint32_t msgBuffIdx, uint32_t stdMask)
Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO...
Definition: flexcan_hal.c:1476
#define CAN_PL2_PLMASK_LO_Data_byte_2(x)
Definition: S32K144.h:1594
Pretended Networking configuration structure Implements : flexcan_pn_config_t_Class.
Definition: flexcan_hal.h:244
#define CAN_MCR_FRZ_MASK
Definition: S32K144.h:1109
__IO uint32_t CTRL2_PN
Definition: S32K144.h:963
#define CAN_CTRL1_PROPSEG_MASK
Definition: S32K144.h:1118
void FLEXCAN_HAL_Init(CAN_Type *base)
Initializes the FlexCAN controller.
Definition: flexcan_hal.c:450
uint32_t * idFilter
Definition: flexcan_hal.h:125
status_t FLEXCAN_HAL_SetTxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, const flexcan_msgbuff_code_status_t *cs, uint32_t msgId, const uint8_t *msgData)
Sets the FlexCAN message buffer fields for transmitting.
Definition: flexcan_hal.c:603
#define CAN_CTRL1_PRESDIV_MASK
Definition: S32K144.h:1178
#define CAN_DLC_VALUE_16_BYTES
Definition: flexcan_hal.c:135
__IO uint32_t FDCBT
Definition: S32K144.h:981
#define CAN_MCR_HALT_MASK
Definition: S32K144.h:1101
#define CAN_FDCBT_FPSEG2_MASK
Definition: S32K144.h:1702
__I uint32_t WMBn_D47
Definition: S32K144.h:977
#define CAN_PL1_HI_Data_byte_4(x)
Definition: S32K144.h:1572
#define CAN_PL2_PLMASK_LO_Data_byte_1(x)
Definition: S32K144.h:1598
status_t FLEXCAN_HAL_SetMaxMsgBuffNum(CAN_Type *base, uint32_t maxMsgBuffNum)
Sets the maximum number of Message Buffers.
Definition: flexcan_hal.c:1033
#define CAN_MCR_SOFTRST_MASK
Definition: S32K144.h:1093
#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x)
Definition: S32K144.h:1577
#define RxFifoFilterElementNum(x)
Definition: flexcan_hal.c:170
#define CAN_CTRL1_PN_WUMF_MSK_MASK
Definition: S32K144.h:1491
__IO uint32_t IMASK1
Definition: S32K144.h:947
#define CAN_FLT_ID1_FLT_ID1(x)
Definition: S32K144.h:1521
#define CAN_MCR_DMA_MASK
Definition: S32K144.h:1065
void FLEXCAN_HAL_GetWMB(const CAN_Type *base, uint8_t wmbIndex, flexcan_msgbuff_t *wmb)
Extracts one of the frames which triggered the wake up event.
#define CAN_MCR_LPMACK_MASK
Definition: S32K144.h:1077
#define CAN_CTRL1_CLKSRC(x)
Definition: S32K144.h:1157
struct CAN_Type::@0 WMB[CAN_WMB_COUNT]
void FLEXCAN_HAL_ExitOperationMode(CAN_Type *base, flexcan_operation_modes_t mode)
Exit operation mode.
Definition: flexcan_hal.c:1722
#define CAN_RXIMR_COUNT
Definition: S32K144.h:932
#define CAN_ID_EXT_SHIFT
Definition: flexcan_hal.h:260
__IO uint32_t RX15MASK
Definition: S32K144.h:943
void FLEXCAN_HAL_SelectClock(CAN_Type *base, flexcan_clk_source_t clk)
Selects the clock source for FlexCAN.
static uint8_t FLEXCAN_HAL_ComputeDLCValue(uint8_t payloadSize)
Definition: flexcan_hal.c:200
#define CAN_CTRL1_LPB(x)
Definition: S32K144.h:1153
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4
Definition: flexcan_hal.c:128
flexcan_clk_source_t
FlexCAN clock source Implements : flexcan_clk_source_t_Class.
Definition: flexcan_hal.h:148
__IO uint32_t RXFGMASK
Definition: S32K144.h:954
void FLEXCAN_HAL_SetRxMsgBuff14ExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX Message Buffer BUF14 extended mask.
Definition: flexcan_hal.c:1628
#define CAN_FLT_ID1_FLT_RTR_MASK
Definition: S32K144.h:1522
#define CAN_CBT_EPROPSEG_MASK
Definition: S32K144.h:1436
void FLEXCAN_HAL_SetRxMsgBuff15ExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX MB BUF15 extended mask.
Definition: flexcan_hal.c:1649
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3
Definition: flexcan_hal.c:126
#define CAN_CS_CODE_SHIFT
Definition: flexcan_hal.h:292
#define FlexCanRxFifoAcceptExtFrame
Definition: flexcan_hal.c:145
#define CAN_MCR_IRMQ_MASK
Definition: S32K144.h:1069
#define CAN_FDCTRL_TDCOFF(x)
Definition: S32K144.h:1684
#define CAN_FDCBT_FPSEG1_MASK
Definition: S32K144.h:1706
void FLEXCAN_HAL_SetPayloadSize(CAN_Type *base, flexcan_fd_payload_size_t payloadSize)
Sets the payload size of the MBs.
Definition: flexcan_hal.c:1802
#define CAN_CTRL1_PN_WTOF_MSK(x)
Definition: S32K144.h:1498
#define CAN_ID_EXT_MASK
Definition: flexcan_hal.h:259
void FLEXCAN_HAL_SetStuffBitCount(CAN_Type *base, bool enable)
Enables/Disables the Stuff Bit Count for CAN FD frames.
Definition: flexcan_hal.c:1861
#define CAN_CBT_ERJW(x)
Definition: S32K144.h:1443
flexcan_fd_payload_size_t
FlexCAN payload sizes Implements : flexcan_fd_payload_size_t_Class.
Definition: flexcan_hal.h:99
#define CAN_FDCBT_FPSEG2(x)
Definition: S32K144.h:1705
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1
Definition: flexcan_hal.c:116
#define CAN_RXIMR_MI_MASK
Definition: S32K144.h:1470
#define CAN_MCR_FRZACK_SHIFT
Definition: S32K144.h:1090
#define CAN_PL2_PLMASK_LO_Data_byte_0(x)
Definition: S32K144.h:1602
flexcan_rx_mask_type_t
FlexCAN RX mask type. Implements : flexcan_rx_mask_type_t_Class.
Definition: flexcan_hal.h:131
#define CAN_MCR_SRXDIS_MASK
Definition: S32K144.h:1073
#define CAN_MCR_RFEN_SHIFT
Definition: S32K144.h:1106
#define CAN_CTRL1_LOM_MASK
Definition: S32K144.h:1122
#define CAN_CBT_BTF_MASK
Definition: S32K144.h:1448
#define CAN_MCR_SUPV(x)
Definition: S32K144.h:1088
void FLEXCAN_HAL_GetErrCounter(const CAN_Type *base, flexcan_buserr_counter_t *errCount)
Gets the transmit error counter and receives the error counter.
Definition: flexcan_hal.c:1319
#define CAN_PL1_LO_Data_byte_2(x)
Definition: S32K144.h:1547
#define CAN_CTRL1_PSEG1_MASK
Definition: S32K144.h:1170
#define CAN_CS_CODE_MASK
Definition: flexcan_hal.h:291
void FLEXCAN_HAL_SetRxFifoGlobalExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN Rx FIFO global extended mask.
Definition: flexcan_hal.c:1455
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK
Definition: flexcan_hal.c:108
#define CAN_FDCTRL_TDCOFF_MASK
Definition: S32K144.h:1681
#define CAN_CTRL1_PRESDIV(x)
Definition: S32K144.h:1181
#define FEATURE_CAN2_MAX_MB_NUM
#define CAN_MCR_FDEN_MASK
Definition: S32K144.h:1049
#define CAN_CTRL1_PROPSEG_SHIFT
Definition: S32K144.h:1119
#define CAN_FDCBT_FPRESDIV_MASK
Definition: S32K144.h:1718
#define CAN_MCR_HALT(x)
Definition: S32K144.h:1104
__I uint32_t WMBn_ID
Definition: S32K144.h:975
flexcan_pn_filter_selection_t idFilterType
Definition: flexcan_hal.h:252
flexcan_pn_id_filter_t idFilter1
Definition: flexcan_hal.h:250
#define CAN_MCR_MDIS_MASK
Definition: S32K144.h:1113
#define CAN_PL1_HI_Data_byte_6(x)
Definition: S32K144.h:1564
#define CAN_DLC_VALUE_64_BYTES
Definition: flexcan_hal.c:140
#define CAN_CTRL1_PRESDIV_SHIFT
Definition: S32K144.h:1179
FlexCAN Message Buffer code and status for transmit and receive Implements : flexcan_msgbuff_code_sta...
Definition: flexcan_hal.h:175
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT
Definition: flexcan_hal.c:98
__IO uint32_t PL2_PLMASK_HI
Definition: S32K144.h:971
__IO uint32_t ECR
Definition: S32K144.h:944
#define CAN_RXMGMASK_MG_MASK
Definition: S32K144.h:1188
#define CAN_CTRL1_PSEG2(x)
Definition: S32K144.h:1169
#define CAN_MCR_MAXMB_MASK
Definition: S32K144.h:1041
#define CAN_MCR_FRZACK_MASK
Definition: S32K144.h:1089
#define CAN_RXFGMASK_FGM_MASK
Definition: S32K144.h:1418
#define CAN_FLT_DLC_FLT_DLC_LO(x)
Definition: S32K144.h:1538
flexcan_pn_filter_selection_t payloadFilterType
Definition: flexcan_hal.h:253
#define CAN_CTRL1_PN_WUMF_MSK(x)
Definition: S32K144.h:1494
status_t FLEXCAN_HAL_SetRxIndividualExtMask(CAN_Type *base, uint32_t msgBuffIdx, uint32_t extMask)
Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx Message Buffers and the Rx FI...
Definition: flexcan_hal.c:1510
void FLEXCAN_HAL_SetFDEnabled(CAN_Type *base, bool enable)
Enables/Disables Flexible Data rate (if supported).
Definition: flexcan_hal.c:1771
void FLEXCAN_HAL_SetRxMsgBuff14StdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN RX Message Buffer BUF14 standard mask.
Definition: flexcan_hal.c:1565
__IO uint32_t ESR1
Definition: S32K144.h:945
__IO uint32_t PL1_LO
Definition: S32K144.h:967