S32 SDK
lpi2c_hal.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
58 #if !defined(LPI2C_HAL_H)
59 #define LPI2C_HAL_H
60 
61 #include <stdbool.h>
62 #include "device_registers.h"
63 
71 /*******************************************************************************
72  * Definitions
73  ******************************************************************************/
74 
75 
80 #define LPI2C_HAL_MASTER_DATA_MATCH_INT 0x4000UL
81 #define LPI2C_HAL_MASTER_PIN_LOW_TIMEOUT_INT 0x2000UL
82 #define LPI2C_HAL_MASTER_FIFO_ERROR_INT 0x1000UL
83 #define LPI2C_HAL_MASTER_ARBITRATION_LOST_INT 0x800UL
84 #define LPI2C_HAL_MASTER_NACK_DETECT_INT 0x400UL
85 #define LPI2C_HAL_MASTER_STOP_DETECT_INT 0x200UL
86 #define LPI2C_HAL_MASTER_END_PACKET_INT 0x100UL
87 #define LPI2C_HAL_MASTER_RECEIVE_DATA_INT 0x2UL
88 #define LPI2C_HAL_MASTER_TRANSMIT_DATA_INT 0x1UL
93 #define LPI2C_HAL_SLAVE_SMBUS_ALERT_RESPONSE_INT 0x8000UL
94 #define LPI2C_HAL_SLAVE_GENERAL_CALL_INT 0x4000UL
95 #define LPI2C_HAL_SLAVE_ADDRESS_MATCH_1_INT 0x2000UL
96 #define LPI2C_HAL_SLAVE_ADDRESS_MATCH_0_INT 0x1000UL
97 #define LPI2C_HAL_SLAVE_FIFO_ERROR_INT 0x800UL
98 #define LPI2C_HAL_SLAVE_BIT_ERROR_INT 0x400UL
99 #define LPI2C_HAL_SLAVE_STOP_DETECT_INT 0x200UL
100 #define LPI2C_HAL_SLAVE_REPEATED_START_INT 0x100UL
101 #define LPI2C_HAL_SLAVE_TRANSMIT_ACK_INT 0x8UL
102 #define LPI2C_HAL_SLAVE_ADDRESS_VALID_INT 0x4UL
103 #define LPI2C_HAL_SLAVE_RECEIVE_DATA_INT 0x2UL
104 #define LPI2C_HAL_SLAVE_TRANSMIT_DATA_INT 0x1UL
109 typedef struct
110 {
111  uint8_t majorNumber;
112  uint8_t minorNumber;
113  uint16_t featureNumber;
115 
119 typedef enum
120 {
124 
128 typedef enum
129 {
133 
137 typedef enum
138 {
142 
146 typedef enum
147 {
157 
161 typedef enum
162 {
171 
175 typedef enum
176 {
180 
184 typedef enum
185 {
189 
193 typedef enum
194 {
204 
208 typedef enum
209 {
219 
223 typedef enum
224 {
234 
238 typedef enum
239 {
243 
247 typedef enum
248 {
252 
256 typedef enum
257 {
261 
265 typedef enum
266 {
270 
274 typedef enum
275 {
279 
280 
281 /*******************************************************************************
282  * API
283  ******************************************************************************/
284 
285 #if defined(__cplusplus)
286 extern "C" {
287 #endif
288 
303 static inline void LPI2C_HAL_GetVersion(const LPI2C_Type *baseAddr, lpi2c_version_info_t *versionInfo)
304 {
305  uint32_t tmp = baseAddr->VERID;
306  versionInfo->majorNumber = (uint8_t)((tmp & LPI2C_VERID_MAJOR_MASK) >> LPI2C_VERID_MAJOR_SHIFT);
307  versionInfo->minorNumber = (uint8_t)((tmp & LPI2C_VERID_MINOR_MASK) >> LPI2C_VERID_MINOR_SHIFT);
308  versionInfo->featureNumber = (uint16_t)((tmp & LPI2C_VERID_FEATURE_MASK) >> LPI2C_VERID_FEATURE_SHIFT);
309 }
310 
311 
321 static inline uint16_t LPI2C_HAL_MasterGetRxFIFOSize(const LPI2C_Type *baseAddr)
322 {
323  uint32_t tmp = baseAddr->PARAM;
325  tmp = 1UL << tmp; /* RX FIFO size = 2^MRXFIFO */
326  return (uint16_t)tmp;
327 }
328 
329 
339 static inline uint16_t LPI2C_HAL_MasterGetTxFIFOSize(const LPI2C_Type *baseAddr)
340 {
341  uint32_t tmp = baseAddr->PARAM;
343  tmp = 1UL << tmp; /* TX FIFO size = 2^MTXFIFO */
344  return (uint16_t)tmp;
345 }
346 
347 
356 static inline void LPI2C_HAL_MasterRxFIFOResetCmd(LPI2C_Type *baseAddr)
357 {
358  uint32_t regValue = (uint32_t)baseAddr->MCR;
359  regValue &= (uint32_t)(~(LPI2C_MCR_RRF_MASK));
360  regValue |= LPI2C_MCR_RRF(1u);
361  baseAddr->MCR = (uint32_t)regValue;
362 }
363 
364 
373 static inline void LPI2C_HAL_MasterTxFIFOResetCmd(LPI2C_Type *baseAddr)
374 {
375  uint32_t regValue = (uint32_t)baseAddr->MCR;
376  regValue &= (uint32_t)(~(LPI2C_MCR_RTF_MASK));
377  regValue |= LPI2C_MCR_RTF(1u);
378  baseAddr->MCR = (uint32_t)regValue;
379 }
380 
381 
391 static inline void LPI2C_HAL_MasterSetDebugMode(LPI2C_Type *baseAddr, bool enable)
392 {
393  uint32_t regValue = (uint32_t)baseAddr->MCR;
394  regValue &= (uint32_t)(~(LPI2C_MCR_DBGEN_MASK));
395  regValue |= LPI2C_MCR_DBGEN(enable);
396  baseAddr->MCR = (uint32_t)regValue;
397 }
398 
399 
409 static inline void LPI2C_HAL_MasterSetDozeMode(LPI2C_Type *baseAddr, bool enable)
410 {
411  uint32_t regValue = (uint32_t)baseAddr->MCR;
412  regValue &= (uint32_t)(~(LPI2C_MCR_DOZEN_MASK));
413  regValue |= LPI2C_MCR_DOZEN(enable);
414  baseAddr->MCR = (uint32_t)regValue;
415 }
416 
417 
429 static inline void LPI2C_HAL_MasterSetSoftwareReset(LPI2C_Type *baseAddr, bool enable)
430 {
431  uint32_t regValue = (uint32_t)baseAddr->MCR;
432  regValue &= (uint32_t)(~(LPI2C_MCR_RST_MASK));
433  regValue |= LPI2C_MCR_RST(enable);
434  baseAddr->MCR = (uint32_t)regValue;
435 }
436 
437 
449 static inline void LPI2C_HAL_MasterSetEnable(LPI2C_Type *baseAddr, bool enable)
450 {
451  uint32_t regValue = (uint32_t)baseAddr->MCR;
452  regValue &= (uint32_t)(~(LPI2C_MCR_MEN_MASK));
453  regValue |= LPI2C_MCR_MEN(enable);
454  baseAddr->MCR = (uint32_t)regValue;
455 }
456 
457 
467 static inline bool LPI2C_HAL_MasterGetDebugMode(const LPI2C_Type *baseAddr)
468 {
469  uint32_t regValue = (uint32_t)baseAddr->MCR;
470  regValue = (regValue & LPI2C_MCR_DBGEN_MASK) >> LPI2C_MCR_DBGEN_SHIFT;
471  return (bool)regValue;
472 }
473 
474 
484 static inline bool LPI2C_HAL_MasterGetDozeMode(const LPI2C_Type *baseAddr)
485 {
486  uint32_t regValue = (uint32_t)baseAddr->MCR;
487  regValue = (regValue & LPI2C_MCR_DOZEN_MASK) >> LPI2C_MCR_DOZEN_SHIFT;
488  return (bool)regValue;
489 }
490 
491 
501 static inline bool LPI2C_HAL_MasterGetSoftwareReset(const LPI2C_Type *baseAddr)
502 {
503  uint32_t regValue = (uint32_t)baseAddr->MCR;
504  regValue = (regValue & LPI2C_MCR_RST_MASK) >> LPI2C_MCR_RST_SHIFT;
505  return (bool)regValue;
506 }
507 
508 
518 static inline bool LPI2C_HAL_MasterGetEnable(const LPI2C_Type *baseAddr)
519 {
520  uint32_t regValue = (uint32_t)baseAddr->MCR;
521  regValue = (regValue & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT;
522  return (bool)regValue;
523 }
524 
525 
535 static inline bool LPI2C_HAL_MasterGetBusBusyEvent(const LPI2C_Type *baseAddr)
536 {
537  uint32_t regValue = (uint32_t)baseAddr->MSR;
538  regValue = (regValue & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT;
539  return (bool)regValue;
540 }
541 
542 
553 static inline bool LPI2C_HAL_MasterGetMasterBusyEvent(const LPI2C_Type *baseAddr)
554 {
555  uint32_t regValue = (uint32_t)baseAddr->MSR;
556  regValue = (regValue & LPI2C_MSR_MBF_MASK) >> LPI2C_MSR_MBF_SHIFT;
557  return (bool)regValue;
558 }
559 
560 
572 static inline bool LPI2C_HAL_MasterGetReceiveDataReadyEvent(const LPI2C_Type *baseAddr)
573 {
574  uint32_t regValue = (uint32_t)baseAddr->MSR;
575  regValue = (regValue & LPI2C_MSR_RDF_MASK) >> LPI2C_MSR_RDF_SHIFT;
576  return (bool)regValue;
577 }
578 
579 
591 static inline bool LPI2C_HAL_MasterGetTransmitDataRequestEvent(const LPI2C_Type *baseAddr)
592 {
593  uint32_t regValue = (uint32_t)baseAddr->MSR;
594  regValue = (regValue & LPI2C_MSR_TDF_MASK) >> LPI2C_MSR_TDF_SHIFT;
595  return (bool)regValue;
596 }
597 
598 
611 static inline bool LPI2C_HAL_MasterGetDataMatchEvent(const LPI2C_Type *baseAddr)
612 {
613  uint32_t regValue = (uint32_t)baseAddr->MSR;
614  regValue = (regValue & LPI2C_MSR_DMF_MASK) >> LPI2C_MSR_DMF_SHIFT;
615  return (bool)regValue;
616 }
617 
618 
629 static inline bool LPI2C_HAL_MasterGetPinLowTimeoutEvent(const LPI2C_Type *baseAddr)
630 {
631  uint32_t regValue = (uint32_t)baseAddr->MSR;
632  regValue = (regValue & LPI2C_MSR_PLTF_MASK) >> LPI2C_MSR_PLTF_SHIFT;
633  return (bool)regValue;
634 }
635 
636 
650 static inline bool LPI2C_HAL_MasterGetFIFOErrorEvent(const LPI2C_Type *baseAddr)
651 {
652  uint32_t regValue = (uint32_t)baseAddr->MSR;
653  regValue = (regValue & LPI2C_MSR_FEF_MASK) >> LPI2C_MSR_FEF_SHIFT;
654  return (bool)regValue;
655 }
656 
657 
670 static inline bool LPI2C_HAL_MasterGetArbitrationLostEvent(const LPI2C_Type *baseAddr)
671 {
672  uint32_t regValue = (uint32_t)baseAddr->MSR;
673  regValue = (regValue & LPI2C_MSR_ALF_MASK) >> LPI2C_MSR_ALF_SHIFT;
674  return (bool)regValue;
675 }
676 
677 
691 static inline bool LPI2C_HAL_MasterGetNACKDetectEvent(const LPI2C_Type *baseAddr)
692 {
693  uint32_t regValue = (uint32_t)baseAddr->MSR;
694  regValue = (regValue & LPI2C_MSR_NDF_MASK) >> LPI2C_MSR_NDF_SHIFT;
695  return (bool)regValue;
696 }
697 
698 
708 static inline bool LPI2C_HAL_MasterGetSTOPDetectEvent(const LPI2C_Type *baseAddr)
709 {
710  uint32_t regValue = (uint32_t)baseAddr->MSR;
711  regValue = (regValue & LPI2C_MSR_SDF_MASK) >> LPI2C_MSR_SDF_SHIFT;
712  return (bool)regValue;
713 }
714 
715 
727 static inline bool LPI2C_HAL_MasterGetEndPacketEvent(const LPI2C_Type *baseAddr)
728 {
729  uint32_t regValue = (uint32_t)baseAddr->MSR;
730  regValue = (regValue & LPI2C_MSR_EPF_MASK) >> LPI2C_MSR_EPF_SHIFT;
731  return (bool)regValue;
732 }
733 
734 
743 static inline void LPI2C_HAL_MasterClearDataMatchEvent(LPI2C_Type *baseAddr)
744 {
745  baseAddr->MSR = ((uint32_t)1U << LPI2C_MSR_DMF_SHIFT);
746 }
747 
748 
760 {
761  baseAddr->MSR = ((uint32_t)1U << LPI2C_MSR_PLTF_SHIFT);
762 }
763 
764 
774 static inline void LPI2C_HAL_MasterClearFIFOErrorEvent(LPI2C_Type *baseAddr)
775 {
776  baseAddr->MSR = ((uint32_t)1U << LPI2C_MSR_FEF_SHIFT);
777 }
778 
779 
790 {
791  baseAddr->MSR = ((uint32_t)1U << LPI2C_MSR_ALF_SHIFT);
792 }
793 
794 
805 {
806  baseAddr->MSR = ((uint32_t)1U << LPI2C_MSR_NDF_SHIFT);
807 }
808 
809 
819 {
820  baseAddr->MSR = ((uint32_t)1U << LPI2C_MSR_SDF_SHIFT);
821 }
822 
823 
832 static inline void LPI2C_HAL_MasterClearEndPacketEvent(LPI2C_Type *baseAddr)
833 {
834  baseAddr->MSR = ((uint32_t)1U << LPI2C_MSR_EPF_SHIFT);
835 }
836 
837 
848 static inline void LPI2C_HAL_MasterSetRxDMA(LPI2C_Type *baseAddr, bool enable)
849 {
850  uint32_t regValue = (uint32_t)baseAddr->MDER;
851  regValue &= (uint32_t)(~(LPI2C_MDER_RDDE_MASK));
852  regValue |= LPI2C_MDER_RDDE(enable);
853  baseAddr->MDER = (uint32_t)regValue;
854 }
855 
856 
867 static inline void LPI2C_HAL_MasterSetTxDMA(LPI2C_Type *baseAddr, bool enable)
868 {
869  uint32_t regValue = (uint32_t)baseAddr->MDER;
870  regValue &= (uint32_t)(~(LPI2C_MDER_TDDE_MASK));
871  regValue |= LPI2C_MDER_TDDE(enable);
872  baseAddr->MDER = (uint32_t)regValue;
873 }
874 
875 
885 static inline bool LPI2C_HAL_MasterGetRxDMA(const LPI2C_Type *baseAddr)
886 {
887  uint32_t regValue = (uint32_t)baseAddr->MDER;
888  regValue = (regValue & LPI2C_MDER_RDDE_MASK) >> LPI2C_MDER_RDDE_SHIFT;
889  return (bool)regValue;
890 }
891 
892 
902 static inline bool LPI2C_HAL_MasterGetTxDMA(const LPI2C_Type *baseAddr)
903 {
904  uint32_t regValue = (uint32_t)baseAddr->MDER;
905  regValue = (regValue & LPI2C_MDER_TDDE_MASK) >> LPI2C_MDER_TDDE_SHIFT;
906  return (bool)regValue;
907 }
908 
909 
931 static inline void LPI2C_HAL_MasterSetInt(LPI2C_Type *baseAddr, uint32_t interrupts, bool enable)
932 {
933  uint32_t tmp = baseAddr->MIER;
934 
935  if (enable == true)
936  {
937  tmp |= interrupts;
938  }
939  else
940  {
941  tmp &= ~interrupts;
942  }
943  baseAddr->MIER = tmp;
944 }
945 
946 
968 static inline bool LPI2C_HAL_MasterGetInt(const LPI2C_Type *baseAddr, uint32_t interrupts)
969 {
970  uint32_t tmp = baseAddr->MIER;
971  bool hasInterrupts = false;
972 
973  if ((tmp & interrupts) != (uint32_t)0U)
974  {
975  hasInterrupts = true;
976  }
977 
978  return hasInterrupts;
979 }
980 
981 
994 static inline void LPI2C_HAL_MasterSetRxDataMatch(LPI2C_Type *baseAddr, lpi2c_rx_data_match_t rxDataMatch)
995 {
996  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
997  regValue &= (uint32_t)(~(LPI2C_MCFGR0_RDMO_MASK));
998  regValue |= LPI2C_MCFGR0_RDMO(rxDataMatch);
999  baseAddr->MCFGR0 = (uint32_t)regValue;
1000 }
1001 
1002 
1014 {
1015  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1016  regValue = (regValue & LPI2C_MCFGR0_RDMO_MASK) >> LPI2C_MCFGR0_RDMO_SHIFT;
1017  return (lpi2c_rx_data_match_t)regValue;
1018 }
1019 
1020 
1036 static inline void LPI2C_HAL_MasterSetCircularFIFO(LPI2C_Type *baseAddr, bool enable)
1037 {
1038  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1039  regValue &= (uint32_t)(~(LPI2C_MCFGR0_CIRFIFO_MASK));
1040  regValue |= LPI2C_MCFGR0_CIRFIFO(enable);
1041  baseAddr->MCFGR0 = (uint32_t)regValue;
1042 }
1043 
1044 
1054 static inline bool LPI2C_HAL_MasterGetCircularFIFO(const LPI2C_Type *baseAddr)
1055 {
1056  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1057  regValue = (regValue & LPI2C_MCFGR0_CIRFIFO_MASK) >> LPI2C_MCFGR0_CIRFIFO_SHIFT;
1058  return (bool)regValue;
1059 }
1060 
1061 
1071 static inline void LPI2C_HAL_MasterSetHreqSelect(LPI2C_Type *baseAddr, lpi2c_hreq_source_t source)
1072 {
1073  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1074  regValue &= (uint32_t)(~(LPI2C_MCFGR0_HRSEL_MASK));
1075  regValue |= LPI2C_MCFGR0_HRSEL(source);
1076  baseAddr->MCFGR0 = (uint32_t)regValue;
1077 }
1078 
1079 
1090 {
1091  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1092  regValue &= (uint32_t)(~(LPI2C_MCFGR0_HRPOL_MASK));
1093  regValue |= LPI2C_MCFGR0_HRPOL(polarity);
1094  baseAddr->MCFGR0 = (uint32_t)regValue;
1095 }
1096 
1097 
1109 static inline void LPI2C_HAL_MasterSetHreqEnable(LPI2C_Type *baseAddr, bool enable)
1110 {
1111  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1112  regValue &= (uint32_t)(~(LPI2C_MCFGR0_HREN_MASK));
1113  regValue |= LPI2C_MCFGR0_HREN(enable);
1114  baseAddr->MCFGR0 = (uint32_t)regValue;
1115 }
1116 
1117 
1128 {
1129  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1130  regValue = (regValue & LPI2C_MCFGR0_HRSEL_MASK) >> LPI2C_MCFGR0_HRSEL_SHIFT;
1131  return (lpi2c_hreq_source_t)regValue;
1132 }
1133 
1134 
1145 {
1146  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1147  regValue = (regValue & LPI2C_MCFGR0_HRPOL_MASK) >> LPI2C_MCFGR0_HRPOL_SHIFT;
1148  return (lpi2c_hreq_polarity_t)regValue;
1149 }
1150 
1151 
1161 static inline bool LPI2C_HAL_MasterGetHreqEnable(const LPI2C_Type *baseAddr)
1162 {
1163  uint32_t regValue = (uint32_t)baseAddr->MCFGR0;
1164  regValue = (regValue & LPI2C_MCFGR0_HREN_MASK) >> LPI2C_MCFGR0_HREN_SHIFT;
1165  return (bool)regValue;
1166 }
1167 
1168 
1179 static inline void LPI2C_HAL_MasterSetPinConfig(LPI2C_Type *baseAddr, lpi2c_pin_config_t configuration)
1180 {
1181  uint32_t tmp = baseAddr->MCFGR1;
1182  tmp &= ~(LPI2C_MCFGR1_PINCFG_MASK);
1183  tmp |= LPI2C_MCFGR1_PINCFG(configuration);
1184  baseAddr->MCFGR1 = tmp;
1185 }
1186 
1187 
1198 {
1199  uint32_t tmp = baseAddr->MCFGR1;
1201  return (lpi2c_pin_config_t)tmp;
1202 }
1203 
1204 
1216 static inline void LPI2C_HAL_MasterSetMatchConfig(LPI2C_Type *baseAddr, lpi2c_match_config_t configuration)
1217 {
1218  uint32_t tmp = baseAddr->MCFGR1;
1219  tmp &= ~(LPI2C_MCFGR1_MATCFG_MASK);
1220  tmp |= LPI2C_MCFGR1_MATCFG(configuration);
1221  baseAddr->MCFGR1 = tmp;
1222 }
1223 
1224 
1235 {
1236  uint32_t tmp = baseAddr->MCFGR1;
1238  return (lpi2c_match_config_t)tmp;
1239 }
1240 
1241 
1252 static inline void LPI2C_HAL_MasterSetTimeoutConfig(LPI2C_Type *baseAddr, lpi2c_timeout_config_t configuration)
1253 {
1254  uint32_t regValue = (uint32_t)baseAddr->MCFGR1;
1255  regValue &= (uint32_t)(~(LPI2C_MCFGR1_TIMECFG_MASK));
1256  regValue |= LPI2C_MCFGR1_TIMECFG(configuration);
1257  baseAddr->MCFGR1 = (uint32_t)regValue;
1258 }
1259 
1260 
1271 {
1272  uint32_t regValue = (uint32_t)baseAddr->MCFGR1;
1273  regValue = (regValue & LPI2C_MCFGR1_TIMECFG_MASK) >> LPI2C_MCFGR1_TIMECFG_SHIFT;
1274  return (lpi2c_timeout_config_t)regValue;
1275 }
1276 
1277 
1289 static inline void LPI2C_HAL_MasterSetNACKConfig(LPI2C_Type *baseAddr, lpi2c_nack_config_t configuration)
1290 {
1291  uint32_t regValue = (uint32_t)baseAddr->MCFGR1;
1292  regValue &= (uint32_t)(~(LPI2C_MCFGR1_IGNACK_MASK));
1293  regValue |= LPI2C_MCFGR1_IGNACK(configuration);
1294  baseAddr->MCFGR1 = (uint32_t)regValue;
1295 }
1296 
1297 
1308 {
1309  uint32_t regValue = (uint32_t)baseAddr->MCFGR1;
1310  regValue = (regValue & LPI2C_MCFGR1_IGNACK_MASK) >> LPI2C_MCFGR1_IGNACK_SHIFT;
1311  return (lpi2c_nack_config_t)regValue;
1312 }
1313 
1314 
1326 static inline void LPI2C_HAL_MasterSetAutoStopConfig(LPI2C_Type *baseAddr, bool enable)
1327 {
1328  uint32_t regValue = (uint32_t)baseAddr->MCFGR1;
1329  regValue &= (uint32_t)(~(LPI2C_MCFGR1_AUTOSTOP_MASK));
1330  regValue |= LPI2C_MCFGR1_AUTOSTOP(enable);
1331  baseAddr->MCFGR1 = (uint32_t)regValue;
1332 }
1333 
1334 
1345 static inline bool LPI2C_HAL_MasterGetAutoStopConfig(const LPI2C_Type *baseAddr)
1346 {
1347  uint32_t regValue = (uint32_t)baseAddr->MCFGR1;
1348  regValue = (regValue & LPI2C_MCFGR1_AUTOSTOP_MASK) >> LPI2C_MCFGR1_AUTOSTOP_SHIFT;
1349  return (bool)regValue;
1350 }
1351 
1352 
1363 static inline void LPI2C_HAL_MasterSetPrescaler(LPI2C_Type *baseAddr, lpi2c_master_prescaler_t prescaler)
1364 {
1365  uint32_t tmp = baseAddr->MCFGR1;
1366  tmp &= ~(LPI2C_MCFGR1_PRESCALE_MASK);
1367  tmp |= LPI2C_MCFGR1_PRESCALE(prescaler);
1368  baseAddr->MCFGR1 = tmp;
1369 }
1370 
1371 
1382 {
1383  uint32_t tmp = baseAddr->MCFGR1;
1385  return (lpi2c_master_prescaler_t)tmp;
1386 }
1387 
1388 
1402 static inline void LPI2C_HAL_MasterSetSDAGlitchFilter(LPI2C_Type *baseAddr, uint8_t cycles)
1403 {
1404  uint32_t tmp = baseAddr->MCFGR2;
1405  tmp &= ~(LPI2C_MCFGR2_FILTSDA_MASK);
1406  tmp |= LPI2C_MCFGR2_FILTSDA(cycles);
1407  baseAddr->MCFGR2 = tmp;
1408 }
1409 
1410 
1420 static inline uint8_t LPI2C_HAL_MasterGetSDAGlitchFilter(const LPI2C_Type *baseAddr)
1421 {
1422  uint32_t tmp = baseAddr->MCFGR2;
1424  return (uint8_t)tmp;
1425 }
1426 
1427 
1441 static inline void LPI2C_HAL_MasterSetSCLGlitchFilter(LPI2C_Type *baseAddr, uint8_t cycles)
1442 {
1443  uint32_t tmp = baseAddr->MCFGR2;
1444  tmp &= ~(LPI2C_MCFGR2_FILTSCL_MASK);
1445  tmp |= LPI2C_MCFGR2_FILTSCL(cycles);
1446  baseAddr->MCFGR2 = tmp;
1447 }
1448 
1449 
1459 static inline uint8_t LPI2C_HAL_MasterGetSCLGlitchFilter(const LPI2C_Type *baseAddr)
1460 {
1461  uint32_t tmp = baseAddr->MCFGR2;
1463  return (uint8_t)tmp;
1464 }
1465 
1466 
1479 static inline void LPI2C_HAL_MasterSetBusIdleTimeout(LPI2C_Type *baseAddr, uint16_t cycles)
1480 {
1481  uint32_t tmp = baseAddr->MCFGR2;
1482  tmp &= ~(LPI2C_MCFGR2_BUSIDLE_MASK);
1483  tmp |= LPI2C_MCFGR2_BUSIDLE(cycles);
1484  baseAddr->MCFGR2 = tmp;
1485 }
1486 
1487 
1497 static inline uint16_t LPI2C_HAL_MasterGetBusIdleTimeout(const LPI2C_Type *baseAddr)
1498 {
1499  uint32_t tmp = baseAddr->MCFGR2;
1501  return (uint16_t)tmp;
1502 }
1503 
1504 
1516 static inline void LPI2C_HAL_MasterSetPinLowTimeout(LPI2C_Type *baseAddr, uint32_t cycles)
1517 {
1518  baseAddr->MCFGR3 = cycles;
1519 }
1520 
1521 
1531 static inline uint32_t LPI2C_HAL_MasterGetPinLowTimeout(const LPI2C_Type *baseAddr)
1532 {
1533  return (uint32_t)(baseAddr->MCFGR3);
1534 }
1535 
1536 
1548 static inline void LPI2C_HAL_MasterSetMatch0(LPI2C_Type *baseAddr, uint8_t value)
1549 {
1550  uint32_t tmp = baseAddr->MDMR;
1551  tmp &= ~(LPI2C_MDMR_MATCH0_MASK);
1552  tmp |= LPI2C_MDMR_MATCH0(value);
1553  baseAddr->MDMR = tmp;
1554 }
1555 
1556 
1566 static inline uint8_t LPI2C_HAL_MasterGetMatch0(const LPI2C_Type *baseAddr)
1567 {
1568  uint32_t tmp = baseAddr->MDMR;
1570  return (uint8_t)tmp;
1571 }
1572 
1573 
1585 static inline void LPI2C_HAL_MasterSetMatch1(LPI2C_Type *baseAddr, uint8_t value)
1586 {
1587  uint32_t tmp = baseAddr->MDMR;
1588  tmp &= ~(LPI2C_MDMR_MATCH1_MASK);
1589  tmp |= LPI2C_MDMR_MATCH1(value);
1590  baseAddr->MDMR = tmp;
1591 }
1592 
1593 
1603 static inline uint8_t LPI2C_HAL_MasterGetMatch1(const LPI2C_Type *baseAddr)
1604 {
1605  uint32_t tmp = baseAddr->MDMR;
1607  return (uint8_t)tmp;
1608 }
1609 
1610 
1621 static inline void LPI2C_HAL_MasterSetDataValidDelay(LPI2C_Type *baseAddr, uint8_t value)
1622 {
1623  uint32_t tmp = baseAddr->MCCR0;
1624  tmp &= ~(LPI2C_MCCR0_DATAVD_MASK);
1625  tmp |= LPI2C_MCCR0_DATAVD(value);
1626  baseAddr->MCCR0 = tmp;
1627 }
1628 
1629 
1639 static inline uint8_t LPI2C_HAL_MasterGetDataValidDelay(const LPI2C_Type *baseAddr)
1640 {
1641  uint32_t tmp = baseAddr->MCCR0;
1643  return (uint8_t)tmp;
1644 }
1645 
1646 
1660 static inline void LPI2C_HAL_MasterSetSetupHoldDelay(LPI2C_Type *baseAddr, uint8_t value)
1661 {
1662  uint32_t tmp = baseAddr->MCCR0;
1663  tmp &= ~(LPI2C_MCCR0_SETHOLD_MASK);
1664  tmp |= LPI2C_MCCR0_SETHOLD(value);
1665  baseAddr->MCCR0 = tmp;
1666 }
1667 
1668 
1679 static inline uint8_t LPI2C_HAL_MasterGetSetupHoldDelay(const LPI2C_Type *baseAddr)
1680 {
1681  uint32_t tmp = baseAddr->MCCR0;
1683  return (uint8_t)tmp;
1684 }
1685 
1686 
1700 static inline void LPI2C_HAL_MasterSetClockHighPeriod(LPI2C_Type *baseAddr, uint8_t value)
1701 {
1702  uint32_t tmp = baseAddr->MCCR0;
1703  tmp &= ~(LPI2C_MCCR0_CLKHI_MASK);
1704  tmp |= LPI2C_MCCR0_CLKHI(value);
1705  baseAddr->MCCR0 = tmp;
1706 }
1707 
1708 
1718 static inline uint8_t LPI2C_HAL_MasterGetClockHighPeriod(const LPI2C_Type *baseAddr)
1719 {
1720  uint32_t tmp = baseAddr->MCCR0;
1722  return (uint8_t)tmp;
1723 }
1724 
1725 
1737 static inline void LPI2C_HAL_MasterSetClockLowPeriod(LPI2C_Type *baseAddr, uint8_t value)
1738 {
1739  uint32_t tmp = baseAddr->MCCR0;
1740  tmp &= ~(LPI2C_MCCR0_CLKLO_MASK);
1741  tmp |= LPI2C_MCCR0_CLKLO(value);
1742  baseAddr->MCCR0 = tmp;
1743 }
1744 
1745 
1755 static inline uint8_t LPI2C_HAL_MasterGetClockLowPeriod(const LPI2C_Type *baseAddr)
1756 {
1757  uint32_t tmp = baseAddr->MCCR0;
1759  return (uint8_t)tmp;
1760 }
1761 
1762 
1775 static inline void LPI2C_HAL_MasterSetDataValidDelayHS(LPI2C_Type *baseAddr, uint8_t value)
1776 {
1777  uint32_t tmp = baseAddr->MCCR1;
1778  tmp &= ~(LPI2C_MCCR1_DATAVD_MASK);
1779  tmp |= LPI2C_MCCR1_DATAVD(value);
1780  baseAddr->MCCR1 = tmp;
1781 }
1782 
1783 
1794 static inline uint8_t LPI2C_HAL_MasterGetDataValidDelayHS(const LPI2C_Type *baseAddr)
1795 {
1796  uint32_t tmp = baseAddr->MCCR1;
1798  return (uint8_t)tmp;
1799 }
1800 
1801 
1816 static inline void LPI2C_HAL_MasterSetSetupHoldDelayHS(LPI2C_Type *baseAddr, uint8_t value)
1817 {
1818  uint32_t tmp = baseAddr->MCCR1;
1819  tmp &= ~(LPI2C_MCCR1_SETHOLD_MASK);
1820  tmp |= LPI2C_MCCR1_SETHOLD(value);
1821  baseAddr->MCCR1 = tmp;
1822 }
1823 
1824 
1835 static inline uint8_t LPI2C_HAL_MasterGetSetupHoldDelayHS(const LPI2C_Type *baseAddr)
1836 {
1837  uint32_t tmp = baseAddr->MCCR1;
1839  return (uint8_t)tmp;
1840 }
1841 
1842 
1857 static inline void LPI2C_HAL_MasterSetClockHighPeriodHS(LPI2C_Type *baseAddr, uint8_t value)
1858 {
1859  uint32_t tmp = baseAddr->MCCR1;
1860  tmp &= ~(LPI2C_MCCR1_CLKHI_MASK);
1861  tmp |= LPI2C_MCCR1_CLKHI(value);
1862  baseAddr->MCCR1 = tmp;
1863 }
1864 
1865 
1876 static inline uint8_t LPI2C_HAL_MasterGetClockHighPeriodHS(const LPI2C_Type *baseAddr)
1877 {
1878  uint32_t tmp = baseAddr->MCCR1;
1880  return (uint8_t)tmp;
1881 }
1882 
1883 
1896 static inline void LPI2C_HAL_MasterSetClockLowPeriodHS(LPI2C_Type *baseAddr, uint8_t value)
1897 {
1898  uint32_t tmp = baseAddr->MCCR1;
1899  tmp &= ~(LPI2C_MCCR1_CLKLO_MASK);
1900  tmp |= LPI2C_MCCR1_CLKLO(value);
1901  baseAddr->MCCR1 = tmp;
1902 }
1903 
1904 
1915 static inline uint8_t LPI2C_HAL_MasterGetClockLowPeriodHS(const LPI2C_Type *baseAddr)
1916 {
1917  uint32_t tmp = baseAddr->MCCR1;
1919  return (uint8_t)tmp;
1920 }
1921 
1922 
1934 static inline void LPI2C_HAL_MasterSetRxFIFOWatermark(LPI2C_Type *baseAddr, uint8_t value)
1935 {
1936  uint32_t tmp = baseAddr->MFCR;
1937  tmp &= ~(LPI2C_MFCR_RXWATER_MASK);
1938  tmp |= LPI2C_MFCR_RXWATER(value);
1939  baseAddr->MFCR = tmp;
1940 }
1941 
1942 
1952 static inline uint8_t LPI2C_HAL_MasterGetRxFIFOWatermark(const LPI2C_Type *baseAddr)
1953 {
1954  uint32_t tmp = baseAddr->MFCR;
1956  return (uint8_t)tmp;
1957 }
1958 
1959 
1971 static inline void LPI2C_HAL_MasterSetTxFIFOWatermark(LPI2C_Type *baseAddr, uint8_t value)
1972 {
1973  uint32_t tmp = baseAddr->MFCR;
1974  tmp &= ~(LPI2C_MFCR_TXWATER_MASK);
1975  tmp |= LPI2C_MFCR_TXWATER(value);
1976  baseAddr->MFCR = tmp;
1977 }
1978 
1979 
1989 static inline uint8_t LPI2C_HAL_MasterGetTxFIFOWatermark(const LPI2C_Type *baseAddr)
1990 {
1991  uint32_t tmp = baseAddr->MFCR;
1993  return (uint8_t)tmp;
1994 }
1995 
1996 
2006 static inline uint8_t LPI2C_HAL_MasterGetRxFIFOCount(const LPI2C_Type *baseAddr)
2007 {
2008  uint32_t tmp = baseAddr->MFSR;
2010  return (uint8_t)tmp;
2011 }
2012 
2013 
2023 static inline uint8_t LPI2C_HAL_MasterGetTxFIFOCount(const LPI2C_Type *baseAddr)
2024 {
2025  uint32_t tmp = baseAddr->MFSR;
2027  return (uint8_t)tmp;
2028 }
2029 
2030 
2042 static inline void LPI2C_HAL_MasterTransmitCmd(LPI2C_Type *baseAddr, lpi2c_master_command_t cmd, uint8_t data)
2043 {
2044  baseAddr->MTDR = ((uint32_t)cmd << 8U) + (uint32_t)data;
2045 }
2046 
2047 
2058 static inline uint8_t LPI2C_HAL_MasterGetRxData(const LPI2C_Type *baseAddr)
2059 {
2060  uint32_t tmp = baseAddr->MRDR;
2062  return (uint8_t)tmp;
2063 }
2064 
2065 
2075 static inline bool LPI2C_HAL_MasterGetRxEmpty(const LPI2C_Type *baseAddr)
2076 {
2077  uint32_t regValue = (uint32_t)baseAddr->MRDR;
2078  regValue = (regValue & LPI2C_MRDR_RXEMPTY_MASK) >> LPI2C_MRDR_RXEMPTY_SHIFT;
2079  return (bool)regValue;
2080 }
2081 
2082 
2092 static inline void LPI2C_HAL_SlaveSetFilterDoze(LPI2C_Type *baseAddr, bool enable)
2093 {
2094  uint32_t regValue = (uint32_t)baseAddr->SCR;
2095  regValue &= (uint32_t)(~(LPI2C_SCR_FILTDZ_MASK));
2096  regValue |= LPI2C_SCR_FILTDZ(enable);
2097  baseAddr->SCR = (uint32_t)regValue;
2098 }
2099 
2100 
2111 static inline bool LPI2C_HAL_SlaveGetFilterDoze(const LPI2C_Type *baseAddr)
2112 {
2113  uint32_t regValue = (uint32_t)baseAddr->SCR;
2114  regValue = (regValue & LPI2C_SCR_FILTDZ_MASK) >> LPI2C_SCR_FILTDZ_SHIFT;
2115  return (bool)regValue;
2116 }
2117 
2118 
2129 static inline void LPI2C_HAL_SlaveSetFilterEnable(LPI2C_Type *baseAddr, bool enable)
2130 {
2131  uint32_t regValue = (uint32_t)baseAddr->SCR;
2132  regValue &= (uint32_t)(~(LPI2C_SCR_FILTEN_MASK));
2133  regValue |= LPI2C_SCR_FILTEN(enable);
2134  baseAddr->SCR = (uint32_t)regValue;
2135 }
2136 
2137 
2147 static inline bool LPI2C_HAL_SlaveGetFilterEnable(const LPI2C_Type *baseAddr)
2148 {
2149  uint32_t regValue = (uint32_t)baseAddr->SCR;
2150  regValue = (regValue & LPI2C_SCR_FILTEN_MASK) >> LPI2C_SCR_FILTEN_SHIFT;
2151  return (bool)regValue;
2152 }
2153 
2154 
2165 static inline void LPI2C_HAL_SlaveSetSoftwareReset(LPI2C_Type *baseAddr, bool enable)
2166 {
2167  uint32_t regValue = (uint32_t)baseAddr->SCR;
2168  regValue &= (uint32_t)(~(LPI2C_SCR_RST_MASK));
2169  regValue |= LPI2C_SCR_RST(enable);
2170  baseAddr->SCR = (uint32_t)regValue;
2171 }
2172 
2173 
2183 static inline bool LPI2C_HAL_SlaveGetSoftwareReset(const LPI2C_Type *baseAddr)
2184 {
2185  uint32_t regValue = (uint32_t)baseAddr->SCR;
2186  regValue = (regValue & LPI2C_SCR_RST_MASK) >> LPI2C_SCR_RST_SHIFT;
2187  return (bool)regValue;
2188 }
2189 
2190 
2200 static inline void LPI2C_HAL_SlaveSetEnable(LPI2C_Type *baseAddr, bool enable)
2201 {
2202  uint32_t regValue = (uint32_t)baseAddr->SCR;
2203  regValue &= (uint32_t)(~(LPI2C_SCR_SEN_MASK));
2204  regValue |= LPI2C_SCR_SEN(enable);
2205  baseAddr->SCR = (uint32_t)regValue;
2206 }
2207 
2208 
2218 static inline bool LPI2C_HAL_SlaveGetEnable(const LPI2C_Type *baseAddr)
2219 {
2220  uint32_t regValue = (uint32_t)baseAddr->SCR;
2221  regValue = (regValue & LPI2C_SCR_SEN_MASK) >> LPI2C_SCR_SEN_SHIFT;
2222  return (bool)regValue;
2223 }
2224 
2225 
2235 static inline bool LPI2C_HAL_SlaveGetBusBusyEvent(const LPI2C_Type *baseAddr)
2236 {
2237  uint32_t regValue = (uint32_t)baseAddr->SSR;
2238  regValue = (regValue & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT;
2239  return (bool)regValue;
2240 }
2241 
2242 
2253 static inline bool LPI2C_HAL_SlaveGetSlaveBusyEvent(const LPI2C_Type *baseAddr)
2254 {
2255  uint32_t regValue = (uint32_t)baseAddr->SSR;
2256  regValue = (regValue & LPI2C_SSR_SBF_MASK) >> LPI2C_SSR_SBF_SHIFT;
2257  return (bool)regValue;
2258 }
2259 
2260 
2271 static inline bool LPI2C_HAL_SlaveGetSMBusAlertResponseEvent(const LPI2C_Type *baseAddr)
2272 {
2273  uint32_t regValue = (uint32_t)baseAddr->SSR;
2274  regValue = (regValue & LPI2C_SSR_SARF_MASK) >> LPI2C_SSR_SARF_SHIFT;
2275  return (bool)regValue;
2276 }
2277 
2278 
2289 static inline bool LPI2C_HAL_SlaveGetGeneralCallEvent(const LPI2C_Type *baseAddr)
2290 {
2291  uint32_t regValue = (uint32_t)baseAddr->SSR;
2292  regValue = (regValue & LPI2C_SSR_GCF_MASK) >> LPI2C_SSR_GCF_SHIFT;
2293  return (bool)regValue;
2294 }
2295 
2296 
2308 static inline bool LPI2C_HAL_SlaveGetAddressMatch1Event(const LPI2C_Type *baseAddr)
2309 {
2310  uint32_t regValue = (uint32_t)baseAddr->SSR;
2311  regValue = (regValue & LPI2C_SSR_AM1F_MASK) >> LPI2C_SSR_AM1F_SHIFT;
2312  return (bool)regValue;
2313 }
2314 
2315 
2327 static inline bool LPI2C_HAL_SlaveGetAddressMatch0Event(const LPI2C_Type *baseAddr)
2328 {
2329  uint32_t regValue = (uint32_t)baseAddr->SSR;
2330  regValue = (regValue & LPI2C_SSR_AM0F_MASK) >> LPI2C_SSR_AM0F_SHIFT;
2331  return (bool)regValue;
2332 }
2333 
2334 
2345 static inline bool LPI2C_HAL_SlaveGetFIFOErrorEvent(const LPI2C_Type *baseAddr)
2346 {
2347  uint32_t regValue = (uint32_t)baseAddr->SSR;
2348  regValue = (regValue & LPI2C_SSR_FEF_MASK) >> LPI2C_SSR_FEF_SHIFT;
2349  return (bool)regValue;
2350 }
2351 
2352 
2364 static inline bool LPI2C_HAL_SlaveGetBitErrorEvent(const LPI2C_Type *baseAddr)
2365 {
2366  uint32_t regValue = (uint32_t)baseAddr->SSR;
2367  regValue = (regValue & LPI2C_SSR_BEF_MASK) >> LPI2C_SSR_BEF_SHIFT;
2368  return (bool)regValue;
2369 }
2370 
2371 
2382 static inline bool LPI2C_HAL_SlaveGetSTOPDetectEvent(const LPI2C_Type *baseAddr)
2383 {
2384  uint32_t regValue = (uint32_t)baseAddr->SSR;
2385  regValue = (regValue & LPI2C_SSR_SDF_MASK) >> LPI2C_SSR_SDF_SHIFT;
2386  return (bool)regValue;
2387 }
2388 
2389 
2401 static inline bool LPI2C_HAL_SlaveGetRepeatedStartEvent(const LPI2C_Type *baseAddr)
2402 {
2403  uint32_t regValue = (uint32_t)baseAddr->SSR;
2404  regValue = (regValue & LPI2C_SSR_RSF_MASK) >> LPI2C_SSR_RSF_SHIFT;
2405  return (bool)regValue;
2406 }
2407 
2408 
2420 static inline bool LPI2C_HAL_SlaveGetTransmitACKEvent(const LPI2C_Type *baseAddr)
2421 {
2422  uint32_t regValue = (uint32_t)baseAddr->SSR;
2423  regValue = (regValue & LPI2C_SSR_TAF_MASK) >> LPI2C_SSR_TAF_SHIFT;
2424  return (bool)regValue;
2425 }
2426 
2427 
2441 static inline bool LPI2C_HAL_SlaveGetAddressValidEvent(const LPI2C_Type *baseAddr)
2442 {
2443  uint32_t regValue = (uint32_t)baseAddr->SSR;
2444  regValue = (regValue & LPI2C_SSR_AVF_MASK) >> LPI2C_SSR_AVF_SHIFT;
2445  return (bool)regValue;
2446 }
2447 
2448 
2462 static inline bool LPI2C_HAL_SlaveGetReceiveDataEvent(const LPI2C_Type *baseAddr)
2463 {
2464  uint32_t regValue = (uint32_t)baseAddr->SSR;
2465  regValue = (regValue & LPI2C_SSR_RDF_MASK) >> LPI2C_SSR_RDF_SHIFT;
2466  return (bool)regValue;
2467 }
2468 
2469 
2483 static inline bool LPI2C_HAL_SlaveGetTransmitDataEvent(const LPI2C_Type *baseAddr)
2484 {
2485  uint32_t regValue = (uint32_t)baseAddr->SSR;
2486  regValue = (regValue & LPI2C_SSR_TDF_MASK) >> LPI2C_SSR_TDF_SHIFT;
2487  return (bool)regValue;
2488 }
2489 
2490 
2499 static inline void LPI2C_HAL_SlaveClearFIFOErrorEvent(LPI2C_Type *baseAddr)
2500 {
2501  baseAddr->SSR = ((uint32_t)1U << LPI2C_SSR_FEF_SHIFT);
2502 }
2503 
2504 
2513 static inline void LPI2C_HAL_SlaveClearBitErrorEvent(LPI2C_Type *baseAddr)
2514 {
2515  baseAddr->SSR = ((uint32_t)1U << LPI2C_SSR_BEF_SHIFT);
2516 }
2517 
2518 
2528 {
2529  baseAddr->SSR = ((uint32_t)1U << LPI2C_SSR_SDF_SHIFT);
2530 }
2531 
2532 
2542 {
2543  baseAddr->SSR = ((uint32_t)1U << LPI2C_SSR_RSF_SHIFT);
2544 }
2545 
2546 
2571 static inline void LPI2C_HAL_SlaveSetInt(LPI2C_Type *baseAddr, uint32_t interrupts, bool enable)
2572 {
2573  uint32_t tmp = baseAddr->SIER;
2574 
2575  if (enable == true)
2576  {
2577  tmp |= interrupts;
2578  }
2579  else
2580  {
2581  tmp &= ~interrupts;
2582  }
2583  baseAddr->SIER = tmp;
2584 }
2585 
2586 
2611 static inline bool LPI2C_HAL_SlaveGetInt(const LPI2C_Type *baseAddr, uint32_t interrupts)
2612 {
2613  uint32_t tmp = baseAddr->SIER;
2614  bool hasInterrupts = false;
2615 
2616  if ((tmp & interrupts) != (uint32_t)0U)
2617  {
2618  hasInterrupts = true;
2619  }
2620 
2621  return hasInterrupts;
2622 }
2623 
2624 
2637 static inline void LPI2C_HAL_SlaveSetAddrDMA(LPI2C_Type *baseAddr, bool enable)
2638 {
2639  uint32_t regValue = (uint32_t)baseAddr->SDER;
2640  regValue &= (uint32_t)(~(LPI2C_SDER_AVDE_MASK));
2641  regValue |= LPI2C_SDER_AVDE(enable);
2642  baseAddr->SDER = (uint32_t)regValue;
2643 }
2644 
2645 
2656 static inline void LPI2C_HAL_SlaveSetRxDMA(LPI2C_Type *baseAddr, bool enable)
2657 {
2658  uint32_t regValue = (uint32_t)baseAddr->SDER;
2659  regValue &= (uint32_t)(~(LPI2C_SDER_RDDE_MASK));
2660  regValue |= LPI2C_SDER_RDDE(enable);
2661  baseAddr->SDER = (uint32_t)regValue;
2662 }
2663 
2664 
2675 static inline void LPI2C_HAL_SlaveSetTxDMA(LPI2C_Type *baseAddr, bool enable)
2676 {
2677  uint32_t regValue = (uint32_t)baseAddr->SDER;
2678  regValue &= (uint32_t)(~(LPI2C_SDER_TDDE_MASK));
2679  regValue |= LPI2C_SDER_TDDE(enable);
2680  baseAddr->SDER = (uint32_t)regValue;
2681 }
2682 
2683 
2693 static inline bool LPI2C_HAL_SlaveGetAddrDMA(const LPI2C_Type *baseAddr)
2694 {
2695  uint32_t regValue = (uint32_t)baseAddr->SDER;
2696  regValue = (regValue & LPI2C_SDER_AVDE_MASK) >> LPI2C_SDER_AVDE_SHIFT;
2697  return (bool)regValue;
2698 }
2699 
2700 
2710 static inline bool LPI2C_HAL_SlaveGetRxDMA(const LPI2C_Type *baseAddr)
2711 {
2712  uint32_t regValue = (uint32_t)baseAddr->SDER;
2713  regValue = (regValue & LPI2C_SDER_RDDE_MASK) >> LPI2C_SDER_RDDE_SHIFT;
2714  return (bool)regValue;
2715 }
2716 
2717 
2727 static inline bool LPI2C_HAL_SlaveGetTxDMA(const LPI2C_Type *baseAddr)
2728 {
2729  uint32_t regValue = (uint32_t)baseAddr->SDER;
2730  regValue = (regValue & LPI2C_SDER_TDDE_MASK) >> LPI2C_SDER_TDDE_SHIFT;
2731  return (bool)regValue;
2732 }
2733 
2734 
2745 static inline void LPI2C_HAL_SlaveSetAddrConfig(LPI2C_Type *baseAddr, lpi2c_slave_addr_config_t configuration)
2746 {
2747  uint32_t tmp = baseAddr->SCFGR1;
2748  tmp &= ~(LPI2C_SCFGR1_ADDRCFG_MASK);
2749  tmp |= LPI2C_SCFGR1_ADDRCFG(configuration);
2750  baseAddr->SCFGR1 = tmp;
2751 }
2752 
2753 
2764 {
2765  uint32_t tmp = baseAddr->SCFGR1;
2767  return (lpi2c_slave_addr_config_t)tmp;
2768 }
2769 
2770 
2783 static inline void LPI2C_HAL_SlaveSetHighSpeedModeDetect(LPI2C_Type *baseAddr, bool enable)
2784 {
2785  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2786  regValue &= (uint32_t)(~(LPI2C_SCFGR1_HSMEN_MASK));
2787  regValue |= LPI2C_SCFGR1_HSMEN(enable);
2788  baseAddr->SCFGR1 = (uint32_t)regValue;
2789 }
2790 
2791 
2801 static inline bool LPI2C_HAL_SlaveGetHighSpeedModeDetect(const LPI2C_Type *baseAddr)
2802 {
2803  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2804  regValue = (regValue & LPI2C_SCFGR1_HSMEN_MASK) >> LPI2C_SCFGR1_HSMEN_SHIFT;
2805  return (bool)regValue;
2806 }
2807 
2808 
2820 static inline void LPI2C_HAL_SlaveSetIgnoreNACK(LPI2C_Type *baseAddr, lpi2c_slave_nack_config_t nack_config)
2821 {
2822  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2823  regValue &= (uint32_t)(~(LPI2C_SCFGR1_IGNACK_MASK));
2824  regValue |= LPI2C_SCFGR1_IGNACK(nack_config);
2825  baseAddr->SCFGR1 = (uint32_t)regValue;
2826 }
2827 
2828 
2839 {
2840  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2841  regValue = (regValue & LPI2C_SCFGR1_IGNACK_MASK) >> LPI2C_SCFGR1_IGNACK_SHIFT;
2842  return (lpi2c_slave_nack_config_t)regValue;
2843 }
2844 
2845 
2859 static inline void LPI2C_HAL_SlaveSetRxDataConfig(LPI2C_Type *baseAddr, lpi2c_slave_rxdata_config_t configuration)
2860 {
2861  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2862  regValue &= (uint32_t)(~(LPI2C_SCFGR1_RXCFG_MASK));
2863  regValue |= LPI2C_SCFGR1_RXCFG(configuration);
2864  baseAddr->SCFGR1 = (uint32_t)regValue;
2865 }
2866 
2867 
2878 {
2879  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2880  regValue = (regValue & LPI2C_SCFGR1_RXCFG_MASK) >> LPI2C_SCFGR1_RXCFG_SHIFT;
2881  return (lpi2c_slave_rxdata_config_t)regValue;
2882 }
2883 
2884 
2901 static inline void LPI2C_HAL_SlaveSetTxFlagConfig(LPI2C_Type *baseAddr, lpi2c_slave_txflag_config_t configuration)
2902 {
2903  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2904  regValue &= (uint32_t)(~(LPI2C_SCFGR1_TXCFG_MASK));
2905  regValue |= LPI2C_SCFGR1_TXCFG(configuration);
2906  baseAddr->SCFGR1 = (uint32_t)regValue;
2907 }
2908 
2909 
2920 {
2921  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2922  regValue = (regValue & LPI2C_SCFGR1_TXCFG_MASK) >> LPI2C_SCFGR1_TXCFG_SHIFT;
2923  return (lpi2c_slave_txflag_config_t)regValue;
2924 }
2925 
2926 
2936 static inline void LPI2C_HAL_SlaveSetSMBusAlert(LPI2C_Type *baseAddr, bool enable)
2937 {
2938  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2939  regValue &= (uint32_t)(~(LPI2C_SCFGR1_SAEN_MASK));
2940  regValue |= LPI2C_SCFGR1_SAEN(enable);
2941  baseAddr->SCFGR1 = (uint32_t)regValue;
2942 }
2943 
2944 
2954 static inline bool LPI2C_HAL_SlaveGetSMBusAlert(const LPI2C_Type *baseAddr)
2955 {
2956  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2957  regValue = (regValue & LPI2C_SCFGR1_SAEN_MASK) >> LPI2C_SCFGR1_SAEN_SHIFT;
2958  return (bool)regValue;
2959 }
2960 
2961 
2971 static inline void LPI2C_HAL_SlaveSetGeneralCall(LPI2C_Type *baseAddr, bool enable)
2972 {
2973  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2974  regValue &= (uint32_t)(~(LPI2C_SCFGR1_GCEN_MASK));
2975  regValue |= LPI2C_SCFGR1_GCEN(enable);
2976  baseAddr->SCFGR1 = (uint32_t)regValue;
2977 }
2978 
2979 
2989 static inline bool LPI2C_HAL_SlaveGetGeneralCall(const LPI2C_Type *baseAddr)
2990 {
2991  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
2992  regValue = (regValue & LPI2C_SCFGR1_GCEN_MASK) >> LPI2C_SCFGR1_GCEN_SHIFT;
2993  return (bool)regValue;
2994 }
2995 
2996 
3009 static inline void LPI2C_HAL_SlaveSetACKStall(LPI2C_Type *baseAddr, bool enable)
3010 {
3011  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
3012  regValue &= (uint32_t)(~(LPI2C_SCFGR1_ACKSTALL_MASK));
3013  regValue |= LPI2C_SCFGR1_ACKSTALL(enable);
3014  baseAddr->SCFGR1 = (uint32_t)regValue;
3015 }
3016 
3017 
3028 static inline bool LPI2C_HAL_SlaveGetACKStall(const LPI2C_Type *baseAddr)
3029 {
3030  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
3031  regValue = (regValue & LPI2C_SCFGR1_ACKSTALL_MASK) >> LPI2C_SCFGR1_ACKSTALL_SHIFT;
3032  return (bool)regValue;
3033 }
3034 
3035 
3047 static inline void LPI2C_HAL_SlaveSetTXDStall(LPI2C_Type *baseAddr, bool enable)
3048 {
3049  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
3050  regValue &= (uint32_t)(~(LPI2C_SCFGR1_TXDSTALL_MASK));
3051  regValue |= LPI2C_SCFGR1_TXDSTALL(enable);
3052  baseAddr->SCFGR1 = (uint32_t)regValue;
3053 }
3054 
3055 
3066 static inline bool LPI2C_HAL_SlaveGetTXDStall(const LPI2C_Type *baseAddr)
3067 {
3068  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
3069  regValue = (regValue & LPI2C_SCFGR1_TXDSTALL_MASK) >> LPI2C_SCFGR1_TXDSTALL_SHIFT;
3070  return (bool)regValue;
3071 }
3072 
3073 
3085 static inline void LPI2C_HAL_SlaveSetRXStall(LPI2C_Type *baseAddr, bool enable)
3086 {
3087  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
3088  regValue &= (uint32_t)(~(LPI2C_SCFGR1_RXSTALL_MASK));
3089  regValue |= LPI2C_SCFGR1_RXSTALL(enable);
3090  baseAddr->SCFGR1 = (uint32_t)regValue;
3091 }
3092 
3093 
3104 static inline bool LPI2C_HAL_SlaveGetRXStall(const LPI2C_Type *baseAddr)
3105 {
3106  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
3107  regValue = (regValue & LPI2C_SCFGR1_RXSTALL_MASK) >> LPI2C_SCFGR1_RXSTALL_SHIFT;
3108  return (bool)regValue;
3109 }
3110 
3111 
3123 static inline void LPI2C_HAL_SlaveSetAddrStall(LPI2C_Type *baseAddr, bool enable)
3124 {
3125  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
3126  regValue &= (uint32_t)(~(LPI2C_SCFGR1_ADRSTALL_MASK));
3127  regValue |= LPI2C_SCFGR1_ADRSTALL(enable);
3128  baseAddr->SCFGR1 = (uint32_t)regValue;
3129 }
3130 
3131 
3142 static inline bool LPI2C_HAL_SlaveGetAddrStall(const LPI2C_Type *baseAddr)
3143 {
3144  uint32_t regValue = (uint32_t)baseAddr->SCFGR1;
3145  regValue = (regValue & LPI2C_SCFGR1_ADRSTALL_MASK) >> LPI2C_SCFGR1_ADRSTALL_SHIFT;
3146  return (bool)regValue;
3147 }
3148 
3149 
3164 static inline void LPI2C_HAL_SlaveSetSDAGlitchFilter(LPI2C_Type *baseAddr, uint8_t cycles)
3165 {
3166  uint32_t tmp = baseAddr->SCFGR2;
3167  tmp &= ~(LPI2C_SCFGR2_FILTSDA_MASK);
3168  tmp |= LPI2C_SCFGR2_FILTSDA(cycles);
3169  baseAddr->SCFGR2 = tmp;
3170 }
3171 
3172 
3182 static inline uint8_t LPI2C_HAL_SlaveGetSDAGlitchFilter(const LPI2C_Type *baseAddr)
3183 {
3184  uint32_t tmp = baseAddr->SCFGR2;
3186  return (uint8_t)tmp;
3187 }
3188 
3189 
3204 static inline void LPI2C_HAL_SlaveSetSCLGlitchFilter(LPI2C_Type *baseAddr, uint8_t cycles)
3205 {
3206  uint32_t tmp = baseAddr->SCFGR2;
3207  tmp &= ~(LPI2C_SCFGR2_FILTSCL_MASK);
3208  tmp |= LPI2C_SCFGR2_FILTSCL(cycles);
3209  baseAddr->SCFGR2 = tmp;
3210 }
3211 
3212 
3222 static inline uint8_t LPI2C_HAL_SlaveGetSCLGlitchFilter(const LPI2C_Type *baseAddr)
3223 {
3224  uint32_t tmp = baseAddr->SCFGR2;
3226  return (uint8_t)tmp;
3227 }
3228 
3229 
3243 static inline void LPI2C_HAL_SlaveSetDataValidDelay(LPI2C_Type *baseAddr, uint8_t cycles)
3244 {
3245  uint32_t tmp = baseAddr->SCFGR2;
3246  tmp &= ~(LPI2C_SCFGR2_DATAVD_MASK);
3247  tmp |= LPI2C_SCFGR2_DATAVD(cycles);
3248  baseAddr->SCFGR2 = tmp;
3249 }
3250 
3251 
3261 static inline uint8_t LPI2C_HAL_SlaveGetDataValidDelay(const LPI2C_Type *baseAddr)
3262 {
3263  uint32_t tmp = baseAddr->SCFGR2;
3265  return (uint8_t)tmp;
3266 }
3267 
3268 
3281 static inline void LPI2C_HAL_SlaveSetClockHoldTime(LPI2C_Type *baseAddr, uint8_t cycles)
3282 {
3283  uint32_t tmp = baseAddr->SCFGR2;
3284  tmp &= ~(LPI2C_SCFGR2_CLKHOLD_MASK);
3285  tmp |= LPI2C_SCFGR2_CLKHOLD(cycles);
3286  baseAddr->SCFGR2 = tmp;
3287 }
3288 
3289 
3299 static inline uint8_t LPI2C_HAL_SlaveGetClockHoldTime(const LPI2C_Type *baseAddr)
3300 {
3301  uint32_t tmp = baseAddr->SCFGR2;
3303  return (uint8_t)tmp;
3304 }
3305 
3306 
3321 static inline void LPI2C_HAL_SlaveSetAddr1(LPI2C_Type *baseAddr, uint16_t addr)
3322 {
3323  uint32_t tmp = baseAddr->SAMR;
3324  tmp &= ~(LPI2C_SAMR_ADDR1_MASK);
3325  tmp |= LPI2C_SAMR_ADDR1(addr);
3326  baseAddr->SAMR = tmp;
3327 }
3328 
3329 
3339 static inline uint16_t LPI2C_HAL_SlaveGetAddr1(const LPI2C_Type *baseAddr)
3340 {
3341  uint32_t tmp = baseAddr->SAMR;
3343  return (uint16_t)tmp;
3344 }
3345 
3346 
3361 static inline void LPI2C_HAL_SlaveSetAddr0(LPI2C_Type *baseAddr, uint16_t addr)
3362 {
3363  uint32_t tmp = baseAddr->SAMR;
3364  tmp &= ~(LPI2C_SAMR_ADDR0_MASK);
3365  tmp |= LPI2C_SAMR_ADDR0(addr);
3366  baseAddr->SAMR = tmp;
3367 }
3368 
3369 
3379 static inline uint16_t LPI2C_HAL_SlaveGetAddr0(const LPI2C_Type *baseAddr)
3380 {
3381  uint32_t tmp = baseAddr->SAMR;
3383  return (uint16_t)tmp;
3384 }
3385 
3386 
3398 {
3399  uint32_t regValue = (uint32_t)baseAddr->SASR;
3400  regValue = (regValue & LPI2C_SASR_ANV_MASK) >> LPI2C_SASR_ANV_SHIFT;
3401  return (lpi2c_slave_addr_valid_t)regValue;
3402 }
3403 
3404 
3418 static inline uint16_t LPI2C_HAL_SlaveGetReceivedAddr(const LPI2C_Type *baseAddr)
3419 {
3420  uint32_t tmp = baseAddr->SASR;
3422  return (uint16_t)tmp;
3423 }
3424 
3425 
3439 {
3440  uint32_t regValue = (uint32_t)baseAddr->STAR;
3441  regValue &= (uint32_t)(~(LPI2C_STAR_TXNACK_MASK));
3442  regValue |= LPI2C_STAR_TXNACK(nack);
3443  baseAddr->STAR = (uint32_t)regValue;
3444 }
3445 
3446 
3457 {
3458  uint32_t regValue = (uint32_t)baseAddr->STAR;
3459  regValue = (regValue & LPI2C_STAR_TXNACK_MASK) >> LPI2C_STAR_TXNACK_SHIFT;
3460  return (lpi2c_slave_nack_transmit_t)regValue;
3461 }
3462 
3463 
3474 static inline void LPI2C_HAL_SlaveTransmitData(LPI2C_Type *baseAddr, uint8_t data)
3475 {
3476  baseAddr->STDR = (uint32_t)data;
3477 }
3478 
3479 
3490 static inline bool LPI2C_HAL_SlaveGetStartOfFrame(const LPI2C_Type *baseAddr)
3491 {
3492  uint32_t regValue = (uint32_t)baseAddr->SRDR;
3493  regValue = (regValue & LPI2C_SRDR_SOF_MASK) >> LPI2C_SRDR_SOF_SHIFT;
3494  return (bool)regValue;
3495 }
3496 
3497 
3507 static inline bool LPI2C_HAL_SlaveGetRXEmpty(const LPI2C_Type *baseAddr)
3508 {
3509  uint32_t regValue = (uint32_t)baseAddr->SRDR;
3510  regValue = (regValue & LPI2C_SRDR_RXEMPTY_MASK) >> LPI2C_SRDR_RXEMPTY_SHIFT;
3511  return (bool)regValue;
3512 }
3513 
3514 
3525 static inline uint8_t LPI2C_HAL_SlaveGetData(const LPI2C_Type *baseAddr)
3526 {
3527  uint32_t tmp = baseAddr->SRDR;
3529  return (uint8_t)tmp;
3530 }
3531 
3532 
3541 void LPI2C_HAL_Init(LPI2C_Type *baseAddr);
3542 
3545 #if defined(__cplusplus)
3546 }
3547 #endif
3548 
3551 #endif /* __LPI2C_HAL_H__*/
3552 /*******************************************************************************
3553  * EOF
3554  ******************************************************************************/
3555 
#define LPI2C_SCFGR1_ADRSTALL_SHIFT
Definition: S32K144.h:5822
lpi2c_nack_config_t
Master NACK reaction configuration Implements : lpi2c_nack_config_t_Class.
Definition: lpi2c_hal.h:184
#define LPI2C_MCFGR1_IGNACK_MASK
Definition: S32K144.h:5571
__IO uint32_t MCFGR2
Definition: S32K144.h:5338
#define LPI2C_MCR_RST_SHIFT
Definition: S32K144.h:5431
static void LPI2C_HAL_SlaveSetHighSpeedModeDetect(LPI2C_Type *baseAddr, bool enable)
Control detection of the High-speed Mode master code.
Definition: lpi2c_hal.h:2783
#define LPI2C_MCFGR0_HREN_SHIFT
Definition: S32K144.h:5543
static bool LPI2C_HAL_MasterGetHreqEnable(const LPI2C_Type *baseAddr)
Return the enable/disable state the host request feature.
Definition: lpi2c_hal.h:1161
static uint8_t LPI2C_HAL_SlaveGetSCLGlitchFilter(const LPI2C_Type *baseAddr)
Return the LPI2C slave SCL glitch filter configuration.
Definition: lpi2c_hal.h:3222
#define LPI2C_MDER_RDDE_SHIFT
Definition: S32K144.h:5538
#define LPI2C_MCFGR2_FILTSCL(x)
Definition: S32K144.h:5595
static uint8_t LPI2C_HAL_MasterGetClockLowPeriodHS(const LPI2C_Type *baseAddr)
Return the configured minimum clock low period in high-speed mode.
Definition: lpi2c_hal.h:1915
static void LPI2C_HAL_MasterSetCircularFIFO(LPI2C_Type *baseAddr, bool enable)
Set the circular FIFO mode for the transmit FIFO.
Definition: lpi2c_hal.h:1036
#define LPI2C_MDER_RDDE(x)
Definition: S32K144.h:5540
static bool LPI2C_HAL_MasterGetReceiveDataReadyEvent(const LPI2C_Type *baseAddr)
Indicate the availability of receive data.
Definition: lpi2c_hal.h:572
lpi2c_timeout_config_t
SCL/SDA low time-out configuration Implements : lpi2c_timeout_config_t_Class.
Definition: lpi2c_hal.h:175
static void LPI2C_HAL_SlaveClearFIFOErrorEvent(LPI2C_Type *baseAddr)
Clear the FIFO overflow or underflow flag.
Definition: lpi2c_hal.h:2499
#define LPI2C_SRDR_RXEMPTY_MASK
Definition: S32K144.h:5915
#define LPI2C_SRDR_SOF_MASK
Definition: S32K144.h:5919
#define LPI2C_SASR_RADDR_MASK
Definition: S32K144.h:5892
#define LPI2C_SCFGR1_ACKSTALL_MASK
Definition: S32K144.h:5833
#define LPI2C_SCFGR1_RXSTALL(x)
Definition: S32K144.h:5828
#define LPI2C_MCFGR0_CIRFIFO_MASK
Definition: S32K144.h:5554
static void LPI2C_HAL_MasterSetEnable(LPI2C_Type *baseAddr, bool enable)
Enable or disable the LPI2C master.
Definition: lpi2c_hal.h:449
static void LPI2C_HAL_MasterSetSoftwareReset(LPI2C_Type *baseAddr, bool enable)
Set/clear the master reset command.
Definition: lpi2c_hal.h:429
#define LPI2C_MCR_MEN_SHIFT
Definition: S32K144.h:5427
#define LPI2C_MSR_ALF_SHIFT
Definition: S32K144.h:5472
#define LPI2C_MCFGR0_HRSEL_SHIFT
Definition: S32K144.h:5551
static bool LPI2C_HAL_SlaveGetReceiveDataEvent(const LPI2C_Type *baseAddr)
Check the availability of receive data.
Definition: lpi2c_hal.h:2462
#define LPI2C_MRDR_RXEMPTY_SHIFT
Definition: S32K144.h:5681
#define LPI2C_MFSR_RXCOUNT_SHIFT
Definition: S32K144.h:5663
#define LPI2C_SCFGR1_GCEN_SHIFT
Definition: S32K144.h:5838
static bool LPI2C_HAL_SlaveGetStartOfFrame(const LPI2C_Type *baseAddr)
Check if the current received data is the first in the current frame.
Definition: lpi2c_hal.h:3490
#define LPI2C_SASR_ANV_MASK
Definition: S32K144.h:5896
#define LPI2C_MCFGR1_PINCFG_SHIFT
Definition: S32K144.h:5584
static lpi2c_slave_nack_config_t LPI2C_HAL_SlaveGetIgnoreNACK(const LPI2C_Type *baseAddr)
Return the configured slave behaviour when NACK is detected.
Definition: lpi2c_hal.h:2838
static void LPI2C_HAL_MasterSetClockHighPeriodHS(LPI2C_Type *baseAddr, uint8_t value)
Set the minimum clock high period in high-speed mode.
Definition: lpi2c_hal.h:1857
static void LPI2C_HAL_SlaveSetSoftwareReset(LPI2C_Type *baseAddr, bool enable)
Set/clear the slave reset command.
Definition: lpi2c_hal.h:2165
#define LPI2C_SAMR_ADDR0(x)
Definition: S32K144.h:5886
#define LPI2C_MCR_DBGEN_MASK
Definition: S32K144.h:5438
static bool LPI2C_HAL_SlaveGetBitErrorEvent(const LPI2C_Type *baseAddr)
Check the detection of a bit error.
Definition: lpi2c_hal.h:2364
#define LPI2C_SCFGR1_SAEN_MASK
Definition: S32K144.h:5841
static void LPI2C_HAL_MasterSetClockHighPeriod(LPI2C_Type *baseAddr, uint8_t value)
Set the minimum clock high period.
Definition: lpi2c_hal.h:1700
#define LPI2C_SCFGR1_ADRSTALL_MASK
Definition: S32K144.h:5821
static void LPI2C_HAL_MasterSetSetupHoldDelayHS(LPI2C_Type *baseAddr, uint8_t value)
Set the setup and hold time for a START / STOP condition in high-speed mode.
Definition: lpi2c_hal.h:1816
static void LPI2C_HAL_MasterSetHreqSelect(LPI2C_Type *baseAddr, lpi2c_hreq_source_t source)
Set the source of the host request input.
Definition: lpi2c_hal.h:1071
static void LPI2C_HAL_SlaveSetIgnoreNACK(LPI2C_Type *baseAddr, lpi2c_slave_nack_config_t nack_config)
Control slave behaviour when NACK is detected.
Definition: lpi2c_hal.h:2820
#define LPI2C_MSR_RDF_SHIFT
Definition: S32K144.h:5456
static void LPI2C_HAL_MasterClearPinLowTimeoutEvent(LPI2C_Type *baseAddr)
Clear the pin low timeout event flag.
Definition: lpi2c_hal.h:759
#define LPI2C_SSR_SARF_SHIFT
Definition: S32K144.h:5747
#define LPI2C_MCCR0_CLKLO_MASK
Definition: S32K144.h:5615
#define LPI2C_MCFGR0_HRPOL(x)
Definition: S32K144.h:5549
static uint16_t LPI2C_HAL_SlaveGetAddr1(const LPI2C_Type *baseAddr)
Return the ADDR1 address for slave address match.
Definition: lpi2c_hal.h:3339
#define LPI2C_MRDR_DATA_SHIFT
Definition: S32K144.h:5677
static void LPI2C_HAL_SlaveSetGeneralCall(LPI2C_Type *baseAddr, bool enable)
Enable or disable general call address.
Definition: lpi2c_hal.h:2971
#define LPI2C_SRDR_DATA_SHIFT
Definition: S32K144.h:5912
static void LPI2C_HAL_MasterSetTimeoutConfig(LPI2C_Type *baseAddr, lpi2c_timeout_config_t configuration)
Set the timeout configuration of the module.
Definition: lpi2c_hal.h:1252
static uint16_t LPI2C_HAL_MasterGetBusIdleTimeout(const LPI2C_Type *baseAddr)
Return the bus idle timeout configuration.
Definition: lpi2c_hal.h:1497
#define LPI2C_MCR_DBGEN(x)
Definition: S32K144.h:5441
#define LPI2C_SCFGR2_DATAVD(x)
Definition: S32K144.h:5873
static bool LPI2C_HAL_SlaveGetRXEmpty(const LPI2C_Type *baseAddr)
Check if the receive data register is empty.
Definition: lpi2c_hal.h:3507
static bool LPI2C_HAL_MasterGetBusBusyEvent(const LPI2C_Type *baseAddr)
Return the idle/busy state of the I2C bus.
Definition: lpi2c_hal.h:535
__IO uint32_t SCR
Definition: S32K144.h:5353
#define LPI2C_MCFGR0_HREN(x)
Definition: S32K144.h:5545
#define LPI2C_SCFGR1_TXDSTALL_MASK
Definition: S32K144.h:5829
static bool LPI2C_HAL_SlaveGetFilterDoze(const LPI2C_Type *baseAddr)
Return the slave filter configuration in doze mode.
Definition: lpi2c_hal.h:2111
static uint8_t LPI2C_HAL_SlaveGetClockHoldTime(const LPI2C_Type *baseAddr)
Return the minimum clock hold time configuration.
Definition: lpi2c_hal.h:3299
#define LPI2C_MCFGR1_MATCFG(x)
Definition: S32K144.h:5582
static bool LPI2C_HAL_MasterGetAutoStopConfig(const LPI2C_Type *baseAddr)
Return the current setting for automatic generation of STOP condition.
Definition: lpi2c_hal.h:1345
#define LPI2C_MCCR0_DATAVD(x)
Definition: S32K144.h:5630
#define LPI2C_SSR_BEF_MASK
Definition: S32K144.h:5726
__IO uint32_t MCR
Definition: S32K144.h:5332
#define LPI2C_MFSR_TXCOUNT_MASK
Definition: S32K144.h:5658
static lpi2c_master_prescaler_t LPI2C_HAL_MasterGetPrescaler(const LPI2C_Type *baseAddr)
Return the LPI2C master prescaler.
Definition: lpi2c_hal.h:1381
__IO uint32_t MCFGR3
Definition: S32K144.h:5339
#define LPI2C_MCCR0_CLKHI_MASK
Definition: S32K144.h:5619
#define LPI2C_MCCR0_SETHOLD(x)
Definition: S32K144.h:5626
static void LPI2C_HAL_SlaveSetRxDataConfig(LPI2C_Type *baseAddr, lpi2c_slave_rxdata_config_t configuration)
Control the functionality of the receive data register.
Definition: lpi2c_hal.h:2859
#define LPI2C_MCCR0_SETHOLD_MASK
Definition: S32K144.h:5623
lpi2c_slave_nack_transmit_t
Slave ACK transmission options Implements : lpi2c_slave_nack_transmit_t_Class.
Definition: lpi2c_hal.h:274
#define LPI2C_SCFGR1_TXDSTALL(x)
Definition: S32K144.h:5832
static bool LPI2C_HAL_SlaveGetFIFOErrorEvent(const LPI2C_Type *baseAddr)
Check the detection of a FIFO overflow or underflow.
Definition: lpi2c_hal.h:2345
static lpi2c_hreq_polarity_t LPI2C_HAL_MasterGetHreqPolarity(const LPI2C_Type *baseAddr)
Return the polarity of the host request input pin.
Definition: lpi2c_hal.h:1144
__IO uint32_t MFCR
Definition: S32K144.h:5347
static bool LPI2C_HAL_MasterGetSTOPDetectEvent(const LPI2C_Type *baseAddr)
Check the occurrence of a STOP detect event.
Definition: lpi2c_hal.h:708
#define LPI2C_SCFGR2_CLKHOLD_SHIFT
Definition: S32K144.h:5867
__I uint32_t SASR
Definition: S32K144.h:5363
static uint8_t LPI2C_HAL_MasterGetSDAGlitchFilter(const LPI2C_Type *baseAddr)
Return the LPI2C SDA glitch filter configuration.
Definition: lpi2c_hal.h:1420
__IO uint32_t MDER
Definition: S32K144.h:5335
lpi2c_slave_nack_config_t
Slave NACK reaction configuration Implements : lpi2c_slave_nack_config_t_Class.
Definition: lpi2c_hal.h:238
static void LPI2C_HAL_MasterClearDataMatchEvent(LPI2C_Type *baseAddr)
Clear the data match event flag.
Definition: lpi2c_hal.h:743
#define LPI2C_MCFGR2_FILTSDA_MASK
Definition: S32K144.h:5596
__IO uint32_t SIER
Definition: S32K144.h:5355
static void LPI2C_HAL_SlaveSetRxDMA(LPI2C_Type *baseAddr, bool enable)
Enable/disable slave receive data DMA requests.
Definition: lpi2c_hal.h:2656
lpi2c_slave_txflag_config_t
Slave Transmit Data Flag function control Implements : lpi2c_slave_txflag_config_t_Class.
Definition: lpi2c_hal.h:256
#define LPI2C_MCCR0_DATAVD_SHIFT
Definition: S32K144.h:5628
static bool LPI2C_HAL_SlaveGetRXStall(const LPI2C_Type *baseAddr)
Return the configured state for clock stretching for data reception.
Definition: lpi2c_hal.h:3104
#define LPI2C_PARAM_MRXFIFO_MASK
Definition: S32K144.h:5421
#define LPI2C_MSR_EPF_MASK
Definition: S32K144.h:5459
#define LPI2C_SSR_BEF_SHIFT
Definition: S32K144.h:5727
#define LPI2C_MCFGR1_PINCFG(x)
Definition: S32K144.h:5586
static void LPI2C_HAL_MasterClearFIFOErrorEvent(LPI2C_Type *baseAddr)
Clear the FIFO error event flag.
Definition: lpi2c_hal.h:774
#define LPI2C_SSR_GCF_SHIFT
Definition: S32K144.h:5743
static void LPI2C_HAL_SlaveClearBitErrorEvent(LPI2C_Type *baseAddr)
Clear bit error flag.
Definition: lpi2c_hal.h:2513
static uint8_t LPI2C_HAL_MasterGetDataValidDelay(const LPI2C_Type *baseAddr)
Return the configured data hold time for SDA.
Definition: lpi2c_hal.h:1639
#define LPI2C_MCR_DOZEN(x)
Definition: S32K144.h:5437
static void LPI2C_HAL_SlaveSetFilterDoze(LPI2C_Type *baseAddr, bool enable)
Configure the slave filter in doze mode.
Definition: lpi2c_hal.h:2092
#define LPI2C_MCCR1_CLKHI_MASK
Definition: S32K144.h:5636
static uint8_t LPI2C_HAL_MasterGetRxData(const LPI2C_Type *baseAddr)
Return the received data.
Definition: lpi2c_hal.h:2058
lpi2c_rx_data_match_t
Non_matching data discard options Implements : lpi2c_rx_data_match_t_Class.
Definition: lpi2c_hal.h:119
#define LPI2C_SCFGR1_HSMEN_MASK
Definition: S32K144.h:5857
__IO uint32_t MIER
Definition: S32K144.h:5334
#define LPI2C_MSR_NDF_SHIFT
Definition: S32K144.h:5468
static bool LPI2C_HAL_MasterGetEnable(const LPI2C_Type *baseAddr)
Return the enable/disable setting for the LPI2C master.
Definition: lpi2c_hal.h:518
#define LPI2C_SCFGR1_ADDRCFG_SHIFT
Definition: S32K144.h:5862
#define LPI2C_SCR_FILTDZ(x)
Definition: S32K144.h:5700
static uint16_t LPI2C_HAL_SlaveGetAddr0(const LPI2C_Type *baseAddr)
Return the ADDR0 address for slave address match.
Definition: lpi2c_hal.h:3379
#define LPI2C_MSR_SDF_SHIFT
Definition: S32K144.h:5464
#define LPI2C_MCCR0_CLKHI(x)
Definition: S32K144.h:5622
#define LPI2C_MCFGR0_HREN_MASK
Definition: S32K144.h:5542
static void LPI2C_HAL_SlaveSetInt(LPI2C_Type *baseAddr, uint32_t interrupts, bool enable)
Enable or disable specified LPI2C slave interrupts.
Definition: lpi2c_hal.h:2571
#define LPI2C_MRDR_DATA_MASK
Definition: S32K144.h:5676
#define LPI2C_SAMR_ADDR1_MASK
Definition: S32K144.h:5887
#define LPI2C_SSR_AM0F_SHIFT
Definition: S32K144.h:5735
#define LPI2C_MCR_DBGEN_SHIFT
Definition: S32K144.h:5439
static void LPI2C_HAL_MasterSetTxFIFOWatermark(LPI2C_Type *baseAddr, uint8_t value)
Set the transmit FIFO watermark.
Definition: lpi2c_hal.h:1971
static bool LPI2C_HAL_MasterGetCircularFIFO(const LPI2C_Type *baseAddr)
Return the circular FIFO mode for the transmit FIFO.
Definition: lpi2c_hal.h:1054
#define LPI2C_MSR_NDF_MASK
Definition: S32K144.h:5467
#define LPI2C_MCFGR2_FILTSCL_MASK
Definition: S32K144.h:5592
#define LPI2C_VERID_MAJOR_SHIFT
Definition: S32K144.h:5413
static uint8_t LPI2C_HAL_MasterGetClockHighPeriodHS(const LPI2C_Type *baseAddr)
Return the configured minimum clock high period in high-speed mode.
Definition: lpi2c_hal.h:1876
#define LPI2C_MCCR0_SETHOLD_SHIFT
Definition: S32K144.h:5624
static uint32_t LPI2C_HAL_MasterGetPinLowTimeout(const LPI2C_Type *baseAddr)
Return the pin low timeout configuration.
Definition: lpi2c_hal.h:1531
static void LPI2C_HAL_MasterClearEndPacketEvent(LPI2C_Type *baseAddr)
Clear the end packet event flag.
Definition: lpi2c_hal.h:832
static void LPI2C_HAL_MasterSetInt(LPI2C_Type *baseAddr, uint32_t interrupts, bool enable)
Enable or disable specified LPI2C master interrupts.
Definition: lpi2c_hal.h:931
static void LPI2C_HAL_SlaveSetTXDStall(LPI2C_Type *baseAddr, bool enable)
Enable or disable clock stretching for data transmission.
Definition: lpi2c_hal.h:3047
#define LPI2C_MCFGR0_CIRFIFO_SHIFT
Definition: S32K144.h:5555
#define LPI2C_STAR_TXNACK(x)
Definition: S32K144.h:5904
lpi2c_hreq_source_t
Host request input source selection Implements : lpi2c_hreq_source_t_Class.
Definition: lpi2c_hal.h:128
static void LPI2C_HAL_MasterClearArbitrationLostEvent(LPI2C_Type *baseAddr)
Clear the arbitration lost event flag.
Definition: lpi2c_hal.h:789
static void LPI2C_HAL_MasterSetNACKConfig(LPI2C_Type *baseAddr, lpi2c_nack_config_t configuration)
Configure the reaction of the module on NACK reception.
Definition: lpi2c_hal.h:1289
__IO uint32_t MCCR0
Definition: S32K144.h:5343
static uint8_t LPI2C_HAL_MasterGetTxFIFOWatermark(const LPI2C_Type *baseAddr)
Return the configured transmit FIFO watermark.
Definition: lpi2c_hal.h:1989
#define LPI2C_SCR_FILTEN_SHIFT
Definition: S32K144.h:5694
static bool LPI2C_HAL_MasterGetDataMatchEvent(const LPI2C_Type *baseAddr)
Check the occurrence of a data match event.
Definition: lpi2c_hal.h:611
#define LPI2C_MRDR_RXEMPTY_MASK
Definition: S32K144.h:5680
#define LPI2C_MCCR1_CLKLO(x)
Definition: S32K144.h:5635
#define LPI2C_MCCR0_CLKHI_SHIFT
Definition: S32K144.h:5620
static void LPI2C_HAL_MasterSetBusIdleTimeout(LPI2C_Type *baseAddr, uint16_t cycles)
Configure the bus idle timeout.
Definition: lpi2c_hal.h:1479
static bool LPI2C_HAL_MasterGetDozeMode(const LPI2C_Type *baseAddr)
Return the doze mode setting for the LPI2C master.
Definition: lpi2c_hal.h:484
static bool LPI2C_HAL_SlaveGetSMBusAlertResponseEvent(const LPI2C_Type *baseAddr)
Check the occurrence of an SMBus alert response.
Definition: lpi2c_hal.h:2271
#define LPI2C_SCFGR1_RXSTALL_MASK
Definition: S32K144.h:5825
#define LPI2C_SCFGR2_CLKHOLD_MASK
Definition: S32K144.h:5866
__I uint32_t MFSR
Definition: S32K144.h:5348
static bool LPI2C_HAL_SlaveGetTxDMA(const LPI2C_Type *baseAddr)
Check if slave transmit data DMA requests are enabled.
Definition: lpi2c_hal.h:2727
#define LPI2C_MFCR_TXWATER_SHIFT
Definition: S32K144.h:5650
static bool LPI2C_HAL_SlaveGetInt(const LPI2C_Type *baseAddr, uint32_t interrupts)
Return the state of the specified LPI2C slave interrupt.
Definition: lpi2c_hal.h:2611
#define LPI2C_MSR_PLTF_MASK
Definition: S32K144.h:5479
#define LPI2C_MCCR1_SETHOLD_MASK
Definition: S32K144.h:5640
static bool LPI2C_HAL_SlaveGetTransmitDataEvent(const LPI2C_Type *baseAddr)
Check if transmit data is requested.
Definition: lpi2c_hal.h:2483
#define LPI2C_MCCR1_CLKLO_SHIFT
Definition: S32K144.h:5633
#define LPI2C_SRDR_RXEMPTY_SHIFT
Definition: S32K144.h:5916
static bool LPI2C_HAL_SlaveGetSTOPDetectEvent(const LPI2C_Type *baseAddr)
Check the detection of a STOP condition.
Definition: lpi2c_hal.h:2382
#define LPI2C_MCR_RST_MASK
Definition: S32K144.h:5430
#define LPI2C_MCR_RRF(x)
Definition: S32K144.h:5449
#define LPI2C_SSR_FEF_SHIFT
Definition: S32K144.h:5731
static bool LPI2C_HAL_MasterGetInt(const LPI2C_Type *baseAddr, uint32_t interrupts)
Return the state of the specified LPI2C master interrupt.
Definition: lpi2c_hal.h:968
#define LPI2C_SCFGR1_TXCFG_SHIFT
Definition: S32K144.h:5846
#define LPI2C_SCFGR1_GCEN_MASK
Definition: S32K144.h:5837
#define LPI2C_MFSR_RXCOUNT_MASK
Definition: S32K144.h:5662
static void LPI2C_HAL_SlaveSetSMBusAlert(LPI2C_Type *baseAddr, bool enable)
Enable or disable match on SMBus Alert.
Definition: lpi2c_hal.h:2936
static void LPI2C_HAL_MasterSetPinLowTimeout(LPI2C_Type *baseAddr, uint32_t cycles)
Configure the pin low timeout.
Definition: lpi2c_hal.h:1516
static bool LPI2C_HAL_SlaveGetAddrDMA(const LPI2C_Type *baseAddr)
Check if slave address valid DMA requests are enabled.
Definition: lpi2c_hal.h:2693
#define LPI2C_MCR_DOZEN_MASK
Definition: S32K144.h:5434
#define LPI2C_MCCR1_DATAVD_SHIFT
Definition: S32K144.h:5645
__IO uint32_t SDER
Definition: S32K144.h:5356
#define LPI2C_MFSR_TXCOUNT_SHIFT
Definition: S32K144.h:5659
static bool LPI2C_HAL_MasterGetSoftwareReset(const LPI2C_Type *baseAddr)
Return the reset setting for the LPI2C master.
Definition: lpi2c_hal.h:501
#define LPI2C_SRDR_SOF_SHIFT
Definition: S32K144.h:5920
#define LPI2C_SAMR_ADDR0_SHIFT
Definition: S32K144.h:5884
static void LPI2C_HAL_SlaveSetRXStall(LPI2C_Type *baseAddr, bool enable)
Enable or disable clock stretching for data reception.
Definition: lpi2c_hal.h:3085
#define LPI2C_SSR_SDF_SHIFT
Definition: S32K144.h:5723
static void LPI2C_HAL_SlaveSetTxDMA(LPI2C_Type *baseAddr, bool enable)
Enable/disable slave transmit data DMA requests.
Definition: lpi2c_hal.h:2675
#define LPI2C_PARAM_MTXFIFO_SHIFT
Definition: S32K144.h:5418
#define LPI2C_SASR_RADDR_SHIFT
Definition: S32K144.h:5893
#define LPI2C_SSR_SBF_MASK
Definition: S32K144.h:5750
#define LPI2C_SAMR_ADDR1_SHIFT
Definition: S32K144.h:5888
#define LPI2C_MCFGR0_HRSEL_MASK
Definition: S32K144.h:5550
lpi2c_match_config_t
Data match selection Implements : lpi2c_match_config_t_Class.
Definition: lpi2c_hal.h:161
lpi2c_slave_addr_valid_t
Slave received address validity Implements : lpi2c_slave_addr_valid_t_Class.
Definition: lpi2c_hal.h:265
#define LPI2C_MCCR1_SETHOLD(x)
Definition: S32K144.h:5643
#define LPI2C_MSR_MBF_SHIFT
Definition: S32K144.h:5488
#define LPI2C_SCFGR1_TXDSTALL_SHIFT
Definition: S32K144.h:5830
static void LPI2C_HAL_SlaveSetTransmitNACK(LPI2C_Type *baseAddr, lpi2c_slave_nack_transmit_t nack)
Configure the ACK/NACK transmission after a received byte.
Definition: lpi2c_hal.h:3438
#define LPI2C_MSR_TDF_MASK
Definition: S32K144.h:5451
#define LPI2C_MCCR1_CLKLO_MASK
Definition: S32K144.h:5632
static lpi2c_hreq_source_t LPI2C_HAL_MasterGetHreqSelect(const LPI2C_Type *baseAddr)
Return the source of the host request input.
Definition: lpi2c_hal.h:1127
__IO uint32_t STAR
Definition: S32K144.h:5364
static bool LPI2C_HAL_SlaveGetRxDMA(const LPI2C_Type *baseAddr)
Check if slave receive data DMA requests are enabled.
Definition: lpi2c_hal.h:2710
#define LPI2C_SSR_BBF_MASK
Definition: S32K144.h:5754
#define LPI2C_SSR_AM0F_MASK
Definition: S32K144.h:5734
#define LPI2C_SCFGR2_FILTSDA(x)
Definition: S32K144.h:5881
__IO uint32_t SAMR
Definition: S32K144.h:5361
#define LPI2C_MDER_TDDE(x)
Definition: S32K144.h:5536
#define LPI2C_SSR_TDF_SHIFT
Definition: S32K144.h:5703
static bool LPI2C_HAL_SlaveGetAddrStall(const LPI2C_Type *baseAddr)
Return the configured state for clock stretching for valid address reception.
Definition: lpi2c_hal.h:3142
__IO uint32_t MDMR
Definition: S32K144.h:5341
static void LPI2C_HAL_SlaveSetAddrStall(LPI2C_Type *baseAddr, bool enable)
Enable or disable clock stretching for valid address reception.
Definition: lpi2c_hal.h:3123
static lpi2c_nack_config_t LPI2C_HAL_MasterGetNACKConfig(const LPI2C_Type *baseAddr)
Return the reaction of the module on NACK reception.
Definition: lpi2c_hal.h:1307
#define LPI2C_SCFGR1_RXCFG_SHIFT
Definition: S32K144.h:5850
static void LPI2C_HAL_SlaveSetSDAGlitchFilter(LPI2C_Type *baseAddr, uint8_t cycles)
Configure the LPI2C slave SDA glitch filter.
Definition: lpi2c_hal.h:3164
#define LPI2C_MCFGR2_BUSIDLE(x)
Definition: S32K144.h:5591
static bool LPI2C_HAL_MasterGetEndPacketEvent(const LPI2C_Type *baseAddr)
Check the occurrence of an end packet event.
Definition: lpi2c_hal.h:727
static lpi2c_match_config_t LPI2C_HAL_MasterGetMatchConfig(const LPI2C_Type *baseAddr)
Return the match mode of the module.
Definition: lpi2c_hal.h:1234
#define LPI2C_SCFGR2_FILTSCL_SHIFT
Definition: S32K144.h:5875
static void LPI2C_HAL_MasterSetClockLowPeriod(LPI2C_Type *baseAddr, uint8_t value)
Set the minimum clock low period.
Definition: lpi2c_hal.h:1737
static void LPI2C_HAL_MasterClearNACKDetectEvent(LPI2C_Type *baseAddr)
Clear the unexpected NACK event flag.
Definition: lpi2c_hal.h:804
uint16_t featureNumber
Definition: lpi2c_hal.h:113
#define LPI2C_SSR_FEF_MASK
Definition: S32K144.h:5730
static bool LPI2C_HAL_MasterGetPinLowTimeoutEvent(const LPI2C_Type *baseAddr)
Check the occurrence of a pin low timeout event.
Definition: lpi2c_hal.h:629
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT
Definition: S32K144.h:5568
static void LPI2C_HAL_MasterClearSTOPDetectEvent(LPI2C_Type *baseAddr)
Clear the STOP detect event flag.
Definition: lpi2c_hal.h:818
lpi2c_pin_config_t
Pin configuration selection Implements : lpi2c_pin_config_t_Class.
Definition: lpi2c_hal.h:146
static void LPI2C_HAL_SlaveSetACKStall(LPI2C_Type *baseAddr, bool enable)
Enable or disable clock stretching for the sending of the ACK bit.
Definition: lpi2c_hal.h:3009
#define LPI2C_MCFGR1_IGNACK_SHIFT
Definition: S32K144.h:5572
#define LPI2C_SSR_AM1F_SHIFT
Definition: S32K144.h:5739
static void LPI2C_HAL_MasterRxFIFOResetCmd(LPI2C_Type *baseAddr)
Reset the master receive FIFO.
Definition: lpi2c_hal.h:356
static uint8_t LPI2C_HAL_SlaveGetSDAGlitchFilter(const LPI2C_Type *baseAddr)
Return the LPI2C slave SDA glitch filter configuration.
Definition: lpi2c_hal.h:3182
__IO uint32_t MCFGR1
Definition: S32K144.h:5337
#define LPI2C_MCR_DOZEN_SHIFT
Definition: S32K144.h:5435
static void LPI2C_HAL_MasterSetPinConfig(LPI2C_Type *baseAddr, lpi2c_pin_config_t configuration)
Set the pin mode of the module.
Definition: lpi2c_hal.h:1179
#define LPI2C_SCR_RST_SHIFT
Definition: S32K144.h:5690
#define LPI2C_SCFGR2_FILTSDA_SHIFT
Definition: S32K144.h:5879
static bool LPI2C_HAL_SlaveGetGeneralCall(const LPI2C_Type *baseAddr)
Return the configured state for the general call address.
Definition: lpi2c_hal.h:2989
static uint8_t LPI2C_HAL_MasterGetMatch1(const LPI2C_Type *baseAddr)
Return the MATCH1 value for the data match feature.
Definition: lpi2c_hal.h:1603
#define LPI2C_SCFGR1_HSMEN(x)
Definition: S32K144.h:5860
#define LPI2C_SCR_RST_MASK
Definition: S32K144.h:5689
#define LPI2C_MSR_RDF_MASK
Definition: S32K144.h:5455
__IO uint32_t SSR
Definition: S32K144.h:5354
#define LPI2C_MDMR_MATCH1_SHIFT
Definition: S32K144.h:5611
#define LPI2C_VERID_MAJOR_MASK
Definition: S32K144.h:5412
#define LPI2C_SDER_RDDE(x)
Definition: S32K144.h:5815
#define LPI2C_MCCR1_DATAVD(x)
Definition: S32K144.h:5647
static bool LPI2C_HAL_MasterGetFIFOErrorEvent(const LPI2C_Type *baseAddr)
Check the occurrence of a FIFO error event.
Definition: lpi2c_hal.h:650
#define LPI2C_MCFGR1_TIMECFG(x)
Definition: S32K144.h:5578
#define LPI2C_PARAM_MTXFIFO_MASK
Definition: S32K144.h:5417
#define LPI2C_STAR_TXNACK_SHIFT
Definition: S32K144.h:5902
static void LPI2C_HAL_MasterSetMatchConfig(LPI2C_Type *baseAddr, lpi2c_match_config_t configuration)
Set the match mode of the module.
Definition: lpi2c_hal.h:1216
static bool LPI2C_HAL_SlaveGetHighSpeedModeDetect(const LPI2C_Type *baseAddr)
Return the state of the High-speed Mode master code detection.
Definition: lpi2c_hal.h:2801
static bool LPI2C_HAL_SlaveGetSMBusAlert(const LPI2C_Type *baseAddr)
Return the configured state for the SMBus Alert match.
Definition: lpi2c_hal.h:2954
static bool LPI2C_HAL_SlaveGetGeneralCallEvent(const LPI2C_Type *baseAddr)
Check the detection of the general call address.
Definition: lpi2c_hal.h:2289
static void LPI2C_HAL_MasterSetMatch1(LPI2C_Type *baseAddr, uint8_t value)
Set the MATCH1 value for the data match feature.
Definition: lpi2c_hal.h:1585
#define LPI2C_SAMR_ADDR1(x)
Definition: S32K144.h:5890
static void LPI2C_HAL_SlaveSetDataValidDelay(LPI2C_Type *baseAddr, uint8_t cycles)
Configure the SDA data valid delay time for the I2C slave.
Definition: lpi2c_hal.h:3243
#define LPI2C_MSR_ALF_MASK
Definition: S32K144.h:5471
#define LPI2C_SDER_RDDE_SHIFT
Definition: S32K144.h:5813
#define LPI2C_SCFGR1_IGNACK_SHIFT
Definition: S32K144.h:5854
#define LPI2C_MCFGR0_HRPOL_SHIFT
Definition: S32K144.h:5547
#define LPI2C_SCR_FILTEN_MASK
Definition: S32K144.h:5693
#define LPI2C_MCFGR1_MATCFG_SHIFT
Definition: S32K144.h:5580
#define LPI2C_MCFGR1_IGNACK(x)
Definition: S32K144.h:5574
static bool LPI2C_HAL_SlaveGetSoftwareReset(const LPI2C_Type *baseAddr)
Return the reset setting for the LPI2C slave.
Definition: lpi2c_hal.h:2183
#define LPI2C_MCR_MEN_MASK
Definition: S32K144.h:5426
#define LPI2C_SCFGR2_FILTSCL_MASK
Definition: S32K144.h:5874
#define LPI2C_VERID_FEATURE_SHIFT
Definition: S32K144.h:5405
static void LPI2C_HAL_MasterSetDozeMode(LPI2C_Type *baseAddr, bool enable)
Set the master behaviour in Doze mode.
Definition: lpi2c_hal.h:409
static lpi2c_rx_data_match_t LPI2C_HAL_MasterGetRxDataMatch(const LPI2C_Type *baseAddr)
Return the current data match discarding policy.
Definition: lpi2c_hal.h:1013
static void LPI2C_HAL_MasterSetDataValidDelayHS(LPI2C_Type *baseAddr, uint8_t value)
Set the data hold time for SDA in high-speed mode.
Definition: lpi2c_hal.h:1775
#define LPI2C_MCCR0_CLKLO(x)
Definition: S32K144.h:5618
__IO uint32_t SCFGR2
Definition: S32K144.h:5359
#define LPI2C_SCFGR1_RXCFG(x)
Definition: S32K144.h:5852
#define LPI2C_SCFGR1_SAEN_SHIFT
Definition: S32K144.h:5842
#define LPI2C_SDER_AVDE_SHIFT
Definition: S32K144.h:5817
#define LPI2C_MCFGR1_PRESCALE_MASK
Definition: S32K144.h:5563
#define LPI2C_SCFGR1_ACKSTALL_SHIFT
Definition: S32K144.h:5834
#define LPI2C_MDER_TDDE_SHIFT
Definition: S32K144.h:5534
static bool LPI2C_HAL_SlaveGetTransmitACKEvent(const LPI2C_Type *baseAddr)
Check if transmitting ACK response is required.
Definition: lpi2c_hal.h:2420
#define LPI2C_VERID_MINOR_SHIFT
Definition: S32K144.h:5409
#define LPI2C_VERID_MINOR_MASK
Definition: S32K144.h:5408
#define LPI2C_SCFGR1_HSMEN_SHIFT
Definition: S32K144.h:5858
static uint16_t LPI2C_HAL_SlaveGetReceivedAddr(const LPI2C_Type *baseAddr)
Return the received slave address.
Definition: lpi2c_hal.h:3418
static uint8_t LPI2C_HAL_MasterGetClockLowPeriod(const LPI2C_Type *baseAddr)
Return the configured minimum clock low period.
Definition: lpi2c_hal.h:1755
static void LPI2C_HAL_MasterSetRxDataMatch(LPI2C_Type *baseAddr, lpi2c_rx_data_match_t rxDataMatch)
Control the discarding of data that does not match the configured criteria.
Definition: lpi2c_hal.h:994
static void LPI2C_HAL_SlaveSetAddrDMA(LPI2C_Type *baseAddr, bool enable)
Enable/disable slave address valid DMA requests.
Definition: lpi2c_hal.h:2637
#define LPI2C_SCFGR1_SAEN(x)
Definition: S32K144.h:5844
LPI2C module version number Implements : lpi2c_version_info_t_Class.
Definition: lpi2c_hal.h:109
#define LPI2C_SCFGR2_FILTSDA_MASK
Definition: S32K144.h:5878
static bool LPI2C_HAL_MasterGetMasterBusyEvent(const LPI2C_Type *baseAddr)
Return the idle/busy state of the LPI2C master.
Definition: lpi2c_hal.h:553
#define LPI2C_SCFGR1_IGNACK(x)
Definition: S32K144.h:5856
#define LPI2C_SSR_TDF_MASK
Definition: S32K144.h:5702
__IO uint32_t MCCR1
Definition: S32K144.h:5345
#define LPI2C_MCFGR0_CIRFIFO(x)
Definition: S32K144.h:5557
lpi2c_master_prescaler_t
LPI2C master prescaler options Implements : lpi2c_master_prescaler_t_Class.
Definition: lpi2c_hal.h:193
static bool LPI2C_HAL_MasterGetDebugMode(const LPI2C_Type *baseAddr)
Return the debug mode setting for the LPI2C master.
Definition: lpi2c_hal.h:467
lpi2c_hreq_polarity_t
Host request input polarity selection Implements : lpi2c_hreq_polarity_t_Class.
Definition: lpi2c_hal.h:137
#define LPI2C_SCR_SEN_MASK
Definition: S32K144.h:5685
#define LPI2C_MDER_RDDE_MASK
Definition: S32K144.h:5537
#define LPI2C_SAMR_ADDR0_MASK
Definition: S32K144.h:5883
#define LPI2C_SCR_FILTEN(x)
Definition: S32K144.h:5696
#define LPI2C_MCFGR2_FILTSCL_SHIFT
Definition: S32K144.h:5593
static uint8_t LPI2C_HAL_MasterGetSetupHoldDelay(const LPI2C_Type *baseAddr)
Return the configured setup and hold time.
Definition: lpi2c_hal.h:1679
#define LPI2C_MCR_RTF_MASK
Definition: S32K144.h:5442
#define LPI2C_SDER_TDDE_MASK
Definition: S32K144.h:5808
#define LPI2C_SCFGR1_ADRSTALL(x)
Definition: S32K144.h:5824
__I uint32_t MRDR
Definition: S32K144.h:5351
#define LPI2C_SDER_AVDE(x)
Definition: S32K144.h:5819
static uint8_t LPI2C_HAL_MasterGetRxFIFOWatermark(const LPI2C_Type *baseAddr)
Return the configured receive FIFO watermark.
Definition: lpi2c_hal.h:1952
#define LPI2C_MCFGR0_RDMO_SHIFT
Definition: S32K144.h:5559
static void LPI2C_HAL_SlaveSetAddr1(LPI2C_Type *baseAddr, uint16_t addr)
Configure the ADDR1 address for slave address match.
Definition: lpi2c_hal.h:3321
__I uint32_t VERID
Definition: S32K144.h:5329
static uint8_t LPI2C_HAL_MasterGetDataValidDelayHS(const LPI2C_Type *baseAddr)
Return the configured data hold time for SDA in high-speed mode.
Definition: lpi2c_hal.h:1794
#define LPI2C_MSR_MBF_MASK
Definition: S32K144.h:5487
static uint16_t LPI2C_HAL_MasterGetTxFIFOSize(const LPI2C_Type *baseAddr)
Get the size of the Master Transmit FIFO.
Definition: lpi2c_hal.h:339
#define LPI2C_SCFGR1_RXCFG_MASK
Definition: S32K144.h:5849
static bool LPI2C_HAL_SlaveGetBusBusyEvent(const LPI2C_Type *baseAddr)
Check the busy state of the bus.
Definition: lpi2c_hal.h:2235
#define LPI2C_MSR_DMF_SHIFT
Definition: S32K144.h:5484
#define LPI2C_MCFGR1_PRESCALE_SHIFT
Definition: S32K144.h:5564
#define LPI2C_MCCR0_CLKLO_SHIFT
Definition: S32K144.h:5616
static void LPI2C_HAL_MasterSetRxFIFOWatermark(LPI2C_Type *baseAddr, uint8_t value)
Set the receive FIFO watermark.
Definition: lpi2c_hal.h:1934
__IO uint32_t MCFGR0
Definition: S32K144.h:5336
static void LPI2C_HAL_SlaveSetAddr0(LPI2C_Type *baseAddr, uint16_t addr)
Configure the ADDR0 address for slave address match.
Definition: lpi2c_hal.h:3361
#define LPI2C_MSR_SDF_MASK
Definition: S32K144.h:5463
#define LPI2C_SSR_SDF_MASK
Definition: S32K144.h:5722
static void LPI2C_HAL_MasterSetHreqPolarity(LPI2C_Type *baseAddr, lpi2c_hreq_polarity_t polarity)
Set the polarity of the host request input pin.
Definition: lpi2c_hal.h:1089
#define LPI2C_VERID_FEATURE_MASK
Definition: S32K144.h:5404
#define LPI2C_MSR_DMF_MASK
Definition: S32K144.h:5483
__IO uint32_t MTDR
Definition: S32K144.h:5349
static void LPI2C_HAL_MasterSetPrescaler(LPI2C_Type *baseAddr, lpi2c_master_prescaler_t prescaler)
Configure the LPI2C master prescaler.
Definition: lpi2c_hal.h:1363
static lpi2c_slave_addr_config_t LPI2C_HAL_SlaveGetAddrConfig(const LPI2C_Type *baseAddr)
Return the address match configuration.
Definition: lpi2c_hal.h:2763
static bool LPI2C_HAL_MasterGetRxEmpty(const LPI2C_Type *baseAddr)
Check if the master receive FIFO is empty.
Definition: lpi2c_hal.h:2075
__I uint32_t PARAM
Definition: S32K144.h:5330
lpi2c_master_command_t
LPI2C master commands Implements : lpi2c_master_command_t_Class.
Definition: lpi2c_hal.h:208
#define LPI2C_SDER_TDDE(x)
Definition: S32K144.h:5811
#define LPI2C_MCR_RST(x)
Definition: S32K144.h:5433
static void LPI2C_HAL_SlaveSetTxFlagConfig(LPI2C_Type *baseAddr, lpi2c_slave_txflag_config_t configuration)
Control the conditions for setting the transmit data flag.
Definition: lpi2c_hal.h:2901
#define LPI2C_MDMR_MATCH0_SHIFT
Definition: S32K144.h:5607
#define LPI2C_MCCR0_DATAVD_MASK
Definition: S32K144.h:5627
#define LPI2C_MCFGR1_MATCFG_MASK
Definition: S32K144.h:5579
static void LPI2C_HAL_SlaveSetSCLGlitchFilter(LPI2C_Type *baseAddr, uint8_t cycles)
Configure the LPI2C slave SCL glitch filter.
Definition: lpi2c_hal.h:3204
#define LPI2C_SCFGR1_GCEN(x)
Definition: S32K144.h:5840
#define LPI2C_SSR_RSF_MASK
Definition: S32K144.h:5718
#define LPI2C_MFCR_RXWATER_MASK
Definition: S32K144.h:5653
static void LPI2C_HAL_MasterSetSetupHoldDelay(LPI2C_Type *baseAddr, uint8_t value)
Set the setup and hold delay for a START / STOP condition.
Definition: lpi2c_hal.h:1660
#define LPI2C_SCFGR1_ADDRCFG(x)
Definition: S32K144.h:5864
#define LPI2C_SCR_FILTDZ_SHIFT
Definition: S32K144.h:5698
#define LPI2C_MFCR_TXWATER(x)
Definition: S32K144.h:5652
#define LPI2C_SCFGR1_ADDRCFG_MASK
Definition: S32K144.h:5861
#define LPI2C_MCFGR1_AUTOSTOP_MASK
Definition: S32K144.h:5567
static void LPI2C_HAL_SlaveSetFilterEnable(LPI2C_Type *baseAddr, bool enable)
Enable/disable the slave filter.
Definition: lpi2c_hal.h:2129
#define LPI2C_SCR_FILTDZ_MASK
Definition: S32K144.h:5697
static uint8_t LPI2C_HAL_SlaveGetData(const LPI2C_Type *baseAddr)
Return the data received by the LPI2C slave receiver.
Definition: lpi2c_hal.h:3525
static void LPI2C_HAL_MasterSetAutoStopConfig(LPI2C_Type *baseAddr, bool enable)
Configure the automatic generation of STOP condition.
Definition: lpi2c_hal.h:1326
static bool LPI2C_HAL_SlaveGetTXDStall(const LPI2C_Type *baseAddr)
Return the configured state for clock stretching for data transmission.
Definition: lpi2c_hal.h:3066
static void LPI2C_HAL_SlaveSetClockHoldTime(LPI2C_Type *baseAddr, uint8_t cycles)
Configure the minimum clock hold time for the I2C slave.
Definition: lpi2c_hal.h:3281
void LPI2C_HAL_Init(LPI2C_Type *baseAddr)
Initializes the LPI2C module to a known state.
Definition: lpi2c_hal.c:59
#define LPI2C_MCFGR1_TIMECFG_SHIFT
Definition: S32K144.h:5576
#define LPI2C_MCFGR0_HRSEL(x)
Definition: S32K144.h:5553
static void LPI2C_HAL_MasterSetDataValidDelay(LPI2C_Type *baseAddr, uint8_t value)
Set the data hold time for SDA.
Definition: lpi2c_hal.h:1621
static uint8_t LPI2C_HAL_MasterGetSetupHoldDelayHS(const LPI2C_Type *baseAddr)
Return the configured setup and hold time in high-speed mode.
Definition: lpi2c_hal.h:1835
static bool LPI2C_HAL_SlaveGetAddressValidEvent(const LPI2C_Type *baseAddr)
Check the validity of the Address Status Register.
Definition: lpi2c_hal.h:2441
#define LPI2C_SCFGR1_TXCFG_MASK
Definition: S32K144.h:5845
#define LPI2C_MCR_MEN(x)
Definition: S32K144.h:5429
static lpi2c_slave_addr_valid_t LPI2C_HAL_SlaveGetAddrValid(const LPI2C_Type *baseAddr)
Check the validity of received address.
Definition: lpi2c_hal.h:3397
static void LPI2C_HAL_MasterSetTxDMA(LPI2C_Type *baseAddr, bool enable)
Enable/disable transmit data DMA requests.
Definition: lpi2c_hal.h:867
#define LPI2C_SCFGR1_IGNACK_MASK
Definition: S32K144.h:5853
static bool LPI2C_HAL_SlaveGetACKStall(const LPI2C_Type *baseAddr)
Return the configured state for clock stretching for the sending of the ACK bit.
Definition: lpi2c_hal.h:3028
#define LPI2C_MDER_TDDE_MASK
Definition: S32K144.h:5533
#define LPI2C_SSR_AVF_SHIFT
Definition: S32K144.h:5711
#define LPI2C_MSR_PLTF_SHIFT
Definition: S32K144.h:5480
static void LPI2C_HAL_SlaveSetAddrConfig(LPI2C_Type *baseAddr, lpi2c_slave_addr_config_t configuration)
Control address match configuration.
Definition: lpi2c_hal.h:2745
static void LPI2C_HAL_MasterTransmitCmd(LPI2C_Type *baseAddr, lpi2c_master_command_t cmd, uint8_t data)
Provide commands and data for the LPI2C master.
Definition: lpi2c_hal.h:2042
#define LPI2C_SCFGR2_DATAVD_SHIFT
Definition: S32K144.h:5871
#define LPI2C_MCCR1_CLKHI_SHIFT
Definition: S32K144.h:5637
static uint16_t LPI2C_HAL_MasterGetRxFIFOSize(const LPI2C_Type *baseAddr)
Get the size of the Master Receive FIFO.
Definition: lpi2c_hal.h:321
#define LPI2C_SSR_AM1F_MASK
Definition: S32K144.h:5738
#define LPI2C_MSR_TDF_SHIFT
Definition: S32K144.h:5452
static lpi2c_slave_rxdata_config_t LPI2C_HAL_SlaveGetRxDataConfig(const LPI2C_Type *baseAddr)
Return the configured functionality of the receive data register.
Definition: lpi2c_hal.h:2877
#define LPI2C_MCFGR2_FILTSDA(x)
Definition: S32K144.h:5599
static uint8_t LPI2C_HAL_MasterGetSCLGlitchFilter(const LPI2C_Type *baseAddr)
Return the LPI2C SCL glitch filter configuration.
Definition: lpi2c_hal.h:1459
#define LPI2C_SSR_AVF_MASK
Definition: S32K144.h:5710
#define LPI2C_SSR_RDF_SHIFT
Definition: S32K144.h:5707
static lpi2c_slave_nack_transmit_t LPI2C_HAL_SlaveGetTransmitNACK(const LPI2C_Type *baseAddr)
Return the configured ACK/NACK transmission setting.
Definition: lpi2c_hal.h:3456
#define LPI2C_PARAM_MRXFIFO_SHIFT
Definition: S32K144.h:5422
#define LPI2C_MCFGR0_RDMO_MASK
Definition: S32K144.h:5558
static uint8_t LPI2C_HAL_MasterGetClockHighPeriod(const LPI2C_Type *baseAddr)
Return the configured minimum clock high period.
Definition: lpi2c_hal.h:1718
#define LPI2C_MCFGR2_BUSIDLE_SHIFT
Definition: S32K144.h:5589
#define LPI2C_MCR_RRF_MASK
Definition: S32K144.h:5446
#define LPI2C_SRDR_DATA_MASK
Definition: S32K144.h:5911
static void LPI2C_HAL_MasterSetDebugMode(LPI2C_Type *baseAddr, bool enable)
Set the master behaviour in Debug mode.
Definition: lpi2c_hal.h:391
#define LPI2C_MCFGR1_AUTOSTOP(x)
Definition: S32K144.h:5570
static lpi2c_timeout_config_t LPI2C_HAL_MasterGetTimeoutConfig(const LPI2C_Type *baseAddr)
Return the timeout configuration of the module.
Definition: lpi2c_hal.h:1270
static bool LPI2C_HAL_MasterGetTransmitDataRequestEvent(const LPI2C_Type *baseAddr)
Indicate if the LPI2C master requests more data.
Definition: lpi2c_hal.h:591
#define LPI2C_MCCR1_DATAVD_MASK
Definition: S32K144.h:5644
#define LPI2C_SCFGR2_FILTSCL(x)
Definition: S32K144.h:5877
#define LPI2C_SCFGR2_CLKHOLD(x)
Definition: S32K144.h:5869
#define LPI2C_SCFGR1_ACKSTALL(x)
Definition: S32K144.h:5836
#define LPI2C_SSR_RDF_MASK
Definition: S32K144.h:5706
#define LPI2C_SCR_RST(x)
Definition: S32K144.h:5692
#define LPI2C_MCFGR1_PRESCALE(x)
Definition: S32K144.h:5566
#define LPI2C_SSR_BBF_SHIFT
Definition: S32K144.h:5755
static void LPI2C_HAL_SlaveClearSTOPDetectEvent(LPI2C_Type *baseAddr)
Clear the STOP detect flag.
Definition: lpi2c_hal.h:2527
static lpi2c_pin_config_t LPI2C_HAL_MasterGetPinConfig(const LPI2C_Type *baseAddr)
Return the pin mode of the module.
Definition: lpi2c_hal.h:1197
static uint8_t LPI2C_HAL_MasterGetTxFIFOCount(const LPI2C_Type *baseAddr)
Return the number of words in the transmit FIFO.
Definition: lpi2c_hal.h:2023
#define LPI2C_MFCR_RXWATER_SHIFT
Definition: S32K144.h:5654
static void LPI2C_HAL_MasterSetHreqEnable(LPI2C_Type *baseAddr, bool enable)
Enable/disable the host request feature.
Definition: lpi2c_hal.h:1109
static void LPI2C_HAL_MasterTxFIFOResetCmd(LPI2C_Type *baseAddr)
Reset the master transmit FIFO.
Definition: lpi2c_hal.h:373
static bool LPI2C_HAL_MasterGetArbitrationLostEvent(const LPI2C_Type *baseAddr)
Check the occurrence of an arbitration lost event.
Definition: lpi2c_hal.h:670
#define LPI2C_SCFGR1_RXSTALL_SHIFT
Definition: S32K144.h:5826
#define LPI2C_SDER_RDDE_MASK
Definition: S32K144.h:5812
#define LPI2C_SSR_SBF_SHIFT
Definition: S32K144.h:5751
#define LPI2C_MSR_FEF_SHIFT
Definition: S32K144.h:5476
static bool LPI2C_HAL_SlaveGetAddressMatch1Event(const LPI2C_Type *baseAddr)
Check the detection of an ADDR1 address match.
Definition: lpi2c_hal.h:2308
__IO uint32_t STDR
Definition: S32K144.h:5366
static void LPI2C_HAL_SlaveClearRepeatedStartEvent(LPI2C_Type *baseAddr)
Clear the repeated START detect flag.
Definition: lpi2c_hal.h:2541
__I uint32_t SRDR
Definition: S32K144.h:5368
static bool LPI2C_HAL_SlaveGetFilterEnable(const LPI2C_Type *baseAddr)
Check if the slave filter is enabled or disabled.
Definition: lpi2c_hal.h:2147
__IO uint32_t SCFGR1
Definition: S32K144.h:5358
__IO uint32_t MSR
Definition: S32K144.h:5333
static void LPI2C_HAL_MasterSetSDAGlitchFilter(LPI2C_Type *baseAddr, uint8_t cycles)
Configure the LPI2C SDA glitch filter.
Definition: lpi2c_hal.h:1402
#define LPI2C_MCR_RTF(x)
Definition: S32K144.h:5445
static void LPI2C_HAL_SlaveSetEnable(LPI2C_Type *baseAddr, bool enable)
Enable or disable the LPI2C slave.
Definition: lpi2c_hal.h:2200
static bool LPI2C_HAL_MasterGetNACKDetectEvent(const LPI2C_Type *baseAddr)
Check the occurrence of an unexpected NACK event.
Definition: lpi2c_hal.h:691
#define LPI2C_MFCR_RXWATER(x)
Definition: S32K144.h:5656
#define LPI2C_MDMR_MATCH1(x)
Definition: S32K144.h:5613
static bool LPI2C_HAL_SlaveGetEnable(const LPI2C_Type *baseAddr)
Return the enable/disable setting for the LPI2C slave.
Definition: lpi2c_hal.h:2218
#define LPI2C_SSR_RSF_SHIFT
Definition: S32K144.h:5719
static void LPI2C_HAL_GetVersion(const LPI2C_Type *baseAddr, lpi2c_version_info_t *versionInfo)
Get the version of the LPI2C module.
Definition: lpi2c_hal.h:303
static bool LPI2C_HAL_MasterGetRxDMA(const LPI2C_Type *baseAddr)
Check if receive data DMA requests are enabled.
Definition: lpi2c_hal.h:885
#define LPI2C_MCFGR1_PINCFG_MASK
Definition: S32K144.h:5583
#define LPI2C_MSR_BBF_MASK
Definition: S32K144.h:5491
#define LPI2C_MCFGR2_FILTSDA_SHIFT
Definition: S32K144.h:5597
#define LPI2C_MSR_FEF_MASK
Definition: S32K144.h:5475
#define LPI2C_MCFGR2_BUSIDLE_MASK
Definition: S32K144.h:5588
static bool LPI2C_HAL_MasterGetTxDMA(const LPI2C_Type *baseAddr)
Check if transmit data DMA requests are enabled.
Definition: lpi2c_hal.h:902
#define LPI2C_MDMR_MATCH1_MASK
Definition: S32K144.h:5610
#define LPI2C_SCR_SEN_SHIFT
Definition: S32K144.h:5686
#define LPI2C_SDER_AVDE_MASK
Definition: S32K144.h:5816
static void LPI2C_HAL_MasterSetRxDMA(LPI2C_Type *baseAddr, bool enable)
Enable/disable receive data DMA requests.
Definition: lpi2c_hal.h:848
#define LPI2C_MCFGR1_TIMECFG_MASK
Definition: S32K144.h:5575
#define LPI2C_STAR_TXNACK_MASK
Definition: S32K144.h:5901
#define LPI2C_SASR_ANV_SHIFT
Definition: S32K144.h:5897
static uint8_t LPI2C_HAL_MasterGetMatch0(const LPI2C_Type *baseAddr)
Return the MATCH0 value for the data match feature.
Definition: lpi2c_hal.h:1566
#define LPI2C_SCFGR1_TXCFG(x)
Definition: S32K144.h:5848
#define LPI2C_MSR_EPF_SHIFT
Definition: S32K144.h:5460
#define LPI2C_SSR_TAF_MASK
Definition: S32K144.h:5714
#define LPI2C_MDMR_MATCH0(x)
Definition: S32K144.h:5609
#define LPI2C_SDER_TDDE_SHIFT
Definition: S32K144.h:5809
lpi2c_slave_rxdata_config_t
Slave receive data register function configuration Implements : lpi2c_slave_rxdata_config_t_Class.
Definition: lpi2c_hal.h:247
#define LPI2C_MCCR1_SETHOLD_SHIFT
Definition: S32K144.h:5641
#define LPI2C_MFCR_TXWATER_MASK
Definition: S32K144.h:5649
#define LPI2C_MDMR_MATCH0_MASK
Definition: S32K144.h:5606
static lpi2c_slave_txflag_config_t LPI2C_HAL_SlaveGetTxFlagConfig(const LPI2C_Type *baseAddr)
Return the configured settings for the transmit data flag.
Definition: lpi2c_hal.h:2919
#define LPI2C_MCFGR0_RDMO(x)
Definition: S32K144.h:5561
static void LPI2C_HAL_MasterSetSCLGlitchFilter(LPI2C_Type *baseAddr, uint8_t cycles)
Configure the LPI2C SCL glitch filter.
Definition: lpi2c_hal.h:1441
#define LPI2C_MCCR1_CLKHI(x)
Definition: S32K144.h:5639
static uint8_t LPI2C_HAL_MasterGetRxFIFOCount(const LPI2C_Type *baseAddr)
Return the number of words in the receive FIFO.
Definition: lpi2c_hal.h:2006
#define LPI2C_SSR_GCF_MASK
Definition: S32K144.h:5742
static bool LPI2C_HAL_SlaveGetAddressMatch0Event(const LPI2C_Type *baseAddr)
Check the detection of an ADDR0 address match.
Definition: lpi2c_hal.h:2327
#define LPI2C_MSR_BBF_SHIFT
Definition: S32K144.h:5492
#define LPI2C_SCFGR2_DATAVD_MASK
Definition: S32K144.h:5870
static void LPI2C_HAL_MasterSetMatch0(LPI2C_Type *baseAddr, uint8_t value)
Set the MATCH0 value for the data match feature.
Definition: lpi2c_hal.h:1548
#define LPI2C_SCR_SEN(x)
Definition: S32K144.h:5688
static void LPI2C_HAL_SlaveTransmitData(LPI2C_Type *baseAddr, uint8_t data)
Provide data for the LPI2C slave transmitter.
Definition: lpi2c_hal.h:3474
static bool LPI2C_HAL_SlaveGetRepeatedStartEvent(const LPI2C_Type *baseAddr)
Check the detection of a repeated START condition.
Definition: lpi2c_hal.h:2401
static bool LPI2C_HAL_SlaveGetSlaveBusyEvent(const LPI2C_Type *baseAddr)
Check the busy state of the slave.
Definition: lpi2c_hal.h:2253
static uint8_t LPI2C_HAL_SlaveGetDataValidDelay(const LPI2C_Type *baseAddr)
Return the SDA data valid delay time configuration.
Definition: lpi2c_hal.h:3261
lpi2c_slave_addr_config_t
Slave address configuration Implements : lpi2c_slave_addr_config_t_Class.
Definition: lpi2c_hal.h:223
static void LPI2C_HAL_MasterSetClockLowPeriodHS(LPI2C_Type *baseAddr, uint8_t value)
Set the minimum clock low period in high-speed mode.
Definition: lpi2c_hal.h:1896
#define LPI2C_SSR_SARF_MASK
Definition: S32K144.h:5746
#define LPI2C_SSR_TAF_SHIFT
Definition: S32K144.h:5715
#define LPI2C_MCFGR0_HRPOL_MASK
Definition: S32K144.h:5546