S32 SDK
lpspi_shared_function.c
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
69 #include <assert.h>
70 #include "lpspi_shared_function.h"
71 
72 /*******************************************************************************
73  * Variables
74  ******************************************************************************/
75 
78 
81 
82 /* Pointer to runtime state structure.*/
84 
85 /*******************************************************************************
86  * Code
87  ******************************************************************************/
88 
99 void LPSPI_DRV_IRQHandler(uint32_t instance)
100 {
101  if(instance < LPSPI_INSTANCE_COUNT)
102  {
103  const LPSPI_Type *base = g_lpspiBase[instance];
104 
105  if (LPSPI_HAL_IsMaster(base))
106  {
107  /* Master mode.*/
108  LPSPI_DRV_MasterIRQHandler(instance);
109  }
110  else
111  {
112  /* Slave mode.*/
113  LPSPI_DRV_SlaveIRQHandler(instance);
114  }
115  }
116 }
122 void LPSPI_DRV_FillupTxBuffer(uint32_t instance)
123 {
124  /* Instantiate local variable of type dspi_master_state_t and point to global state. */
125  lpspi_state_t * lpspiState = g_lpspiStatePtr[instance];
126  LPSPI_Type *base = g_lpspiBase[instance];
127  uint32_t wordToSend = 0;
128  uint16_t numOfBytes;
129  uint8_t j;
130  uint16_t index;
131  uint8_t availableSpace = (uint8_t)(lpspiState->fifoSize - (uint8_t)LPSPI_HAL_ReadTxCount(base));
132 
133  /* Fill the TX buffer. */
134  while(availableSpace != 0U)
135  {
136  if (lpspiState->isPcsContinuous == true)
137  {
138  if(lpspiState->txCount == 1U)
139  {
140  /* Disable continuous PCS */
142  lpspiState->txCount = 0U;
143  break;
144  }
145  }
146  /* Get the number of bytes which can be written in a single 32 bits word. */
147  if ((lpspiState->bytesPerFrame - lpspiState->txFrameCnt) <= (uint16_t)4)
148  {
149  numOfBytes = (uint16_t)(lpspiState->bytesPerFrame - lpspiState->txFrameCnt);
150  }
151  else
152  {
153  numOfBytes = 4U;
154  }
155  wordToSend = 0;
156  /* Generate the word which will be written in buffer. */
157  /* For the case when frame size > 4 bytes and MSB the words must be written in
158  * specific order because the hardware MSB/LSB is not enough.
159  */
160  if ((lpspiState->lsb == false) && (lpspiState->bytesPerFrame > 4U))
161  {
162  index = (uint16_t)(lpspiState->bytesPerFrame - 1U - lpspiState->txFrameCnt);
163  for (j = 0; j < numOfBytes; j++)
164  {
165  wordToSend = ((wordToSend)<<8) + (lpspiState->txBuff[index]);
166  index--;
167  }
168  lpspiState->txFrameCnt = (uint16_t)((lpspiState->txFrameCnt + numOfBytes) % lpspiState->bytesPerFrame);
169  if (lpspiState->txFrameCnt == 0U)
170  {
171  lpspiState->txBuff = lpspiState->txBuff + lpspiState->bytesPerFrame;
172  }
173  }
174  else
175  {
176  for (j = 0; j < numOfBytes; j++)
177  {
178  wordToSend = wordToSend + ((uint32_t)*(lpspiState->txBuff) << (8U * j));
179  lpspiState->txBuff++;
180  }
181  lpspiState->txFrameCnt = (uint16_t)((lpspiState->txFrameCnt + numOfBytes) % lpspiState->bytesPerFrame);
182  }
183  LPSPI_HAL_WriteData(base, wordToSend);
184  /* Update internal variable used in transmission. */
185  lpspiState->txCount = (uint16_t)(lpspiState->txCount - numOfBytes);
186  /* Verify if all bytes were send. */
187  if (lpspiState->txCount == 0U)
188  {
189  break;
190  }
191  availableSpace = (uint8_t)(availableSpace - 1U);
192  }
193 }
200 void LPSPI_DRV_ReadRXBuffer(uint32_t instance)
201 {
202  lpspi_state_t * lpspiState = g_lpspiStatePtr[instance];
203  const LPSPI_Type *base = g_lpspiBase[instance];
204  uint32_t receivedWord;
205  uint16_t numOfBytes;
206  uint16_t j;
207  uint16_t index;
208  uint8_t filledSpace = (uint8_t)LPSPI_HAL_ReadRxCount(base);
209  while (filledSpace!= 0U)
210  {
211  receivedWord = LPSPI_HAL_ReadData(base);
212  /* Get the number of bytes which can be read from this 32 bites */
213  if ((lpspiState->bytesPerFrame - lpspiState->rxFrameCnt) <= (uint16_t)4)
214  {
215  numOfBytes = (uint16_t)(lpspiState->bytesPerFrame - lpspiState->rxFrameCnt);
216  }
217  else
218  {
219  numOfBytes = 4U;
220  }
221  /* Generate the word which will be write in buffer. */
222  if ((lpspiState->lsb == false) && (lpspiState->bytesPerFrame > 4U))
223  {
224  index = (uint16_t)(lpspiState->bytesPerFrame - lpspiState->rxFrameCnt - 1U);
225  for (j = numOfBytes; j > 0U; j--)
226  {
227  lpspiState->rxBuff[index] = (uint8_t)(receivedWord >> ((j - 1U) * 8U));
228  index--;
229  }
230  lpspiState->rxFrameCnt = (uint16_t)((lpspiState->rxFrameCnt + numOfBytes) % lpspiState->bytesPerFrame);
231  if (lpspiState->rxFrameCnt == 0U)
232  {
233  lpspiState->rxBuff = lpspiState->rxBuff + lpspiState->bytesPerFrame;
234  }
235  }
236  else
237  {
238  for (j = 0; j < numOfBytes; j++)
239  {
240  *(lpspiState->rxBuff) = (uint8_t)(receivedWord >> (j * 8U));
241  lpspiState->rxBuff++;
242  }
243  lpspiState->rxFrameCnt = (uint16_t)((lpspiState->rxFrameCnt + numOfBytes) % lpspiState->bytesPerFrame);
244  }
245 
246  /* Update internal variable used in transmission. */
247  lpspiState->rxCount = (uint16_t)(lpspiState->rxCount - numOfBytes);
248  /* Verify if all bytes were sent. */
249  if (lpspiState->rxCount == 0U)
250  {
251  break;
252  }
253  filledSpace = (uint8_t)(filledSpace - 1U);
254  }
255 }
256 
261 void LPSPI_DRV_DisableTEIEInterrupts(uint32_t instance)
262 {
263  LPSPI_Type *base = g_lpspiBase[instance];
264 
269 }
270 
271 /*******************************************************************************
272  * EOF
273  ******************************************************************************/
274 
volatile uint16_t rxFrameCnt
static uint32_t LPSPI_HAL_ReadRxCount(const LPSPI_Type *base)
Reads RX COUNT form the FIFO Status Register.
Definition: lpspi_hal.h:828
#define LPSPI_INSTANCE_COUNT
Definition: S32K144.h:6194
volatile uint16_t txFrameCnt
Runtime state structure for the LPSPI master driver.
void LPSPI_DRV_ReadRXBuffer(uint32_t instance)
Read all data from RX FIFO This function will read all data from RX FIFO and will transfer this infro...
static void LPSPI_HAL_ClearContCBit(LPSPI_Type *base)
Clear CONTC bit form TCR Register.
Definition: lpspi_hal.h:841
lpspi_state_t * g_lpspiStatePtr[LPSPI_INSTANCE_COUNT]
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K144.h:269
static uint32_t LPSPI_HAL_ReadData(const LPSPI_Type *base)
Reads data from the data buffer.
Definition: lpspi_hal.h:785
void LPSPI_DRV_FillupTxBuffer(uint32_t instance)
Fill up the TX FIFO with data. This function fills up the TX FIFO with data based on the bytes/frame...
static bool LPSPI_HAL_IsMaster(const LPSPI_Type *base)
Returns whether the LPSPI module is in master mode.
Definition: lpspi_hal.h:384
volatile uint16_t rxCount
void LPSPI_DRV_MasterIRQHandler(uint32_t instance)
Interrupt handler for LPSPI master mode. This handler uses the buffers stored in the lpspi_master_sta...
volatile uint16_t txCount
static uint32_t LPSPI_HAL_ReadTxCount(const LPSPI_Type *base)
Reads TX COUNT form the FIFO Status Register.
Definition: lpspi_hal.h:814
void LPSPI_DRV_IRQHandler(uint32_t instance)
The function LPSPI_DRV_IRQHandler passes IRQ control to either the master or slave driver...
IRQn_Type g_lpspiIrqId[LPSPI_INSTANCE_COUNT]
Table to save LPSPI IRQ enumeration numbers defined in the CMSIS header file.
#define LPSPI_IRQS
Definition: S32K144.h:6219
void LPSPI_DRV_DisableTEIEInterrupts(uint32_t instance)
Disable the TEIE interrupts at the end of a transfer. Disable the interrupts and clear the status for...
static void LPSPI_HAL_SetIntMode(LPSPI_Type *base, lpspi_status_flag_t interruptSrc, bool enable)
Configures the LPSPI interrupts.
Definition: lpspi_hal.h:492
status_t LPSPI_HAL_ClearStatusFlag(LPSPI_Type *base, lpspi_status_flag_t statusFlag)
Clears the LPSPI status flag.
Definition: lpspi_hal.c:278
LPSPI_Type * g_lpspiBase[LPSPI_INSTANCE_COUNT]
Table of base pointers for SPI instances.
const uint8_t * txBuff
void LPSPI_DRV_SlaveIRQHandler(uint32_t instance)
Interrupt handler for LPSPI slave mode. This handler uses the buffers stored in the lpspi_master_stat...
#define LPSPI_BASE_PTRS
Definition: S32K144.h:6213
static void LPSPI_HAL_WriteData(LPSPI_Type *base, uint32_t data)
Writes data into the TX data buffer.
Definition: lpspi_hal.h:756