105 #define DIVIDER_MIN_VALUE 1U
106 #define DIVIDER_MAX_VALUE 0xFFU
110 #define TX_SHIFTER(x) (x)
111 #define RX_SHIFTER(x) (uint8_t)((x) + 1U)
112 #define SCL_TIMER(x) (x)
113 #define CONTROL_TIMER(x) (uint8_t)((x) + 1U)
126 static void FLEXIO_I2C_DRV_MasterComputeBaudRateDivider(uint32_t baudRate,
134 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 2U;
136 if (tmpDiv < DIVIDER_MIN_VALUE)
138 tmpDiv = DIVIDER_MIN_VALUE;
140 if (tmpDiv > DIVIDER_MAX_VALUE)
142 tmpDiv = DIVIDER_MAX_VALUE;
145 *divider = (uint16_t)tmpDiv;
155 static void FLEXIO_I2C_DRV_MasterConfigure(
const flexio_i2c_master_state_t *master, uint32_t inputClock, uint32_t baudRate)
159 uint8_t resourceIndex;
162 resourceIndex = master->flexioCommon.resourceIndex;
165 FLEXIO_I2C_DRV_MasterComputeBaudRateDivider(baudRate, ÷r, inputClock);
169 TX_SHIFTER(resourceIndex),
176 TX_SHIFTER(resourceIndex),
181 CONTROL_TIMER(resourceIndex),
186 RX_SHIFTER(resourceIndex),
191 RX_SHIFTER(resourceIndex),
196 CONTROL_TIMER(resourceIndex),
202 SCL_TIMER(resourceIndex),
211 SCL_TIMER(resourceIndex),
212 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
223 CONTROL_TIMER(resourceIndex),
232 CONTROL_TIMER(resourceIndex),
233 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
253 uint8_t resourceIndex;
255 resourceIndex = master->flexioCommon.resourceIndex;
257 bytesNo = master->txRemainingBytes;
258 bytesNo = (bytesNo * 18U) + 1U;
261 timerCmp = (uint16_t)((timerCmp & 0x00FFU) | (uint16_t)((bytesNo & 0xFFU) << 8U));
275 uint8_t resourceIndex;
277 resourceIndex = master->flexioCommon.resourceIndex;
279 addrByte = (uint8_t)((uint8_t)(master->slaveAddress << 1U) + (uint8_t)(master->receive ? 1U : 0U));
294 uint8_t resourceIndex;
297 resourceIndex = master->flexioCommon.resourceIndex;
302 if (master->rxRemainingBytes == 0U)
307 if (master->addrReceived ==
false)
310 master->addrReceived =
true;
311 if (master->receive ==
true)
319 master->rxRemainingBytes--;
320 if (master->receive ==
true)
323 *(master->data) = data;
327 if ((master->receive ==
true) && (master->rxRemainingBytes == 1U))
347 uint8_t resourceIndex;
350 resourceIndex = master->flexioCommon.resourceIndex;
353 if (master->txRemainingBytes == 0U)
358 master->txRemainingBytes--;
360 if (master->txRemainingBytes == 0U)
363 if (master->sendStop ==
true)
374 else if (master->receive ==
true)
382 data = *(master->data);
401 uint8_t resourceIndex;
404 resourceIndex = master->flexioCommon.resourceIndex;
414 switch (master->driverType)
419 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
422 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
446 master->driverIdle =
true;
449 if (master->blocking ==
true)
465 uint8_t resourceIndex;
467 resourceIndex = master->flexioCommon.resourceIndex;
489 uint8_t resourceIndex;
491 resourceIndex = master->flexioCommon.resourceIndex;
509 FLEXIO_I2C_DRV_MasterEndTransfer(master);
523 switch (master->driverType)
527 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
537 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
545 master->blocking =
false;
550 FLEXIO_I2C_DRV_MasterStopTransfer(master);
553 return master->status;
572 uint8_t resourceIndex;
574 resourceIndex = master->flexioCommon.resourceIndex;
588 uint8_t pinMask = (uint8_t)((1U << master->sdaPin) | (1U << master->sclPin));
610 static void FLEXIO_I2C_DRV_MasterCheckStatus(
void *stateStruct)
613 uint8_t resourceIndex;
620 resourceIndex = master->flexioCommon.resourceIndex;
632 if (FLEXIO_I2C_DRV_MasterCheckNack(baseAddr, master))
636 FLEXIO_I2C_DRV_MasterStopTransfer(master);
638 if (master->callback != NULL)
654 FLEXIO_I2C_DRV_ReadData(master);
668 FLEXIO_I2C_DRV_MasterStopTransfer(master);
670 if (master->callback != NULL)
680 FLEXIO_I2C_DRV_WriteData(master);
681 if (master->txRemainingBytes == 0U)
703 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
704 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter])) + (
sizeof(uint32_t) - 1U);
722 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
723 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter]));
734 static inline void FLEXIO_I2C_DRV_MasterDmaBlockImmediate(
edma_software_tcd_t *stcdBase, uint8_t blockNo)
747 static inline void FLEXIO_I2C_DRV_MasterDmaBlockTerminate(
edma_software_tcd_t *stcdBase, uint8_t blockNo)
770 if (master->receive ==
false)
772 addr = (uint32_t)(master->data);
777 master->dummyDmaIdle = 0xFFU;
778 addr = (uint32_t)(&(master->dummyDmaIdle));
781 srcList[0U].
length = master->rxRemainingBytes;
783 destList[0U].
address = FLEXIO_I2C_DRV_MasterComputeTxRegAddr(master);
784 destList[0U].
length = master->rxRemainingBytes;
788 if (master->sendStop)
790 master->dummyDmaStop = 0U;
794 master->dummyDmaStop = 0xFFU;
796 srcList[1U].
address = (uint32_t)(&(master->dummyDmaStop));
799 destList[1U].
address = FLEXIO_I2C_DRV_MasterComputeTxRegAddr(master);
805 1U, srcList, destList, 2U);
807 if (master->receive ==
true)
813 FLEXIO_I2C_DRV_MasterDmaBlockTerminate(stcdBase, 0U);
830 uint8_t blockCnt = 0U;
836 dmaChn = master->rxDMAChannel;
839 if (master->receive ==
false)
844 FLEXIO_I2C_DRV_MasterComputeRxRegAddr(master),
845 (uint32_t)(&(master->dummyDmaReceive)),
857 srcList[blockCnt].
address = FLEXIO_I2C_DRV_MasterComputeRxRegAddr(master);
858 srcList[blockCnt].
length = 1U;
860 destList[blockCnt].
address = (uint32_t)(&(master->dummyDmaReceive));
861 destList[blockCnt].
length = 1U;
865 if (master->rxRemainingBytes > 1U)
868 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
872 master->dmaReceiveTxStop0 = (uint8_t)(tmp & 0xFFU);
873 srcList[blockCnt].
address = (uint32_t)(&(master->dmaReceiveTxStop0));
874 srcList[blockCnt].
length = 1U;
876 destList[blockCnt].
address = (uint32_t)(&(baseAddr->
SHIFTCFG[shifter]));
877 destList[blockCnt].
length = 1U;
881 srcList[blockCnt].
address = FLEXIO_I2C_DRV_MasterComputeRxRegAddr(master);
882 srcList[blockCnt].
length = master->rxRemainingBytes - 1U;
884 destList[blockCnt].
address = (uint32_t)(master->data);
885 destList[blockCnt].
length = master->rxRemainingBytes - 1U;
892 master->dmaReceiveTxStop1 = (uint8_t)(tmp & 0xFFU);
893 srcList[blockCnt].
address = (uint32_t)(&(master->dmaReceiveTxStop1));
894 srcList[blockCnt].
length = 1U;
896 destList[blockCnt].
address = (uint32_t)(&(baseAddr->
SHIFTCFG[shifter]));
897 destList[blockCnt].
length = 1U;
902 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
906 master->dmaReceiveRxStop1 = (uint8_t)(tmp & 0xFFU);
907 srcList[blockCnt].
address = (uint32_t)(&(master->dmaReceiveRxStop1));
908 srcList[blockCnt].
length = 1U;
910 destList[blockCnt].
address = (uint32_t)(&(baseAddr->
SHIFTCFG[shifter]));
911 destList[blockCnt].
length = 1U;
915 srcList[blockCnt].
address = FLEXIO_I2C_DRV_MasterComputeRxRegAddr(master);
916 srcList[blockCnt].
length = 1U;
918 destList[blockCnt].
address = (uint32_t)(&(master->data[master->rxRemainingBytes - 1U]));
919 destList[blockCnt].
length = 1U;
929 FLEXIO_I2C_DRV_MasterDmaBlockImmediate(stcdBase, 0U);
930 if (master->rxRemainingBytes > 1U)
932 FLEXIO_I2C_DRV_MasterDmaBlockImmediate(stcdBase, 2U);
933 FLEXIO_I2C_DRV_MasterDmaBlockImmediate(stcdBase, 3U);
936 FLEXIO_I2C_DRV_MasterDmaBlockTerminate(stcdBase, (uint8_t)(blockCnt - 2U));
949 uint32_t alignedStcd;
957 FLEXIO_I2C_DRV_MasterDmaConfigTx(master, stcdBase);
958 FLEXIO_I2C_DRV_MasterDmaConfigRx(master, &stcdBase[FLEXIO_I2C_DMA_TX_CHAIN_LENGTH]);
973 static void FLEXIO_I2C_DRV_MasterEndDmaTransfer(
void *stateStruct)
976 uint8_t resourceIndex;
983 resourceIndex = master->flexioCommon.resourceIndex;
991 FLEXIO_I2C_DRV_MasterStopTransfer(master);
993 if (master->callback != NULL)
1010 FLEXIO_I2C_DRV_MasterStopTransfer(master);
1012 if (master->callback != NULL)
1033 uint8_t resourceIndex;
1037 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1038 resourceIndex = master->flexioCommon.resourceIndex;
1046 if (FLEXIO_I2C_DRV_MasterBusBusy(baseAddr, master))
1052 master->data = (uint8_t *)buff;
1054 master->txRemainingBytes = size + 1U;
1055 master->rxRemainingBytes = size;
1057 master->driverIdle =
false;
1058 master->sendStop = sendStop;
1059 master->receive = receive;
1060 master->addrReceived =
false;
1063 FLEXIO_I2C_DRV_MasterSetBytesNo(baseAddr, master);
1065 FLEXIO_I2C_DRV_MasterEnableTransfer(master);
1067 switch (master->driverType)
1071 FLEXIO_I2C_DRV_MasterSendAddress(baseAddr, master);
1074 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
1077 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
1084 FLEXIO_I2C_DRV_MasterSendAddress(baseAddr, master);
1088 FLEXIO_I2C_DRV_MasterStartDmaTransfer(master);
1094 FLEXIO_I2C_DRV_MasterSendAddress(baseAddr, master);
1123 uint32_t inputClock;
1142 master->flexioCommon.resourceCount = 2U;
1158 master->driverType = userConfigPtr->
driverType;
1160 master->sdaPin = userConfigPtr->
sdaPin;
1161 master->sclPin = userConfigPtr->
sclPin;
1162 master->callback = userConfigPtr->
callback;
1164 master->blocking =
false;
1165 master->driverIdle =
true;
1169 FLEXIO_I2C_DRV_MasterConfigure(master, inputClock, userConfigPtr->
baudRate);
1172 switch (master->driverType)
1175 master->flexioCommon.isr = FLEXIO_I2C_DRV_MasterCheckStatus;
1185 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(master->flexioCommon.resourceIndex)];
1186 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(master->flexioCommon.resourceIndex)];
1190 master->flexioCommon.isr = FLEXIO_I2C_DRV_MasterEndDmaTransfer;
1238 uint32_t inputClock;
1240 uint8_t resourceIndex;
1244 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1245 resourceIndex = master->flexioCommon.resourceIndex;
1255 FLEXIO_I2C_DRV_MasterComputeBaudRateDivider(baudRate, ÷r, inputClock);
1259 timerCmp = (uint16_t)((timerCmp & 0xFF00U) | divider);
1277 uint32_t inputClock;
1281 uint8_t resourceIndex;
1285 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1286 resourceIndex = master->flexioCommon.resourceIndex;
1295 divider = (uint16_t)(timerCmp & 0x00FFU);
1298 *baudRate = (inputClock + divider + 2U) / (2U * ((uint32_t)divider + 2U));
1319 master->slaveAddress = address;
1332 const uint8_t * txBuff,
1340 return FLEXIO_I2C_DRV_MasterStartTransfer(master, (uint8_t *)txBuff, txSize, sendStop,
false);
1352 const uint8_t * txBuff,
1366 master->blocking =
true;
1369 status = FLEXIO_I2C_DRV_MasterStartTransfer(master, (uint8_t *)txBuff, txSize, sendStop,
false);
1373 master->blocking =
false;
1378 return FLEXIO_I2C_DRV_MasterWaitTransferEnd(master, timeout);
1398 return FLEXIO_I2C_DRV_MasterStartTransfer(master, rxBuff, rxSize, sendStop,
true);
1424 master->blocking =
true;
1427 status = FLEXIO_I2C_DRV_MasterStartTransfer(master, rxBuff, rxSize, sendStop,
true);
1431 master->blocking =
false;
1436 return FLEXIO_I2C_DRV_MasterWaitTransferEnd(master, timeout);
1460 FLEXIO_I2C_DRV_MasterStopTransfer(master);
1480 FLEXIO_I2C_DRV_MasterCheckStatus(master);
1483 if (bytesRemaining != NULL)
1487 *bytesRemaining = master->rxRemainingBytes;
1490 if (!master->driverIdle)
1496 return master->status;
eDMA TCD Implements : edma_software_tcd_t_Class
static void FLEXIO_HAL_SetShifterInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the shifter interrupts.
static void FLEXIO_HAL_SetShifterMode(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_mode_t mode)
Sets the mode of the specified shifter.
static uint16_t FLEXIO_HAL_GetTimerCompare(const FLEXIO_Type *baseAddr, uint8_t timer)
Returns the compare value of the specified timer.
DMAMUX_Type *const g_dmamuxBase[DMAMUX_INSTANCE_COUNT]
Array for DMAMUX module register base address.
static void FLEXIO_HAL_SetTimerControl(FLEXIO_Type *baseAddr, uint8_t timer, uint8_t trigger, flexio_trigger_polarity_t triggerPolarity, flexio_trigger_source_t triggerSource, uint8_t pin, flexio_pin_polarity_t pinPolarity, flexio_pin_config_t pinConfig, flexio_timer_mode_t mode)
Sets all control settings for specified timer.
static uint8_t FLEXIO_HAL_GetPinData(const FLEXIO_Type *baseAddr)
Returns the current input data read from the FlexIO pins.
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
static bool FLEXIO_HAL_GetTimerStatus(const FLEXIO_Type *baseAddr, uint8_t timer)
Returns the current status of the specified timer.
#define FLEXIO_I2C_MAX_SIZE
Maximum size of a transfer. The restriction is that the total number of SCL edges must not exceed 8 b...
static void FLEXIO_HAL_SetTimerMode(FLEXIO_Type *baseAddr, uint8_t timer, flexio_timer_mode_t mode)
Sets the mode of the specified timer.
FLEXIO_Type *const g_flexioBase[FLEXIO_INSTANCE_COUNT]
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
#define FLEXIO_INSTANCE_COUNT
void EDMA_HAL_TCDSetMajorCount(DMA_Type *base, uint32_t channel, uint32_t count)
Sets the major iteration count according to minor loop channel link setting.
status_t FLEXIO_I2C_DRV_MasterInit(uint32_t instance, const flexio_i2c_master_user_config_t *userConfigPtr, flexio_i2c_master_state_t *master)
Initialize the FLEXIO_I2C master mode driver.
static void FLEXIO_HAL_WriteShifterBuffer(FLEXIO_Type *baseAddr, uint8_t shifter, uint32_t value, flexio_shifter_buffer_mode_t mode)
Writes a value in the specified shifter buffer.
static void FLEXIO_HAL_SetShifterPinConfig(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_pin_config_t config)
Configures the pin assigned to the specified shifter.
static void FLEXIO_HAL_ClearTimerStatus(FLEXIO_Type *baseAddr, uint8_t timer)
Clears the status of the specified timer.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
static void FLEXIO_HAL_SetTimerInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the timer interrupts.
static void FLEXIO_HAL_SetShifterConfig(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_start_t start, flexio_shifter_stop_t stop, flexio_shifter_source_t source)
Sets all configuration settings for specified shifter.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
status_t FLEXIO_I2C_DRV_MasterGetBaudRate(flexio_i2c_master_state_t *master, uint32_t *baudRate)
Get the currently configured baud rate.
static uint32_t FLEXIO_HAL_ReadShifterBuffer(const FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_buffer_mode_t mode)
Reads the value from the specified shifter buffer.
flexio_callback_t callback
flexio_driver_type_t driverType
#define STCD_ADDR(address)
static void EDMA_HAL_TCDSetSrcOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the source address signed offset for the hardware TCD.
__IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT]
static void FLEXIO_HAL_SetShifterControl(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_mode_t mode, uint8_t pin, flexio_pin_polarity_t pinPolarity, flexio_pin_config_t pinConfig, uint8_t timer, flexio_timer_polarity_t timerPolarity)
Sets all control settings for the specified shifter.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
status_t FLEXIO_I2C_DRV_MasterSetSlaveAddr(flexio_i2c_master_state_t *master, uint16_t address)
Set the slave address for any subsequent I2C communication.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
status_t EDMA_DRV_ConfigScatterGatherTransfer(uint8_t channel, edma_software_tcd_t *stcd, edma_transfer_size_t transferSize, uint32_t bytesOnEachRequest, const edma_scatter_gather_list_t *srcList, const edma_scatter_gather_list_t *destList, uint8_t tcdCount)
Configures the DMA transfer in a scatter-gather mode.
const uint8_t g_flexioDMASrc[FLEXIO_INSTANCE_COUNT][FEATURE_FLEXIO_MAX_SHIFTER_COUNT]
Data structure for configuring a discrete memory transfer. Implements : edma_scatter_gather_list_t_Cl...
status_t FLEXIO_I2C_DRV_MasterDeinit(flexio_i2c_master_state_t *master)
De-initialize the FLEXIO_I2C master mode driver.
static void FLEXIO_HAL_SetTimerCompare(FLEXIO_Type *baseAddr, uint8_t timer, uint16_t value)
Configures the compare value for the specified timer.
#define FLEXIO_SHIFTCFG_SSTOP(x)
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
static void FLEXIO_HAL_SetTimerConfig(FLEXIO_Type *baseAddr, uint8_t timer, flexio_timer_start_t start, flexio_timer_stop_t stop, flexio_timer_enable_t enable, flexio_timer_disable_t disable, flexio_timer_reset_t reset, flexio_timer_decrement_t decrement, flexio_timer_output_t output)
Sets all configuration settings for specified timer.
edma_transfer_type_t type
static void EDMA_HAL_TCDSetDisableDmaRequestAfterTCDDoneCmd(DMA_Type *base, uint32_t channel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
#define DMA_TCD_CSR_START(x)
status_t FLEXIO_I2C_DRV_MasterSetBaudRate(flexio_i2c_master_state_t *master, uint32_t baudRate)
Set the baud rate for any subsequent I2C communication.
__IO uint32_t SHIFTCFG[FLEXIO_SHIFTCFG_COUNT]
static void EDMA_HAL_TCDSetDestOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the destination address signed offset for the TCD.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
flexio_device_state_t * g_flexioDeviceStatePtr[FLEXIO_INSTANCE_COUNT]
DMA_Type *const g_edmaBase[DMA_INSTANCE_COUNT]
Array for the eDMA module register base address.
static bool FLEXIO_HAL_GetShifterStatus(const FLEXIO_Type *baseAddr, uint8_t shifter)
Returns the current status of the specified shifter.
static void FLEXIO_HAL_ClearShifterErrorStatus(FLEXIO_Type *baseAddr, uint8_t shifter)
Clears the error status of the specified shifter.
Master internal context structure.
#define FLEXIO_SHIFTCFG_SSTOP_MASK
static void DMAMUX_HAL_SetChannelSource(DMAMUX_Type *base, uint32_t channel, uint8_t source)
Configures the DMA request for the DMAMUX channel.
static void FLEXIO_HAL_SetShifterErrorInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the shifter error interrupts.
Master configuration structure.
status_t FLEXIO_I2C_DRV_MasterSendDataBlocking(flexio_i2c_master_state_t *master, const uint8_t *txBuff, uint32_t txSize, bool sendStop, uint32_t timeout)
Perform a blocking send transaction on the I2C bus.
static bool FLEXIO_HAL_GetShifterErrorStatus(const FLEXIO_Type *baseAddr, uint8_t shifter)
Returns the current error status of the specified shifter.
const clock_names_t g_flexioClock[FLEXIO_INSTANCE_COUNT]
status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t dataBufferSize)
Configures a simple single block data transfer with DMA.
status_t FLEXIO_I2C_DRV_MasterReceiveDataBlocking(flexio_i2c_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize, bool sendStop, uint32_t timeout)
Perform a blocking receive transaction on the I2C bus.
status_t FLEXIO_I2C_DRV_MasterTransferAbort(flexio_i2c_master_state_t *master)
Aborts a non-blocking I2C master transaction.
status_t FLEXIO_I2C_DRV_MasterReceiveData(flexio_i2c_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize, bool sendStop)
Perform a non-blocking receive transaction on the I2C bus.
static void FLEXIO_HAL_SetShifterStopBit(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_stop_t stop)
Configures the stop bit of the specified shifter.
status_t FLEXIO_I2C_DRV_MasterGetStatus(flexio_i2c_master_state_t *master, uint32_t *bytesRemaining)
Get the status of the current non-blocking I2C master transaction.
status_t FLEXIO_I2C_DRV_MasterSendData(flexio_i2c_master_state_t *master, const uint8_t *txBuff, uint32_t txSize, bool sendStop)
Perform a non-blocking send transaction on the I2C bus.
static void FLEXIO_HAL_ClearShifterStatus(FLEXIO_Type *baseAddr, uint8_t shifter)
Clears the status of the specified shifter.
#define DMA_TCD_CSR_DREQ(x)
static void FLEXIO_HAL_SetShifterDMARequest(FLEXIO_Type *baseAddr, uint8_t requestMask, bool enable)
Enables or disables the shifter DMA requests.