S32 SDK
erm_hal.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #ifndef ERM_HAL_H
20 #define ERM_HAL_H
21 
24 #include <stddef.h>
25 #include <stdbool.h>
26 #include "device_registers.h"
27 
35 /*******************************************************************************
36  * Definitions
37  ******************************************************************************/
39 #define ERM_CHANNELS_OFFSET_SIZE (4U)
40 
41 #define ERM_NCE_START (30U)
42 
43 #define ERM_SBC_START (31U)
44 
49 typedef enum
50 {
55 
56 
57 /*******************************************************************************
58  * API
59  ******************************************************************************/
65 #if defined(__cplusplus)
66 extern "C" {
67 #endif
68 
78 void ERM_HAL_Init(ERM_Type * const base);
79 
93 static inline void ERM_HAL_EnableEventInterrupt(ERM_Type * const base,
94  uint8_t channel,
95  erm_ecc_event_t eccEvent,
96  bool enable)
97 {
98  DEV_ASSERT(channel < ERM_EARn_COUNT);
99  uint32_t tempCtrl = base->CR0;
100 
101  /* Single-bit correction */
102  if (eccEvent == ERM_EVENT_SINGLE_BIT)
103  {
104  if (enable)
105  {
106  tempCtrl |= 1UL << (ERM_SBC_START - (channel * ERM_CHANNELS_OFFSET_SIZE));
107  }
108  else
109  {
110  tempCtrl &= ~(1UL << (ERM_SBC_START - (channel * ERM_CHANNELS_OFFSET_SIZE)));
111  }
112  }
113  else
114  {
115  /* Non-correctable */
116  if (eccEvent == ERM_EVENT_NON_CORRECTABLE)
117  {
118  if (enable)
119  {
120  tempCtrl |= 1UL << (ERM_NCE_START - (channel * ERM_CHANNELS_OFFSET_SIZE));
121  }
122  else
123  {
124  tempCtrl &= ~(1UL << (ERM_NCE_START - (channel * ERM_CHANNELS_OFFSET_SIZE)));
125  }
126  }
127  }
128 
129  /* Write to register */
130  base->CR0 = tempCtrl;
131 }
132 
146 static inline bool ERM_HAL_IsEventInterruptEnabled(const ERM_Type * const base,
147  uint8_t channel,
148  erm_ecc_event_t eccEvent)
149 {
150  DEV_ASSERT(channel < ERM_EARn_COUNT);
151  bool retVal = false;
152 
153  /* Single-bit correction */
154  if (eccEvent == ERM_EVENT_SINGLE_BIT)
155  {
156  retVal = (((base->CR0 >> (ERM_SBC_START - (channel * ERM_CHANNELS_OFFSET_SIZE))) & 1U) != 0U);
157  }
158  else
159  {
160  /* Non-correctable */
161  if (eccEvent == ERM_EVENT_NON_CORRECTABLE)
162  {
163  retVal = (((base->CR0 >> (ERM_NCE_START - (channel * ERM_CHANNELS_OFFSET_SIZE))) & 1U) != 0U);
164  }
165  }
166 
167  return retVal;
168 }
169 
183 static inline bool ERM_HAL_IsEventDetected(const ERM_Type * const base,
184  uint8_t channel,
185  erm_ecc_event_t eccEvent)
186 {
187  DEV_ASSERT(channel < ERM_EARn_COUNT);
188  uint32_t retVal = 0U;
189 
190  /* Single-bit correction */
191  if (eccEvent == ERM_EVENT_SINGLE_BIT)
192  {
193  retVal = base->SR0 >> (ERM_SBC_START - (channel * ERM_CHANNELS_OFFSET_SIZE));
194  }
195  else
196  {
197  /* Non-correctable */
198  if (eccEvent == ERM_EVENT_NON_CORRECTABLE)
199  {
200  retVal = base->SR0 >> (ERM_NCE_START - (channel * ERM_CHANNELS_OFFSET_SIZE));
201  }
202  }
203 
204  return (retVal & 1U) != 0U;
205 }
206 
217 static inline void ERM_HAL_ClearEvent(ERM_Type * const base,
218  uint8_t channel,
219  erm_ecc_event_t eccEvent)
220 {
221  DEV_ASSERT(channel < ERM_EARn_COUNT);
222 
223  /* Single-bit correction */
224  if (eccEvent == ERM_EVENT_SINGLE_BIT)
225  {
226  base->SR0 = 1UL << (ERM_SBC_START - (channel * ERM_CHANNELS_OFFSET_SIZE));
227  }
228  else
229  {
230  /* Non-correctable */
231  if (eccEvent == ERM_EVENT_NON_CORRECTABLE)
232  {
233  base->SR0 = 1UL << (ERM_NCE_START - (channel * ERM_CHANNELS_OFFSET_SIZE));
234  }
235  }
236 
237 #ifdef ERRATA_E9005
238  /* Read-after-write sequence to guarantee required serialization of memory operations */
239  (void)base->SR0;
240 #endif
241 }
242 
253 static inline uint32_t ERM_HAL_GetLastErrorAddress(const ERM_Type * const base,
254  uint8_t channel)
255 {
256  DEV_ASSERT(channel < ERM_EARn_COUNT);
257 
258  return base->EARn[channel].EAR;
259 }
260 
272  uint8_t channel,
273  uint32_t * addressPtr);
274 
277 #if defined(__cplusplus)
278 }
279 #endif
280 
283 #endif /* ERM_HAL_H */
284 /*******************************************************************************
285  * EOF
286  ******************************************************************************/
__I uint32_t EAR
Definition: S32K144.h:3264
static bool ERM_HAL_IsEventInterruptEnabled(const ERM_Type *const base, uint8_t channel, erm_ecc_event_t eccEvent)
Checks if the Memory n interrupt event is enabled.
Definition: erm_hal.h:146
static void ERM_HAL_EnableEventInterrupt(ERM_Type *const base, uint8_t channel, erm_ecc_event_t eccEvent, bool enable)
Enables Memory n interrupt event.
Definition: erm_hal.h:93
void ERM_HAL_Init(ERM_Type *const base)
Initializes the ERM module.
Definition: erm_hal.c:44
#define ERM_SBC_START
Start bit of single bit correction.
Definition: erm_hal.h:43
static uint32_t ERM_HAL_GetLastErrorAddress(const ERM_Type *const base, uint8_t channel)
Gets the address of the last ECC event in Memory n.
Definition: erm_hal.h:253
#define ERM_EARn_COUNT
Definition: S32K144.h:3255
__IO uint32_t CR0
Definition: S32K144.h:3259
#define DEV_ASSERT(x)
Definition: devassert.h:78
erm_ecc_event_t
ERM types of ECC events Implements : erm_ecc_event_t_Class.
Definition: erm_hal.h:49
#define ERM_CHANNELS_OFFSET_SIZE
The distance between channels.
Definition: erm_hal.h:39
static void ERM_HAL_ClearEvent(ERM_Type *const base, uint8_t channel, erm_ecc_event_t eccEvent)
Clears error event and the corresponding interrupt notification.
Definition: erm_hal.h:217
erm_ecc_event_t ERM_HAL_GetErrorDetail(const ERM_Type *const base, uint8_t channel, uint32_t *addressPtr)
Gets the address of the last ECC event in Memory n and ECC event.
Definition: erm_hal.c:59
static bool ERM_HAL_IsEventDetected(const ERM_Type *const base, uint8_t channel, erm_ecc_event_t eccEvent)
Checks if the Memory n error event is detected.
Definition: erm_hal.h:183
struct ERM_Type::@11 EARn[ERM_EARn_COUNT]
#define ERM_NCE_START
Start bit of non correctable error.
Definition: erm_hal.h:41
__IO uint32_t SR0
Definition: S32K144.h:3261