S32 SDK

Detailed Description

Memory Protection Unit Peripheral Driver.

Pre-Initialization information of MPU module

  1. Before using the MPU driver the protocol clock of the module must be configured by the application using PCC module.
  2. Bus fault or Hard fault exception must be configured to handle MPU access violation.

To initialize the MPU module, call the MPU_DRV_Init() function and provide the user configuration data structure. This function sets the configuration of the MPU module automatically and enables the MPU module.
Note that the configuration for region 0:

This is example code to configure the MPU driver:

/* Device instance number */
#define MEMPROTECT1 (0U)
/* Number of region in user configuration */
#define MPU_NUM_OF_REGION_CFG0 (3U)
/* Master access rights configuration 0 */
mpu_master_access_right_t AccessRightConfig0[] =
{
/* CORE_0 */
{
.masterNum = FEATURE_MPU_MASTER_CORE, /* Master number */
.accessRight = MPU_SUPERVISOR_USER_NONE, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
},
/* DEBUGGER_0 */
{
.masterNum = FEATURE_MPU_MASTER_DEBUGGER, /* Master number */
.accessRight = MPU_SUPERVISOR_USER_RWX, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
},
/* DMA_0 */
{
.masterNum = FEATURE_MPU_MASTER_DMA, /* Master number */
.accessRight = MPU_SUPERVISOR_USER_RW, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
}
};
/* Master access rights configuration 1 */
mpu_master_access_right_t AccessRightConfig1[] =
{
/* CORE_1 */
{
.masterNum = FEATURE_MPU_MASTER_CORE, /* Master number */
.accessRight = MPU_SUPERVISOR_RWX_USER_NONE, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
},
/* DEBUGGER_1 */
{
.masterNum = FEATURE_MPU_MASTER_DEBUGGER, /* Master number */
.accessRight = MPU_SUPERVISOR_USER_RWX, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
},
/* DMA_1 */
{
.masterNum = FEATURE_MPU_MASTER_DMA, /* Master number */
.accessRight = MPU_SUPERVISOR_USER_RW, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
}
};
/* Master access rights configuration 2 */
mpu_master_access_right_t AccessRightConfig2[] =
{
/* CORE_2 */
{
.masterNum = FEATURE_MPU_MASTER_CORE, /* Master number */
.accessRight = MPU_SUPERVISOR_USER_WX, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
},
/* DEBUGGER_2 */
{
.masterNum = FEATURE_MPU_MASTER_DEBUGGER, /* Master number */
.accessRight = MPU_SUPERVISOR_USER_RWX, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
},
/* DMA_2 */
{
.masterNum = FEATURE_MPU_MASTER_DMA, /* Master number */
.accessRight = MPU_SUPERVISOR_USER_RW, /* Access right */
.processIdentifierEnable = false /* Disable identifier */
}
};
/* User configuration 0 */
const mpu_user_config_t memProtect1_UserConfig0[] =
{
/* Region 0 */
{
.startAddr = 0x00000000UL, /* Memory region start address */
.endAddr = 0xFFFFFFFFUL, /* Memory region end address */
.masterAccRight = AccessRightConfig0, /* Master access right */
.processIdentifier = 0U, /* Process identifier */
.processIdMask = 0U /* Process identifier mask */
},
/* Region 1 */
{
.startAddr = 0x00000000UL, /* Memory region start address */
.endAddr = 0x00080000UL, /* Memory region end address */
.masterAccRight = AccessRightConfig1, /* Master access right */
.processIdentifier = 0U, /* Process identifier */
.processIdMask = 0U /* Process identifier mask */
},
/* Region 2 */
{
.startAddr = 0x1FF00000UL, /* Memory region start address */
.endAddr = 0x20000000UL, /* Memory region end address */
.masterAccRight = AccessRightConfig2, /* Master access right */
.processIdentifier = 0U, /* Process identifier */
.processIdMask = 0U /* Process identifier mask */
}
};
/* Initializes the MPU module */
MPU_DRV_Init(MEMPROTECT1, MPU_NUM_OF_REGION_CFG0, memProtect1_UserConfig0);

After MPU initialization:
The MPU_DRV_Deinit() can be used to reset by default and disable MPU module.
The MPU_DRV_SetMasterAccessRights() can be used to change the access rights for special master ports and for special region numbers.
The MPU_DRV_SetRegionAddr() can be used to change the start/end address for a region.
The MPU_DRV_SetRegionConfig() can be used to set the whole region with the start/end address with access rights.
The MPU_DRV_GetDetailErrorAccessInfo() API is provided to get the error status of a special slave port.
When an error happens in this port, the MPU_DRV_GetDetailErrorAccessInfo() API is provided to get the detailed error information.

Data Structures

struct  mpu_master_access_right_t
 MPU master access rights. Implements : mpu_master_access_right_t_Class. More...
 
struct  mpu_user_config_t
 MPU user region configuration structure. This structure is used when calling the MPU_DRV_Init function. Implements : mpu_user_config_t_Class. More...
 

Macros

#define MPU_USER_MASK   (0x07U)
 
#define MPU_USER_SHIFT   (0U)
 
#define MPU_SUPERVISOR_MASK   (0x18U)
 
#define MPU_SUPERVISOR_SHIFT   (3U)
 
#define MPU_W_MASK   (0x20U)
 
#define MPU_W_SHIFT   (5U)
 
#define MPU_R_MASK   (0x40U)
 
#define MPU_R_SHIFT   (6U)
 

Enumerations

enum  mpu_access_rights_t {
  MPU_SUPERVISOR_RWX_USER_NONE = 0x00U, MPU_SUPERVISOR_RWX_USER_X = 0x01U, MPU_SUPERVISOR_RWX_USER_W = 0x02U, MPU_SUPERVISOR_RWX_USER_WX = 0x03U,
  MPU_SUPERVISOR_RWX_USER_R = 0x04U, MPU_SUPERVISOR_RWX_USER_RX = 0x05U, MPU_SUPERVISOR_RWX_USER_RW = 0x06U, MPU_SUPERVISOR_RWX_USER_RWX = 0x07U,
  MPU_SUPERVISOR_RX_USER_NONE = 0x08U, MPU_SUPERVISOR_RX_USER_X = 0x09U, MPU_SUPERVISOR_RX_USER_W = 0x0AU, MPU_SUPERVISOR_RX_USER_WX = 0x0BU,
  MPU_SUPERVISOR_RX_USER_R = 0x0CU, MPU_SUPERVISOR_RX_USER_RX = 0x0DU, MPU_SUPERVISOR_RX_USER_RW = 0x0EU, MPU_SUPERVISOR_RX_USER_RWX = 0x0FU,
  MPU_SUPERVISOR_RW_USER_NONE = 0x10U, MPU_SUPERVISOR_RW_USER_X = 0x11U, MPU_SUPERVISOR_RW_USER_W = 0x12U, MPU_SUPERVISOR_RW_USER_WX = 0x13U,
  MPU_SUPERVISOR_RW_USER_R = 0x14U, MPU_SUPERVISOR_RW_USER_RX = 0x15U, MPU_SUPERVISOR_RW_USER_RW = 0x16U, MPU_SUPERVISOR_RW_USER_RWX = 0x17U,
  MPU_SUPERVISOR_USER_NONE = 0x18U, MPU_SUPERVISOR_USER_X = 0x19U, MPU_SUPERVISOR_USER_W = 0x1AU, MPU_SUPERVISOR_USER_WX = 0x1BU,
  MPU_SUPERVISOR_USER_R = 0x1CU, MPU_SUPERVISOR_USER_RX = 0x1DU, MPU_SUPERVISOR_USER_RW = 0x1EU, MPU_SUPERVISOR_USER_RWX = 0x1FU,
  MPU_NONE = 0x80U, MPU_W = 0xA0U, MPU_R = 0xC0U, MPU_RW = 0xE0U
}
 MPU access rights.

Code Supervisor User Description
MPU_SUPERVISOR_RWX_USER_NONE r w x - - - Allow Read, write, execute in supervisor mode; no access in user mode
MPU_SUPERVISOR_RWX_USER_X r w x - - x Allow Read, write, execute in supervisor mode; execute in user mode
MPU_SUPERVISOR_RWX_USER_W r w x - w - Allow Read, write, execute in supervisor mode; write in user mode
MPU_SUPERVISOR_RWX_USER_WX r w x - w x Allow Read, write, execute in supervisor mode; write and execute in user mode
MPU_SUPERVISOR_RWX_USER_R r w x r - - Allow Read, write, execute in supervisor mode; read in user mode
MPU_SUPERVISOR_RWX_USER_RX r w x r - x Allow Read, write, execute in supervisor mode; read and execute in user mode
MPU_SUPERVISOR_RWX_USER_RW r w x r w - Allow Read, write, execute in supervisor mode; read and write in user mode
MPU_SUPERVISOR_RWX_USER_RWX r w x r w x Allow Read, write, execute in supervisor mode; read, write and execute in user mode
MPU_SUPERVISOR_RX_USER_NONE r - x - - - Allow Read, execute in supervisor mode; no access in user mode
MPU_SUPERVISOR_RX_USER_X r - x - - x Allow Read, execute in supervisor mode; execute in user mode
MPU_SUPERVISOR_RX_USER_W r - x - w - Allow Read, execute in supervisor mode; write in user mode
MPU_SUPERVISOR_RX_USER_WX r - x - w x Allow Read, execute in supervisor mode; write and execute in user mode
MPU_SUPERVISOR_RX_USER_R r - x r - - Allow Read, execute in supervisor mode; read in user mode
MPU_SUPERVISOR_RX_USER_RX r - x r - x Allow Read, execute in supervisor mode; read and execute in user mode
MPU_SUPERVISOR_RX_USER_RW r - x r w - Allow Read, execute in supervisor mode; read and write in user mode
MPU_SUPERVISOR_RX_USER_RWX r - x r w x Allow Read, execute in supervisor mode; read, write and execute in user mode
MPU_SUPERVISOR_RW_USER_NONE r w - - - - Allow Read, write in supervisor mode; no access in user mode
MPU_SUPERVISOR_RW_USER_X r w - - - x Allow Read, write in supervisor mode; execute in user mode
MPU_SUPERVISOR_RW_USER_W r w - - w - Allow Read, write in supervisor mode; write in user mode
MPU_SUPERVISOR_RW_USER_WX r w - - w x Allow Read, write in supervisor mode; write and execute in user mode
MPU_SUPERVISOR_RW_USER_R r w - r - - Allow Read, write in supervisor mode; read in user mode
MPU_SUPERVISOR_RW_USER_RX r w - r - x Allow Read, write in supervisor mode; read and execute in user mode
MPU_SUPERVISOR_RW_USER_RW r w - r w - Allow Read, write in supervisor mode; read and write in user mode
MPU_SUPERVISOR_RW_USER_RWX r w - r w x Allow Read, write in supervisor mode; read, write and execute in user mode
MPU_SUPERVISOR_USER_NONE - - - - - - No access allowed in user and supervisor modes
MPU_SUPERVISOR_USER_X - - x - - x Execute operation is allowed in user and supervisor modes
MPU_SUPERVISOR_USER_W - w - - w - Write operation is allowed in user and supervisor modes
MPU_SUPERVISOR_USER_WX - w x - w x Write and execute operations are allowed in user and supervisor modes
MPU_SUPERVISOR_USER_R r - - r - - Read operation is allowed in user and supervisor modes
MPU_SUPERVISOR_USER_RX r - x r - x Read and execute operations are allowed in user and supervisor modes
MPU_SUPERVISOR_USER_RW r w - r w - Read and write operations are allowed in user and supervisor modes
MPU_SUPERVISOR_USER_RWX r w x r w x Read write and execute operations are allowed in user and supervisor modes
More...
 

Variables

MPU_Type *const g_mpuBase [MPU_INSTANCE_COUNT]
 Table of base addresses for MPU instances. More...
 

MPU Driver API

status_t MPU_DRV_Init (uint32_t instance, uint8_t regionCnt, const mpu_user_config_t *userConfigArr)
 The function sets the MPU regions according to user input and then enables the MPU. Please note that access rights for region 0 will always be configured and regionCnt takes values between 1 and the maximum region count supported by the hardware. e.g. In S32K144 the number of supported regions is 8. The user must make sure that the clock is enabled. More...
 
void MPU_DRV_Deinit (uint32_t instance)
 De-initializes the MPU region by resetting and disabling MPU module. More...
 
void MPU_DRV_SetRegionAddr (uint32_t instance, uint8_t regionNum, uint32_t startAddr, uint32_t endAddr)
 Sets the region start and end address. More...
 
status_t MPU_DRV_SetRegionConfig (uint32_t instance, uint8_t regionNum, const mpu_user_config_t *userConfigPtr)
 Sets the region configuration. More...
 
status_t MPU_DRV_SetMasterAccessRights (uint32_t instance, uint8_t regionNum, const mpu_master_access_right_t *accessRightsPtr)
 Configures access permission. More...
 
void MPU_DRV_GetDetailErrorAccessInfo (uint32_t instance, uint8_t slavePortNum, mpu_access_err_info_t *errInfoPtr)
 Gets the MPU access error detail information for a slave port. More...
 

Macro Definition Documentation

#define MPU_R_MASK   (0x40U)

Definition at line 52 of file mpu_driver.h.

#define MPU_R_SHIFT   (6U)

Definition at line 53 of file mpu_driver.h.

#define MPU_SUPERVISOR_MASK   (0x18U)

Definition at line 48 of file mpu_driver.h.

#define MPU_SUPERVISOR_SHIFT   (3U)

Definition at line 49 of file mpu_driver.h.

#define MPU_USER_MASK   (0x07U)

Definition at line 46 of file mpu_driver.h.

#define MPU_USER_SHIFT   (0U)

Definition at line 47 of file mpu_driver.h.

#define MPU_W_MASK   (0x20U)

Definition at line 50 of file mpu_driver.h.

#define MPU_W_SHIFT   (5U)

Definition at line 51 of file mpu_driver.h.

Enumeration Type Documentation

MPU access rights.

Code Supervisor User Description
MPU_SUPERVISOR_RWX_USER_NONE r w x - - - Allow Read, write, execute in supervisor mode; no access in user mode
MPU_SUPERVISOR_RWX_USER_X r w x - - x Allow Read, write, execute in supervisor mode; execute in user mode
MPU_SUPERVISOR_RWX_USER_W r w x - w - Allow Read, write, execute in supervisor mode; write in user mode
MPU_SUPERVISOR_RWX_USER_WX r w x - w x Allow Read, write, execute in supervisor mode; write and execute in user mode
MPU_SUPERVISOR_RWX_USER_R r w x r - - Allow Read, write, execute in supervisor mode; read in user mode
MPU_SUPERVISOR_RWX_USER_RX r w x r - x Allow Read, write, execute in supervisor mode; read and execute in user mode
MPU_SUPERVISOR_RWX_USER_RW r w x r w - Allow Read, write, execute in supervisor mode; read and write in user mode
MPU_SUPERVISOR_RWX_USER_RWX r w x r w x Allow Read, write, execute in supervisor mode; read, write and execute in user mode
MPU_SUPERVISOR_RX_USER_NONE r - x - - - Allow Read, execute in supervisor mode; no access in user mode
MPU_SUPERVISOR_RX_USER_X r - x - - x Allow Read, execute in supervisor mode; execute in user mode
MPU_SUPERVISOR_RX_USER_W r - x - w - Allow Read, execute in supervisor mode; write in user mode
MPU_SUPERVISOR_RX_USER_WX r - x - w x Allow Read, execute in supervisor mode; write and execute in user mode
MPU_SUPERVISOR_RX_USER_R r - x r - - Allow Read, execute in supervisor mode; read in user mode
MPU_SUPERVISOR_RX_USER_RX r - x r - x Allow Read, execute in supervisor mode; read and execute in user mode
MPU_SUPERVISOR_RX_USER_RW r - x r w - Allow Read, execute in supervisor mode; read and write in user mode
MPU_SUPERVISOR_RX_USER_RWX r - x r w x Allow Read, execute in supervisor mode; read, write and execute in user mode
MPU_SUPERVISOR_RW_USER_NONE r w - - - - Allow Read, write in supervisor mode; no access in user mode
MPU_SUPERVISOR_RW_USER_X r w - - - x Allow Read, write in supervisor mode; execute in user mode
MPU_SUPERVISOR_RW_USER_W r w - - w - Allow Read, write in supervisor mode; write in user mode
MPU_SUPERVISOR_RW_USER_WX r w - - w x Allow Read, write in supervisor mode; write and execute in user mode
MPU_SUPERVISOR_RW_USER_R r w - r - - Allow Read, write in supervisor mode; read in user mode
MPU_SUPERVISOR_RW_USER_RX r w - r - x Allow Read, write in supervisor mode; read and execute in user mode
MPU_SUPERVISOR_RW_USER_RW r w - r w - Allow Read, write in supervisor mode; read and write in user mode
MPU_SUPERVISOR_RW_USER_RWX r w - r w x Allow Read, write in supervisor mode; read, write and execute in user mode
MPU_SUPERVISOR_USER_NONE - - - - - - No access allowed in user and supervisor modes
MPU_SUPERVISOR_USER_X - - x - - x Execute operation is allowed in user and supervisor modes
MPU_SUPERVISOR_USER_W - w - - w - Write operation is allowed in user and supervisor modes
MPU_SUPERVISOR_USER_WX - w x - w x Write and execute operations are allowed in user and supervisor modes
MPU_SUPERVISOR_USER_R r - - r - - Read operation is allowed in user and supervisor modes
MPU_SUPERVISOR_USER_RX r - x r - x Read and execute operations are allowed in user and supervisor modes
MPU_SUPERVISOR_USER_RW r w - r w - Read and write operations are allowed in user and supervisor modes
MPU_SUPERVISOR_USER_RWX r w x r w x Read write and execute operations are allowed in user and supervisor modes

Code Read/Write permission Description
MPU_NONE - - No Read/Write access permission
MPU_W - w Write access permission
MPU_R r - Read access permission
MPU_RW r w Read/Write access permission

Implements : mpu_access_rights_t_Class

Enumerator
MPU_SUPERVISOR_RWX_USER_NONE 

0b00000000U : rwx|—

MPU_SUPERVISOR_RWX_USER_X 

0b00000001U : rwx|–x

MPU_SUPERVISOR_RWX_USER_W 

0b00000010U : rwx|-w-

MPU_SUPERVISOR_RWX_USER_WX 

0b00000011U : rwx|-wx

MPU_SUPERVISOR_RWX_USER_R 

0b00000100U : rwx|r–

MPU_SUPERVISOR_RWX_USER_RX 

0b00000101U : rwx|r-x

MPU_SUPERVISOR_RWX_USER_RW 

0b00000110U : rwx|rw-

MPU_SUPERVISOR_RWX_USER_RWX 

0b00000111U : rwx|rwx

MPU_SUPERVISOR_RX_USER_NONE 

0b00001000U : r-x|—

MPU_SUPERVISOR_RX_USER_X 

0b00001001U : r-x|–x

MPU_SUPERVISOR_RX_USER_W 

0b00001010U : r-x|-w-

MPU_SUPERVISOR_RX_USER_WX 

0b00001011U : r-x|-wx

MPU_SUPERVISOR_RX_USER_R 

0b00001100U : r-x|r–

MPU_SUPERVISOR_RX_USER_RX 

0b00001101U : r-x|r-x

MPU_SUPERVISOR_RX_USER_RW 

0b00001110U : r-x|rw-

MPU_SUPERVISOR_RX_USER_RWX 

0b00001111U : r-x|rwx

MPU_SUPERVISOR_RW_USER_NONE 

0b00010000U : rw-|—

MPU_SUPERVISOR_RW_USER_X 

0b00010001U : rw-|–x

MPU_SUPERVISOR_RW_USER_W 

0b00010010U : rw-|-w-

MPU_SUPERVISOR_RW_USER_WX 

0b00010011U : rw-|-wx

MPU_SUPERVISOR_RW_USER_R 

0b00010100U : rw-|r–

MPU_SUPERVISOR_RW_USER_RX 

0b00010101U : rw-|r-x

MPU_SUPERVISOR_RW_USER_RW 

0b00010110U : rw-|rw-

MPU_SUPERVISOR_RW_USER_RWX 

0b00010111U : rw-|rwx

MPU_SUPERVISOR_USER_NONE 

0b00011000U : —|—

MPU_SUPERVISOR_USER_X 

0b00011001U : –x|–x

MPU_SUPERVISOR_USER_W 

0b00011010U : -w-|-w-

MPU_SUPERVISOR_USER_WX 

0b00011011U : -wx|-wx

MPU_SUPERVISOR_USER_R 

0b00011100U : r–|r–

MPU_SUPERVISOR_USER_RX 

0b00011101U : r-x|r-x

MPU_SUPERVISOR_USER_RW 

0b00011110U : rw-|rw-

MPU_SUPERVISOR_USER_RWX 

0b00011111U : rwx|rwx

MPU_NONE 

0b10000000U : –

MPU_W 

0b10100000U : w-

MPU_R 

0b11000000U : -r

MPU_RW 

0b11100000U : wr

Definition at line 101 of file mpu_driver.h.

Function Documentation

void MPU_DRV_Deinit ( uint32_t  instance)

De-initializes the MPU region by resetting and disabling MPU module.

Parameters
[in]instanceThe MPU peripheral instance number.

Definition at line 149 of file mpu_driver.c.

void MPU_DRV_GetDetailErrorAccessInfo ( uint32_t  instance,
uint8_t  slavePortNum,
mpu_access_err_info_t errInfoPtr 
)

Gets the MPU access error detail information for a slave port.

Parameters
[in]instanceThe MPU peripheral instance number.
[in]slavePortNumThe slave port number to get Error Detail.
[out]errInfoPtrA pointer to access error info structure.

Definition at line 325 of file mpu_driver.c.

status_t MPU_DRV_Init ( uint32_t  instance,
uint8_t  regionCnt,
const mpu_user_config_t userConfigArr 
)

The function sets the MPU regions according to user input and then enables the MPU. Please note that access rights for region 0 will always be configured and regionCnt takes values between 1 and the maximum region count supported by the hardware. e.g. In S32K144 the number of supported regions is 8. The user must make sure that the clock is enabled.

Parameters
[in]instanceThe MPU peripheral instance number.
[in]regionCntNumber of configuration regions.
[in]userConfigArrThe pointer to the array of MPU user configure structure, see mpu_user_config_t.
Returns
operation status
  • STATUS_SUCCESS: Operation was successful.
  • STATUS_ERROR: Operation failed due to master number is out of range supported by hardware.

Definition at line 85 of file mpu_driver.c.

status_t MPU_DRV_SetMasterAccessRights ( uint32_t  instance,
uint8_t  regionNum,
const mpu_master_access_right_t accessRightsPtr 
)

Configures access permission.

Parameters
[in]instanceThe MPU peripheral instance number.
[in]regionNumThe MPU region number.
[in]accessRightsPtrA pointer to access permission structure.
Returns
operation status
  • STATUS_SUCCESS: Operation was successful.
  • STATUS_ERROR: Operation failed due to master number is out of range supported by hardware.

Definition at line 273 of file mpu_driver.c.

void MPU_DRV_SetRegionAddr ( uint32_t  instance,
uint8_t  regionNum,
uint32_t  startAddr,
uint32_t  endAddr 
)

Sets the region start and end address.

Parameters
[in]instanceThe MPU peripheral instance number.
[in]regionNumThe region number.
[in]startAddrRegion start address.
[in]endAddrRegion end address.

Definition at line 168 of file mpu_driver.c.

status_t MPU_DRV_SetRegionConfig ( uint32_t  instance,
uint8_t  regionNum,
const mpu_user_config_t userConfigPtr 
)

Sets the region configuration.

Parameters
[in]instanceThe MPU peripheral instance number.
[in]regionNumThe region number.
[in]userConfigPtrRegion configuration structure pointer.
Returns
operation status
  • STATUS_SUCCESS: Operation was successful.
  • STATUS_ERROR: Operation failed due to master number is out of range supported by hardware.

Definition at line 195 of file mpu_driver.c.

Variable Documentation

MPU_Type* const g_mpuBase[MPU_INSTANCE_COUNT]

Table of base addresses for MPU instances.

Definition at line 69 of file mpu_driver.c.