S32 SDK
adc_hal.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #ifndef ADC_HAL_H
20 #define ADC_HAL_H
21 
22 #include <stdint.h>
23 #include <stdbool.h>
24 #include "device_registers.h"
25 
48 /*******************************************************************************
49  * Definitions
50  ******************************************************************************/
55 typedef enum
56 {
57  ADC_CLK_DIVIDE_1 = 0x00U,
58  ADC_CLK_DIVIDE_2 = 0x01U,
59  ADC_CLK_DIVIDE_4 = 0x02U,
62 
67 typedef enum
68 {
73 
78 typedef enum
79 {
80  ADC_CLK_ALT_1 = 0x00U,
81  ADC_CLK_ALT_2 = 0x01U,
82  ADC_CLK_ALT_3 = 0x02U,
83  ADC_CLK_ALT_4 = 0x03U
85 
90 typedef enum
91 {
95 
100 typedef enum
101 {
105 
110 typedef enum
111 {
112  ADC_AVERAGE_4 = 0x00U,
113  ADC_AVERAGE_8 = 0x01U,
114  ADC_AVERAGE_16 = 0x02U,
115  ADC_AVERAGE_32 = 0x03U
116 } adc_average_t;
117 
128 typedef enum
129 {
163 
166 /*******************************************************************************
167  * API
168  ******************************************************************************/
169 
170 #if defined (__cplusplus)
171 extern "C" {
172 #endif
173 
190 void ADC_HAL_Init(ADC_Type * const baseAddr);
191 
204 static inline bool ADC_HAL_GetConvActiveFlag(const ADC_Type * const baseAddr)
205 {
206  uint32_t tmp = (uint32_t)baseAddr->SC2;
207  tmp = (tmp & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT;
208 
209  return (tmp != 0u) ? true : false;
210 }
211 
227 static inline adc_clk_divide_t ADC_HAL_GetClockDivide(const ADC_Type * const baseAddr)
228 {
229  uint32_t tmp = baseAddr->CFG1;
230  tmp = (tmp & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT;
231 
232  /* Enum defines all possible values, so casting is safe */
233  return (adc_clk_divide_t)(tmp);
234 }
235 
250 static inline void ADC_HAL_SetClockDivide(ADC_Type * const baseAddr,
251  const adc_clk_divide_t clockDivide)
252 {
253  uint32_t tmp = baseAddr->CFG1;
254  tmp &= ~(ADC_CFG1_ADIV_MASK);
255  tmp |= ADC_CFG1_ADIV(clockDivide);
256  baseAddr->CFG1 = tmp;
257 }
258 
272 static inline uint8_t ADC_HAL_GetSampleTime(const ADC_Type * const baseAddr)
273 {
274  uint32_t tmp = baseAddr->CFG2;
276 
277  return (uint8_t)(tmp);
278 }
279 
294 static inline void ADC_HAL_SetSampleTime(ADC_Type * const baseAddr,
295  uint8_t sampletime)
296 {
297  /* Clip sample time to minimum value */
298  uint8_t rsampletime = (uint8_t)((sampletime > 0U) ? sampletime : 1U);
299  uint32_t tmp = baseAddr->CFG2;
300  tmp &= ~(ADC_CFG2_SMPLTS_MASK);
301  tmp |= ADC_CFG2_SMPLTS(rsampletime);
302  baseAddr->CFG2 = tmp;
303 }
304 
319 static inline adc_resolution_t ADC_HAL_GetResolution(const ADC_Type * const baseAddr)
320 {
321  uint32_t tmp = baseAddr->CFG1;
322  tmp = (tmp & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT;
323  adc_resolution_t retValue;
324  /* Enum does not define all possible values, do a swith-case */
325  switch (tmp)
326  {
327  case 0x00U:
328  retValue = ADC_RESOLUTION_8BIT;
329  break;
330  case 0x01U:
331  retValue = ADC_RESOLUTION_12BIT;
332  break;
333  case 0x02U:
334  retValue = ADC_RESOLUTION_10BIT;
335  break;
336  default:
337  retValue = ADC_RESOLUTION_8BIT;
338  break;
339  }
340 
341  return retValue;
342 }
343 
357 static inline void ADC_HAL_SetResolution(ADC_Type * const baseAddr,
358  const adc_resolution_t resolution)
359 {
360  uint32_t tmp = baseAddr->CFG1;
361  tmp &= ~(ADC_CFG1_MODE_MASK);
362  tmp |= ADC_CFG1_MODE(resolution);
363  baseAddr->CFG1 = tmp;
364 }
365 
381 static inline adc_input_clock_t ADC_HAL_GetInputClock(const ADC_Type * const baseAddr)
382 {
383  uint32_t tmp = baseAddr->CFG1;
385 
386  /* Enum defines all possible values, so casting is safe */
387  return (adc_input_clock_t)(tmp);
388 }
389 
405 static inline void ADC_HAL_SetInputClock(ADC_Type * const baseAddr,
406  const adc_input_clock_t inputClock)
407 {
408  uint32_t tmp = baseAddr->CFG1;
409  tmp &= ~(ADC_CFG1_ADICLK_MASK);
410  tmp |= ADC_CFG1_ADICLK(inputClock);
411  baseAddr->CFG1 = tmp;
412 }
413 
431 static inline adc_trigger_t ADC_HAL_GetTriggerMode(const ADC_Type * const baseAddr)
432 {
433  uint32_t tmp = baseAddr->SC2;
434  tmp = (tmp & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT;
435 
436  /* Enum defines all possible values, so casting is safe */
437  return (adc_trigger_t)(tmp);
438 }
439 
456 static inline void ADC_HAL_SetTriggerMode(ADC_Type * const baseAddr,
457  const adc_trigger_t trigger)
458 {
459  uint32_t tmp = baseAddr->SC2;
460  tmp &= ~(ADC_SC2_ADTRG_MASK);
461  tmp |= ADC_SC2_ADTRG(trigger);
462  baseAddr->SC2 = tmp;
463 }
464 
477 static inline bool ADC_HAL_GetDMAEnableFlag(const ADC_Type * const baseAddr)
478 {
479  uint32_t tmp = (uint32_t)baseAddr->SC2;
480  tmp = (tmp & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT;
481 
482  return (tmp != 0u) ? true : false;
483 }
484 
497 static inline void ADC_HAL_SetDMAEnableFlag(ADC_Type * const baseAddr,
498  const bool state)
499 {
500  uint32_t tmp = (uint32_t)baseAddr->SC2;
501  tmp &= (uint32_t)(~(ADC_SC2_DMAEN_MASK));
502  tmp |= ADC_SC2_DMAEN(state ? (uint32_t)1u : (uint32_t)0u);
503  baseAddr->SC2 = (uint32_t)tmp;
504 }
505 
520 static inline adc_voltage_reference_t ADC_HAL_GetVoltageReference(const ADC_Type * const baseAddr)
521 {
522  uint32_t tmp = baseAddr->SC2;
523  tmp = (tmp & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT;
524 
525  /* Enum defines all possible values, so casting is safe */
526  return (adc_voltage_reference_t)(tmp);
527 }
528 
543 static inline void ADC_HAL_SetVoltageReference(ADC_Type * const baseAddr,
544  const adc_voltage_reference_t voltageRef)
545 {
546  uint32_t tmp = baseAddr->SC2;
547  tmp &= ~(ADC_SC2_REFSEL_MASK);
548  tmp |= ADC_SC2_REFSEL(voltageRef);
549  baseAddr->SC2 = tmp;
550 }
551 
566 static inline bool ADC_HAL_GetContinuousConvFlag(const ADC_Type * const baseAddr)
567 {
568  uint32_t tmp = (uint32_t)baseAddr->SC3;
569  tmp = (tmp & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT;
570 
571  return (tmp != 0u) ? true : false;
572 }
573 
588 static inline void ADC_HAL_SetContinuousConvFlag(ADC_Type * const baseAddr,
589  const bool state)
590 {
591  uint32_t tmp = (uint32_t)baseAddr->SC3;
592  /* Clear the affected bitfield and write '0' to the w1c bits to avoid side-effects */
593  tmp &= ~(ADC_SC3_ADCO_MASK);
594  tmp |= ADC_SC3_ADCO(state ? (uint32_t)1u : (uint32_t)0u);
595  baseAddr->SC3 = (uint32_t)tmp;
596 }
597 
618 static inline bool ADC_HAL_GetHwCompareEnableFlag(const ADC_Type * const baseAddr)
619 {
620  uint32_t tmp = (uint32_t)baseAddr->SC2;
621  tmp = (tmp & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT;
622 
623  return (tmp != 0u) ? true : false;
624 }
625 
638 static inline void ADC_HAL_SetHwCompareEnableFlag(ADC_Type * const baseAddr,
639  const bool state)
640 {
641  uint32_t tmp = (uint32_t)baseAddr->SC2;
642  tmp &= (uint32_t)(~(ADC_SC2_ACFE_MASK));
643  tmp |= ADC_SC2_ACFE(state ? (uint32_t)1u : (uint32_t)0u);
644  baseAddr->SC2 = (uint32_t)tmp;
645 }
646 
660 static inline bool ADC_HAL_GetHwCompareGtEnableFlag(const ADC_Type * const baseAddr)
661 {
662  uint32_t tmp = (uint32_t)baseAddr->SC2;
663  tmp = (tmp & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT;
664 
665  return (tmp != 0u) ? true : false;
666 }
667 
681 static inline void ADC_HAL_SetHwCompareGtEnableFlag(ADC_Type * const baseAddr,
682  const bool state)
683 {
684  uint32_t tmp = (uint32_t)baseAddr->SC2;
685  tmp &= (uint32_t)(~(ADC_SC2_ACFGT_MASK));
686  tmp |= ADC_SC2_ACFGT(state ? (uint32_t)1u : (uint32_t)0u);
687  baseAddr->SC2 = (uint32_t)tmp;
688 }
689 
703 static inline bool ADC_HAL_GetHwCompareRangeEnableFlag(const ADC_Type * const baseAddr)
704 {
705  uint32_t tmp = (uint32_t)baseAddr->SC2;
706  tmp = (tmp & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT;
707 
708  return (tmp != 0u) ? true : false;
709 }
710 
724 static inline void ADC_HAL_SetHwCompareRangeEnableFlag(ADC_Type * const baseAddr,
725  const bool state)
726 {
727  uint32_t tmp = (uint32_t)baseAddr->SC2;
728  tmp &= (uint32_t)(~(ADC_SC2_ACREN_MASK));
729  tmp |= ADC_SC2_ACREN(state ? (uint32_t)1u : (uint32_t)0u);
730  baseAddr->SC2 = (uint32_t)tmp;
731 }
732 
747 static inline uint16_t ADC_HAL_GetHwCompareComp1Value(const ADC_Type * const baseAddr)
748 {
749  return (uint16_t)baseAddr->CV[0U];
750 }
751 
766 static inline void ADC_HAL_SetHwCompareComp1Value(ADC_Type * const baseAddr,
767  const uint16_t value)
768 {
769  baseAddr->CV[0U] = ADC_CV_CV(value);
770 }
771 
786 static inline uint16_t ADC_HAL_GetHwCompareComp2Value(const ADC_Type * const baseAddr)
787 {
788  return (uint16_t)baseAddr->CV[1U];
789 }
790 
805 static inline void ADC_HAL_SetHwCompareComp2Value(ADC_Type * const baseAddr,
806  const uint16_t value)
807 {
808  baseAddr->CV[1U] = ADC_CV_CV(value);
809 }
810 
832 static inline bool ADC_HAL_GetHwAverageEnableFlag(const ADC_Type * const baseAddr)
833 {
834  uint32_t tmp = (uint32_t)baseAddr->SC3;
835  tmp = (tmp & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT;
836 
837  return (tmp != 0u) ? true : false;
838 }
839 
852 static inline void ADC_HAL_SetHwAverageEnableFlag(ADC_Type * const baseAddr,
853  const bool state)
854 {
855  uint32_t tmp = baseAddr->SC3;
856  /* Clear the affected bitfield */
857  tmp &= ~(ADC_SC3_AVGE_MASK);
858  tmp |= ADC_SC3_AVGE(state ? (uint32_t)1u : (uint32_t)0u);
859  baseAddr->SC3 = tmp;
860 }
861 
878 static inline adc_average_t ADC_HAL_GetHwAverageMode(const ADC_Type * const baseAddr)
879 {
880  uint32_t tmp = baseAddr->SC3;
881  tmp = (tmp & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT;
882 
883  /* Enum defines all possible values, so casting is safe */
884  return (adc_average_t)(tmp);
885 }
886 
903 static inline void ADC_HAL_SetHwAverageMode(ADC_Type * const baseAddr,
904  const adc_average_t averageMode)
905 {
906  uint32_t tmp = baseAddr->SC3;
907  /* Clear the affected bitfield */
908  tmp &= ~(ADC_SC3_AVGS_MASK);
909  tmp |= ADC_SC3_AVGS(averageMode);
910  baseAddr->SC3 = tmp;
911 }
912 
933 static inline bool ADC_HAL_GetCalibrationActiveFlag(const ADC_Type * const baseAddr)
934 {
935  uint32_t tmp = (uint32_t)baseAddr->SC3;
936  tmp = (tmp & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT;
937 
938  return (tmp != 0u) ? true : false;
939 }
940 
953 static inline void ADC_HAL_SetCalibrationActiveFlag(ADC_Type * const baseAddr,
954  const bool state)
955 {
956  uint32_t tmp = baseAddr->SC3;
957  tmp &= ~(ADC_SC3_CAL_MASK);
958  tmp |= ADC_SC3_CAL(state ? (uint32_t)1u : (uint32_t)0u);
959  baseAddr->SC3 = tmp;
960 }
961 
975 static inline uint16_t ADC_HAL_GetUserGainValue(const ADC_Type * const baseAddr)
976 {
977  uint32_t tmp = baseAddr->UG;
978  tmp = (tmp & ADC_UG_UG_MASK) >> ADC_UG_UG_SHIFT;
979 
980  return (uint16_t)tmp;
981 }
982 
995 static inline void ADC_HAL_SetUserGainValue(ADC_Type * const baseAddr,
996  const uint16_t value)
997 {
998  uint16_t clp0 = (uint16_t)baseAddr->CLP0;
999  uint16_t clp1 = (uint16_t)baseAddr->CLP1;
1000  uint16_t clp2 = (uint16_t)baseAddr->CLP2;
1001  uint16_t clp3 = (uint16_t)baseAddr->CLP3;
1002  uint16_t clps = (uint16_t)baseAddr->CLPS;
1003  /* Add CLP0, CLP1, CLP2, CLP3 and CLPS */
1004  uint16_t sum = (uint16_t)(value + clp0 + clp1 + clp2 + clp3 + clps);
1005  /* If OR of bits [15:11] from the sum is 1 (set), write 0xFFFFU to Gain register */
1006  uint16_t temp = (uint16_t)(sum & 0xF800U);
1007  if (temp != 0x0000U)
1008  {
1009  temp = 0xFFFFU;
1010  }
1011 
1012  baseAddr->UG = (uint32_t)value;
1013  baseAddr->G = (uint32_t)temp;
1014 }
1015 
1030 static inline uint16_t ADC_HAL_GetUserOffsetValue(const ADC_Type * const baseAddr)
1031 {
1032  uint32_t tmp = baseAddr->USR_OFS;
1034 
1035  return (uint16_t)tmp;
1036 }
1037 
1052 static inline void ADC_HAL_SetUserOffsetValue(ADC_Type * const baseAddr,
1053  const uint16_t value)
1054 {
1055  baseAddr->USR_OFS = ADC_USR_OFS_USR_OFS(value);
1056 }
1057 
1079 static inline bool ADC_HAL_GetChanInterruptEnableFlag(const ADC_Type * const baseAddr,
1080  const uint8_t chanIndex)
1081 {
1082  uint32_t tmp = (uint32_t)baseAddr->SC1[chanIndex];
1083  tmp = (tmp & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT;
1084 
1085  return (tmp != 0u) ? true : false;
1086 }
1087 
1102 static inline void ADC_HAL_SetChanInterruptEnableFlag(ADC_Type * const baseAddr,
1103  const uint8_t chanIndex,
1104  const bool state)
1105 {
1106  uint32_t tmp = baseAddr->SC1[chanIndex];
1107  tmp &= ~(ADC_SC1_AIEN_MASK);
1108  tmp |= ADC_SC1_AIEN(state ? (uint32_t)1u : (uint32_t)0u);
1109  /* If software trigger is configured and chanIndex is 0, this will trigger a new conversion */
1110  baseAddr->SC1[chanIndex] = tmp;
1111 }
1112 
1146 static inline adc_inputchannel_t ADC_HAL_GetInputChannel(const ADC_Type * const baseAddr,
1147  const uint8_t chanIndex)
1148 {
1149  uint32_t tmp = baseAddr->SC1[chanIndex];
1150  tmp = (tmp & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT;
1151 
1152  /* Enum defines all possible values, so casting is safe */
1153  return (adc_inputchannel_t)(tmp);
1154 }
1155 
1190 static inline void ADC_HAL_SetInputChannel(ADC_Type * const baseAddr,
1191  const uint8_t chanIndex,
1192  const adc_inputchannel_t inputChan)
1193 {
1194  uint32_t tmp = baseAddr->SC1[chanIndex];
1195  tmp &= ~(ADC_SC1_ADCH_MASK);
1196  tmp |= ADC_SC1_ADCH(inputChan);
1197  baseAddr->SC1[chanIndex] = tmp;
1198 }
1199 
1214 static inline bool ADC_HAL_GetConvCompleteFlag(const ADC_Type * const baseAddr,
1215  const uint8_t chanIndex)
1216 {
1217  uint32_t tmp = baseAddr->SC1[chanIndex];
1218  tmp = (tmp & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT;
1219 
1220  return (tmp != 0u) ? true : false;
1221 }
1222 
1236 static inline uint16_t ADC_HAL_GetChanResult(const ADC_Type * const baseAddr,
1237  const uint8_t chanIndex)
1238 {
1239  uint32_t tmp = baseAddr->R[chanIndex];
1240  tmp = (tmp & ADC_R_D_MASK) >> ADC_R_D_SHIFT;
1241 
1242  return (uint16_t)tmp;
1243 }
1244 
1263 static inline void ADC_HAL_ClearLatchTriggers(ADC_Type * const baseAddr)
1264 {
1265  baseAddr->CFG1 |= ADC_CFG1_CLRLTRG(0x01u);
1266 }
1267 
1278 static inline uint32_t ADC_HAL_GetTriggerErrorFlags(const ADC_Type * const baseAddr)
1279 {
1280  uint32_t tmp = baseAddr->SC2;
1282 
1283  return tmp;
1284 }
1285 
1295 static inline void ADC_HAL_ClearTriggerErrorFlags(ADC_Type * const baseAddr)
1296 {
1297  baseAddr->SC2 |= ADC_SC2_TRGSTERR(0x0Fu);
1298 }
1299 
1310 static inline uint32_t ADC_HAL_GetTriggerLatchFlags(const ADC_Type * const baseAddr)
1311 {
1312  uint32_t tmp = baseAddr->SC2;
1314 
1315  return tmp;
1316 }
1317 
1328 static inline uint32_t ADC_HAL_GetTriggerProcNumber(const ADC_Type * const baseAddr)
1329 {
1330  uint32_t tmp = baseAddr->SC2;
1332 
1333  return tmp;
1334 }
1335 
1338 #if defined (__cplusplus)
1339 }
1340 #endif
1341 
1344 #endif /* ADC_HAL_H */
1345 /*******************************************************************************
1346  * EOF
1347  ******************************************************************************/
static void ADC_HAL_SetContinuousConvFlag(ADC_Type *const baseAddr, const bool state)
Sets the Continuous Conversion Flag state.
Definition: adc_hal.h:588
#define ADC_SC1_COCO_SHIFT
Definition: S32K144.h:483
#define ADC_SC3_AVGS_SHIFT
Definition: S32K144.h:561
static bool ADC_HAL_GetHwAverageEnableFlag(const ADC_Type *const baseAddr)
Gets the Hardware Average Enable Flag state.
Definition: adc_hal.h:832
#define ADC_USR_OFS_USR_OFS(x)
Definition: S32K144.h:590
static uint16_t ADC_HAL_GetChanResult(const ADC_Type *const baseAddr, const uint8_t chanIndex)
Gets the conversion result for the selected measurement channel.
Definition: adc_hal.h:1236
#define ADC_CFG1_ADICLK_SHIFT
Definition: S32K144.h:488
static void ADC_HAL_SetChanInterruptEnableFlag(ADC_Type *const baseAddr, const uint8_t chanIndex, const bool state)
Sets the Channel Interrupt Enable to a new state.
Definition: adc_hal.h:1102
__IO uint32_t CFG1
Definition: S32K144.h:411
__IO uint32_t USR_OFS
Definition: S32K144.h:419
__IO uint32_t CLPS
Definition: S32K144.h:424
#define ADC_CFG1_MODE_MASK
Definition: S32K144.h:491
static void ADC_HAL_SetSampleTime(ADC_Type *const baseAddr, uint8_t sampletime)
Sets the Sample time in AD clock cycles.
Definition: adc_hal.h:294
static bool ADC_HAL_GetHwCompareGtEnableFlag(const ADC_Type *const baseAddr)
Gets the Hardware Compare Greater Than Enable Flag state.
Definition: adc_hal.h:660
#define ADC_SC3_ADCO(x)
Definition: S32K144.h:571
adc_input_clock_t
Input clock source selection Implements : adc_input_clock_t_Class.
Definition: adc_hal.h:78
#define ADC_SC2_ADACT_MASK
Definition: S32K144.h:543
#define ADC_SC2_ACREN(x)
Definition: S32K144.h:530
adc_clk_divide_t
Clock Divider selection Implements : adc_clk_divide_t_Class.
Definition: adc_hal.h:55
#define ADC_SC1_ADCH(x)
Definition: S32K144.h:477
#define ADC_SC2_REFSEL(x)
Definition: S32K144.h:522
#define ADC_SC2_ACREN_SHIFT
Definition: S32K144.h:528
adc_inputchannel_t
Input channel selection Implements : adc_inputchannel_t_Class.
Definition: adc_hal.h:128
static void ADC_HAL_SetUserOffsetValue(ADC_Type *const baseAddr, const uint16_t value)
Sets the User Offset Register value.
Definition: adc_hal.h:1052
static adc_trigger_t ADC_HAL_GetTriggerMode(const ADC_Type *const baseAddr)
Gets the ADC Trigger Mode.
Definition: adc_hal.h:431
static bool ADC_HAL_GetConvActiveFlag(const ADC_Type *const baseAddr)
Gets the Conversion Active Flag.
Definition: adc_hal.h:204
static uint16_t ADC_HAL_GetHwCompareComp2Value(const ADC_Type *const baseAddr)
Gets the Compare Register 2 value.
Definition: adc_hal.h:786
#define ADC_SC3_AVGS_MASK
Definition: S32K144.h:560
static void ADC_HAL_SetInputClock(ADC_Type *const baseAddr, const adc_input_clock_t inputClock)
Sets the AD Clock Input configuration.
Definition: adc_hal.h:405
static void ADC_HAL_SetCalibrationActiveFlag(ADC_Type *const baseAddr, const bool state)
Sets the Calibration Active Flag state.
Definition: adc_hal.h:953
#define ADC_CFG2_SMPLTS(x)
Definition: S32K144.h:507
static void ADC_HAL_SetClockDivide(ADC_Type *const baseAddr, const adc_clk_divide_t clockDivide)
Sets the ADC clock divider configuration.
Definition: adc_hal.h:250
adc_resolution_t
Conversion resolution selection Implements : adc_resolution_t_Class.
Definition: adc_hal.h:67
#define ADC_SC2_ACFGT_MASK
Definition: S32K144.h:531
#define ADC_SC2_DMAEN(x)
Definition: S32K144.h:526
#define ADC_SC2_TRGPRNUM_SHIFT
Definition: S32K144.h:548
#define ADC_SC3_AVGE(x)
Definition: S32K144.h:567
__IO uint32_t SC3
Definition: S32K144.h:416
__IO uint32_t G
Definition: S32K144.h:422
#define ADC_SC2_DMAEN_MASK
Definition: S32K144.h:523
#define ADC_SC2_REFSEL_SHIFT
Definition: S32K144.h:520
__IO uint32_t CFG2
Definition: S32K144.h:412
static bool ADC_HAL_GetContinuousConvFlag(const ADC_Type *const baseAddr)
Gets the Continuous Conversion Flag state.
Definition: adc_hal.h:566
#define ADC_SC2_ADACT_SHIFT
Definition: S32K144.h:544
#define ADC_SC2_ACFGT(x)
Definition: S32K144.h:534
#define ADC_SC2_ADTRG(x)
Definition: S32K144.h:542
#define ADC_USR_OFS_USR_OFS_SHIFT
Definition: S32K144.h:588
#define ADC_CFG1_ADIV_MASK
Definition: S32K144.h:495
static uint16_t ADC_HAL_GetUserGainValue(const ADC_Type *const baseAddr)
Gets the User Gain Register value.
Definition: adc_hal.h:975
#define ADC_SC2_ADTRG_SHIFT
Definition: S32K144.h:540
__IO uint32_t CLP3
Definition: S32K144.h:425
__IO uint32_t CLP0
Definition: S32K144.h:428
#define ADC_SC2_TRGPRNUM_MASK
Definition: S32K144.h:547
#define ADC_CFG1_MODE(x)
Definition: S32K144.h:494
__IO uint32_t CLP2
Definition: S32K144.h:426
#define ADC_SC1_AIEN(x)
Definition: S32K144.h:481
#define ADC_UG_UG_MASK
Definition: S32K144.h:607
#define ADC_SC2_TRGSTERR_MASK
Definition: S32K144.h:555
static void ADC_HAL_ClearLatchTriggers(ADC_Type *const baseAddr)
Clear the latched triggers.
Definition: adc_hal.h:1263
#define ADC_SC2_DMAEN_SHIFT
Definition: S32K144.h:524
__I uint32_t R[ADC_R_COUNT]
Definition: S32K144.h:413
static bool ADC_HAL_GetHwCompareRangeEnableFlag(const ADC_Type *const baseAddr)
Gets the Hardware Compare Range Enable state.
Definition: adc_hal.h:703
#define ADC_SC3_ADCO_MASK
Definition: S32K144.h:568
static void ADC_HAL_SetUserGainValue(ADC_Type *const baseAddr, const uint16_t value)
Sets the User Gain Register value.
Definition: adc_hal.h:995
#define ADC_SC2_REFSEL_MASK
Definition: S32K144.h:519
#define ADC_CFG1_ADICLK(x)
Definition: S32K144.h:490
#define ADC_SC3_AVGE_SHIFT
Definition: S32K144.h:565
__IO uint32_t CLP1
Definition: S32K144.h:427
static void ADC_HAL_SetHwAverageEnableFlag(ADC_Type *const baseAddr, const bool state)
Sets the Hardware Average Enable Flag state.
Definition: adc_hal.h:852
#define ADC_SC3_ADCO_SHIFT
Definition: S32K144.h:569
static uint32_t ADC_HAL_GetTriggerLatchFlags(const ADC_Type *const baseAddr)
Get the trigger latch flags bits.
Definition: adc_hal.h:1310
#define ADC_SC3_CAL(x)
Definition: S32K144.h:575
__IO uint32_t UG
Definition: S32K144.h:423
#define ADC_SC1_ADCH_MASK
Definition: S32K144.h:474
static adc_inputchannel_t ADC_HAL_GetInputChannel(const ADC_Type *const baseAddr, const uint8_t chanIndex)
Gets the configured input channel for the selected measurement channel.
Definition: adc_hal.h:1146
static void ADC_HAL_SetResolution(ADC_Type *const baseAddr, const adc_resolution_t resolution)
Sets the Resolution Mode configuration.
Definition: adc_hal.h:357
#define ADC_CV_CV(x)
Definition: S32K144.h:517
#define ADC_SC1_ADCH_SHIFT
Definition: S32K144.h:475
static void ADC_HAL_SetHwCompareComp1Value(ADC_Type *const baseAddr, const uint16_t value)
Sets the Compare Register 1 value.
Definition: adc_hal.h:766
__IO uint32_t CV[ADC_CV_COUNT]
Definition: S32K144.h:414
__IO uint32_t SC2
Definition: S32K144.h:415
#define ADC_SC2_ADTRG_MASK
Definition: S32K144.h:539
static uint32_t ADC_HAL_GetTriggerErrorFlags(const ADC_Type *const baseAddr)
Get the trigger latch error flags.
Definition: adc_hal.h:1278
static void ADC_HAL_ClearTriggerErrorFlags(ADC_Type *const baseAddr)
Clear the latch trigger error flags.
Definition: adc_hal.h:1295
#define ADC_CFG1_CLRLTRG(x)
Definition: S32K144.h:502
void ADC_HAL_Init(ADC_Type *const baseAddr)
Initializes the ADC instance to reset values.
Definition: adc_hal.c:45
#define ADC_SC2_ACFGT_SHIFT
Definition: S32K144.h:532
#define ADC_CFG1_MODE_SHIFT
Definition: S32K144.h:492
adc_average_t
Hardware average selection Implements : adc_average_t_Class.
Definition: adc_hal.h:110
#define ADC_UG_UG_SHIFT
Definition: S32K144.h:608
#define ADC_SC2_ACREN_MASK
Definition: S32K144.h:527
static void ADC_HAL_SetHwCompareGtEnableFlag(ADC_Type *const baseAddr, const bool state)
Sets the Hardware Compare Greater Than Enable Flag state.
Definition: adc_hal.h:681
#define ADC_SC3_CAL_MASK
Definition: S32K144.h:572
#define ADC_SC3_CAL_SHIFT
Definition: S32K144.h:573
static void ADC_HAL_SetInputChannel(ADC_Type *const baseAddr, const uint8_t chanIndex, const adc_inputchannel_t inputChan)
Sets the input channel configuration for the measurement channel.
Definition: adc_hal.h:1190
#define ADC_SC2_TRGSTLAT_SHIFT
Definition: S32K144.h:552
static adc_clk_divide_t ADC_HAL_GetClockDivide(const ADC_Type *const baseAddr)
Gets the current ADC clock divider configuration.
Definition: adc_hal.h:227
#define ADC_SC2_ACFE_MASK
Definition: S32K144.h:535
static bool ADC_HAL_GetDMAEnableFlag(const ADC_Type *const baseAddr)
Gets the DMA Enable Flag state.
Definition: adc_hal.h:477
static adc_average_t ADC_HAL_GetHwAverageMode(const ADC_Type *const baseAddr)
Gets the Hardware Average Mode.
Definition: adc_hal.h:878
#define ADC_USR_OFS_USR_OFS_MASK
Definition: S32K144.h:587
#define ADC_SC3_AVGS(x)
Definition: S32K144.h:563
#define ADC_SC2_ACFE(x)
Definition: S32K144.h:538
static uint16_t ADC_HAL_GetUserOffsetValue(const ADC_Type *const baseAddr)
Gets the User Offset Register value.
Definition: adc_hal.h:1030
static void ADC_HAL_SetTriggerMode(ADC_Type *const baseAddr, const adc_trigger_t trigger)
Sets the ADC Trigger Mode.
Definition: adc_hal.h:456
adc_trigger_t
Trigger type selection Implements : adc_trigger_t_Class.
Definition: adc_hal.h:90
#define ADC_SC1_AIEN_MASK
Definition: S32K144.h:478
#define ADC_R_D_SHIFT
Definition: S32K144.h:510
static void ADC_HAL_SetHwCompareEnableFlag(ADC_Type *const baseAddr, const bool state)
Sets the Hardware Compare Enable Flag state.
Definition: adc_hal.h:638
static void ADC_HAL_SetHwCompareRangeEnableFlag(ADC_Type *const baseAddr, const bool state)
Sets the Hardware Compare Range Enable state.
Definition: adc_hal.h:724
__IO uint32_t SC1[ADC_SC1_COUNT]
Definition: S32K144.h:410
static adc_voltage_reference_t ADC_HAL_GetVoltageReference(const ADC_Type *const baseAddr)
Gets the ADC Reference Voltage selection.
Definition: adc_hal.h:520
static void ADC_HAL_SetHwCompareComp2Value(ADC_Type *const baseAddr, const uint16_t value)
Sets the Compare Register 2 value.
Definition: adc_hal.h:805
#define ADC_SC2_ACFE_SHIFT
Definition: S32K144.h:536
#define ADC_SC2_TRGSTERR_SHIFT
Definition: S32K144.h:556
#define ADC_CFG1_ADICLK_MASK
Definition: S32K144.h:487
static uint16_t ADC_HAL_GetHwCompareComp1Value(const ADC_Type *const baseAddr)
Gets the Compare Register 1 value.
Definition: adc_hal.h:747
static uint32_t ADC_HAL_GetTriggerProcNumber(const ADC_Type *const baseAddr)
Get the index of the trigger under process.
Definition: adc_hal.h:1328
static void ADC_HAL_SetVoltageReference(ADC_Type *const baseAddr, const adc_voltage_reference_t voltageRef)
Sets the ADC Reference Voltage selection.
Definition: adc_hal.h:543
static adc_resolution_t ADC_HAL_GetResolution(const ADC_Type *const baseAddr)
Gets the Resolution Mode configuration.
Definition: adc_hal.h:319
#define ADC_SC1_COCO_MASK
Definition: S32K144.h:482
#define ADC_CFG2_SMPLTS_SHIFT
Definition: S32K144.h:505
static adc_input_clock_t ADC_HAL_GetInputClock(const ADC_Type *const baseAddr)
Gets the AD Clock Input configuration.
Definition: adc_hal.h:381
static bool ADC_HAL_GetConvCompleteFlag(const ADC_Type *const baseAddr, const uint8_t chanIndex)
Gets the measurement channel Conversion Complete Flag state.
Definition: adc_hal.h:1214
#define ADC_SC1_AIEN_SHIFT
Definition: S32K144.h:479
#define ADC_SC2_TRGSTERR(x)
Definition: S32K144.h:558
static void ADC_HAL_SetDMAEnableFlag(ADC_Type *const baseAddr, const bool state)
Sets the DMA Enable Flag state.
Definition: adc_hal.h:497
static uint8_t ADC_HAL_GetSampleTime(const ADC_Type *const baseAddr)
Gets the Sample time in AD clock cycles.
Definition: adc_hal.h:272
static void ADC_HAL_SetHwAverageMode(ADC_Type *const baseAddr, const adc_average_t averageMode)
Sets the Hardware Average Mode.
Definition: adc_hal.h:903
#define ADC_CFG2_SMPLTS_MASK
Definition: S32K144.h:504
static bool ADC_HAL_GetChanInterruptEnableFlag(const ADC_Type *const baseAddr, const uint8_t chanIndex)
Gets the Channel Interrupt Enable state.
Definition: adc_hal.h:1079
adc_voltage_reference_t
Voltage reference selection Implements : adc_voltage_reference_t_Class.
Definition: adc_hal.h:100
#define ADC_R_D_MASK
Definition: S32K144.h:509
#define ADC_CFG1_ADIV(x)
Definition: S32K144.h:498
#define ADC_CFG1_ADIV_SHIFT
Definition: S32K144.h:496
#define ADC_SC3_AVGE_MASK
Definition: S32K144.h:564
static bool ADC_HAL_GetCalibrationActiveFlag(const ADC_Type *const baseAddr)
Gets the Calibration Active Flag state.
Definition: adc_hal.h:933
static bool ADC_HAL_GetHwCompareEnableFlag(const ADC_Type *const baseAddr)
Gets the Hardware Compare Enable Flag state.
Definition: adc_hal.h:618
#define ADC_SC2_TRGSTLAT_MASK
Definition: S32K144.h:551