S32 SDK
sim_hal_S32K144.h
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #if !defined(SIM_HAL_S32K144_H)
20 #define SIM_HAL_S32K144_H
21 
22 #include "device_registers.h"
23 #include <stdbool.h>
24 #include <stddef.h>
25 
42 /*******************************************************************************
43  * Definitions
44  ******************************************************************************/
45 
46 /* @brief TClk clock frequency. */
47 #define NUMBER_OF_TCLK_INPUTS 3U
48 extern uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]; /* TCLKx clocks */
49 
50 
55 typedef enum
56 {
64 
69 typedef enum
70 {
74 
75 
80 typedef enum
81 {
85 
90 typedef enum
91 {
101 
106 typedef enum
107 {
117 
122 typedef enum
123 {
129 
134 typedef enum
135 {
136  SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* SOSCDIV1 clock */
137  SIM_RTCCLK_SEL_LPO_32K, /* 32 kHz LPO clock */
138  SIM_RTCCLK_SEL_RTC_CLKIN, /* RTC_CLKIN clock */
139  SIM_RTCCLK_SEL_FIRCDIV1_CLK /* FIRCDIV1 clock */
141 
146 typedef enum
147 {
148  SIM_LPO_CLK_SEL_LPO_128K, /* 128 kHz LPO clock */
149  SIM_LPO_CLK_SEL_NO_CLOCK, /* No clock */
150  SIM_LPO_CLK_SEL_LPO_32K, /* 32 kHz LPO clock which is divided by the 128 kHz LPO clock */
151  SIM_LPO_CLK_SEL_LPO_1K /* 1 kHz LPO clock which is divided by the 128 kHz LPO clock */
153 
158 typedef enum
159 {
165 
170 typedef enum
171 {
181 
186 typedef enum
187 {
191 
196 typedef enum
197 {
201 
206 typedef enum
207 {
213 
218 typedef struct
219 {
220  bool initialize;
221  bool enable;
225 
230 typedef struct
231 {
232  bool initialize;
236  bool enableLpo1k;
238 
243 typedef struct
244 {
245  bool initialize;
246  bool enableMscm;
247  bool enableMpu;
248  bool enableDma;
249  bool enableErm;
250  bool enableEim;
252 
257 typedef struct
258 {
259  bool initialize;
260  uint32_t tclkFreq[NUMBER_OF_TCLK_INPUTS];
262 
267 typedef enum
268 {
272 
277 typedef enum
278 {
282 } sim_package_t;
283 
288 typedef enum
289 {
290  SIM_FEATURE_FLEXIO = (1U << 5U),
291  SIM_FEATURE_ISO_CAN_FD = (1U << 6U),
292  SIM_FEATURE_SECURITY = (1U << 7U),
294 
299 typedef enum
300 {
310 
315 typedef enum
316 {
326 
331 typedef struct
332 {
333  bool initialize;
334  bool divEnable;
336  uint8_t divider;
337  bool divFraction;
339 
344 typedef struct
345 {
352 
353 /*******************************************************************************
354  * API
355  ******************************************************************************/
356 
357 #if defined(__cplusplus)
358 extern "C" {
359 #endif /* __cplusplus*/
360 
370 static inline void SIM_HAL_SetSramLRetentionCmd(SIM_Type * base, bool setting)
371 {
372  uint32_t regValue = (uint32_t)base->CHIPCTL;
373  regValue &= (uint32_t)(~(SIM_CHIPCTL_SRAML_RETEN_MASK));
374  regValue |= SIM_CHIPCTL_SRAML_RETEN(setting ? 1UL : 0UL);
375  base->CHIPCTL = (uint32_t)regValue;
376 }
377 
387 static inline bool SIM_HAL_GetSramLRetentionCmd(const SIM_Type * base)
388 {
389  uint32_t regValue = (uint32_t)base->CHIPCTL;
391  return (regValue != 0U) ? true : false;
392 }
393 
394 
404 static inline void SIM_HAL_SetSramURetentionCmd(SIM_Type * base, bool setting)
405 {
406  uint32_t regValue = (uint32_t)base->CHIPCTL;
407  regValue &= (uint32_t)(~(SIM_CHIPCTL_SRAMU_RETEN_MASK));
408  regValue |= SIM_CHIPCTL_SRAMU_RETEN(setting ? 1UL : 0UL);
409  base->CHIPCTL = (uint32_t)regValue;
410 }
411 
421 static inline bool SIM_HAL_GetSramURetentionCmd(const SIM_Type * base)
422 {
423  uint32_t regValue = (uint32_t)base->CHIPCTL;
425  return (regValue != 0U) ? true : false;
426 }
427 
437 static inline void SIM_HAL_SetAdcSupplyEnCmd(SIM_Type * base, bool setting)
438 {
439  uint32_t regValue = (uint32_t)base->CHIPCTL;
440  regValue &= (uint32_t)(~(SIM_CHIPCTL_ADC_SUPPLYEN_MASK));
441  regValue |= SIM_CHIPCTL_ADC_SUPPLYEN(setting ? 1UL : 0UL);
442  base->CHIPCTL = (uint32_t)regValue;
443 }
444 
454 static inline bool SIM_HAL_GetAdcSupplyEnCmd(const SIM_Type * base)
455 {
456  uint32_t regValue = (uint32_t)base->CHIPCTL;
458  return (regValue != 0U) ? true : false;
459 }
460 
470 static inline void SIM_HAL_SetAdcSupplySrc(SIM_Type * base, sim_adc_supply_src_t setting)
471 {
472  uint32_t regValue;
473  DEV_ASSERT(((uint32_t)setting) < (1UL<<SIM_CHIPCTL_ADC_SUPPLY_WIDTH));
474  regValue = base->CHIPCTL;
475  regValue &= ~(SIM_CHIPCTL_ADC_SUPPLY_MASK);
476  regValue |= SIM_CHIPCTL_ADC_SUPPLY(setting);
477  base->CHIPCTL = regValue;
478 }
479 
490 {
491  sim_adc_supply_src_t retValue;
493  {
494  case 0x5U:
495  retValue = ADC_SUPPLY_LV;
496  break;
497  case 0x4U:
498  retValue = ADC_SUPPLY_VDD_FLASH_3V;
499  break;
500  case 0x3U:
501  retValue = ADC_SUPPLY_VDD_3V;
502  break;
503  case 0x2U:
504  retValue = ADC_SUPPLY_VREFH;
505  break;
506  case 0x1U:
507  retValue = ADC_SUPPLY_VDDA;
508  break;
509  case 0x0U:
510  /* pass-through */
511  default:
512  retValue = ADC_SUPPLY_VDD;
513  break;
514  }
515  return retValue;
516 }
517 
518 
528 static inline void SIM_HAL_SetPdbBackToBackSrc(SIM_Type * base, sim_pdb_bb_src_t setting)
529 {
530  uint32_t settingValue, regValue;
531  switch(setting)
532  {
534  settingValue = 1U;
535  break;
537  /* Pass-through */
538  default:
539  settingValue = 0U;
540  break;
541  }
542 
543  regValue = (uint32_t)base->CHIPCTL;
544  regValue &= (uint32_t)(~(SIM_CHIPCTL_PDB_BB_SEL_MASK));
545  regValue |= SIM_CHIPCTL_PDB_BB_SEL(settingValue);
546  base->CHIPCTL = (uint32_t)regValue;
547 }
548 
559 {
560  sim_pdb_bb_src_t retValue;
561 
563  {
564  case 1U:
565  retValue = PDB_BACK_TO_BACK_OPTION_1;
566  break;
567  case 0U:
568  /* pass-through */
569  default:
570  retValue = PDB_BACK_TO_BACK_OPTION_0;
571  break;
572  }
573  return retValue;
574 }
575 
584 
592 void SIM_HAL_GetClkoutConfig(const SIM_Type * base, sim_clock_out_config_t *config);
593 
604 void SIM_HAL_InitClkout(SIM_Type * base, const sim_clock_out_config_t *config);
605 
614 static inline void SIM_HAL_DeinitClkout(SIM_Type * base)
615 {
616  /* Disable divider. */
617  base->CHIPCTL &= (uint32_t)(~(SIM_CHIPCTL_CLKOUTEN_MASK));
618 }
619 
629 static inline void SIM_HAL_SetAdcInterleaveSel(SIM_Type * base, uint8_t setting)
630 {
631  uint32_t regValue;
633 
634  regValue = base->CHIPCTL;
635  regValue &= ~(SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK);
636  regValue |= SIM_CHIPCTL_ADC_INTERLEAVE_EN(setting);
637  base->CHIPCTL = regValue;
638 }
639 
649 static inline uint8_t SIM_HAL_GetAdcInterleaveSel(const SIM_Type * base)
650 {
651  uint32_t regValue = base->CHIPCTL;
653  return (uint8_t)regValue;
654 }
655 
666  uint32_t instance,
667  sim_ftm_clk_sel_t select);
668 
679  uint32_t instance);
680 
691  uint32_t instance,
692  uint8_t select);
693 
703 uint8_t SIM_HAL_GetFtmFaultSelMode(const SIM_Type * base,
704  uint32_t instance);
705 
716 {
717  sim_rtc_clk_sel_src_t retValue;
719  {
720  case 0x3U:
721  retValue = SIM_RTCCLK_SEL_FIRCDIV1_CLK;
722  break;
723  case 0x2U:
724  retValue = SIM_RTCCLK_SEL_RTC_CLKIN;
725  break;
726  case 0x1U:
727  retValue = SIM_RTCCLK_SEL_LPO_32K;
728  break;
729  case 0x0U:
730  /* pass-through */
731  default:
732  retValue = SIM_RTCCLK_SEL_SOSCDIV1_CLK;
733  break;
734  }
735  return retValue;
736 }
737 
738 
749 static inline void SIM_HAL_SetLpoClocks(SIM_Type* base, sim_lpo_clock_config_t setting)
750 {
751  uint32_t regValue = base->LPOCLKS;
752 
753  regValue &= ~( SIM_LPOCLKS_LPO1KCLKEN_MASK |
757 
758  regValue |= SIM_LPOCLKS_LPO1KCLKEN(setting.enableLpo1k ? 1UL : 0UL);
759  regValue |= SIM_LPOCLKS_LPO32KCLKEN(setting.enableLpo32k ? 1UL : 0UL);
760  regValue |= SIM_LPOCLKS_LPOCLKSEL(setting.sourceLpoClk);
761  regValue |= SIM_LPOCLKS_RTCCLKSEL(setting.sourceRtcClk);
762 
763  /* Write value to register. */
764  base->LPOCLKS = regValue;
765 }
766 
777 {
778  sim_lpoclk_sel_src_t retValue;
779 
781  {
782  case 0x3U:
783  retValue = SIM_LPO_CLK_SEL_LPO_1K;
784  break;
785  case 0x2U:
786  retValue = SIM_LPO_CLK_SEL_LPO_32K;
787  break;
788  case 0x1U:
789  retValue = SIM_LPO_CLK_SEL_NO_CLOCK;
790  break;
791  case 0x0U:
792  /* pass-through */
793  default:
794  retValue = SIM_LPO_CLK_SEL_LPO_128K;
795  break;
796  }
797  return retValue;
798 }
799 
809 static inline bool SIM_HAL_GetLpo32kClkEnCmd(const SIM_Type * base)
810 {
811  uint32_t regValue = (uint32_t)base->LPOCLKS;
813  return (regValue != 0U) ? true : false;
814 }
815 
825 static inline bool SIM_HAL_GetLpo1kClkEnCmd(const SIM_Type * base)
826 {
827  uint32_t regValue = (uint32_t)base->LPOCLKS;
829  return (regValue != 0U) ? true : false;
830 }
831 
838 uint32_t SIM_HAL_GetLpoFreq(const SIM_Type * base);
839 
846 uint32_t SIM_HAL_GetLpo128KFreq(const SIM_Type * base);
847 
854 uint32_t SIM_HAL_GetLpo32KFreq(const SIM_Type * base);
855 
862 uint32_t SIM_HAL_GetLpo1KFreq(const SIM_Type * base);
863 
874  uint32_t instance,
875  sim_adc_pretrg_sel_t select);
876 
887  uint32_t instance);
888 
899  uint32_t instance,
900  sim_adc_sw_pretrg_sel_t select);
901 
912  uint32_t instance);
913 
924  uint32_t instance,
925  sim_adc_trg_sel_t select);
926 
937  uint32_t instance);
938 
939 
949 static inline void SIM_HAL_SetFtmGlobalLoad(SIM_Type* base, bool enable)
950 {
951  uint32_t regValue = (uint32_t)base->FTMOPT1;
952  regValue &= (uint32_t)(~(SIM_FTMOPT1_FTMGLDOK_MASK));
953  regValue |= SIM_FTMOPT1_FTMGLDOK(enable ? 1UL : 0UL);
954  base->FTMOPT1 = (uint32_t)regValue;
955 }
956 
966 static inline bool SIM_HAL_GetFtmGlobalLoad(const SIM_Type * base)
967 {
968  uint32_t regValue = (uint32_t)base->FTMOPT1;
969  regValue = (regValue & SIM_FTMOPT1_FTMGLDOK_MASK) >> SIM_FTMOPT1_FTMGLDOK_SHIFT;
970  return (regValue != 0U) ? true : false;
971 }
972 
973 
985  uint32_t instance,
986  uint8_t channel,
987  sim_ftm_ch_out_src_t select);
988 
1001  uint32_t instance,
1002  uint8_t channel);
1003 
1014 void SIM_HAL_SetFtmChSrcMode(SIM_Type * base,
1015  uint32_t instance,
1016  uint8_t channel,
1017  sim_ftm_ch_src_t select);
1018 
1030  uint32_t instance,
1031  uint8_t channel);
1032 
1043 void SIM_HAL_SetFtmSyncCmd(SIM_Type * base, uint32_t instance, bool sync);
1044 
1056 static inline bool SIM_HAL_GetFtmSyncCmd(const SIM_Type * base, uint32_t instance)
1057 {
1058  uint32_t regValue = base->FTMOPT1;
1059  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1060 
1061  switch (instance)
1062  {
1063  case 0U:
1065  break;
1066  case 1U:
1068  break;
1069  case 2U:
1071  break;
1072  case 3U:
1074  break;
1075 #if FTM_INSTANCE_COUNT > 4U
1076  case 4U:
1077  regValue = (regValue & SIM_FTMOPT1_FTM4SYNCBIT_MASK) >> SIM_FTMOPT1_FTM4SYNCBIT_SHIFT;
1078  break;
1079 #endif
1080 #if FTM_INSTANCE_COUNT > 5U
1081  case 5U:
1082  regValue = (regValue & SIM_FTMOPT1_FTM5SYNCBIT_MASK) >> SIM_FTMOPT1_FTM5SYNCBIT_SHIFT;
1083  break;
1084 #endif
1085 #if FTM_INSTANCE_COUNT > 6U
1086  case 6U:
1087  regValue = (regValue & SIM_FTMOPT1_FTM6SYNCBIT_MASK) >> SIM_FTMOPT1_FTM6SYNCBIT_SHIFT;
1088  break;
1089 #endif
1090 #if FTM_INSTANCE_COUNT > 7U
1091  case 7U:
1092  regValue = (regValue & SIM_FTMOPT1_FTM7SYNCBIT_MASK) >> SIM_FTMOPT1_FTM7SYNCBIT_SHIFT;
1093  break;
1094 #endif
1095  default:
1096  regValue = 0U;
1097  break;
1098  }
1099 
1100  return (regValue == 0U) ? false : true;
1101 }
1102 
1113 static inline void SIM_HAL_SetObeCtrlCmd(SIM_Type * base, uint32_t instance, bool setting)
1114 {
1115  uint32_t settingValue = (setting == false) ? 0UL : 1UL;
1116  uint32_t regValue = base->MISCTRL0;
1117  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1118 
1119  switch (instance)
1120  {
1121  case 0U:
1122  regValue &= ~(SIM_MISCTRL0_FTM0_OBE_CTRL_MASK);
1123  regValue |= SIM_MISCTRL0_FTM0_OBE_CTRL(settingValue);
1124  break;
1125  case 1U:
1126  regValue &= ~(SIM_MISCTRL0_FTM1_OBE_CTRL_MASK);
1127  regValue |= SIM_MISCTRL0_FTM1_OBE_CTRL(settingValue);
1128  break;
1129  case 2U:
1130  regValue &= ~(SIM_MISCTRL0_FTM2_OBE_CTRL_MASK);
1131  regValue |= SIM_MISCTRL0_FTM2_OBE_CTRL(settingValue);
1132  break;
1133  case 3U:
1134  regValue &= ~(SIM_MISCTRL0_FTM3_OBE_CTRL_MASK);
1135  regValue |= SIM_MISCTRL0_FTM3_OBE_CTRL(settingValue);
1136  break;
1137 #if FTM_INSTANCE_COUNT > 4U
1138  case 4U:
1139  regValue &= ~(SIM_MISCTRL0_FTM4_OBE_CTRL_MASK);
1140  regValue |= SIM_MISCTRL0_FTM4_OBE_CTRL(settingValue);
1141  break;
1142 #endif
1143 #if FTM_INSTANCE_COUNT > 5U
1144  case 5U:
1145  regValue &= ~(SIM_MISCTRL0_FTM5_OBE_CTRL_MASK);
1146  regValue |= SIM_MISCTRL0_FTM5_OBE_CTRL(settingValue);
1147  break;
1148 #endif
1149 #if FTM_INSTANCE_COUNT > 6U
1150  case 6U:
1151  regValue &= ~(SIM_MISCTRL0_FTM6_OBE_CTRL_MASK);
1152  regValue |= SIM_MISCTRL0_FTM6_OBE_CTRL(settingValue);
1153  break;
1154 #endif
1155 #if FTM_INSTANCE_COUNT > 7U
1156  case 7U:
1157  regValue &= ~(SIM_MISCTRL0_FTM7_OBE_CTRL_MASK);
1158  regValue |= SIM_MISCTRL0_FTM7_OBE_CTRL(settingValue);
1159  break;
1160 #endif
1161  default:
1162  /* Nothing to do, error is caught by DEV_ASSERT(instance < FTM_INSTANCE_COUNT) */
1163  break;
1164  }
1165  base->MISCTRL0 = regValue;
1166 }
1167 
1178 static inline bool SIM_HAL_GetObeCtrlCmd(const SIM_Type * base, uint32_t instance)
1179 {
1180  uint32_t regValue = base->MISCTRL0;
1181  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1182 
1183  switch (instance)
1184  {
1185  case 0U:
1187  break;
1188  case 1U:
1190  break;
1191  case 2U:
1193  break;
1194  case 3U:
1196  break;
1197 #if FTM_INSTANCE_COUNT > 4U
1198  case 4U:
1199  regValue = (regValue & SIM_MISCTRL0_FTM4_OBE_CTRL_MASK) >> SIM_MISCTRL0_FTM4_OBE_CTRL_SHIFT;
1200  break;
1201 #endif
1202 #if FTM_INSTANCE_COUNT > 5U
1203  case 5U:
1204  regValue = (regValue & SIM_MISCTRL0_FTM5_OBE_CTRL_MASK) >> SIM_MISCTRL0_FTM5_OBE_CTRL_SHIFT;
1205  break;
1206 #endif
1207 #if FTM_INSTANCE_COUNT > 6U
1208  case 6U:
1209  regValue = (regValue & SIM_MISCTRL0_FTM6_OBE_CTRL_MASK) >> SIM_MISCTRL0_FTM6_OBE_CTRL_SHIFT;
1210  break;
1211 #endif
1212 #if FTM_INSTANCE_COUNT > 7U
1213  case 7U:
1214  regValue = (regValue & SIM_MISCTRL0_FTM7_OBE_CTRL_MASK) >> SIM_MISCTRL0_FTM7_OBE_CTRL_SHIFT;
1215  break;
1216 #endif
1217  default:
1218  regValue = 0U;
1219  break;
1220  }
1221  return (regValue == 0U) ? false : true;
1222 }
1223 
1224 
1234 static inline uint32_t SIM_HAL_GetGeneration(const SIM_Type * base)
1235 {
1236  uint32_t regValue = base->SDID;
1237  regValue = (regValue & SIM_SDID_GENERATION_MASK) >> SIM_SDID_GENERATION_SHIFT;
1238  return regValue;
1239 }
1240 
1250 static inline uint32_t SIM_HAL_GetSubSeries(const SIM_Type * base)
1251 {
1252  uint32_t regValue = base->SDID;
1253  regValue = (regValue & SIM_SDID_SUBSERIES_MASK) >> SIM_SDID_SUBSERIES_SHIFT;
1254  return regValue;
1255 }
1256 
1266 static inline uint32_t SIM_HAL_GetDerivate(const SIM_Type * base)
1267 {
1268  uint32_t regValue = base->SDID;
1269  regValue = (regValue & SIM_SDID_DERIVATE_MASK) >> SIM_SDID_DERIVATE_SHIFT;
1270  return regValue;
1271 }
1272 
1283 static inline sim_ram_size_t SIM_HAL_GetRamSize(const SIM_Type * base)
1284 {
1285  sim_ram_size_t retValue;
1286 
1288  {
1289  case 0xDU:
1290  retValue = SIM_RAM_SIZE_48KB;
1291  break;
1292  case 0xFU:
1293  /* pass-through */
1294  default:
1295  retValue = SIM_RAM_SIZE_64KB;
1296  break;
1297  }
1298  return retValue;
1299 }
1300 
1310 static inline uint32_t SIM_HAL_GetRevId(const SIM_Type * base)
1311 {
1312  uint32_t regValue = base->SDID;
1313  regValue = (regValue & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT;
1314  return regValue;
1315 }
1316 
1326 static inline sim_package_t SIM_HAL_GetPackage(const SIM_Type * base)
1327 {
1328  sim_package_t retValue;
1329 
1331  {
1332  case 0x3U:
1333  retValue = SIM_PACKAGE_64_LQFP;
1334  break;
1335  case 0x4U:
1336  retValue = SIM_PACKAGE_100_LQFP;
1337  break;
1338  case 0x8U:
1339  /* pass-through */
1340  default:
1341  retValue = SIM_PACKAGE_100_MAP_BGA;
1342  break;
1343  }
1344  return retValue;
1345 }
1346 
1357 static inline uint32_t SIM_HAL_GetFeatures(const SIM_Type * base)
1358 {
1359  uint32_t regValue = base->SDID;
1360  regValue = (regValue & SIM_SDID_FEATURES_MASK) >> SIM_SDID_FEATURES_SHIFT;
1361  return regValue;
1362 }
1363 
1373 static inline void SIM_HAL_SetEimClockGate(SIM_Type* base, bool enable)
1374 {
1375  uint32_t regValue = (uint32_t)base->PLATCGC;
1376  regValue &= (uint32_t)(~(SIM_PLATCGC_CGCEIM_MASK));
1377  regValue |= SIM_PLATCGC_CGCEIM(enable ? 1UL : 0UL);
1378  base->PLATCGC = (uint32_t)regValue;
1379 }
1380 
1390 static inline bool SIM_HAL_GetEimClockGate(const SIM_Type * base)
1391 {
1392  uint32_t regValue = (uint32_t)base->PLATCGC;
1393  regValue = (regValue & SIM_PLATCGC_CGCEIM_MASK) >> SIM_PLATCGC_CGCEIM_SHIFT;
1394  return (regValue != 0U) ? true : false;
1395 }
1396 
1406 static inline void SIM_HAL_SetErmClockGate(SIM_Type* base, bool enable)
1407 {
1408  uint32_t regValue = (uint32_t)base->PLATCGC;
1409  regValue &= (uint32_t)(~(SIM_PLATCGC_CGCERM_MASK));
1410  regValue |= SIM_PLATCGC_CGCERM(enable ? 1UL : 0UL);
1411  base->PLATCGC = (uint32_t)regValue;
1412 }
1413 
1423 static inline bool SIM_HAL_GetErmClockGate(const SIM_Type * base)
1424 {
1425  uint32_t regValue = (uint32_t)base->PLATCGC;
1426  regValue = (regValue & SIM_PLATCGC_CGCERM_MASK) >> SIM_PLATCGC_CGCERM_SHIFT;
1427  return (regValue != 0U) ? true : false;
1428 }
1429 
1439 static inline void SIM_HAL_SetDmaClockGate(SIM_Type* base, bool enable)
1440 {
1441  uint32_t regValue = (uint32_t)base->PLATCGC;
1442  regValue &= (uint32_t)(~(SIM_PLATCGC_CGCDMA_MASK));
1443  regValue |= SIM_PLATCGC_CGCDMA(enable ? 1UL : 0UL);
1444  base->PLATCGC = (uint32_t)regValue;
1445 }
1446 
1456 static inline bool SIM_HAL_GetDmaClockGate(const SIM_Type * base)
1457 {
1458  uint32_t regValue = (uint32_t)base->PLATCGC;
1459  regValue = (regValue & SIM_PLATCGC_CGCDMA_MASK) >> SIM_PLATCGC_CGCDMA_SHIFT;
1460  return (regValue != 0U) ? true : false;
1461 }
1462 
1472 static inline void SIM_HAL_SetMpuClockGate(SIM_Type* base, bool enable)
1473 {
1474  uint32_t regValue = (uint32_t)base->PLATCGC;
1475  regValue &= (uint32_t)(~(SIM_PLATCGC_CGCMPU_MASK));
1476  regValue |= SIM_PLATCGC_CGCMPU(enable ? 1UL : 0UL);
1477  base->PLATCGC = (uint32_t)regValue;
1478 }
1479 
1489 static inline bool SIM_HAL_GetMpuClockGate(const SIM_Type * base)
1490 {
1491  uint32_t regValue = (uint32_t)base->PLATCGC;
1492  regValue = (regValue & SIM_PLATCGC_CGCMPU_MASK) >> SIM_PLATCGC_CGCMPU_SHIFT;
1493  return (regValue != 0U) ? true : false;
1494 }
1495 
1505 static inline void SIM_HAL_SetMscmClockGate(SIM_Type* base, bool enable)
1506 {
1507  uint32_t regValue = (uint32_t)base->PLATCGC;
1508  regValue &= (uint32_t)(~(SIM_PLATCGC_CGCMSCM_MASK));
1509  regValue |= SIM_PLATCGC_CGCMSCM(enable ? 1UL : 0UL);
1510  base->PLATCGC = (uint32_t)regValue;
1511 }
1512 
1522 static inline bool SIM_HAL_GetMscmClockGate(const SIM_Type * base)
1523 {
1524  uint32_t regValue = (uint32_t)base->PLATCGC;
1525  regValue = (regValue & SIM_PLATCGC_CGCMSCM_MASK) >> SIM_PLATCGC_CGCMSCM_SHIFT;
1526  return (regValue != 0U) ? true : false;
1527 }
1528 
1539 {
1540  sim_eee_sram_size_t retValue;
1541 
1543  {
1544  case 0x9U:
1545  retValue = SIM_EEE_SRAM_SIZE_32B;
1546  break;
1547  case 0x8U:
1548  retValue = SIM_EEE_SRAM_SIZE_64B;
1549  break;
1550  case 0x7U:
1551  retValue = SIM_EEE_SRAM_SIZE_128B;
1552  break;
1553  case 0x6U:
1554  retValue = SIM_EEE_SRAM_SIZE_256B;
1555  break;
1556  case 0x5U:
1557  retValue = SIM_EEE_SRAM_SIZE_512B;
1558  break;
1559  case 0x4U:
1560  retValue = SIM_EEE_SRAM_SIZE_1KB;
1561  break;
1562  case 0x3U:
1563  retValue = SIM_EEE_SRAM_SIZE_2KB;
1564  break;
1565  case 0x2U:
1566  /* pass-through */
1567  default:
1568  retValue = SIM_EEE_SRAM_SIZE_4KB;
1569  break;
1570  }
1571  return retValue;
1572 }
1573 
1584 {
1585  sim_flexnvm_partition_t retValue;
1586 
1588  {
1589  case 0xFU:
1590  retValue = SIM_DEPART_1111;
1591  break;
1592  case 0xCU:
1593  retValue = SIM_DEPART_1100;
1594  break;
1595  case 0xBU:
1596  retValue = SIM_DEPART_1011;
1597  break;
1598  case 0xAU:
1599  retValue = SIM_DEPART_1010;
1600  break;
1601  case 0x8U:
1602  retValue = SIM_DEPART_1000;
1603  break;
1604  case 0x4U:
1605  retValue = SIM_DEPART_0100;
1606  break;
1607  case 0x3U:
1608  retValue = SIM_DEPART_0011;
1609  break;
1610  case 0x0U:
1611  /* pass-through */
1612  default:
1613  retValue = SIM_DEPART_0000;
1614  break;
1615  }
1616  return retValue;
1617 }
1618 
1628 static inline uint32_t SIM_HAL_GetUniqueIdHigh(const SIM_Type * base)
1629 {
1630  return base->UIDH;
1631 }
1632 
1642 static inline uint32_t SIM_HAL_GetUniqueIdMidHigh(const SIM_Type * base)
1643 {
1644  return base->UIDMH;
1645 }
1646 
1656 static inline uint32_t SIM_HAL_GetUniqueIdMidLow(const SIM_Type * base)
1657 {
1658  return base->UIDML;
1659 }
1660 
1670 static inline uint32_t SIM_HAL_GetUniqueIdLow(const SIM_Type * base)
1671 {
1672  return base->UIDL;
1673 }
1674 
1683 
1694 void SIM_HAL_InitTraceClock(SIM_Type * base,
1695  const sim_trace_clock_config_t *config);
1696 
1705 static inline void SIM_HAL_DeinitTraceClock(SIM_Type * base)
1706 {
1707  /* Disable divider. */
1708  base->CLKDIV4 &= (uint32_t)(~(SIM_CLKDIV4_TRACEDIVEN_MASK));
1709 }
1710 
1720 static inline void SIM_HAL_SetSwTriggerTrgmux(SIM_Type * base, bool disable)
1721 {
1722  uint32_t regValue = (uint32_t)base->MISCTRL1;
1723  regValue &= (uint32_t)(~(SIM_MISCTRL1_SW_TRG_MASK));
1724  regValue |= SIM_MISCTRL1_SW_TRG(disable ? 1UL : 0UL);
1725  base->MISCTRL1 = (uint32_t)regValue;
1726 }
1727 
1737 static inline uint32_t SIM_HAL_GetSwTriggerTrgmux(const SIM_Type * base)
1738 {
1739  uint32_t regValue = (uint32_t)base->MISCTRL1;
1740  regValue = (regValue & SIM_MISCTRL1_SW_TRG_MASK) >> SIM_MISCTRL1_SW_TRG_SHIFT;
1741  return (uint32_t)regValue;
1742 }
1743 
1754 static inline void SIM_HAL_SetTClkFreq(SIM_Type * base, uint8_t index, uint32_t frequency)
1755 {
1756  (void) base;
1757  if(index < NUMBER_OF_TCLK_INPUTS) {
1758  g_TClkFreq[index] = frequency;
1759  }
1760 }
1761 
1772 static inline uint32_t SIM_HAL_GetTClkFreq(SIM_Type * base, uint8_t index)
1773 {
1774  uint32_t retValue = 0U;
1775  (void) base;
1776  if(index < NUMBER_OF_TCLK_INPUTS) {
1777  retValue = g_TClkFreq[index];
1778  }
1779 
1780  return retValue;
1781 }
1782 
1783 #if defined(__cplusplus)
1784 }
1785 #endif /* __cplusplus*/
1786 
1787 
1790 #endif /* SIM_HAL_S32K144_H */
1791 /*******************************************************************************
1792  * EOF
1793  ******************************************************************************/
1794 
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT
Definition: S32K144.h:10756
sim_eee_sram_size_t
SIM EEE SRAM Size Implements sim_eee_sram_size_t_Class.
sim_adc_sw_pretrg_sel_t SIM_HAL_GetAdcSwPreTriggerMode(const SIM_Type *base, uint32_t instance)
Gets the ADCx software pre-trigger select setting.
void SIM_HAL_SetAdcTriggerMode(SIM_Type *base, uint32_t instance, sim_adc_trg_sel_t select)
Sets the ADCx trigger select setting.
static void SIM_HAL_SetDmaClockGate(SIM_Type *base, bool enable)
Set the DMA Clock Gate from the Platform Clock Gating Control Register.
uint32_t SIM_HAL_GetLpo1KFreq(const SIM_Type *base)
Get SIM LPO 1KHz clock frequency (LPO_1K_CLOCK).
__IO uint32_t MISCTRL0
Definition: S32K144.h:10715
static sim_ram_size_t SIM_HAL_GetRamSize(const SIM_Type *base)
Gets RAM size.
sim_adc_supply_src_t
Internal supplies monitored by ADC_SUPPLY Implements sim_adc_supply_src_t_Class.
static void SIM_HAL_SetObeCtrlCmd(SIM_Type *base, uint32_t instance, bool setting)
Sets FTM channel state.
__IO uint32_t LPOCLKS
Definition: S32K144.h:10711
SIM LPO Clocks configuration. Implements sim_lpo_clock_config_t_Class.
sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(const SIM_Type *base, uint32_t instance)
Gets the ADCx pre-trigger select setting.
#define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT
Definition: S32K144.h:10872
#define SIM_PLATCGC_CGCEIM_SHIFT
Definition: S32K144.h:10975
static bool SIM_HAL_GetDmaClockGate(const SIM_Type *base)
Gets the DMA Clock Gate from the Platform Clock Gating Control Register.
sim_tclk_config_t tclkConfig
__I uint32_t SDID
Definition: S32K144.h:10716
static void SIM_HAL_SetTClkFreq(SIM_Type *base, uint8_t index, uint32_t frequency)
Sets the TClk Frequency.
sim_ftm_ch_src_t
SIM FlexTimer x channel y input source select Implements sim_ftm_ch_src_t_Class.
static sim_adc_supply_src_t SIM_HAL_GetAdcSupplySrc(const SIM_Type *base)
Get ADC supply source.
static uint32_t SIM_HAL_GetDerivate(const SIM_Type *base)
Gets the Derivate from the System Device ID register (SIM_SDID).
__IO uint32_t FTMOPT1
Definition: S32K144.h:10714
#define SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT
Definition: S32K144.h:10784
#define SIM_SDID_SUBSERIES_SHIFT
Definition: S32K144.h:10950
#define SIM_LPOCLKS_LPO1KCLKEN_SHIFT
Definition: S32K144.h:10830
sim_ftm_clk_sel_t
SIM FlexTimer external clock select Implements sim_ftm_clk_sel_t_Class.
#define SIM_MISCTRL0_FTM3_OBE_CTRL(x)
Definition: S32K144.h:10927
void SIM_HAL_GetTraceClockDefaultConfig(sim_trace_clock_config_t *config)
Get the default Debug Trace clock configuration.
static bool SIM_HAL_GetLpo1kClkEnCmd(const SIM_Type *base)
Gets the 1 kHz LPO clock Control.
#define SIM_CHIPCTL_ADC_SUPPLYEN(x)
Definition: S32K144.h:10786
static sim_pdb_bb_src_t SIM_HAL_GetPdbBackToBackSrc(const SIM_Type *base)
Get PDB back-to-back selection.
#define SIM_CHIPCTL_SRAMU_RETEN(x)
Definition: S32K144.h:10790
#define SIM_MISCTRL0_FTM2_OBE_CTRL_MASK
Definition: S32K144.h:10920
#define SIM_CLKDIV4_TRACEDIVEN_MASK
Definition: S32K144.h:11016
#define SIM_PLATCGC_CGCERM_MASK
Definition: S32K144.h:10970
#define SIM_SDID_DERIVATE_SHIFT
Definition: S32K144.h:10946
sim_ram_size_t
SIM RAM size Implements sim_ram_size_t_Class.
static bool SIM_HAL_GetMpuClockGate(const SIM_Type *base)
Gets the MPU Clock Gating from the Platform Clock Gating Control Register.
sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(const SIM_Type *base, uint32_t instance)
Gets the FlexTimer x external clock pin select setting.
#define SIM_CHIPCTL_PDB_BB_SEL(x)
Definition: S32K144.h:10778
#define SIM_MISCTRL0_FTM0_OBE_CTRL_MASK
Definition: S32K144.h:10912
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK
Definition: S32K144.h:10755
uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]
Definition: clock_S32K144.c:67
void SIM_HAL_GetClkoutConfig(const SIM_Type *base, sim_clock_out_config_t *config)
Get the SIM CLKOUT clock configuration.
__IO uint32_t FCFG1
Definition: S32K144.h:10720
#define SIM_FTMOPT1_FTM3SYNCBIT_SHIFT
Definition: S32K144.h:10884
#define SIM_LPOCLKS_LPOCLKSEL(x)
Definition: S32K144.h:10840
void SIM_HAL_SetAdcPreTriggerMode(SIM_Type *base, uint32_t instance, sim_adc_pretrg_sel_t select)
Sets the ADCx pre-trigger select setting.
#define SIM_SDID_DERIVATE_MASK
Definition: S32K144.h:10945
static void SIM_HAL_DeinitTraceClock(SIM_Type *base)
De-initialize SIM Debug Trace.
#define SIM_CHIPCTL_ADC_SUPPLY_SHIFT
Definition: S32K144.h:10780
static uint32_t SIM_HAL_GetUniqueIdLow(const SIM_Type *base)
Gets the UID31_0 from Unique Identification Register Low.
SIM configure structure. Implements sim_clock_config_t_Class.
#define SIM_MISCTRL1_SW_TRG_SHIFT
Definition: S32K144.h:11022
#define SIM_FTMOPT1_FTM2SYNCBIT_SHIFT
Definition: S32K144.h:10880
static void SIM_HAL_SetAdcSupplySrc(SIM_Type *base, sim_adc_supply_src_t setting)
Set ADC Supply Enable setting.
static sim_package_t SIM_HAL_GetPackage(const SIM_Type *base)
Gets the Package in System Device ID register (SIM_SDID).
#define SIM_MISCTRL0_FTM3_OBE_CTRL_MASK
Definition: S32K144.h:10924
static sim_rtc_clk_sel_src_t SIM_HAL_GetRtcClkSrc(const SIM_Type *base)
Get the clock selection of RTCCLKSEL.
#define SIM_PLATCGC_CGCDMA_SHIFT
Definition: S32K144.h:10967
static bool SIM_HAL_GetAdcSupplyEnCmd(const SIM_Type *base)
Get ADC Supply Enable setting.
void SIM_HAL_SetFtmChSrcMode(SIM_Type *base, uint32_t instance, uint8_t channel, sim_ftm_ch_src_t select)
Sets the FlexTimer x channel y input source select setting.
static bool SIM_HAL_GetEimClockGate(const SIM_Type *base)
Gets the EIM Clock Gate from the Platform Clock Gating Control Register.
sim_adc_sw_pretrg_sel_t
SIM ADCx software pre-trigger select Implements sim_adc_sw_pretrg_sel_t_Class.
static void SIM_HAL_SetSramURetentionCmd(SIM_Type *base, bool setting)
Set SRAM U Retention setting.
#define SIM_FCFG1_EEERAMSIZE_MASK
Definition: S32K144.h:10983
sim_package_t
SIM Package Implements sim_package_t_Class.
static uint32_t SIM_HAL_GetGeneration(const SIM_Type *base)
Gets the product series Generation from System Device ID register (SIM_SDID).
#define SIM_MISCTRL0_FTM1_OBE_CTRL_MASK
Definition: S32K144.h:10916
sim_clkout_div_t divider
static void SIM_HAL_SetMpuClockGate(SIM_Type *base, bool enable)
Configure the MPU Clock Gating from the Platform Clock Gating Control Register.
#define SIM_CHIPCTL_ADC_SUPPLY_MASK
Definition: S32K144.h:10779
#define SIM_PLATCGC_CGCERM_SHIFT
Definition: S32K144.h:10971
static bool SIM_HAL_GetFtmGlobalLoad(const SIM_Type *base)
Gets the FTM Global Load from the FTM Option Register 1.
#define SIM_FCFG1_DEPART_SHIFT
Definition: S32K144.h:10980
static bool SIM_HAL_GetErmClockGate(const SIM_Type *base)
Gets the ERM Clock Gate from the Platform Clock Gating Control Register.
#define SIM_FTMOPT1_FTM0SYNCBIT_MASK
Definition: S32K144.h:10871
#define SIM_SDID_GENERATION_MASK
Definition: S32K144.h:10953
#define SIM_SDID_REVID_SHIFT
Definition: S32K144.h:10938
sim_trace_clock_config_t traceClockConfig
#define SIM_MISCTRL0_FTM1_OBE_CTRL(x)
Definition: S32K144.h:10919
sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(const SIM_Type *base, uint32_t instance)
Gets the ADCx trigger select setting.
#define SIM_PLATCGC_CGCMSCM(x)
Definition: S32K144.h:10961
sim_rtc_clk_sel_src_t sourceRtcClk
#define SIM_CHIPCTL_SRAMU_RETEN_SHIFT
Definition: S32K144.h:10788
static bool SIM_HAL_GetLpo32kClkEnCmd(const SIM_Type *base)
Gets the 32 kHz LPO clock Control.
static void SIM_HAL_SetPdbBackToBackSrc(SIM_Type *base, sim_pdb_bb_src_t setting)
Set PDB back-to-back selection.
uint32_t SIM_HAL_GetLpoFreq(const SIM_Type *base)
Get SIM LPO clock frequency (LPO_CLOCK).
#define DEV_ASSERT(x)
Definition: devassert.h:78
__I uint32_t UIDL
Definition: S32K144.h:10725
#define SIM_SDID_RAMSIZE_SHIFT
Definition: S32K144.h:10942
#define NUMBER_OF_TCLK_INPUTS
static sim_eee_sram_size_t SIM_HAL_GetEeeSramSize(const SIM_Type *base)
Gets the EEE SRAM size in the Flash Configuration Register 1.
uint8_t SIM_HAL_GetFtmFaultSelMode(const SIM_Type *base, uint32_t instance)
Gets the FlexTimer x faults select settings.
static sim_lpoclk_sel_src_t SIM_HAL_GetLpoClkSrc(const SIM_Type *base)
Get the clock selection of LPOCLKSEL.
sim_plat_gate_config_t platGateConfig
void SIM_HAL_SetAdcSwPreTriggerMode(SIM_Type *base, uint32_t instance, sim_adc_sw_pretrg_sel_t select)
Sets the ADCx software pre-trigger select setting.
static uint32_t SIM_HAL_GetRevId(const SIM_Type *base)
Gets the Revision ID in the System Device ID register (SIM_SDID).
sim_adc_trg_sel_t
SIM ADCx trigger select Implements sim_adc_trg_sel_t_Class.
#define SIM_FTMOPT1_FTM3SYNCBIT_MASK
Definition: S32K144.h:10883
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN(x)
Definition: S32K144.h:10758
#define SIM_FCFG1_EEERAMSIZE_SHIFT
Definition: S32K144.h:10984
static uint32_t SIM_HAL_GetUniqueIdHigh(const SIM_Type *base)
Gets the UID127_96 from Unique Identification Register High.
static void SIM_HAL_SetAdcInterleaveSel(SIM_Type *base, uint8_t setting)
Set ADC interleave channel select.
#define SIM_LPOCLKS_RTCCLKSEL(x)
Definition: S32K144.h:10844
#define SIM_SDID_PACKAGE_SHIFT
Definition: S32K144.h:10934
__IO uint32_t MISCTRL1
Definition: S32K144.h:10728
static void SIM_HAL_SetMscmClockGate(SIM_Type *base, bool enable)
Configure the MSCM Clock Gating from the Platform Clock Gating Control Register.
static void SIM_HAL_SetSramLRetentionCmd(SIM_Type *base, bool setting)
Set SRAM L Retention setting.
static bool SIM_HAL_GetSramLRetentionCmd(const SIM_Type *base)
Get SRAM L Retention setting.
sim_clkout_src_t source
#define SIM_LPOCLKS_LPO1KCLKEN_MASK
Definition: S32K144.h:10829
sim_features_t
SIM Features Implements sim_features_t_Class.
#define SIM_FTMOPT1_FTMGLDOK_SHIFT
Definition: S32K144.h:10900
#define SIM_CHIPCTL_SRAMU_RETEN_MASK
Definition: S32K144.h:10787
#define SIM_MISCTRL0_FTM0_OBE_CTRL(x)
Definition: S32K144.h:10915
#define SIM_FTMOPT1_FTM2SYNCBIT_MASK
Definition: S32K144.h:10879
__IO uint32_t CHIPCTL
Definition: S32K144.h:10708
#define SIM_SDID_REVID_MASK
Definition: S32K144.h:10937
#define SIM_LPOCLKS_LPO1KCLKEN(x)
Definition: S32K144.h:10832
#define SIM_CHIPCTL_ADC_SUPPLY(x)
Definition: S32K144.h:10782
__I uint32_t UIDMH
Definition: S32K144.h:10723
#define SIM_PLATCGC_CGCMSCM_MASK
Definition: S32K144.h:10958
sim_pdb_bb_src_t
PDB back-to-back select Implements sim_pdb_bb_src_t_Class.
#define FTM_INSTANCE_COUNT
Definition: S32K144.h:4021
static uint32_t SIM_HAL_GetSwTriggerTrgmux(const SIM_Type *base)
Gets the Software Trigger bit to TRGMUX.
void SIM_HAL_SetFtmSyncCmd(SIM_Type *base, uint32_t instance, bool sync)
Set FlexTimer x hardware trigger 0 software synchronization.
#define SIM_MISCTRL0_FTM2_OBE_CTRL(x)
Definition: S32K144.h:10923
static void SIM_HAL_SetSwTriggerTrgmux(SIM_Type *base, bool disable)
Sets the Software Trigger bit to TRGMUX setting.
__IO uint32_t CLKDIV4
Definition: S32K144.h:10727
sim_lpoclk_sel_src_t
SIM LPOCLKSEL clock source select Implements sim_lpoclk_sel_src_t_Class.
#define SIM_MISCTRL1_SW_TRG(x)
Definition: S32K144.h:11024
#define SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT
Definition: S32K144.h:10921
static uint32_t SIM_HAL_GetUniqueIdMidHigh(const SIM_Type *base)
Gets the UID95_64 from Unique Identification Register Mid High.
clock_trace_src_t
Debug trace clock source select Implements clock_trace_src_t_Class.
sim_clock_out_config_t clockOutConfig
sim_rtc_clk_sel_src_t
SIM CLK32KSEL clock source select Implements sim_rtc_clk_sel_src_t_Class.
#define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT
Definition: S32K144.h:10876
#define SIM_CHIPCTL_PDB_BB_SEL_SHIFT
Definition: S32K144.h:10776
#define SIM_LPOCLKS_LPOCLKSEL_SHIFT
Definition: S32K144.h:10838
uint32_t SIM_HAL_GetLpo128KFreq(const SIM_Type *base)
Get SIM LPO 128KHz clock frequency (LPO_128K_CLOCK).
#define SIM_SDID_FEATURES_MASK
Definition: S32K144.h:10929
static uint32_t SIM_HAL_GetSubSeries(const SIM_Type *base)
Gets the sub-series in the System Device ID register (SIM_SDID).
sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(const SIM_Type *base, uint32_t instance, uint8_t channel)
Gets the FlexTimer x channel y output source select setting.
static void SIM_HAL_SetLpoClocks(SIM_Type *base, sim_lpo_clock_config_t setting)
Set the clock selection of LPOCLKSEL.
static void SIM_HAL_SetErmClockGate(SIM_Type *base, bool enable)
Set the ERM Clock Gate from the Platform Clock Gating Control Register.
static uint32_t SIM_HAL_GetFeatures(const SIM_Type *base)
Gets the Features from System Device ID register (SIM_SDID).
#define SIM_CHIPCTL_SRAML_RETEN_SHIFT
Definition: S32K144.h:10792
#define SIM_SDID_SUBSERIES_MASK
Definition: S32K144.h:10949
#define SIM_PLATCGC_CGCEIM_MASK
Definition: S32K144.h:10974
__IO uint32_t PLATCGC
Definition: S32K144.h:10718
sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(const SIM_Type *base, uint32_t instance, uint8_t channel)
Gets the FlexTimer x channel y input source select setting.
SIM Platform Gate Clock configuration. Implements sim_plat_gate_config_t_Class.
#define SIM_FTMOPT1_FTMGLDOK_MASK
Definition: S32K144.h:10899
#define SIM_PLATCGC_CGCDMA_MASK
Definition: S32K144.h:10966
#define SIM_FTMOPT1_FTMGLDOK(x)
Definition: S32K144.h:10902
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN_WIDTH
Definition: S32K144.h:10757
void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type *base, uint32_t instance, sim_ftm_clk_sel_t select)
Sets the FlexTimer x external clock pin select setting.
#define SIM_PLATCGC_CGCMPU_MASK
Definition: S32K144.h:10962
#define SIM_MISCTRL1_SW_TRG_MASK
Definition: S32K144.h:11021
SIM ClockOut configuration. Implements sim_clock_out_config_t_Class.
static uint32_t SIM_HAL_GetTClkFreq(SIM_Type *base, uint8_t index)
Gets the TClk Frequency.
void SIM_HAL_SetFtmFaultSelMode(SIM_Type *base, uint32_t instance, uint8_t select)
Sets the FlexTimer x faults select settings.
static void SIM_HAL_SetEimClockGate(SIM_Type *base, bool enable)
Set the EIM Clock Gate from the Platform Clock Gating Control Register.
void SIM_HAL_InitTraceClock(SIM_Type *base, const sim_trace_clock_config_t *config)
Initialize SIM Debug Trace.
#define SIM_LPOCLKS_RTCCLKSEL_SHIFT
Definition: S32K144.h:10842
#define SIM_PLATCGC_CGCMPU(x)
Definition: S32K144.h:10965
#define SIM_SDID_FEATURES_SHIFT
Definition: S32K144.h:10930
#define SIM_LPOCLKS_LPOCLKSEL_MASK
Definition: S32K144.h:10837
sim_lpo_clock_config_t lpoClockConfig
static void SIM_HAL_DeinitClkout(SIM_Type *base)
De-initialize SIM CLKOUT.
static bool SIM_HAL_GetSramURetentionCmd(const SIM_Type *base)
Get SRAM U Retention setting.
static void SIM_HAL_SetAdcSupplyEnCmd(SIM_Type *base, bool setting)
Set ADC Supply Enable setting.
#define SIM_PLATCGC_CGCMPU_SHIFT
Definition: S32K144.h:10963
#define SIM_SDID_GENERATION_SHIFT
Definition: S32K144.h:10954
#define SIM_CHIPCTL_CLKOUTEN_MASK
Definition: S32K144.h:10767
#define SIM_CHIPCTL_PDB_BB_SEL_MASK
Definition: S32K144.h:10775
__I uint32_t UIDH
Definition: S32K144.h:10722
#define SIM_CHIPCTL_SRAML_RETEN_MASK
Definition: S32K144.h:10791
sim_lpoclk_sel_src_t sourceLpoClk
#define SIM_FCFG1_DEPART_MASK
Definition: S32K144.h:10979
#define SIM_PLATCGC_CGCERM(x)
Definition: S32K144.h:10973
#define SIM_LPOCLKS_LPO32KCLKEN_SHIFT
Definition: S32K144.h:10834
#define SIM_SDID_PACKAGE_MASK
Definition: S32K144.h:10933
static uint32_t SIM_HAL_GetUniqueIdMidLow(const SIM_Type *base)
Gets the UID63_32 from Unique Identification Register Mid Low.
clock_trace_src_t source
static void SIM_HAL_SetFtmGlobalLoad(SIM_Type *base, bool enable)
Configure the FTM Global Load from the FTM Option Register 1.
static bool SIM_HAL_GetObeCtrlCmd(const SIM_Type *base, uint32_t instance)
Gets FTM channel state.
sim_clkout_src_t
SIM CLKOUT select Implements sim_clkout_src_t_Class.
static uint8_t SIM_HAL_GetAdcInterleaveSel(const SIM_Type *base)
Get ADC interleave channel select.
void SIM_HAL_SetFtmChOutSrcMode(SIM_Type *base, uint32_t instance, uint8_t channel, sim_ftm_ch_out_src_t select)
Sets the FlexTimer x channel y output source select setting.
#define SIM_LPOCLKS_LPO32KCLKEN(x)
Definition: S32K144.h:10836
#define SIM_PLATCGC_CGCDMA(x)
Definition: S32K144.h:10969
#define SIM_LPOCLKS_LPO32KCLKEN_MASK
Definition: S32K144.h:10833
#define SIM_LPOCLKS_RTCCLKSEL_MASK
Definition: S32K144.h:10841
#define SIM_FTMOPT1_FTM1SYNCBIT_MASK
Definition: S32K144.h:10875
__I uint32_t UIDML
Definition: S32K144.h:10724
SIM Platform Gate Clock configuration. Implements sim_tclk_config_t_Class.
sim_flexnvm_partition_t
SIM FlexNVM partition Implements sim_flexnvm_partition_t_Class.
#define SIM_PLATCGC_CGCMSCM_SHIFT
Definition: S32K144.h:10959
#define SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT
Definition: S32K144.h:10925
static bool SIM_HAL_GetMscmClockGate(const SIM_Type *base)
Gets the MSCM Clock Gating from the Platform Clock Gating Control Register.
#define SIM_PLATCGC_CGCEIM(x)
Definition: S32K144.h:10977
static sim_flexnvm_partition_t SIM_HAL_GetFlexNvmPartition(const SIM_Type *base)
Gets the FlexNVM partition in the Flash Configuration Register 1.
#define SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT
Definition: S32K144.h:10917
#define SIM_CHIPCTL_SRAML_RETEN(x)
Definition: S32K144.h:10794
#define SIM_SDID_RAMSIZE_MASK
Definition: S32K144.h:10941
#define SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT
Definition: S32K144.h:10913
#define SIM_CHIPCTL_ADC_SUPPLYEN_MASK
Definition: S32K144.h:10783
sim_clkout_div_t
SIM CLKOUT divider Implements sim_clkout_div_t_Class.
uint32_t SIM_HAL_GetLpo32KFreq(const SIM_Type *base)
Get SIM LPO 32KHz clock frequency (LPO_32K_CLOCK).
void SIM_HAL_GetClkoutDefaultConfig(sim_clock_out_config_t *config)
Get the default SIM CLKOUT clock configuration.
void SIM_HAL_InitClkout(SIM_Type *base, const sim_clock_out_config_t *config)
Initialize SIM CLKOUT.
sim_ftm_ch_out_src_t
SIM FlexTimer x channel y output source select Implements sim_ftm_ch_out_src_t_Class.
static bool SIM_HAL_GetFtmSyncCmd(const SIM_Type *base, uint32_t instance)
Get FlexTimer x hardware trigger software synchronization setting.
#define SIM_CHIPCTL_ADC_SUPPLY_WIDTH
Definition: S32K144.h:10781
SIM Debug Trace clock configuration. Implements sim_trace_clock_config_t_Class.
sim_adc_pretrg_sel_t
SIM ADCx pre-trigger select Implements sim_adc_pretrg_sel_t_Class.