19 #if !defined(SIM_HAL_S32K144_H)
20 #define SIM_HAL_S32K144_H
47 #define NUMBER_OF_TCLK_INPUTS 3U
357 #if defined(__cplusplus)
372 uint32_t regValue = (uint32_t)base->
CHIPCTL;
375 base->
CHIPCTL = (uint32_t)regValue;
389 uint32_t regValue = (uint32_t)base->
CHIPCTL;
391 return (regValue != 0U) ?
true :
false;
406 uint32_t regValue = (uint32_t)base->
CHIPCTL;
409 base->
CHIPCTL = (uint32_t)regValue;
423 uint32_t regValue = (uint32_t)base->
CHIPCTL;
425 return (regValue != 0U) ?
true :
false;
439 uint32_t regValue = (uint32_t)base->
CHIPCTL;
442 base->
CHIPCTL = (uint32_t)regValue;
456 uint32_t regValue = (uint32_t)base->
CHIPCTL;
458 return (regValue != 0U) ?
true :
false;
530 uint32_t settingValue, regValue;
543 regValue = (uint32_t)base->
CHIPCTL;
546 base->
CHIPCTL = (uint32_t)regValue;
651 uint32_t regValue = base->
CHIPCTL;
653 return (uint8_t)regValue;
751 uint32_t regValue = base->
LPOCLKS;
811 uint32_t regValue = (uint32_t)base->
LPOCLKS;
813 return (regValue != 0U) ?
true :
false;
827 uint32_t regValue = (uint32_t)base->
LPOCLKS;
829 return (regValue != 0U) ?
true :
false;
951 uint32_t regValue = (uint32_t)base->
FTMOPT1;
954 base->
FTMOPT1 = (uint32_t)regValue;
968 uint32_t regValue = (uint32_t)base->
FTMOPT1;
970 return (regValue != 0U) ?
true :
false;
1058 uint32_t regValue = base->
FTMOPT1;
1075 #if FTM_INSTANCE_COUNT > 4U
1077 regValue = (regValue & SIM_FTMOPT1_FTM4SYNCBIT_MASK) >> SIM_FTMOPT1_FTM4SYNCBIT_SHIFT;
1080 #if FTM_INSTANCE_COUNT > 5U
1082 regValue = (regValue & SIM_FTMOPT1_FTM5SYNCBIT_MASK) >> SIM_FTMOPT1_FTM5SYNCBIT_SHIFT;
1085 #if FTM_INSTANCE_COUNT > 6U
1087 regValue = (regValue & SIM_FTMOPT1_FTM6SYNCBIT_MASK) >> SIM_FTMOPT1_FTM6SYNCBIT_SHIFT;
1090 #if FTM_INSTANCE_COUNT > 7U
1092 regValue = (regValue & SIM_FTMOPT1_FTM7SYNCBIT_MASK) >> SIM_FTMOPT1_FTM7SYNCBIT_SHIFT;
1100 return (regValue == 0U) ?
false :
true;
1115 uint32_t settingValue = (setting ==
false) ? 0UL : 1UL;
1116 uint32_t regValue = base->
MISCTRL0;
1137 #if FTM_INSTANCE_COUNT > 4U
1139 regValue &= ~(SIM_MISCTRL0_FTM4_OBE_CTRL_MASK);
1140 regValue |= SIM_MISCTRL0_FTM4_OBE_CTRL(settingValue);
1143 #if FTM_INSTANCE_COUNT > 5U
1145 regValue &= ~(SIM_MISCTRL0_FTM5_OBE_CTRL_MASK);
1146 regValue |= SIM_MISCTRL0_FTM5_OBE_CTRL(settingValue);
1149 #if FTM_INSTANCE_COUNT > 6U
1151 regValue &= ~(SIM_MISCTRL0_FTM6_OBE_CTRL_MASK);
1152 regValue |= SIM_MISCTRL0_FTM6_OBE_CTRL(settingValue);
1155 #if FTM_INSTANCE_COUNT > 7U
1157 regValue &= ~(SIM_MISCTRL0_FTM7_OBE_CTRL_MASK);
1158 regValue |= SIM_MISCTRL0_FTM7_OBE_CTRL(settingValue);
1180 uint32_t regValue = base->
MISCTRL0;
1197 #if FTM_INSTANCE_COUNT > 4U
1199 regValue = (regValue & SIM_MISCTRL0_FTM4_OBE_CTRL_MASK) >> SIM_MISCTRL0_FTM4_OBE_CTRL_SHIFT;
1202 #if FTM_INSTANCE_COUNT > 5U
1204 regValue = (regValue & SIM_MISCTRL0_FTM5_OBE_CTRL_MASK) >> SIM_MISCTRL0_FTM5_OBE_CTRL_SHIFT;
1207 #if FTM_INSTANCE_COUNT > 6U
1209 regValue = (regValue & SIM_MISCTRL0_FTM6_OBE_CTRL_MASK) >> SIM_MISCTRL0_FTM6_OBE_CTRL_SHIFT;
1212 #if FTM_INSTANCE_COUNT > 7U
1214 regValue = (regValue & SIM_MISCTRL0_FTM7_OBE_CTRL_MASK) >> SIM_MISCTRL0_FTM7_OBE_CTRL_SHIFT;
1221 return (regValue == 0U) ?
false :
true;
1236 uint32_t regValue = base->
SDID;
1252 uint32_t regValue = base->
SDID;
1268 uint32_t regValue = base->
SDID;
1312 uint32_t regValue = base->
SDID;
1359 uint32_t regValue = base->
SDID;
1375 uint32_t regValue = (uint32_t)base->
PLATCGC;
1378 base->
PLATCGC = (uint32_t)regValue;
1392 uint32_t regValue = (uint32_t)base->
PLATCGC;
1394 return (regValue != 0U) ?
true :
false;
1408 uint32_t regValue = (uint32_t)base->
PLATCGC;
1411 base->
PLATCGC = (uint32_t)regValue;
1425 uint32_t regValue = (uint32_t)base->
PLATCGC;
1427 return (regValue != 0U) ?
true :
false;
1441 uint32_t regValue = (uint32_t)base->
PLATCGC;
1444 base->
PLATCGC = (uint32_t)regValue;
1458 uint32_t regValue = (uint32_t)base->
PLATCGC;
1460 return (regValue != 0U) ?
true :
false;
1474 uint32_t regValue = (uint32_t)base->
PLATCGC;
1477 base->
PLATCGC = (uint32_t)regValue;
1491 uint32_t regValue = (uint32_t)base->
PLATCGC;
1493 return (regValue != 0U) ?
true :
false;
1507 uint32_t regValue = (uint32_t)base->
PLATCGC;
1510 base->
PLATCGC = (uint32_t)regValue;
1524 uint32_t regValue = (uint32_t)base->
PLATCGC;
1526 return (regValue != 0U) ?
true :
false;
1722 uint32_t regValue = (uint32_t)base->
MISCTRL1;
1725 base->
MISCTRL1 = (uint32_t)regValue;
1739 uint32_t regValue = (uint32_t)base->
MISCTRL1;
1741 return (uint32_t)regValue;
1774 uint32_t retValue = 0U;
1783 #if defined(__cplusplus)
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT
sim_eee_sram_size_t
SIM EEE SRAM Size Implements sim_eee_sram_size_t_Class.
sim_adc_sw_pretrg_sel_t SIM_HAL_GetAdcSwPreTriggerMode(const SIM_Type *base, uint32_t instance)
Gets the ADCx software pre-trigger select setting.
void SIM_HAL_SetAdcTriggerMode(SIM_Type *base, uint32_t instance, sim_adc_trg_sel_t select)
Sets the ADCx trigger select setting.
static void SIM_HAL_SetDmaClockGate(SIM_Type *base, bool enable)
Set the DMA Clock Gate from the Platform Clock Gating Control Register.
uint32_t SIM_HAL_GetLpo1KFreq(const SIM_Type *base)
Get SIM LPO 1KHz clock frequency (LPO_1K_CLOCK).
static sim_ram_size_t SIM_HAL_GetRamSize(const SIM_Type *base)
Gets RAM size.
sim_adc_supply_src_t
Internal supplies monitored by ADC_SUPPLY Implements sim_adc_supply_src_t_Class.
static void SIM_HAL_SetObeCtrlCmd(SIM_Type *base, uint32_t instance, bool setting)
Sets FTM channel state.
SIM LPO Clocks configuration. Implements sim_lpo_clock_config_t_Class.
sim_adc_pretrg_sel_t SIM_HAL_GetAdcPreTriggerMode(const SIM_Type *base, uint32_t instance)
Gets the ADCx pre-trigger select setting.
#define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT
#define SIM_PLATCGC_CGCEIM_SHIFT
static bool SIM_HAL_GetDmaClockGate(const SIM_Type *base)
Gets the DMA Clock Gate from the Platform Clock Gating Control Register.
sim_tclk_config_t tclkConfig
static void SIM_HAL_SetTClkFreq(SIM_Type *base, uint8_t index, uint32_t frequency)
Sets the TClk Frequency.
sim_ftm_ch_src_t
SIM FlexTimer x channel y input source select Implements sim_ftm_ch_src_t_Class.
static sim_adc_supply_src_t SIM_HAL_GetAdcSupplySrc(const SIM_Type *base)
Get ADC supply source.
static uint32_t SIM_HAL_GetDerivate(const SIM_Type *base)
Gets the Derivate from the System Device ID register (SIM_SDID).
#define SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT
#define SIM_SDID_SUBSERIES_SHIFT
#define SIM_LPOCLKS_LPO1KCLKEN_SHIFT
sim_ftm_clk_sel_t
SIM FlexTimer external clock select Implements sim_ftm_clk_sel_t_Class.
#define SIM_MISCTRL0_FTM3_OBE_CTRL(x)
void SIM_HAL_GetTraceClockDefaultConfig(sim_trace_clock_config_t *config)
Get the default Debug Trace clock configuration.
static bool SIM_HAL_GetLpo1kClkEnCmd(const SIM_Type *base)
Gets the 1 kHz LPO clock Control.
#define SIM_CHIPCTL_ADC_SUPPLYEN(x)
static sim_pdb_bb_src_t SIM_HAL_GetPdbBackToBackSrc(const SIM_Type *base)
Get PDB back-to-back selection.
#define SIM_CHIPCTL_SRAMU_RETEN(x)
#define SIM_MISCTRL0_FTM2_OBE_CTRL_MASK
#define SIM_CLKDIV4_TRACEDIVEN_MASK
#define SIM_PLATCGC_CGCERM_MASK
#define SIM_SDID_DERIVATE_SHIFT
sim_ram_size_t
SIM RAM size Implements sim_ram_size_t_Class.
static bool SIM_HAL_GetMpuClockGate(const SIM_Type *base)
Gets the MPU Clock Gating from the Platform Clock Gating Control Register.
sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode(const SIM_Type *base, uint32_t instance)
Gets the FlexTimer x external clock pin select setting.
#define SIM_CHIPCTL_PDB_BB_SEL(x)
#define SIM_MISCTRL0_FTM0_OBE_CTRL_MASK
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK
uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]
void SIM_HAL_GetClkoutConfig(const SIM_Type *base, sim_clock_out_config_t *config)
Get the SIM CLKOUT clock configuration.
#define SIM_FTMOPT1_FTM3SYNCBIT_SHIFT
#define SIM_LPOCLKS_LPOCLKSEL(x)
void SIM_HAL_SetAdcPreTriggerMode(SIM_Type *base, uint32_t instance, sim_adc_pretrg_sel_t select)
Sets the ADCx pre-trigger select setting.
#define SIM_SDID_DERIVATE_MASK
static void SIM_HAL_DeinitTraceClock(SIM_Type *base)
De-initialize SIM Debug Trace.
#define SIM_CHIPCTL_ADC_SUPPLY_SHIFT
static uint32_t SIM_HAL_GetUniqueIdLow(const SIM_Type *base)
Gets the UID31_0 from Unique Identification Register Low.
SIM configure structure. Implements sim_clock_config_t_Class.
#define SIM_MISCTRL1_SW_TRG_SHIFT
#define SIM_FTMOPT1_FTM2SYNCBIT_SHIFT
static void SIM_HAL_SetAdcSupplySrc(SIM_Type *base, sim_adc_supply_src_t setting)
Set ADC Supply Enable setting.
static sim_package_t SIM_HAL_GetPackage(const SIM_Type *base)
Gets the Package in System Device ID register (SIM_SDID).
#define SIM_MISCTRL0_FTM3_OBE_CTRL_MASK
static sim_rtc_clk_sel_src_t SIM_HAL_GetRtcClkSrc(const SIM_Type *base)
Get the clock selection of RTCCLKSEL.
#define SIM_PLATCGC_CGCDMA_SHIFT
static bool SIM_HAL_GetAdcSupplyEnCmd(const SIM_Type *base)
Get ADC Supply Enable setting.
void SIM_HAL_SetFtmChSrcMode(SIM_Type *base, uint32_t instance, uint8_t channel, sim_ftm_ch_src_t select)
Sets the FlexTimer x channel y input source select setting.
static bool SIM_HAL_GetEimClockGate(const SIM_Type *base)
Gets the EIM Clock Gate from the Platform Clock Gating Control Register.
sim_adc_sw_pretrg_sel_t
SIM ADCx software pre-trigger select Implements sim_adc_sw_pretrg_sel_t_Class.
static void SIM_HAL_SetSramURetentionCmd(SIM_Type *base, bool setting)
Set SRAM U Retention setting.
#define SIM_FCFG1_EEERAMSIZE_MASK
sim_package_t
SIM Package Implements sim_package_t_Class.
static uint32_t SIM_HAL_GetGeneration(const SIM_Type *base)
Gets the product series Generation from System Device ID register (SIM_SDID).
#define SIM_MISCTRL0_FTM1_OBE_CTRL_MASK
static void SIM_HAL_SetMpuClockGate(SIM_Type *base, bool enable)
Configure the MPU Clock Gating from the Platform Clock Gating Control Register.
#define SIM_CHIPCTL_ADC_SUPPLY_MASK
#define SIM_PLATCGC_CGCERM_SHIFT
static bool SIM_HAL_GetFtmGlobalLoad(const SIM_Type *base)
Gets the FTM Global Load from the FTM Option Register 1.
#define SIM_FCFG1_DEPART_SHIFT
static bool SIM_HAL_GetErmClockGate(const SIM_Type *base)
Gets the ERM Clock Gate from the Platform Clock Gating Control Register.
#define SIM_FTMOPT1_FTM0SYNCBIT_MASK
#define SIM_SDID_GENERATION_MASK
#define SIM_SDID_REVID_SHIFT
sim_trace_clock_config_t traceClockConfig
#define SIM_MISCTRL0_FTM1_OBE_CTRL(x)
sim_adc_trg_sel_t SIM_HAL_GetAdcTriggerMode(const SIM_Type *base, uint32_t instance)
Gets the ADCx trigger select setting.
#define SIM_PLATCGC_CGCMSCM(x)
sim_rtc_clk_sel_src_t sourceRtcClk
#define SIM_CHIPCTL_SRAMU_RETEN_SHIFT
static bool SIM_HAL_GetLpo32kClkEnCmd(const SIM_Type *base)
Gets the 32 kHz LPO clock Control.
static void SIM_HAL_SetPdbBackToBackSrc(SIM_Type *base, sim_pdb_bb_src_t setting)
Set PDB back-to-back selection.
uint32_t SIM_HAL_GetLpoFreq(const SIM_Type *base)
Get SIM LPO clock frequency (LPO_CLOCK).
#define SIM_SDID_RAMSIZE_SHIFT
#define NUMBER_OF_TCLK_INPUTS
static sim_eee_sram_size_t SIM_HAL_GetEeeSramSize(const SIM_Type *base)
Gets the EEE SRAM size in the Flash Configuration Register 1.
uint8_t SIM_HAL_GetFtmFaultSelMode(const SIM_Type *base, uint32_t instance)
Gets the FlexTimer x faults select settings.
static sim_lpoclk_sel_src_t SIM_HAL_GetLpoClkSrc(const SIM_Type *base)
Get the clock selection of LPOCLKSEL.
sim_plat_gate_config_t platGateConfig
void SIM_HAL_SetAdcSwPreTriggerMode(SIM_Type *base, uint32_t instance, sim_adc_sw_pretrg_sel_t select)
Sets the ADCx software pre-trigger select setting.
static uint32_t SIM_HAL_GetRevId(const SIM_Type *base)
Gets the Revision ID in the System Device ID register (SIM_SDID).
sim_adc_trg_sel_t
SIM ADCx trigger select Implements sim_adc_trg_sel_t_Class.
#define SIM_FTMOPT1_FTM3SYNCBIT_MASK
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN(x)
#define SIM_FCFG1_EEERAMSIZE_SHIFT
static uint32_t SIM_HAL_GetUniqueIdHigh(const SIM_Type *base)
Gets the UID127_96 from Unique Identification Register High.
static void SIM_HAL_SetAdcInterleaveSel(SIM_Type *base, uint8_t setting)
Set ADC interleave channel select.
#define SIM_LPOCLKS_RTCCLKSEL(x)
#define SIM_SDID_PACKAGE_SHIFT
static void SIM_HAL_SetMscmClockGate(SIM_Type *base, bool enable)
Configure the MSCM Clock Gating from the Platform Clock Gating Control Register.
static void SIM_HAL_SetSramLRetentionCmd(SIM_Type *base, bool setting)
Set SRAM L Retention setting.
static bool SIM_HAL_GetSramLRetentionCmd(const SIM_Type *base)
Get SRAM L Retention setting.
#define SIM_LPOCLKS_LPO1KCLKEN_MASK
sim_features_t
SIM Features Implements sim_features_t_Class.
#define SIM_FTMOPT1_FTMGLDOK_SHIFT
#define SIM_CHIPCTL_SRAMU_RETEN_MASK
#define SIM_MISCTRL0_FTM0_OBE_CTRL(x)
#define SIM_FTMOPT1_FTM2SYNCBIT_MASK
#define SIM_SDID_REVID_MASK
#define SIM_LPOCLKS_LPO1KCLKEN(x)
#define SIM_CHIPCTL_ADC_SUPPLY(x)
#define SIM_PLATCGC_CGCMSCM_MASK
sim_pdb_bb_src_t
PDB back-to-back select Implements sim_pdb_bb_src_t_Class.
#define FTM_INSTANCE_COUNT
static uint32_t SIM_HAL_GetSwTriggerTrgmux(const SIM_Type *base)
Gets the Software Trigger bit to TRGMUX.
void SIM_HAL_SetFtmSyncCmd(SIM_Type *base, uint32_t instance, bool sync)
Set FlexTimer x hardware trigger 0 software synchronization.
#define SIM_MISCTRL0_FTM2_OBE_CTRL(x)
static void SIM_HAL_SetSwTriggerTrgmux(SIM_Type *base, bool disable)
Sets the Software Trigger bit to TRGMUX setting.
sim_lpoclk_sel_src_t
SIM LPOCLKSEL clock source select Implements sim_lpoclk_sel_src_t_Class.
#define SIM_MISCTRL1_SW_TRG(x)
#define SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT
static uint32_t SIM_HAL_GetUniqueIdMidHigh(const SIM_Type *base)
Gets the UID95_64 from Unique Identification Register Mid High.
clock_trace_src_t
Debug trace clock source select Implements clock_trace_src_t_Class.
sim_clock_out_config_t clockOutConfig
sim_rtc_clk_sel_src_t
SIM CLK32KSEL clock source select Implements sim_rtc_clk_sel_src_t_Class.
#define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT
#define SIM_CHIPCTL_PDB_BB_SEL_SHIFT
#define SIM_LPOCLKS_LPOCLKSEL_SHIFT
uint32_t SIM_HAL_GetLpo128KFreq(const SIM_Type *base)
Get SIM LPO 128KHz clock frequency (LPO_128K_CLOCK).
#define SIM_SDID_FEATURES_MASK
static uint32_t SIM_HAL_GetSubSeries(const SIM_Type *base)
Gets the sub-series in the System Device ID register (SIM_SDID).
sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode(const SIM_Type *base, uint32_t instance, uint8_t channel)
Gets the FlexTimer x channel y output source select setting.
static void SIM_HAL_SetLpoClocks(SIM_Type *base, sim_lpo_clock_config_t setting)
Set the clock selection of LPOCLKSEL.
static void SIM_HAL_SetErmClockGate(SIM_Type *base, bool enable)
Set the ERM Clock Gate from the Platform Clock Gating Control Register.
static uint32_t SIM_HAL_GetFeatures(const SIM_Type *base)
Gets the Features from System Device ID register (SIM_SDID).
#define SIM_CHIPCTL_SRAML_RETEN_SHIFT
#define SIM_SDID_SUBSERIES_MASK
#define SIM_PLATCGC_CGCEIM_MASK
sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode(const SIM_Type *base, uint32_t instance, uint8_t channel)
Gets the FlexTimer x channel y input source select setting.
SIM Platform Gate Clock configuration. Implements sim_plat_gate_config_t_Class.
#define SIM_FTMOPT1_FTMGLDOK_MASK
#define SIM_PLATCGC_CGCDMA_MASK
#define SIM_FTMOPT1_FTMGLDOK(x)
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN_WIDTH
void SIM_HAL_SetFtmExternalClkPinMode(SIM_Type *base, uint32_t instance, sim_ftm_clk_sel_t select)
Sets the FlexTimer x external clock pin select setting.
#define SIM_PLATCGC_CGCMPU_MASK
#define SIM_MISCTRL1_SW_TRG_MASK
SIM ClockOut configuration. Implements sim_clock_out_config_t_Class.
static uint32_t SIM_HAL_GetTClkFreq(SIM_Type *base, uint8_t index)
Gets the TClk Frequency.
void SIM_HAL_SetFtmFaultSelMode(SIM_Type *base, uint32_t instance, uint8_t select)
Sets the FlexTimer x faults select settings.
static void SIM_HAL_SetEimClockGate(SIM_Type *base, bool enable)
Set the EIM Clock Gate from the Platform Clock Gating Control Register.
void SIM_HAL_InitTraceClock(SIM_Type *base, const sim_trace_clock_config_t *config)
Initialize SIM Debug Trace.
#define SIM_LPOCLKS_RTCCLKSEL_SHIFT
#define SIM_PLATCGC_CGCMPU(x)
#define SIM_SDID_FEATURES_SHIFT
#define SIM_LPOCLKS_LPOCLKSEL_MASK
sim_lpo_clock_config_t lpoClockConfig
static void SIM_HAL_DeinitClkout(SIM_Type *base)
De-initialize SIM CLKOUT.
static bool SIM_HAL_GetSramURetentionCmd(const SIM_Type *base)
Get SRAM U Retention setting.
static void SIM_HAL_SetAdcSupplyEnCmd(SIM_Type *base, bool setting)
Set ADC Supply Enable setting.
#define SIM_PLATCGC_CGCMPU_SHIFT
#define SIM_SDID_GENERATION_SHIFT
#define SIM_CHIPCTL_CLKOUTEN_MASK
#define SIM_CHIPCTL_PDB_BB_SEL_MASK
#define SIM_CHIPCTL_SRAML_RETEN_MASK
sim_lpoclk_sel_src_t sourceLpoClk
#define SIM_FCFG1_DEPART_MASK
#define SIM_PLATCGC_CGCERM(x)
#define SIM_LPOCLKS_LPO32KCLKEN_SHIFT
#define SIM_SDID_PACKAGE_MASK
static uint32_t SIM_HAL_GetUniqueIdMidLow(const SIM_Type *base)
Gets the UID63_32 from Unique Identification Register Mid Low.
static void SIM_HAL_SetFtmGlobalLoad(SIM_Type *base, bool enable)
Configure the FTM Global Load from the FTM Option Register 1.
static bool SIM_HAL_GetObeCtrlCmd(const SIM_Type *base, uint32_t instance)
Gets FTM channel state.
sim_clkout_src_t
SIM CLKOUT select Implements sim_clkout_src_t_Class.
static uint8_t SIM_HAL_GetAdcInterleaveSel(const SIM_Type *base)
Get ADC interleave channel select.
void SIM_HAL_SetFtmChOutSrcMode(SIM_Type *base, uint32_t instance, uint8_t channel, sim_ftm_ch_out_src_t select)
Sets the FlexTimer x channel y output source select setting.
#define SIM_LPOCLKS_LPO32KCLKEN(x)
#define SIM_PLATCGC_CGCDMA(x)
#define SIM_LPOCLKS_LPO32KCLKEN_MASK
#define SIM_LPOCLKS_RTCCLKSEL_MASK
#define SIM_FTMOPT1_FTM1SYNCBIT_MASK
SIM Platform Gate Clock configuration. Implements sim_tclk_config_t_Class.
sim_flexnvm_partition_t
SIM FlexNVM partition Implements sim_flexnvm_partition_t_Class.
#define SIM_PLATCGC_CGCMSCM_SHIFT
#define SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT
static bool SIM_HAL_GetMscmClockGate(const SIM_Type *base)
Gets the MSCM Clock Gating from the Platform Clock Gating Control Register.
#define SIM_PLATCGC_CGCEIM(x)
static sim_flexnvm_partition_t SIM_HAL_GetFlexNvmPartition(const SIM_Type *base)
Gets the FlexNVM partition in the Flash Configuration Register 1.
#define SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT
#define SIM_CHIPCTL_SRAML_RETEN(x)
#define SIM_SDID_RAMSIZE_MASK
#define SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT
#define SIM_CHIPCTL_ADC_SUPPLYEN_MASK
sim_clkout_div_t
SIM CLKOUT divider Implements sim_clkout_div_t_Class.
uint32_t SIM_HAL_GetLpo32KFreq(const SIM_Type *base)
Get SIM LPO 32KHz clock frequency (LPO_32K_CLOCK).
void SIM_HAL_GetClkoutDefaultConfig(sim_clock_out_config_t *config)
Get the default SIM CLKOUT clock configuration.
void SIM_HAL_InitClkout(SIM_Type *base, const sim_clock_out_config_t *config)
Initialize SIM CLKOUT.
sim_ftm_ch_out_src_t
SIM FlexTimer x channel y output source select Implements sim_ftm_ch_out_src_t_Class.
static bool SIM_HAL_GetFtmSyncCmd(const SIM_Type *base, uint32_t instance)
Get FlexTimer x hardware trigger software synchronization setting.
#define SIM_CHIPCTL_ADC_SUPPLY_WIDTH
SIM Debug Trace clock configuration. Implements sim_trace_clock_config_t_Class.
sim_adc_pretrg_sel_t
SIM ADCx pre-trigger select Implements sim_adc_pretrg_sel_t_Class.