S32 SDK
system_S32K144.c
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1 /*
2  * Copyright (c) 2015 Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
46 #include "device_registers.h"
47 #include "system_S32K144.h"
48 #include "stdbool.h"
49 
50 /* ----------------------------------------------------------------------------
51  -- Core clock
52  ---------------------------------------------------------------------------- */
53 
55 
56 /*FUNCTION**********************************************************************
57  *
58  * Function Name : SystemInit
59  * Description : This function disables the watchdog, enables FPU
60  * and the power mode protection if the corresponding feature macro
61  * is enabled. SystemInit is called from startup_device file.
62  *
63  * Implements : SystemInit_Activity
64  *END**************************************************************************/
65 void SystemInit(void)
66 {
67 /**************************************************************************/
68  /* FPU ENABLE*/
69 /**************************************************************************/
70 #ifdef ENABLE_FPU
71  /* Enable CP10 and CP11 coprocessors */
73 #ifdef ERRATA_E6940
74  /* Disable lazy context save of floating point state by clearing LSPEN bit
75  * Workaround for errata e6940 */
76  S32_SCB->FPCCR &= ~(S32_SCB_FPCCR_LSPEN_MASK);
77 #endif
78 #endif /* ENABLE_FPU */
79 
80 /**************************************************************************/
81  /* WDOG DISABLE*/
82 /**************************************************************************/
83 
84 #if (DISABLE_WDOG)
85  /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/
86  WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE;
87  /* The dummy read is used in order to make sure that the WDOG registers will be configured only
88  * after the write of the unlock value was completed. */
89  (void)WDOG->CNT;
90 
91  /* Initial write of WDOG configuration register:
92  * enables support for 32-bit refresh/unlock command write words,
93  * clock select from LPO, update enable, watchdog disabled */
94  WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) |
96  (0U << WDOG_CS_EN_SHIFT) |
97  (1U << WDOG_CS_UPDATE_SHIFT) );
98 
99  /* Configure timeout */
100  WDOG->TOVAL = (uint32_t )0xFFFF;
101 #endif /* (DISABLE_WDOG) */
102 
103 /**************************************************************************/
104  /* Power mode protection */
105 /**************************************************************************/
106 #ifdef SYSTEM_SMC_PMPROT_VALUE
107  /* Power mode protection initialization */
108  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
109 #endif
110 }
111 
112 /*FUNCTION**********************************************************************
113  *
114  * Function Name : SystemCoreClockUpdate
115  * Description : This function must be called whenever the core clock is changed
116  * during program execution. It evaluates the clock register settings and calculates
117  * the current core clock.
118  *
119  * Implements : SystemCoreClockUpdate_Activity
120  *END**************************************************************************/
122 {
123  uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */
124  uint32_t regValue; /* Temporary variable */
125  uint32_t divider, prediv, multi;
126  bool validSystemClockSource = true;
127  static const uint32_t fircFreq[] = {
132  };
133 
134  divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U;
135 
136  switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
137  case 0x1:
138  /* System OSC */
139  SCGOUTClock = CPU_XTAL_CLK_HZ;
140  break;
141  case 0x2:
142  /* Slow IRC */
143  regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
144  SCGOUTClock = (regValue != 0U) ?
146  break;
147  case 0x3:
148  /* Fast IRC */
149  regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
150  SCGOUTClock= fircFreq[regValue];
151  break;
152  case 0x6:
153  /* System PLL */
154  SCGOUTClock = CPU_XTAL_CLK_HZ;
155  prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U;
156  multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U;
157  SCGOUTClock = SCGOUTClock * multi / (prediv * 2U);
158  break;
159  default:
160  validSystemClockSource = false;
161  break;
162  }
163 
164  if (validSystemClockSource == true) {
165  SystemCoreClock = (SCGOUTClock / divider);
166  }
167 }
168 
169 /*FUNCTION**********************************************************************
170  *
171  * Function Name : SystemSoftwareReset
172  * Description : This function is used to initiate a system reset
173  *
174  * Implements : SystemSoftwareReset_Activity
175  *END**************************************************************************/
177 {
178  uint32_t regValue;
179 
180  /* Read Application Interrupt and Reset Control Register */
181  regValue = S32_SCB->AIRCR;
182 
183  /* Clear register key */
184  regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
185 
186  /* Configure System reset request bit and Register Key */
188  regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
189 
190  /* Write computed register value */
191  S32_SCB->AIRCR = regValue;
192 }
193 
194 /*******************************************************************************
195  * EOF
196  ******************************************************************************/
#define SMC
Definition: S32K144.h:11066
#define SCG_SPLLCFG_MULT_MASK
Definition: S32K144.h:10678
#define DEFAULT_SYSTEM_CLOCK
uint32_t SystemCoreClock
System clock frequency (core clock)
void SystemInit(void)
Setup the SoC.
#define CPU_XTAL_CLK_HZ
#define SCG_FIRCCFG_RANGE_SHIFT
Definition: S32K144.h:10632
#define FEATURE_WDOG_UNLOCK_VALUE
#define WDOG_CS_CMD32EN_SHIFT
Definition: S32K144.h:11344
void SystemSoftwareReset(void)
Initiates a system reset.
#define WDOG_CS_CLK_SHIFT
Definition: S32K144.h:11328
#define SCG_CSR_SCS_MASK
Definition: S32K144.h:10446
#define S32_SCB_AIRCR_SYSRESETREQ(x)
Definition: S32K144.h:9906
#define SCG_FIRCCFG_RANGE_MASK
Definition: S32K144.h:10631
#define S32_SCB_CPACR_CP10_MASK
Definition: S32K144.h:10172
#define FEATURE_SCG_FIRC_FREQ1
#define SCG_CSR_DIVCORE_SHIFT
Definition: S32K144.h:10443
#define FEATURE_SCB_VECTKEY
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
#define SCG_CSR_DIVCORE_MASK
Definition: S32K144.h:10442
#define S32_SCB_AIRCR_VECTKEY(x)
Definition: S32K144.h:9918
#define FEATURE_SCG_FIRC_FREQ0
#define S32_SCB
Definition: S32K144.h:9795
#define SCG_CSR_SCS_SHIFT
Definition: S32K144.h:10447
#define FEATURE_WDOG_CLK_FROM_LPO
#define FEATURE_SCG_SIRC_LOW_RANGE_FREQ
#define SCG_SPLLCFG_PREDIV_MASK
Definition: S32K144.h:10674
Device specific configuration file for S32K144.
#define S32_SCB_FPCCR_LSPEN_MASK
Definition: S32K144.h:10209
#define SCG
Definition: S32K144.h:10398
#define FEATURE_SCG_FIRC_FREQ2
#define S32_SCB_AIRCR_VECTKEY_MASK
Definition: S32K144.h:9915
#define SCG_SIRCCFG_RANGE_SHIFT
Definition: S32K144.h:10593
#define FEATURE_SCG_FIRC_FREQ3
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock variable.
#define SCG_SPLLCFG_MULT_SHIFT
Definition: S32K144.h:10679
#define SCG_SPLLCFG_PREDIV_SHIFT
Definition: S32K144.h:10675
#define S32_SCB_CPACR_CP11_MASK
Definition: S32K144.h:10176
#define SCG_SIRCCFG_RANGE_MASK
Definition: S32K144.h:10592
#define WDOG_CS_UPDATE_SHIFT
Definition: S32K144.h:11316
#define WDOG_CS_EN_SHIFT
Definition: S32K144.h:11324
#define WDOG
Definition: S32K144.h:11277