92 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT (31U)
94 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT (30U)
96 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT (15U)
98 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT (14U)
100 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK (0x3FFFFFFFU)
102 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT (1U)
104 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK (0x3FF80000U)
106 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT (19U)
108 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK (0x3FFFU)
110 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1 (16U)
112 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2 (0U)
114 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK (0x7FFU)
116 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1 (19U)
118 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2 (3U)
120 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK (0xFFU)
122 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1 (24U)
124 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2 (16U)
126 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3 (8U)
128 #define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4 (0U)
130 #define FLEXCAN_ALL_INT (0x0007U)
134 #define CAN_DLC_VALUE_12_BYTES 9U
135 #define CAN_DLC_VALUE_16_BYTES 10U
136 #define CAN_DLC_VALUE_20_BYTES 11U
137 #define CAN_DLC_VALUE_24_BYTES 12U
138 #define CAN_DLC_VALUE_32_BYTES 13U
139 #define CAN_DLC_VALUE_48_BYTES 14U
140 #define CAN_DLC_VALUE_64_BYTES 15U
142 #define RxFifoFilterTableOffset 0x18U
144 #define FlexCanRxFifoAcceptRemoteFrame 1UL
145 #define FlexCanRxFifoAcceptExtFrame 1UL
147 #define FLEXCAN_8_BYTE_PAYLOAD_MB_SIZE 16U
148 #define FLEXCAN_ARBITRATION_FIELD_SIZE 8U
162 return (5U + ((((x) + 1U) * 8U) / 4U));
167 #define FlexcanSwapBytesInWordIndex(index) (((index) & ~3U) + (3U - ((index) & 3U)))
170 #define RxFifoFilterElementNum(x) (((x) + 1U) * 8U)
185 uint8_t arbitration_field_size = 8U;
187 uint8_t mb_size = (uint8_t)(payload_size + arbitration_field_size);
189 uint32_t mb_index = msgBuffIdx * ((uint32_t)mb_size >> 2U);
191 return &(base->
RAMn[mb_index]);
205 if (payloadSize <= 8U)
209 else if ((payloadSize > 8U) && (payloadSize <= 12U))
213 else if ((payloadSize > 12U) && (payloadSize <= 16U))
217 else if ((payloadSize > 16U) && (payloadSize <= 20U))
221 else if ((payloadSize > 20U) && (payloadSize <= 24U))
225 else if ((payloadSize > 24U) && (payloadSize <= 32U))
229 else if ((payloadSize > 32U) && (payloadSize <= 48U))
233 else if ((payloadSize > 48U) && (payloadSize <= 64U))
311 #if (CAN_INSTANCE_COUNT > 1U)
318 #if (CAN_INSTANCE_COUNT > 2U)
338 volatile uint32_t *RAM = base->
RAMn;
341 for (databyte = 0; databyte < RAM_size; databyte++) {
354 #if defined(CPU_S32V234)
357 base->
CTRL2 = (base->
CTRL2 & ~CAN_CTRL2_WRMFRZ_MASK) | CAN_CTRL2_WRMFRZ(1U);
362 for (databyte = FEATURE_CAN_SMB_FD_START_ADDRESS_OFFSET; databyte < FEATURE_CAN_SMB_FD_END_ADDRESS_OFFSET; databyte++) {
367 base->
CTRL2 = (base->
CTRL2 & ~CAN_CTRL2_WRMFRZ_MASK) | CAN_CTRL2_WRMFRZ(0U);
422 #if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
608 const uint8_t *msgData)
612 uint32_t val1, val2 = 1;
613 uint32_t flexcan_mb_config = 0;
620 volatile uint32_t *flexcan_mb_id = &flexcan_mb[1];
621 volatile uint8_t *flexcan_mb_data = (
volatile uint8_t *)(&flexcan_mb[2]);
622 volatile uint32_t *flexcan_mb_data_32 = &flexcan_mb[2];
623 const uint32_t *msgData_32 = (
const uint32_t *)msgData;
641 if (msgBuffIdx <= val2) {
661 for (databyte = 0; databyte < cs->
dataLen; databyte += 4U)
663 REV_BYTES_32(msgData_32[databyte >> 2U], flexcan_mb_data_32[databyte >> 2U]);
665 for ( ; databyte < cs->
dataLen; databyte++)
670 for (databyte = cs->
dataLen; databyte < payload_size; databyte++)
734 *flexcan_mb |= flexcan_mb_config;
760 uint32_t val1, val2 = 1;
763 volatile uint32_t *flexcan_mb_id = &flexcan_mb[1];
782 if (msgBuffIdx <= val2) {
846 uint32_t val1, val2 = 1;
850 volatile const uint32_t *flexcan_mb_id = &flexcan_mb[1];
851 volatile const uint8_t *flexcan_mb_data = (
volatile const uint8_t *)(&flexcan_mb[2]);
852 volatile const uint32_t *flexcan_mb_data_32 = &flexcan_mb[2];
853 uint32_t *msgBuff_data_32 = (uint32_t *)(msgBuff->
data);
856 uint8_t flexcan_mb_dlc_value = (uint8_t)(((*flexcan_mb) &
CAN_CS_DLC_MASK) >> 16);
859 msgBuff->
dataLen = payload_size;
877 if (msgBuffIdx <= val2) {
885 msgBuff->
cs = *flexcan_mb;
888 msgBuff->
msgId = (*flexcan_mb_id);
896 for (i = 0 ; i < payload_size ; i += 4U)
898 mbWord = flexcan_mb_data_32[i >> 2U];
901 for ( ; i < payload_size ; i++)
1035 uint32_t maxMsgBuffNum)
1048 if (maxMsgBuffNum > max_mb_num)
1061 for (msgBuffIdx = 0; msgBuffIdx < maxMsgBuffNum; msgBuffIdx++)
1064 volatile uint32_t *flexcan_mb_id = &flexcan_mb[1];
1065 volatile uint8_t *flexcan_mb_data = (
volatile uint8_t *)(&flexcan_mb[2]);
1068 *flexcan_mb_id = 0x0;
1069 for (databyte = 0; databyte < can_real_payload; databyte++)
1071 flexcan_mb_data[databyte] = 0x0;
1098 uint32_t i, j, numOfFilters;
1099 uint32_t val1 = 0, val2 = 0, val = 0;
1122 filterTable[i] = val + ((idFilterTable->
idFilter[i] <<
1128 filterTable[i] = val + ((idFilterTable->
idFilter[i] <<
1153 filterTable[i] = val1 + ((idFilterTable->
idFilter[j] &
1156 filterTable[i] |= val2 + ((idFilterTable->
idFilter[j + 1U] &
1162 filterTable[i] = val1 + ((idFilterTable->
idFilter[j] &
1165 filterTable[i] |= val2 + ((idFilterTable->
idFilter[j + 1U] &
1178 filterTable[i] = ((idFilterTable->
idFilter[j] &
1181 filterTable[i] = ((idFilterTable->
idFilter[j + 1U] &
1184 filterTable[i] = ((idFilterTable->
idFilter[j + 2U] &
1187 filterTable[i] = ((idFilterTable->
idFilter[j + 3U] &
1212 uint32_t msgBuffIdx,
bool enable)
1225 temp = 1UL << msgBuffIdx;
1228 (base->
IMASK1) = ((base ->IMASK1) | (temp));
1249 uint32_t temp = (uint32_t)errType;
1306 uint32_t msgBuffIdx)
1309 return (uint8_t)((base->
IFLAG1 >> msgBuffIdx) & 1U);
1367 volatile const uint32_t *flexcan_mb = base->
RAMn;
1368 volatile const uint32_t *flexcan_mb_id = &base->
RAMn[1];
1369 volatile const uint32_t *flexcan_mb_data_32 = &flexcan_mb[2];
1370 uint32_t *msgData_32 = (uint32_t *)(rxFifo->
data);
1372 uint8_t flexcan_mb_dlc_value = (uint8_t)(((*flexcan_mb) &
CAN_CS_DLC_MASK) >> 16);
1375 rxFifo->
dataLen = can_real_payload;
1376 rxFifo->
cs = *flexcan_mb;
1380 rxFifo->
msgId = *flexcan_mb_id;
1388 for (databyte = 0; databyte < can_real_payload; databyte += 4U)
1390 mbWord = flexcan_mb_data_32[databyte >> 2U];
1478 uint32_t msgBuffIdx,
1512 uint32_t msgBuffIdx,
1818 #if FEATURE_CAN_HAS_MBDSR1
1819 tmp &= ~(CAN_FDCTRL_MBDSR1_MASK);
1820 tmp |= ((uint32_t)payloadSize) << CAN_FDCTRL_MBDSR1_SHIFT;
1838 uint32_t payloadSize;
1850 return (uint8_t)payloadSize;
1865 #if FEATURE_CAN_HAS_STFCNTEN_ENABLE
1866 base->
CTRL2 = (base->
CTRL2 & ~CAN_CTRL2_STFCNTEN_MASK) | CAN_CTRL2_STFCNTEN(enable? 1UL : 0UL);
1867 #elif FEATURE_CAN_HAS_ISOCANFDEN_ENABLE
1891 #if FEATURE_CAN_HAS_DMA_ENABLE
1902 if (enable && (rxFifoEnabled == 0U))
1949 #if FEATURE_CAN_HAS_PRETENDED_NETWORKING
2064 uint32_t *tmp, wmbData;
2066 tmp = (uint32_t *)&wmb->
data[0];
2070 tmp = (uint32_t *)&wmb->
data[4];
#define CAN_PL1_LO_Data_byte_1(x)
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2
#define CAN_MCR_SRXDIS(x)
status_t FLEXCAN_HAL_SetRxFifoDMA(CAN_Type *base, bool enable)
Enables/Disables the DMA support for RxFIFO.
#define CAN_PL2_PLMASK_HI_Data_byte_7(x)
void FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX Message Buffer global extended mask.
void FLEXCAN_HAL_SetTimeSegmentsCbt(CAN_Type *base, const flexcan_time_segment_t *timeSeg)
Sets the FlexCAN time segments for setting up bit rate for FD BRS.
void FLEXCAN_HAL_ClearErrIntStatusFlag(CAN_Type *base)
Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup).
#define CAN_DLC_VALUE_20_BYTES
#define CAN_FLT_DLC_FLT_DLC_HI(x)
#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK
#define CAN_PL1_HI_Data_byte_7(x)
void FLEXCAN_HAL_ConfigPN(CAN_Type *base, const flexcan_pn_config_t *pnConfig)
Configures the Pretended Networking mode.
#define CAN_CTRL2_ISOCANFDEN(x)
void FLEXCAN_HAL_SetTimeSegments(CAN_Type *base, const flexcan_time_segment_t *timeSeg)
Sets the FlexCAN time segments for setting up bit rate.
void FLEXCAN_HAL_GetTimeSegments(const CAN_Type *base, flexcan_time_segment_t *timeSeg)
Gets the FlexCAN time segments to calculate the bit rate.
void FLEXCAN_HAL_SetTDCOffset(CAN_Type *base, bool enable, uint8_t offset)
Enables/Disables the Transceiver Delay Compensation feature and sets the Transceiver Delay Compensati...
void FLEXCAN_HAL_DisableRxFifo(CAN_Type *base)
Disables the Rx FIFO.
#define CAN_MCR_SOFTRST_SHIFT
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT
static volatile uint32_t * FLEXCAN_HAL_GetMsgBuffRegion(CAN_Type *base, uint32_t msgBuffIdx)
void FLEXCAN_HAL_ExitFreezeMode(CAN_Type *base)
Un freezes the FlexCAN module.
#define CAN_CTRL1_PN_FCS_MASK
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1
void FLEXCAN_HAL_Enable(CAN_Type *base)
Enables FlexCAN controller.
__IO uint32_t PL2_PLMASK_LO
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK
#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK
#define CAN_CTRL2_PN_MATCHTO(x)
#define CAN_DLC_VALUE_48_BYTES
#define FEATURE_CAN0_MAX_MB_NUM
#define CAN_FDCBT_FRJW(x)
#define CAN_DLC_VALUE_12_BYTES
#define CAN_CTRL2_PN_MATCHTO_MASK
FlexCAN bus error counters Implements : flexcan_buserr_counter_t_Class.
#define CAN_CTRL1_LPB_MASK
#define CAN_CTRL1_PN_IDFS(x)
#define CAN_CTRL1_PSEG2_MASK
status_t FLEXCAN_HAL_EnableRxFifo(CAN_Type *base, uint32_t numOfFilters)
Enables the Rx FIFO.
#define CAN_CBT_EPRESDIV_MASK
#define CAN_FLT_ID2_IDMASK_RTR_MSK(x)
__IO uint32_t RAMn[CAN_RAMn_COUNT]
bool FLEXCAN_HAL_IsFDEnabled(const CAN_Type *base)
Checks if the Flexible Data rate feature is enabled.
#define CAN_PL1_LO_Data_byte_3(x)
__IO uint32_t FLT_ID2_IDMASK
#define CAN_FLT_ID1_FLT_RTR(x)
#define CAN_CTRL1_PSEG1(x)
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2
uint8_t FLEXCAN_HAL_GetPayloadSize(const CAN_Type *base)
Gets the payload size of the MBs.
#define CAN_MCR_IDAM_MASK
#define CAN_MCR_WRNEN_MASK
#define CAN_FDCTRL_FDRATE_MASK
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1
status_t FLEXCAN_HAL_GetMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, flexcan_msgbuff_t *msgBuff)
Gets the FlexCAN message buffer fields.
status_t FLEXCAN_HAL_SetMsgBuffIntCmd(CAN_Type *base, uint32_t msgBuffIdx, bool enable)
Enables/Disables the FlexCAN Message Buffer interrupt.
#define FlexcanSwapBytesInWordIndex(index)
void FLEXCAN_HAL_Disable(CAN_Type *base)
Disables FlexCAN controller.
#define CAN_MCR_IDAM_SHIFT
static uint32_t RxFifoOcuppiedLastMsgBuff(uint32_t x)
#define CAN_CTRL1_PN_IDFS_MASK
#define CAN_MCR_MDIS_SHIFT
#define CAN_FLT_DLC_FLT_DLC_HI_MASK
#define CAN_CBT_ERJW_MASK
flexcan_pn_filter_combination_t filterComb
#define CAN_DLC_VALUE_32_BYTES
status_t FLEXCAN_HAL_LockRxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx)
Locks the FlexCAN Rx message buffer.
#define CAN_FDCTRL_TDCEN_MASK
#define CAN_MCR_LPMACK_SHIFT
#define CAN_CTRL1_CLKSRC_MASK
#define CAN_CBT_EPRESDIV(x)
#define CAN_RX14MASK_RX14M_MASK
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT
uint8_t FLEXCAN_HAL_GetMsgBuffIntStatusFlag(const CAN_Type *base, uint32_t msgBuffIdx)
Gets the individual FlexCAN MB interrupt flag.
void FLEXCAN_HAL_SetRxFifoGlobalStdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN RX FIFO global standard mask.
static uint32_t FLEXCAN_HAL_MaxMbRAMSize(const CAN_Type *base)
#define CAN_FDCBT_FPROPSEG(x)
#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK
void FLEXCAN_HAL_EnterFreezeMode(CAN_Type *base)
Freezes the FlexCAN module.
#define CAN_MCR_FDEN_SHIFT
#define CAN_PL2_PLMASK_HI_Data_byte_4(x)
#define CAN_ECR_TXERRCNT_MASK
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2
#define CAN_FLT_ID1_FLT_IDE(x)
#define CAN_CTRL2_ISOCANFDEN_MASK
#define CAN_CTRL2_RFFN_MASK
#define CAN_FDCBT_FPSEG1(x)
#define CAN_PL1_LO_Data_byte_0(x)
void FLEXCAN_HAL_SetSelfReception(CAN_Type *base, bool enable)
Enables/Disables the Self Reception feature.
#define CAN_CTRL1_PSEG2_SHIFT
#define CAN_FLT_ID2_IDMASK_IDE_MSK(x)
#define CAN_CTRL1_PN_PLFS(x)
#define CAN_FDCBT_FPRESDIV(x)
#define CAN_CTRL1_PN_WTOF_MSK_MASK
#define REV_BYTES_32(a, b)
Reverse byte order in a word.
#define CAN_RX15MASK_RX15M_MASK
#define CAN_FLT_ID1_FLT_IDE_MASK
#define CAN_MCR_RFEN_MASK
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT
#define CAN_FDCBT_FRJW_MASK
void FLEXCAN_HAL_SetErrIntCmd(CAN_Type *base, flexcan_int_type_t errType, bool enable)
Enables error interrupt of the FlexCAN module.
flexcan_int_type_t
FlexCAN error interrupt types Implements : flexcan_int_type_t_Class.
#define CAN_CBT_EPSEG1(x)
#define CAN_DLC_VALUE_24_BYTES
#define CAN_PL2_PLMASK_LO_Data_byte_3(x)
flexcan_pn_id_filter_t idFilter2
#define CAN_CTRL1_PSEG1_SHIFT
#define CAN_ECR_RXERRCNT_SHIFT
#define CAN_FDCTRL_FDRATE(x)
void FLEXCAN_HAL_SetRxMsgBuff15StdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN Rx Message Buffer BUF15 standard mask.
#define CAN_MCR_SOFTRST(x)
#define FEATURE_CAN1_MAX_MB_NUM
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK
flexcan_pn_payload_filter_t payloadFilter
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT
#define CAN_PL2_PLMASK_HI_Data_byte_5(x)
#define CAN_CTRL1_PN_PLFS_MASK
void FLEXCAN_HAL_SetOperationMode(CAN_Type *base, flexcan_operation_modes_t mode)
Set operation mode.
void FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN Rx Message Buffer global standard mask.
#define CAN_CTRL1_PN_FCS(x)
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT
#define CAN_PL2_PLMASK_HI_Data_byte_6(x)
FlexCAN timing related structures Implements : flexcan_time_segment_t_Class.
#define CAN_CBT_EPSEG2_MASK
void FLEXCAN_HAL_SetRxMaskType(CAN_Type *base, flexcan_rx_mask_type_t type)
Sets the Rx masking type.
#define CAN_FLT_ID1_FLT_ID1_MASK
static void FLEXCAN_HAL_ClearRAM(CAN_Type *base)
#define CAN_MCR_SUPV_MASK
#define CAN_CTRL2_RFFN_SHIFT
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
#define CAN_FDCTRL_MBDSR0_SHIFT
flexcan_operation_modes_t
FlexCAN operation modes Implements : flexcan_operation_modes_t_Class.
#define CAN_CBT_EPROPSEG(x)
void FLEXCAN_HAL_SetRxFifoFilter(CAN_Type *base, flexcan_rx_fifo_id_element_format_t idFormat, const flexcan_id_table_t *idFilterTable)
Sets the FlexCAN Rx FIFO fields.
#define CAN_MCR_MAXMB_SHIFT
#define CAN_CTRL1_PN_NMATCH_MASK
#define CAN_CBT_EPSEG2(x)
__IO uint32_t RXIMR[CAN_RXIMR_COUNT]
static bool FLEXCAN_HAL_IsRxFifoEnabled(const CAN_Type *base)
Checks if Rx FIFO is enabled.
void FLEXCAN_HAL_SetRxFifoFilterNum(CAN_Type *base, uint32_t number)
Sets the number of the Rx FIFO filters.
flexcan_rx_fifo_id_element_format_t
ID formats for RxFIFO Implements : flexcan_rx_fifo_id_element_format_t_Class.
#define CAN_FDCBT_FPROPSEG_MASK
void FLEXCAN_HAL_ReadRxFifo(const CAN_Type *base, flexcan_msgbuff_t *rxFifo)
Gets the FlexCAN Rx FIFO data.
#define CAN_PL1_HI_Data_byte_5(x)
#define RxFifoFilterTableOffset
status_t FLEXCAN_HAL_SetRxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, const flexcan_msgbuff_code_status_t *cs, uint32_t msgId)
Sets the FlexCAN message buffer fields for receiving.
#define CAN_CTRL1_RJW_SHIFT
static uint8_t FLEXCAN_HAL_ComputePayloadSize(uint8_t dlcValue)
#define CAN_ECR_RXERRCNT_MASK
FlexCAN message buffer structure Implements : flexcan_msgbuff_t_Class.
#define CAN_CTRL1_RJW_MASK
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK
flexcan_msgbuff_id_type_t msgIdType
#define CAN_CTRL1_PN_NMATCH(x)
#define CAN_CTRL1_PROPSEG(x)
#define FLEXCAN_ARBITRATION_FIELD_SIZE
#define FLEXCAN_8_BYTE_PAYLOAD_MB_SIZE
#define CAN_ECR_TXERRCNT_SHIFT
#define CAN_FDCTRL_MBDSR0_MASK
#define FlexCanRxFifoAcceptRemoteFrame
FlexCAN RX FIFO ID filter table structure Implements : flexcan_id_table_t_Class.
#define CAN_CBT_EPSEG1_MASK
status_t FLEXCAN_HAL_SetRxIndividualStdMask(CAN_Type *base, uint32_t msgBuffIdx, uint32_t stdMask)
Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO...
#define CAN_PL2_PLMASK_LO_Data_byte_2(x)
Pretended Networking configuration structure Implements : flexcan_pn_config_t_Class.
#define CAN_CTRL1_PROPSEG_MASK
void FLEXCAN_HAL_Init(CAN_Type *base)
Initializes the FlexCAN controller.
status_t FLEXCAN_HAL_SetTxMsgBuff(CAN_Type *base, uint32_t msgBuffIdx, const flexcan_msgbuff_code_status_t *cs, uint32_t msgId, const uint8_t *msgData)
Sets the FlexCAN message buffer fields for transmitting.
#define CAN_CTRL1_PRESDIV_MASK
#define CAN_DLC_VALUE_16_BYTES
#define CAN_MCR_HALT_MASK
#define CAN_FDCBT_FPSEG2_MASK
#define CAN_PL1_HI_Data_byte_4(x)
#define CAN_PL2_PLMASK_LO_Data_byte_1(x)
status_t FLEXCAN_HAL_SetMaxMsgBuffNum(CAN_Type *base, uint32_t maxMsgBuffNum)
Sets the maximum number of Message Buffers.
#define CAN_MCR_SOFTRST_MASK
#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x)
#define RxFifoFilterElementNum(x)
#define CAN_CTRL1_PN_WUMF_MSK_MASK
#define CAN_FLT_ID1_FLT_ID1(x)
void FLEXCAN_HAL_GetWMB(const CAN_Type *base, uint8_t wmbIndex, flexcan_msgbuff_t *wmb)
Extracts one of the frames which triggered the wake up event.
#define CAN_MCR_LPMACK_MASK
#define CAN_CTRL1_CLKSRC(x)
struct CAN_Type::@0 WMB[CAN_WMB_COUNT]
void FLEXCAN_HAL_ExitOperationMode(CAN_Type *base, flexcan_operation_modes_t mode)
Exit operation mode.
void FLEXCAN_HAL_SelectClock(CAN_Type *base, flexcan_clk_source_t clk)
Selects the clock source for FlexCAN.
static uint8_t FLEXCAN_HAL_ComputeDLCValue(uint8_t payloadSize)
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4
flexcan_clk_source_t
FlexCAN clock source Implements : flexcan_clk_source_t_Class.
void FLEXCAN_HAL_SetRxMsgBuff14ExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX Message Buffer BUF14 extended mask.
#define CAN_FLT_ID1_FLT_RTR_MASK
#define CAN_CBT_EPROPSEG_MASK
void FLEXCAN_HAL_SetRxMsgBuff15ExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN RX MB BUF15 extended mask.
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3
#define CAN_CS_CODE_SHIFT
#define FlexCanRxFifoAcceptExtFrame
#define CAN_MCR_IRMQ_MASK
#define CAN_FDCTRL_TDCOFF(x)
#define CAN_FDCBT_FPSEG1_MASK
void FLEXCAN_HAL_SetPayloadSize(CAN_Type *base, flexcan_fd_payload_size_t payloadSize)
Sets the payload size of the MBs.
#define CAN_CTRL1_PN_WTOF_MSK(x)
void FLEXCAN_HAL_SetStuffBitCount(CAN_Type *base, bool enable)
Enables/Disables the Stuff Bit Count for CAN FD frames.
flexcan_fd_payload_size_t
FlexCAN payload sizes Implements : flexcan_fd_payload_size_t_Class.
#define CAN_FDCBT_FPSEG2(x)
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1
#define CAN_RXIMR_MI_MASK
#define CAN_MCR_FRZACK_SHIFT
#define CAN_PL2_PLMASK_LO_Data_byte_0(x)
flexcan_rx_mask_type_t
FlexCAN RX mask type. Implements : flexcan_rx_mask_type_t_Class.
#define CAN_MCR_SRXDIS_MASK
#define CAN_MCR_RFEN_SHIFT
#define CAN_CTRL1_LOM_MASK
void FLEXCAN_HAL_GetErrCounter(const CAN_Type *base, flexcan_buserr_counter_t *errCount)
Gets the transmit error counter and receives the error counter.
#define CAN_PL1_LO_Data_byte_2(x)
#define CAN_CTRL1_PSEG1_MASK
void FLEXCAN_HAL_SetRxFifoGlobalExtMask(CAN_Type *base, uint32_t extMask)
Sets the FlexCAN Rx FIFO global extended mask.
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK
#define CAN_FDCTRL_TDCOFF_MASK
#define CAN_CTRL1_PRESDIV(x)
#define FEATURE_CAN2_MAX_MB_NUM
#define CAN_MCR_FDEN_MASK
#define CAN_CTRL1_PROPSEG_SHIFT
#define CAN_FDCBT_FPRESDIV_MASK
flexcan_pn_filter_selection_t idFilterType
flexcan_pn_id_filter_t idFilter1
#define CAN_MCR_MDIS_MASK
#define CAN_PL1_HI_Data_byte_6(x)
#define CAN_DLC_VALUE_64_BYTES
#define CAN_CTRL1_PRESDIV_SHIFT
FlexCAN Message Buffer code and status for transmit and receive Implements : flexcan_msgbuff_code_sta...
#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT
__IO uint32_t PL2_PLMASK_HI
#define CAN_RXMGMASK_MG_MASK
#define CAN_CTRL1_PSEG2(x)
#define CAN_MCR_MAXMB_MASK
#define CAN_MCR_FRZACK_MASK
#define CAN_RXFGMASK_FGM_MASK
#define CAN_FLT_DLC_FLT_DLC_LO(x)
flexcan_pn_filter_selection_t payloadFilterType
#define CAN_CTRL1_PN_WUMF_MSK(x)
status_t FLEXCAN_HAL_SetRxIndividualExtMask(CAN_Type *base, uint32_t msgBuffIdx, uint32_t extMask)
Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx Message Buffers and the Rx FI...
void FLEXCAN_HAL_SetFDEnabled(CAN_Type *base, bool enable)
Enables/Disables Flexible Data rate (if supported).
void FLEXCAN_HAL_SetRxMsgBuff14StdMask(CAN_Type *base, uint32_t stdMask)
Sets the FlexCAN RX Message Buffer BUF14 standard mask.