S32 SDK
edma_driver.c
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1 /*
2  * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
60 #include "edma_driver.h"
61 #include "clock_manager.h"
62 #include "interrupt_manager.h"
63 
64 /*******************************************************************************
65  * Variables
66  ******************************************************************************/
68 static edma_state_t *s_edma = NULL;
69 
70 /*******************************************************************************
71  * PROTOTYPES
72  ******************************************************************************/
73 static status_t EDMA_DRV_RequestChannel(uint8_t requestedChannel, dma_request_source_t source,
74  edma_chn_state_t *chn);
75 static void EDMA_DRV_ClearIntStatus(uint8_t channel);
77 #ifdef DEV_ERROR_DETECT
78 static bool EDMA_DRV_ValidTransferSize(edma_transfer_size_t size);
79 #endif
80 
81 /*******************************************************************************
82  * Code
83  ******************************************************************************/
84 /*FUNCTION**********************************************************************
85  *
86  * Function Name : EDMA_DRV_Init
87  * Description : Initializes the eDMA module.
88  *
89  * Implements : EDMA_DRV_Init_Activity
90  *END**************************************************************************/
91 status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t *userConfig,
92  edma_chn_state_t * const chnStateArray[],
93  const edma_channel_config_t * const chnConfigArray[],
94  uint8_t chnCount)
95 {
96  uint32_t i;
97  DMA_Type * edmaRegBase;
98  IRQn_Type irqNumber;
99  status_t edmaStatus = STATUS_SUCCESS;
100  status_t chnInitStatus;
101 #ifdef DEV_ERROR_DETECT
102  uint32_t freq;
103  status_t clockManagerStatus;
104 #endif
105 
106  /* Check the state and configuration structure pointers are valid */
107  DEV_ASSERT((edmaState != NULL) && (userConfig != NULL));
108 
109  /* Check the module has not already been initialized */
110  DEV_ASSERT(s_edma == NULL);
111 
112 #ifdef DEV_ERROR_DETECT
113  /* Check that eDMA and DMAMUX modules are clock gated on */
114  clockManagerStatus = CLOCK_SYS_GetFreq(g_edmaClockNames[0U], &freq);
115  DEV_ASSERT(clockManagerStatus == STATUS_SUCCESS);
116 
117  for (i = 0U; i < DMAMUX_INSTANCE_COUNT; i++)
118  {
119  clockManagerStatus = CLOCK_SYS_GetFreq(g_dmamuxClockNames[i], &freq);
120  DEV_ASSERT(clockManagerStatus == STATUS_SUCCESS);
121  }
122 #endif
123 
124  /* Save the runtime state structure for the driver */
125  s_edma = edmaState;
126 
127  /* Clear the state structure. */
128  volatile uint8_t *clearStructPtr = (volatile uint8_t *)s_edma;
129  size_t clearSize = sizeof(edma_state_t);
130  while (clearSize > 0U)
131  {
132  *clearStructPtr = 0;
133  clearStructPtr ++;
134  clearSize --;
135  }
136 
137  edmaRegBase = g_edmaBase[0U];
138 
139  /* Init eDMA module on hardware level. */
140  EDMA_HAL_Init(edmaRegBase);
141 
142  /* Set arbitration mode */
143  EDMA_HAL_SetChannelArbitrationMode(edmaRegBase, userConfig->chnArbitration);
144 #if (FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
145  EDMA_HAL_SetGroupArbitrationMode(edmaRegBase, userConfig->groupArbitration);
146  EDMA_HAL_SetGroupPriority(edmaRegBase, userConfig->groupPriority);
147 #endif
148 
149  /* Set 'Halt on error' configuration */
150  EDMA_HAL_SetHaltOnErrorCmd(edmaRegBase, !userConfig->notHaltOnError);
151 
152 #if defined FEATURE_EDMA_HAS_ERROR_IRQ
153  /* Enable the error interrupts for eDMA module. */
154  for (i = 0U; i < FEATURE_ERROR_INTERRUPT_LINES; i++)
155  {
156  /* Enable channel interrupt ID. */
157  irqNumber = g_edmaErrIrqId[i];
158  INT_SYS_EnableIRQ(irqNumber);
159  }
160 #endif
161 
162  /* Register all edma channel interrupt handler into vector table. */
163  for (i = 0U; i < FEATURE_CHANNEL_INTERRUPT_LINES; i++)
164  {
165  /* Enable channel interrupt ID. */
166  irqNumber = g_edmaIrqId[i];
167  INT_SYS_EnableIRQ(irqNumber);
168  }
169 
170  /* Initialize all DMAMUX instances */
171  for (i = 0U; i < DMAMUX_INSTANCE_COUNT; i++)
172  {
174  }
175 
176  /* Initialize the channels based on configuration list */
177  if ((chnStateArray != NULL) && (chnConfigArray != NULL))
178  {
179  for (i = 0U; i < chnCount; i++)
180  {
181  chnInitStatus = EDMA_DRV_ChannelInit(chnStateArray[i], chnConfigArray[i]);
182  if (chnInitStatus != STATUS_SUCCESS)
183  {
184  edmaStatus = chnInitStatus;
185  }
186  }
187  }
188 
189  return edmaStatus;
190 }
191 
192 /*FUNCTION**********************************************************************
193  *
194  * Function Name : EDMA_DRV_Deinit
195  * Description : Deinitialize EDMA.
196  *
197  * Implements : EDMA_DRV_Deinit_Activity
198  *END**************************************************************************/
200 {
201  uint32_t i;
202  IRQn_Type irqNumber;
203  const edma_chn_state_t *chn;
204 
205  /* Release all edma channel. */
206 #if defined FEATURE_EDMA_HAS_ERROR_IRQ
207  /* Disable the error interrupts for eDMA module. */
208  for (i = 0U; i < FEATURE_ERROR_INTERRUPT_LINES; i++)
209  {
210  /* Enable channel interrupt ID. */
211  irqNumber = g_edmaErrIrqId[i];
212  INT_SYS_DisableIRQ(irqNumber);
213  }
214 #endif
215  if (s_edma != NULL)
216  {
217  for (i = 0U; i < FEATURE_EDMA_MODULE_CHANNELS; i++)
218  {
219  /* Release all channels. */
220  chn = s_edma->chn[i];
221  if (chn != NULL)
222  {
223  (void) EDMA_DRV_ReleaseChannel(chn->channel);
224  }
225  }
226  for (i = 0U; i < FEATURE_CHANNEL_INTERRUPT_LINES; i++)
227  {
228  /* Disable channel interrupts. */
229  irqNumber = g_edmaIrqId[i];
230  INT_SYS_DisableIRQ(irqNumber);
231  }
232 
233  s_edma = NULL;
234  }
235 
236  return STATUS_SUCCESS;
237 }
238 
239 /*FUNCTION**********************************************************************
240  *
241  * Function Name : EDMA_DRV_ChannelInit
242  * Description : Initialize EDMA channel.
243  *
244  * Implements : EDMA_DRV_ChannelInit_Activity
245  *END**************************************************************************/
246 status_t EDMA_DRV_ChannelInit(edma_chn_state_t *edmaChannelState, const edma_channel_config_t *edmaChannelConfig)
247 {
248  DMA_Type * edmaRegBase = g_edmaBase[0U];
249  status_t status;
250 
251  /* Check the state and configuration structure pointers are valid */
252  DEV_ASSERT((edmaChannelState != NULL) && (edmaChannelConfig != NULL));
253  /* Check if the module is initialized */
254  DEV_ASSERT(s_edma != NULL);
255  /* Check if the channel defined by user in the channel configuration structure is valid */
256  DEV_ASSERT(edmaChannelConfig->channel < FEATURE_EDMA_MODULE_CHANNELS);
257 
258  /* Request the channel */
259  status = EDMA_DRV_RequestChannel(edmaChannelConfig->channel, edmaChannelConfig->source, edmaChannelState);
260 
261  if (status == STATUS_SUCCESS)
262  {
263  /* Set the channel priority, as defined in the configuration, only if fixed arbitration mode is selected */
265  (edmaChannelConfig->priority != EDMA_CHN_DEFAULT_PRIORITY))
266  {
267  EDMA_HAL_SetChannelPriority(edmaRegBase, edmaChannelConfig->channel, edmaChannelConfig->priority);
268  }
269 
270  /* Install the user callback */
271  status = EDMA_DRV_InstallCallback(edmaChannelConfig->channel, edmaChannelConfig->callback,
272  edmaChannelConfig->callbackParam);
273  }
274 
275  return status;
276 }
277 
278 /*FUNCTION**********************************************************************
279  *
280  * Function Name : EDMA_DRV_InstallCallback
281  * Description : Register callback function and parameter.
282  *
283  * Implements : EDMA_DRV_InstallCallback_Activity
284  *END**************************************************************************/
285 status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
286 {
287  /* Check the channel number is valid */
289 
290  edma_chn_state_t * chnState = s_edma->chn[channel];
291  /* Check the channel is allocated */
292  DEV_ASSERT(chnState != NULL);
293 
294  chnState->callback = callback;
295  chnState->parameter = parameter;
296 
297  return STATUS_SUCCESS;
298 }
299 
300 /*FUNCTION**********************************************************************
301  *
302  * Function Name : EDMA_DRV_RequestChannel
303  * Description : Request an eDMA channel.
304  *
305  *END**************************************************************************/
306 static status_t EDMA_DRV_RequestChannel(uint8_t requestedChannel, dma_request_source_t source,
307  edma_chn_state_t *chn)
308 {
309  /* Retrieve the DMAMUX instance serving this channel */
310  uint8_t dmamuxInstance = (uint8_t)FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(source);
311  /* Retrieve the appropriate request source index for the corresponding DMAMUX instance */
312  uint8_t sourceDmamuxChannel = (uint8_t)FEATURE_DMAMUX_REQ_SRC_TO_CHN(source);
313  /* Retrieve the appropriate DMAMUX channel for the selected request source */
314  uint32_t dmamuxChannel = FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(requestedChannel);
315  /* Base addresses for eDMA and DMAMUX */
316  DMA_Type * edmaRegBase = g_edmaBase[0U];
317  DMAMUX_Type * dmamuxRegBase = g_dmamuxBase[dmamuxInstance];
318 
319  /* Check the channel has not already been allocated */
320  DEV_ASSERT(s_edma->chn[requestedChannel] == NULL);
321 
322  /* Channel allocation */
323  s_edma->chn[requestedChannel] = chn;
324 
325  /* Reset the channel state structure to default value. */
326  uint8_t *clearStructPtr = (uint8_t *)chn;
327  size_t clearSize = sizeof(edma_chn_state_t);
328  while (clearSize > 0U)
329  {
330  *clearStructPtr = 0;
331  clearStructPtr ++;
332  clearSize --;
333  }
334 
335  /* Init the channel state structure to the allocated channel number. */
336  chn->channel = requestedChannel;
337 
338  /* Enable error interrupt for this channel */
339  EDMA_HAL_SetErrorIntCmd(edmaRegBase, requestedChannel, true);
340 
341  /* Configure the DMAMUX for edma channel */
342  DMAMUX_HAL_SetChannelCmd(dmamuxRegBase, dmamuxChannel, false);
343  DMAMUX_HAL_SetChannelSource(dmamuxRegBase, dmamuxChannel, sourceDmamuxChannel);
344  DMAMUX_HAL_SetChannelCmd(dmamuxRegBase, dmamuxChannel, true);
345 
346  /* Clear the TCD registers for this channel */
347  EDMA_HAL_TCDClearReg(edmaRegBase, requestedChannel);
348 
349  return STATUS_SUCCESS;
350 }
351 
352 /*FUNCTION**********************************************************************
353  *
354  * Function Name : EDMA_DRV_ReleaseChannel
355  * Description : Free eDMA channel's hardware and software resource.
356  *
357  * Implements : EDMA_DRV_ReleaseChannel_Activity
358  *END**************************************************************************/
360 {
361  /* Check the channel number is valid */
363 
364  /* Check the DMA module is initialized */
365  DEV_ASSERT(s_edma != NULL);
366 
367  edma_chn_state_t * chnState = s_edma->chn[channel];
368 
369  /* Check the channel is initialized */
370  DEV_ASSERT(chnState != NULL);
371 
372  DMA_Type * edmaRegBase = g_edmaBase[0U];
373 
374  /* Stop edma channel. */
375  EDMA_HAL_SetDmaRequestCmd(edmaRegBase, channel, false);
376 
377  /* Reset the channel state structure to default value. */
378  uint8_t *clearStructPtr = (uint8_t *)chnState;
379  size_t clearSize = sizeof(edma_chn_state_t);
380  while (clearSize > 0U)
381  {
382  *clearStructPtr = 0;
383  clearStructPtr ++;
384  clearSize --;
385  }
386 
387  s_edma->chn[channel] = NULL;
388 
389  return STATUS_SUCCESS;
390 }
391 
392 /*FUNCTION**********************************************************************
393  *
394  * Function Name : EDMA_DRV_ClearIntStatus
395  * Description : Clear done and interrupt status.
396  *
397  *END**************************************************************************/
398 static void EDMA_DRV_ClearIntStatus(uint8_t channel)
399 {
400  DMA_Type * edmaRegBase = g_edmaBase[0U];
401  EDMA_HAL_ClearDoneStatusFlag(edmaRegBase, channel);
402  EDMA_HAL_ClearIntStatusFlag(edmaRegBase, channel);
403 }
404 
405 /*FUNCTION**********************************************************************
406  *
407  * Function Name : EDMA_DRV_ClearSoftwareTCD
408  * Description : Clear the software tcd structure.
409  *
410  *END**************************************************************************/
412 {
413  uint8_t *byteAccess = (uint8_t *)stcd;
414  size_t clearSize = sizeof(edma_software_tcd_t);
415  while (clearSize > 0U)
416  {
417  *byteAccess = 0;
418  byteAccess ++;
419  clearSize --;
420  }
421 }
422 
423 /*FUNCTION**********************************************************************
424  *
425  * Function Name : EDMA_DRV_IRQHandler
426  * Description : EDMA IRQ handler.
427  *END**************************************************************************/
428 void EDMA_DRV_IRQHandler(uint8_t channel)
429 {
430  const edma_chn_state_t *chn = s_edma->chn[channel];
431 
432  EDMA_DRV_ClearIntStatus(channel);
433 
434  if (chn != NULL)
435  {
436  if (chn->callback != NULL)
437  {
438  chn->callback(chn->parameter, chn->status);
439  }
440  }
441 }
442 
443 /*FUNCTION**********************************************************************
444  *
445  * Function Name : EDMA_DRV_ErrorIRQHandler
446  * Description : EDMA error IRQ handler
447  *END**************************************************************************/
449 {
450  uint8_t channel = 0U;
451  uint32_t error;
452  DMA_Type * edmaRegBase = g_edmaBase[0U];
453  edma_chn_state_t *chn;
454 
455  error = EDMA_HAL_GetErrorIntStatusFlag(edmaRegBase);
456 
457  while ((error != 0UL) && (channel < (uint8_t) FEATURE_EDMA_MODULE_CHANNELS))
458  {
459  if ((error & EDMA_ERR_LSB_MASK) != 0UL)
460  {
461  EDMA_HAL_SetDmaRequestCmd(edmaRegBase, channel, false);
462  chn = s_edma->chn[channel];
463  if (chn != NULL)
464  {
465  EDMA_DRV_ClearIntStatus(channel);
466  EDMA_HAL_ClearErrorIntStatusFlag(edmaRegBase, channel);
467  chn->status = EDMA_CHN_ERROR;
468  if (chn->callback != NULL)
469  {
470  chn->callback(chn->parameter, chn->status);
471  }
472  }
473  }
474  error = error >> 1U;
475  channel++;
476  }
477  EDMA_HAL_SetHaltCmd(edmaRegBase, false);
478 }
479 
480 /*FUNCTION**********************************************************************
481  *
482  * Function Name : EDMA_DRV_ConfigSingleBlockTransfer
483  * Description : Configures a DMA single block transfer.
484  *
485  * Implements : EDMA_DRV_ConfigSingleBlockTransfer_Activity
486  *END**************************************************************************/
488  uint32_t srcAddr, uint32_t destAddr,
489  edma_transfer_size_t transferSize, uint32_t dataBufferSize)
490 {
491  /* Check the channel number is valid */
493 
494  /* Check the eDMA module is initialized */
495  DEV_ASSERT(s_edma != NULL);
496 
497  /* Check the channel is initialized */
498  DEV_ASSERT(s_edma->chn[channel] != NULL);
499 
500 #ifdef DEV_ERROR_DETECT
501  /* Check if the value passed for 'transferSize' is valid */
502  DEV_ASSERT(EDMA_DRV_ValidTransferSize(transferSize));
503 #endif
504 
505  DMA_Type * edmaRegBase = g_edmaBase[0U];
506  uint8_t transferOffset;
507  status_t status = STATUS_SUCCESS;
508 
509  /* Compute the transfer offset, based on transfer size.
510  * The number of bytes transferred in each source read/destination write
511  * is obtained with the following formula:
512  * source_read_size = 2^SSIZE
513  * destination_write_size = 2^DSIZE
514  */
515  transferOffset = (uint8_t) (1U << ((uint8_t)transferSize));
516 
517  /* The number of bytes to be transferred (buffer size) must
518  * be a multiple of the source read/destination write size
519  */
520  if ((dataBufferSize % transferOffset) != 0U)
521  {
522  status = STATUS_ERROR;
523  }
524 
525  if (status == STATUS_SUCCESS)
526  {
527  /* Clear transfer control descriptor for the current channel */
528  EDMA_HAL_TCDClearReg(edmaRegBase, channel);
529 
530  /* Configure source and destination addresses */
531  EDMA_HAL_TCDSetSrcAddr(edmaRegBase, channel, srcAddr);
532  EDMA_HAL_TCDSetDestAddr(edmaRegBase, channel, destAddr);
533 
534  /* Set transfer size (1B/2B/4B/16B/32B) */
535  EDMA_HAL_TCDSetAttribute(edmaRegBase, channel, EDMA_MODULO_OFF, EDMA_MODULO_OFF, transferSize, transferSize);
536 
537  /* Configure source/destination offset. */
538  switch (type)
539  {
541  EDMA_HAL_TCDSetSrcOffset(edmaRegBase, channel, 0);
542  EDMA_HAL_TCDSetDestOffset(edmaRegBase, channel, (int8_t) transferOffset);
543  break;
545  EDMA_HAL_TCDSetSrcOffset(edmaRegBase, channel, (int8_t) transferOffset);
546  EDMA_HAL_TCDSetDestOffset(edmaRegBase, channel, 0);
547  break;
549  EDMA_HAL_TCDSetSrcOffset(edmaRegBase, channel, (int8_t) transferOffset);
550  EDMA_HAL_TCDSetDestOffset(edmaRegBase, channel, (int8_t) transferOffset);
551  break;
552  default:
553  /* This should never be reached - all the possible values have been handled. */
554  break;
555  }
556 
557  /* Set the total number of bytes to be transfered */
558  EDMA_HAL_TCDSetNbytes(edmaRegBase, channel, dataBufferSize);
559 
560  /* Set major iteration count to 1 (single block mode) */
561  EDMA_HAL_TCDSetMajorCount(edmaRegBase, channel, 1U);
562 
563  /* Enable interrupt when the transfer completes */
564  EDMA_HAL_TCDSetIntCmd(edmaRegBase, channel, true);
565  }
566 
567  return status;
568 }
569 
570 /*FUNCTION**********************************************************************
571  *
572  * Function Name : EDMA_DRV_ConfigLoopTransfer
573  * Description : Configures the DMA transfer in a loop.
574  *
575  * Implements : EDMA_DRV_ConfigLoopTransfer_Activity
576  *END**************************************************************************/
577 status_t EDMA_DRV_ConfigLoopTransfer(uint8_t channel, const edma_transfer_config_t *transferConfig)
578 {
579  /* Check the channel number is valid */
581 
582  /* Check the eDMA module is initialized */
583  DEV_ASSERT(s_edma != NULL);
584 
585  /* Check the channel is initialized */
586  DEV_ASSERT(s_edma->chn[channel] != NULL);
587 
588  /* Check the transfer configuration structure is valid */
589  DEV_ASSERT(transferConfig != NULL);
590 
591  /* Check the minor/major loop properties are defined */
592  DEV_ASSERT(transferConfig->loopTransferConfig != NULL);
593 
594  /* Enable minor loop mapping */
595  DMA_Type * edmaRegBase = g_edmaBase[0U];
596  EDMA_HAL_SetMinorLoopMappingCmd(edmaRegBase, true);
597 
598  /* Write the configuration in the transfer control descriptor registers */
599  EDMA_DRV_PushConfigToReg(channel, transferConfig);
600 
601  /* Enable interrupt when major loop count completes */
602  EDMA_HAL_TCDSetIntCmd(edmaRegBase, channel, true);
603 
604  return STATUS_SUCCESS;
605 }
606 
607 /*FUNCTION**********************************************************************
608  *
609  * Function Name : EDMA_DRV_ConfigScatterGatherTransfer
610  * Description : Configure eDMA for scatter/gather operation
611  *
612  * Implements : EDMA_DRV_ConfigScatterGatherTransfer_Activity
613  *END**************************************************************************/
615  edma_transfer_size_t transferSize, uint32_t bytesOnEachRequest,
616  const edma_scatter_gather_list_t *srcList,
617  const edma_scatter_gather_list_t *destList, uint8_t tcdCount)
618 {
619  /* Check the channel number is valid */
621 
622  /* Check the eDMA module is initialized */
623  DEV_ASSERT(s_edma != NULL);
624 
625  /* Check the channel is initialized */
626  DEV_ASSERT(s_edma->chn[channel] != NULL);
627 
628  /* Check the input arrays for scatter/gather operation are valid */
629  DEV_ASSERT((stcd != NULL) && (srcList != NULL) && (destList != NULL));
630 
631 #ifdef DEV_ERROR_DETECT
632  /* Check if the value passed for 'transferSize' is valid */
633  DEV_ASSERT(EDMA_DRV_ValidTransferSize(transferSize));
634 #endif
635 
636  uint8_t i;
637  uint16_t transferOffset;
638  uint32_t stcdAlignedAddr = STCD_ADDR(stcd);
639  edma_software_tcd_t *stcdAddr = (edma_software_tcd_t *)stcdAlignedAddr;
640  edma_loop_transfer_config_t loopConfig;
641  edma_transfer_config_t config;
642  status_t status = STATUS_SUCCESS;
643 
644  /* Compute the transfer offset, based on transfer size.
645  * The number of bytes transferred in each source read/destination write
646  * is obtained with the following formula:
647  * source_read_size = 2^SSIZE
648  * destination_write_size = 2^DSIZE
649  */
650  transferOffset = (uint16_t) (1UL << ((uint16_t)transferSize));
651 
652  /* The number of bytes to be transferred on each request must
653  * be a multiple of the source read/destination write size
654  */
655  if ((bytesOnEachRequest % transferOffset) != 0U)
656  {
657  status = STATUS_ERROR;
658  }
659 
660  /* Clear the configuration structures before initializing them. */
661  uint8_t *clearStructPtr = (uint8_t *)(&config);
662  size_t clearSize = sizeof(edma_transfer_config_t);
663  while (clearSize > 0U)
664  {
665  *clearStructPtr = 0;
666  clearStructPtr ++;
667  clearSize --;
668  }
669 
670  clearStructPtr = (uint8_t *)(&loopConfig);
671  clearSize = sizeof(edma_loop_transfer_config_t);
672  while (clearSize > 0U)
673  {
674  *clearStructPtr = 0;
675  clearStructPtr ++;
676  clearSize --;
677  }
678 
679  /* Configure the transfer for scatter/gather mode. */
680  config.srcLastAddrAdjust = 0;
681  config.destLastAddrAdjust = 0;
682  config.srcModulo = EDMA_MODULO_OFF;
683  config.destModulo = EDMA_MODULO_OFF;
684  config.srcTransferSize = transferSize;
685  config.destTransferSize = transferSize;
686  config.minorByteTransferCount = bytesOnEachRequest;
687  config.interruptEnable = true;
688  config.scatterGatherEnable = true;
689  config.loopTransferConfig = &loopConfig;
690  config.loopTransferConfig->srcOffsetEnable = false;
691  config.loopTransferConfig->dstOffsetEnable = false;
694 
695  /* Copy scatter/gather lists to transfer configuration*/
696  for (i = 0U; (i < tcdCount) && (status == STATUS_SUCCESS); i++)
697  {
698  config.srcAddr = srcList[i].address;
699  config.destAddr = destList[i].address;
700  if ((srcList[i].length != destList[i].length) || (srcList[i].type != destList[i].type))
701  {
702  status = STATUS_ERROR;
703  break;
704  }
705  config.loopTransferConfig->majorLoopIterationCount = srcList[i].length/bytesOnEachRequest;
706 
707  switch (srcList[i].type)
708  {
710  /* Configure Source Read. */
711  config.srcOffset = 0;
712  /* Configure Dest Write. */
713  config.destOffset = (int16_t) transferOffset;
714  break;
716  /* Configure Source Read. */
717  config.srcOffset = (int16_t) transferOffset;
718  /* Configure Dest Write. */
719  config.destOffset = 0;
720  break;
722  /* Configure Source Read. */
723  config.srcOffset = (int16_t) transferOffset;
724  /* Configure Dest Write. */
725  config.destOffset = (int16_t) transferOffset;
726  break;
727  default:
728  /* This should never be reached - all the possible values have been handled. */
729  break;
730  }
731 
732  /* Configure the pointer to next software TCD structure; for the last one, this address should be 0 */
733  if (i == ((uint8_t)(tcdCount - 1U)))
734  {
735  config.scatterGatherNextDescAddr = 0U;
736  }
737  else
738  {
739  edma_software_tcd_t *nextAddr = &stcdAddr[i];
740  config.scatterGatherNextDescAddr = ((uint32_t) nextAddr);
741  }
742 
743  if (i == 0U)
744  {
745  /* Push the configuration for the first descriptor to registers */
746  EDMA_DRV_PushConfigToReg(channel, &config);
747  }
748  else
749  {
750  /* Copy configuration to software TCD structure */
751  EDMA_DRV_PushConfigToSTCD(&config, &stcdAddr[i - 1U]);
752  }
753  }
754 
755  return status;
756 }
757 
758 /*FUNCTION**********************************************************************
759  *
760  * Function Name : EDMA_DRV_StartChannel
761  * Description : Starts an eDMA channel.
762  *
763  * Implements : EDMA_DRV_StartChannel_Activity
764  *END**************************************************************************/
766 {
767  /* Check the channel number is valid */
769 
770  /* Check the eDMA module is initialized */
771  DEV_ASSERT(s_edma != NULL);
772 
773  /* Check the channel is initialized */
774  DEV_ASSERT(s_edma->chn[channel] != NULL);
775 
776  /* Enable requests for current channel */
777  DMA_Type * edmaRegBase = g_edmaBase[0U];
778  EDMA_HAL_SetDmaRequestCmd(edmaRegBase, channel, true);
779 
780  return STATUS_SUCCESS;
781 }
782 
783 /*FUNCTION**********************************************************************
784  *
785  * Function Name : EDMA_DRV_StopChannel
786  * Description : Stops an eDMA channel.
787  *
788  * Implements : EDMA_DRV_StopChannel_Activity
789  *END**************************************************************************/
791 {
792  /* Check the channel number is valid */
794 
795  /* Check the eDMA module is initialized */
796  DEV_ASSERT(s_edma != NULL);
797 
798  /* Check the channel is initialized */
799  DEV_ASSERT(s_edma->chn[channel] != NULL);
800 
801  /* Disable requests for current channel */
802  DMA_Type * edmaRegBase = g_edmaBase[0U];
803  EDMA_HAL_SetDmaRequestCmd(edmaRegBase, channel, false);
804 
805  return STATUS_SUCCESS;
806 }
807 
808 /*FUNCTION**********************************************************************
809  *
810  * Function Name : EDMA_DRV_PushConfigToSTCD
811  * Description : Copy the configuration to the software TCD structure.
812  *
813  * Implements : EDMA_DRV_PushConfigToSTCD_Activity
814  *END**************************************************************************/
816 {
817  if ((config != NULL) && (stcd != NULL))
818  {
819  /* Clear the array of software TCDs passed by the user */
821 
822  /* Set the software TCD fields */
823  stcd->ATTR = (uint16_t)((((uint16_t)config->srcModulo) << DMA_TCD_ATTR_SMOD_SHIFT) | (((uint16_t)config->srcTransferSize) << DMA_TCD_ATTR_SSIZE_SHIFT) |
824  (((uint16_t)config->destModulo) << DMA_TCD_ATTR_DMOD_SHIFT) | (((uint16_t)config->destTransferSize) << DMA_TCD_ATTR_DSIZE_SHIFT));
825  stcd->SADDR = config->srcAddr;
826  stcd->SOFF = config->srcOffset;
827  stcd->NBYTES = config->minorByteTransferCount;
828  stcd->SLAST = config->srcLastAddrAdjust;
829  stcd->DADDR = config->destAddr;
830  stcd->DOFF = config->destOffset;
831  stcd->CITER = (uint16_t) config->loopTransferConfig->majorLoopIterationCount;
832  if (config->scatterGatherEnable)
833  {
834  stcd->DLAST_SGA = (int32_t) config->scatterGatherNextDescAddr;
835  }
836  else
837  {
838  stcd->DLAST_SGA = config->destLastAddrAdjust;
839  }
840  stcd->CSR = (uint16_t) (((config->interruptEnable ? 1UL : 0UL) << DMA_TCD_CSR_INTMAJOR_SHIFT) |
841  ((config->scatterGatherEnable ? 1UL : 0UL) << DMA_TCD_CSR_ESG_SHIFT));
842  stcd->BITER = (uint16_t) config->loopTransferConfig->majorLoopIterationCount;
843  }
844 }
845 
846 /*FUNCTION**********************************************************************
847  *
848  * Function Name : EDMA_DRV_PushConfigToReg
849  * Description : Copy the configuration to the TCD registers.
850  *
851  * Implements : EDMA_DRV_PushConfigToReg_Activity
852  *END**************************************************************************/
853 void EDMA_DRV_PushConfigToReg(uint8_t channel, const edma_transfer_config_t *tcd)
854 {
855  /* Check the channel number is valid */
857 
858  /* Check the eDMA module is initialized */
859  DEV_ASSERT(s_edma != NULL);
860 
861  /* Check the channel is initialized */
862  DEV_ASSERT(s_edma->chn[channel] != NULL);
863 
864  /* Check the transfer configuration structure is valid */
865  DEV_ASSERT(tcd != NULL);
866 
867  DMA_Type * edmaRegBase = g_edmaBase[0U];
868  /* Clear TCD registers */
869  EDMA_HAL_TCDClearReg(edmaRegBase, channel);
870 
871  /* Set source and destination addresses */
872  EDMA_HAL_TCDSetSrcAddr(edmaRegBase, channel, tcd->srcAddr);
873  EDMA_HAL_TCDSetDestAddr(edmaRegBase, channel, tcd->destAddr);
874 
875  /* Set source/destination modulo feature and transfer size */
876  EDMA_HAL_TCDSetAttribute(edmaRegBase, channel, tcd->srcModulo, tcd->destModulo,
877  tcd->srcTransferSize, tcd->destTransferSize);
878 
879  /* Set source/destination offset and last adjustment; for scatter/gather operation, destination
880  * last adjustment is the address of the next TCD structure to be loaded by the eDMA engine */
881  EDMA_HAL_TCDSetSrcOffset(edmaRegBase, channel, tcd->srcOffset);
882  EDMA_HAL_TCDSetDestOffset(edmaRegBase, channel, tcd->destOffset);
883  EDMA_HAL_TCDSetSrcLastAdjust(edmaRegBase, channel, tcd->srcLastAddrAdjust);
884  if (tcd->scatterGatherEnable)
885  {
886  EDMA_HAL_TCDSetScatterGatherCmd(edmaRegBase, channel, true);
888  }
889  else
890  {
891  EDMA_HAL_TCDSetScatterGatherCmd(edmaRegBase, channel, false);
892  EDMA_HAL_TCDSetDestLastAdjust(edmaRegBase, channel, tcd->destLastAddrAdjust);
893  }
894 
895  /* Configure channel interrupt */
896  EDMA_HAL_TCDSetIntCmd(edmaRegBase, channel, tcd->interruptEnable);
897 
898  /* If loop configuration is available, copy minor/major loop setup to registers */
899  if (tcd->loopTransferConfig != NULL)
900  {
904  EDMA_HAL_TCDSetNbytes(edmaRegBase, channel, tcd->minorByteTransferCount);
905 
910 
912  }
913  else
914  {
915  EDMA_HAL_TCDSetNbytes(edmaRegBase, channel, tcd->minorByteTransferCount);
916  }
917 }
918 
919 #ifdef DEV_ERROR_DETECT
920 /*FUNCTION**********************************************************************
921  *
922  * Function Name : EDMA_DRV_ValidTransferSize
923  * Description : Check if the transfer size value is legal (0/1/2/4/5).
924  *
925  *END**************************************************************************/
926 static bool EDMA_DRV_ValidTransferSize(edma_transfer_size_t size)
927 {
928  bool isValid;
929  switch (size)
930  {
936  isValid = true;
937  break;
938  default:
939  isValid = false;
940  break;
941  }
942  return isValid;
943 }
944 #endif
945 
946 /*FUNCTION**********************************************************************
947  *
948  * Function Name : EDMA_DRV_GetChannelStatus
949  * Description : Returns the eDMA channel status.
950  *
951  * Implements : EDMA_DRV_GetChannelStatus_Activity
952  *END**************************************************************************/
954 {
955  /* Check the channel number is valid */
957 
958  /* Check the eDMA module is initialized */
959  DEV_ASSERT(s_edma != NULL);
960 
961  /* Check the channel is initialized */
962  DEV_ASSERT(s_edma->chn[channel] != NULL);
963 
964  return s_edma->chn[channel]->status;
965 }
966 
967 /*******************************************************************************
968  * EOF
969  ******************************************************************************/
970 
971 
void EDMA_DRV_PushConfigToSTCD(const edma_transfer_config_t *config, edma_software_tcd_t *stcd)
Copies the channel configuration to the software TCD structure.
Definition: edma_driver.c:815
void DMAMUX_HAL_Init(DMAMUX_Type *base)
Initializes the DMAMUX module to the reset state.
Definition: dmamux_hal.c:42
edma_chn_state_t *volatile chn[FEATURE_EDMA_MODULE_CHANNELS]
Definition: edma_driver.h:195
static void EDMA_HAL_TCDSetSrcAddr(DMA_Type *base, uint32_t channel, uint32_t address)
Configures the source address for the hardware TCD.
Definition: edma_hal.h:794
static void EDMA_HAL_TCDSetChannelMajorLink(DMA_Type *base, uint32_t channel, uint32_t majorLinkChannel, bool enable)
Configures the major channel link the TCD.
Definition: edma_hal.h:1069
eDMA TCD Implements : edma_software_tcd_t_Class
Definition: edma_driver.h:260
void EDMA_HAL_TCDSetScatterGatherLink(DMA_Type *base, uint32_t channel, uint32_t nextTCDAddr)
Configures the memory address for the next transfer TCD for the TCD.
Definition: edma_hal.c:332
uint32_t minorByteTransferCount
Definition: edma_driver.h:242
#define DMAMUX_INSTANCE_COUNT
Definition: S32K144.h:3115
DMAMUX_Type *const g_dmamuxBase[DMAMUX_INSTANCE_COUNT]
Array for DMAMUX module register base address.
Definition: edma_common.c:50
edma_modulo_t destModulo
Definition: edma_driver.h:241
static status_t EDMA_DRV_RequestChannel(uint8_t requestedChannel, dma_request_source_t source, edma_chn_state_t *chn)
Definition: edma_driver.c:306
void EDMA_HAL_TCDClearReg(DMA_Type *base, uint32_t channel)
Clears all registers to 0 for the hardware TCD.
Definition: edma_hal.c:172
edma_callback_t callback
Definition: edma_driver.h:163
The user configuration structure for the eDMA driver.
Definition: edma_driver.h:107
edma_transfer_type_t
A type for the DMA transfer. Implements : edma_transfer_type_t_Class.
Definition: edma_driver.h:170
static void EDMA_HAL_TCDSetDestMinorLoopOffsetCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/disables the destination minor loop offset feature for the TCD.
Definition: edma_hal.h:910
The user configuration structure for the an eDMA driver channel.
Definition: edma_driver.h:158
#define FEATURE_EDMA_MODULE_CHANNELS
status_t EDMA_DRV_ReleaseChannel(uint8_t channel)
Releases an eDMA channel.
Definition: edma_driver.c:359
static void EDMA_HAL_TCDSetSrcLastAdjust(DMA_Type *base, uint32_t channel, int32_t size)
Configures the last source address adjustment for the TCD.
Definition: edma_hal.h:952
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
Definition: edma_driver.c:790
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K144.h:269
void EDMA_HAL_TCDSetMajorCount(DMA_Type *base, uint32_t channel, uint32_t count)
Sets the major iteration count according to minor loop channel link setting.
Definition: edma_hal.c:388
status_t EDMA_DRV_Deinit(void)
De-initializes the eDMA module.
Definition: edma_driver.c:199
status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t *userConfig, edma_chn_state_t *const chnStateArray[], const edma_channel_config_t *const chnConfigArray[], uint8_t chnCount)
Initializes the eDMA module.
Definition: edma_driver.c:91
edma_channel_priority_t priority
Definition: edma_driver.h:159
static void EDMA_HAL_TCDSetSrcMinorLoopOffsetCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/disables the source minor loop offset feature for the TCD.
Definition: edma_hal.h:881
void EDMA_DRV_IRQHandler(uint8_t channel)
Definition: edma_driver.c:428
static void DMAMUX_HAL_SetChannelCmd(DMAMUX_Type *base, uint32_t channel, bool enable)
Enables/Disables the DMAMUX channel.
Definition: dmamux_hal.h:63
static void EDMA_HAL_ClearIntStatusFlag(DMA_Type *base, uint8_t channel)
Clears the interrupt status for the eDMA channel or all channels.
Definition: edma_hal.h:737
const clock_names_t g_edmaClockNames[DMA_INSTANCE_COUNT]
Array for eDMA clock sources.
Definition: edma_common.c:61
dma_request_source_t
Structure for the DMA hardware request.
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
static void EDMA_HAL_TCDSetScatterGatherCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/Disables the scatter/gather feature for the TCD.
Definition: edma_hal.h:1094
void EDMA_HAL_SetErrorIntCmd(DMA_Type *base, uint8_t channel, bool enable)
Enables/Disables the error interrupt for channels.
Definition: edma_hal.c:106
const IRQn_Type g_edmaIrqId[FEATURE_CHANNEL_INTERRUPT_LINES]
Array for eDMA channel interrupt vector number.
Definition: edma_common.c:53
#define DEV_ASSERT(x)
Definition: devassert.h:78
uint32_t scatterGatherNextDescAddr
Definition: edma_driver.h:245
status_t EDMA_DRV_ConfigLoopTransfer(uint8_t channel, const edma_transfer_config_t *transferConfig)
Configures the DMA transfer in loop mode.
Definition: edma_driver.c:577
#define STCD_ADDR(address)
Definition: edma_driver.h:90
status_t EDMA_DRV_ChannelInit(edma_chn_state_t *edmaChannelState, const edma_channel_config_t *edmaChannelConfig)
Initializes an eDMA channel.
Definition: edma_driver.c:246
void EDMA_DRV_ErrorIRQHandler(void)
Definition: edma_driver.c:448
Runtime state structure for the eDMA driver.
Definition: edma_driver.h:194
static void EDMA_HAL_TCDSetSrcOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the source address signed offset for the hardware TCD.
Definition: edma_hal.h:813
edma_chn_status_t
Channel status for eDMA channel.
Definition: edma_driver.h:125
static void EDMA_HAL_TCDSetDestAddr(DMA_Type *base, uint32_t channel, uint32_t address)
Configures the destination address for the TCD.
Definition: edma_hal.h:968
edma_transfer_size_t destTransferSize
Definition: edma_driver.h:230
edma_callback_t callback
Definition: edma_driver.h:144
#define DMA_TCD_ATTR_DMOD_SHIFT
Definition: S32K144.h:2934
static void EDMA_HAL_SetHaltCmd(DMA_Type *base, bool halt)
Halts/Un-halts the DMA Operations.
Definition: edma_hal.h:206
static void EDMA_HAL_TCDSetDestLastAdjust(DMA_Type *base, uint32_t channel, int32_t adjust)
Configures the last source address adjustment.
Definition: edma_hal.h:1007
#define DMA_TCD_CSR_ESG_SHIFT
Definition: S32K144.h:3040
static void EDMA_HAL_SetChannelPriority(DMA_Type *base, uint32_t channel, edma_channel_priority_t priority)
Sets the eDMA channel priority.
Definition: edma_hal.h:475
void EDMA_DRV_PushConfigToReg(uint8_t channel, const edma_transfer_config_t *tcd)
Copies the channel configuration to the TCD registers.
Definition: edma_driver.c:853
static void EDMA_HAL_SetHaltOnErrorCmd(DMA_Type *base, bool haltOnError)
Halts or does not halt the eDMA module when an error occurs.
Definition: edma_hal.h:225
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
static edma_state_t * s_edma
EDMA global structure to maintain eDMA state.
Definition: edma_driver.c:68
edma_arbitration_algorithm_t chnArbitration
Definition: edma_driver.h:108
void EDMA_HAL_TCDSetMinorLoopOffset(DMA_Type *base, uint32_t channel, int32_t offset)
Configures the minor loop offset for the TCD.
Definition: edma_hal.c:297
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:31
void EDMA_HAL_TCDSetChannelMinorLink(DMA_Type *base, uint32_t channel, uint32_t linkChannel, bool enable)
Sets the channel minor link for the TCD.
Definition: edma_hal.c:347
static void EDMA_HAL_SetMinorLoopMappingCmd(DMA_Type *base, bool enable)
Enables/Disables the minor loop mapping.
Definition: edma_hal.h:584
static void EDMA_DRV_ClearIntStatus(uint8_t channel)
Definition: edma_driver.c:398
void EDMA_HAL_TCDSetAttribute(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo, edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize)
Configures the transfer attribute for the eDMA channel.
Definition: edma_hal.c:194
edma_modulo_t srcModulo
Definition: edma_driver.h:240
status_t EDMA_DRV_ConfigScatterGatherTransfer(uint8_t channel, edma_software_tcd_t *stcd, edma_transfer_size_t transferSize, uint32_t bytesOnEachRequest, const edma_scatter_gather_list_t *srcList, const edma_scatter_gather_list_t *destList, uint8_t tcdCount)
Configures the DMA transfer in a scatter-gather mode.
Definition: edma_driver.c:614
#define DMA_TCD_ATTR_SMOD_SHIFT
Definition: S32K144.h:2942
#define EDMA_ERR_LSB_MASK
Macro for accessing the least significant bit of the ERR register.
Definition: edma_driver.h:98
edma_transfer_size_t srcTransferSize
Definition: edma_driver.h:229
Data structure for configuring a discrete memory transfer. Implements : edma_scatter_gather_list_t_Cl...
Definition: edma_driver.h:179
#define FEATURE_CHANNEL_INTERRUPT_LINES
volatile edma_chn_status_t status
Definition: edma_driver.h:148
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
Definition: edma_hal.h:132
static void EDMA_HAL_ClearErrorIntStatusFlag(DMA_Type *base, uint8_t channel)
Clears the error interrupt status for the eDMA channel or channels.
Definition: edma_hal.h:645
edma_chn_status_t EDMA_DRV_GetChannelStatus(uint8_t channel)
Gets the eDMA channel status.
Definition: edma_driver.c:953
edma_transfer_type_t type
Definition: edma_driver.h:182
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
Definition: edma_driver.c:765
const IRQn_Type g_edmaErrIrqId[FEATURE_ERROR_INTERRUPT_LINES]
Array for eDMA module's error interrupt vector number.
Definition: edma_common.c:57
#define FEATURE_DMAMUX_REQ_SRC_TO_CHN(x)
static void EDMA_HAL_TCDSetDestOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the destination address signed offset for the TCD.
Definition: edma_hal.h:987
#define FEATURE_ERROR_INTERRUPT_LINES
static uint32_t EDMA_HAL_GetErrorIntStatusFlag(const DMA_Type *base)
Gets the eDMA error interrupt status.
Definition: edma_hal.h:632
DMA_Type *const g_edmaBase[DMA_INSTANCE_COUNT]
Array for the eDMA module register base address.
Definition: edma_common.c:47
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
void EDMA_HAL_SetDmaRequestCmd(DMA_Type *base, uint8_t channel, bool enable)
Enables/Disables the DMA request for the channel or all channels.
Definition: edma_hal.c:125
#define DMA_TCD_CSR_INTMAJOR_SHIFT
Definition: S32K144.h:3028
static void EDMA_HAL_TCDSetIntCmd(DMA_Type *base, uint32_t channel, bool enable)
Enables/Disables the interrupt after the major loop completes for the TCD.
Definition: edma_hal.h:1166
static void EDMA_HAL_ClearDoneStatusFlag(DMA_Type *base, uint8_t channel)
Clears the done status for a channel or all channels.
Definition: edma_hal.h:688
static void DMAMUX_HAL_SetChannelSource(DMAMUX_Type *base, uint32_t channel, uint8_t source)
Configures the DMA request for the DMAMUX channel.
Definition: dmamux_hal.h:108
#define DMA_TCD_ATTR_SSIZE_SHIFT
Definition: S32K144.h:2938
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
Definition: edma_driver.h:137
dma_request_source_t source
Definition: edma_driver.h:162
static edma_arbitration_algorithm_t EDMA_HAL_GetChannelArbitrationMode(const DMA_Type *base)
Gets the channel arbitration algorithm.
Definition: edma_hal.h:512
void EDMA_HAL_Init(DMA_Type *base)
Initializes eDMA module to known state.
Definition: edma_hal.c:42
void EDMA_HAL_TCDSetNbytes(DMA_Type *base, uint32_t channel, uint32_t nbytes)
Configures the nbytes for the eDMA channel.
Definition: edma_hal.c:215
status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t dataBufferSize)
Configures a simple single block data transfer with DMA.
Definition: edma_driver.c:487
static void EDMA_DRV_ClearSoftwareTCD(edma_software_tcd_t *stcd)
Definition: edma_driver.c:411
#define FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(x)
eDMA loop transfer configuration.
Definition: edma_driver.h:204
#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x)
eDMA transfer size configuration.
Definition: edma_driver.h:226
edma_loop_transfer_config_t * loopTransferConfig
Definition: edma_driver.h:251
static void EDMA_HAL_SetChannelArbitrationMode(DMA_Type *base, edma_arbitration_algorithm_t channelArbitration)
Sets the channel arbitration algorithm.
Definition: edma_hal.h:496
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
Definition: edma_driver.c:285
const clock_names_t g_dmamuxClockNames[DMAMUX_INSTANCE_COUNT]
Definition: edma_common.c:62
#define DMA_TCD_ATTR_DSIZE_SHIFT
Definition: S32K144.h:2930
Data structure for the eDMA channel state. Implements : edma_chn_state_t_Class.
Definition: edma_driver.h:142