S32 SDK
ftm_driver.c
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
63 #include "ftm_driver.h"
64 
65 /*******************************************************************************
66  * Variables
67  ******************************************************************************/
68 
71 
77 
80 
86 
87 /*******************************************************************************
88  * Code
89  ******************************************************************************/
90 static void FTM_DRV_InputCaptureHandler(uint32_t instance,
91  uint8_t channelPair);
92 
93 static void FTM_DRV_IrqHandler(uint32_t instance,
94  uint8_t channelPair);
95 
96 void FTM0_Ch0_Ch1_IRQHandler(void);
97 
98 void FTM0_Ch2_Ch3_IRQHandler(void);
99 
100 void FTM0_Ch4_Ch5_IRQHandler(void);
101 
102 void FTM0_Ch6_Ch7_IRQHandler(void);
103 
104 void FTM1_Ch0_Ch1_IRQHandler(void);
105 
106 void FTM1_Ch2_Ch3_IRQHandler(void);
107 
108 void FTM1_Ch4_Ch5_IRQHandler(void);
109 
110 void FTM1_Ch6_Ch7_IRQHandler(void);
111 
112 void FTM2_Ch0_Ch1_IRQHandler(void);
113 
114 void FTM2_Ch2_Ch3_IRQHandler(void);
115 
116 void FTM2_Ch4_Ch5_IRQHandler(void);
117 
118 void FTM2_Ch6_Ch7_IRQHandler(void);
119 
120 void FTM3_Ch0_Ch1_IRQHandler(void);
121 
122 void FTM3_Ch2_Ch3_IRQHandler(void);
123 
124 void FTM3_Ch4_Ch5_IRQHandler(void);
125 
126 void FTM3_Ch6_Ch7_IRQHandler(void);
127 
128 /*FUNCTION**********************************************************************
129  *
130  * Function Name : FTM_DRV_Init
131  * Description : Initializes the FTM driver and get the clock frequency value
132  * which select one of three possible clock sources for the FTM counter.
133  *
134  * Implements : FTM_DRV_Init_Activity
135  *END**************************************************************************/
136 status_t FTM_DRV_Init(uint32_t instance,
137  const ftm_user_config_t * info,
138  ftm_state_t * state)
139 {
140  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
141  DEV_ASSERT(info != NULL);
142  DEV_ASSERT(state != NULL);
143  FTM_Type * ftmBase = g_ftmBase[instance];
144  status_t status = STATUS_SUCCESS;
145 
146  /* Check if this instance is already initialized */
147  if (ftmStatePtr[instance] != NULL)
148  {
149  status = STATUS_ERROR;
150  }
151  else
152  {
153  /* Configure state structure. */
154  state->ftmClockSource = info->ftmClockSource;
156  state->ftmPeriod = 0U;
157  ftmStatePtr[instance] = state;
158  /* The reset operation doesn't care about write protection. FTM_HAL_Reset will
159  * disable this protection.*/
160  FTM_HAL_Reset(ftmBase);
161  FTM_HAL_Init(ftmBase, info->ftmPrescaler);
162  /* Get clock name used to configure the FlexTimer module */
164  /* Check the functional clock is selected for FTM */
165  DEV_ASSERT(state->ftmSourceClockFrequency > 0U);
166  }
167 
168  if (STATUS_SUCCESS == status)
169  {
170  /* Check if the mode operation in PWM mode */
172  {
173  /* Configure sync for between registers and buffers */
174  status = FTM_DRV_SetSync(instance, &(info->syncMethod));
175  }
176 
177  /* Enable the generation of initialization trigger on chip module */
179  FTM_HAL_SetBdmMode(ftmBase, info->BDMMode);
180 
181  /* Check if enable interrupt in counter mode */
182  if (info->isTofIsrEnabled)
183  {
184  FTM_HAL_SetTimerOverflowInt(ftmBase, true);
186  }
187  else
188  {
189  FTM_HAL_SetTimerOverflowInt(ftmBase, false);
191  }
192  }
193 
194  return status;
195 }
196 
197 /*FUNCTION**********************************************************************
198  *
199  * Function Name : FTM_DRV_Deinit
200  * Description : Shuts down the FTM driver.
201  * First, FTM_DRV_Init must be called. Then this function will disables the FTM module.
202  *
203  * Implements : FTM_DRV_Deinit_Activity
204  *END**************************************************************************/
205 status_t FTM_DRV_Deinit(uint32_t instance)
206 {
207  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
208  FTM_Type * ftmBase = g_ftmBase[instance];
209 
210  /* Reset all FTM register */
211  FTM_HAL_Reset(ftmBase);
212  ftmStatePtr[instance] = NULL;
213 
214  return STATUS_SUCCESS;
215 }
216 
217 /*FUNCTION**********************************************************************
218  *
219  * Function Name : FTM_DRV_InitCounter
220  * Description : Initializes the FTM counter. This function provides access to the
221  * FTM counter settings. The counter can be run in Up counting or Up-down counting modes.
222  * To run the counter in Free running mode, choose Up counting option and provide
223  * 0x0 for the countStartVal and 0xFFFF for countFinalVal. Please call this
224  * function only when FTM is used as timer/counter.
225  *
226  * Implements : FTM_DRV_InitCounter_Activity
227  *END**************************************************************************/
228 status_t FTM_DRV_InitCounter(uint32_t instance,
229  const ftm_timer_param_t * timer)
230 {
231  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
232  DEV_ASSERT(timer != NULL);
233  DEV_ASSERT((FTM_MODE_UP_TIMER == timer->mode) || (FTM_MODE_UP_DOWN_TIMER == timer->mode));
234  FTM_Type * ftmBase = g_ftmBase[instance];
235  ftm_state_t * state = ftmStatePtr[instance];
236  status_t retStatus = STATUS_SUCCESS;
237  uint8_t channel = 0U;
238 
239  if ((NULL != state) && (FTM_MODE_NOT_INITIALIZED == state->ftmMode))
240  {
241  /* Disable counter clock */
243  /* Clear the overflow flag */
245  /* Set counter initial and maximum values */
246  FTM_HAL_SetCounterInitVal(ftmBase, timer->initialValue);
247  FTM_HAL_SetMod(ftmBase, timer->finalValue);
248  /* Disable the quadrature decoder mode */
249  FTM_HAL_SetQuadDecoderCmd(ftmBase, false);
250  /* Use FTM as counter, disable all the channels */
251  for (channel = 0U; channel < FEATURE_FTM_CHANNEL_COUNT; channel++)
252  {
253  FTM_HAL_SetChnEdgeLevel(ftmBase, channel, 0U);
254  }
255 
256  /* Check the FTM counter modes */
257  if (FTM_MODE_UP_TIMER == timer->mode)
258  {
259  FTM_HAL_SetCpwms(ftmBase, false);
260  }
261  else if (FTM_MODE_UP_DOWN_TIMER == timer->mode)
262  {
263  FTM_HAL_SetCpwms(ftmBase, true);
264  }
265  else
266  {
267  /* Do nothing */
268  }
269 
270  state->ftmMode = timer->mode;
271  }
272  else
273  {
274  retStatus = STATUS_ERROR;
275  }
276 
277  return retStatus;
278 }
279 
280 /*FUNCTION**********************************************************************
281  *
282  * Function Name : FTM_DRV_CounterStart
283  * Description : Starts the FTM counter.
284  *
285  * Implements : FTM_DRV_CounterStart_Activity
286  *END**************************************************************************/
287 status_t FTM_DRV_CounterStart(uint32_t instance)
288 {
289  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
290  FTM_Type * ftmBase = g_ftmBase[instance];
291 
292  const ftm_state_t * state = ftmStatePtr[instance];
293  /* Check the clock source is available for FTM counter */
294  DEV_ASSERT(state->ftmSourceClockFrequency > 0U);
295  /* Enable counter clock */
296  FTM_HAL_SetClockSource(ftmBase, state->ftmClockSource);
297 
298  return STATUS_SUCCESS;
299 }
300 
301 /*FUNCTION**********************************************************************
302  *
303  * Function Name : FTM_DRV_CounterStop
304  * Description : Stops the FTM counter.
305  *
306  * Implements : FTM_DRV_CounterStop_Activity
307  *END**************************************************************************/
308 status_t FTM_DRV_CounterStop(uint32_t instance)
309 {
310  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
311  FTM_Type * ftmBase = g_ftmBase[instance];
312  ftm_state_t * state = ftmStatePtr[instance];
313 
314  /* Stop the FTM counter */
317 
318  return STATUS_SUCCESS;
319 }
320 
321 /*FUNCTION**********************************************************************
322  *
323  * Function Name : FTM_DRV_CounterRead
324  * Description : Reads back the current value of the FTM counter.
325  *
326  * Implements : FTM_DRV_CounterRead_Activity
327  *END**************************************************************************/
328 uint32_t FTM_DRV_CounterRead(uint32_t instance)
329 {
330  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
331  FTM_Type const * ftmBase = g_ftmBase[instance];
332 
333  return FTM_HAL_GetCounter(ftmBase);
334 }
335 
336 /*FUNCTION**********************************************************************
337  *
338  * Function Name : FTM_DRV_DeinitPwm
339  * Description : Stops all PWM channels.
340  *
341  * Implements : FTM_DRV_DeinitPwm_Activity
342  *END**************************************************************************/
343 status_t FTM_DRV_DeinitPwm(uint32_t instance)
344 {
345  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
346  FTM_Type * ftmBase = g_ftmBase[instance];
347  uint8_t channel;
348  uint8_t chnlPairNum;
349  ftm_state_t * state = ftmStatePtr[instance];
350 
351  /* Stop the FTM counter */
353  for (channel = 0U; channel < FEATURE_FTM_CHANNEL_COUNT; channel++)
354  {
355  chnlPairNum = (uint8_t)(channel >> 1U);
356  /* Disable PWM mode in hardware */
357  FTM_HAL_SetChnCountVal(ftmBase, channel, 0U);
358  FTM_HAL_SetChnEdgeLevel(ftmBase, channel, 0U);
359  FTM_HAL_SetChnMSnBAMode(ftmBase, channel, 0U);
360  FTM_HAL_SetCpwms(ftmBase, false);
361  /* Configure polarity bit */
363  FTM_HAL_DisablePwmChannelOutputs(ftmBase, channel);
364  /* Clear the PWM synchronization */
365  FTM_HAL_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum, false);
366  /* Clear combination for each pair of channels */
367  FTM_HAL_SetDualChnMofCombineCmd(ftmBase, chnlPairNum, false);
368  FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairNum, false);
369  FTM_HAL_SetDualChnDeadtimeCmd(ftmBase, chnlPairNum, false);
370  FTM_HAL_SetDualChnFaultCmd(ftmBase, chnlPairNum, false);
371  }
372 
373  /* Clear the dead-time pre-scaler and value */
374  FTM_HAL_SetExtDeadtimeValue(ftmBase, 0U);
376  FTM_HAL_SetDeadtimeCount(ftmBase, 0U);
377  /* Clear fault control register */
378  FTM_HAL_ClearFaultControl(ftmBase);
379  /* Disable fault interrupt */
380  FTM_HAL_SetFaultInt(ftmBase, false);
381  /* Disable fault control */
383  /* Clear the module value of the registers */
384  FTM_HAL_SetMod(ftmBase, 0U);
385  FTM_HAL_SetCounter(ftmBase, 0U);
387 
388  return STATUS_SUCCESS;
389 }
390 
391 /*FUNCTION**********************************************************************
392  *
393  * Function Name : FTM_DRV_InitPwm
394  * Description : Configures duty cycle and frequency and starts outputting
395  * PWM on specified channels.
396  *
397  * Implements : FTM_DRV_InitPwm_Activity
398  *END**************************************************************************/
399 status_t FTM_DRV_InitPwm(uint32_t instance,
400  const ftm_pwm_param_t * param)
401 {
402  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
403  DEV_ASSERT(param != NULL);
404  status_t retVal = STATUS_SUCCESS;
405  uint8_t index = 0U;
406  uint8_t hwChannel = 0U;
407  uint8_t fltChannel = 0U;
408  uint8_t chnlPairNum = 0U;
409  uint8_t channelId = 0U;
410  ftm_state_t * state = ftmStatePtr[instance];
411  FTM_Type * ftmBase = g_ftmBase[instance];
412 
413  if ((NULL != state) && (FTM_MODE_NOT_INITIALIZED == state->ftmMode))
414  {
415  /* Disable counter clock */
417  /* Clear the overflow flag */
419  /* Disable write protection */
420  FTM_HAL_SetWriteProtectionCmd(ftmBase, false);
421  /* Configure FTM mode */
422  state->ftmMode = param->mode;
423 
424  /* Configure independent PWM channels */
425  for (index = 0U; index < param->nNumIndependentPwmChannels; index++)
426  {
427  channelId = param->pwmIndependentChannelConfig[index].hwChannelId;
428  chnlPairNum = (uint8_t)(channelId >> 1U);
429  FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum, false);
430  /* Set ELSB bit and clear ELSA bit*/
431  FTM_HAL_SetChnEdgeLevel(ftmBase, channelId, 2U);
432  /* Set MSB and MSA bits*/
433  FTM_HAL_SetChnMSnBAMode(ftmBase, channelId, 3U);
434  /* Write FTMn_PWMLOAD register to enable synchronized loading points for the given channel */
435  FTM_HAL_EnablePwmChannelOutputs(ftmBase, channelId);
436  FTM_HAL_SetChnOutputPolarityCmd(ftmBase, channelId, param->pwmIndependentChannelConfig[index].polarity);
437  FTM_HAL_SetDualChnFaultCmd(ftmBase, chnlPairNum, ((param->faultConfig)->faultMode != FTM_FAULT_CONTROL_DISABLED) ? true : false);
438  /* Enable sync control for channels*/
439  FTM_HAL_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum, true);
440  FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairNum, false);
441  FTM_HAL_SetDualChnMofCombineCmd(ftmBase, chnlPairNum, false);
442  /* Enable the generation a trigger on chip module */
444  }
445 
446  /* Configure combined PWM channels */
447  for (index = 0U; index < param->nNumCombinedPwmChannels; index++)
448  {
449  channelId = param->pwmCombinedChannelConfig[index].hwChannelId;
450  chnlPairNum = (uint8_t)(channelId >> 1U);
451  FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum, false);
452  /* Set ELSB bit and clear ELSA bit*/
453  FTM_HAL_SetChnEdgeLevel(ftmBase, channelId, 2U);
454  /* Set MSB and MSA bits */
455  FTM_HAL_SetChnMSnBAMode(ftmBase, channelId, 3U);
456  /* Write FTMn_PWMLOAD register to enable synchronized loading points for the given channel */
457  /* Enable channel (n) output */
458  FTM_HAL_EnablePwmChannelOutputs(ftmBase, channelId);
459  /* Enable channel (n+1) output */
461  {
462  FTM_HAL_EnablePwmChannelOutputs(ftmBase, (uint8_t)(channelId + 1U));
463  /* When ELSB = 0 and ELSA = 0 for channel (n+1) output is not available */
464  FTM_HAL_SetChnEdgeLevel(ftmBase, (uint8_t)(channelId + 1U), 2U);
465  /* Configure complementary mode for channel (n+1) */
466  FTM_HAL_SetDualChnCompCmd(ftmBase, chnlPairNum, param->pwmCombinedChannelConfig[index].secondChannelPolarity);
467  }
468  else
469  {
470  FTM_HAL_DisablePwmChannelOutputs(ftmBase, (uint8_t)(channelId + 1U));
471  }
472 
474  FTM_HAL_SetDualChnFaultCmd(ftmBase, chnlPairNum, ((param->faultConfig)->faultMode != FTM_FAULT_CONTROL_DISABLED) ? true : false);
475  /* Enable sync control for channels */
476  FTM_HAL_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum, true);
477  /* Enable the combine mode */
478  FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairNum, true);
479  /* Configure the modified combine mode */
481  /* Configure dead time */
482  FTM_HAL_SetDualChnDeadtimeCmd(ftmBase, chnlPairNum, param->pwmCombinedChannelConfig[index].deadTime);
483  /* Enable the generation a trigger on the channel (n) */
484  FTM_HAL_SetChnTriggerCmd(ftmBase, (chnlPairNum << 1U), param->pwmCombinedChannelConfig[index].enableExternalTrigger);
485  /* Enable the generation a trigger on the channel (n+1) */
486  FTM_HAL_SetChnTriggerCmd(ftmBase, (chnlPairNum << 1U) + 1U, param->pwmCombinedChannelConfig[index].enableExternalTriggerOnNextChn);
487  }
488 
489  /* Set enable outputs to be set to Initial/default value */
490  FTM_HAL_SetInitChnOutputCmd(ftmBase, true);
491  /* Enable faults (if faults were configured) */
492  if ((param->faultConfig)->faultMode != FTM_FAULT_CONTROL_DISABLED)
493  {
494  /* Configure PWM Output behavior */
495  FTM_HAL_SetPwmFaultBehavior(ftmBase, ((param->faultConfig)->pwmOutputStateOnFault) ? true : false);
496  /* Configure fault filter value */
497  FTM_HAL_SetFaultInputFilterVal(ftmBase, ((param->faultConfig)->faultFilterValue));
498  for (fltChannel = 0U; fltChannel < FTM_FEATURE_FAULT_CHANNELS; fltChannel++)
499  {
500  if (true == (param->faultConfig)->ftmFaultChannelParam[fltChannel].faultChannelEnabled)
501  {
502  /* Enable fault channel */
503  FTM_HAL_SetFaultInputCmd(ftmBase, fltChannel, true);
504  /* Configure fault filter */
506  fltChannel,
507  ((param->faultConfig)->ftmFaultChannelParam[fltChannel].faultFilterEnabled) ? true : false);
508  /* Configure fault outputs */
509  FTM_HAL_SetChnFaultInputPolarityCmd(ftmBase, fltChannel,
510  ((param->faultConfig)->ftmFaultChannelParam[fltChannel].ftmFaultPinPolarity));
511  }
512  }
513 
514  /* Set fault interrupt */
515  if (true == ((param->faultConfig)->pwmFaultInterrupt))
516  {
517  FTM_HAL_SetFaultInt(ftmBase, true);
518  }
519 
520  /* Enable fault control */
521  FTM_HAL_SetFaultControlMode(ftmBase, (param->faultConfig)->faultMode);
522  }
523 
524  /* Configure PWM mode: edge or center aligned */
525  FTM_HAL_SetCpwms(ftmBase, (param->mode == FTM_MODE_CEN_ALIGNED_PWM) ? true : false);
526  /* Calculate frequency of the give FTM hardware module - all channels will run at the same frequency */
527  state->ftmPeriod = FTM_DRV_ConvertFreqToPeriodTicks(instance, param->uFrequencyHZ);
528  /* Based on reference manual, in PWM mode CNTIN is to be set 0*/
529  FTM_HAL_SetCounterInitVal(ftmBase, 0U);
530  /* Write MOD register with the value of the period */
531  /* For center aligned mode MOD register should be divided by 2 */
532  /* For edge aligned mode period is determined by: MOD-CNTIN+1 */
533  if (param->mode == FTM_MODE_CEN_ALIGNED_PWM)
534  {
535  FTM_HAL_SetMod(ftmBase, (uint16_t)(state->ftmPeriod >> 1U));
536  }
537  else
538  {
539  FTM_HAL_SetMod(ftmBase, (uint16_t)(state->ftmPeriod - 1U));
540  }
541 
542  for (index = 0U; index < param->nNumIndependentPwmChannels; index++)
543  {
544  hwChannel = param->pwmIndependentChannelConfig[index].hwChannelId;
545  /* Write CnV registers and setup duty cycle and phase values */
546  retVal = FTM_DRV_UpdatePwmChannel(instance,
547  hwChannel,
550  0U,
551  false);
552  }
553 
554  for (index = 0U; index < param->nNumCombinedPwmChannels; index++)
555  {
556  hwChannel = param->pwmCombinedChannelConfig[index].hwChannelId;
557  /* Write CnV registers and setup duty cycle and phase values */
558  retVal = FTM_DRV_UpdatePwmChannel(instance,
559  hwChannel,
561  param->pwmCombinedChannelConfig[index].firstEdge,
562  param->pwmCombinedChannelConfig[index].secondEdge,
563  false);
564  }
565 
566  if (STATUS_SUCCESS == retVal)
567  {
568  /* Configure dead time for combine mode */
569  FTM_HAL_SetDeadtimeCount(ftmBase, param->deadTimeValue);
571  FTM_HAL_Enable(ftmBase, true);
572  FTM_HAL_SetPwmSyncMode(ftmBase, true);
573  /* Set clock source to start counter */
574  FTM_HAL_SetClockSource(ftmBase, state->ftmClockSource);
575  }
576  else
577  {
578  /* Restore FTM mode if initialization fails */
580  }
581  }
582  else
583  {
584  retVal = STATUS_ERROR;
585  }
586 
587  return retVal;
588 }
589 
590 /*FUNCTION**********************************************************************
591  *
592  * Function Name : FTM_DRV_UpdatePwmChannel
593  * Description : This function will update the duty cycle of PWM output.
594  * - If the type of update in the duty cycle, this function will convert the input parameters representing
595  * frequency in Hz to a period value in ticks needed by the hardware timer. Period is calculated depending
596  * on the operating mode of the FTM module and is stored in internal state structure.
597  * firstEdge and secondEdge can have value between 0 - FTM_MAX_DUTY_CYCLE(0 = 0% duty
598  * and FTM_MAX_DUTY_CYCLE = 100% duty). secondEdge value is used only whenFTM module is used in PWM combine mode.
599  * - If the type of update in ticks, this function will get value in ticks to the hardware timer.
600  * firstEdge and secondEdge variables can have value between 0 and ftmPeriod is stored in the state structure.
601  * - in the modified combine mode, the firstEdge parameter is fixed value and only can modify the secondEdge variables
602  * which is the initial value in the channel (n+1) match edge when the FTM counter has been ran.
603  *
604  * Implements : FTM_DRV_UpdatePwmChannel_Activity
605  *END**************************************************************************/
607  uint8_t channel,
608  ftm_pwm_update_option_t typeOfUpdate,
609  uint16_t firstEdge,
610  uint16_t secondEdge,
611  bool softwareTrigger)
612 {
613  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
615  uint16_t hwFirstEdge = 0U;
616  uint16_t hwSecondEdge = 0U;
617  uint16_t ftmPeriod = 0U;
618  uint8_t chnlPairNum = (uint8_t)(channel >> 1U);
619  FTM_Type * ftmBase = g_ftmBase[instance];
620  ftm_state_t * state = ftmStatePtr[instance];
621  status_t retStatus = STATUS_SUCCESS;
622 
623  /* Get the newest period in the MOD register */
624  ftmPeriod = FTM_HAL_GetMod(ftmBase);
625  /* Check the mode operation in FTM module */
626  if (state->ftmMode == FTM_MODE_CEN_ALIGNED_PWM)
627  {
628  ftmPeriod = (uint16_t)(ftmPeriod << 1U);
629  }
630  else if (state->ftmMode == FTM_MODE_EDGE_ALIGNED_PWM)
631  {
632  ftmPeriod = (uint16_t)(ftmPeriod + 1U);
633  }
634  else
635  {
636  retStatus = STATUS_ERROR;
637  }
638 
639  /* Check the type of update for PWM */
640  if (FTM_PWM_UPDATE_IN_DUTY_CYCLE == typeOfUpdate)
641  {
642  if ((firstEdge <= FTM_MAX_DUTY_CYCLE) && (secondEdge <= FTM_MAX_DUTY_CYCLE))
643  {
644  /* Calculate DutyCycle based of the previously calculated frequency*/
645  /* For greater resolution the DutyCycle values are in the range [0. FTM_MAX_DUTY_CYCLE]
646  * where 0 = 0% or PWM always at Low and FTM_MAX_DUTY_CYCLE = 100% or PWM always HIGH;
647  * a value of 0x4000 is equivalent of 50% DutyCycle. */
648  hwFirstEdge = (uint16_t)((ftmPeriod * firstEdge) >> FTM_DUTY_TO_TICKS_SHIFT);
649  hwSecondEdge = (uint16_t)((ftmPeriod * secondEdge) >> FTM_DUTY_TO_TICKS_SHIFT);
650  /* adjust DutyCycle if 100% value is to be achieved. */
651  if (FTM_MAX_DUTY_CYCLE == firstEdge)
652  {
653  /* If expected duty is 100% then increase by 1 the value that is to be written
654  * to Hardware so it will exceed value of period */
655  hwFirstEdge = (uint16_t)(hwFirstEdge + 1U);
656  }
657  }
658  else
659  {
660  retStatus = STATUS_ERROR;
661  }
662  }
663  else
664  {
665  if ((firstEdge <= (state->ftmPeriod)) && (secondEdge <= (state->ftmPeriod)))
666  {
667  hwFirstEdge = firstEdge;
668  hwSecondEdge = secondEdge;
669  }
670  else
671  {
672  retStatus = STATUS_ERROR;
673  }
674  }
675 
676  if (STATUS_SUCCESS == retStatus)
677  {
678  if (true == FTM_HAL_GetDualChnCombineCmd(ftmBase, chnlPairNum))
679  {
680  if (true == FTM_HAL_GetDualChnMofCombineCmd(ftmBase, chnlPairNum))
681  {
682  /* Check the clock source for FTM counter is disabled or not */
683  if (FTM_HAL_GetClockSource(ftmBase) == 0U)
684  {
685  FTM_HAL_SetChnCountVal(ftmBase, (uint8_t)(chnlPairNum * 2U), hwFirstEdge);
686  }
687  }
688  else
689  {
690  FTM_HAL_SetChnCountVal(ftmBase, (uint8_t)(chnlPairNum * 2U), hwFirstEdge);
691  }
692 
693  /* Modify the initial value in the channel (n+1) match edge */
694  FTM_HAL_SetChnCountVal(ftmBase, (uint8_t)((chnlPairNum * 2U) + 1U), hwSecondEdge);
695  }
696  else
697  {
698  /* Channel value is divided by 2 for up down counter mode to keep same duty */
699  if (true == FTM_HAL_GetCpwms(ftmBase))
700  {
701  FTM_HAL_SetChnCountVal(ftmBase, channel, (uint16_t)(hwFirstEdge >> 1U));
702  }
703  else
704  {
705  FTM_HAL_SetChnCountVal(ftmBase, channel, hwFirstEdge);
706  }
707  }
708 
709  /* Software trigger is generated to change CnV registers */
710  /* Before this please configure sync mechanism to use software trigger */
711  if (softwareTrigger)
712  {
713  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
714  }
715 
716  /* Store the PWM period in the state structure */
717  state->ftmPeriod = ftmPeriod;
718  }
719 
720  return retStatus;
721 }
722 
723 /*FUNCTION**********************************************************************
724  *
725  * Function Name : FTM_DRV_UpdatePwmPeriod
726  * Description : This function will update the new period in the frequency or
727  * in the counter value into mode register which modify the period of PWM signal
728  * on the channel output.
729  * - If the type of update in the duty cycle which is reused in FTM_DRV_UpdatePwmChannel
730  * function to convert the newValue parameters representing frequency in Hz to
731  * a period value to update the MOD register. The newValue parameter must be value
732  * between 1U and maximum is the frequency of the FTM counter.
733  * - If the type of update in ticks, this function will get value in counting to
734  * the MOD register. The newValue parameter must be value between 1U and 0xFFFFU
735  *
736  * Implements : FTM_DRV_UpdatePwmPeriod_Activity
737  *END**************************************************************************/
739  ftm_pwm_update_option_t typeOfUpdate,
740  uint32_t newValue,
741  bool softwareTrigger)
742 {
743  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
744  DEV_ASSERT(newValue != 0U);
745  uint32_t ftmPeriod = 0U;
746  FTM_Type * ftmBase = g_ftmBase[instance];
747  const ftm_state_t * state = ftmStatePtr[instance];
748  status_t retStatus = STATUS_SUCCESS;
749 
750  /* Check the type of update for period in PWM mode */
751  if (FTM_PWM_UPDATE_IN_TICKS == typeOfUpdate)
752  {
753  ftmPeriod = newValue;
754  }
755  else
756  {
757  if (newValue <= state->ftmSourceClockFrequency)
758  {
759  ftmPeriod = (uint32_t)FTM_DRV_ConvertFreqToPeriodTicks(instance, newValue);
760  }
761  else
762  {
763  retStatus = STATUS_ERROR;
764  }
765  }
766 
767  if (STATUS_SUCCESS == retStatus)
768  {
769  /* Check the ftmPeriod is invalid */
770  DEV_ASSERT(ftmPeriod <= 0xFFFFU);
771  /* Check the signal operation in which PWM mode */
773  if (FTM_MODE_CEN_ALIGNED_PWM == state->ftmMode)
774  {
775  ftmPeriod = (ftmPeriod >> 1U);
776  }
777  else
778  {
779  ftmPeriod = (ftmPeriod - 1U);
780  }
781  /* Set the new modulo value into MOD register */
782  FTM_HAL_SetMod(ftmBase, (uint16_t)(ftmPeriod));
783  /* Software trigger is generated to change MOD registers */
784  if (softwareTrigger)
785  {
786  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
787  }
788  }
789 
790  return retStatus;
791 }
792 
793 /*FUNCTION**********************************************************************
794  *
795  * Function Name : FTM_DRV_MaskOutputChannels
796  * Description : This function will mask the output of the channels and at match
797  * events will be ignored by the masked channels.
798  *
799  * Implements : FTM_DRV_MaskOutputChannels_Activity
800  *END**************************************************************************/
802  uint32_t channelsMask,
803  bool softwareTrigger)
804 {
805  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
806  FTM_Type * ftmBase = g_ftmBase[instance];
807 
808  FTM_HAL_SetOutmaskReg(ftmBase, channelsMask);
809  if (softwareTrigger)
810  {
811  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
812  }
813 
814  return STATUS_SUCCESS;
815 }
816 
817 /*FUNCTION**********************************************************************
818  *
819  * Function Name : FTM_DRV_SetInitialCounterValue
820  * Description : This function configure the initial counter value. The counter
821  * will get this value after an overflow event.
822  *
823  * Implements : FTM_DRV_SetInitialCounterValue_Activity
824  *END**************************************************************************/
826  uint16_t counterValue,
827  bool softwareTrigger)
828 {
829  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
830  FTM_Type * ftmBase = g_ftmBase[instance];
831 
832  FTM_HAL_SetCounterInitVal(ftmBase, counterValue);
833  if (softwareTrigger)
834  {
835  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
836  }
837 
838  return STATUS_SUCCESS;
839 }
840 
841 /*FUNCTION**********************************************************************
842  *
843  * Function Name : FTM_DRV_SetHalfCycleReloadPoint
844  * Description : This function configure the value of the counter which will
845  * generates an reload point.
846  *
847  * Implements : FTM_DRV_SetHalfCycleReloadPoint_Activity
848  *END**************************************************************************/
850  uint16_t reloadPoint,
851  bool softwareTrigger)
852 {
853  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
854  FTM_Type * ftmBase = g_ftmBase[instance];
855 
856  FTM_HAL_SetHalfCycleValue(ftmBase, reloadPoint);
857  if (softwareTrigger)
858  {
859  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
860  }
861 
862  return STATUS_SUCCESS;
863 }
864 
865 /*FUNCTION**********************************************************************
866  *
867  * Function Name : FTM_DRV_SetSoftwareOutputChannelValue
868  * Description : This function will force the output value of a channel to a specific value.
869  * Before using this function it's mandatory to mask the match events using
870  * FTM_DRV_MaskOutputChannels and to enable software output control using
871  * FTM_DRV_SetSoftwareOutputChannelControl.
872  *
873  * Implements : FTM_DRV_SetSoftOutChnValue_Activity
874  *END**************************************************************************/
876  uint8_t channelsValues,
877  bool softwareTrigger)
878 {
879  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
880  FTM_Type * ftmBase = g_ftmBase[instance];
881  FTM_HAL_SetAllChnSoftwareCtrlVal(ftmBase, channelsValues);
882  if (softwareTrigger)
883  {
884  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
885  }
886 
887  return STATUS_SUCCESS;
888 }
889 
890 /*FUNCTION**********************************************************************
891  *
892  * Function Name : FTM_DRV_SetSoftwareOutputChannelControl
893  * Description : This function will configure which output channel can be
894  * software controlled.
895  *
896  * Implements : FTM_DRV_SetSoftwareOutputChannelControl_Activity
897  *END**************************************************************************/
899  uint8_t channelsMask,
900  bool softwareTrigger)
901 {
902  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
903  FTM_Type * ftmBase = g_ftmBase[instance];
904  FTM_HAL_SetAllChnSoftwareCtrlCmd(ftmBase, channelsMask);
905  if (softwareTrigger)
906  {
907  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
908  }
909 
910  return STATUS_SUCCESS;
911 }
912 
913 /*FUNCTION**********************************************************************
914  *
915  * Function Name : FTM_DRV_SetInvertingControl
916  * Description : This function will configure if the second channel of a pair
917  * will be inverted or not.
918  *
919  * Implements : FTM_DRV_SetInvertingControl_Activity
920  *END**************************************************************************/
922  uint8_t channelsPairMask,
923  bool softwareTrigger)
924 {
925  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
926  FTM_Type * ftmBase = g_ftmBase[instance];
927 
928  FTM_HAL_SetInvctrlReg(ftmBase, channelsPairMask);
929  if (softwareTrigger)
930  {
931  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
932  }
933 
934  return STATUS_SUCCESS;
935 }
936 
937 /*FUNCTION**********************************************************************
938  *
939  * Function Name : FTM_DRV_SetModuloCounterValue
940  * Description : This function configure the maximum counter value.
941  *
942  * Implements : FTM_DRV_SetModuloCounterValue_Activity
943  *END**************************************************************************/
945  uint16_t counterValue,
946  bool softwareTrigger)
947 {
948  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
949  FTM_Type * ftmBase = g_ftmBase[instance];
950 
951  FTM_HAL_SetMod(ftmBase, counterValue);
952  if (softwareTrigger)
953  {
954  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
955  }
956 
957  return STATUS_SUCCESS;
958 }
959 
960 /*FUNCTION**********************************************************************
961  *
962  * Function Name : FTM_DRV_SetSync
963  * Description : This function configure the synchronization for PWM register
964  * (CnV, MOD, CINT, HCR, OUTMASK).If this function is used whit wrong parameters
965  * it's possible to generate wrong waveform. Registers synchronization need to
966  * be configured for PWM and output compare mode.
967  *
968  * Implements : FTM_DRV_SetSync_Activity
969  *END**************************************************************************/
970 status_t FTM_DRV_SetSync(uint32_t instance,
971  const ftm_pwm_sync_t * param)
972 {
973  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
974  DEV_ASSERT(param != NULL);
975  FTM_Type * ftmBase = g_ftmBase[instance];
976  status_t retStatus = STATUS_SUCCESS;
977  bool hardwareSync = param->hardwareSync0 || param->hardwareSync1 || param->hardwareSync2;
978 
979  /* Software and hardware triggers are not allowed in the same time */
980  if ((param->softwareSync && hardwareSync) || (true != (param->softwareSync || hardwareSync)))
981  {
982  retStatus = STATUS_ERROR;
983  }
984  else if (param->softwareSync)
985  {
986  /* Configure sync for OUTMASK register */
988  /* Configure sync for INVCTRL register */
990  /* Configure sync for SWOCTRL register */
992  /* Configure sync for MOD, HCR, CNTIN, and CnV registers */
994  /* Configure synchronization method (waiting next loading point or now) */
996  }
997  else
998  {
999  /* Configure sync for OUTMASK register */
1001  /* Configure sync for INVCTRL register */
1003  /* Configure sync for SWOCTRL register */
1005  /* Configure sync for MOD, HCR, CNTIN, and CnV registers */
1007  /* Configure synchronization method (waiting next loading point or now) */
1008  FTM_HAL_SetCounterHardwareSyncModeCmd(ftmBase, (bool)param->syncPoint);
1009  }
1010 
1011  if (STATUS_SUCCESS == retStatus)
1012  {
1013  /* Enhanced PWM sync is used */
1014  FTM_HAL_SetPwmSyncModeCmd(ftmBase, true);
1015  /* Configure trigger source for sync */
1016  FTM_HAL_SetHardwareSyncTriggerSrc(ftmBase, 0U, param->hardwareSync0);
1017  FTM_HAL_SetHardwareSyncTriggerSrc(ftmBase, 1U, param->hardwareSync1);
1018  FTM_HAL_SetHardwareSyncTriggerSrc(ftmBase, 2U, param->hardwareSync2);
1019  /* Configure loading points */
1020  FTM_HAL_SetMaxLoadingCmd(ftmBase, param->maxLoadingPoint);
1021  FTM_HAL_SetMinLoadingCmd(ftmBase, param->minLoadingPoint);
1022  /* Configure sync for OUTMASK register */
1023  FTM_HAL_SetOutmaskPwmSyncModeCmd(ftmBase, (bool)param->maskRegSync);
1024  /* Configure sync for INVCTRL register */
1026  /* Configure sync for SWOCTRL register */
1028  /* Configure sync for MOD, HCR, CNTIN, and CnV registers */
1030  /* Configure if FTM clears TRIGj (j=0,1,2) when the hardware trigger j is detected. */
1032  }
1033 
1034  return retStatus;
1035 }
1036 
1037 /*FUNCTION**********************************************************************
1038  *
1039  * Function Name : FTM_DRV_InitOutputCompare
1040  * Description : Configures the FTM to generate timed pulses
1041  * When the FTM counter matches the value of compareVal argument (this is
1042  * written into CnV register), the channel output is changed based on what is specified
1043  * in the compareMode argument.
1044  *
1045  * Implements : FTM_DRV_InitOutputCompare_Activity
1046  *END**************************************************************************/
1048  const ftm_output_cmp_param_t * param)
1049 {
1050  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1051  DEV_ASSERT(param != NULL);
1052  FTM_Type * ftmBase = g_ftmBase[instance];
1053  uint8_t index = 0U;
1054  uint8_t hwChannel = 0U;
1055  uint8_t chnlPairNum = 0U;
1056  ftm_state_t * state = ftmStatePtr[instance];
1057  status_t retStatus = STATUS_SUCCESS;
1058 
1059  if ((NULL != state) && (FTM_MODE_NOT_INITIALIZED == state->ftmMode))
1060  {
1062  FTM_HAL_SetCpwms(ftmBase, false);
1063  /* Clear the overflow flag */
1064  FTM_HAL_ClearTimerOverflow(ftmBase);
1065  FTM_HAL_SetCounterInitVal(ftmBase, 0U);
1066  FTM_HAL_SetMod(ftmBase, param->maxCountValue);
1067  FTM_HAL_SetCounter(ftmBase, 0U);
1068  FTM_HAL_SetQuadDecoderCmd(ftmBase, false);
1069  /* Use FTM as counter, disable all the channels */
1070  for (index = 0U; index < param->nNumOutputChannels; index++)
1071  {
1072  hwChannel = param->outputChannelConfig[index].hwChannelId;
1073  chnlPairNum = (uint8_t)(hwChannel >> 1U);
1074  FTM_HAL_SetDualChnMofCombineCmd(ftmBase, chnlPairNum, false);
1075  FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairNum, false);
1076  FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum, false);
1077  /* Set Channel Output mode */
1078  FTM_HAL_SetChnEdgeLevel(ftmBase, hwChannel, (uint8_t)(param->outputChannelConfig[index].chMode));
1079  /* Enter counter mode for all configured channels */
1080  FTM_HAL_SetChnMSnBAMode(ftmBase, hwChannel, 1U);
1081  /* Write initial count value for all channels */
1082  FTM_HAL_SetChnCountVal(ftmBase, hwChannel, param->outputChannelConfig[index].comparedValue);
1083  /* Enable channel output */
1084  FTM_HAL_EnablePwmChannelOutputs(ftmBase, hwChannel);
1085  /* Enable the generation a trigger on chip module */
1086  FTM_HAL_SetChnTriggerCmd(ftmBase, hwChannel, param->outputChannelConfig[index].enableExternalTrigger);
1087  }
1088 
1089  /* Set software trigger */
1090  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
1091  state->ftmMode = param->mode;
1092  /* Set clock source to start the counter */
1093  FTM_HAL_SetClockSource(ftmBase, state->ftmClockSource);
1094  }
1095  else
1096  {
1097  retStatus = STATUS_ERROR;
1098  }
1099 
1100  return retStatus;
1101 }
1102 
1103 /*FUNCTION**********************************************************************
1104  *
1105  * Function Name : FTM_DRV_DeinitOutputCompare
1106  * Description : Disables compare match output control and clears FTM timer configuration
1107  *
1108  * Implements : FTM_DRV_DeinitOutputCompare_Activity
1109  *END**************************************************************************/
1111  const ftm_output_cmp_param_t * param)
1112 {
1113  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1114  DEV_ASSERT(param != NULL);
1115  FTM_Type * ftmBase = g_ftmBase[instance];
1116  uint8_t index = 0U;
1117  uint8_t hwChannel = 0U;
1118  ftm_state_t * state = ftmStatePtr[instance];
1119 
1120  /* Stop the FTM counter */
1122  /* Clear the overflow flag */
1123  FTM_HAL_ClearTimerOverflow(ftmBase);
1124  FTM_HAL_SetCounterInitVal(ftmBase, 0U);
1125  for (index = 0U; index < param->nNumOutputChannels; index++)
1126  {
1127  hwChannel = param->outputChannelConfig[index].hwChannelId;
1128  /* Disable Channel Output mode */
1129  FTM_HAL_SetChnEdgeLevel(ftmBase, hwChannel, (uint8_t)0U);
1130  /* Write initial count value for all channels to 0xFFFF */
1131  FTM_HAL_SetChnCountVal(ftmBase, hwChannel, 0U);
1132  /* Disable channel output */
1133  FTM_HAL_DisablePwmChannelOutputs(ftmBase, hwChannel);
1134  }
1135 
1136  /* Clear out the registers */
1137  FTM_HAL_SetMod(ftmBase, 0U);
1138  FTM_HAL_SetCounter(ftmBase, 0U);
1140 
1141  return STATUS_SUCCESS;
1142 }
1143 
1144 /*FUNCTION**********************************************************************
1145  *
1146  * Function Name : FTM_DRV_UpdateOutputCompareChannel
1147  * Description : Sets the next compare match value on the given channel starting
1148  * from the current counter value.
1149  *
1150  * Implements : FTM_DRV_UpdateOutputCompareChannel_Activity
1151  *END**************************************************************************/
1153  uint8_t channel,
1154  uint16_t nextComparematchValue,
1156  bool softwareTrigger)
1157 {
1158  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1160  uint16_t counterValue = FTM_HAL_GetCounter(g_ftmBase[instance]);
1161  uint16_t compareValue = 0U;
1162  uint16_t maxCounterValue;
1163  FTM_Type * ftmBase = g_ftmBase[instance];
1164 
1165  if (update == FTM_RELATIVE_VALUE)
1166  {
1167  maxCounterValue = FTM_HAL_GetMod(g_ftmBase[instance]);
1168  /* Configure channel compare register */
1169  if ((uint16_t)(counterValue + nextComparematchValue) > maxCounterValue)
1170  {
1171  compareValue = (uint16_t)(nextComparematchValue - (maxCounterValue - counterValue));
1172  }
1173  else
1174  {
1175  compareValue = (uint16_t)(counterValue + nextComparematchValue);
1176  }
1177  }
1178  else
1179  {
1180  compareValue = nextComparematchValue;
1181  }
1182 
1183  /* Set CnV value and use software trigger for sync */
1184  FTM_HAL_SetChnCountVal(g_ftmBase[instance], channel, compareValue);
1185  if (softwareTrigger)
1186  {
1187  FTM_HAL_SetSoftwareTriggerCmd(ftmBase, true);
1188  }
1189 
1190  return STATUS_SUCCESS;
1191 }
1192 
1193 /*FUNCTION**********************************************************************
1194  *
1195  * Function Name : FTM_DRV_InitInputCapture
1196  * Description : Configures Channel Input Capture for either getting time-stamps on edge detection
1197  * or on signal measurement . When the edge specified in the captureMode
1198  * argument occurs on the channel the FTM counter is captured into the CnV register.
1199  * The user will have to read the CnV register separately to get this value. The filter
1200  * function is disabled if the filterVal argument passed in is 0. The filter function
1201  * is available only on channels 0,1,2,3.
1202  *
1203  * Implements : FTM_DRV_InitInputCapture_Activity
1204  *END**************************************************************************/
1206  const ftm_input_param_t * param)
1207 {
1208  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1209  DEV_ASSERT(param != NULL);
1210  FTM_Type * ftmBase = g_ftmBase[instance];
1211  uint8_t chnlPairNum = 0U;
1212  uint8_t index = 0U;
1213  uint8_t hwChannel = 0U;
1214  ftm_signal_measurement_mode_t measurementType;
1215  ftm_state_t * state = ftmStatePtr[instance];
1216  status_t retStatus = STATUS_SUCCESS;
1217 
1218  if ((NULL != state) && (FTM_MODE_NOT_INITIALIZED == state->ftmMode))
1219  {
1221  FTM_HAL_SetCounterInitVal(ftmBase, 0U);
1222  FTM_HAL_SetMod(ftmBase, param->nMaxCountValue);
1223  FTM_HAL_SetCpwms(ftmBase, false);
1224  /* Disable the combine mode */
1225  FTM_HAL_SetDualChnMofCombineCmd(ftmBase, chnlPairNum, false);
1226  FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairNum, false);
1227 
1228  for (index = 0U; index < param->nNumChannels; index++)
1229  {
1230  hwChannel = param->inputChConfig[index].hwChannelId;
1231  chnlPairNum = (uint8_t)(hwChannel >> 1U);
1232  /* Save in state structure user define handlers */
1233  state->channelsCallbacksParams[hwChannel] = param->inputChConfig[index].channelsCallbacksParams;
1234  state->channelsCallbacks[hwChannel] = param->inputChConfig[index].channelsCallbacks;
1235  /* Enable filtering for input channels */
1236  if (hwChannel < CHAN4_IDX)
1237  {
1238  if (true == param->inputChConfig[index].filterEn)
1239  {
1240  FTM_HAL_SetChnInputCaptureFilter(ftmBase, hwChannel, (uint8_t)param->inputChConfig[index].filterValue);
1241  }
1242  else
1243  {
1244  FTM_HAL_SetChnInputCaptureFilter(ftmBase, hwChannel, 0U);
1245  }
1246  }
1247 
1248  if (FTM_EDGE_DETECT == param->inputChConfig[index].inputMode)
1249  {
1250  /* Disable the dual edge mode */
1251  FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum, false);
1252  /* Set input capture mode */
1253  FTM_HAL_SetChnMSnBAMode(ftmBase, hwChannel, 0U);
1254  /* Check if no edge is selected */
1256  /* Set the event which will generate the interrupt */
1257  FTM_HAL_SetChnEdgeLevel(ftmBase, hwChannel, (uint8_t)param->inputChConfig[index].edgeAlignement);
1258  /* Enable interrupt request for the current channel */
1259  FTM_HAL_EnableChnInt(ftmBase, hwChannel);
1260  INT_SYS_EnableIRQ(g_ftmIrqId[instance][hwChannel]);
1261  }
1262  else if (FTM_SIGNAL_MEASUREMENT == param->inputChConfig[index].inputMode)
1263  {
1264  /* Enable the dual edge mode */
1265  FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum, true);
1266  /* Enable dual edge input capture */
1267  FTM_HAL_SetDualChnDecapCmd(ftmBase, chnlPairNum, true);
1268  /* If continuous mode is set*/
1269  if (true == param->inputChConfig[index].continuousModeEn)
1270  {
1271  /* Set MSnA and MSnB bit*/
1272  FTM_HAL_SetChnMSnBAMode(ftmBase, hwChannel, 3U);
1273  }
1274  else
1275  {
1276  /* Clear MSnA and Set MSnB bit*/
1277  FTM_HAL_SetChnMSnBAMode(ftmBase, hwChannel, 2U);
1278  }
1279 
1280  measurementType = param->inputChConfig[index].measurementType;
1281  /* Check If want to measure a pulse width or period of the signal */
1282  if ((FTM_PERIOD_ON_MEASUREMENT == measurementType) || (FTM_RISING_EDGE_PERIOD_MEASUREMENT== measurementType))
1283  {
1284  FTM_HAL_SetChnEdgeLevel(ftmBase, hwChannel, 1U);
1285  if (FTM_PERIOD_ON_MEASUREMENT == measurementType)
1286  {
1287  /* Measure time between rising and falling edge - positive duty */
1288  FTM_HAL_SetChnEdgeLevel(ftmBase, (uint8_t)(hwChannel + 1U), 2U);
1289  }
1290  else
1291  {
1292  /* If channel (n) is configured to capture falling edges (ELS(n)B:ELS(n)A = 0:1)
1293  * then channel (n+1) also captures falling edges (ELS(n+1)B:ELS(n+1)A = 0:1) */
1294  FTM_HAL_SetChnEdgeLevel(ftmBase, (uint8_t)(hwChannel + 1U), 1U);
1295  }
1296  }
1297  else if ((FTM_PERIOD_OFF_MEASUREMENT == measurementType) || (FTM_FALLING_EDGE_PERIOD_MEASUREMENT == measurementType))
1298  {
1299  FTM_HAL_SetChnEdgeLevel(ftmBase, hwChannel, 2U);
1300  if (FTM_PERIOD_OFF_MEASUREMENT == measurementType)
1301  {
1302  /* Measure time between falling and rising edge - negative duty */
1303  FTM_HAL_SetChnEdgeLevel(ftmBase, (uint8_t)(hwChannel + 1U), 1U);
1304  }
1305  else
1306  {
1307  /* If channel (n) is configured to capture rising edges (ELS(n)B:ELS(n)A = 1:0) than
1308  * channel (n+1) is setup to capture also raising edges (ELS(n+1)B:ELS(n+1)A = 1:0) */
1309  FTM_HAL_SetChnEdgeLevel(ftmBase, (uint8_t)(hwChannel + 1U), 2U);
1310  }
1311  }
1312  else
1313  {
1314  retStatus = STATUS_ERROR;
1315  break;
1316  }
1317 
1318  /* Enable the interrupt request for the channel which will indicate that the measurement is done. */
1319  FTM_HAL_EnableChnInt(ftmBase, (uint8_t)(hwChannel + 1U));
1320  INT_SYS_EnableIRQ(g_ftmIrqId[instance][hwChannel]);
1321  }
1322  else
1323  {
1324  /* Do nothing */
1325  }
1326  }
1327 
1328  if (STATUS_SUCCESS == retStatus)
1329  {
1331  /* Set clock source to start the counter */
1332  FTM_HAL_SetClockSource(ftmBase, state->ftmClockSource);
1333  }
1334  }
1335  else
1336  {
1337  retStatus = STATUS_ERROR;
1338  }
1339 
1340  return retStatus;
1341 }
1342 
1343 /*FUNCTION**********************************************************************
1344  *
1345  * Function Name : FTM_DRV_DeinitInputCapture
1346  * Description : Disables Channel Input Capture
1347  *
1348  * Implements : FTM_DRV_DeinitInputCapture_Activity
1349  *END**************************************************************************/
1351  const ftm_input_param_t * param)
1352 {
1353  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1354  DEV_ASSERT(param != NULL);
1355  FTM_Type * ftmBase = g_ftmBase[instance];
1356  uint8_t chnlPairNum = 0U;
1357  uint8_t index = 0U;
1358  uint8_t hwChannel = 0U;
1359  ftm_state_t * state = ftmStatePtr[instance];
1360 
1361  /* FTM counter is disabled */
1363  FTM_HAL_SetCounterInitVal(ftmBase, 0U);
1364  FTM_HAL_SetMod(ftmBase, 0xFFFFU);
1365  FTM_HAL_SetCpwms(ftmBase, false);
1366  for (index = 0U; index < param->nNumChannels; index++)
1367  {
1368  hwChannel = param->inputChConfig[index].hwChannelId;
1369  chnlPairNum = (uint8_t)(hwChannel >> 1U);
1370  /* Disable filtering for input channels */
1371  if (hwChannel < CHAN4_IDX)
1372  {
1373  FTM_HAL_SetChnInputCaptureFilter(ftmBase, hwChannel, 0U);
1374  }
1375 
1376  FTM_HAL_SetDualChnCombineCmd(ftmBase, chnlPairNum, false);
1377  FTM_HAL_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum, false);
1378  FTM_HAL_SetChnEdgeLevel(ftmBase, hwChannel, (uint8_t)0U);
1379  FTM_HAL_DisableChnInt(ftmBase, hwChannel);
1380  }
1381 
1382  /* Clear Callbacks function from the state structure */
1383  for (index = 0U; index < FEATURE_FTM_CHANNEL_COUNT; index++)
1384  {
1385  state->channelsCallbacksParams[index] = NULL;
1386  state->channelsCallbacks[index] = NULL;
1387  }
1388 
1390 
1391  return STATUS_SUCCESS;
1392 }
1393 
1394 /*FUNCTION**********************************************************************
1395  *
1396  * Function Name : FTM_DRV_GetInputCaptureMeasurement
1397  * Description : This function is used to calculate the measurement and/or time stamps values
1398  * which are read from the C(n, n+1)V registers and stored to the static buffers.
1399  *
1400  * Implements : FTM_DRV_GetInputCaptureMeasurement_Activity
1401  *END**************************************************************************/
1402 uint16_t FTM_DRV_GetInputCaptureMeasurement(uint32_t instance,
1403  uint8_t channel)
1404 {
1405  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1407  const ftm_state_t * state = ftmStatePtr[instance];
1408 
1409  return state->measurementResults[channel];
1410 }
1411 
1412 /*FUNCTION**********************************************************************
1413  *
1414  * Function Name : FTM_DRV_StartNewSignalMeasurement
1415  * Description : This function starts new Signal Measurements on a dual input compare channel
1416  * that is configured as single-shot measurement.
1417  *
1418  * Implements : FTM_DRV_StartNewSignalMeasurement_Activity
1419  *END**************************************************************************/
1421  uint8_t channel)
1422 {
1423  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1425  /* Clear CH(n)F and CH(n+1)F flags and Set DECAP bit */
1426  FTM_Type * ftmBase = g_ftmBase[instance];
1427  uint8_t chnlPairNum = (uint8_t)(channel >> 1U);
1428 
1429  /* Get channel mode */
1431  {
1432  if (FTM_HAL_GetDualChnCombineCmd(ftmBase, chnlPairNum))
1433  {
1434  /* Clear event flags for channel n and n + 1 */
1435  FTM_HAL_ClearChnEventFlag(ftmBase, (uint8_t)(channel + 1U));
1436  FTM_HAL_ClearChnEventFlag(ftmBase, channel);
1437  /* Set DECAP bit to start measurement */
1438  FTM_HAL_SetDualChnDecapCmd(ftmBase, chnlPairNum, true);
1439  }
1440  }
1441  else
1442  {
1443  /* Nothing to do */
1444  }
1445 
1446  return STATUS_SUCCESS;
1447 }
1448 
1449 /*FUNCTION**********************************************************************
1450  *
1451  * Function Name : FTM_DRV_QuadDecodeStart
1452  * Description : Configures the parameters needed and activates quadrature
1453  * decode mode.
1454  *
1455  * Implements : FTM_DRV_QuadDecodeStart_Activity
1456  *END**************************************************************************/
1458  const ftm_quad_decode_config_t * config)
1459 {
1460  DEV_ASSERT((instance == FTM1_IDX) || (instance == FTM2_IDX));
1461  DEV_ASSERT(config != NULL);
1462  FTM_Type * ftmBase = g_ftmBase[instance];
1463  ftm_state_t * state = ftmStatePtr[instance];
1464  status_t retStatus = STATUS_SUCCESS;
1465 
1466  if ((NULL != state) && (FTM_MODE_NOT_INITIALIZED == state->ftmMode))
1467  {
1468  /* Disable Quadrature Decoder */
1469  FTM_HAL_SetQuadDecoderCmd(ftmBase, false);
1471  /* Configure Quadrature Decoder */
1472  /* Set decoder mode Speed and direction or Phase A and Phase B encoding */
1473  FTM_HAL_SetQuadMode(ftmBase, config->mode);
1474  /* Set filter state for Phase A (enable/disable) */
1476  /* Set Phase A filter value if phase filter is enabled */
1477  if (config->phaseAConfig.phaseInputFilter)
1478  {
1480  }
1481 
1482  /* Set filter state for Phase B (enable/disable) */
1484  /* Set Phase B filter value if phase filter is enabled */
1485  if (config->phaseBConfig.phaseInputFilter)
1486  {
1488  }
1489 
1490  /* Set polarity for Phase A and Phase B */
1493  /* Configure counter (initial value and maximum value) */
1494  FTM_HAL_SetCounterInitVal(ftmBase, config->initialVal);
1495  FTM_HAL_SetMod(ftmBase, config->maxVal);
1496  FTM_HAL_SetCounter(ftmBase, config->initialVal);
1497  /* Enable Quadrature Decoder */
1498  FTM_HAL_SetQuadDecoderCmd(ftmBase, true);
1500  }
1501  else
1502  {
1503  retStatus = STATUS_ERROR;
1504  }
1505 
1506  return retStatus;
1507 }
1508 
1509 /*FUNCTION**********************************************************************
1510  *
1511  * Function Name : FTM_DRV_QuadDecodeStop
1512  * Description : De-activates quadrature decoder mode.
1513  *
1514  * Implements : FTM_DRV_QuadDecodeStop_Activity
1515  *END**************************************************************************/
1517 {
1518  DEV_ASSERT((instance == FTM1_IDX) || (instance == FTM2_IDX));
1519  FTM_Type * ftmBase = g_ftmBase[instance];
1520  ftm_state_t * state = ftmStatePtr[instance];
1521 
1522  /* Disable Quadrature decoder */
1523  FTM_HAL_SetQuadDecoderCmd(ftmBase, false);
1525 
1526  return STATUS_SUCCESS;
1527 }
1528 
1529 /*FUNCTION**********************************************************************
1530  *
1531  * Function Name : FTM_DRV_QuadGetState
1532  * Description : Return the current quadrature decoder state
1533  * (counter value, overflow flag and overflow direction)
1534  *
1535  * Implements : FTM_DRV_QuadGetState_Activity
1536  *END**************************************************************************/
1538 {
1539  DEV_ASSERT((instance == FTM1_IDX) || (instance == FTM2_IDX));
1540  FTM_Type const * ftmBase = g_ftmBase[instance];
1542 
1543  state.counterDirection = FTM_HAL_GetQuadDir(ftmBase);
1545  state.overflowFlag = FTM_HAL_HasTimerOverflowed(ftmBase);
1546  state.counter = FTM_HAL_GetCounter(ftmBase);
1547 
1548  return state;
1549 }
1550 
1551 /*FUNCTION**********************************************************************
1552  *
1553  * Function Name : FTM_DRV_GetFrequency
1554  * Description : Retrieves the frequency of the clock source feeding the FTM counter.
1555  * Function will return a 0 if no clock source is selected and the FTM counter is disabled.
1556  * The returned value is clock sources for the FTM counter.
1557  *
1558  * Implements : FTM_DRV_GetFrequency_Activity
1559  *END**************************************************************************/
1560 uint32_t FTM_DRV_GetFrequency(uint32_t instance)
1561 {
1562  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1563  PCC_Type const * pccBase = PCC_BASE_PTRS;
1564  FTM_Type const * ftmBase = g_ftmBase[instance];
1565  clock_names_t ftmClkName;
1566  peripheral_clock_source_t clockSelect;
1567  uint8_t clkPs;
1568  uint32_t frequency = 0U;
1569  const ftm_state_t * state = ftmStatePtr[instance];
1570  clkPs = (uint8_t)(1U << FTM_HAL_GetClockPs(ftmBase));
1571 
1572  switch (state->ftmClockSource)
1573  {
1575  clockSelect = PCC_HAL_GetClockSourceSel(pccBase, g_ftmExtClockSel[instance][1]);
1576  if (CLK_SRC_OFF == clockSelect)
1577  {
1578  ftmClkName = g_ftmExtClockSel[instance][0];
1579  }
1580  else
1581  {
1582  ftmClkName = g_ftmExtClockSel[instance][1];
1583  }
1584 
1585  /* Get the clock frequency value */
1586  (void)CLOCK_SYS_GetFreq(ftmClkName, &frequency);
1587  break;
1589  /* Get the clock frequency value */
1590  (void)CLOCK_SYS_GetFreq(SIM_RTCCLK_CLOCK, &frequency);
1591  break;
1593  /* Get the clock frequency value */
1594  (void)CLOCK_SYS_GetFreq(CORE_CLOCK, &frequency);
1595  break;
1596  default:
1597  /* Nothing to do */
1598  break;
1599  }
1600 
1601  return (uint32_t)(frequency / clkPs);
1602 }
1603 
1604 /*FUNCTION**********************************************************************
1605  *
1606  * Function Name : FTM_DRV_ConvertFreqToPeriodTicks
1607  * Description : This function converts the input parameters representing
1608  * frequency in Hz to a period value in ticks needed by the hardware timer.
1609  *
1610  * Implements : FTM_DRV_ConvertFreqToPeriodTicks_Activity
1611  *END**************************************************************************/
1612 uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance,
1613  uint32_t freqencyHz)
1614 {
1615  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
1616  DEV_ASSERT(freqencyHz != 0U);
1617  uint32_t uFTMhz;
1618  const ftm_state_t * state = ftmStatePtr[instance];
1619  uFTMhz = state->ftmSourceClockFrequency;
1620 
1621  return (uint16_t)(uFTMhz / freqencyHz);
1622 }
1623 
1624 /* Implementation of FTM0_Ch0_Ch1_IRQHandler master handler named in startup code. */
1626 {
1627  FTM_DRV_IrqHandler(0U, 0U);
1628 }
1629 
1630 /* Implementation of FTM0_Ch2_Ch3_IRQHandler master handler named in startup code. */
1632 {
1633  FTM_DRV_IrqHandler(0U, 1U);
1634 }
1635 
1636 /* Implementation of FTM0_Ch4_Ch5_IRQHandler master handler named in startup code. */
1638 {
1639  FTM_DRV_IrqHandler(0U, 2U);
1640 }
1641 
1642 /* Implementation of FTM0_Ch6_Ch7_IRQHandler master handler named in startup code. */
1644 {
1645  FTM_DRV_IrqHandler(0U, 3U);
1646 }
1647 
1648 /* Implementation of FTM1_Ch0_Ch1_IRQHandler master handler named in startup code. */
1650 {
1651  FTM_DRV_IrqHandler(1U, 0U);
1652 }
1653 
1654 /* Implementation of FTM1_Ch2_Ch3_IRQHandler master handler named in startup code. */
1656 {
1657  FTM_DRV_IrqHandler(1U, 1U);
1658 }
1659 
1660 /* Implementation of FTM1_Ch4_Ch5_IRQHandler master handler named in startup code. */
1662 {
1663  FTM_DRV_IrqHandler(1U, 2U);
1664 }
1665 
1666 /* Implementation of FTM1_Ch6_Ch7_IRQHandler master handler named in startup code. */
1668 {
1669  FTM_DRV_IrqHandler(1U, 3U);
1670 }
1671 
1672 /* Implementation of FTM2_Ch0_Ch1_IRQHandler master handler named in startup code. */
1674 {
1675  FTM_DRV_IrqHandler(2U, 0U);
1676 }
1677 
1678 /* Implementation of FTM2_Ch2_Ch3_IRQHandler master handler named in startup code. */
1680 {
1681  FTM_DRV_IrqHandler(2U, 1U);
1682 }
1683 
1684 /* Implementation of FTM2_Ch4_Ch5_IRQHandler master handler named in startup code. */
1686 {
1687  FTM_DRV_IrqHandler(2U, 2U);
1688 }
1689 
1690 /* Implementation of FTM2_Ch6_Ch7_IRQHandler master handler named in startup code. */
1692 {
1693  FTM_DRV_IrqHandler(2U, 3U);
1694 }
1695 
1696 /* Implementation of FTM3_Ch0_Ch1_IRQHandler master handler named in startup code. */
1698 {
1699  FTM_DRV_IrqHandler(3U, 0U);
1700 }
1701 
1702 /* Implementation of FTM3_Ch2_Ch3_IRQHandler master handler named in startup code. */
1704 {
1705  FTM_DRV_IrqHandler(3U, 1U);
1706 }
1707 
1708 /* Implementation of FTM3_Ch4_Ch5_IRQHandler master handler named in startup code. */
1710 {
1711  FTM_DRV_IrqHandler(3U, 2U);
1712 }
1713 
1714 /* Implementation of FTM3_Ch6_Ch7_IRQHandler master handler named in startup code. */
1716 {
1717  FTM_DRV_IrqHandler(3U, 3U);
1718 }
1719 
1720 static void FTM_DRV_IrqHandler(uint32_t instance,
1721  uint8_t channelPair)
1722 {
1723  const ftm_state_t * state = ftmStatePtr[instance];
1724  switch (state->ftmMode)
1725  {
1727  FTM_DRV_InputCaptureHandler(instance, channelPair);
1728  break;
1729  default:
1730  /* Nothing to do */
1731  break;
1732  }
1733 }
1734 
1735 static void FTM_DRV_InputCaptureHandler(uint32_t instance,
1736  uint8_t channelPair)
1737 {
1738  ftm_state_t * state = ftmStatePtr[instance];
1739  FTM_Type * ftmBase = g_ftmBase[instance];
1740 
1741  /* Verify the mode for current pair of channels */
1742  if (FTM_HAL_GetDualEdgeCaptureBit(ftmBase, channelPair))
1743  {
1744  /* Dual edge input capture case */
1745  uint16_t first_event_time = FTM_HAL_GetChnCountVal(ftmBase, (uint8_t)(channelPair << 1U));
1746  uint16_t second_event_time = FTM_HAL_GetChnCountVal(ftmBase, (uint8_t)((channelPair << 1U) + 1U));
1747  if (second_event_time < first_event_time)
1748  {
1749  /* Measurement when overflow occurred */
1750  state->measurementResults[channelPair << 1U] = (uint16_t)(second_event_time + (FTM_HAL_GetMod(ftmBase) - first_event_time));
1751  }
1752  else
1753  {
1754  /* Measurement when overflow doesn't occurred */
1755  state->measurementResults[channelPair << 1U] = (uint16_t)(second_event_time - first_event_time);
1756  }
1757 
1758  /* Clear flags for channels n and n+1 */
1759  FTM_HAL_ClearChnEventFlag(ftmBase, (uint8_t)(channelPair << 1U));
1760  FTM_HAL_ClearChnEventFlag(ftmBase, (uint8_t)((channelPair << 1U) + 1U));
1761  /* If the callback is define use it */
1762  if ((state->channelsCallbacks[(channelPair << 1U)]) != NULL)
1763  {
1764  state->channelsCallbacks[(channelPair << 1U)](state->channelsCallbacksParams[channelPair << 1U]);
1765  }
1766  }
1767  else
1768  {
1769  /* To get the channel interrupt source the both channels flag must be checked */
1770  if (FTM_HAL_HasChnEventOccurred(ftmBase, (uint8_t)(channelPair << 1U)))
1771  {
1772  /* Get the time stamp of the event */
1773  state->measurementResults[channelPair << 1U] = FTM_HAL_GetChnCountVal(ftmBase, (uint8_t)(channelPair << 1U));
1774  /* Clear the flag for C(n) channel */
1775  FTM_HAL_ClearChnEventFlag(ftmBase, (uint8_t)(channelPair << 1U));
1776  /* If the callback is define use it */
1777  if ((state->channelsCallbacks[channelPair << 1U]) != NULL)
1778  {
1779  state->channelsCallbacks[channelPair << 1U](state->channelsCallbacksParams[channelPair << 1U]);
1780  }
1781  }
1782  else
1783  {
1784  /* Get the time stamp of the event */
1785  state->measurementResults[(channelPair << 1U) + 1U] = FTM_HAL_GetChnCountVal(ftmBase, (uint8_t)((channelPair << 1U) + 1U));
1786  /* Clear the flag for C(n+1) channel */
1787  FTM_HAL_ClearChnEventFlag(ftmBase, (uint8_t)((channelPair << 1U) + 1U));
1788  /* If the callback is define use it */
1789  if ((state->channelsCallbacks[(channelPair << 1U) + 1U]) != NULL)
1790  {
1791  state->channelsCallbacks[(channelPair << 1U) + 1U](state->channelsCallbacksParams[(channelPair << 1U) + 1U]);
1792  }
1793  }
1794  }
1795 }
1796 
1797 /*******************************************************************************
1798  * EOF
1799  ******************************************************************************/
static void FTM_HAL_SetInitTriggerCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the generation of the trigger when the FTM counter is equal to the CNTIN register...
Definition: ftm_hal.h:1973
static void FTM_DRV_InputCaptureHandler(uint32_t instance, uint8_t channelPair)
Definition: ftm_driver.c:1735
ftm_reg_update_t initCounterSync
Definition: ftm_driver.h:189
#define FTM_Reload_IRQS
Definition: S32K144.h:4062
static void FTM_HAL_SetDualChnPwmSyncCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the FTM peripheral timer channel pair counter PWM sync.
Definition: ftm_hal.h:1698
ftm_pwm_sync_t syncMethod
Definition: ftm_driver.h:202
status_t FTM_DRV_SetInvertingControl(uint32_t instance, uint8_t channelsPairMask, bool softwareTrigger)
This function will configure if the second channel of a pair will be inverted or not.
Definition: ftm_driver.c:921
static void FTM_HAL_SetSwoctrlPwmSyncModeCmd(FTM_Type *const ftmBase, ftm_reg_update_t mode)
Sets the SWOCTRL register PWM synchronization mode.
Definition: ftm_hal.h:2886
static void FTM_HAL_SetExtDeadtimeValue(FTM_Type *const ftmBase, uint8_t value)
Sets the FTM extended dead-time value.
Definition: ftm_hal.h:1916
status_t FTM_DRV_InitCounter(uint32_t instance, const ftm_timer_param_t *timer)
Initialize the FTM counter.
Definition: ftm_driver.c:228
FlexTimer state structure of the driver.
Definition: ftm_driver.h:156
void FTM3_Ch0_Ch1_IRQHandler(void)
Definition: ftm_driver.c:1697
static void FTM_HAL_SetQuadDecoderCmd(FTM_Type *const ftmBase, bool enable)
Enables the channel quadrature decoder.
Definition: ftm_hal.h:2108
static void FTM_HAL_SetChnOutputPolarityCmd(FTM_Type *const ftmBase, uint8_t channel, ftm_polarity_t polarity)
Sets the FTM peripheral timer channel output polarity.
Definition: ftm_hal.h:1299
ftm_edge_alignment_mode_t edgeAlignement
Definition: ftm_driver.h:334
static void FTM_HAL_DisableChnInt(FTM_Type *const ftmBase, uint8_t channel)
Disables the FTM peripheral timer channel(n) interrupt.
Definition: ftm_hal.h:1001
#define FTM_IRQS
Definition: S32K144.h:4056
ftm_channel_event_callback_t channelsCallbacks
Definition: ftm_driver.h:340
static void FTM_HAL_SetDualChnMofCombineCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables the FTM peripheral timer channel modified combine mode.
Definition: ftm_hal.h:1644
ftm_bdm_mode_t BDMMode
Definition: ftm_driver.h:208
bool hardwareSync2
Definition: ftm_driver.h:180
static void FTM_HAL_SetQuadPhaseAFilterCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the phase A input filter.
Definition: ftm_hal.h:2131
Configuration structure that the user needs to set.
Definition: ftm_driver.h:200
static void FTM_HAL_SetOutmaskPwmSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Determines when the OUTMASK register is updated with the value of its buffer.
Definition: ftm_hal.h:1578
uint16_t ftmPeriod
Definition: ftm_driver.h:160
uint32_t uFrequencyHZ
Definition: ftm_driver.h:306
const IRQn_Type g_ftmReloadIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_driver.c:76
uint16_t initialValue
Definition: ftm_driver.h:223
static void FTM_HAL_EnablePwmChannelOutputs(FTM_Type *const ftmBase, uint8_t channel)
Enable PWM channel Outputs.
Definition: ftm_hal.h:555
void FTM_HAL_SetChnTriggerCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the generation of the FTM peripheral timer channel trigger when the FTM counter i...
Definition: ftm_hal.c:106
status_t FTM_DRV_InitOutputCompare(uint32_t instance, const ftm_output_cmp_param_t *param)
Configures the FTM to generate timed pulses(Output compare mode).
Definition: ftm_driver.c:1047
ftm_config_mode_t mode
Definition: ftm_driver.h:377
void FTM2_Ch4_Ch5_IRQHandler(void)
Definition: ftm_driver.c:1685
static void FTM_HAL_SetDualChnFaultCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables the FTM peripheral timer channel pair fault control.
Definition: ftm_hal.h:1671
FlexTimer driver input capture parameters.
Definition: ftm_driver.h:348
status_t FTM_DRV_UpdatePwmPeriod(uint32_t instance, ftm_pwm_update_option_t typeOfUpdate, uint32_t newValue, bool softwareTrigger)
This function will update the new period in the frequency or in the counter value into mode register ...
Definition: ftm_driver.c:738
static void FTM_HAL_SetPwmSyncMode(FTM_Type *const ftmBase, bool enable)
Sets the FTM peripheral timer sync mode.
Definition: ftm_hal.h:1516
const ftm_input_ch_param_t * inputChConfig
Definition: ftm_driver.h:352
FTM_Type *const g_ftmBase[FTM_INSTANCE_COUNT]
Table of base addresses for FTM instances.
Definition: ftm_driver.c:70
static void FTM_HAL_SetBdmMode(FTM_Type *const ftmBase, ftm_bdm_mode_t val)
Sets the BDM mode.
Definition: ftm_hal.h:2663
void FTM2_Ch0_Ch1_IRQHandler(void)
Definition: ftm_driver.c:1673
static void FTM_HAL_SetSwoctrlHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets the sync mode for the FTM SWOCTRL register when using a hardware trigger.
Definition: ftm_hal.h:2694
static void FTM_HAL_SetChnEdgeLevel(FTM_Type *const ftmBase, uint8_t channel, uint8_t level)
Sets the FTM peripheral timer channel edge level.
Definition: ftm_hal.h:803
status_t FTM_DRV_StartNewSignalMeasurement(uint32_t instance, uint8_t channel)
Starts new single-shot signal measurement of the given channel.
Definition: ftm_driver.c:1420
status_t FTM_DRV_QuadDecodeStop(uint32_t instance)
De-activates the quadrature decode mode.
Definition: ftm_driver.c:1516
status_t FTM_DRV_DeinitOutputCompare(uint32_t instance, const ftm_output_cmp_param_t *param)
Disables compare match output control and clears FTM timer configuration.
Definition: ftm_driver.c:1110
void FTM0_Ch4_Ch5_IRQHandler(void)
Definition: ftm_driver.c:1637
static void FTM_HAL_Enable(FTM_Type *const ftmBase, bool enable)
Enables the FTM peripheral timer group.
Definition: ftm_hal.h:1468
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K144.h:269
FlexTimer Registers sync parameters Please don't use software and hardware trigger simultaneously Imp...
Definition: ftm_driver.h:172
const ftm_combined_ch_param_t * pwmCombinedChannelConfig
Definition: ftm_driver.h:308
ftm_output_compare_mode_t chMode
Definition: ftm_driver.h:363
static void FTM_HAL_SetChnCountVal(FTM_Type *const ftmBase, uint8_t channel, uint16_t value)
Sets the FTM peripheral timer channel counter value.
Definition: ftm_hal.h:1137
ftm_config_mode_t mode
Definition: ftm_driver.h:222
#define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT
FlexTimer driver timer mode configuration structure.
Definition: ftm_driver.h:220
static void FTM_HAL_SetInvctrlReg(FTM_Type *const ftmBase, uint32_t regVal)
Writes the provided value to the Inverting control register.
Definition: ftm_hal.h:2387
status_t FTM_DRV_SetModuloCounterValue(uint32_t instance, uint16_t counterValue, bool softwareTrigger)
This function configure the maximum counter value.
Definition: ftm_driver.c:944
void FTM1_Ch6_Ch7_IRQHandler(void)
Definition: ftm_driver.c:1667
bool hardwareSync1
Definition: ftm_driver.h:178
static void FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM SWOCTRL register when using a software trigger.
Definition: ftm_hal.h:2774
status_t FTM_DRV_QuadDecodeStart(uint32_t instance, const ftm_quad_decode_config_t *config)
Configures the quadrature mode and starts measurement.
Definition: ftm_driver.c:1457
static bool FTM_HAL_GetQuadTimerOverflowDir(const FTM_Type *ftmBase)
Gets the Timer overflow direction in quadrature mode.
Definition: ftm_hal.h:2242
ftm_deadtime_ps_t deadTimePrescaler
Definition: ftm_driver.h:305
static void FTM_HAL_SetWriteProtectionCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM write protection.
Definition: ftm_hal.h:1445
uint8_t nNumCombinedPwmChannels
Definition: ftm_driver.h:302
status_t FTM_DRV_Init(uint32_t instance, const ftm_user_config_t *info, ftm_state_t *state)
Initializes the FTM driver.
Definition: ftm_driver.c:136
static const clock_names_t g_ftmExtClockSel[FTM_INSTANCE_COUNT][2]
Select external clock pin or clock source for peripheral.
Definition: ftm_driver.c:82
ftm_quad_decoder_state_t FTM_DRV_QuadGetState(uint32_t instance)
Return the current quadrature decoder state (counter value, overflow flag and overflow direction) ...
Definition: ftm_driver.c:1537
static void FTM_HAL_SetQuadPhaseBFilterCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the phase B input filter.
Definition: ftm_hal.h:2154
static bool FTM_HAL_GetCpwms(const FTM_Type *ftmBase)
Gets the FTM count direction bit.
Definition: ftm_hal.h:636
status_t FTM_DRV_CounterStart(uint32_t instance)
Starts the FTM counter.
Definition: ftm_driver.c:287
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
void * channelsCallbacksParams[FEATURE_FTM_CHANNEL_COUNT]
Definition: ftm_driver.h:163
#define DEV_ASSERT(x)
Definition: devassert.h:78
static void FTM_HAL_SetTimerOverflowInt(FTM_Type *const ftmBase, bool state)
Enables the FTM peripheral timer overflow interrupt.
Definition: ftm_hal.h:525
const IRQn_Type g_ftmFaultIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_driver.c:74
void FTM0_Ch0_Ch1_IRQHandler(void)
Definition: ftm_driver.c:1625
static void FTM_HAL_DisablePwmChannelOutputs(FTM_Type *const ftmBase, uint8_t channel)
Disable PWM channel Outputs.
Definition: ftm_hal.h:569
void FTM1_Ch4_Ch5_IRQHandler(void)
Definition: ftm_driver.c:1661
ftm_phase_params_t phaseAConfig
Definition: ftm_driver.h:405
static bool FTM_HAL_HasTimerOverflowed(const FTM_Type *ftmBase)
Returns the FTM peripheral timer overflow interrupt flag.
Definition: ftm_hal.h:604
static void FTM_HAL_SetFaultInputFilterCmd(FTM_Type *const ftmBase, uint8_t inputNum, bool enable)
Enables or disables the fault input filter.
Definition: ftm_hal.h:2272
status_t FTM_DRV_MaskOutputChannels(uint32_t instance, uint32_t channelsMask, bool softwareTrigger)
This function will mask the output of the channels and at match events will be ignored by the masked ...
Definition: ftm_driver.c:801
static void FTM_HAL_SetFaultInt(FTM_Type *const ftmBase, bool state)
Enables/disables the FTM peripheral timer fault interrupt.
Definition: ftm_hal.h:1352
static bool FTM_HAL_GetQuadDir(const FTM_Type *ftmBase)
Gets the FTM counter direction in quadrature mode.
Definition: ftm_hal.h:2226
status_t FTM_DRV_InitPwm(uint32_t instance, const ftm_pwm_param_t *param)
Configures the duty cycle and frequency and starts outputting the PWM on all channels configured in p...
Definition: ftm_driver.c:399
static void FTM_HAL_SetHalfCycleValue(FTM_Type *const ftmBase, uint16_t value)
Sets the value for the half cycle reload register.
Definition: ftm_hal.h:418
uint32_t FTM_DRV_GetFrequency(uint32_t instance)
Retrieves the frequency of the clock source feeding the FTM counter.
Definition: ftm_driver.c:1560
status_t FTM_DRV_InitInputCapture(uint32_t instance, const ftm_input_param_t *param)
Configures Channel Input Capture for either getting time-stamps on edge detection or on signal measur...
Definition: ftm_driver.c:1205
status_t FTM_DRV_UpdatePwmChannel(uint32_t instance, uint8_t channel, ftm_pwm_update_option_t typeOfUpdate, uint16_t firstEdge, uint16_t secondEdge, bool softwareTrigger)
This function updates the waveform output in PWM mode (duty cycle and phase).
Definition: ftm_driver.c:606
static uint8_t FTM_HAL_GetChnMode(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel mode.
Definition: ftm_hal.h:846
static void FTM_HAL_SetDualChnDeadtimeCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disabled the FTM peripheral timer channel pair deadtime insertion.
Definition: ftm_hal.h:1725
const IRQn_Type g_ftmIrqId[FTM_INSTANCE_COUNT][FEATURE_FTM_CHANNEL_COUNT]
Interrupt vectors for the FTM peripheral.
Definition: ftm_driver.c:73
ftm_phase_params_t phaseBConfig
Definition: ftm_driver.h:406
status_t FTM_DRV_SetSoftwareOutputChannelControl(uint32_t instance, uint8_t channelsMask, bool softwareTrigger)
This function will configure which output channel can be software controlled.
Definition: ftm_driver.c:898
static void FTM_HAL_SetModCntinCvHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM MOD, CNTIN and CV registers when using a hardware trigger. ...
Definition: ftm_hal.h:2742
uint16_t FTM_DRV_GetInputCaptureMeasurement(uint32_t instance, uint8_t channel)
This function is used to calculate the measurement and/or time stamps values which are read from the ...
Definition: ftm_driver.c:1402
peripheral_clock_source_t
PCC clock source select Implements peripheral_clock_source_t_Class.
Definition: pcc_hal.h:118
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
ftm_clock_source_t ftmClockSource
Definition: ftm_driver.h:158
status_t FTM_DRV_CounterStop(uint32_t instance)
Stops the FTM counter.
Definition: ftm_driver.c:308
bool hardwareSync0
Definition: ftm_driver.h:176
static void FTM_HAL_SetFaultInputFilterVal(FTM_Type *const ftmBase, uint32_t value)
Sets the fault input filter value.
Definition: ftm_hal.h:2255
#define FTM_Fault_IRQS
Definition: S32K144.h:4060
uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance, uint32_t freqencyHz)
This function is used to covert the given frequency to period in ticks.
Definition: ftm_driver.c:1612
#define FTM_DUTY_TO_TICKS_SHIFT
Shift value which converts duty to ticks.
Definition: ftm_driver.h:63
void * channelsCallbacksParams
Definition: ftm_driver.h:339
const ftm_pwm_fault_param_t * faultConfig
Definition: ftm_driver.h:309
#define CHAN1_IDX
Channel number for CHAN2.
Definition: ftm_hal.h:231
void FTM1_Ch2_Ch3_IRQHandler(void)
Definition: ftm_driver.c:1655
static void FTM_HAL_SetDualChnDecapCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the FTM peripheral timer channel dual edge capture.
Definition: ftm_hal.h:1752
ftm_pwm_sync_mode_t syncPoint
Definition: ftm_driver.h:191
uint16_t finalValue
Definition: ftm_driver.h:224
ftm_quad_decode_mode_t mode
Definition: ftm_driver.h:402
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:31
uint16_t nMaxCountValue
Definition: ftm_driver.h:351
#define FEATURE_FTM_CHANNEL_COUNT
static void FTM_HAL_SetInvctrlHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM INVCTRL register when using a hardware trigger.
Definition: ftm_hal.h:2710
static void FTM_HAL_SetAllChnSoftwareCtrlCmd(FTM_Type *const ftmBase, uint8_t channelsMask)
Enables or disables the channel software output control.The main difference between this function and...
Definition: ftm_hal.h:2430
#define FTM2_IDX
Instance number for FTM3.
Definition: ftm_hal.h:122
FTM quadrature configure structure.
Definition: ftm_driver.h:400
static void FTM_HAL_EnableChnInt(FTM_Type *const ftmBase, uint8_t channel)
Enables the FTM peripheral timer channel(n) interrupt.
Definition: ftm_hal.h:985
void FTM3_Ch2_Ch3_IRQHandler(void)
Definition: ftm_driver.c:1703
void FTM_HAL_SetChnInputCaptureFilter(FTM_Type *const ftmBase, uint8_t channel, uint8_t value)
Sets the FTM peripheral timer channel input capture filter value.
Definition: ftm_hal.c:143
bool maxLoadingPoint
Definition: ftm_driver.h:182
#define FTM1_IDX
Instance number for FTM2.
Definition: ftm_hal.h:120
void FTM2_Ch6_Ch7_IRQHandler(void)
Definition: ftm_driver.c:1691
static void FTM_HAL_SetDualChnCombineCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the FTM peripheral timer channel pair output combine mode.
Definition: ftm_hal.h:1853
#define FTM_INSTANCE_COUNT
Definition: S32K144.h:4021
uint16_t measurementResults[FEATURE_FTM_CHANNEL_COUNT]
Definition: ftm_driver.h:162
static void FTM_HAL_SetCntinPwmSyncModeCmd(FTM_Type *const ftmBase, ftm_reg_update_t mode)
Sets the CNTIN register PWM synchronization mode.
Definition: ftm_hal.h:2918
#define CHAN4_IDX
Channel number for CHAN5.
Definition: ftm_hal.h:237
const ftm_output_cmp_ch_param_t * outputChannelConfig
Definition: ftm_driver.h:379
static uint16_t FTM_HAL_GetMod(const FTM_Type *ftmBase)
Returns the FTM peripheral counter modulo value.
Definition: ftm_hal.h:739
static void FTM_HAL_SetMinLoadingCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer minimum loading points.
Definition: ftm_hal.h:1627
static void FTM_HAL_SetCpwms(FTM_Type *const ftmBase, bool mode)
Sets the FTM count direction bit.
Definition: ftm_hal.h:619
static void FTM_HAL_ClearChnEventFlag(FTM_Type *const ftmBase, uint8_t channel)
Clear the channel flag by writing a 0 to the CHF bit.
Definition: ftm_hal.h:1037
void FTM3_Ch6_Ch7_IRQHandler(void)
Definition: ftm_driver.c:1715
uint8_t phaseFilterVal
Definition: ftm_driver.h:391
uint8_t nNumIndependentPwmChannels
Definition: ftm_driver.h:301
bool enableInitializationTrigger
Definition: ftm_driver.h:211
static void FTM_HAL_SetDeadtimePrescale(FTM_Type *const ftmBase, ftm_deadtime_ps_t divider)
Sets the FTM dead time divider.
Definition: ftm_hal.h:1935
#define FTM_Overflow_IRQS
Definition: S32K144.h:4061
#define FTM_FEATURE_FAULT_CHANNELS
static void FTM_HAL_SetHardwareSyncTriggerSrc(FTM_Type *const ftmBase, uint8_t trigger_num, bool enable)
Sets the FTM hardware synchronization trigger.
Definition: ftm_hal.h:1552
static void FTM_HAL_SetCounterSoftwareSyncModeCmd(FTM_Type *const ftmBase, ftm_pwm_sync_mode_t update_mode)
Sets sync mode for FTM counter register when using a software trigger.
Definition: ftm_hal.h:2854
void FTM0_Ch6_Ch7_IRQHandler(void)
Definition: ftm_driver.c:1643
ftm_pwm_update_option_t
FlexTimer Configure type of PWM update in the duty cycle or in ticks.
Definition: ftm_driver.h:107
FlexTimer driver PWM parameters.
Definition: ftm_driver.h:299
static void FTM_HAL_SetPwmFaultBehavior(FTM_Type *const ftmBase, bool enable)
Configures the behavior of the PWM outputs when a fault is detected.
Definition: ftm_hal.h:2337
static void FTM_HAL_SetInvctrlPwmSyncModeCmd(FTM_Type *const ftmBase, ftm_reg_update_t mode)
Sets the INVCTRL register PWM synchronization mode.
Definition: ftm_hal.h:2902
static void FTM_HAL_ClearTimerOverflow(FTM_Type *const ftmBase)
Clears the timer overflow interrupt flag.
Definition: ftm_hal.h:584
static bool FTM_HAL_GetDualChnCombineCmd(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Verify if an channels pair is used in combine mode or not.
Definition: ftm_hal.h:1881
ftm_reg_update_t inverterSync
Definition: ftm_driver.h:186
ftm_channel_event_callback_t channelsCallbacks[FEATURE_FTM_CHANNEL_COUNT]
Definition: ftm_driver.h:164
clock_names_t
Clock names.
status_t FTM_DRV_SetInitialCounterValue(uint32_t instance, uint16_t counterValue, bool softwareTrigger)
This function configure the initial counter value. The counter will get this value after an overflow ...
Definition: ftm_driver.c:825
static void FTM_HAL_ClearFaultControl(FTM_Type *const ftmBase)
Clears the entire content value of the Fault control register.
Definition: ftm_hal.h:2295
ftm_signal_measurement_mode_t measurementType
Definition: ftm_driver.h:335
status_t FTM_DRV_Deinit(uint32_t instance)
Shuts down the FTM driver.
Definition: ftm_driver.c:205
ftm_polarity_t mainChannelPolarity
Definition: ftm_driver.h:282
ftm_state_t * ftmStatePtr[FTM_INSTANCE_COUNT]
Pointer to runtime state structure.
Definition: ftm_driver.c:79
void FTM_HAL_Init(FTM_Type *const ftmBase, ftm_clock_ps_t ftmClockPrescaler)
Initializes the FTM. This function will enable the flexTimer module and selects one pre-scale factor ...
Definition: ftm_hal.c:43
static void FTM_HAL_SetFaultInputCmd(FTM_Type *const ftmBase, uint8_t inputNum, bool enable)
Enables or disables the fault input.
Definition: ftm_hal.h:2311
ftm_config_mode_t ftmMode
Definition: ftm_driver.h:159
status_t FTM_DRV_DeinitInputCapture(uint32_t instance, const ftm_input_param_t *param)
Disables input capture mode and clears FTM timer configuration.
Definition: ftm_driver.c:1350
static bool FTM_HAL_GetDualEdgeCaptureBit(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Enables the FTM peripheral timer dual edge capture mode.
Definition: ftm_hal.h:1807
ftm_signal_measurement_mode_t
FlexTimer input capture measurement type for dual edge input capture.
Definition: ftm_driver.h:82
static void FTM_HAL_SetOutmaskReg(FTM_Type *const ftmBase, uint32_t regVal)
Writes the provided value to the OUTMASK register.
Definition: ftm_hal.h:1228
static peripheral_clock_source_t PCC_HAL_GetClockSourceSel(const PCC_Type *const base, const clock_names_t clockName)
Gets the selection of a clock source for a specific peripheral.
Definition: pcc_hal.h:431
static void FTM_HAL_SetFaultControlMode(FTM_Type *const ftmBase, ftm_fault_mode_t mode)
Defines the FTM fault control mode.
Definition: ftm_hal.h:1413
status_t FTM_DRV_SetHalfCycleReloadPoint(uint32_t instance, uint16_t reloadPoint, bool softwareTrigger)
This function configure the value of the counter which will generates an reload point.
Definition: ftm_driver.c:849
static void FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM MOD, CNTIN and CV registers when using a software trigger. ...
Definition: ftm_hal.h:2822
static void FTM_HAL_SetInvctrlSoftwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM INVCTRL register when using a software trigger.
Definition: ftm_hal.h:2790
static void FTM_HAL_SetSoftwareTriggerCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer software trigger.
Definition: ftm_hal.h:1532
ftm_second_channel_polarity_t secondChannelPolarity
Definition: ftm_driver.h:285
static void FTM_HAL_SetMod(FTM_Type *const ftmBase, uint16_t value)
Sets the FTM peripheral timer modulo value.
Definition: ftm_hal.h:724
void FTM3_Ch4_Ch5_IRQHandler(void)
Definition: ftm_driver.c:1709
static void FTM_HAL_SetDualChnCompCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, ftm_second_channel_polarity_t polarity)
Enables or disables the FTM peripheral timer channel pair output complement mode. ...
Definition: ftm_hal.h:1826
static void FTM_HAL_SetCounterInitVal(FTM_Type *const ftmBase, uint16_t value)
Sets the FTM peripheral timer counter initial value.
Definition: ftm_hal.h:752
ftm_config_mode_t ftmMode
Definition: ftm_driver.h:204
static void FTM_HAL_SetCounterHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM counter register when using a hardware trigger.
Definition: ftm_hal.h:2758
static void FTM_HAL_SetChnMSnBAMode(FTM_Type *const ftmBase, uint8_t channel, uint8_t selection)
Sets the FTM peripheral timer channel mode.
Definition: ftm_hal.h:781
FlexTimer driver PWM parameters.
Definition: ftm_driver.h:374
static void FTM_HAL_SetOutmaskSoftwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM OUTMASK register when using a software trigger.
Definition: ftm_hal.h:2806
static void FTM_HAL_SetQuadMode(FTM_Type *const ftmBase, ftm_quad_decode_mode_t quadMode)
Sets the encoding mode used in quadrature decoding mode.
Definition: ftm_hal.h:2209
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
status_t FTM_DRV_UpdateOutputCompareChannel(uint32_t instance, uint8_t channel, uint16_t nextComparematchValue, ftm_output_compare_update_t update, bool softwareTrigger)
Sets the next compare match value based on the current counter value.
Definition: ftm_driver.c:1152
static bool FTM_HAL_GetDualChnMofCombineCmd(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Verify if an channels pair is used in the modified combine mode or not.
Definition: ftm_hal.h:1901
ftm_reg_update_t maskRegSync
Definition: ftm_driver.h:188
const ftm_independent_ch_param_t * pwmIndependentChannelConfig
Definition: ftm_driver.h:307
ftm_polarity_t polarity
Definition: ftm_driver.h:261
static void FTM_HAL_SetDeadtimeCount(FTM_Type *const ftmBase, uint8_t count)
Sets the FTM deadtime value.
Definition: ftm_hal.h:1953
void FTM0_Ch2_Ch3_IRQHandler(void)
Definition: ftm_driver.c:1631
bool minLoadingPoint
Definition: ftm_driver.h:184
ftm_input_op_mode_t inputMode
Definition: ftm_driver.h:333
static uint8_t FTM_HAL_GetClockSource(const FTM_Type *ftmBase)
Reads the FTM clock source.
Definition: ftm_hal.h:483
static void FTM_HAL_SetChnFaultInputPolarityCmd(FTM_Type *const ftmBase, uint8_t fltChannel, ftm_polarity_t polarity)
Sets the FTM peripheral timer channel fault input polarity.
Definition: ftm_hal.h:1326
bool autoClearTrigger
Definition: ftm_driver.h:190
ftm_output_compare_update_t
FlexTimer input capture type of the next output compare value.
Definition: ftm_driver.h:96
status_t FTM_DRV_SetSync(uint32_t instance, const ftm_pwm_sync_t *param)
This function configures sync mechanism for some FTM registers (MOD, CNINT, HCR, CnV, OUTMASK, INVCTRL, SWOCTRL).
Definition: ftm_driver.c:970
static void FTM_HAL_SetOutmaskHardwareSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets sync mode for FTM OUTMASK register when using a hardware trigger.
Definition: ftm_hal.h:2726
void FTM_HAL_Reset(FTM_Type *const ftmBase)
Resets the FTM registers. All the register use in the driver should be reset to default value of each...
Definition: ftm_hal.c:59
#define FTM_BASE_PTRS
Definition: S32K144.h:4044
#define PCC_BASE_PTRS
Definition: S32K144.h:8145
static void FTM_HAL_SetMaxLoadingCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer maximum loading points.
Definition: ftm_hal.h:1611
#define FTM_MAX_DUTY_CYCLE
Maximum value for PWM duty cycle.
Definition: ftm_driver.h:61
static void FTM_HAL_SetInitChnOutputCmd(FTM_Type *const ftmBase, bool enable)
Initializes the channels output.
Definition: ftm_hal.h:1499
status_t FTM_DRV_SetSoftOutChnValue(uint32_t instance, uint8_t channelsValues, bool softwareTrigger)
This function will force the output value of a channel to a specific value. Before using this functio...
Definition: ftm_driver.c:875
static void FTM_DRV_IrqHandler(uint32_t instance, uint8_t channelPair)
Definition: ftm_driver.c:1720
static void FTM_HAL_SetAllChnSoftwareCtrlVal(FTM_Type *const ftmBase, uint8_t channelsValues)
Sets the channel software output control value.
Definition: ftm_hal.h:2474
uint32_t FTM_DRV_CounterRead(uint32_t instance)
Reads back the current value of the FTM counter.
Definition: ftm_driver.c:328
const IRQn_Type g_ftmOverflowIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_driver.c:75
static void FTM_HAL_SetPwmSyncModeCmd(FTM_Type *const ftmBase, bool mode)
Sets the PWM synchronization mode to enhanced or legacy.
Definition: ftm_hal.h:2870
static uint8_t FTM_HAL_GetClockPs(const FTM_Type *ftmBase)
Reads the FTM clock divider.
Definition: ftm_hal.h:511
static uint16_t FTM_HAL_GetChnCountVal(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel counter value.
Definition: ftm_hal.h:1156
ftm_quad_phase_polarity_t phasePolarity
Definition: ftm_driver.h:392
status_t FTM_DRV_DeinitPwm(uint32_t instance)
Stops all PWM channels .
Definition: ftm_driver.c:343
ftm_clock_source_t ftmClockSource
Definition: ftm_driver.h:207
static void FTM_HAL_SetHwTriggerSyncModeCmd(FTM_Type *const ftmBase, bool enable)
Sets hardware trigger mode.
Definition: ftm_hal.h:2838
void FTM2_Ch2_Ch3_IRQHandler(void)
Definition: ftm_driver.c:1679
void FTM1_Ch0_Ch1_IRQHandler(void)
Definition: ftm_driver.c:1649
static void FTM_HAL_SetQuadPhaseAPolarity(FTM_Type *const ftmBase, ftm_quad_phase_polarity_t mode)
Selects polarity for the quadrature decode phase A input.
Definition: ftm_hal.h:2177
#define CHAN0_IDX
Channel number for CHAN1.
Definition: ftm_hal.h:229
uint32_t ftmSourceClockFrequency
Definition: ftm_driver.h:161
static bool FTM_HAL_HasChnEventOccurred(const FTM_Type *ftmBase, uint8_t channel)
Returns whether any event for the FTM peripheral timer channel has occurred.
Definition: ftm_hal.h:1021
FTM quadrature state(counter value and flags)
Definition: ftm_driver.h:414
ftm_config_mode_t mode
Definition: ftm_driver.h:303
uint8_t nNumChannels
Definition: ftm_driver.h:350
ftm_reg_update_t outRegSync
Definition: ftm_driver.h:187
static void FTM_HAL_SetQuadPhaseBPolarity(FTM_Type *const ftmBase, ftm_quad_phase_polarity_t mode)
Selects polarity for the quadrature decode phase B input.
Definition: ftm_hal.h:2193
uint8_t deadTimeValue
Definition: ftm_driver.h:304
static void FTM_HAL_SetClockSource(FTM_Type *const ftmBase, ftm_clock_source_t clock)
Sets the FTM clock source.
Definition: ftm_hal.h:464
static uint16_t FTM_HAL_GetCounter(const FTM_Type *ftmBase)
Returns the FTM peripheral current counter value.
Definition: ftm_hal.h:711
static void FTM_HAL_SetCounter(FTM_Type *const ftmBase, uint16_t value)
Sets the FTM peripheral current counter value.
Definition: ftm_hal.h:696
ftm_clock_ps_t ftmPrescaler
Definition: ftm_driver.h:205
static void FTM_HAL_SetDualEdgeCaptureCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables the FTM peripheral timer dual edge capture mode.
Definition: ftm_hal.h:1779