84 #define DIVIDER_MIN_VALUE 1U
85 #define DIVIDER_MAX_VALUE 0xFFU
89 #define TX_SHIFTER(x) (x)
90 #define RX_SHIFTER(x) (uint8_t)((x) + 1U)
91 #define SCK_TIMER(x) (x)
92 #define SS_TIMER(x) (uint8_t)((x) + 1U)
95 #define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU)
107 static void FLEXIO_SPI_DRV_MasterComputeBaudRateDivider(uint32_t baudRate,
114 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 1U;
116 if (tmpDiv < DIVIDER_MIN_VALUE)
118 tmpDiv = DIVIDER_MIN_VALUE;
120 if (tmpDiv > DIVIDER_MAX_VALUE)
122 tmpDiv = DIVIDER_MAX_VALUE;
125 *divider = (uint16_t)tmpDiv;
146 uint8_t resourceIndex;
149 resourceIndex = master->flexioCommon.resourceIndex;
151 FLEXIO_SPI_DRV_MasterComputeBaudRateDivider(userConfigPtr->
baudRate, ÷r, inputClock);
153 divider += (uint16_t)((((uint16_t)(userConfigPtr->
transferSize) * 8U * 2U) - 1U) << 8U);
185 TX_SHIFTER(resourceIndex),
190 SCK_TIMER(resourceIndex),
193 TX_SHIFTER(resourceIndex),
200 RX_SHIFTER(resourceIndex),
205 SCK_TIMER(resourceIndex),
208 RX_SHIFTER(resourceIndex),
216 SCK_TIMER(resourceIndex),
225 SCK_TIMER(resourceIndex),
226 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
237 SS_TIMER(resourceIndex),
246 SS_TIMER(resourceIndex),
250 userConfigPtr->
ssPin,
266 uint8_t resourceIndex;
271 resourceIndex = master->flexioCommon.resourceIndex;
274 switch (master->driverType)
279 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
282 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
294 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
302 master->driverIdle =
true;
303 master->txRemainingBytes = 0U;
304 master->rxRemainingBytes = 0U;
307 if (master->blocking ==
true)
323 uint8_t resourceIndex;
325 resourceIndex = master->flexioCommon.resourceIndex;
352 uint8_t resourceIndex;
354 resourceIndex = master->flexioCommon.resourceIndex;
370 FLEXIO_SPI_DRV_MasterEndTransfer(master);
386 switch (master->driverType)
390 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
399 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
407 master->blocking =
false;
412 FLEXIO_SPI_DRV_MasterStopTransfer(master);
415 return master->status;
425 static void FLEXIO_SPI_DRV_MasterEndDmaTransfer(
void *stateStruct,
edma_chn_status_t status)
442 FLEXIO_SPI_DRV_MasterStopTransfer(master);
444 if (master->callback != NULL)
465 uint8_t resourceIndex;
468 resourceIndex = slave->flexioCommon.resourceIndex;
498 TX_SHIFTER(resourceIndex),
503 SCK_TIMER(resourceIndex),
506 TX_SHIFTER(resourceIndex),
513 RX_SHIFTER(resourceIndex),
518 SCK_TIMER(resourceIndex),
521 RX_SHIFTER(resourceIndex),
529 SCK_TIMER(resourceIndex),
538 SCK_TIMER(resourceIndex),
539 (uint8_t)(userConfigPtr->
ssPin << 1U),
559 uint8_t resourceIndex;
562 resourceIndex = master->flexioCommon.resourceIndex;
569 data >>= (32U - (8U * (uint32_t)(master->transferSize)));
576 if ((master->rxRemainingBytes > 0U) && (master->rxData != NULL))
578 switch (master->transferSize)
581 *(uint8_t *)master->rxData = (uint8_t)data;
584 *(uint16_t *)master->rxData = (uint16_t)data;
587 *(uint32_t *)master->rxData = (uint32_t)data;
594 master->rxData = &master->rxData[(master->transferSize)];
595 master->rxRemainingBytes -= (uint32_t)(master->transferSize);
613 uint32_t data = FLEXIO_SPI_DUMMYDATA;
614 uint8_t resourceIndex;
617 resourceIndex = master->flexioCommon.resourceIndex;
619 if (master->txRemainingBytes == 0U)
625 if ((master->txRemainingBytes > 0U) && (master->txData != NULL))
628 switch (master->transferSize)
631 data = (uint32_t)(*(
const uint8_t *)master->txData);
634 data = (uint32_t)(*(
const uint16_t *)master->txData);
637 data = (uint32_t)(*(
const uint32_t *)master->txData);
644 master->txData = &master->txData[master->transferSize];
645 master->txRemainingBytes -= (uint32_t)(master->transferSize);
654 data <<= 32U - (8U * (uint32_t)(master->transferSize));
675 static void FLEXIO_SPI_DRV_MasterCheckStatus(
void *stateStruct)
679 uint8_t resourceIndex;
685 resourceIndex = master->flexioCommon.resourceIndex;
692 FLEXIO_SPI_DRV_MasterStopTransfer(master);
694 if (master->callback != NULL)
704 FLEXIO_SPI_DRV_MasterStopTransfer(master);
706 if (master->callback != NULL)
715 FLEXIO_SPI_DRV_ReadData(master);
720 FLEXIO_SPI_DRV_WriteData(master);
721 if (master->txRemainingBytes == 0U)
730 if ((master->txRemainingBytes == 0U) && (master->rxRemainingBytes == 0U))
738 FLEXIO_SPI_DRV_MasterStopTransfer(master);
740 if (master->callback != NULL)
761 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
764 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter]));
768 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter])) + (
sizeof(uint32_t) - (uint32_t)master->transferSize);
787 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
790 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter])) + (
sizeof(uint32_t) - (uint32_t)master->transferSize);
794 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter]));
808 uint8_t resourceIndex;
818 resourceIndex = master->flexioCommon.resourceIndex;
820 if (master->txData != NULL)
822 addr = (uint32_t)(master->txData);
827 master->dummyDmaData = FLEXIO_SPI_DUMMYDATA;
828 addr = (uint32_t)(&(master->dummyDmaData));
835 FLEXIO_SPI_DRV_MasterComputeTxRegAddr(master),
836 dmaTransferSize[(uint32_t)master->transferSize - 1U],
837 (uint32_t)master->transferSize);
838 if (master->txData == NULL)
846 if (master->rxData != NULL)
848 addr = (uint32_t)(master->rxData);
853 addr = (uint32_t)(&(master->dummyDmaData));
859 FLEXIO_SPI_DRV_MasterComputeRxRegAddr(master),
861 dmaTransferSize[(uint32_t)master->transferSize - 1U],
862 (uint32_t)master->transferSize);
863 if (master->rxData == NULL)
922 master->flexioCommon.resourceCount = 2U;
937 master->driverType = userConfigPtr->
driverType;
938 master->bitOrder = userConfigPtr->
bitOrder;
940 master->callback = userConfigPtr->
callback;
942 master->blocking =
false;
943 master->driverIdle =
true;
944 master->master =
true;
948 FLEXIO_SPI_DRV_MasterConfigure(master, userConfigPtr, inputClock);
954 master->flexioCommon.isr = FLEXIO_SPI_DRV_MasterCheckStatus;
964 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(master->flexioCommon.resourceIndex)];
965 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(master->flexioCommon.resourceIndex)];
1015 uint32_t inputClock;
1017 uint8_t resourceIndex;
1021 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1022 resourceIndex = master->flexioCommon.resourceIndex;
1032 FLEXIO_SPI_DRV_MasterComputeBaudRateDivider(baudRate, ÷r, inputClock);
1036 timerCmp = (uint16_t)((timerCmp & 0xFF00U) | divider);
1057 uint32_t inputClock;
1059 uint8_t resourceIndex;
1063 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1064 resourceIndex = master->flexioCommon.resourceIndex;
1073 divider = (uint16_t)(timerCmp & 0x00FFU);
1076 *baudRate = (inputClock + divider + 1U) / (2U * ((uint32_t)divider + 1U));
1093 const uint8_t *txData,
1098 uint8_t resourceIndex;
1101 DEV_ASSERT((dataSize % (uint32_t)(master->transferSize)) == 0U);
1102 DEV_ASSERT((txData != NULL) || (rxData != NULL));
1104 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1105 resourceIndex = master->flexioCommon.resourceIndex;
1110 master->txData = txData;
1111 master->rxData = rxData;
1112 master->txRemainingBytes = dataSize;
1113 master->rxRemainingBytes = dataSize;
1114 master->driverIdle =
false;
1118 FLEXIO_SPI_DRV_MasterEnableTransfer(master);
1120 switch (master->driverType)
1125 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
1128 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
1133 FLEXIO_SPI_DRV_MasterCheckStatus(master);
1136 FLEXIO_SPI_DRV_MasterStartDmaTransfer(master);
1155 const uint8_t *txData,
1165 master->blocking =
true;
1171 master->blocking =
false;
1176 return FLEXIO_SPI_DRV_MasterWaitTransferEnd(master, timeout);
1192 FLEXIO_SPI_DRV_MasterStopTransfer(master);
1212 FLEXIO_SPI_DRV_MasterCheckStatus(master);
1215 if (bytesRemaining != NULL)
1217 *bytesRemaining = master->txRemainingBytes;
1220 return master->status;
1247 slave->flexioCommon.resourceCount = 2U;
1262 slave->driverType = userConfigPtr->
driverType;
1263 slave->bitOrder = userConfigPtr->
bitOrder;
1265 slave->callback = userConfigPtr->
callback;
1267 slave->blocking =
false;
1268 slave->driverIdle =
true;
1269 slave->master =
false;
1273 FLEXIO_SPI_DRV_SlaveConfigure(slave, userConfigPtr);
1279 slave->flexioCommon.isr = FLEXIO_SPI_DRV_MasterCheckStatus;
1289 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(slave->flexioCommon.resourceIndex)];
1290 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(slave->flexioCommon.resourceIndex)];
status_t FLEXIO_SPI_DRV_MasterGetBaudRate(flexio_spi_master_state_t *master, uint32_t *baudRate)
Get the currently configured baud rate.
__IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT]
static void FLEXIO_HAL_SetShifterInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the shifter interrupts.
static void FLEXIO_HAL_SetShifterMode(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_mode_t mode)
Sets the mode of the specified shifter.
flexio_timer_polarity_t
Shift clock polarity options Implements : flexio_timer_polarity_t_Class.
static uint16_t FLEXIO_HAL_GetTimerCompare(const FLEXIO_Type *baseAddr, uint8_t timer)
Returns the compare value of the specified timer.
DMAMUX_Type *const g_dmamuxBase[DMAMUX_INSTANCE_COUNT]
Array for DMAMUX module register base address.
static void FLEXIO_HAL_SetTimerControl(FLEXIO_Type *baseAddr, uint8_t timer, uint8_t trigger, flexio_trigger_polarity_t triggerPolarity, flexio_trigger_source_t triggerSource, uint8_t pin, flexio_pin_polarity_t pinPolarity, flexio_pin_config_t pinConfig, flexio_timer_mode_t mode)
Sets all control settings for specified timer.
flexio_spi_transfer_size_t transferSize
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
status_t FLEXIO_SPI_DRV_MasterTransferBlocking(flexio_spi_master_state_t *master, const uint8_t *txData, uint8_t *rxData, uint32_t dataSize, uint32_t timeout)
Perform a blocking SPI master transaction.
static void FLEXIO_HAL_SetTimerMode(FLEXIO_Type *baseAddr, uint8_t timer, flexio_timer_mode_t mode)
Sets the mode of the specified timer.
FLEXIO_Type *const g_flexioBase[FLEXIO_INSTANCE_COUNT]
status_t FLEXIO_SPI_DRV_MasterTransfer(flexio_spi_master_state_t *master, const uint8_t *txData, uint8_t *rxData, uint32_t dataSize)
Perform a non-blocking SPI master transaction.
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
#define FLEXIO_INSTANCE_COUNT
void EDMA_HAL_TCDSetMajorCount(DMA_Type *base, uint32_t channel, uint32_t count)
Sets the major iteration count according to minor loop channel link setting.
flexio_callback_t callback
flexio_shifter_start_t
Timer start bit options - for Transmit, Receive or Match Store modes only Implements : flexio_shifter...
flexio_spi_transfer_bit_order_t bitOrder
static void FLEXIO_HAL_WriteShifterBuffer(FLEXIO_Type *baseAddr, uint8_t shifter, uint32_t value, flexio_shifter_buffer_mode_t mode)
Writes a value in the specified shifter buffer.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
static void FLEXIO_HAL_SetShifterConfig(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_start_t start, flexio_shifter_stop_t stop, flexio_shifter_source_t source)
Sets all configuration settings for specified shifter.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
static uint32_t FLEXIO_HAL_ReadShifterBuffer(const FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_buffer_mode_t mode)
Reads the value from the specified shifter buffer.
status_t FLEXIO_SPI_DRV_MasterGetStatus(flexio_spi_master_state_t *master, uint32_t *bytesRemaining)
Get the status of the current non-blocking SPI master transaction.
Slave configuration structure.
flexio_driver_type_t driverType
static void EDMA_HAL_TCDSetSrcOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the source address signed offset for the hardware TCD.
edma_chn_status_t
Channel status for eDMA channel.
__IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT]
static void FLEXIO_HAL_SetShifterControl(FLEXIO_Type *baseAddr, uint8_t shifter, flexio_shifter_mode_t mode, uint8_t pin, flexio_pin_polarity_t pinPolarity, flexio_pin_config_t pinConfig, uint8_t timer, flexio_timer_polarity_t timerPolarity)
Sets all control settings for the specified shifter.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
flexio_spi_transfer_size_t transferSize
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Master configuration structure.
status_t FLEXIO_SPI_DRV_MasterSetBaudRate(flexio_spi_master_state_t *master, uint32_t baudRate)
Set the baud rate for any subsequent SPI communication.
const uint8_t g_flexioDMASrc[FLEXIO_INSTANCE_COUNT][FEATURE_FLEXIO_MAX_SHIFTER_COUNT]
status_t FLEXIO_SPI_DRV_SlaveInit(uint32_t instance, const flexio_spi_slave_user_config_t *userConfigPtr, flexio_spi_slave_state_t *slave)
Initialize the FLEXIO_SPI slave mode driver.
static void FLEXIO_HAL_SetTimerCompare(FLEXIO_Type *baseAddr, uint8_t timer, uint16_t value)
Configures the compare value for the specified timer.
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
flexio_spi_transfer_bit_order_t bitOrder
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
static void FLEXIO_HAL_SetTimerConfig(FLEXIO_Type *baseAddr, uint8_t timer, flexio_timer_start_t start, flexio_timer_stop_t stop, flexio_timer_enable_t enable, flexio_timer_disable_t disable, flexio_timer_reset_t reset, flexio_timer_decrement_t decrement, flexio_timer_output_t output)
Sets all configuration settings for specified timer.
static void EDMA_HAL_TCDSetDisableDmaRequestAfterTCDDoneCmd(DMA_Type *base, uint32_t channel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
static void EDMA_HAL_TCDSetDestOffset(DMA_Type *base, uint32_t channel, int16_t offset)
Configures the destination address signed offset for the TCD.
status_t FLEXIO_SPI_DRV_MasterInit(uint32_t instance, const flexio_spi_master_user_config_t *userConfigPtr, flexio_spi_master_state_t *master)
Initialize the FLEXIO_SPI master mode driver.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
flexio_pin_polarity_t
Pin polarity options Implements : flexio_pin_polarity_t_Class.
flexio_shifter_stop_t
Timer stop bit options - for Transmit, Receive or Match Store modes only Implements : flexio_shifter_...
flexio_device_state_t * g_flexioDeviceStatePtr[FLEXIO_INSTANCE_COUNT]
DMA_Type *const g_edmaBase[DMA_INSTANCE_COUNT]
Array for the eDMA module register base address.
status_t FLEXIO_SPI_DRV_MasterDeinit(flexio_spi_master_state_t *master)
De-initialize the FLEXIO_SPI master mode driver.
static bool FLEXIO_HAL_GetShifterStatus(const FLEXIO_Type *baseAddr, uint8_t shifter)
Returns the current status of the specified shifter.
static void FLEXIO_HAL_ClearShifterErrorStatus(FLEXIO_Type *baseAddr, uint8_t shifter)
Clears the error status of the specified shifter.
static void DMAMUX_HAL_SetChannelSource(DMAMUX_Type *base, uint32_t channel, uint8_t source)
Configures the DMA request for the DMAMUX channel.
static void FLEXIO_HAL_SetShifterErrorInterrupt(FLEXIO_Type *baseAddr, uint8_t interruptMask, bool enable)
Enables or disables the shifter error interrupts.
status_t FLEXIO_SPI_DRV_MasterTransferAbort(flexio_spi_master_state_t *master)
Aborts a non-blocking SPI master transaction.
Master internal context structure.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
static bool FLEXIO_HAL_GetShifterErrorStatus(const FLEXIO_Type *baseAddr, uint8_t shifter)
Returns the current error status of the specified shifter.
flexio_driver_type_t driverType
const clock_names_t g_flexioClock[FLEXIO_INSTANCE_COUNT]
status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t dataBufferSize)
Configures a simple single block data transfer with DMA.
flexio_callback_t callback
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
static void FLEXIO_HAL_ClearShifterStatus(FLEXIO_Type *baseAddr, uint8_t shifter)
Clears the status of the specified shifter.
static void FLEXIO_HAL_SetShifterDMARequest(FLEXIO_Type *baseAddr, uint8_t requestMask, bool enable)
Enables or disables the shifter DMA requests.