S32 SDK
scg_hal.c
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1 /*
2  * Copyright (c) 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
30 #include "scg_hal.h"
31 
32 
33 /******************************************************************************
34  * Definitions
35  *****************************************************************************/
36 
37 /* @brief System PLL base multiplier value, it is the multiplier value when SCG_SPLLCFG[MULT]=0. */
38 #define SCG_SPLL_MULT_BASE 16U
39 
40 /*
41  * @brief System PLL base divider value, it is the PLL reference clock divider value when
42  * SCG_SPLLCFG[PREDIV]=0.
43  */
44 #define SCG_SPLL_PREDIV_BASE 1U
45 
46 /*
47  * @brief System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the range of
48  * SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX.
49  */
50 #define SCG_SPLL_REF_MIN 8000000U
51 
52 /*
53  * @brief System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the range of
54  * SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX.
55  */
56 #define SCG_SPLL_REF_MAX 32000000U
57 
58 
59 #if FEATURE_SOC_SCG_COUNT
60 
61 /*FUNCTION*********************************************************************
62  *
63  * Function Name : SCG_HAL_GetSystemClockFreq
64  * Description : This function gets the SCG system clock frequency, these
65  * clocks are used for core, platform, external and bus clock domains.
66  *
67  * Implements SCG_HAL_GetSystemClockFreq_Activity
68  *END*************************************************************************/
69 uint32_t SCG_HAL_GetSystemClockFreq(const SCG_Type * base,
71 {
72  uint32_t freq;
73  uint32_t regValue;
75 
77 
78  switch(src)
79  {
81  freq = SCG_HAL_GetSysOscFreq(base);
82  break;
84  freq = SCG_HAL_GetSircFreq(base);
85  break;
87  freq = SCG_HAL_GetFircFreq(base);
88  break;
90  freq = SCG_HAL_GetSysPllFreq(base);
91  break;
92  default:
93  freq = 0U;
94  break;
95  }
96 
97  regValue = base->CSR;
98  regValue = (regValue & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT;
99  freq /= (regValue + 1U);
100 
101  switch(type)
102  {
104  /* Intentionally left blank */
105  break;
107  regValue = base->CSR;
108  regValue = (regValue & SCG_CSR_DIVBUS_MASK) >> SCG_CSR_DIVBUS_SHIFT;
109  freq /= (regValue + 1U);
110  break;
112  regValue = base->CSR;
113  regValue = (regValue & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT;
114  freq /= (regValue + 1U);
115  break;
116  default:
117  freq = 0U;
118  break;
119  }
120 
121  return freq;
122 }
123 
124 /*FUNCTION*********************************************************************
125  *
126  * Function Name : SCG_HAL_SetSystemClockConfig
127  * Description : This function sets the system configuration for the specified mode.
128  *
129  * Implements SCG_HAL_SetSystemClockConfig_Activity
130  *END*************************************************************************/
133  scg_system_clock_config_t const *config)
134 {
135  status_t status = STATUS_SUCCESS;
136  volatile uint32_t *regAddr = NULL; /* Address of the register that is written */
137  uint32_t srcFreq = 0U;
138  uint32_t value = (uint32_t)((((uint32_t)(config->src) << SCG_CSR_SCS_SHIFT) & SCG_CSR_SCS_MASK) |
139  (((uint32_t)(config->divCore) << SCG_CSR_DIVCORE_SHIFT) & SCG_CSR_DIVCORE_MASK) |
140  (((uint32_t)(config->divBus) << SCG_CSR_DIVBUS_SHIFT) & SCG_CSR_DIVBUS_MASK) |
141  (((uint32_t)(config->divSlow) << SCG_CSR_DIVSLOW_SHIFT) & SCG_CSR_DIVSLOW_MASK) );
142 
143  /* The maximum clock frequencies in all power modes */
144  static const uint32_t maxClocksFreq[MAX_FREQ_MODES_NO][MAX_FREQ_CLK_NO] = CLOCK_MAX_FREQUENCIES;
145  uint32_t maxFreqRunMode = 0U;
146  const uint32_t sysFreqMul = ((uint32_t)config->divCore) + 1UL;
147  const uint32_t busFreqMul = (((uint32_t)config->divCore) + 1UL) * (((uint32_t)config->divBus) + 1UL);
148  const uint32_t slowFreqMul = (((uint32_t)config->divCore) + 1UL) * (((uint32_t)config->divSlow) + 1UL);
149 
150 
152 
153  switch(config->src)
154  {
156  srcFreq = SCG_HAL_GetSysOscFreq(base);
157  break;
159  srcFreq = SCG_HAL_GetSircFreq(base);
160  break;
162  srcFreq = SCG_HAL_GetFircFreq(base);
163  break;
165  srcFreq = SCG_HAL_GetSysPllFreq(base);
166  break;
167  default:
168  srcFreq = 0U;
169  break;
170  }
171 
172 
173  switch (mode)
174  {
176  regAddr = &base->RCCR;
177  maxFreqRunMode = MAX_FREQ_RUN;
178  break;
181  (SCG_SYSTEM_CLOCK_SRC_SIRC == config->src));
182  regAddr = &base->VCCR;
183  maxFreqRunMode = MAX_FREQ_VLPR;
184  break;
186  regAddr = &base->VCCR;
187  base->HCCR = value;
188  maxFreqRunMode = MAX_FREQ_HSRUN;
189  break;
190  default:
191  /* Invalid mode */
192  DEV_ASSERT(false);
193  break;
194  }
195 
196  /* Verify the frequencies of sys, bus and slow clocks. */
197  if ((srcFreq > (sysFreqMul * maxClocksFreq[maxFreqRunMode][MAX_FREQ_SYS_CLK])) || /* Sys(core) clock */
198  (srcFreq > (busFreqMul * maxClocksFreq[maxFreqRunMode][MAX_FREQ_BUS_CLK])) || /* Bus clock */
199  (srcFreq > (slowFreqMul * maxClocksFreq[maxFreqRunMode][MAX_FREQ_SLOW_CLK]))) /* Slow clock */
200  {
201  /* Configuration for the next system clock source is not valid. */
202  status = STATUS_ERROR;
203  }
204 
205  if ((regAddr != NULL) && (status == STATUS_SUCCESS))
206  {
207  /* Write register. */
208  *regAddr = value;
209  }
210 
211  return status;
212 }
213 
214 /*FUNCTION*********************************************************************
215  *
216  * Function Name : SCG_HAL_GetSystemClockConfig
217  * Description : This function gets the system configuration for the specified mode.
218  *
219  * Implements SCG_HAL_GetSystemClockConfig_Activity
220  *END*************************************************************************/
221 void SCG_HAL_GetSystemClockConfig(const SCG_Type * base,
224 {
225  uint32_t value;
226  static const scg_system_clock_div_t systemClockDividerValues[] = {SCG_SYSTEM_CLOCK_DIV_BY_1,
230 
231  switch (mode)
232  {
234  value = base->CSR;
235  break;
237  value = base->RCCR;
238  break;
240  value = base->VCCR;
241  break;
243  value = base->HCCR;
244  break;
245  default:
246  value = 0U;
247  break;
248  }
249 
250  switch((value & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT)
251  {
252  case 1U:
254  break;
255  case 2U:
256  config->src = SCG_SYSTEM_CLOCK_SRC_SIRC;
257  break;
258  case 3U:
259  config->src = SCG_SYSTEM_CLOCK_SRC_FIRC;
260  break;
261  case 6U:
263  break;
264  default:
265  config->src = SCG_SYSTEM_CLOCK_SRC_NONE;
266  break;
267  }
268 
269  config->divCore = systemClockDividerValues[(value & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT];
270  config->divBus = systemClockDividerValues[(value & SCG_CSR_DIVBUS_MASK) >> SCG_CSR_DIVBUS_SHIFT ];
271  config->divSlow = systemClockDividerValues[(value & SCG_CSR_DIVSLOW_MASK) >> SCG_CSR_DIVSLOW_SHIFT];
272 }
273 
274 /*FUNCTION*********************************************************************
275  *
276  * Function Name : SCG_HAL_GetSysOscDefaultConfig
277  * Description : This function gets the default system OSC configuration.
278  *
279  * Implements SCG_HAL_GetSysOscDefaultConfig_Activity
280  *END*************************************************************************/
282 {
283  DEV_ASSERT(config != NULL);
284 
285  config->enableInStop = false;
286  config->enableInLowPower = false;
287 
289  config->locked = false;
290 
291  config->div1 = SCG_ASYNC_CLOCK_DISABLE;
292  config->div2 = SCG_ASYNC_CLOCK_DISABLE;
293 
294  config->extRef = SCG_SOSC_REF_EXT;
295  config->gain = SCG_SOSC_GAIN_LOW;
296  config->range = SCG_SOSC_RANGE_LOW;
297  config->initialize = true;
298 }
299 
300 /*FUNCTION*********************************************************************
301  *
302  * Function Name : SCG_HAL_InitSysOsc
303  * Description : This function enables the SCG system OSC clock according
304  * to the configuration.
305  *
306  * Implements SCG_HAL_InitSysOsc_Activity
307  *END*************************************************************************/
309  scg_sosc_config_t const *config)
310 {
311  status_t retStatus = STATUS_SUCCESS;
312  uint32_t regValue;
313 
314  DEV_ASSERT(config != NULL);
315  /* Control register can be written. */
317 
318  /* If clock is used by system, return error. */
320  {
321  retStatus = STATUS_BUSY;
322  }
323  else
324  {
325  /* Disable monitor, disable clock and clear error. */
327 
328  /* Now start to set up OSC clock. */
329  /* Step 1. Setup dividers. */
330  base->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(config->div1) |
331  SCG_SOSCDIV_SOSCDIV2(config->div2);
332  /* Step 2. Set OSC configuration. */
333  base->SOSCCFG = SCG_SOSCCFG_RANGE(config->range) |
334  SCG_SOSCCFG_HGO(config->gain) |
335  SCG_SOSCCFG_EREFS(config->extRef);
336  /* Step 3. Enable clock. */
337  base->SOSCCSR = SCG_SOSCCSR_SOSCEN(1U);
338  /* Step 4. Enable monitor. */
339  base->SOSCCSR = (base->SOSCCSR
343  | (uint32_t)config->monitorMode;
344 
345 
346  /* Step 4. Lock Control Status Register. */
347  regValue = (uint32_t)base->SOSCCSR;
348  regValue &= (uint32_t)(~(SCG_SOSCCSR_LK_MASK));
349  regValue |= SCG_SOSCCSR_LK(((config->locked) ? 1UL : 0UL));
350  base->SOSCCSR = (uint32_t)regValue;
351 
352  g_xtal0ClkFreq = config->freq;
353  }
354 
355  return retStatus;
356 }
357 
358 /*FUNCTION*********************************************************************
359  *
360  * Function Name : SCG_HAL_DeinitSysOsc
361  * Description : Disables the SCG System OSC clock.
362  *
363  * Implements SCG_HAL_DeinitSysOsc_Activity
364  *END*************************************************************************/
366 {
367  status_t retStatus = STATUS_SUCCESS;
368 
369  /* If clock is used by system, return error. */
371  {
372  retStatus = STATUS_BUSY;
373  }
374  else
375  {
376  /* Clear LK bit field */
377  base->SOSCCSR &= (uint32_t)(~(SCG_SOSCCSR_LK_MASK));
378 
379  /* Clear SOSCCSR */
381 
382  g_xtal0ClkFreq = 0U;
383  }
384  return retStatus;
385 }
386 
387 /*FUNCTION*********************************************************************
388  *
389  * Function Name : SCG_HAL_GetSysOscFreq
390  * Description : Get SCG System OSC clock frequency (SYSOSC).
391  *
392  * Implements SCG_HAL_GetSysOscFreq_Activity
393  *END*************************************************************************/
394 uint32_t SCG_HAL_GetSysOscFreq(const SCG_Type * base)
395 {
396  uint32_t retValue;
397  if (((base->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) >> SCG_SOSCCSR_SOSCVLD_SHIFT) != 0U) /* System OSC clock is valid. */
398  {
399  retValue = g_xtal0ClkFreq;
400  }
401  else
402  {
403  retValue = 0U;
404  }
405  return retValue;
406 }
407 
408 /*FUNCTION*********************************************************************
409  *
410  * Function Name : SCG_HAL_GetSysOscAsyncFreq
411  * Description : Get SCG asynchronous clock frequency from system OSC.
412  *
413  * Implements SCG_HAL_GetSysOscAsyncFreq_Activity
414  *END*************************************************************************/
415 uint32_t SCG_HAL_GetSysOscAsyncFreq(const SCG_Type * base,
417 {
418  uint32_t regValue, retValue, oscFreq, divider = 0U;
419 
420  oscFreq = SCG_HAL_GetSysOscFreq(base);
421 
422  /* Get divider. */
423  if (oscFreq != 0U)
424  {
425  switch (type)
426  {
428  regValue = base->SOSCDIV;
429  regValue = (regValue & SCG_SOSCDIV_SOSCDIV2_MASK) >> SCG_SOSCDIV_SOSCDIV2_SHIFT;
430  divider = regValue;
431  break;
433  regValue = base->SOSCDIV;
434  regValue = (regValue & SCG_SOSCDIV_SOSCDIV1_MASK) >> SCG_SOSCDIV_SOSCDIV1_SHIFT;
435  divider = regValue;
436  break;
437  default:
438  /* Invalid type */
439  DEV_ASSERT(false);
440  break;
441  }
442  }
443  if (divider != 0U)
444  {
445  retValue = (oscFreq >> (divider-1U));
446  }
447  else /* Output disabled. */
448  {
449  retValue = 0U;
450  }
451  return retValue;
452 }
453 
454 /*FUNCTION*********************************************************************
455  *
456  * Function Name : SCG_HAL_GetSircDefaultConfig
457  * Description : This function gets the default SIRC configuration.
458  *
459  * Implements SCG_HAL_GetSircDefaultConfig_Activity
460  *END*************************************************************************/
462 {
463  DEV_ASSERT(config != NULL);
464 
465  config->enableInStop = false;
466  config->enableInLowPower = true;
467  config->locked = false;
468  config->div1 = SCG_ASYNC_CLOCK_DISABLE;
469  config->div2 = SCG_ASYNC_CLOCK_DISABLE;
470  config->range = SCG_SIRC_RANGE_HIGH;
471  config->initialize = true;
472 }
473 
474 /*FUNCTION*********************************************************************
475  *
476  * Function Name : SCG_HAL_InitSirc
477  * Description : This function enables the SCG SIRC clock according
478  * to the configuration.
479  *
480  * Implements SCG_HAL_InitSirc_Activity
481  *END*************************************************************************/
483  const scg_sirc_config_t *config)
484 {
485  status_t retStatus = STATUS_SUCCESS;
486  uint32_t regValue;
487 
488  DEV_ASSERT(config != NULL);
489  /* Control register can be written. */
491 
492  /* If clock is used by system, return error. */
494  {
495  retStatus = STATUS_BUSY;
496  }
497  else
498  {
499  /* Disable clock. */
500  base->SIRCCSR &= (uint32_t)(~(SCG_SIRCCSR_SIRCEN_MASK));
501 
502  /* Now start to set up SIRC clock. */
503  /* Step 1. Setup dividers. */
504  base->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(config->div1) |
505  SCG_SIRCDIV_SIRCDIV2(config->div2);
506  /* Step 2. Set SIRC configuration. */
507  base->SIRCCFG = SCG_SIRCCFG_RANGE(config->range);
508  /* Step 3. Enable clock. */
509  base->SIRCCSR = SCG_SIRCCSR_SIRCEN(1U) |
510  SCG_SIRCCSR_SIRCSTEN(((config->enableInStop) ? 1UL : 0UL )) |
511  SCG_SIRCCSR_SIRCLPEN(((config->enableInLowPower) ? 1UL : 0UL ));
512  /* Step 4. Lock Control Status Register. */
513  regValue = (uint32_t)base->SIRCCSR;
514  regValue &= (uint32_t)(~(SCG_SIRCCSR_LK_MASK));
515  regValue |= SCG_SIRCCSR_LK(((config->locked) ? 1UL : 0UL));
516  base->SIRCCSR = (uint32_t)regValue;
517  }
518 
519  return retStatus;
520 }
521 
522 /*FUNCTION*********************************************************************
523  *
524  * Function Name : SCG_HAL_DeinitSirc
525  * Description : Disables the SCG slow IRC.
526  *
527  * Implements SCG_HAL_DeinitSirc_Activity
528  *END*************************************************************************/
530 {
531  status_t retStatus;
532 
533  /* If clock is used by system, return error. */
535  {
536  retStatus = STATUS_BUSY;
537  }
538  else
539  {
540  /* Clear LK bit field */
541  base->SIRCCSR &= (uint32_t)(~(SCG_SIRCCSR_LK_MASK));
542 
543  /* Clear SIRCCSR */
544  base->SIRCCSR = 0;
545 
546  retStatus = STATUS_SUCCESS;
547  }
548  return retStatus;
549 }
550 
551 /*FUNCTION*********************************************************************
552  *
553  * Function Name : SCG_HAL_GetSircFreq
554  * Description : Get SCG SIRC clock frequency.
555  *
556  * Implements SCG_HAL_GetSircFreq_Activity
557  *END*************************************************************************/
558 uint32_t SCG_HAL_GetSircFreq(const SCG_Type * base)
559 {
560  uint32_t retValue;
561 
562  if (((base->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) >> SCG_SIRCCSR_SIRCVLD_SHIFT) != 0U) /* SIRC is valid. */
563  {
564  retValue = (((base->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ?
566  }
567  else
568  {
569  retValue = 0U;
570  }
571  return retValue;
572 }
573 
574 /*FUNCTION*********************************************************************
575  *
576  * Function Name : SCG_HAL_GetSircAsyncFreq
577  * Description : Get SCG asynchronous clock frequency from SIRC.
578  *
579  * Implements SCG_HAL_GetSircAsyncFreq_Activity
580  *END*************************************************************************/
581 uint32_t SCG_HAL_GetSircAsyncFreq(const SCG_Type * base,
583 {
584  uint32_t regValue, retValue, sircFreq, divider = 0U;
585 
586  sircFreq = SCG_HAL_GetSircFreq(base);
587 
588  /* Get divider. */
589  if (sircFreq != 0U)
590  {
591  switch (type)
592  {
594  regValue = base->SIRCDIV;
595  regValue = (regValue & SCG_SIRCDIV_SIRCDIV2_MASK) >> SCG_SIRCDIV_SIRCDIV2_SHIFT;
596  divider = regValue;
597  break;
599  regValue = base->SIRCDIV;
600  regValue = (regValue & SCG_SIRCDIV_SIRCDIV1_MASK) >> SCG_SIRCDIV_SIRCDIV1_SHIFT;
601  divider = regValue;
602  break;
603  default:
604  /* Invalid type */
605  DEV_ASSERT(false);
606  break;
607  }
608  }
609  if (divider != 0U)
610  {
611  retValue = (sircFreq >> (divider-1U));
612  }
613  else /* Output disabled. */
614  {
615  retValue = 0U;
616  }
617  return retValue;
618 }
619 
620 /*FUNCTION*********************************************************************
621  *
622  * Function Name : SCG_HAL_GetFircDefaultConfig
623  * Description : This function gets the default FIRC configuration.
624  *
625  * Implements SCG_HAL_GetFircDefaultConfig_Activity
626  *END*************************************************************************/
628 {
629  DEV_ASSERT(config != NULL);
630 
631  config->enableInStop = false;
632  config->enableInLowPower = false;
633  config->regulator = true;
634  config->locked = false;
635 
636  config->div1 = SCG_ASYNC_CLOCK_DISABLE;
637  config->div2 = SCG_ASYNC_CLOCK_DISABLE;
638 
639  config->range = SCG_FIRC_RANGE_48M;
640 
641  config->initialize = true;
642 }
643 
644 /*FUNCTION*********************************************************************
645  *
646  * Function Name : SCG_HAL_InitFirc
647  * Description : This function enables the SCG FIRC clock according
648  * to the configuration.
649  *
650  * Implements SCG_HAL_InitFirc_Activity
651  *END*************************************************************************/
653  const scg_firc_config_t *config)
654 {
655  status_t retStatus = STATUS_SUCCESS;
656  uint32_t regValue;
657 
658  DEV_ASSERT(config != NULL);
659  /* Control register can be written. */
661 
662  /* If clock is used by system, return error. */
664  {
665  retStatus = STATUS_BUSY;
666  }
667  else
668  {
669  /* Disable clock. */
670  base->FIRCCSR &= (uint32_t)(~(SCG_FIRCCSR_FIRCEN_MASK));
671  /* Clear error. */
672  base->FIRCCSR |= SCG_FIRCCSR_FIRCERR(1U);
673 
674  /* Now start to set up FIRC clock. */
675  /* Step 1. Setup dividers. */
676  base->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(config->div1) |
677  SCG_FIRCDIV_FIRCDIV2(config->div2);
678 
679  /* Step 2. Set FIRC configuration. */
680  base->FIRCCFG = SCG_FIRCCFG_RANGE(config->range);
681 
682 
683  /* Step 3. Enable clock. */
684  base->FIRCCSR = (base->FIRCCSR
687  | (SCG_FIRCCSR_FIRCEN(1U) |
688  SCG_FIRCCSR_FIRCREGOFF((config->regulator ? 0UL : 1UL)));
689 
690 
691 
692  /* Step 5. Lock Control Status Register */
693  regValue = (uint32_t)base->FIRCCSR;
694  regValue &= (uint32_t)(~(SCG_FIRCCSR_LK_MASK));
695  regValue |= SCG_FIRCCSR_LK(((config->locked) ? 1UL : 0UL));
696  base->FIRCCSR = (uint32_t)regValue;
697 
698  /* Check if an error was detected */
700  {
701  retStatus = STATUS_ERROR;
702  }
703  }
704  return retStatus;
705 }
706 
707 /*FUNCTION*********************************************************************
708  *
709  * Function Name : SCG_HAL_DeinitFirc
710  * Description : Disables the SCG fast IRC.
711  *
712  * Implements SCG_HAL_DeinitFirc_Activity
713  *END*************************************************************************/
715 {
716  status_t retStatus = STATUS_SUCCESS;
717 
718  /* If clock is used by system, return error. */
720  {
721  retStatus = STATUS_BUSY;
722  }
723  else
724  {
725  /* Clear LK bit field */
726  base->FIRCCSR &= (uint32_t)(~(SCG_FIRCCSR_LK_MASK));
727 
728  /* Clear FIRCCSR */
730  }
731  return retStatus;
732 }
733 
734 /*FUNCTION*********************************************************************
735  *
736  * Function Name : SCG_HAL_GetFircFreq
737  * Description : Get SCG FIRC clock frequency.
738  *
739  * Implements SCG_HAL_GetFircFreq_Activity
740  *END*************************************************************************/
741 uint32_t SCG_HAL_GetFircFreq(const SCG_Type * base)
742 {
743  uint32_t retValue;
744 
745  static const uint32_t fircFreq[] = {
750  };
751 
752  if (((base->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) >> SCG_FIRCCSR_FIRCVLD_SHIFT) != 0U) /* FIRC is valid. */
753  {
754  uint32_t regValue = base->FIRCCFG;
755  regValue = (regValue & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
756  retValue = fircFreq[regValue];
757  }
758  else
759  {
760  retValue = 0U;
761  }
762  return retValue;
763 }
764 
765 /*FUNCTION*********************************************************************
766  *
767  * Function Name : SCG_HAL_GetFircAsyncFreq
768  * Description : Get SCG asynchronous clock frequency from FIRC.
769  *
770  * Implements SCG_HAL_GetFircAsyncFreq_Activity
771  *END*************************************************************************/
772 uint32_t SCG_HAL_GetFircAsyncFreq(const SCG_Type * base,
774 {
775  uint32_t fircFreq = SCG_HAL_GetFircFreq(base);
776  uint32_t regValue, retValue, divider = 0U;
777 
778  /* Get divider. */
779  if (fircFreq != 0U)
780  {
781  switch (type)
782  {
784  regValue = base->FIRCDIV;
785  regValue = (regValue & SCG_FIRCDIV_FIRCDIV2_MASK) >> SCG_FIRCDIV_FIRCDIV2_SHIFT;
786  divider = regValue;
787  break;
789  regValue = base->FIRCDIV;
790  regValue = (regValue & SCG_FIRCDIV_FIRCDIV1_MASK) >> SCG_FIRCDIV_FIRCDIV1_SHIFT;
791  divider = regValue;
792  break;
793  default:
794  /* Invalid type */
795  DEV_ASSERT(false);
796  break;
797  }
798  }
799  if (divider != 0U)
800  {
801  retValue = (fircFreq >> (divider-1U));
802  }
803  else /* Output disabled. */
804  {
805  retValue = 0U;
806  }
807  return retValue;
808 }
809 
810 /*FUNCTION*********************************************************************
811  *
812  * Function Name : SCG_HAL_GetSysPllDefaultConfig
813  * Description : This function gets the default system PLL configuration.
814  *
815  * Implements SCG_HAL_GetSysPllDefaultConfig_Activity
816  *END*************************************************************************/
818 {
819  DEV_ASSERT(config != NULL);
820 
821  config->enableInStop = false;
823  config->locked = false;
824 
825  config->div1 = SCG_ASYNC_CLOCK_DISABLE;
826  config->div2 = SCG_ASYNC_CLOCK_DISABLE;
827 
828  config->prediv = 0;
829  config->mult = 0;
830  config->src = 0;
831  config->initialize = true;
832 }
833 
834 /*FUNCTION*********************************************************************
835  *
836  * Function Name : SCG_HAL_InitSysPll
837  * Description : This function enables the SCG system PLL clock according
838  * to the configuration.
839  *
840  * Implements SCG_HAL_InitSysPll_Activity
841  *END*************************************************************************/
843  scg_spll_config_t const *config)
844 {
845  status_t retStatus = STATUS_SUCCESS;
846  uint32_t srcFreq, regValue;
847 
848  DEV_ASSERT(config != NULL);
849  /* Control register can be written. */
851 
852  /* If clock is used by system, return error. */
854  {
855  retStatus = STATUS_BUSY;
856  }
857  else
858  {
859  /* Get clock source frequency. */
860  srcFreq = SCG_HAL_GetSysOscFreq(base);
861 
862  DEV_ASSERT(srcFreq != 0U);
863 
864  /* Pre-divider checking. */
865  srcFreq /= (((uint32_t)config->prediv) + SCG_SPLL_PREDIV_BASE);
866 
867  DEV_ASSERT((srcFreq >= SCG_SPLL_REF_MIN) && (srcFreq <= SCG_SPLL_REF_MAX));
868 
869  /* Disable monitor, disable clock and clear error. */
871 
872  /* Now start to set up PLL clock. */
873  /* Step 1. Setup dividers. */
874  base->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(config->div1) |
875  SCG_SPLLDIV_SPLLDIV2(config->div2);
876  /* Step 2. Set PLL configuration. */
877  base->SPLLCFG = SCG_SPLLCFG_PREDIV(config->prediv) |
878  SCG_SPLLCFG_MULT(config->mult);
879  /* Step 3. Enable clock. */
880  base->SPLLCSR = SCG_SPLLCSR_SPLLEN(1U);
881  /* Step 4. Enable monitor. */
882  base->SPLLCSR = (base->SPLLCSR
886  | (uint32_t)config->monitorMode;
887 
888  /* Step 5. Lock Control Status Register */
889  regValue = (uint32_t)base->SPLLCSR;
890  regValue &= (uint32_t)(~(SCG_SPLLCSR_LK_MASK));
891  regValue |= SCG_SPLLCSR_LK(((config->locked) ? 1UL : 0UL));
892  base->SPLLCSR = (uint32_t)regValue;
893  }
894  return retStatus;
895 }
896 
897 /*FUNCTION*********************************************************************
898  *
899  * Function Name : SCG_HAL_DeinitSysPll
900  * Description : Disables the SCG system PLL.
901  *
902  * Implements SCG_HAL_DeinitSysPll_Activity
903  *END*************************************************************************/
905 {
906  status_t retStatus = STATUS_SUCCESS;
907 
908  /* If clock is used by system, return error. */
910  {
911  retStatus = STATUS_BUSY;
912  }
913  else
914  {
915  /* Clear LK bit field */
916  base->SPLLCSR &= (uint32_t)(~(SCG_SPLLCSR_LK_MASK));
917 
918  /* Clear SPLLCSR */
920  }
921  return retStatus;
922 }
923 
924 /*FUNCTION*********************************************************************
925  *
926  * Function Name : SCG_HAL_GetSysPllFreq
927  * Description : Get SCG system PLL clock frequency.
928  *
929  * Implements SCG_HAL_GetSysPllFreq_Activity
930  *END*************************************************************************/
931 uint32_t SCG_HAL_GetSysPllFreq(const SCG_Type * base)
932 {
933  uint32_t freq, regValue, retValue;
934 
935  if (((base->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) >> SCG_SPLLCSR_SPLLVLD_SHIFT) != 0U) /* System PLL is valid. */
936  {
937  /* Get System OSC. frequency. */
938  freq = SCG_HAL_GetSysOscFreq(base);
939 
940  if (freq != 0U) /* If source is valid. */
941  {
942  regValue = base->SPLLCFG;
943  regValue = (regValue & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT;
944  freq /= (regValue + SCG_SPLL_PREDIV_BASE); /* Pre-divider. */
945 
946  regValue = base->SPLLCFG;
947  regValue = (regValue & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT;
948  freq *= (regValue + SCG_SPLL_MULT_BASE); /* Multiplier. */
949 
950  freq = freq >> 1U; /* Divide VCO by 2. */
951  }
952 
953  retValue = freq;
954  }
955  else
956  {
957  retValue = 0U;
958  }
959  return retValue;
960 }
961 
962 /*FUNCTION*********************************************************************
963  *
964  * Function Name : SCG_HAL_GetSysPllAsyncFreq
965  * Description : Get SCG asynchronous clock frequency from system PLL.
966  *
967  * Implements SCG_HAL_GetSysPllAsyncFreq_Activity
968  *END*************************************************************************/
969 uint32_t SCG_HAL_GetSysPllAsyncFreq(const SCG_Type * base,
971 {
972  uint32_t pllFreq = SCG_HAL_GetSysPllFreq(base);
973  uint32_t regValue, retValue, divider = 0U;
974 
975  /* Get divider. */
976  if (pllFreq != 0U)
977  {
978  switch (type)
979  {
981  regValue = base->SPLLDIV;
982  regValue = (regValue & SCG_SPLLDIV_SPLLDIV2_MASK) >> SCG_SPLLDIV_SPLLDIV2_SHIFT;
983  divider = regValue;
984  break;
986  regValue = base->SPLLDIV;
987  regValue = (regValue & SCG_SPLLDIV_SPLLDIV1_MASK) >> SCG_SPLLDIV_SPLLDIV1_SHIFT;
988  divider = regValue;
989  break;
990  default:
991  /* Invalid type */
992  DEV_ASSERT(false);
993  break;
994  }
995  }
996  if (divider != 0U)
997  {
998  retValue = (pllFreq >> (divider-1U));
999  }
1000  else /* Output disabled. */
1001  {
1002  retValue = 0U;
1003  }
1004  return retValue;
1005 }
1006 
1007 /*FUNCTION*********************************************************************
1008  *
1009  * Function Name : SCG_HAL_SetRtcClkInFreq
1010  * Description : Configures SCG RTC CLKIN clock frequency.
1011  *
1012  * Implements SCG_HAL_SetRtcClkInFreq_Activity
1013  *END*************************************************************************/
1014 void SCG_HAL_SetRtcClkInFreq(SCG_Type * base, uint32_t frequency)
1015 {
1016  (void) (base);
1017  g_RtcClkInFreq = frequency;;
1018 }
1019 
1020 /*FUNCTION*********************************************************************
1021  *
1022  * Function Name : SCG_HAL_GetRtcClkInFreq
1023  * Description : Get SCG RTC CLKIN clock frequency.
1024  *
1025  * Implements SCG_HAL_GetRtcClkInFreq_Activity
1026  *END*************************************************************************/
1027 uint32_t SCG_HAL_GetRtcClkInFreq(SCG_Type * base)
1028 {
1029  (void) (base);
1030  return g_RtcClkInFreq;
1031 }
1032 
1033 #endif
1034 
1035 /******************************************************************************
1036  * EOF
1037  *****************************************************************************/
1038 
status_t SCG_HAL_InitSirc(SCG_Type *base, const scg_sirc_config_t *config)
Initialize SCG slow IRC clock.
#define SCG_SIRCDIV_SIRCDIV1(x)
Definition: S32K144.h:10586
void SCG_HAL_GetSystemClockConfig(const SCG_Type *base, scg_system_clock_mode_t mode, scg_system_clock_config_t *config)
Get the system clock configuration for specified mode.
scg_async_clock_div_t div1
Definition: scg_hal.h:332
scg_async_clock_div_t div2
Definition: scg_hal.h:297
#define SCG_SPLLCFG_MULT_MASK
Definition: S32K144.h:10678
#define SCG_SIRCCSR_LK(x)
Definition: S32K144.h:10573
#define SCG_CSR_DIVBUS_MASK
Definition: S32K144.h:10438
scg_async_clock_div_t div1
Definition: scg_hal.h:266
status_t SCG_HAL_InitSysOsc(SCG_Type *base, scg_sosc_config_t const *config)
Initialize SCG system OSC.
#define SCG_SPLLDIV_SPLLDIV2_SHIFT
Definition: S32K144.h:10670
#define SCG_SPLLCSR_LK_MASK
Definition: S32K144.h:10648
#define SCG_FIRCCSR_LK_MASK
Definition: S32K144.h:10605
#define MAX_FREQ_BUS_CLK
#define SCG_SPLLCSR_SPLLCM_MASK
Definition: S32K144.h:10640
#define SCG_SPLLCSR_SPLLVLD_MASK
Definition: S32K144.h:10652
scg_async_clock_div_t div2
Definition: scg_hal.h:267
scg_system_clock_mode_t
SCG system clock modes. Implements scg_system_clock_mode_t_Class.
Definition: scg_hal.h:87
#define SCG_FIRCCSR_FIRCVLD_MASK
Definition: S32K144.h:10609
scg_system_clock_type_t
SCG system clock type. Implements scg_system_clock_type_t_Class.
Definition: scg_hal.h:62
status_t SCG_HAL_DeinitFirc(SCG_Type *base)
De-initialize SCG fast IRC.
#define SCG_FIRCCFG_RANGE_SHIFT
Definition: S32K144.h:10632
#define MAX_FREQ_SLOW_CLK
#define SCG_FIRCCSR_FIRCERR(x)
Definition: S32K144.h:10620
#define MAX_FREQ_CLK_NO
uint32_t SCG_HAL_GetRtcClkInFreq(SCG_Type *base)
Get SCG RTC CLKIN clock frequency.
void SCG_HAL_SetRtcClkInFreq(SCG_Type *base, uint32_t frequency)
Set SCG RTC CLKIN clock frequency.
#define SCG_SOSCCSR_LK_MASK
Definition: S32K144.h:10519
status_t SCG_HAL_InitFirc(SCG_Type *base, const scg_firc_config_t *config)
Initialize SCG fast IRC clock.
uint32_t SCG_HAL_GetFircFreq(const SCG_Type *base)
Get SCG FIRC clock frequency.
#define SCG_FIRCCSR_FIRCREGOFF_MASK
Definition: S32K144.h:10601
#define SCG_SIRCCSR_SIRCLPEN(x)
Definition: S32K144.h:10569
#define SCG_SOSCDIV_SOSCDIV1_SHIFT
Definition: S32K144.h:10537
#define SCG_SIRCDIV_SIRCDIV1_SHIFT
Definition: S32K144.h:10584
#define SCG_SIRCCSR_SIRCSEL_SHIFT
Definition: S32K144.h:10579
scg_firc_range_t range
Definition: scg_hal.h:294
#define CLOCK_MAX_FREQUENCIES
#define SCG_SPLLCFG_PREDIV(x)
Definition: S32K144.h:10677
#define SCG_FIRCCSR_FIRCVLD_SHIFT
Definition: S32K144.h:10610
__IO uint32_t FIRCCFG
Definition: S32K144.h:10383
scg_sirc_range_t range
Definition: scg_hal.h:264
#define SCG_CSR_DIVSLOW_SHIFT
Definition: S32K144.h:10435
#define SCG_SOSCDIV_SOSCDIV2_MASK
Definition: S32K144.h:10540
#define MAX_FREQ_VLPR
Maximum frequencies of core, bus and flash clocks. Each entry represents the maximum frequency of SYS...
#define SCG_FIRCDIV_FIRCDIV1_MASK
Definition: S32K144.h:10622
#define SCG_SIRCCSR_SIRCSEL_MASK
Definition: S32K144.h:10578
scg_spll_monitor_mode_t monitorMode
Definition: scg_hal.h:326
scg_async_clock_div_t div2
Definition: scg_hal.h:238
uint8_t prediv
Definition: scg_hal.h:328
__IO uint32_t RCCR
Definition: S32K144.h:10368
#define SCG_CSR_SCS_MASK
Definition: S32K144.h:10446
#define SCG_SPLLDIV_SPLLDIV1_SHIFT
Definition: S32K144.h:10666
#define SCG_SOSCCFG_HGO(x)
Definition: S32K144.h:10552
__I uint32_t CSR
Definition: S32K144.h:10367
#define SCG_SIRCDIV_SIRCDIV1_MASK
Definition: S32K144.h:10583
#define SCG_SPLLCSR_LK_SHIFT
Definition: S32K144.h:10649
#define SCG_SIRCCSR_SIRCVLD_SHIFT
Definition: S32K144.h:10575
#define SCG_SOSCCFG_EREFS(x)
Definition: S32K144.h:10548
void SCG_HAL_GetSircDefaultConfig(scg_sirc_config_t *config)
Get the default slow IRC clock configuration.
#define SCG_FIRCDIV_FIRCDIV2_SHIFT
Definition: S32K144.h:10627
__IO uint32_t SIRCCSR
Definition: S32K144.h:10377
#define SCG_FIRCCFG_RANGE_MASK
Definition: S32K144.h:10631
#define MAX_FREQ_RUN
static scg_system_clock_src_t SCG_HAL_GetSystemClockSrc(const SCG_Type *base)
Get SCG system clock source.
Definition: scg_hal.h:727
status_t SCG_HAL_DeinitSirc(SCG_Type *base)
De-initialize SCG slow IRC.
#define SCG_SPLLCSR_LK(x)
Definition: S32K144.h:10651
#define SCG_FIRCCFG_RANGE(x)
Definition: S32K144.h:10634
#define FEATURE_SCG_FIRC_FREQ1
#define SCG_SOSCCSR_SOSCERR_MASK
Definition: S32K144.h:10531
#define SCG_CSR_DIVCORE_SHIFT
Definition: S32K144.h:10443
scg_sosc_ext_ref_t extRef
Definition: scg_hal.h:232
__IO uint32_t SIRCDIV
Definition: S32K144.h:10378
#define SCG_CSR_DIVSLOW_MASK
Definition: S32K144.h:10434
#define MAX_FREQ_HSRUN
uint32_t SCG_HAL_GetSysOscAsyncFreq(const SCG_Type *base, scg_async_clock_type_t type)
Get SCG asynchronous clock frequency from system OSC.
void SCG_HAL_GetSysPllDefaultConfig(scg_spll_config_t *config)
Get the default system PLL configuration.
#define SCG_SOSCCSR_SOSCSEL_SHIFT
Definition: S32K144.h:10528
#define SCG_SPLLCSR_SPLLSEL_SHIFT
Definition: S32K144.h:10657
uint32_t SCG_HAL_GetSircFreq(const SCG_Type *base)
Get SCG SIRC clock frequency.
__IO uint32_t VCCR
Definition: S32K144.h:10369
__IO uint32_t FIRCCSR
Definition: S32K144.h:10381
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
#define DEV_ASSERT(x)
Definition: devassert.h:78
uint32_t SCG_HAL_GetSysOscFreq(const SCG_Type *base)
Get SCG system OSC clock frequency (SYSOSC).
SCG system PLL configuration. Implements scg_spll_config_t_Class.
Definition: scg_hal.h:324
SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class.
Definition: scg_hal.h:262
#define SCG_SIRCCSR_SIRCSTEN(x)
Definition: S32K144.h:10565
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
Definition: scg_hal.h:292
#define SCG_CSR_DIVCORE_MASK
Definition: S32K144.h:10442
#define SCG_SOSCCSR_SOSCEN(x)
Definition: S32K144.h:10510
bool enableInLowPower
Definition: scg_hal.h:300
#define SCG_FIRCCSR_FIRCEN_MASK
Definition: S32K144.h:10597
#define SCG_SIRCCFG_RANGE(x)
Definition: S32K144.h:10595
#define FEATURE_SCG_FIRC_FREQ0
#define SCG_SPLL_REF_MIN
Definition: scg_hal.c:50
#define MAX_FREQ_MODES_NO
status_t SCG_HAL_DeinitSysPll(SCG_Type *base)
De-initialize SCG system PLL.
status_t SCG_HAL_SetSystemClockConfig(SCG_Type *base, scg_system_clock_mode_t mode, scg_system_clock_config_t const *config)
Set the system clock configuration in specified mode.
bool enableInLowPower
Definition: scg_hal.h:271
#define SCG_CSR_SCS_SHIFT
Definition: S32K144.h:10447
__IO uint32_t SIRCCFG
Definition: S32K144.h:10379
#define SCG_SOSCDIV_SOSCDIV2(x)
Definition: S32K144.h:10543
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:31
__IO uint32_t HCCR
Definition: S32K144.h:10370
bool enableInLowPower
Definition: scg_hal.h:241
scg_sosc_gain_t gain
Definition: scg_hal.h:233
scg_async_clock_div_t div1
Definition: scg_hal.h:296
void SCG_HAL_GetFircDefaultConfig(scg_firc_config_t *config)
Get the default fast IRC clock configuration.
SCG system clock configuration. Implements scg_system_clock_config_t_Class.
Definition: scg_hal.h:124
#define SCG_SPLLDIV_SPLLDIV1(x)
Definition: S32K144.h:10668
uint32_t SCG_HAL_GetSysPllAsyncFreq(const SCG_Type *base, scg_async_clock_type_t type)
Get SCG asynchronous clock frequency from system PLL.
#define SCG_SOSCCSR_LK_SHIFT
Definition: S32K144.h:10520
__IO uint32_t SPLLDIV
Definition: S32K144.h:10386
#define SCG_SPLL_MULT_BASE
Definition: scg_hal.c:38
#define SCG_FIRCDIV_FIRCDIV2(x)
Definition: S32K144.h:10629
__IO uint32_t SOSCCSR
Definition: S32K144.h:10373
#define FEATURE_SCG_SIRC_LOW_RANGE_FREQ
#define SCG_SIRCCSR_LK_MASK
Definition: S32K144.h:10570
#define SCG_SOSCCSR_SOSCVLD_MASK
Definition: S32K144.h:10523
#define SCG_SPLLCSR_SPLLSEL_MASK
Definition: S32K144.h:10656
#define SCG_SPLLCFG_MULT(x)
Definition: S32K144.h:10681
#define SCG_SPLLCSR_SPLLERR_MASK
Definition: S32K144.h:10660
scg_system_clock_div_t divCore
Definition: scg_hal.h:128
#define SCG_SPLLDIV_SPLLDIV2_MASK
Definition: S32K144.h:10669
scg_async_clock_div_t div2
Definition: scg_hal.h:333
#define SCG_SPLLCFG_PREDIV_MASK
Definition: S32K144.h:10674
scg_system_clock_div_t divSlow
Definition: scg_hal.h:126
#define SCG_FIRCCSR_FIRCSEL_SHIFT
Definition: S32K144.h:10614
status_t SCG_HAL_InitSysPll(SCG_Type *base, scg_spll_config_t const *config)
Initialize SCG system PLL.
__IO uint32_t SPLLCFG
Definition: S32K144.h:10387
#define SCG_SOSCCSR_LK(x)
Definition: S32K144.h:10522
#define SCG_SOSCCSR_SOSCCMRE_MASK
Definition: S32K144.h:10515
scg_system_clock_src_t
SCG system clock source. Implements scg_system_clock_src_t_Class.
Definition: scg_hal.h:74
status_t SCG_HAL_DeinitSysOsc(SCG_Type *base)
De-initialize SCG system OSC.
scg_async_clock_type_t
SCG asynchronous clock type. Implements scg_async_clock_type_t_Class.
Definition: scg_hal.h:156
__IO uint32_t FIRCDIV
Definition: S32K144.h:10382
#define SCG_SIRCDIV_SIRCDIV2_MASK
Definition: S32K144.h:10587
scg_async_clock_div_t div1
Definition: scg_hal.h:237
uint8_t mult
Definition: scg_hal.h:329
#define SCG_FIRCDIV_FIRCDIV1_SHIFT
Definition: S32K144.h:10623
#define SCG_SIRCCSR_LK_SHIFT
Definition: S32K144.h:10571
#define SCG_SOSCDIV_SOSCDIV2_SHIFT
Definition: S32K144.h:10541
scg_sosc_range_t range
Definition: scg_hal.h:235
uint32_t SCG_HAL_GetSysPllFreq(const SCG_Type *base)
Get SCG system PLL clock frequency.
#define FEATURE_SCG_FIRC_FREQ2
uint32_t SCG_HAL_GetSircAsyncFreq(const SCG_Type *base, scg_async_clock_type_t type)
Get SCG asynchronous clock frequency from SIRC.
#define SCG_SIRCCFG_RANGE_SHIFT
Definition: S32K144.h:10593
scg_sosc_monitor_mode_t monitorMode
Definition: scg_hal.h:230
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
Definition: scg_hal.h:226
#define SCG_SPLL_REF_MAX
Definition: scg_hal.c:56
#define SCG_FIRCCSR_FIRCEN(x)
Definition: S32K144.h:10600
#define SCG_SIRCDIV_SIRCDIV2_SHIFT
Definition: S32K144.h:10588
#define FEATURE_SCG_FIRC_FREQ3
uint32_t g_xtal0ClkFreq
Definition: clock_S32K144.c:73
#define SCG_FIRCCSR_LK_SHIFT
Definition: S32K144.h:10606
__IO uint32_t SPLLCSR
Definition: S32K144.h:10385
#define SCG_SIRCCSR_SIRCVLD_MASK
Definition: S32K144.h:10574
#define SCG_SIRCCSR_SIRCEN(x)
Definition: S32K144.h:10561
#define SCG_SOSCCSR_SOSCVLD_SHIFT
Definition: S32K144.h:10524
#define SCG_SPLLCSR_SPLLCMRE_MASK
Definition: S32K144.h:10644
#define SCG_SOSCCSR_SOSCCM_MASK
Definition: S32K144.h:10511
__IO uint32_t SOSCDIV
Definition: S32K144.h:10374
#define SCG_SOSCDIV_SOSCDIV1_MASK
Definition: S32K144.h:10536
#define SCG_SPLLDIV_SPLLDIV1_MASK
Definition: S32K144.h:10665
scg_system_clock_div_t
SCG system clock divider value. Implements scg_system_clock_div_t_Class.
Definition: scg_hal.h:100
#define SCG_FIRCCSR_FIRCERR_SHIFT
Definition: S32K144.h:10618
uint32_t freq
Definition: scg_hal.h:228
#define SCG_SPLLCFG_MULT_SHIFT
Definition: S32K144.h:10679
void SCG_HAL_GetSysOscDefaultConfig(scg_sosc_config_t *config)
Get the default system OSC configuration.
#define SCG_SPLLCFG_PREDIV_SHIFT
Definition: S32K144.h:10675
#define SCG_FIRCCSR_FIRCSEL_MASK
Definition: S32K144.h:10613
scg_system_clock_src_t src
Definition: scg_hal.h:129
#define SCG_FIRCDIV_FIRCDIV2_MASK
Definition: S32K144.h:10626
#define SCG_FIRCCSR_FIRCERR_MASK
Definition: S32K144.h:10617
#define SCG_FIRCCSR_LK(x)
Definition: S32K144.h:10608
#define MAX_FREQ_SYS_CLK
#define SCG_FIRCDIV_FIRCDIV1(x)
Definition: S32K144.h:10625
uint32_t SCG_HAL_GetFircAsyncFreq(const SCG_Type *base, scg_async_clock_type_t type)
Get SCG asynchronous clock frequency from FIRC.
#define SCG_SIRCCSR_SIRCEN_MASK
Definition: S32K144.h:10558
#define SCG_CSR_DIVBUS_SHIFT
Definition: S32K144.h:10439
#define SCG_SIRCCFG_RANGE_MASK
Definition: S32K144.h:10592
#define SCG_SOSCCFG_RANGE(x)
Definition: S32K144.h:10556
#define SCG_SOSCCSR_SOSCSEL_MASK
Definition: S32K144.h:10527
__IO uint32_t SOSCCFG
Definition: S32K144.h:10375
#define SCG_SOSCDIV_SOSCDIV1(x)
Definition: S32K144.h:10539
uint32_t g_RtcClkInFreq
Definition: clock_S32K144.c:70
uint32_t SCG_HAL_GetSystemClockFreq(const SCG_Type *base, scg_system_clock_type_t type)
Get SCG system clock frequency.
#define SCG_SPLLCSR_SPLLVLD_SHIFT
Definition: S32K144.h:10653
#define SCG_SPLLDIV_SPLLDIV2(x)
Definition: S32K144.h:10672
#define SCG_SPLL_PREDIV_BASE
Definition: scg_hal.c:44
#define SCG_FIRCCSR_FIRCREGOFF(x)
Definition: S32K144.h:10604
#define SCG_SPLLCSR_SPLLEN(x)
Definition: S32K144.h:10639
scg_system_clock_div_t divBus
Definition: scg_hal.h:127
#define SCG_SIRCDIV_SIRCDIV2(x)
Definition: S32K144.h:10590