S32 SDK

#include <S32K144.h>

Data Fields

uint8_t RESERVED_0 [8]
 
__I uint16_t PLASC
 
__I uint16_t PLAMC
 
__IO uint32_t CPCR
 
__IO uint32_t ISCR
 
uint8_t RESERVED_1 [28]
 
__IO uint32_t PID
 
uint8_t RESERVED_2 [12]
 
__IO uint32_t CPO
 
uint8_t RESERVED_3 [956]
 
__IO uint32_t LMDR [MCM_LMDR_COUNT]
 
__IO uint32_t LMDR2
 
uint8_t RESERVED_4 [116]
 
__IO uint32_t LMPECR
 
uint8_t RESERVED_5 [4]
 
__IO uint32_t LMPEIR
 
uint8_t RESERVED_6 [4]
 
__I uint32_t LMFAR
 
__I uint32_t LMFATR
 
uint8_t RESERVED_7 [8]
 
__I uint32_t LMFDHR
 
__I uint32_t LMFDLR
 

Detailed Description

MCM - Register Layout Typedef

Definition at line 7196 of file S32K144.h.

Field Documentation

__IO uint32_t CPCR

Core Platform Control Register, offset: 0xC

Definition at line 7200 of file S32K144.h.

__IO uint32_t CPO

Compute Operation Control Register, offset: 0x40

Definition at line 7205 of file S32K144.h.

__IO uint32_t ISCR

Interrupt Status and Control Register, offset: 0x10

Definition at line 7201 of file S32K144.h.

__IO uint32_t LMDR[MCM_LMDR_COUNT]

Local Memory Descriptor Register, array offset: 0x400, array step: 0x4

Definition at line 7207 of file S32K144.h.

__IO uint32_t LMDR2

Local Memory Descriptor Register2, offset: 0x408

Definition at line 7208 of file S32K144.h.

__I uint32_t LMFAR

LMEM Fault Address Register, offset: 0x490

Definition at line 7214 of file S32K144.h.

__I uint32_t LMFATR

LMEM Fault Attribute Register, offset: 0x494

Definition at line 7215 of file S32K144.h.

__I uint32_t LMFDHR

LMEM Fault Data High Register, offset: 0x4A0

Definition at line 7217 of file S32K144.h.

__I uint32_t LMFDLR

LMEM Fault Data Low Register, offset: 0x4A4

Definition at line 7218 of file S32K144.h.

__IO uint32_t LMPECR

LMEM Parity and ECC Control Register, offset: 0x480

Definition at line 7210 of file S32K144.h.

__IO uint32_t LMPEIR

LMEM Parity and ECC Interrupt Register, offset: 0x488

Definition at line 7212 of file S32K144.h.

__IO uint32_t PID

Process ID Register, offset: 0x30

Definition at line 7203 of file S32K144.h.

__I uint16_t PLAMC

Crossbar Switch (AXBS) Master Configuration, offset: 0xA

Definition at line 7199 of file S32K144.h.

__I uint16_t PLASC

Crossbar Switch (AXBS) Slave Configuration, offset: 0x8

Definition at line 7198 of file S32K144.h.

uint8_t RESERVED_0[8]

Definition at line 7197 of file S32K144.h.

uint8_t RESERVED_1[28]

Definition at line 7202 of file S32K144.h.

uint8_t RESERVED_2[12]

Definition at line 7204 of file S32K144.h.

uint8_t RESERVED_3[956]

Definition at line 7206 of file S32K144.h.

uint8_t RESERVED_4[116]

Definition at line 7209 of file S32K144.h.

uint8_t RESERVED_5[4]

Definition at line 7211 of file S32K144.h.

uint8_t RESERVED_6[4]

Definition at line 7213 of file S32K144.h.

uint8_t RESERVED_7[8]

Definition at line 7216 of file S32K144.h.


The documentation for this struct was generated from the following file: