timing_irq.c
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1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
37 #include "timing_irq.h"
38 #include "device_registers.h"
39 
40 /*******************************************************************************
41  * Code
42  ******************************************************************************/
43 
44 /* Define interrupt handler for Timing instance */
45 
46 /* Define TIMING PAL over LPIT */
47 #if (defined (TIMING_OVER_LPIT))
48 
49 #if (FEATURE_LPIT_HAS_NUM_IRQS_CHANS == 1)
50 void LPIT0_IRQHandler(void)
51 {
52  uint32_t chanIntFlags = LPIT_DRV_GetInterruptFlagTimerChannels(0U, 0xFU);
53  bool chan0IntFlag = ((chanIntFlags & LPIT_MSR_TIF0_MASK) != 0U) ? true : false;
54  bool chan1IntFlag = ((chanIntFlags & LPIT_MSR_TIF1_MASK) != 0U) ? true : false;
55  bool chan2IntFlag = ((chanIntFlags & LPIT_MSR_TIF2_MASK) != 0U) ? true : false;
56  bool chan3IntFlag = ((chanIntFlags & LPIT_MSR_TIF3_MASK) != 0U) ? true : false;
57 
58  if (chan0IntFlag)
59  {
60  TIMING_Lpit_IrqHandler(0U, 0U);
61  }
62 
63  if (chan1IntFlag)
64  {
65  TIMING_Lpit_IrqHandler(0U, 1U);
66  }
67 
68  if (chan2IntFlag)
69  {
70  TIMING_Lpit_IrqHandler(0U, 2U);
71  }
72 
73  if (chan3IntFlag)
74  {
75  TIMING_Lpit_IrqHandler(0U, 3U);
76  }
77 }
78 #else
79 void LPIT0_Ch0_IRQHandler(void)
80 {
81  TIMING_Lpit_IrqHandler(0U, 0U);
82 }
83 
84 void LPIT0_Ch1_IRQHandler(void)
85 {
86  TIMING_Lpit_IrqHandler(0U, 1U);
87 }
88 
89 void LPIT0_Ch2_IRQHandler(void)
90 {
91  TIMING_Lpit_IrqHandler(0U, 2U);
92 }
93 
94 void LPIT0_Ch3_IRQHandler(void)
95 {
96  TIMING_Lpit_IrqHandler(0U, 3U);
97 }
98 #endif /* FEATURE_LPIT_HAS_NUM_IRQS_CHANS == 1U */
99 
100 #endif /* TIMING_OVER_LPIT */
101 
102 /* Define TIMING PAL over LPTMR */
103 #if (defined (TIMING_OVER_LPTMR))
104 
105 void LPTMR0_IRQHandler(void)
106 {
107  TIMING_Lptmr_IrqHandler(0U, 0U);
108 }
109 
110 #endif /* TIMING_OVER_LPTMR */
111 
112 /* Define TIMING PAL over PIT */
113 #if (defined(TIMING_OVER_PIT))
114 
115 void PIT_Ch0_IRQHandler(void)
116 {
117  TIMING_Pit_IrqHandler(0U, 0U);
118 }
119 
120 void PIT_Ch1_IRQHandler(void)
121 {
122  TIMING_Pit_IrqHandler(0U, 1U);
123 }
124 
125 void PIT_Ch2_IRQHandler(void)
126 {
127  TIMING_Pit_IrqHandler(0U, 2U);
128 }
129 
130 void PIT_Ch3_IRQHandler(void)
131 {
132  TIMING_Pit_IrqHandler(0U, 3U);
133 }
134 #if (PIT_TIMER_COUNT > 4U)
135 void PIT_Ch4_IRQHandler(void)
136 {
137  TIMING_Pit_IrqHandler(0U, 4U);
138 }
139 
140 void PIT_Ch5_IRQHandler(void)
141 {
142  TIMING_Pit_IrqHandler(0U, 5U);
143 }
144 
145 void PIT_Ch6_IRQHandler(void)
146 {
147  TIMING_Pit_IrqHandler(0U, 6U);
148 }
149 
150 void PIT_Ch7_IRQHandler(void)
151 {
152  TIMING_Pit_IrqHandler(0U, 7U);
153 }
154 
155 void PIT_Ch8_IRQHandler(void)
156 {
157  TIMING_Pit_IrqHandler(0U, 8U);
158 }
159 
160 void PIT_Ch9_IRQHandler(void)
161 {
162  TIMING_Pit_IrqHandler(0U, 9U);
163 }
164 
165 void PIT_Ch10_IRQHandler(void)
166 {
167  TIMING_Pit_IrqHandler(0U, 10U);
168 }
169 
170 void PIT_Ch11_IRQHandler(void)
171 {
172  TIMING_Pit_IrqHandler(0U, 11U);
173 }
174 
175 void PIT_Ch12_IRQHandler(void)
176 {
177  TIMING_Pit_IrqHandler(0U, 12U);
178 }
179 
180 void PIT_Ch13_IRQHandler(void)
181 {
182  TIMING_Pit_IrqHandler(0U, 13U);
183 }
184 
185 void PIT_Ch14_IRQHandler(void)
186 {
187  TIMING_Pit_IrqHandler(0U, 14U);
188 }
189 
190 void PIT_Ch15_IRQHandler(void)
191 {
192  TIMING_Pit_IrqHandler(0U, 15U);
193 }
194 #endif /* PIT_TIMER_COUNT > 4U */
195 
196 #endif /* TIMING_OVER_PIT */
197 
198 /* Define TIMING PAL over FTM */
199 #if (defined(TIMING_OVER_FTM))
200 
201 #if (FTM_INSTANCE_COUNT > 0U)
202 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
203 void FTM0_Ch0_7_IrqHandler(void)
204 {
205  const FTM_Type * const base = ftmBase[0];
206  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
207  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
208  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
209  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
210  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
211  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
212  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
213  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
214 
215  if (chan0IntFlag && g_ftmChannelRunning[0][0])
216  {
217  TIMING_Ftm_IrqHandler(0U, 0U);
218  }
219 
220  if (chan1IntFlag && g_ftmChannelRunning[0][1])
221  {
222  TIMING_Ftm_IrqHandler(0U, 1U);
223  }
224 
225  if (chan2IntFlag && g_ftmChannelRunning[0][2])
226  {
227  TIMING_Ftm_IrqHandler(0U, 2U);
228  }
229 
230  if (chan3IntFlag && g_ftmChannelRunning[0][3])
231  {
232  TIMING_Ftm_IrqHandler(0U, 3U);
233  }
234 
235  if (chan4IntFlag && g_ftmChannelRunning[0][4])
236  {
237  TIMING_Ftm_IrqHandler(0U, 4U);
238  }
239 
240  if (chan5IntFlag && g_ftmChannelRunning[0][5])
241  {
242  TIMING_Ftm_IrqHandler(0U, 5U);
243  }
244 
245  if (chan6IntFlag && g_ftmChannelRunning[0][6])
246  {
247  TIMING_Ftm_IrqHandler(0U, 6U);
248  }
249 
250  if (chan7IntFlag && g_ftmChannelRunning[0][7])
251  {
252  TIMING_Ftm_IrqHandler(0U, 7U);
253  }
254 }
255 #else
256 void FTM0_Ch0_Ch1_IrqHandler(void)
257 {
258  const FTM_Type * const base = ftmBase[0];
259  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
260  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
261 
262  if (chan0IntFlag && g_ftmChannelRunning[0][0])
263  {
264  TIMING_Ftm_IrqHandler(0U, 0U);
265  }
266 
267  if (chan1IntFlag && g_ftmChannelRunning[0][1])
268  {
269  TIMING_Ftm_IrqHandler(0U, 1U);
270  }
271 }
272 
273 void FTM0_Ch2_Ch3_IrqHandler(void)
274 {
275  const FTM_Type * const base = ftmBase[0];
276  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
277  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
278 
279  if (chan2IntFlag && g_ftmChannelRunning[0][2])
280  {
281  TIMING_Ftm_IrqHandler(0U, 2U);
282  }
283 
284  if (chan3IntFlag && g_ftmChannelRunning[0][3])
285  {
286  TIMING_Ftm_IrqHandler(0U, 3U);
287  }
288 }
289 
290 void FTM0_Ch4_Ch5_IrqHandler(void)
291 {
292  const FTM_Type * const base = ftmBase[0];
293  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
294  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
295 
296  if (chan4IntFlag && g_ftmChannelRunning[0][4])
297  {
298  TIMING_Ftm_IrqHandler(0U, 4U);
299  }
300 
301  if (chan5IntFlag && g_ftmChannelRunning[0][5])
302  {
303  TIMING_Ftm_IrqHandler(0U, 5U);
304  }
305 }
306 
307 void FTM0_Ch6_Ch7_IrqHandler(void)
308 {
309  const FTM_Type * const base = ftmBase[0];
310  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
311  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
312 
313  if (chan6IntFlag && g_ftmChannelRunning[0][6])
314  {
315  TIMING_Ftm_IrqHandler(0U, 6U);
316  }
317 
318  if (chan7IntFlag && g_ftmChannelRunning[0][7])
319  {
320  TIMING_Ftm_IrqHandler(0U, 7U);
321  }
322 }
323 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
324 #endif /* FTM_INSTANCE_COUNT > 0U */
325 
326 #if (FTM_INSTANCE_COUNT > 1U)
327 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
328 void FTM1_Ch0_7_IrqHandler(void)
329 {
330  const FTM_Type * const base = ftmBase[1];
331  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
332  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
333  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
334  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
335  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
336  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
337  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
338  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
339 
340  if (chan0IntFlag && g_ftmChannelRunning[1][0])
341  {
342  TIMING_Ftm_IrqHandler(1U, 0U);
343  }
344 
345  if (chan1IntFlag && g_ftmChannelRunning[1][1])
346  {
347  TIMING_Ftm_IrqHandler(1U, 1U);
348  }
349 
350  if (chan2IntFlag && g_ftmChannelRunning[1][2])
351  {
352  TIMING_Ftm_IrqHandler(1U, 2U);
353  }
354 
355  if (chan3IntFlag && g_ftmChannelRunning[1][3])
356  {
357  TIMING_Ftm_IrqHandler(1U, 3U);
358  }
359 
360  if (chan4IntFlag && g_ftmChannelRunning[1][4])
361  {
362  TIMING_Ftm_IrqHandler(1U, 4U);
363  }
364 
365  if (chan5IntFlag && g_ftmChannelRunning[1][5])
366  {
367  TIMING_Ftm_IrqHandler(1U, 5U);
368  }
369 
370  if (chan6IntFlag && g_ftmChannelRunning[1][6])
371  {
372  TIMING_Ftm_IrqHandler(1U, 6U);
373  }
374 
375  if (chan7IntFlag && g_ftmChannelRunning[1][7])
376  {
377  TIMING_Ftm_IrqHandler(1U, 7U);
378  }
379 }
380 #else
381 void FTM1_Ch0_Ch1_IrqHandler(void)
382 {
383  const FTM_Type * const base = ftmBase[1];
384  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
385  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
386 
387  if (chan0IntFlag && g_ftmChannelRunning[1][0])
388  {
389  TIMING_Ftm_IrqHandler(1U, 0U);
390  }
391 
392  if (chan1IntFlag && g_ftmChannelRunning[1][1])
393  {
394  TIMING_Ftm_IrqHandler(1U, 1U);
395  }
396 }
397 
398 void FTM1_Ch2_Ch3_IrqHandler(void)
399 {
400  const FTM_Type * const base = ftmBase[1];
401  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
402  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
403 
404  if (chan2IntFlag && g_ftmChannelRunning[1][2])
405  {
406  TIMING_Ftm_IrqHandler(1U, 2U);
407  }
408 
409  if (chan3IntFlag && g_ftmChannelRunning[1][3])
410  {
411  TIMING_Ftm_IrqHandler(1U, 3U);
412  }
413 }
414 
415 void FTM1_Ch4_Ch5_IrqHandler(void)
416 {
417  const FTM_Type * const base = ftmBase[1];
418  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
419  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
420 
421  if (chan4IntFlag && g_ftmChannelRunning[1][4])
422  {
423  TIMING_Ftm_IrqHandler(1U, 4U);
424  }
425 
426  if (chan5IntFlag && g_ftmChannelRunning[1][5])
427  {
428  TIMING_Ftm_IrqHandler(1U, 5U);
429  }
430 }
431 
432 void FTM1_Ch6_Ch7_IrqHandler(void)
433 {
434  const FTM_Type * const base = ftmBase[1];
435  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
436  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
437 
438  if (chan6IntFlag && g_ftmChannelRunning[1][6])
439  {
440  TIMING_Ftm_IrqHandler(1U, 6U);
441  }
442 
443  if (chan7IntFlag && g_ftmChannelRunning[1][7])
444  {
445  TIMING_Ftm_IrqHandler(1U, 7U);
446  }
447 }
448 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
449 #endif /* FTM_INSTANCE_COUNT > 1U */
450 
451 #if (FTM_INSTANCE_COUNT > 2U)
452 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
453 void FTM2_Ch0_7_IrqHandler(void)
454 {
455  const FTM_Type * const base = ftmBase[2];
456  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
457  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
458  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
459  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
460  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
461  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
462  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
463  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
464 
465  if (chan0IntFlag && g_ftmChannelRunning[2][0])
466  {
467  TIMING_Ftm_IrqHandler(2U, 0U);
468  }
469 
470  if (chan1IntFlag && g_ftmChannelRunning[2][1])
471  {
472  TIMING_Ftm_IrqHandler(2U, 1U);
473  }
474 
475  if (chan2IntFlag && g_ftmChannelRunning[2][2])
476  {
477  TIMING_Ftm_IrqHandler(2U, 2U);
478  }
479 
480  if (chan3IntFlag && g_ftmChannelRunning[2][3])
481  {
482  TIMING_Ftm_IrqHandler(2U, 3U);
483  }
484 
485  if (chan4IntFlag && g_ftmChannelRunning[2][4])
486  {
487  TIMING_Ftm_IrqHandler(2U, 4U);
488  }
489 
490  if (chan5IntFlag && g_ftmChannelRunning[2][5])
491  {
492  TIMING_Ftm_IrqHandler(2U, 5U);
493  }
494 
495  if (chan6IntFlag && g_ftmChannelRunning[2][6])
496  {
497  TIMING_Ftm_IrqHandler(2U, 6U);
498  }
499 
500  if (chan7IntFlag && g_ftmChannelRunning[2][7])
501  {
502  TIMING_Ftm_IrqHandler(2U, 7U);
503  }
504 }
505 #else
506 void FTM2_Ch0_Ch1_IrqHandler(void)
507 {
508  const FTM_Type * const base = ftmBase[2];
509  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
510  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
511 
512  if (chan0IntFlag && g_ftmChannelRunning[2][0])
513  {
514  TIMING_Ftm_IrqHandler(2U, 0U);
515  }
516 
517  if (chan1IntFlag && g_ftmChannelRunning[2][1])
518  {
519  TIMING_Ftm_IrqHandler(2U, 1U);
520  }
521 }
522 
523 void FTM2_Ch2_Ch3_IrqHandler(void)
524 {
525  const FTM_Type * const base = ftmBase[2];
526  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
527  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
528 
529  if (chan2IntFlag && g_ftmChannelRunning[2][2])
530  {
531  TIMING_Ftm_IrqHandler(2U, 2U);
532  }
533 
534  if (chan3IntFlag && g_ftmChannelRunning[2][3])
535  {
536  TIMING_Ftm_IrqHandler(2U, 3U);
537  }
538 }
539 
540 void FTM2_Ch4_Ch5_IrqHandler(void)
541 {
542  const FTM_Type * const base = ftmBase[2];
543  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
544  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
545 
546  if (chan4IntFlag && g_ftmChannelRunning[2][4])
547  {
548  TIMING_Ftm_IrqHandler(2U, 4U);
549  }
550 
551  if (chan5IntFlag && g_ftmChannelRunning[2][5])
552  {
553  TIMING_Ftm_IrqHandler(2U, 5U);
554  }
555 }
556 
557 void FTM2_Ch6_Ch7_IrqHandler(void)
558 {
559  const FTM_Type * const base = ftmBase[2];
560  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
561  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
562 
563  if (chan6IntFlag && g_ftmChannelRunning[2][6])
564  {
565  TIMING_Ftm_IrqHandler(2U, 6U);
566  }
567 
568  if (chan7IntFlag && g_ftmChannelRunning[2][7])
569  {
570  TIMING_Ftm_IrqHandler(2U, 7U);
571  }
572 }
573 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
574 #endif /* FTM_INSTANCE_COUNT > 2U */
575 
576 #if (FTM_INSTANCE_COUNT > 3U)
577 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
578 void FTM3_Ch0_7_IrqHandler(void)
579 {
580  const FTM_Type * const base = ftmBase[3];
581  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
582  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
583  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
584  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
585  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
586  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
587  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
588  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
589 
590  if (chan0IntFlag && g_ftmChannelRunning[3][0])
591  {
592  TIMING_Ftm_IrqHandler(3U, 0U);
593  }
594 
595  if (chan1IntFlag && g_ftmChannelRunning[3][1])
596  {
597  TIMING_Ftm_IrqHandler(3U, 1U);
598  }
599 
600  if (chan2IntFlag && g_ftmChannelRunning[3][2])
601  {
602  TIMING_Ftm_IrqHandler(3U, 2U);
603  }
604 
605  if (chan3IntFlag && g_ftmChannelRunning[3][3])
606  {
607  TIMING_Ftm_IrqHandler(3U, 3U);
608  }
609 
610  if (chan4IntFlag && g_ftmChannelRunning[3][4])
611  {
612  TIMING_Ftm_IrqHandler(3U, 4U);
613  }
614 
615  if (chan5IntFlag && g_ftmChannelRunning[3][5])
616  {
617  TIMING_Ftm_IrqHandler(3U, 5U);
618  }
619 
620  if (chan6IntFlag && g_ftmChannelRunning[3][6])
621  {
622  TIMING_Ftm_IrqHandler(3U, 6U);
623  }
624 
625  if (chan7IntFlag && g_ftmChannelRunning[3][7])
626  {
627  TIMING_Ftm_IrqHandler(3U, 7U);
628  }
629 }
630 #else
631 void FTM3_Ch0_Ch1_IrqHandler(void)
632 {
633  const FTM_Type * const base = ftmBase[3];
634  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
635  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
636 
637  if (chan0IntFlag && g_ftmChannelRunning[3][0])
638  {
639  TIMING_Ftm_IrqHandler(3U, 0U);
640  }
641 
642  if (chan1IntFlag && g_ftmChannelRunning[3][1])
643  {
644  TIMING_Ftm_IrqHandler(3U, 1U);
645  }
646 }
647 
648 void FTM3_Ch2_Ch3_IrqHandler(void)
649 {
650  const FTM_Type * const base = ftmBase[3];
651  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
652  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
653 
654  if (chan2IntFlag && g_ftmChannelRunning[3][2])
655  {
656  TIMING_Ftm_IrqHandler(3U, 2U);
657  }
658 
659  if (chan3IntFlag && g_ftmChannelRunning[3][3])
660  {
661  TIMING_Ftm_IrqHandler(3U, 3U);
662  }
663 }
664 
665 void FTM3_Ch4_Ch5_IrqHandler(void)
666 {
667  const FTM_Type * const base = ftmBase[3];
668  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
669  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
670 
671  if (chan4IntFlag && g_ftmChannelRunning[3][4])
672  {
673  TIMING_Ftm_IrqHandler(3U, 4U);
674  }
675 
676  if (chan5IntFlag && g_ftmChannelRunning[3][5])
677  {
678  TIMING_Ftm_IrqHandler(3U, 5U);
679  }
680 }
681 
682 void FTM3_Ch6_Ch7_IrqHandler(void)
683 {
684  const FTM_Type * const base = ftmBase[3];
685  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
686  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
687 
688  if (chan6IntFlag && g_ftmChannelRunning[3][6])
689  {
690  TIMING_Ftm_IrqHandler(3U, 6U);
691  }
692 
693  if (chan7IntFlag && g_ftmChannelRunning[3][7])
694  {
695  TIMING_Ftm_IrqHandler(3U, 7U);
696  }
697 }
698 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
699 #endif /* FTM_INSTANCE_COUNT > 3U */
700 
701 #if (FTM_INSTANCE_COUNT > 4U)
702 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
703 void FTM4_Ch0_7_IrqHandler(void)
704 {
705  const FTM_Type * const base = ftmBase[4];
706  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
707  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
708  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
709  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
710  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
711  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
712  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
713  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
714 
715  if (chan0IntFlag && g_ftmChannelRunning[4][0])
716  {
717  TIMING_Ftm_IrqHandler(4U, 0U);
718  }
719 
720  if (chan1IntFlag && g_ftmChannelRunning[4][1])
721  {
722  TIMING_Ftm_IrqHandler(4U, 1U);
723  }
724 
725  if (chan2IntFlag && g_ftmChannelRunning[4][2])
726  {
727  TIMING_Ftm_IrqHandler(4U, 2U);
728  }
729 
730  if (chan3IntFlag && g_ftmChannelRunning[4][3])
731  {
732  TIMING_Ftm_IrqHandler(4U, 3U);
733  }
734 
735  if (chan4IntFlag && g_ftmChannelRunning[4][4])
736  {
737  TIMING_Ftm_IrqHandler(4U, 4U);
738  }
739 
740  if (chan5IntFlag && g_ftmChannelRunning[4][5])
741  {
742  TIMING_Ftm_IrqHandler(4U, 5U);
743  }
744 
745  if (chan6IntFlag && g_ftmChannelRunning[4][6])
746  {
747  TIMING_Ftm_IrqHandler(4U, 6U);
748  }
749 
750  if (chan7IntFlag && g_ftmChannelRunning[4][7])
751  {
752  TIMING_Ftm_IrqHandler(4U, 7U);
753  }
754 }
755 #else
756 void FTM4_Ch0_Ch1_IrqHandler(void)
757 {
758  const FTM_Type * const base = ftmBase[4];
759  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
760  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
761 
762  if (chan0IntFlag && g_ftmChannelRunning[4][0])
763  {
764  TIMING_Ftm_IrqHandler(4U, 0U);
765  }
766 
767  if (chan1IntFlag && g_ftmChannelRunning[4][1])
768  {
769  TIMING_Ftm_IrqHandler(4U, 1U);
770  }
771 }
772 
773 void FTM4_Ch2_Ch3_IrqHandler(void)
774 {
775  const FTM_Type * const base = ftmBase[4];
776  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
777  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
778 
779  if (chan2IntFlag && g_ftmChannelRunning[4][2])
780  {
781  TIMING_Ftm_IrqHandler(4U, 2U);
782  }
783 
784  if (chan3IntFlag && g_ftmChannelRunning[4][3])
785  {
786  TIMING_Ftm_IrqHandler(4U, 3U);
787  }
788 }
789 
790 void FTM4_Ch4_Ch5_IrqHandler(void)
791 {
792  const FTM_Type * const base = ftmBase[4];
793  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
794  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
795 
796  if (chan4IntFlag && g_ftmChannelRunning[4][4])
797  {
798  TIMING_Ftm_IrqHandler(4U, 4U);
799  }
800 
801  if (chan5IntFlag && g_ftmChannelRunning[4][5])
802  {
803  TIMING_Ftm_IrqHandler(4U, 5U);
804  }
805 }
806 
807 void FTM4_Ch6_Ch7_IrqHandler(void)
808 {
809  const FTM_Type * const base = ftmBase[4];
810  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
811  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
812 
813  if (chan6IntFlag && g_ftmChannelRunning[4][6])
814  {
815  TIMING_Ftm_IrqHandler(4U, 6U);
816  }
817 
818  if (chan7IntFlag && g_ftmChannelRunning[4][7])
819  {
820  TIMING_Ftm_IrqHandler(4U, 7U);
821  }
822 }
823 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
824 #endif /* FTM_INSTANCE_COUNT > 4U */
825 
826 #if (FTM_INSTANCE_COUNT > 5U)
827 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
828 void FTM5_Ch0_7_IrqHandler(void)
829 {
830  const FTM_Type * const base = ftmBase[5];
831  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
832  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
833  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
834  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
835  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
836  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
837  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
838  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
839 
840  if (chan0IntFlag && g_ftmChannelRunning[5][0])
841  {
842  TIMING_Ftm_IrqHandler(5U, 0U);
843  }
844 
845  if (chan1IntFlag && g_ftmChannelRunning[5][1])
846  {
847  TIMING_Ftm_IrqHandler(5U, 1U);
848  }
849 
850  if (chan2IntFlag && g_ftmChannelRunning[5][2])
851  {
852  TIMING_Ftm_IrqHandler(5U, 2U);
853  }
854 
855  if (chan3IntFlag && g_ftmChannelRunning[5][3])
856  {
857  TIMING_Ftm_IrqHandler(5U, 3U);
858  }
859 
860  if (chan4IntFlag && g_ftmChannelRunning[5][4])
861  {
862  TIMING_Ftm_IrqHandler(5U, 4U);
863  }
864 
865  if (chan5IntFlag && g_ftmChannelRunning[5][5])
866  {
867  TIMING_Ftm_IrqHandler(5U, 5U);
868  }
869 
870  if (chan6IntFlag && g_ftmChannelRunning[5][6])
871  {
872  TIMING_Ftm_IrqHandler(5U, 6U);
873  }
874 
875  if (chan7IntFlag && g_ftmChannelRunning[5][7])
876  {
877  TIMING_Ftm_IrqHandler(5U, 7U);
878  }
879 }
880 #else
881 void FTM5_Ch0_Ch1_IrqHandler(void)
882 {
883  const FTM_Type * const base = ftmBase[5];
884  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
885  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
886 
887  if (chan0IntFlag && g_ftmChannelRunning[5][0])
888  {
889  TIMING_Ftm_IrqHandler(5U, 0U);
890  }
891 
892  if (chan1IntFlag && g_ftmChannelRunning[5][1])
893  {
894  TIMING_Ftm_IrqHandler(5U, 1U);
895  }
896 }
897 
898 void FTM5_Ch2_Ch3_IrqHandler(void)
899 {
900  const FTM_Type * const base = ftmBase[5];
901  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
902  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
903 
904  if (chan2IntFlag && g_ftmChannelRunning[5][2])
905  {
906  TIMING_Ftm_IrqHandler(5U, 2U);
907  }
908 
909  if (chan3IntFlag && g_ftmChannelRunning[5][3])
910  {
911  TIMING_Ftm_IrqHandler(5U, 3U);
912  }
913 }
914 
915 void FTM5_Ch4_Ch5_IrqHandler(void)
916 {
917  const FTM_Type * const base = ftmBase[5];
918  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
919  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
920 
921  if (chan4IntFlag && g_ftmChannelRunning[5][4])
922  {
923  TIMING_Ftm_IrqHandler(5U, 4U);
924  }
925 
926  if (chan5IntFlag && g_ftmChannelRunning[5][5])
927  {
928  TIMING_Ftm_IrqHandler(5U, 5U);
929  }
930 }
931 
932 void FTM5_Ch6_Ch7_IrqHandler(void)
933 {
934  const FTM_Type * const base = ftmBase[5];
935  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
936  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
937 
938  if (chan6IntFlag && g_ftmChannelRunning[5][6])
939  {
940  TIMING_Ftm_IrqHandler(5U, 6U);
941  }
942 
943  if (chan7IntFlag && g_ftmChannelRunning[5][7])
944  {
945  TIMING_Ftm_IrqHandler(5U, 7U);
946  }
947 }
948 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
949 #endif /* FTM_INSTANCE_COUNT > 5U */
950 
951 #if (FTM_INSTANCE_COUNT > 6U)
952 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
953 void FTM6_Ch0_7_IrqHandler(void)
954 {
955  const FTM_Type * const base = ftmBase[6];
956  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
957  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
958  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
959  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
960  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
961  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
962  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
963  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
964 
965  if (chan0IntFlag && g_ftmChannelRunning[6][0])
966  {
967  TIMING_Ftm_IrqHandler(6U, 0U);
968  }
969 
970  if (chan1IntFlag && g_ftmChannelRunning[6][1])
971  {
972  TIMING_Ftm_IrqHandler(6U, 1U);
973  }
974 
975  if (chan2IntFlag && g_ftmChannelRunning[6][2])
976  {
977  TIMING_Ftm_IrqHandler(6U, 2U);
978  }
979 
980  if (chan3IntFlag && g_ftmChannelRunning[6][3])
981  {
982  TIMING_Ftm_IrqHandler(6U, 3U);
983  }
984 
985  if (chan4IntFlag && g_ftmChannelRunning[6][4])
986  {
987  TIMING_Ftm_IrqHandler(6U, 4U);
988  }
989 
990  if (chan5IntFlag && g_ftmChannelRunning[6][5])
991  {
992  TIMING_Ftm_IrqHandler(6U, 5U);
993  }
994 
995  if (chan6IntFlag && g_ftmChannelRunning[6][6])
996  {
997  TIMING_Ftm_IrqHandler(6U, 6U);
998  }
999 
1000  if (chan7IntFlag && g_ftmChannelRunning[6][7])
1001  {
1002  TIMING_Ftm_IrqHandler(6U, 7U);
1003  }
1004 }
1005 #else
1006 void FTM6_Ch0_Ch1_IrqHandler(void)
1007 {
1008  const FTM_Type * const base = ftmBase[6];
1009  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
1010  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
1011 
1012  if (chan0IntFlag && g_ftmChannelRunning[6][0])
1013  {
1014  TIMING_Ftm_IrqHandler(6U, 0U);
1015  }
1016 
1017  if (chan1IntFlag && g_ftmChannelRunning[6][1])
1018  {
1019  TIMING_Ftm_IrqHandler(6U, 1U);
1020  }
1021 }
1022 
1023 void FTM6_Ch2_Ch3_IrqHandler(void)
1024 {
1025  const FTM_Type * const base = ftmBase[6];
1026  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
1027  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
1028 
1029  if (chan2IntFlag && g_ftmChannelRunning[6][2])
1030  {
1031  TIMING_Ftm_IrqHandler(6U, 2U);
1032  }
1033 
1034  if (chan3IntFlag && g_ftmChannelRunning[6][3])
1035  {
1036  TIMING_Ftm_IrqHandler(6U, 3U);
1037  }
1038 }
1039 
1040 void FTM6_Ch4_Ch5_IrqHandler(void)
1041 {
1042  const FTM_Type * const base = ftmBase[6];
1043  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
1044  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
1045 
1046  if (chan4IntFlag && g_ftmChannelRunning[6][4])
1047  {
1048  TIMING_Ftm_IrqHandler(6U, 4U);
1049  }
1050 
1051  if (chan5IntFlag && g_ftmChannelRunning[6][5])
1052  {
1053  TIMING_Ftm_IrqHandler(6U, 5U);
1054  }
1055 }
1056 
1057 void FTM6_Ch6_Ch7_IrqHandler(void)
1058 {
1059  const FTM_Type * const base = ftmBase[6];
1060  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
1061  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
1062 
1063  if (chan6IntFlag && g_ftmChannelRunning[6][6])
1064  {
1065  TIMING_Ftm_IrqHandler(6U, 6U);
1066  }
1067 
1068  if (chan7IntFlag && g_ftmChannelRunning[6][7])
1069  {
1070  TIMING_Ftm_IrqHandler(6U, 7U);
1071  }
1072 }
1073 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1074 #endif /* FTM_INSTANCE_COUNT > 6U */
1075 
1076 #if (FTM_INSTANCE_COUNT > 7U)
1077 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1078 void FTM7_Ch0_7_IrqHandler(void)
1079 {
1080  const FTM_Type * const base = ftmBase[7];
1081  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
1082  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
1083  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
1084  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
1085  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
1086  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
1087  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
1088  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
1089 
1090  if (chan0IntFlag && g_ftmChannelRunning[7][0])
1091  {
1092  TIMING_Ftm_IrqHandler(7U, 0U);
1093  }
1094 
1095  if (chan1IntFlag && g_ftmChannelRunning[7][1])
1096  {
1097  TIMING_Ftm_IrqHandler(7U, 1U);
1098  }
1099 
1100  if (chan2IntFlag && g_ftmChannelRunning[7][2])
1101  {
1102  TIMING_Ftm_IrqHandler(7U, 2U);
1103  }
1104 
1105  if (chan3IntFlag && g_ftmChannelRunning[7][3])
1106  {
1107  TIMING_Ftm_IrqHandler(7U, 3U);
1108  }
1109 
1110  if (chan4IntFlag && g_ftmChannelRunning[7][4])
1111  {
1112  TIMING_Ftm_IrqHandler(7U, 4U);
1113  }
1114 
1115  if (chan5IntFlag && g_ftmChannelRunning[7][5])
1116  {
1117  TIMING_Ftm_IrqHandler(7U, 5U);
1118  }
1119 
1120  if (chan6IntFlag && g_ftmChannelRunning[7][6])
1121  {
1122  TIMING_Ftm_IrqHandler(7U, 6U);
1123  }
1124 
1125  if (chan7IntFlag && g_ftmChannelRunning[7][7])
1126  {
1127  TIMING_Ftm_IrqHandler(7U, 7U);
1128  }
1129 }
1130 #else
1131 void FTM7_Ch0_Ch1_IrqHandler(void)
1132 {
1133  const FTM_Type * const base = ftmBase[7];
1134  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
1135  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
1136 
1137  if (chan0IntFlag && g_ftmChannelRunning[7][0])
1138  {
1139  TIMING_Ftm_IrqHandler(7U, 0U);
1140  }
1141 
1142  if (chan1IntFlag && g_ftmChannelRunning[7][1])
1143  {
1144  TIMING_Ftm_IrqHandler(7U, 1U);
1145  }
1146 }
1147 
1148 void FTM7_Ch2_Ch3_IrqHandler(void)
1149 {
1150  const FTM_Type * const base = ftmBase[7];
1151  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
1152  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
1153 
1154  if (chan2IntFlag && g_ftmChannelRunning[7][2])
1155  {
1156  TIMING_Ftm_IrqHandler(7U, 2U);
1157  }
1158 
1159  if (chan3IntFlag && g_ftmChannelRunning[7][3])
1160  {
1161  TIMING_Ftm_IrqHandler(7U, 3U);
1162  }
1163 }
1164 
1165 void FTM7_Ch4_Ch5_IrqHandler(void)
1166 {
1167  const FTM_Type * const base = ftmBase[7];
1168  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
1169  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
1170 
1171  if (chan4IntFlag && g_ftmChannelRunning[7][4])
1172  {
1173  TIMING_Ftm_IrqHandler(7U, 4U);
1174  }
1175 
1176  if (chan5IntFlag && g_ftmChannelRunning[7][5])
1177  {
1178  TIMING_Ftm_IrqHandler(7U, 5U);
1179  }
1180 }
1181 
1182 void FTM7_Ch6_Ch7_IrqHandler(void)
1183 {
1184  const FTM_Type * const base = ftmBase[7];
1185  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
1186  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
1187 
1188  if (chan6IntFlag && g_ftmChannelRunning[7][6])
1189  {
1190  TIMING_Ftm_IrqHandler(7U, 6U);
1191  }
1192 
1193  if (chan7IntFlag && g_ftmChannelRunning[7][7])
1194  {
1195  TIMING_Ftm_IrqHandler(7U, 7U);
1196  }
1197 }
1198 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1199 #endif /* FTM_INSTANCE_COUNT > 7U */
1200 
1201 /* Array storing references to TIMING over FTM irq handlers */
1202 const isr_t s_timingOverFtmIsr[FTM_INSTANCE_COUNT][FTM_CONTROLS_COUNT] =
1203 {
1204 #if (FTM_INSTANCE_COUNT > 0U)
1205 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1206  {FTM0_Ch0_7_IrqHandler,
1207  FTM0_Ch0_7_IrqHandler,
1208  FTM0_Ch0_7_IrqHandler,
1209  FTM0_Ch0_7_IrqHandler,
1210  FTM0_Ch0_7_IrqHandler,
1211  FTM0_Ch0_7_IrqHandler,
1212  FTM0_Ch0_7_IrqHandler,
1213  FTM0_Ch0_7_IrqHandler},
1214 #else
1215  {FTM0_Ch0_Ch1_IrqHandler,
1216  FTM0_Ch0_Ch1_IrqHandler,
1217  FTM0_Ch2_Ch3_IrqHandler,
1218  FTM0_Ch2_Ch3_IrqHandler,
1219  FTM0_Ch4_Ch5_IrqHandler,
1220  FTM0_Ch4_Ch5_IrqHandler,
1221  FTM0_Ch6_Ch7_IrqHandler,
1222  FTM0_Ch6_Ch7_IrqHandler},
1223 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1224 #endif /* FTM_INSTANCE_COUNT > 0U */
1225 
1226 #if (FTM_INSTANCE_COUNT > 1U)
1227 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1228  {FTM1_Ch0_7_IrqHandler,
1229  FTM1_Ch0_7_IrqHandler,
1230  FTM1_Ch0_7_IrqHandler,
1231  FTM1_Ch0_7_IrqHandler,
1232  FTM1_Ch0_7_IrqHandler,
1233  FTM1_Ch0_7_IrqHandler,
1234  FTM1_Ch0_7_IrqHandler,
1235  FTM1_Ch0_7_IrqHandler},
1236 #else
1237  {FTM1_Ch0_Ch1_IrqHandler,
1238  FTM1_Ch0_Ch1_IrqHandler,
1239  FTM1_Ch2_Ch3_IrqHandler,
1240  FTM1_Ch2_Ch3_IrqHandler,
1241  FTM1_Ch4_Ch5_IrqHandler,
1242  FTM1_Ch4_Ch5_IrqHandler,
1243  FTM1_Ch6_Ch7_IrqHandler,
1244  FTM1_Ch6_Ch7_IrqHandler},
1245 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1246 #endif /* FTM_INSTANCE_COUNT > 1U */
1247 
1248 #if (FTM_INSTANCE_COUNT > 2U)
1249 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1250  {FTM2_Ch0_7_IrqHandler,
1251  FTM2_Ch0_7_IrqHandler,
1252  FTM2_Ch0_7_IrqHandler,
1253  FTM2_Ch0_7_IrqHandler,
1254  FTM2_Ch0_7_IrqHandler,
1255  FTM2_Ch0_7_IrqHandler,
1256  FTM2_Ch0_7_IrqHandler,
1257  FTM2_Ch0_7_IrqHandler},
1258 #else
1259  {FTM2_Ch0_Ch1_IrqHandler,
1260  FTM2_Ch0_Ch1_IrqHandler,
1261  FTM2_Ch2_Ch3_IrqHandler,
1262  FTM2_Ch2_Ch3_IrqHandler,
1263  FTM2_Ch4_Ch5_IrqHandler,
1264  FTM2_Ch4_Ch5_IrqHandler,
1265  FTM2_Ch6_Ch7_IrqHandler,
1266  FTM2_Ch6_Ch7_IrqHandler},
1267 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1268 #endif /* FTM_INSTANCE_COUNT > 2U */
1269 
1270 #if (FTM_INSTANCE_COUNT > 3U)
1271 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1272  {FTM3_Ch0_7_IrqHandler,
1273  FTM3_Ch0_7_IrqHandler,
1274  FTM3_Ch0_7_IrqHandler,
1275  FTM3_Ch0_7_IrqHandler,
1276  FTM3_Ch0_7_IrqHandler,
1277  FTM3_Ch0_7_IrqHandler,
1278  FTM3_Ch0_7_IrqHandler,
1279  FTM3_Ch0_7_IrqHandler},
1280 #else
1281  {FTM3_Ch0_Ch1_IrqHandler,
1282  FTM3_Ch0_Ch1_IrqHandler,
1283  FTM3_Ch2_Ch3_IrqHandler,
1284  FTM3_Ch2_Ch3_IrqHandler,
1285  FTM3_Ch4_Ch5_IrqHandler,
1286  FTM3_Ch4_Ch5_IrqHandler,
1287  FTM3_Ch6_Ch7_IrqHandler,
1288  FTM3_Ch6_Ch7_IrqHandler},
1289 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1290 #endif /* FTM_INSTANCE_COUNT > 3U */
1291 
1292 #if (FTM_INSTANCE_COUNT > 4U)
1293 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1294  {FTM4_Ch0_7_IrqHandler,
1295  FTM4_Ch0_7_IrqHandler,
1296  FTM4_Ch0_7_IrqHandler,
1297  FTM4_Ch0_7_IrqHandler,
1298  FTM4_Ch0_7_IrqHandler,
1299  FTM4_Ch0_7_IrqHandler,
1300  FTM4_Ch0_7_IrqHandler,
1301  FTM4_Ch0_7_IrqHandler},
1302 #else
1303  {FTM4_Ch0_Ch1_IrqHandler,
1304  FTM4_Ch0_Ch1_IrqHandler,
1305  FTM4_Ch2_Ch3_IrqHandler,
1306  FTM4_Ch2_Ch3_IrqHandler,
1307  FTM4_Ch4_Ch5_IrqHandler,
1308  FTM4_Ch4_Ch5_IrqHandler,
1309  FTM4_Ch6_Ch7_IrqHandler,
1310  FTM4_Ch6_Ch7_IrqHandler},
1311 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1312 #endif /* FTM_INSTANCE_COUNT > 4U */
1313 
1314 #if (FTM_INSTANCE_COUNT > 5U)
1315 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1316  {FTM5_Ch0_7_IrqHandler,
1317  FTM5_Ch0_7_IrqHandler,
1318  FTM5_Ch0_7_IrqHandler,
1319  FTM5_Ch0_7_IrqHandler,
1320  FTM5_Ch0_7_IrqHandler,
1321  FTM5_Ch0_7_IrqHandler,
1322  FTM5_Ch0_7_IrqHandler,
1323  FTM5_Ch0_7_IrqHandler},
1324 #else
1325  {FTM5_Ch0_Ch1_IrqHandler,
1326  FTM5_Ch0_Ch1_IrqHandler,
1327  FTM5_Ch2_Ch3_IrqHandler,
1328  FTM5_Ch2_Ch3_IrqHandler,
1329  FTM5_Ch4_Ch5_IrqHandler,
1330  FTM5_Ch4_Ch5_IrqHandler,
1331  FTM5_Ch6_Ch7_IrqHandler,
1332  FTM5_Ch6_Ch7_IrqHandler},
1333 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1334 #endif /* FTM_INSTANCE_COUNT > 5U */
1335 
1336 #if (FTM_INSTANCE_COUNT > 6U)
1337 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1338  {FTM6_Ch0_7_IrqHandler,
1339  FTM6_Ch0_7_IrqHandler,
1340  FTM6_Ch0_7_IrqHandler,
1341  FTM6_Ch0_7_IrqHandler,
1342  FTM6_Ch0_7_IrqHandler,
1343  FTM6_Ch0_7_IrqHandler,
1344  FTM6_Ch0_7_IrqHandler,
1345  FTM6_Ch0_7_IrqHandler},
1346 #else
1347  {FTM6_Ch0_Ch1_IrqHandler,
1348  FTM6_Ch0_Ch1_IrqHandler,
1349  FTM6_Ch2_Ch3_IrqHandler,
1350  FTM6_Ch2_Ch3_IrqHandler,
1351  FTM6_Ch4_Ch5_IrqHandler,
1352  FTM6_Ch4_Ch5_IrqHandler,
1353  FTM6_Ch6_Ch7_IrqHandler,
1354  FTM6_Ch6_Ch7_IrqHandler},
1355 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1356 #endif /* FTM_INSTANCE_COUNT > 6U */
1357 
1358 #if (FTM_INSTANCE_COUNT > 7U)
1359 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1360  {FTM7_Ch0_7_IrqHandler,
1361  FTM7_Ch0_7_IrqHandler,
1362  FTM7_Ch0_7_IrqHandler,
1363  FTM7_Ch0_7_IrqHandler,
1364  FTM7_Ch0_7_IrqHandler,
1365  FTM7_Ch0_7_IrqHandler,
1366  FTM7_Ch0_7_IrqHandler,
1367  FTM7_Ch0_7_IrqHandler},
1368 #else
1369  {FTM7_Ch0_Ch1_IrqHandler,
1370  FTM7_Ch0_Ch1_IrqHandler,
1371  FTM7_Ch2_Ch3_IrqHandler,
1372  FTM7_Ch2_Ch3_IrqHandler,
1373  FTM7_Ch4_Ch5_IrqHandler,
1374  FTM7_Ch4_Ch5_IrqHandler,
1375  FTM7_Ch6_Ch7_IrqHandler,
1376  FTM7_Ch6_Ch7_IrqHandler},
1377 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
1378 #endif /* FTM_INSTANCE_COUNT > 7U */
1379 };
1380 
1381 #endif /* TIMING_OVER_FTM */
1382 
1383 /* Define TIMING PAL over STM */
1384 #if (defined (TIMING_OVER_STM))
1385 
1386 #if (STM_INSTANCE_COUNT > 0U)
1387 void STM0_Ch0_IRQHandler(void)
1388 {
1389  TIMING_Stm_IrqHandler(0U, 0U);
1390 }
1391 
1392 void STM0_Ch1_IRQHandler(void)
1393 {
1394  TIMING_Stm_IrqHandler(0U, 1U);
1395 }
1396 
1397 void STM0_Ch2_IRQHandler(void)
1398 {
1399  TIMING_Stm_IrqHandler(0U, 2U);
1400 }
1401 
1402 void STM0_Ch3_IRQHandler(void)
1403 {
1404  TIMING_Stm_IrqHandler(0U, 3U);
1405 }
1406 #endif /* STM_INSTANCE_COUNT > 0U */
1407 
1408 #if (STM_INSTANCE_COUNT > 1U)
1409 void STM1_Ch0_IRQHandler(void)
1410 {
1411  TIMING_Stm_IrqHandler(1U, 0U);
1412 }
1413 
1414 void STM1_Ch1_IRQHandler(void)
1415 {
1416  TIMING_Stm_IrqHandler(1U, 1U);
1417 }
1418 
1419 void STM1_Ch2_IRQHandler(void)
1420 {
1421  TIMING_Stm_IrqHandler(1U, 2U);
1422 }
1423 
1424 void STM1_Ch3_IRQHandler(void)
1425 {
1426  TIMING_Stm_IrqHandler(1U, 3U);
1427 }
1428 #endif /* STM_INSTANCE_COUNT > 1U */
1429 
1430 #if (STM_INSTANCE_COUNT > 2U)
1431 void STM2_Ch0_IRQHandler(void)
1432 {
1433  TIMING_Stm_IrqHandler(2U, 0U);
1434 }
1435 
1436 void STM2_Ch1_IRQHandler(void)
1437 {
1438  TIMING_Stm_IrqHandler(2U, 1U);
1439 }
1440 
1441 void STM2_Ch2_IRQHandler(void)
1442 {
1443  TIMING_Stm_IrqHandler(2U, 2U);
1444 }
1445 
1446 void STM2_Ch3_IRQHandler(void)
1447 {
1448  TIMING_Stm_IrqHandler(2U, 3U);
1449 }
1450 #endif /* STM_INSTANCE_COUNT > 2U */
1451 
1452 #endif /* TIMING_OVER_STM */
1453 
1454 /*******************************************************************************
1455  * EOF
1456  ******************************************************************************/
#define FTM_CONTROLS_COUNT
Definition: S32K118.h:3822
#define LPIT_MSR_TIF1_MASK
Definition: S32K118.h:5893
#define LPIT_MSR_TIF3_MASK
Definition: S32K118.h:5901
static bool FTM_DRV_GetChnEventStatus(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel event status.
Definition: ftm_common.h:766
#define LPIT_MSR_TIF2_MASK
Definition: S32K118.h:5897
#define LPIT_MSR_TIF0_MASK
Definition: S32K118.h:5889
#define FTM_INSTANCE_COUNT
Definition: S32K118.h:3868
uint32_t LPIT_DRV_GetInterruptFlagTimerChannels(uint32_t instance, uint32_t mask)
Gets the current interrupt flag of timer channels.
Definition: lpit_driver.c:667
void(* isr_t)(void)
Interrupt handler type.