interrupt_manager.c
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1 /*
2  * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
58 #include "interrupt_manager.h"
59 
60 /*******************************************************************************
61  * Definitions
62  ******************************************************************************/
63 
67 static int32_t g_interruptDisableCount = 0;
68 
74 extern uint32_t __VECTOR_RAM[((uint32_t)(FEATURE_INTERRUPT_IRQ_MAX)) + 16U + 1U];
75 
76 /*******************************************************************************
77  * Code
78  ******************************************************************************/
79 
80 /*FUNCTION**********************************************************************
81  *
82  * Function Name : INT_SYS_InstallHandler
83  * Description : Install an interrupt handler routine for a given IRQ number
84  * This function will let application register/replace the interrupt
85  * handler for specified IRQ number. IRQ number is different than Vector
86  * number. IRQ 0 will start from Vector 16 address. Refer to reference
87  * manual for details. Also refer to startup_<CPU>.s file for each chip
88  * family to find out the default interrupt handler for each device. This
89  * function will convert the IRQ number to vector number by adding 16 to
90  * it.
91  *
92  * Note : This method is applicable only if interrupt vector is
93  * copied in RAM, __flash_vector_table__ symbol is used to
94  * control this from linker options.
95  * Implements INT_SYS_InstallHandler_Activity
96  *
97  *END**************************************************************************/
99  const isr_t newHandler,
100  isr_t* const oldHandler)
101 {
102 
103 #if (defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT))
104 
105  /* Check IRQ number */
106  int32_t dev_irqNumber = (int32_t)irqNumber;
108  DEV_ASSERT(dev_irqNumber <= (int32_t)FEATURE_INTERRUPT_IRQ_MAX);
109  DEV_ASSERT(__VECTOR_RAM != 0U);
110  /* Check whether there is vector table in RAM */
111  DEV_ASSERT((uint32_t)__VECTOR_RAM == S32_SCB->VTOR);
112 
113 #endif /*(defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT)) */
114 
115  /* Save the former handler pointer */
116  if (oldHandler != (isr_t *) 0)
117  {
118  *oldHandler = (isr_t)__VECTOR_RAM[((int32_t)irqNumber) + 16];
119  }
120 
121 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
122 
123  #if (defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT))
124 
125  DEV_ASSERT((uint32_t)irqNumber < MSCM_IRSPRC_COUNT);
126  /* Check routing is not read-only in case it needs to be written */
127  uint16_t cpu_enable = (uint16_t)(1UL << (MSCM->CPXNUM));
128  if ((MSCM->IRSPRC[irqNumber] & cpu_enable) == 0U)
129  {
130  DEV_ASSERT((MSCM->IRSPRC[irqNumber] & (uint16_t)(MSCM_IRSPRC_RO_MASK)) == (uint16_t)MSCM_IRSPRC_RO(0));
131  }
132 
133  #endif /*(defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT)) */
134 
135 #endif /* FEATURE_MSCM_HAS_INTERRUPT_ROUTER */
136 
137  /* Set handler into vector table */
138  __VECTOR_RAM[((int32_t)irqNumber) + 16] = (uint32_t)newHandler;
139 
140 }
141 
142 /*FUNCTION**********************************************************************
143  *
144  * Function Name : INT_SYS_EnableIRQ
145  * Description : Enables an interrupt for a given IRQ number.
146  * It calls the system NVIC API to access the interrupt control
147  * register and MSCM (if available) API for interrupt routing.
148  * The input IRQ number does not include the core interrupt, only
149  * the peripheral interrupt, from 0 to a maximum supported IRQ.
150  * Implements INT_SYS_EnableIRQ_Activity
151  *END**************************************************************************/
153 {
154 
155  /* Check IRQ number */
156  DEV_ASSERT(0 <= (int32_t)irqNumber);
157  DEV_ASSERT((uint32_t)irqNumber <= (uint32_t)FEATURE_INTERRUPT_IRQ_MAX);
158 
159  /* Enable interrupt */
160  S32_NVIC->ISER[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
161 
162 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
163 
164  /* Enable routing to current CPU */
165  uint16_t cpu_enable = (uint16_t)(1UL << (MSCM->CPXNUM));
166  MSCM->IRSPRC[irqNumber] |= cpu_enable;
167 
168 #endif /* FEATURE_MSCM_HAS_INTERRUPT_ROUTER */
169 }
170 
171 /*FUNCTION**********************************************************************
172  *
173  * Function Name : INT_SYS_DisableIRQ
174  * Description : Disable individual interrupt for a specified IRQ
175  * It calls the system NVIC API to access the interrupt control register
176  * and MSCM (if available) API for interrupt routing.
177  * Implements INT_SYS_DisableIRQ_Activity
178  *
179  *END**************************************************************************/
181 {
182 
183  /* Check IRQ number */
184  DEV_ASSERT(0 <= (int32_t)irqNumber);
185  DEV_ASSERT((uint32_t)irqNumber <= (uint32_t)FEATURE_INTERRUPT_IRQ_MAX);
186 
187  /* Disable interrupt */
188  S32_NVIC->ICER[((uint32_t)(irqNumber) >> 5U)] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
189 
190 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
191 
192  /* Disable routing to current CPU */
193  uint16_t cpu_enable = (uint16_t)(1UL << (MSCM->CPXNUM));
194  MSCM->IRSPRC[irqNumber] &= (uint16_t)~(cpu_enable);
195 
196 #endif /* FEATURE_MSCM_HAS_INTERRUPT_ROUTER */
197 
198 }
199 
200 /*FUNCTION**********************************************************************
201  *
202  * Function Name : INT_SYS_EnableIRQGlobal
203  * Description : Enable system interrupt
204  * This function will enable the global interrupt by calling the core API
205  * Implements INT_SYS_EnableIRQGlobal_Activity
206  *
207  *END**************************************************************************/
209 {
210  /* Check and update */
211  if (g_interruptDisableCount > 0)
212  {
214 
215  if (g_interruptDisableCount <= 0)
216  {
217  /* Enable the global interrupt*/
219  }
220  }
221 }
222 
223 /*FUNCTION**********************************************************************
224  *
225  * Function Name : INT_SYS_DisableIRQGlobal
226  * Description : Disable system interrupt
227  * This function will disable the global interrupt by calling the core API
228  * Implements INT_SYS_DisableIRQGlobal_Activity
229  *
230  *END**************************************************************************/
232 {
233  /* Disable the global interrupt */
235 
236  /* Update counter*/
238 }
239 
240 /*FUNCTION**********************************************************************
241  *
242  * Function Name : INT_SYS_SetPriority
243  * Description : Set the priority of an interrupt
244  * This function will set the priority of an interrupt.
245  * Note: The priority cannot be set for every core interrupt.
246  * Implements INT_SYS_SetPriority_Activity
247  *
248  *END**************************************************************************/
249 void INT_SYS_SetPriority(IRQn_Type irqNumber, uint8_t priority)
250 {
251 
252 #if (defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT))
253 
254  /* Check IRQ number and priority. */
255  int32_t dev_irqNumber = (int32_t)irqNumber;
256  DEV_ASSERT(dev_irqNumber <= (int32_t)FEATURE_INTERRUPT_IRQ_MAX);
257  DEV_ASSERT(priority < (uint8_t)(1U << FEATURE_NVIC_PRIO_BITS));
258 
259 #endif /*(defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT)) */
260 
261  uint8_t shift = (uint8_t) (8U - FEATURE_NVIC_PRIO_BITS);
262 
263  if ((int32_t)irqNumber < 0)
264  {
265  uint32_t intVectorId = ((uint32_t)(irqNumber) & 0xFU);
266  uint32_t regId = intVectorId / 4U;
267 
268  /* Compute pointer to SHPR register - avoid MISRA violation. */
269  #if defined (S32K11x_SERIES)
270  DEV_ASSERT((int32_t)regId != 1);
271 
272  volatile uint32_t * shpr_reg_ptr = ((regId == 2U) ? (volatile uint32_t *)&S32_SCB->SHPR2 : (volatile uint32_t *)&S32_SCB->SHPR3);
273  uint8_t priByteShift = ((uint8_t)(intVectorId) & 0x3U) << 3U;
274 
275  /* Clear the old value from the register */
276  *shpr_reg_ptr &= ~(0xFFUL << priByteShift);
277 
278  /* Set Priority for Cortex-M0P System Interrupts */
279  *shpr_reg_ptr |= ((uint32_t)(((((uint32_t)priority) << shift)) & 0xFFUL)) << priByteShift;
280  #else
281  volatile uint8_t * shpr_reg_ptr = ((regId == 1U) ? (volatile uint8_t *)&S32_SCB->SHPR1 : ((regId == 2U) ? (volatile uint8_t *)&S32_SCB->SHPR2 : (volatile uint8_t *)&S32_SCB->SHPR3));
282 
283  /* Set Priority for Cortex-M4 System Interrupts */
284  shpr_reg_ptr[intVectorId % 4U] = (uint8_t)(((((uint32_t)priority) << shift)) & 0xffUL);
285  #endif /* defined (S32K11x_SERIES) */
286  }
287  else
288  {
289  /* Set Priority for device specific Interrupts */
290  #if defined (S32K11x_SERIES)
291  uint32_t iprVectorId = (uint32_t)(irqNumber) >> 2U;
292  uint8_t priByteShift = (((uint8_t)(irqNumber)) & 0x3U) << 3U;
293 
294  /* Clear the old value from the register */
295  S32_NVIC->IPR[iprVectorId] &= ~(0xFFUL << priByteShift);
296 
297  S32_NVIC->IPR[iprVectorId] |= ((uint32_t)(((((uint32_t)priority) << shift)) & 0xFFUL)) << priByteShift;
298  #else
299  S32_NVIC->IP[(uint32_t)(irqNumber)] = (uint8_t)(((((uint32_t)priority) << shift)) & 0xFFUL);
300  #endif /* defined (S32K11x_SERIES) */
301  }
302 }
303 
304 /*FUNCTION**********************************************************************
305  *
306  * Function Name : INT_SYS_GetPriority
307  * Description : Get the priority of an interrupt
308  * This function will get the priority of an interrupt.
309  * Note: The priority cannot be obtained for every core interrupt.
310  * Implements INT_SYS_GetPriority_Activity
311  *
312  *END**************************************************************************/
313 uint8_t INT_SYS_GetPriority(IRQn_Type irqNumber)
314 {
315 
316 #if (defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT))
317 
318  /* Check IRQ number. */
319  int32_t dev_irqNumber = (int32_t)irqNumber;
320  DEV_ASSERT(dev_irqNumber <= (int32_t)FEATURE_INTERRUPT_IRQ_MAX);
321 
322 #endif /*(defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT)) */
323 
324  uint8_t priority = 0U;
325  uint8_t shift = (uint8_t) (8U - FEATURE_NVIC_PRIO_BITS);
326 
327  if ((int32_t)irqNumber < 0)
328  {
329  uint32_t intVectorId = ((uint32_t)(irqNumber) & 0xFU);
330  uint32_t regId = intVectorId / 4U;
331 
332  /* Compute pointer to SHPR register - avoid MISRA violation. */
333  #if defined (S32K11x_SERIES)
334  DEV_ASSERT((int32_t)regId != 1);
335 
336  volatile const uint32_t * shpr_reg_ptr = ((regId == 2U) ? (volatile uint32_t *)&S32_SCB->SHPR2 : (volatile uint32_t *)&S32_SCB->SHPR3);
337  uint8_t priByteShift = ((uint8_t)(intVectorId) & 0x3U) << 3U;
338 
339  priority = ((uint8_t)(*shpr_reg_ptr >> priByteShift)) >> shift;
340  #else
341  volatile const uint8_t * shpr_reg_ptr = ((regId == 1U) ? (volatile uint8_t *)&S32_SCB->SHPR1 : ((regId == 2U) ? (volatile uint8_t *)&S32_SCB->SHPR2 : (volatile uint8_t *)&S32_SCB->SHPR3));
342 
343  /* Get Priority from Cortex-M System Interrupts */
344  priority = (uint8_t)(shpr_reg_ptr[intVectorId % 4U] >> (shift));
345  #endif /* defined (S32K11x_SERIES) */
346  }
347  else
348  {
349  /* Get Priority for device specific Interrupts */
350  #if defined (S32K11x_SERIES)
351  uint32_t iprVectorId = (uint32_t)(irqNumber) >> 2U;
352  uint8_t priByteShift = (((uint8_t)(irqNumber)) & 0x3U) << 3U;
353  priority = ((uint8_t)(S32_NVIC->IPR[iprVectorId] >> priByteShift)) >> shift;
354  #else
355  priority = (uint8_t)(S32_NVIC->IP[(uint32_t)(irqNumber)] >> shift);
356  #endif /* defined (S32K11x_SERIES) */
357  }
358 
359  return priority;
360 }
361 
362 #if FEATURE_INTERRUPT_HAS_PENDING_STATE
363 /*FUNCTION**********************************************************************
364  *
365  * Function Name : INT_SYS_ClearPending
366  * Description : Clear Pending Interrupt
367  * This function clears the pending bit of a peripheral interrupt
368  * or a directed interrupt to this CPU (if available).
369  * Implements INT_SYS_ClearPending_Activity
370  *
371  *END**************************************************************************/
372 void INT_SYS_ClearPending(IRQn_Type irqNumber)
373 {
374 
375  /* Check IRQ number */
376  DEV_ASSERT(0 <= (int32_t)irqNumber);
377  DEV_ASSERT((uint32_t)irqNumber <= (uint32_t)FEATURE_INTERRUPT_IRQ_MAX);
378 
379 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
380 
381  if ((FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber) && (irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX))
382  {
383  /* Clear Directed CPU Pending Interrupt */
384  switch (MSCM->CPXNUM)
385  {
386  case 0:
387  MSCM->IRCP0IR |= (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN));
388  break;
389  default:
390  MSCM->IRCP1IR |= (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN));
391  break;
392  }
393  return;
394  }
395 
396 #endif /* FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER */
397 
398  /* Clear Pending Interrupt */
399  S32_NVIC->ICPR[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
400 }
401 
402 /*FUNCTION**********************************************************************
403  *
404  * Function Name : INT_SYS_SetPending
405  * Description : Set Pending Interrupt
406  * This function configures the pending bit of a peripheral interrupt.
407  * Implements INT_SYS_SetPending_Activity
408  *
409  *END**************************************************************************/
410 void INT_SYS_SetPending(IRQn_Type irqNumber)
411 {
412 
413  /* Check IRQ number */
414  DEV_ASSERT(0 <= (int32_t)irqNumber);
415  DEV_ASSERT((uint32_t)irqNumber <= (uint32_t)FEATURE_INTERRUPT_IRQ_MAX);
416 
417  /* Set Pending Interrupt */
418  S32_NVIC->ISPR[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
419 }
420 
421 /*FUNCTION**********************************************************************
422  *
423  * Function Name : INT_SYS_GetPending
424  * Description : Get Pending Interrupt
425  * This function gets the pending bit of a peripheral interrupt or a directed
426  * interrupt to this CPU (if available).
427  * Implements INT_SYS_GetPending_Activity
428  *
429  *END**************************************************************************/
430 uint32_t INT_SYS_GetPending(IRQn_Type irqNumber)
431 {
432 
433  /* Check IRQ number */
434  DEV_ASSERT(0 <= (int32_t)irqNumber);
435  DEV_ASSERT((uint32_t)irqNumber <= (uint32_t)FEATURE_INTERRUPT_IRQ_MAX);
436 
437 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
438 
439  /* Get Directed CPU Pending Interrupt */
440  if ((FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber) && (irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX))
441  {
442  return (((((MSCM->CPXNUM != 0UL) ? MSCM->IRCP1IR : MSCM->IRCP0IR) &
443  (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN))) != 0UL) ? 1UL : 0UL);
444  }
445 
446 #endif /* FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER */
447 
448  /* Get Pending Interrupt */
449  return ((uint32_t)(((S32_NVIC->ISPR[(((uint32_t)irqNumber) >> 5UL)] & (1UL << (((uint32_t)irqNumber) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
450 }
451 #endif /* FEATURE_INTERRUPT_HAS_PENDING_STATE */
452 
453 #if FEATURE_INTERRUPT_HAS_ACTIVE_STATE
454 /*FUNCTION**********************************************************************
455  *
456  * Function Name : INT_SYS_GetActive
457  * Description : Get active state of a peripheral interrupt
458  * This function gets the active state of a peripheral interrupt.
459  * Implements INT_SYS_GetActive_Activity
460  *
461  *END**************************************************************************/
462 uint32_t INT_SYS_GetActive(IRQn_Type irqNumber)
463 {
464 
465  /* Check IRQ number */
466  DEV_ASSERT(0 <= (int32_t)irqNumber);
467  DEV_ASSERT((uint32_t)irqNumber <= (uint32_t)FEATURE_INTERRUPT_IRQ_MAX);
468 
469  /* Get Active Interrupt */
470  return ((uint32_t)(((S32_NVIC->IABR[(((uint32_t)irqNumber) >> 5UL)] & (1UL << (((uint32_t)irqNumber) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
471 }
472 #endif /* FEATURE_INTERRUPT_HAS_ACTIVE_STATE */
473 
474 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
475 
485 /*FUNCTION**********************************************************************
486  *
487  * Function Name : INT_SYS_GenerateDirectedCpuInterrupt
488  * Description : Get active state of a peripheral interrupt
489  * This function gets the active state of a peripheral interrupt.
490  * Implements INT_SYS_GenerateDirectedCpuInterrupt_Activity
491  *
492  *END**************************************************************************/
493 void INT_SYS_GenerateDirectedCpuInterrupt(IRQn_Type irqNumber, interrupt_manager_cpu_targets_t cpu_target)
494 {
495 
496  /* Check IRQ number */
497  DEV_ASSERT(FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber);
498  DEV_ASSERT(irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX);
499 
500  uint32_t reg_val = MSCM_IRCPGIR_INTID((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN);
501 
502  switch (cpu_target)
503  {
504  case INTERRUPT_MANAGER_TARGET_SELF:
505  reg_val |= MSCM_IRCPGIR_TLF(2);
506  break;
507  case INTERRUPT_MANAGER_TARGET_OTHERS:
508  reg_val |= MSCM_IRCPGIR_TLF(1);
509  break;
510  case INTERRUPT_MANAGER_TARGET_NONE:
511  case INTERRUPT_MANAGER_TARGET_CP0:
512  case INTERRUPT_MANAGER_TARGET_CP1:
513  case INTERRUPT_MANAGER_TARGET_CP0_CP1:
514  reg_val |= (MSCM_IRCPGIR_TLF(0) | MSCM_IRCPGIR_CPUTL(cpu_target));
515  break;
516  default:
517  /* Not treated case ? */
518  break;
519  }
520 
521  /* Generate Directed CPU Interrupt */
522  MSCM->IRCPGIR = reg_val;
523 }
524 
525 #endif /* FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER */
526 
527 /*******************************************************************************
528  * EOF
529  ******************************************************************************/
uint32_t __VECTOR_RAM[((uint32_t)(FEATURE_INTERRUPT_IRQ_MAX))+16U+1U]
Declaration of vector table. FEATURE_INTERRUPT_IRQ_MAX is the highest interrupt request number...
#define S32_NVIC
Definition: S32K118.h:8946
void INT_SYS_SetPending(IRQn_Type irqNumber)
Set Pending Interrupt.
#define DISABLE_INTERRUPTS()
Disable interrupts.
Definition: s32_core_cm0.h:82
uint32_t INT_SYS_GetPending(IRQn_Type irqNumber)
Get Pending Interrupt.
#define FEATURE_NVIC_PRIO_BITS
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
void INT_SYS_DisableIRQGlobal(void)
Disable system interrupt.
#define DEV_ASSERT(x)
Definition: devassert.h:77
static int32_t g_interruptDisableCount
Counter to manage the nested callings of global disable/enable interrupt.
#define S32_SCB
Definition: S32K118.h:9048
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K118.h:188
void INT_SYS_SetPriority(IRQn_Type irqNumber, uint8_t priority)
Set Interrupt Priority.
#define FEATURE_INTERRUPT_IRQ_MAX
void INT_SYS_ClearPending(IRQn_Type irqNumber)
Clear Pending Interrupt.
void INT_SYS_EnableIRQGlobal(void)
Enables system interrupt.
#define MSCM
Definition: S32K118.h:7603
#define ENABLE_INTERRUPTS()
Enable interrupts.
Definition: s32_core_cm0.h:71
uint8_t INT_SYS_GetPriority(IRQn_Type irqNumber)
Get Interrupt Priority.
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
#define FEATURE_INTERRUPT_IRQ_MIN
void(* isr_t)(void)
Interrupt handler type.
void INT_SYS_InstallHandler(IRQn_Type irqNumber, const isr_t newHandler, isr_t *const oldHandler)
Installs an interrupt handler routine for a given IRQ number.