Macros | |
#define | ERM_CR0_ENCIE0_MASK 0x40000000u |
#define | ERM_CR0_ENCIE0_SHIFT 30u |
#define | ERM_CR0_ENCIE0_WIDTH 1u |
#define | ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE0_SHIFT))&ERM_CR0_ENCIE0_MASK) |
#define | ERM_CR0_ESCIE0_MASK 0x80000000u |
#define | ERM_CR0_ESCIE0_SHIFT 31u |
#define | ERM_CR0_ESCIE0_WIDTH 1u |
#define | ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE0_SHIFT))&ERM_CR0_ESCIE0_MASK) |
#define | ERM_SR0_NCE0_MASK 0x40000000u |
#define | ERM_SR0_NCE0_SHIFT 30u |
#define | ERM_SR0_NCE0_WIDTH 1u |
#define | ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE0_SHIFT))&ERM_SR0_NCE0_MASK) |
#define | ERM_SR0_SBC0_MASK 0x80000000u |
#define | ERM_SR0_SBC0_SHIFT 31u |
#define | ERM_SR0_SBC0_WIDTH 1u |
#define | ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC0_SHIFT))&ERM_SR0_SBC0_MASK) |
#define | ERM_EARn_EAR_MASK 0xFFFFFFFFu |
#define | ERM_EARn_EAR_SHIFT 0u |
#define | ERM_EARn_EAR_WIDTH 32u |
#define | ERM_EARn_EAR(x) (((uint32_t)(((uint32_t)(x))<<ERM_EARn_EAR_SHIFT))&ERM_EARn_EAR_MASK) |
#define ERM_CR0_ENCIE0 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE0_SHIFT))&ERM_CR0_ENCIE0_MASK) |
#define ERM_CR0_ESCIE0 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE0_SHIFT))&ERM_CR0_ESCIE0_MASK) |
#define ERM_EARn_EAR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ERM_EARn_EAR_SHIFT))&ERM_EARn_EAR_MASK) |
#define ERM_SR0_NCE0 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE0_SHIFT))&ERM_SR0_NCE0_MASK) |
#define ERM_SR0_SBC0 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC0_SHIFT))&ERM_SR0_SBC0_MASK) |