UJA1169.h File Reference

Go to the source code of this file.

Macros

#define SBC_UJA_REG_ADDR_MASK   (0xFEU)
 Register address macros. More...
 
#define SBC_UJA_REG_ADDR_SHIFT   (1U)
 
#define SBC_UJA_REG_ADDR_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REG_ADDR_SHIFT)&SBC_UJA_REG_ADDR_MASK)
 
#define SBC_UJA_WTDOG_CTR_WMC_MASK   (0xE0U)
 Watchdog mode control, watchdog mode control macros. More...
 
#define SBC_UJA_WTDOG_CTR_WMC_SHIFT   (5U)
 
#define SBC_UJA_WTDOG_CTR_WMC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_WMC_SHIFT)&SBC_UJA_WTDOG_CTR_WMC_MASK)
 
#define SBC_UJA_WTDOG_CTR_NWP_MASK   (0x0FU)
 Watchdog mode control, nominal watchdog period macros. More...
 
#define SBC_UJA_WTDOG_CTR_NWP_SHIFT   (0U)
 
#define SBC_UJA_WTDOG_CTR_NWP_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_NWP_SHIFT)&SBC_UJA_WTDOG_CTR_NWP_MASK)
 
#define SBC_UJA_WTDOG_CTR_MASK   (SBC_UJA_WTDOG_CTR_WMC_MASK | SBC_UJA_WTDOG_CTR_NWP_MASK)
 Watchdog control macros. More...
 
#define SBC_UJA_WTDOG_CTR_SHIFT   (0U)
 
#define SBC_UJA_WTDOG_CTR_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_SHIFT)&SBC_UJA_WTDOG_CTR_MASK)
 
#define SBC_UJA_MODE_MC_MASK   (0x07U)
 Mode control, mode control macros. More...
 
#define SBC_UJA_MODE_MC_SHIFT   (0U)
 
#define SBC_UJA_MODE_MC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MODE_MC_SHIFT)&SBC_UJA_MODE_MC_MASK)
 
#define SBC_UJA_MODE_MASK   (SBC_UJA_MODE_MC_MASK)
 Mode control macros. More...
 
#define SBC_UJA_MODE_SHIFT   (SBC_UJA_MODE_MC_SHIFT)
 
#define SBC_UJA_MODE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MODE_SHIFT)&SBC_UJA_MODE_MASK)
 
#define SBC_UJA_FAIL_SAFE_LHC_MASK   (0x04U)
 Fail-safe control register, LIMP home control macros. More...
 
#define SBC_UJA_FAIL_SAFE_LHC_SHIFT   (2U)
 
#define SBC_UJA_FAIL_SAFE_LHC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_LHC_SHIFT)&SBC_UJA_FAIL_SAFE_LHC_MASK)
 
#define SBC_UJA_FAIL_SAFE_RCC_MASK   (0x03U)
 Fail-safe control register, reset counter control macros. More...
 
#define SBC_UJA_FAIL_SAFE_RCC_SHIFT   (0U)
 
#define SBC_UJA_FAIL_SAFE_RCC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_RCC_SHIFT)&SBC_UJA_FAIL_SAFE_RCC_MASK)
 
#define SBC_UJA_FAIL_SAFE_MASK   (SBC_UJA_FAIL_SAFE_LHC_MASK | SBC_UJA_FAIL_SAFE_RCC_MASK)
 Fail-safe control register macros. More...
 
#define SBC_UJA_FAIL_SAFE_SHIFT   (0U)
 
#define SBC_UJA_FAIL_SAFE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_SHIFT)&SBC_UJA_FAIL_SAFE_MASK)
 
#define SBC_UJA_MAIN_OTWS_MASK   (0x40U)
 Main status register, Overtemperature warning status macros. More...
 
#define SBC_UJA_MAIN_OTWS_SHIFT   (6U)
 
#define SBC_UJA_MAIN_OTWS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_OTWS_SHIFT)&SBC_UJA_MAIN_OTWS_MASK)
 
#define SBC_UJA_MAIN_NMS_MASK   (0x20U)
 Main status register, Normal mode status macros. More...
 
#define SBC_UJA_MAIN_NMS_SHIFT   (5U)
 
#define SBC_UJA_MAIN_NMS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_NMS_SHIFT)&SBC_UJA_MAIN_NMS_MASK)
 
#define SBC_UJA_MAIN_RSS_MASK   (0x1FU)
 Main status register, Reset source status macros. More...
 
#define SBC_UJA_MAIN_RSS_SHIFT   (0U)
 
#define SBC_UJA_MAIN_RSS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_RSS_SHIFT)&SBC_UJA_MAIN_RSS_MASK)
 
#define SBC_UJA_MAIN_MASK   (SBC_UJA_MAIN_OTWS_MASK | SBC_UJA_MAIN_NMS_MASK | SBC_UJA_MAIN_RSS_MASK)
 Main status macros. More...
 
#define SBC_UJA_MAIN_SHIFT   (0U)
 
#define SBC_UJA_MAIN_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_SHIFT)&SBC_UJA_MAIN_MASK)
 
#define SBC_UJA_SYS_EVNT_OTWE_MASK   (0x04U)
 System event capture enable, overtemperature warning enable macros. More...
 
#define SBC_UJA_SYS_EVNT_OTWE_SHIFT   (2U)
 
#define SBC_UJA_SYS_EVNT_OTWE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_OTWE_SHIFT)&SBC_UJA_SYS_EVNT_OTWE_MASK)
 
#define SBC_UJA_SYS_EVNT_SPIFE_MASK   (0x02U)
 System event capture enable, SPI failure enable. More...
 
#define SBC_UJA_SYS_EVNT_SPIFE_SHIFT   (1U)
 
#define SBC_UJA_SYS_EVNT_SPIFE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_SPIFE_SHIFT)&SBC_UJA_SYS_EVNT_SPIFE_MASK)
 
#define SBC_UJA_SYS_EVNT_MASK   (SBC_UJA_SYS_EVNT_OTWE_MASK | SBC_UJA_SYS_EVNT_SPIFE_MASK)
 System event capture enable. More...
 
#define SBC_UJA_SYS_EVNT_SHIFT   (1U)
 
#define SBC_UJA_SYS_EVNT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_SHIFT)&SBC_UJA_SYS_EVNT_MASK)
 
#define SBC_UJA_WTDOG_STAT_FNMS_MASK   (0x08U)
 Watchdog status register, forced Normal mode status macros. More...
 
#define SBC_UJA_WTDOG_STAT_FNMS_SHIFT   (3U)
 
#define SBC_UJA_WTDOG_STAT_FNMS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_FNMS_SHIFT)&SBC_UJA_WTDOG_STAT_FNMS_MASK)
 
#define SBC_UJA_WTDOG_STAT_SDMS_MASK   (0x04U)
 Watchdog status register, Software Development mode status macros. More...
 
#define SBC_UJA_WTDOG_STAT_SDMS_SHIFT   (2U)
 
#define SBC_UJA_WTDOG_STAT_SDMS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_SDMS_SHIFT)&SBC_UJA_WTDOG_STAT_SDMS_MASK)
 
#define SBC_UJA_WTDOG_STAT_WDS_MASK   (0x03U)
 Watchdog status register, watchdog status macros. More...
 
#define SBC_UJA_WTDOG_STAT_WDS_SHIFT   (0U)
 
#define SBC_UJA_WTDOG_STAT_WDS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_WDS_SHIFT)&SBC_UJA_WTDOG_STAT_WDS_MASK)
 
#define SBC_UJA_WTDOG_STAT_MASK
 Watchdog status macros. More...
 
#define SBC_UJA_WTDOG_STAT_SHIFT   (0U)
 
#define SBC_UJA_WTDOG_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_SHIFT)&SBC_UJA_WTDOG_STAT_MASK)
 
#define SBC_UJA_MEMORY_X_MASK   (0xFFU)
 Memory X macros. More...
 
#define SBC_UJA_MEMORY_X_SHIFT   (0U)
 
#define SBC_UJA_MEMORY_X_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MEMORY_X_SHIFT)&SBC_UJA_MEMORY_X_MASK)
 
#define SBC_UJA_LOCK_LK6C_MASK   (0x40U)
 Lock control 6: address area 0x68 to 0x6F macros. More...
 
#define SBC_UJA_LOCK_LK6C_SHIFT   (6U)
 
#define SBC_UJA_LOCK_LK6C_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK6C_SHIFT)&SBC_UJA_LOCK_LK6C_MASK)
 
#define SBC_UJA_LOCK_LK5C_MASK   (0x20U)
 Lock control control 5: address area 0x50 to 0x5F - unused register range macros. More...
 
#define SBC_UJA_LOCK_LK5C_SHIFT   (5U)
 
#define SBC_UJA_LOCK_LK5C_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK5C_SHIFT)&SBC_UJA_LOCK_LK5C_MASK)
 
#define SBC_UJA_LOCK_LK4C_MASK   (0x10U)
 Lock control 4: address area 0x40 to 0x4F - WAKE pin control macros. More...
 
#define SBC_UJA_LOCK_LK4C_SHIFT   (4U)
 
#define SBC_UJA_LOCK_LK4C_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK4C_SHIFT)&SBC_UJA_LOCK_LK4C_MASK)
 
#define SBC_UJA_LOCK_LK3C_MASK   (0x08U)
 Lock control 3: address area 0x30 to 0x3F - unused register range macros. More...
 
#define SBC_UJA_LOCK_LK3C_SHIFT   (3U)
 
#define SBC_UJA_LOCK_LK3C_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK3C_SHIFT)&SBC_UJA_LOCK_LK3C_MASK)
 
#define SBC_UJA_LOCK_LK2C_MASK   (0x04U)
 Lock control 2: address area 0x20 to 0x2F - transceiver control macros. More...
 
#define SBC_UJA_LOCK_LK2C_SHIFT   (2U)
 
#define SBC_UJA_LOCK_LK2C_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK2C_SHIFT)&SBC_UJA_LOCK_LK2C_MASK)
 
#define SBC_UJA_LOCK_LK1C_MASK   (0x02U)
 Lock control 1: address area 0x10 to 0x1F - regulator control macros. More...
 
#define SBC_UJA_LOCK_LK1C_SHIFT   (1U)
 
#define SBC_UJA_LOCK_LK1C_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK1C_SHIFT)&SBC_UJA_LOCK_LK1C_MASK)
 
#define SBC_UJA_LOCK_LK0C_MASK   (0x01U)
 Lock control 0: address area 0x06 to 0x09 - general-purpose memory macros. More...
 
#define SBC_UJA_LOCK_LK0C_SHIFT   (0U)
 
#define SBC_UJA_LOCK_LK0C_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK0C_SHIFT)&SBC_UJA_LOCK_LK0C_MASK)
 
#define SBC_UJA_LOCK_LKNC_MASK
 Lock control N macros. More...
 
#define SBC_UJA_LOCK_LKNC_SHIFT   (0U)
 
#define SBC_UJA_LOCK_LKNC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LKNC_SHIFT)&SBC_UJA_LOCK_LKNC_MASK)
 
#define SBC_UJA_REGULATOR_PDC_MASK   (0x40U)
 Regulator control register, power distribution control macros. More...
 
#define SBC_UJA_REGULATOR_PDC_SHIFT   (6U)
 
#define SBC_UJA_REGULATOR_PDC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_PDC_SHIFT)&SBC_UJA_REGULATOR_PDC_MASK)
 
#define SBC_UJA_REGULATOR_V2C_MASK   (0x0CU)
 Regulator control register, V2/VEXT configuration macros. More...
 
#define SBC_UJA_REGULATOR_V2C_SHIFT   (2U)
 
#define SBC_UJA_REGULATOR_V2C_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_V2C_SHIFT)&SBC_UJA_REGULATOR_V2C_MASK)
 
#define SBC_UJA_REGULATOR_V1RTC_MASK   (0x03U)
 Regulator control register, set V1 reset threshold macros. More...
 
#define SBC_UJA_REGULATOR_V1RTC_SHIFT   (0U)
 
#define SBC_UJA_REGULATOR_V1RTC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_V1RTC_SHIFT)&SBC_UJA_REGULATOR_V1RTC_MASK)
 
#define SBC_UJA_REGULATOR_MASK   (SBC_UJA_REGULATOR_PDC_MASK | SBC_UJA_REGULATOR_V2C_MASK | SBC_UJA_REGULATOR_V1RTC_MASK)
 Regulator control register macros. More...
 
#define SBC_UJA_REGULATOR_SHIFT   (0U)
 
#define SBC_UJA_REGULATOR_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_SHIFT)&SBC_UJA_REGULATOR_MASK)
 
#define SBC_UJA_SUPPLY_STAT_V2S_MASK   (0x06U)
 Supply voltage status register, V2/VEXT status macros. More...
 
#define SBC_UJA_SUPPLY_STAT_V2S_SHIFT   (1U)
 
#define SBC_UJA_SUPPLY_STAT_V2S_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_V2S_SHIFT)&SBC_UJA_SUPPLY_STAT_V2S_MASK)
 
#define SBC_UJA_SUPPLY_STAT_V1S_MASK   (0x01U)
 Supply voltage status register, V1 status macros. More...
 
#define SBC_UJA_SUPPLY_STAT_V1S_SHIFT   (0U)
 
#define SBC_UJA_SUPPLY_STAT_V1S_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_V1S_SHIFT)&SBC_UJA_SUPPLY_STAT_V1S_MASK)
 
#define SBC_UJA_SUPPLY_STAT_MASK   (SBC_UJA_SUPPLY_STAT_V2S_MASK | SBC_UJA_SUPPLY_STAT_V1S_MASK)
 Supply voltage status register macros. More...
 
#define SBC_UJA_SUPPLY_STAT_SHIFT   (0U)
 
#define SBC_UJA_SUPPLY_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_SHIFT)&SBC_UJA_SUPPLY_STAT_MASK)
 
#define SBC_UJA_SUPPLY_EVNT_V2OE_MASK   (0x04U)
 Supply event capture enable register, V2/VEXT overvoltage enable macros. More...
 
#define SBC_UJA_SUPPLY_EVNT_V2OE_SHIFT   (2U)
 
#define SBC_UJA_SUPPLY_EVNT_V2OE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V2OE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V2OE_MASK)
 
#define SBC_UJA_SUPPLY_EVNT_V2UE_MASK   (0x02U)
 Supply event capture enable register, V2/VEXT undervoltage enable macros. More...
 
#define SBC_UJA_SUPPLY_EVNT_V2UE_SHIFT   (1U)
 
#define SBC_UJA_SUPPLY_EVNT_V2UE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V2UE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V2UE_MASK)
 
#define SBC_UJA_SUPPLY_EVNT_V1UE_MASK   (0x01U)
 Supply event capture enable register, V1 undervoltage enable macros. More...
 
#define SBC_UJA_SUPPLY_EVNT_V1UE_SHIFT   (0U)
 
#define SBC_UJA_SUPPLY_EVNT_V1UE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V1UE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V1UE_MASK)
 
#define SBC_UJA_SUPPLY_EVNT_MASK
 Supply event capture enable register macros. More...
 
#define SBC_UJA_SUPPLY_EVNT_SHIFT   (0U)
 
#define SBC_UJA_SUPPLY_EVNT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_SHIFT)&SBC_UJA_SUPPLY_EVNT_MASK)
 
#define SBC_UJA_CAN_CFDC_MASK   (0x40U)
 CAN control register, CAN FD control macros. More...
 
#define SBC_UJA_CAN_CFDC_SHIFT   (6U)
 
#define SBC_UJA_CAN_CFDC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CFDC_SHIFT)&SBC_UJA_CAN_CFDC_MASK)
 
#define SBC_UJA_CAN_PNCOK_MASK   (0x20U)
 CAN control register, CAN partial networking configuration OK macros. More...
 
#define SBC_UJA_CAN_PNCOK_SHIFT   (5U)
 
#define SBC_UJA_CAN_PNCOK_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_PNCOK_SHIFT)&SBC_UJA_CAN_PNCOK_MASK)
 
#define SBC_UJA_CAN_CPNC_MASK   (0x10U)
 CAN control register, CAN partial networking control macros. More...
 
#define SBC_UJA_CAN_CPNC_SHIFT   (4U)
 
#define SBC_UJA_CAN_CPNC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CPNC_SHIFT)&SBC_UJA_CAN_CPNC_MASK)
 
#define SBC_UJA_CAN_CMC_MASK   (0x03U)
 CAN control register, CAN mode control macros. More...
 
#define SBC_UJA_CAN_CMC_SHIFT   (0U)
 
#define SBC_UJA_CAN_CMC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CMC_SHIFT)&SBC_UJA_CAN_CMC_MASK)
 
#define SBC_UJA_CAN_MASK
 CAN control register macros. More...
 
#define SBC_UJA_CAN_SHIFT   (0U)
 
#define SBC_UJA_CAN_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_SHIFT)&SBC_UJA_CAN_MASK)
 
#define SBC_UJA_TRANS_STAT_CTS_MASK   (0x80U)
 Transceiver status register, CAN transceiver status macros. More...
 
#define SBC_UJA_TRANS_STAT_CTS_SHIFT   (7U)
 
#define SBC_UJA_TRANS_STAT_CTS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CTS_SHIFT)&SBC_UJA_TRANS_STAT_CTS_MASK)
 
#define SBC_UJA_TRANS_STAT_CPNERR_MASK   (0x40U)
 Transceiver status register, CAN partial networking error macros. More...
 
#define SBC_UJA_TRANS_STAT_CPNERR_SHIFT   (6U)
 
#define SBC_UJA_TRANS_STAT_CPNERR_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CPNERR_SHIFT)&SBC_UJA_TRANS_STAT_CPNERR_MASK)
 
#define SBC_UJA_TRANS_STAT_CPNS_MASK   (0x20U)
 Transceiver status register, CAN partial networking status macros. More...
 
#define SBC_UJA_TRANS_STAT_CPNS_SHIFT   (5U)
 
#define SBC_UJA_TRANS_STAT_CPNS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CPNS_SHIFT)&SBC_UJA_TRANS_STAT_CPNS_MASK)
 
#define SBC_UJA_TRANS_STAT_COSCS_MASK   (0x10U)
 Transceiver status register, CAN oscillator status macros. More...
 
#define SBC_UJA_TRANS_STAT_COSCS_SHIFT   (4U)
 
#define SBC_UJA_TRANS_STAT_COSCS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_COSCS_SHIFT)&SBC_UJA_TRANS_STAT_COSCS_MASK)
 
#define SBC_UJA_TRANS_STAT_CBSS_MASK   (0x08U)
 Transceiver status register, CAN-bus silence status macros. More...
 
#define SBC_UJA_TRANS_STAT_CBSS_SHIFT   (3U)
 
#define SBC_UJA_TRANS_STAT_CBSS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CBSS_SHIFT)&SBC_UJA_TRANS_STAT_CBSS_MASK)
 
#define SBC_UJA_TRANS_STAT_VCS_MASK   (0x02U)
 Transceiver status register, VCAN status macros. More...
 
#define SBC_UJA_TRANS_STAT_VCS_SHIFT   (1U)
 
#define SBC_UJA_TRANS_STAT_VCS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_VCS_SHIFT)&SBC_UJA_TRANS_STAT_VCS_MASK)
 
#define SBC_UJA_TRANS_STAT_CFS_MASK   (0x01U)
 Transceiver status register, CAN failure status macros. More...
 
#define SBC_UJA_TRANS_STAT_CFS_SHIFT   (0U)
 
#define SBC_UJA_TRANS_STAT_CFS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CFS_SHIFT)&SBC_UJA_TRANS_STAT_CFS_MASK)
 
#define SBC_UJA_TRANS_STAT_MASK
 Transceiver status register macros. More...
 
#define SBC_UJA_TRANS_STAT_SHIFT   (0U)
 
#define SBC_UJA_TRANS_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_SHIFT)&SBC_UJA_TRANS_STAT_MASK)
 
#define SBC_UJA_TRANS_EVNT_CBSE_MASK   (0x10U)
 Transceiver event capture enable register, CAN-bus silence enable macros. More...
 
#define SBC_UJA_TRANS_EVNT_CBSE_SHIFT   (4U)
 
#define SBC_UJA_TRANS_EVNT_CBSE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CBSE_SHIFT)&SBC_UJA_TRANS_EVNT_CBSE_MASK)
 
#define SBC_UJA_TRANS_EVNT_CFE_MASK   (0x02U)
 Transceiver event capture enable register, CAN failure enable macros. More...
 
#define SBC_UJA_TRANS_EVNT_CFE_SHIFT   (1U)
 
#define SBC_UJA_TRANS_EVNT_CFE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CFE_SHIFT)&SBC_UJA_TRANS_EVNT_CFE_MASK)
 
#define SBC_UJA_TRANS_EVNT_CWE_MASK   (0x01U)
 Transceiver event capture enable register, CAN wake-up enable. More...
 
#define SBC_UJA_TRANS_EVNT_CWE_SHIFT   (0U)
 
#define SBC_UJA_TRANS_EVNT_CWE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CWE_SHIFT)&SBC_UJA_TRANS_EVNT_CWE_MASK)
 
#define SBC_UJA_TRANS_EVNT_MASK
 Transceiver event capture enable register macros. More...
 
#define SBC_UJA_TRANS_EVNT_SHIFT   (0U)
 
#define SBC_UJA_TRANS_EVNT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_SHIFT)&SBC_UJA_TRANS_EVNT_MASK)
 
#define SBC_UJA_DAT_RATE_CDR_MASK   (0x07U)
 Data rate register, CAN data rate selection macros. More...
 
#define SBC_UJA_DAT_RATE_CDR_SHIFT   (0U)
 
#define SBC_UJA_DAT_RATE_CDR_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_DAT_RATE_CDR_SHIFT)&SBC_UJA_DAT_RATE_CDR_MASK)
 
#define SBC_UJA_DAT_RATE_MASK   (SBC_UJA_DAT_RATE_CDR_MASK)
 Data rate register macros. More...
 
#define SBC_UJA_DAT_RATE_SHIFT   (SBC_UJA_DAT_RATE_CDR_SHIFT)
 
#define SBC_UJA_DAT_RATE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_DAT_RATE_SHIFT)&SBC_UJA_DAT_RATE_MASK)
 
#define SBC_UJA_IDENTIF_0700_MASK   (0xFFU)
 Identifier 0x27 - ID07:ID00 bits macros. More...
 
#define SBC_UJA_IDENTIF_0700_SHIFT   (0U)
 
#define SBC_UJA_IDENTIF_0700_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_0700_SHIFT)&SBC_UJA_IDENTIF_0700_MASK)
 
#define SBC_UJA_IDENTIF_1508_MASK   (0xFFU)
 Identifier 0x28 - ID15:ID08 bits macros. More...
 
#define SBC_UJA_IDENTIF_1508_SHIFT   (0U)
 
#define SBC_UJA_IDENTIF_1508_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_1508_SHIFT)&SBC_UJA_IDENTIF_1508_MASK)
 
#define SBC_UJA_IDENTIF_2318_MASK   (0xFCU)
 Identifier 0x29 - ID23:ID18 bits macros. More...
 
#define SBC_UJA_IDENTIF_2318_SHIFT   (2U)
 
#define SBC_UJA_IDENTIF_2318_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2318_SHIFT)&SBC_UJA_IDENTIF_2318_MASK)
 
#define SBC_UJA_IDENTIF_1716_MASK   (0x03U)
 Identifier 0x29 - ID17:ID16 bits macros. More...
 
#define SBC_UJA_IDENTIF_1716_SHIFT   (0U)
 
#define SBC_UJA_IDENTIF_1716_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_1716_SHIFT)&SBC_UJA_IDENTIF_1716_MASK)
 
#define SBC_UJA_IDENTIF_2316_MASK   (0xFFU)
 Identifier 0x29 - ID23:ID16 bits macros. More...
 
#define SBC_UJA_IDENTIF_2316_SHIFT   (0U)
 
#define SBC_UJA_IDENTIF_2316_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2316_SHIFT)&SBC_UJA_IDENTIF_2316_MASK)
 
#define SBC_UJA_IDENTIF_2824_MASK   (0x1FU)
 Identifier 0x2A - ID28:ID24 bits macros. More...
 
#define SBC_UJA_IDENTIF_2824_SHIFT   (0U)
 
#define SBC_UJA_IDENTIF_2824_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2824_SHIFT)&SBC_UJA_IDENTIF_2824_MASK)
 
#define SBC_UJA_IDENTIF_X_MASK   (0xFFU)
 Identifier X macros (0x27-0x2Ah). More...
 
#define SBC_UJA_IDENTIF_X_SHIFT   (0U)
 
#define SBC_UJA_IDENTIF_X_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_0_SHIFT)&SBC_UJA_IDENTIF_0_MASK)
 
#define SBC_UJA_MASK_0700_MASK   (0xFFU)
 Mask 0x2b - M07:M00 macros. More...
 
#define SBC_UJA_MASK_0700_SHIFT   (0U)
 
#define SBC_UJA_MASK_0700_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_0700_SHIFT)&SBC_UJA_MASK_0700_MASK)
 
#define SBC_UJA_MASK_1508_MASK   (0xFFU)
 Mask 0x2c - M15:M08 macros. More...
 
#define SBC_UJA_MASK_1508_SHIFT   (0U)
 
#define SBC_UJA_MASK_1508_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_1508_SHIFT)&SBC_UJA_MASK_1508_MASK)
 
#define SBC_UJA_MASK_2318_MASK   (0xFCU)
 Mask 0x2d - M23:M18 macros. More...
 
#define SBC_UJA_MASK_2318_SHIFT   (2U)
 
#define SBC_UJA_MASK_2318_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2318_SHIFT)&SBC_UJA_MASK_2318_MASK)
 
#define SBC_UJA_MASK_1716_MASK   (0x03U)
 Mask 0x2d - M17:M16 macros. More...
 
#define SBC_UJA_MASK_1716_SHIFT   (2U)
 
#define SBC_UJA_MASK_1716_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_1716_SHIFT)&SBC_UJA_MASK_1716_MASK)
 
#define SBC_UJA_MASK_2316_MASK   (0xFFU)
 Mask 0x2d - M23:M16 macros. More...
 
#define SBC_UJA_MASK_2316_SHIFT   (0U)
 
#define SBC_UJA_MASK_2316_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2316_SHIFT)&SBC_UJA_MASK_2316_MASK)
 
#define SBC_UJA_MASK_2824_MASK   (0x1FU)
 Mask 0x2e - M28:M24 macros. More...
 
#define SBC_UJA_MASK_2824_SHIFT   (0U)
 
#define SBC_UJA_MASK_2824_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2824_SHIFT)&SBC_UJA_MASK_2824_MASK)
 
#define SBC_UJA_MASK_X_MASK   (0xFFU)
 Mask X macros (0x2b-0x2e). More...
 
#define SBC_UJA_MASK_X_SHIFT   (0U)
 
#define SBC_UJA_MASK_X_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_X_SHIFT)&SBC_UJA_MASK_X_MASK)
 
#define SBC_UJA_FRAME_CTR_IDE_MASK   (0x80U)
 Frame control register, identifier format macros. More...
 
#define SBC_UJA_FRAME_CTR_IDE_SHIFT   (7U)
 
#define SBC_UJA_FRAME_CTR_IDE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_IDE_SHIFT)&SBC_UJA_FRAME_CTR_IDE_MASK)
 
#define SBC_UJA_FRAME_CTR_PNDM_MASK   (0x40U)
 Frame control register, partial networking data mask macros. More...
 
#define SBC_UJA_FRAME_CTR_PNDM_SHIFT   (6U)
 
#define SBC_UJA_FRAME_CTR_PNDM_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_PNDM_SHIFT)&SBC_UJA_FRAME_CTR_PNDM_MASK)
 
#define SBC_UJA_FRAME_CTR_DLC_MASK   (0x0FU)
 Frame control register, number of data bytes expected in a CAN frame macros. More...
 
#define SBC_UJA_FRAME_CTR_DLC_SHIFT   (0U)
 
#define SBC_UJA_FRAME_CTR_DLC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_DLC_SHIFT)&SBC_UJA_FRAME_CTR_DLC_MASK)
 
#define SBC_UJA_FRAME_CTR_MASK
 Frame control register. More...
 
#define SBC_UJA_FRAME_CTR_SHIFT   (0U)
 
#define SBC_UJA_FRAME_CTR_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_SHIFT)&SBC_UJA_FRAME_CTR_MASK)
 
#define SBC_UJA_DATA_MASK_X_MASK   (0xFFU)
 Data mask registers (0x68 to 0x6F) macros Data mask 0-7 configuration. More...
 
#define SBC_UJA_DATA_MASK_X_SHIFT   (0U)
 
#define SBC_UJA_DATA_MASK_X_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_DATA_MASK_X_SHIFT)&SBC_UJA_DATA_MASK_X_MASK)
 
#define SBC_UJA_WAKE_STAT_WPVS_MASK   (0x02FU)
 WAKE pin status register, WAKE pin status macros. More...
 
#define SBC_UJA_WAKE_STAT_WPVS_SHIFT   (1U)
 
#define SBC_UJA_WAKE_STAT_WPVS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_STAT_WPVS_SHIFT)&SBC_UJA_WAKE_STAT_WPVS_MASK)
 
#define SBC_UJA_WAKE_STAT_MASK   (SBC_UJA_WAKE_STAT_WPVS_MASK)
 WAKE pin status register. More...
 
#define SBC_UJA_WAKE_STAT_SHIFT   (SBC_UJA_WAKE_STAT_WPVS_SHIFT)
 
#define SBC_UJA_WAKE_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_STAT_SHIFT)&SBC_UJA_WAKE_STAT_MASK)
 
#define SBC_UJA_WAKE_EN_WPRE_MASK   (0x02U)
 WAKE pin event capture enable register, WAKE pin rising-edge enable macros. More...
 
#define SBC_UJA_WAKE_EN_WPRE_SHIFT   (1U)
 
#define SBC_UJA_WAKE_EN_WPRE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_WPRE_SHIFT)&SBC_UJA_WAKE_EN_WPRE_MASK)
 
#define SBC_UJA_WAKE_EN_WPFE_MASK   (0x01U)
 WAKE pin event capture enable register, WAKE pin falling-edge enable macros. More...
 
#define SBC_UJA_WAKE_EN_WPFE_SHIFT   (0U)
 
#define SBC_UJA_WAKE_EN_WPFE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_WPFE_SHIFT)&SBC_UJA_WAKE_EN_WPFE_MASK)
 
#define SBC_UJA_WAKE_EN_MASK   (SBC_UJA_WAKE_EN_WPRE_MASK | SBC_UJA_WAKE_EN_WPFE_MASK)
 WAKE pin event capture enable register macros. More...
 
#define SBC_UJA_WAKE_EN_SHIFT   (0U)
 
#define SBC_UJA_WAKE_EN_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_SHIFT)&SBC_UJA_WAKE_EN_MASK)
 
#define SBC_UJA_GL_EVNT_STAT_WPE_MASK   (0x08U)
 Global event status register, WAKE pin event macros. More...
 
#define SBC_UJA_GL_EVNT_STAT_WPE_SHIFT   (3U)
 
#define SBC_UJA_GL_EVNT_STAT_WPE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_WPE_SHIFT)&SBC_UJA_GL_EVNT_STAT_WPE_MASK)
 
#define SBC_UJA_GL_EVNT_STAT_TRXE_MASK   (0x04U)
 Global event status register, transceiver event macros. More...
 
#define SBC_UJA_GL_EVNT_STAT_TRXE_SHIFT   (2U)
 
#define SBC_UJA_GL_EVNT_STAT_TRXE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_TRXE_SHIFT)&SBC_UJA_GL_EVNT_STAT_TRXE_MASK)
 
#define SBC_UJA_GL_EVNT_STAT_SUPE_MASK   (0x02U)
 Global event status register, supply event macros. More...
 
#define SBC_UJA_GL_EVNT_STAT_SUPE_SHIFT   (1U)
 
#define SBC_UJA_GL_EVNT_STAT_SUPE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SUPE_SHIFT)&SBC_UJA_GL_EVNT_STAT_SUPE_MASK)
 
#define SBC_UJA_GL_EVNT_STAT_SYSE_MASK   (0x01U)
 Global event status register, system event macros. More...
 
#define SBC_UJA_GL_EVNT_STAT_SYSE_SHIFT   (0U)
 
#define SBC_UJA_GL_EVNT_STAT_SYSE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SYSE_SHIFT)&SBC_UJA_GL_EVNT_STAT_SYSE_MASK)
 
#define SBC_UJA_GL_EVNT_STAT_MASK
 Global event status register macros. More...
 
#define SBC_UJA_GL_EVNT_STAT_SHIFT   (0U)
 
#define SBC_UJA_GL_EVNT_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SHIFT)&SBC_UJA_GL_EVNT_STAT_MASK)
 
#define SBC_UJA_SYS_EVNT_STAT_PO_MASK   (0x10U)
 System event status register, power-on macros. More...
 
#define SBC_UJA_SYS_EVNT_STAT_PO_SHIFT   (4U)
 
#define SBC_UJA_SYS_EVNT_STAT_PO_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_PO_SHIFT)&SBC_UJA_SYS_EVNT_STAT_PO_MASK)
 
#define SBC_UJA_SYS_EVNT_STAT_OTW_MASK   (0x04U)
 System event status register, overtemperature warning macros. More...
 
#define SBC_UJA_SYS_EVNT_STAT_OTW_SHIFT   (2U)
 
#define SBC_UJA_SYS_EVNT_STAT_OTW_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_OTW_SHIFT)&SBC_UJA_SYS_EVNT_STAT_OTW_MASK)
 
#define SBC_UJA_SYS_EVNT_STAT_SPIF_MASK   (0x02U)
 System event status register, SPI failure macros. More...
 
#define SBC_UJA_SYS_EVNT_STAT_SPIF_SHIFT   (1U)
 
#define SBC_UJA_SYS_EVNT_STAT_SPIF_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_SPIF_SHIFT)&SBC_UJA_SYS_EVNT_STAT_SPIF_MASK)
 
#define SBC_UJA_SYS_EVNT_STAT_WDF_MASK   (0x01U)
 System event status register, watchdog failure macros. More...
 
#define SBC_UJA_SYS_EVNT_STAT_WDF_SHIFT   (0U)
 
#define SBC_UJA_SYS_EVNT_STAT_WDF_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_WDF_SHIFT)&SBC_UJA_SYS_EVNT_STAT_WDF_MASK)
 
#define SBC_UJA_SYS_EVNT_STAT_MASK
 System event status register macros. More...
 
#define SBC_UJA_SYS_EVNT_STAT_SHIFT   (0U)
 
#define SBC_UJA_SYS_EVNT_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_SHIFT)&SBC_UJA_SYS_EVNT_STAT_MASK)
 
#define SBC_UJA_SUP_EVNT_STAT_V2O_MASK   (0x04U)
 Supply event status register, V2/VEXT overvoltage macros. More...
 
#define SBC_UJA_SUP_EVNT_STAT_V2O_SHIFT   (2U)
 
#define SBC_UJA_SUP_EVNT_STAT_V2O_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V2O_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V2O_MASK)
 
#define SBC_UJA_SUP_EVNT_STAT_V2U_MASK   (0x02U)
 Supply event status register, V2/VEXT undervoltage macros. More...
 
#define SBC_UJA_SUP_EVNT_STAT_V2U_SHIFT   (1U)
 
#define SBC_UJA_SUP_EVNT_STAT_V2U_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V2U_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V2U_MASK)
 
#define SBC_UJA_SUP_EVNT_STAT_V1U_MASK   (0x01U)
 Supply event status register, V1 undervoltage: macros. More...
 
#define SBC_UJA_SUP_EVNT_STAT_V1U_SHIFT   (0U)
 
#define SBC_UJA_SUP_EVNT_STAT_V1U_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V1U_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V1U_MASK)
 
#define SBC_UJA_SUP_EVNT_STAT_MASK
 Supply event status register macros. More...
 
#define SBC_UJA_SUP_EVNT_STAT_SHIFT   (0U)
 
#define SBC_UJA_SUP_EVNT_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_SHIFT)&SBC_UJA_SUP_EVNT_STAT_MASK)
 
#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK   (0x20U)
 Transceiver event status register, partial networking frame detection error macros. More...
 
#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_SHIFT   (5U)
 
#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_PNFDE_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK)
 
#define SBC_UJA_TRANS_EVNT_STAT_CBS_MASK   (0x10U)
 Transceiver event status register, CAN-bus status macros. More...
 
#define SBC_UJA_TRANS_EVNT_STAT_CBS_SHIFT   (4U)
 
#define SBC_UJA_TRANS_EVNT_STAT_CBS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CBS_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CBS_MASK)
 
#define SBC_UJA_TRANS_EVNT_STAT_CF_MASK   (0x02U)
 Transceiver event status register, CAN failure. More...
 
#define SBC_UJA_TRANS_EVNT_STAT_CF_SHIFT   (1U)
 
#define SBC_UJA_TRANS_EVNT_STAT_CF_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CF_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CF_MASK)
 
#define SBC_UJA_TRANS_EVNT_STAT_CW_MASK   (0x01U)
 Transceiver event status register, CAN wake-up. More...
 
#define SBC_UJA_TRANS_EVNT_STAT_CW_SHIFT   (0U)
 
#define SBC_UJA_TRANS_EVNT_STAT_CW_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CW_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CW_MASK)
 
#define SBC_UJA_TRANS_EVNT_STAT_MASK
 Transceiver event status register macros. More...
 
#define SBC_UJA_TRANS_EVNT_STAT_SHIFT   (0U)
 
#define SBC_UJA_TRANS_EVNT_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_MASK)
 
#define SBC_UJA_WAKE_EVNT_STAT_WPR_MASK   (0x02U)
 WAKE pin event status register, WAKE pin rising edge macros. More...
 
#define SBC_UJA_WAKE_EVNT_STAT_WPR_SHIFT   (1U)
 
#define SBC_UJA_WAKE_EVNT_STAT_WPR_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_WPR_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_WPR_MASK)
 
#define SBC_UJA_WAKE_EVNT_STAT_WPF_MASK   (0x01U)
 WAKE pin event status register, WAKE pin falling edge macros. More...
 
#define SBC_UJA_WAKE_EVNT_STAT_WPF_SHIFT   (0U)
 
#define SBC_UJA_WAKE_EVNT_STAT_WPF_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_WPF_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_WPF_MASK)
 
#define SBC_UJA_WAKE_EVNT_STAT_MASK   (SBC_UJA_WAKE_EVNT_STAT_WPR_MASK | SBC_UJA_WAKE_EVNT_STAT_WPF_MASK)
 WAKE pin event status register macros. More...
 
#define SBC_UJA_WAKE_EVNT_STAT_SHIFT   (0U)
 
#define SBC_UJA_WAKE_EVNT_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_MASK)
 
#define SBC_UJA_MTPNV_STAT_WRCNTS_MASK   (0xFCU)
 MTPNV status register, write counter status macros. More...
 
#define SBC_UJA_MTPNV_STAT_WRCNTS_SHIFT   (2U)
 
#define SBC_UJA_MTPNV_STAT_WRCNTS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_WRCNTS_SHIFT)&SBC_UJA_MTPNV_STAT_WRCNTS_MASK)
 
#define SBC_UJA_MTPNV_STAT_ECCS_MASK   (0x02U)
 MTPNV status register, error correction code status. More...
 
#define SBC_UJA_MTPNV_STAT_ECCS_SHIFT   (1U)
 
#define SBC_UJA_MTPNV_STAT_ECCS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_ECCS_SHIFT)&SBC_UJA_MTPNV_STAT_ECCS_MASK)
 
#define SBC_UJA_MTPNV_STAT_NVMPS_MASK   (0x01U)
 MTPNV status register, non-volatile memory programming status. More...
 
#define SBC_UJA_MTPNV_STAT_NVMPS_SHIFT   (0U)
 
#define SBC_UJA_MTPNV_STAT_NVMPS_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_NVMPS_SHIFT)&SBC_UJA_MTPNV_STAT_NVMPS_MASK)
 
#define SBC_UJA_MTPNV_STAT_MASK
 MTPNV status register macros. More...
 
#define SBC_UJA_MTPNV_STAT_SHIFT   (0U)
 
#define SBC_UJA_MTPNV_STAT_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_SHIFT)&SBC_UJA_MTPNV_STAT_MASK)
 
#define SBC_UJA_START_UP_RLC_MASK   (0x30U)
 Start-up control register, RSTN output reset pulse width macros. More...
 
#define SBC_UJA_START_UP_RLC_SHIFT   (4U)
 
#define SBC_UJA_START_UP_RLC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_RLC_SHIFT)&SBC_UJA_START_UP_RLC_MASK)
 
#define SBC_UJA_START_UP_V2SUC_MASK   (0x08U)
 Start-up control register, V2/VEXT start-up control macros. More...
 
#define SBC_UJA_START_UP_V2SUC_SHIFT   (3U)
 
#define SBC_UJA_START_UP_V2SUC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_V2SUC_SHIFT)&SBC_UJA_START_UP_V2SUC_MASK)
 
#define SBC_UJA_START_UP_MASK   (SBC_UJA_START_UP_RLC_MASK | SBC_UJA_START_UP_V2SUC_MASK)
 Start-up control register macros. More...
 
#define SBC_UJA_START_UP_SHIFT   (3U)
 
#define SBC_UJA_START_UP_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_SHIFT)&SBC_UJA_START_UP_MASK)
 
#define SBC_UJA_SBC_V1RTSUC_MASK   (0x30U)
 SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up macros. More...
 
#define SBC_UJA_SBC_V1RTSUC_SHIFT   (4U)
 
#define SBC_UJA_SBC_V1RTSUC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_V1RTSUC_SHIFT)&SBC_UJA_SBC_V1RTSUC_MASK)
 
#define SBC_UJA_SBC_FNMC_MASK   (0x08U)
 SBC configuration control register, Forced Normal mode control macros. More...
 
#define SBC_UJA_SBC_FNMC_SHIFT   (3U)
 
#define SBC_UJA_SBC_FNMC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_FNMC_SHIFT)&SBC_UJA_SBC_FNMC_MASK)
 
#define SBC_UJA_SBC_SDMC_MASK   (0x04U)
 SBC configuration control register, Software Development mode control macros. More...
 
#define SBC_UJA_SBC_SDMC_SHIFT   (2U)
 
#define SBC_UJA_SBC_SDMC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SDMC_SHIFT)&SBC_UJA_SBC_SDMC_MASK)
 
#define SBC_UJA_SBC_SLPC_MASK   (0x01U)
 SBC configuration control register, Sleep control macros. More...
 
#define SBC_UJA_SBC_SLPC_SHIFT   (0U)
 
#define SBC_UJA_SBC_SLPC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SLPC_SHIFT)&SBC_UJA_SBC_SLPC_MASK)
 
#define SBC_UJA_SBC_MASK
 SBC configuration control register macros. More...
 
#define SBC_UJA_SBC_SHIFT   (0U)
 
#define SBC_UJA_SBC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SHIFT)&SBC_UJA_SBC_MASK)
 
#define SBC_UJA_MTPNV_CRC_MASK   (0xFFU)
 MTPNV CRC control register macros. More...
 
#define SBC_UJA_MTPNV_CRC_SHIFT   (0U)
 
#define SBC_UJA_MTPNV_CRC_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_CRC_SHIFT)&SBC_UJA_MTPNV_CRC_MASK)
 
#define SBC_UJA_IDENTIF_MASK   (0xFFU)
 Device identification register macros. More...
 
#define SBC_UJA_IDENTIF_SHIFT   (0U)
 
#define SBC_UJA_IDENTIF_F(x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_SHIFT)&SBC_UJA_IDENTIF_MASK)
 

Macro Definition Documentation

#define SBC_UJA_CAN_CFDC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CFDC_SHIFT)&SBC_UJA_CAN_CFDC_MASK)

Definition at line 337 of file UJA1169.h.

#define SBC_UJA_CAN_CFDC_MASK   (0x40U)

CAN control register, CAN FD control macros.

Definition at line 335 of file UJA1169.h.

#define SBC_UJA_CAN_CFDC_SHIFT   (6U)

Definition at line 336 of file UJA1169.h.

#define SBC_UJA_CAN_CMC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CMC_SHIFT)&SBC_UJA_CAN_CMC_MASK)

Definition at line 358 of file UJA1169.h.

#define SBC_UJA_CAN_CMC_MASK   (0x03U)

CAN control register, CAN mode control macros.

Definition at line 356 of file UJA1169.h.

#define SBC_UJA_CAN_CMC_SHIFT   (0U)

Definition at line 357 of file UJA1169.h.

#define SBC_UJA_CAN_CPNC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CPNC_SHIFT)&SBC_UJA_CAN_CPNC_MASK)

Definition at line 351 of file UJA1169.h.

#define SBC_UJA_CAN_CPNC_MASK   (0x10U)

CAN control register, CAN partial networking control macros.

Definition at line 349 of file UJA1169.h.

#define SBC_UJA_CAN_CPNC_SHIFT   (4U)

Definition at line 350 of file UJA1169.h.

#define SBC_UJA_CAN_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_SHIFT)&SBC_UJA_CAN_MASK)

Definition at line 366 of file UJA1169.h.

#define SBC_UJA_CAN_MASK
Value:
#define SBC_UJA_CAN_CPNC_MASK
CAN control register, CAN partial networking control macros.
Definition: UJA1169.h:349
#define SBC_UJA_CAN_PNCOK_MASK
CAN control register, CAN partial networking configuration OK macros.
Definition: UJA1169.h:342
#define SBC_UJA_CAN_CFDC_MASK
CAN control register, CAN FD control macros.
Definition: UJA1169.h:335
#define SBC_UJA_CAN_CMC_MASK
CAN control register, CAN mode control macros.
Definition: UJA1169.h:356

CAN control register macros.

Definition at line 363 of file UJA1169.h.

#define SBC_UJA_CAN_PNCOK_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_PNCOK_SHIFT)&SBC_UJA_CAN_PNCOK_MASK)

Definition at line 344 of file UJA1169.h.

#define SBC_UJA_CAN_PNCOK_MASK   (0x20U)

CAN control register, CAN partial networking configuration OK macros.

Definition at line 342 of file UJA1169.h.

#define SBC_UJA_CAN_PNCOK_SHIFT   (5U)

Definition at line 343 of file UJA1169.h.

#define SBC_UJA_CAN_SHIFT   (0U)

Definition at line 365 of file UJA1169.h.

#define SBC_UJA_DAT_RATE_CDR_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_DAT_RATE_CDR_SHIFT)&SBC_UJA_DAT_RATE_CDR_MASK)

Definition at line 461 of file UJA1169.h.

#define SBC_UJA_DAT_RATE_CDR_MASK   (0x07U)

Data rate register, CAN data rate selection macros.

Definition at line 459 of file UJA1169.h.

#define SBC_UJA_DAT_RATE_CDR_SHIFT   (0U)

Definition at line 460 of file UJA1169.h.

#define SBC_UJA_DAT_RATE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_DAT_RATE_SHIFT)&SBC_UJA_DAT_RATE_MASK)

Definition at line 468 of file UJA1169.h.

#define SBC_UJA_DAT_RATE_MASK   (SBC_UJA_DAT_RATE_CDR_MASK)

Data rate register macros.

Definition at line 466 of file UJA1169.h.

#define SBC_UJA_DAT_RATE_SHIFT   (SBC_UJA_DAT_RATE_CDR_SHIFT)

Definition at line 467 of file UJA1169.h.

#define SBC_UJA_DATA_MASK_X_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_DATA_MASK_X_SHIFT)&SBC_UJA_DATA_MASK_X_MASK)

Definition at line 603 of file UJA1169.h.

#define SBC_UJA_DATA_MASK_X_MASK   (0xFFU)

Data mask registers (0x68 to 0x6F) macros Data mask 0-7 configuration.

Definition at line 601 of file UJA1169.h.

#define SBC_UJA_DATA_MASK_X_SHIFT   (0U)

Definition at line 602 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_SHIFT)&SBC_UJA_FAIL_SAFE_MASK)

Definition at line 106 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_LHC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_LHC_SHIFT)&SBC_UJA_FAIL_SAFE_LHC_MASK)

Definition at line 92 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_LHC_MASK   (0x04U)

Fail-safe control register, LIMP home control macros.

Definition at line 90 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_LHC_SHIFT   (2U)

Definition at line 91 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_MASK   (SBC_UJA_FAIL_SAFE_LHC_MASK | SBC_UJA_FAIL_SAFE_RCC_MASK)

Fail-safe control register macros.

Definition at line 104 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_RCC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_RCC_SHIFT)&SBC_UJA_FAIL_SAFE_RCC_MASK)

Definition at line 99 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_RCC_MASK   (0x03U)

Fail-safe control register, reset counter control macros.

Definition at line 97 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_RCC_SHIFT   (0U)

Definition at line 98 of file UJA1169.h.

#define SBC_UJA_FAIL_SAFE_SHIFT   (0U)

Definition at line 105 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_DLC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_DLC_SHIFT)&SBC_UJA_FRAME_CTR_DLC_MASK)

Definition at line 587 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_DLC_MASK   (0x0FU)

Frame control register, number of data bytes expected in a CAN frame macros.

Definition at line 585 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_DLC_SHIFT   (0U)

Definition at line 586 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_SHIFT)&SBC_UJA_FRAME_CTR_MASK)

Definition at line 595 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_IDE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_IDE_SHIFT)&SBC_UJA_FRAME_CTR_IDE_MASK)

Definition at line 573 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_IDE_MASK   (0x80U)

Frame control register, identifier format macros.

Definition at line 571 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_IDE_SHIFT   (7U)

Definition at line 572 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_MASK
Value:
#define SBC_UJA_FRAME_CTR_PNDM_MASK
Frame control register, partial networking data mask macros.
Definition: UJA1169.h:578
#define SBC_UJA_FRAME_CTR_DLC_MASK
Frame control register, number of data bytes expected in a CAN frame macros.
Definition: UJA1169.h:585
#define SBC_UJA_FRAME_CTR_IDE_MASK
Frame control register, identifier format macros.
Definition: UJA1169.h:571

Frame control register.

Definition at line 592 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_PNDM_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_PNDM_SHIFT)&SBC_UJA_FRAME_CTR_PNDM_MASK)

Definition at line 580 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_PNDM_MASK   (0x40U)

Frame control register, partial networking data mask macros.

Definition at line 578 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_PNDM_SHIFT   (6U)

Definition at line 579 of file UJA1169.h.

#define SBC_UJA_FRAME_CTR_SHIFT   (0U)

Definition at line 594 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SHIFT)&SBC_UJA_GL_EVNT_STAT_MASK)

Definition at line 676 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_MASK
Value:
#define SBC_UJA_GL_EVNT_STAT_SUPE_MASK
Global event status register, supply event macros.
Definition: UJA1169.h:659
#define SBC_UJA_GL_EVNT_STAT_WPE_MASK
Global event status register, WAKE pin event macros.
Definition: UJA1169.h:645
#define SBC_UJA_GL_EVNT_STAT_TRXE_MASK
Global event status register, transceiver event macros.
Definition: UJA1169.h:652
#define SBC_UJA_GL_EVNT_STAT_SYSE_MASK
Global event status register, system event macros.
Definition: UJA1169.h:666

Global event status register macros.

Definition at line 673 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_SHIFT   (0U)

Definition at line 675 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_SUPE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SUPE_SHIFT)&SBC_UJA_GL_EVNT_STAT_SUPE_MASK)

Definition at line 661 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_SUPE_MASK   (0x02U)

Global event status register, supply event macros.

Definition at line 659 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_SUPE_SHIFT   (1U)

Definition at line 660 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_SYSE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SYSE_SHIFT)&SBC_UJA_GL_EVNT_STAT_SYSE_MASK)

Definition at line 668 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_SYSE_MASK   (0x01U)

Global event status register, system event macros.

Definition at line 666 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_SYSE_SHIFT   (0U)

Definition at line 667 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_TRXE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_TRXE_SHIFT)&SBC_UJA_GL_EVNT_STAT_TRXE_MASK)

Definition at line 654 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_TRXE_MASK   (0x04U)

Global event status register, transceiver event macros.

Definition at line 652 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_TRXE_SHIFT   (2U)

Definition at line 653 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_WPE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_WPE_SHIFT)&SBC_UJA_GL_EVNT_STAT_WPE_MASK)

Definition at line 647 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_WPE_MASK   (0x08U)

Global event status register, WAKE pin event macros.

Definition at line 645 of file UJA1169.h.

#define SBC_UJA_GL_EVNT_STAT_WPE_SHIFT   (3U)

Definition at line 646 of file UJA1169.h.

#define SBC_UJA_IDENTIF_0700_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_0700_SHIFT)&SBC_UJA_IDENTIF_0700_MASK)

Definition at line 475 of file UJA1169.h.

#define SBC_UJA_IDENTIF_0700_MASK   (0xFFU)

Identifier 0x27 - ID07:ID00 bits macros.

Definition at line 473 of file UJA1169.h.

#define SBC_UJA_IDENTIF_0700_SHIFT   (0U)

Definition at line 474 of file UJA1169.h.

#define SBC_UJA_IDENTIF_1508_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_1508_SHIFT)&SBC_UJA_IDENTIF_1508_MASK)

Definition at line 482 of file UJA1169.h.

#define SBC_UJA_IDENTIF_1508_MASK   (0xFFU)

Identifier 0x28 - ID15:ID08 bits macros.

Definition at line 480 of file UJA1169.h.

#define SBC_UJA_IDENTIF_1508_SHIFT   (0U)

Definition at line 481 of file UJA1169.h.

#define SBC_UJA_IDENTIF_1716_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_1716_SHIFT)&SBC_UJA_IDENTIF_1716_MASK)

Definition at line 496 of file UJA1169.h.

#define SBC_UJA_IDENTIF_1716_MASK   (0x03U)

Identifier 0x29 - ID17:ID16 bits macros.

Definition at line 494 of file UJA1169.h.

#define SBC_UJA_IDENTIF_1716_SHIFT   (0U)

Definition at line 495 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2316_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2316_SHIFT)&SBC_UJA_IDENTIF_2316_MASK)

Definition at line 503 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2316_MASK   (0xFFU)

Identifier 0x29 - ID23:ID16 bits macros.

Definition at line 501 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2316_SHIFT   (0U)

Definition at line 502 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2318_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2318_SHIFT)&SBC_UJA_IDENTIF_2318_MASK)

Definition at line 489 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2318_MASK   (0xFCU)

Identifier 0x29 - ID23:ID18 bits macros.

Definition at line 487 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2318_SHIFT   (2U)

Definition at line 488 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2824_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2824_SHIFT)&SBC_UJA_IDENTIF_2824_MASK)

Definition at line 510 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2824_MASK   (0x1FU)

Identifier 0x2A - ID28:ID24 bits macros.

Definition at line 508 of file UJA1169.h.

#define SBC_UJA_IDENTIF_2824_SHIFT   (0U)

Definition at line 509 of file UJA1169.h.

#define SBC_UJA_IDENTIF_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_SHIFT)&SBC_UJA_IDENTIF_MASK)

Definition at line 902 of file UJA1169.h.

#define SBC_UJA_IDENTIF_MASK   (0xFFU)

Device identification register macros.

Definition at line 900 of file UJA1169.h.

#define SBC_UJA_IDENTIF_SHIFT   (0U)

Definition at line 901 of file UJA1169.h.

#define SBC_UJA_IDENTIF_X_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_0_SHIFT)&SBC_UJA_IDENTIF_0_MASK)

Definition at line 517 of file UJA1169.h.

#define SBC_UJA_IDENTIF_X_MASK   (0xFFU)

Identifier X macros (0x27-0x2Ah).

Definition at line 515 of file UJA1169.h.

#define SBC_UJA_IDENTIF_X_SHIFT   (0U)

Definition at line 516 of file UJA1169.h.

#define SBC_UJA_LOCK_LK0C_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK0C_SHIFT)&SBC_UJA_LOCK_LK0C_MASK)

Definition at line 240 of file UJA1169.h.

#define SBC_UJA_LOCK_LK0C_MASK   (0x01U)

Lock control 0: address area 0x06 to 0x09 - general-purpose memory macros.

Definition at line 238 of file UJA1169.h.

#define SBC_UJA_LOCK_LK0C_SHIFT   (0U)

Definition at line 239 of file UJA1169.h.

#define SBC_UJA_LOCK_LK1C_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK1C_SHIFT)&SBC_UJA_LOCK_LK1C_MASK)

Definition at line 233 of file UJA1169.h.

#define SBC_UJA_LOCK_LK1C_MASK   (0x02U)

Lock control 1: address area 0x10 to 0x1F - regulator control macros.

Definition at line 231 of file UJA1169.h.

#define SBC_UJA_LOCK_LK1C_SHIFT   (1U)

Definition at line 232 of file UJA1169.h.

#define SBC_UJA_LOCK_LK2C_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK2C_SHIFT)&SBC_UJA_LOCK_LK2C_MASK)

Definition at line 226 of file UJA1169.h.

#define SBC_UJA_LOCK_LK2C_MASK   (0x04U)

Lock control 2: address area 0x20 to 0x2F - transceiver control macros.

Definition at line 224 of file UJA1169.h.

#define SBC_UJA_LOCK_LK2C_SHIFT   (2U)

Definition at line 225 of file UJA1169.h.

#define SBC_UJA_LOCK_LK3C_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK3C_SHIFT)&SBC_UJA_LOCK_LK3C_MASK)

Definition at line 219 of file UJA1169.h.

#define SBC_UJA_LOCK_LK3C_MASK   (0x08U)

Lock control 3: address area 0x30 to 0x3F - unused register range macros.

Definition at line 217 of file UJA1169.h.

#define SBC_UJA_LOCK_LK3C_SHIFT   (3U)

Definition at line 218 of file UJA1169.h.

#define SBC_UJA_LOCK_LK4C_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK4C_SHIFT)&SBC_UJA_LOCK_LK4C_MASK)

Definition at line 212 of file UJA1169.h.

#define SBC_UJA_LOCK_LK4C_MASK   (0x10U)

Lock control 4: address area 0x40 to 0x4F - WAKE pin control macros.

Definition at line 210 of file UJA1169.h.

#define SBC_UJA_LOCK_LK4C_SHIFT   (4U)

Definition at line 211 of file UJA1169.h.

#define SBC_UJA_LOCK_LK5C_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK5C_SHIFT)&SBC_UJA_LOCK_LK5C_MASK)

Definition at line 205 of file UJA1169.h.

#define SBC_UJA_LOCK_LK5C_MASK   (0x20U)

Lock control control 5: address area 0x50 to 0x5F - unused register range macros.

Definition at line 203 of file UJA1169.h.

#define SBC_UJA_LOCK_LK5C_SHIFT   (5U)

Definition at line 204 of file UJA1169.h.

#define SBC_UJA_LOCK_LK6C_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK6C_SHIFT)&SBC_UJA_LOCK_LK6C_MASK)

Definition at line 198 of file UJA1169.h.

#define SBC_UJA_LOCK_LK6C_MASK   (0x40U)

Lock control 6: address area 0x68 to 0x6F macros.

Definition at line 196 of file UJA1169.h.

#define SBC_UJA_LOCK_LK6C_SHIFT   (6U)

Definition at line 197 of file UJA1169.h.

#define SBC_UJA_LOCK_LKNC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LKNC_SHIFT)&SBC_UJA_LOCK_LKNC_MASK)

Definition at line 250 of file UJA1169.h.

#define SBC_UJA_LOCK_LKNC_MASK
Value:
#define SBC_UJA_LOCK_LK6C_MASK
Lock control 6: address area 0x68 to 0x6F macros.
Definition: UJA1169.h:196
#define SBC_UJA_LOCK_LK2C_MASK
Lock control 2: address area 0x20 to 0x2F - transceiver control macros.
Definition: UJA1169.h:224
#define SBC_UJA_LOCK_LK1C_MASK
Lock control 1: address area 0x10 to 0x1F - regulator control macros.
Definition: UJA1169.h:231
#define SBC_UJA_LOCK_LK3C_MASK
Lock control 3: address area 0x30 to 0x3F - unused register range macros.
Definition: UJA1169.h:217
#define SBC_UJA_LOCK_LK4C_MASK
Lock control 4: address area 0x40 to 0x4F - WAKE pin control macros.
Definition: UJA1169.h:210
#define SBC_UJA_LOCK_LK5C_MASK
Lock control control 5: address area 0x50 to 0x5F - unused register range macros. ...
Definition: UJA1169.h:203
#define SBC_UJA_LOCK_LK0C_MASK
Lock control 0: address area 0x06 to 0x09 - general-purpose memory macros.
Definition: UJA1169.h:238

Lock control N macros.

Definition at line 245 of file UJA1169.h.

#define SBC_UJA_LOCK_LKNC_SHIFT   (0U)

Definition at line 249 of file UJA1169.h.

#define SBC_UJA_MAIN_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_SHIFT)&SBC_UJA_MAIN_MASK)

Definition at line 134 of file UJA1169.h.

Main status macros.

Definition at line 132 of file UJA1169.h.

#define SBC_UJA_MAIN_NMS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_NMS_SHIFT)&SBC_UJA_MAIN_NMS_MASK)

Definition at line 120 of file UJA1169.h.

#define SBC_UJA_MAIN_NMS_MASK   (0x20U)

Main status register, Normal mode status macros.

Definition at line 118 of file UJA1169.h.

#define SBC_UJA_MAIN_NMS_SHIFT   (5U)

Definition at line 119 of file UJA1169.h.

#define SBC_UJA_MAIN_OTWS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_OTWS_SHIFT)&SBC_UJA_MAIN_OTWS_MASK)

Definition at line 113 of file UJA1169.h.

#define SBC_UJA_MAIN_OTWS_MASK   (0x40U)

Main status register, Overtemperature warning status macros.

Definition at line 111 of file UJA1169.h.

#define SBC_UJA_MAIN_OTWS_SHIFT   (6U)

Definition at line 112 of file UJA1169.h.

#define SBC_UJA_MAIN_RSS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_RSS_SHIFT)&SBC_UJA_MAIN_RSS_MASK)

Definition at line 127 of file UJA1169.h.

#define SBC_UJA_MAIN_RSS_MASK   (0x1FU)

Main status register, Reset source status macros.

Definition at line 125 of file UJA1169.h.

#define SBC_UJA_MAIN_RSS_SHIFT   (0U)

Definition at line 126 of file UJA1169.h.

#define SBC_UJA_MAIN_SHIFT   (0U)

Definition at line 133 of file UJA1169.h.

#define SBC_UJA_MASK_0700_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_0700_SHIFT)&SBC_UJA_MASK_0700_MASK)

Definition at line 524 of file UJA1169.h.

#define SBC_UJA_MASK_0700_MASK   (0xFFU)

Mask 0x2b - M07:M00 macros.

Definition at line 522 of file UJA1169.h.

#define SBC_UJA_MASK_0700_SHIFT   (0U)

Definition at line 523 of file UJA1169.h.

#define SBC_UJA_MASK_1508_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_1508_SHIFT)&SBC_UJA_MASK_1508_MASK)

Definition at line 531 of file UJA1169.h.

#define SBC_UJA_MASK_1508_MASK   (0xFFU)

Mask 0x2c - M15:M08 macros.

Definition at line 529 of file UJA1169.h.

#define SBC_UJA_MASK_1508_SHIFT   (0U)

Definition at line 530 of file UJA1169.h.

#define SBC_UJA_MASK_1716_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_1716_SHIFT)&SBC_UJA_MASK_1716_MASK)

Definition at line 545 of file UJA1169.h.

#define SBC_UJA_MASK_1716_MASK   (0x03U)

Mask 0x2d - M17:M16 macros.

Definition at line 543 of file UJA1169.h.

#define SBC_UJA_MASK_1716_SHIFT   (2U)

Definition at line 544 of file UJA1169.h.

#define SBC_UJA_MASK_2316_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2316_SHIFT)&SBC_UJA_MASK_2316_MASK)

Definition at line 552 of file UJA1169.h.

#define SBC_UJA_MASK_2316_MASK   (0xFFU)

Mask 0x2d - M23:M16 macros.

Definition at line 550 of file UJA1169.h.

#define SBC_UJA_MASK_2316_SHIFT   (0U)

Definition at line 551 of file UJA1169.h.

#define SBC_UJA_MASK_2318_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2318_SHIFT)&SBC_UJA_MASK_2318_MASK)

Definition at line 538 of file UJA1169.h.

#define SBC_UJA_MASK_2318_MASK   (0xFCU)

Mask 0x2d - M23:M18 macros.

Definition at line 536 of file UJA1169.h.

#define SBC_UJA_MASK_2318_SHIFT   (2U)

Definition at line 537 of file UJA1169.h.

#define SBC_UJA_MASK_2824_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2824_SHIFT)&SBC_UJA_MASK_2824_MASK)

Definition at line 559 of file UJA1169.h.

#define SBC_UJA_MASK_2824_MASK   (0x1FU)

Mask 0x2e - M28:M24 macros.

Definition at line 557 of file UJA1169.h.

#define SBC_UJA_MASK_2824_SHIFT   (0U)

Definition at line 558 of file UJA1169.h.

#define SBC_UJA_MASK_X_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_X_SHIFT)&SBC_UJA_MASK_X_MASK)

Definition at line 566 of file UJA1169.h.

#define SBC_UJA_MASK_X_MASK   (0xFFU)

Mask X macros (0x2b-0x2e).

Definition at line 564 of file UJA1169.h.

#define SBC_UJA_MASK_X_SHIFT   (0U)

Definition at line 565 of file UJA1169.h.

#define SBC_UJA_MEMORY_X_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MEMORY_X_SHIFT)&SBC_UJA_MEMORY_X_MASK)

Definition at line 191 of file UJA1169.h.

#define SBC_UJA_MEMORY_X_MASK   (0xFFU)

Memory X macros.

Definition at line 189 of file UJA1169.h.

#define SBC_UJA_MEMORY_X_SHIFT   (0U)

Definition at line 190 of file UJA1169.h.

#define SBC_UJA_MODE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MODE_SHIFT)&SBC_UJA_MODE_MASK)

Definition at line 85 of file UJA1169.h.

#define SBC_UJA_MODE_MASK   (SBC_UJA_MODE_MC_MASK)

Mode control macros.

Definition at line 83 of file UJA1169.h.

#define SBC_UJA_MODE_MC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MODE_MC_SHIFT)&SBC_UJA_MODE_MC_MASK)

Definition at line 78 of file UJA1169.h.

#define SBC_UJA_MODE_MC_MASK   (0x07U)

Mode control, mode control macros.

Definition at line 76 of file UJA1169.h.

#define SBC_UJA_MODE_MC_SHIFT   (0U)

Definition at line 77 of file UJA1169.h.

#define SBC_UJA_MODE_SHIFT   (SBC_UJA_MODE_MC_SHIFT)

Definition at line 84 of file UJA1169.h.

#define SBC_UJA_MTPNV_CRC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_CRC_SHIFT)&SBC_UJA_MTPNV_CRC_MASK)

Definition at line 895 of file UJA1169.h.

#define SBC_UJA_MTPNV_CRC_MASK   (0xFFU)

MTPNV CRC control register macros.

Definition at line 893 of file UJA1169.h.

#define SBC_UJA_MTPNV_CRC_SHIFT   (0U)

Definition at line 894 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_ECCS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_ECCS_SHIFT)&SBC_UJA_MTPNV_STAT_ECCS_MASK)

Definition at line 813 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_ECCS_MASK   (0x02U)

MTPNV status register, error correction code status.

Definition at line 811 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_ECCS_SHIFT   (1U)

Definition at line 812 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_SHIFT)&SBC_UJA_MTPNV_STAT_MASK)

Definition at line 828 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_MASK
Value:
#define SBC_UJA_MTPNV_STAT_ECCS_MASK
MTPNV status register, error correction code status.
Definition: UJA1169.h:811
#define SBC_UJA_MTPNV_STAT_WRCNTS_MASK
MTPNV status register, write counter status macros.
Definition: UJA1169.h:804
#define SBC_UJA_MTPNV_STAT_NVMPS_MASK
MTPNV status register, non-volatile memory programming status.
Definition: UJA1169.h:818

MTPNV status register macros.

Definition at line 825 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_NVMPS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_NVMPS_SHIFT)&SBC_UJA_MTPNV_STAT_NVMPS_MASK)

Definition at line 820 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_NVMPS_MASK   (0x01U)

MTPNV status register, non-volatile memory programming status.

Definition at line 818 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_NVMPS_SHIFT   (0U)

Definition at line 819 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_SHIFT   (0U)

Definition at line 827 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_WRCNTS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_WRCNTS_SHIFT)&SBC_UJA_MTPNV_STAT_WRCNTS_MASK)

Definition at line 806 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_WRCNTS_MASK   (0xFCU)

MTPNV status register, write counter status macros.

Definition at line 804 of file UJA1169.h.

#define SBC_UJA_MTPNV_STAT_WRCNTS_SHIFT   (2U)

Definition at line 805 of file UJA1169.h.

#define SBC_UJA_REG_ADDR_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REG_ADDR_SHIFT)&SBC_UJA_REG_ADDR_MASK)

Definition at line 50 of file UJA1169.h.

#define SBC_UJA_REG_ADDR_MASK   (0xFEU)

Register address macros.

Definition at line 48 of file UJA1169.h.

#define SBC_UJA_REG_ADDR_SHIFT   (1U)

Definition at line 49 of file UJA1169.h.

#define SBC_UJA_REGULATOR_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_SHIFT)&SBC_UJA_REGULATOR_MASK)

Definition at line 278 of file UJA1169.h.

Regulator control register macros.

Definition at line 276 of file UJA1169.h.

#define SBC_UJA_REGULATOR_PDC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_PDC_SHIFT)&SBC_UJA_REGULATOR_PDC_MASK)

Definition at line 257 of file UJA1169.h.

#define SBC_UJA_REGULATOR_PDC_MASK   (0x40U)

Regulator control register, power distribution control macros.

Definition at line 255 of file UJA1169.h.

#define SBC_UJA_REGULATOR_PDC_SHIFT   (6U)

Definition at line 256 of file UJA1169.h.

#define SBC_UJA_REGULATOR_SHIFT   (0U)

Definition at line 277 of file UJA1169.h.

#define SBC_UJA_REGULATOR_V1RTC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_V1RTC_SHIFT)&SBC_UJA_REGULATOR_V1RTC_MASK)

Definition at line 271 of file UJA1169.h.

#define SBC_UJA_REGULATOR_V1RTC_MASK   (0x03U)

Regulator control register, set V1 reset threshold macros.

Definition at line 269 of file UJA1169.h.

#define SBC_UJA_REGULATOR_V1RTC_SHIFT   (0U)

Definition at line 270 of file UJA1169.h.

#define SBC_UJA_REGULATOR_V2C_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_V2C_SHIFT)&SBC_UJA_REGULATOR_V2C_MASK)

Definition at line 264 of file UJA1169.h.

#define SBC_UJA_REGULATOR_V2C_MASK   (0x0CU)

Regulator control register, V2/VEXT configuration macros.

Definition at line 262 of file UJA1169.h.

#define SBC_UJA_REGULATOR_V2C_SHIFT   (2U)

Definition at line 263 of file UJA1169.h.

#define SBC_UJA_SBC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SHIFT)&SBC_UJA_SBC_MASK)

Definition at line 888 of file UJA1169.h.

#define SBC_UJA_SBC_FNMC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_FNMC_SHIFT)&SBC_UJA_SBC_FNMC_MASK)

Definition at line 865 of file UJA1169.h.

#define SBC_UJA_SBC_FNMC_MASK   (0x08U)

SBC configuration control register, Forced Normal mode control macros.

Definition at line 863 of file UJA1169.h.

#define SBC_UJA_SBC_FNMC_SHIFT   (3U)

Definition at line 864 of file UJA1169.h.

#define SBC_UJA_SBC_MASK
Value:
#define SBC_UJA_SBC_SDMC_MASK
SBC configuration control register, Software Development mode control macros.
Definition: UJA1169.h:871
#define SBC_UJA_SBC_V1RTSUC_MASK
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up macr...
Definition: UJA1169.h:855
#define SBC_UJA_SBC_FNMC_MASK
SBC configuration control register, Forced Normal mode control macros.
Definition: UJA1169.h:863
#define SBC_UJA_SBC_SLPC_MASK
SBC configuration control register, Sleep control macros.
Definition: UJA1169.h:878

SBC configuration control register macros.

Definition at line 885 of file UJA1169.h.

#define SBC_UJA_SBC_SDMC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SDMC_SHIFT)&SBC_UJA_SBC_SDMC_MASK)

Definition at line 873 of file UJA1169.h.

#define SBC_UJA_SBC_SDMC_MASK   (0x04U)

SBC configuration control register, Software Development mode control macros.

Definition at line 871 of file UJA1169.h.

#define SBC_UJA_SBC_SDMC_SHIFT   (2U)

Definition at line 872 of file UJA1169.h.

#define SBC_UJA_SBC_SHIFT   (0U)

Definition at line 887 of file UJA1169.h.

#define SBC_UJA_SBC_SLPC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SLPC_SHIFT)&SBC_UJA_SBC_SLPC_MASK)

Definition at line 880 of file UJA1169.h.

#define SBC_UJA_SBC_SLPC_MASK   (0x01U)

SBC configuration control register, Sleep control macros.

Definition at line 878 of file UJA1169.h.

#define SBC_UJA_SBC_SLPC_SHIFT   (0U)

Definition at line 879 of file UJA1169.h.

#define SBC_UJA_SBC_V1RTSUC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_V1RTSUC_SHIFT)&SBC_UJA_SBC_V1RTSUC_MASK)

Definition at line 857 of file UJA1169.h.

#define SBC_UJA_SBC_V1RTSUC_MASK   (0x30U)

SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up macros.

Definition at line 855 of file UJA1169.h.

#define SBC_UJA_SBC_V1RTSUC_SHIFT   (4U)

Definition at line 856 of file UJA1169.h.

#define SBC_UJA_START_UP_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_SHIFT)&SBC_UJA_START_UP_MASK)

Definition at line 849 of file UJA1169.h.

#define SBC_UJA_START_UP_MASK   (SBC_UJA_START_UP_RLC_MASK | SBC_UJA_START_UP_V2SUC_MASK)

Start-up control register macros.

Definition at line 847 of file UJA1169.h.

#define SBC_UJA_START_UP_RLC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_RLC_SHIFT)&SBC_UJA_START_UP_RLC_MASK)

Definition at line 835 of file UJA1169.h.

#define SBC_UJA_START_UP_RLC_MASK   (0x30U)

Start-up control register, RSTN output reset pulse width macros.

Definition at line 833 of file UJA1169.h.

#define SBC_UJA_START_UP_RLC_SHIFT   (4U)

Definition at line 834 of file UJA1169.h.

#define SBC_UJA_START_UP_SHIFT   (3U)

Definition at line 848 of file UJA1169.h.

#define SBC_UJA_START_UP_V2SUC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_V2SUC_SHIFT)&SBC_UJA_START_UP_V2SUC_MASK)

Definition at line 842 of file UJA1169.h.

#define SBC_UJA_START_UP_V2SUC_MASK   (0x08U)

Start-up control register, V2/VEXT start-up control macros.

Definition at line 840 of file UJA1169.h.

#define SBC_UJA_START_UP_V2SUC_SHIFT   (3U)

Definition at line 841 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_SHIFT)&SBC_UJA_SUP_EVNT_STAT_MASK)

Definition at line 741 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_MASK
Value:
#define SBC_UJA_SUP_EVNT_STAT_V2O_MASK
Supply event status register, V2/VEXT overvoltage macros.
Definition: UJA1169.h:717
#define SBC_UJA_SUP_EVNT_STAT_V1U_MASK
Supply event status register, V1 undervoltage: macros.
Definition: UJA1169.h:731
#define SBC_UJA_SUP_EVNT_STAT_V2U_MASK
Supply event status register, V2/VEXT undervoltage macros.
Definition: UJA1169.h:724

Supply event status register macros.

Definition at line 738 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_SHIFT   (0U)

Definition at line 740 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V1U_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V1U_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V1U_MASK)

Definition at line 733 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V1U_MASK   (0x01U)

Supply event status register, V1 undervoltage: macros.

Definition at line 731 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V1U_SHIFT   (0U)

Definition at line 732 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V2O_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V2O_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V2O_MASK)

Definition at line 719 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V2O_MASK   (0x04U)

Supply event status register, V2/VEXT overvoltage macros.

Definition at line 717 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V2O_SHIFT   (2U)

Definition at line 718 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V2U_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V2U_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V2U_MASK)

Definition at line 726 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V2U_MASK   (0x02U)

Supply event status register, V2/VEXT undervoltage macros.

Definition at line 724 of file UJA1169.h.

#define SBC_UJA_SUP_EVNT_STAT_V2U_SHIFT   (1U)

Definition at line 725 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_SHIFT)&SBC_UJA_SUPPLY_EVNT_MASK)

Definition at line 330 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_MASK
Value:
#define SBC_UJA_SUPPLY_EVNT_V2UE_MASK
Supply event capture enable register, V2/VEXT undervoltage enable macros.
Definition: UJA1169.h:313
#define SBC_UJA_SUPPLY_EVNT_V2OE_MASK
Supply event capture enable register, V2/VEXT overvoltage enable macros.
Definition: UJA1169.h:305
#define SBC_UJA_SUPPLY_EVNT_V1UE_MASK
Supply event capture enable register, V1 undervoltage enable macros.
Definition: UJA1169.h:320

Supply event capture enable register macros.

Definition at line 327 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_SHIFT   (0U)

Definition at line 329 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V1UE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V1UE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V1UE_MASK)

Definition at line 322 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V1UE_MASK   (0x01U)

Supply event capture enable register, V1 undervoltage enable macros.

Definition at line 320 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V1UE_SHIFT   (0U)

Definition at line 321 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V2OE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V2OE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V2OE_MASK)

Definition at line 307 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V2OE_MASK   (0x04U)

Supply event capture enable register, V2/VEXT overvoltage enable macros.

Definition at line 305 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V2OE_SHIFT   (2U)

Definition at line 306 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V2UE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V2UE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V2UE_MASK)

Definition at line 315 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V2UE_MASK   (0x02U)

Supply event capture enable register, V2/VEXT undervoltage enable macros.

Definition at line 313 of file UJA1169.h.

#define SBC_UJA_SUPPLY_EVNT_V2UE_SHIFT   (1U)

Definition at line 314 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_SHIFT)&SBC_UJA_SUPPLY_STAT_MASK)

Definition at line 299 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_MASK   (SBC_UJA_SUPPLY_STAT_V2S_MASK | SBC_UJA_SUPPLY_STAT_V1S_MASK)

Supply voltage status register macros.

Definition at line 297 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_SHIFT   (0U)

Definition at line 298 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_V1S_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_V1S_SHIFT)&SBC_UJA_SUPPLY_STAT_V1S_MASK)

Definition at line 292 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_V1S_MASK   (0x01U)

Supply voltage status register, V1 status macros.

Definition at line 290 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_V1S_SHIFT   (0U)

Definition at line 291 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_V2S_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_V2S_SHIFT)&SBC_UJA_SUPPLY_STAT_V2S_MASK)

Definition at line 285 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_V2S_MASK   (0x06U)

Supply voltage status register, V2/VEXT status macros.

Definition at line 283 of file UJA1169.h.

#define SBC_UJA_SUPPLY_STAT_V2S_SHIFT   (1U)

Definition at line 284 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_SHIFT)&SBC_UJA_SYS_EVNT_MASK)

Definition at line 155 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_MASK   (SBC_UJA_SYS_EVNT_OTWE_MASK | SBC_UJA_SYS_EVNT_SPIFE_MASK)

System event capture enable.

Definition at line 153 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_OTWE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_OTWE_SHIFT)&SBC_UJA_SYS_EVNT_OTWE_MASK)

Definition at line 141 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_OTWE_MASK   (0x04U)

System event capture enable, overtemperature warning enable macros.

Definition at line 139 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_OTWE_SHIFT   (2U)

Definition at line 140 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_SHIFT   (1U)

Definition at line 154 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_SPIFE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_SPIFE_SHIFT)&SBC_UJA_SYS_EVNT_SPIFE_MASK)

Definition at line 148 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_SPIFE_MASK   (0x02U)

System event capture enable, SPI failure enable.

Definition at line 146 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_SPIFE_SHIFT   (1U)

Definition at line 147 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_SHIFT)&SBC_UJA_SYS_EVNT_STAT_MASK)

Definition at line 712 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_MASK
Value:
#define SBC_UJA_SYS_EVNT_STAT_WDF_MASK
System event status register, watchdog failure macros.
Definition: UJA1169.h:702
#define SBC_UJA_SYS_EVNT_STAT_OTW_MASK
System event status register, overtemperature warning macros.
Definition: UJA1169.h:688
#define SBC_UJA_SYS_EVNT_STAT_PO_MASK
System event status register, power-on macros.
Definition: UJA1169.h:681
#define SBC_UJA_SYS_EVNT_STAT_SPIF_MASK
System event status register, SPI failure macros.
Definition: UJA1169.h:695

System event status register macros.

Definition at line 709 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_OTW_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_OTW_SHIFT)&SBC_UJA_SYS_EVNT_STAT_OTW_MASK)

Definition at line 690 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_OTW_MASK   (0x04U)

System event status register, overtemperature warning macros.

Definition at line 688 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_OTW_SHIFT   (2U)

Definition at line 689 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_PO_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_PO_SHIFT)&SBC_UJA_SYS_EVNT_STAT_PO_MASK)

Definition at line 683 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_PO_MASK   (0x10U)

System event status register, power-on macros.

Definition at line 681 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_PO_SHIFT   (4U)

Definition at line 682 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_SHIFT   (0U)

Definition at line 711 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_SPIF_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_SPIF_SHIFT)&SBC_UJA_SYS_EVNT_STAT_SPIF_MASK)

Definition at line 697 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_SPIF_MASK   (0x02U)

System event status register, SPI failure macros.

Definition at line 695 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_SPIF_SHIFT   (1U)

Definition at line 696 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_WDF_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_WDF_SHIFT)&SBC_UJA_SYS_EVNT_STAT_WDF_MASK)

Definition at line 704 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_WDF_MASK   (0x01U)

System event status register, watchdog failure macros.

Definition at line 702 of file UJA1169.h.

#define SBC_UJA_SYS_EVNT_STAT_WDF_SHIFT   (0U)

Definition at line 703 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CBSE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CBSE_SHIFT)&SBC_UJA_TRANS_EVNT_CBSE_MASK)

Definition at line 432 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CBSE_MASK   (0x10U)

Transceiver event capture enable register, CAN-bus silence enable macros.

Definition at line 430 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CBSE_SHIFT   (4U)

Definition at line 431 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CFE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CFE_SHIFT)&SBC_UJA_TRANS_EVNT_CFE_MASK)

Definition at line 439 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CFE_MASK   (0x02U)

Transceiver event capture enable register, CAN failure enable macros.

Definition at line 437 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CFE_SHIFT   (1U)

Definition at line 438 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CWE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CWE_SHIFT)&SBC_UJA_TRANS_EVNT_CWE_MASK)

Definition at line 446 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CWE_MASK   (0x01U)

Transceiver event capture enable register, CAN wake-up enable.

Definition at line 444 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_CWE_SHIFT   (0U)

Definition at line 445 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_SHIFT)&SBC_UJA_TRANS_EVNT_MASK)

Definition at line 454 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_MASK
Value:
#define SBC_UJA_TRANS_EVNT_CBSE_MASK
Transceiver event capture enable register, CAN-bus silence enable macros.
Definition: UJA1169.h:430
#define SBC_UJA_TRANS_EVNT_CWE_MASK
Transceiver event capture enable register, CAN wake-up enable.
Definition: UJA1169.h:444
#define SBC_UJA_TRANS_EVNT_CFE_MASK
Transceiver event capture enable register, CAN failure enable macros.
Definition: UJA1169.h:437

Transceiver event capture enable register macros.

Definition at line 451 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_SHIFT   (0U)

Definition at line 453 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CBS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CBS_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CBS_MASK)

Definition at line 756 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CBS_MASK   (0x10U)

Transceiver event status register, CAN-bus status macros.

Definition at line 754 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CBS_SHIFT   (4U)

Definition at line 755 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CF_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CF_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CF_MASK)

Definition at line 763 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CF_MASK   (0x02U)

Transceiver event status register, CAN failure.

Definition at line 761 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CF_SHIFT   (1U)

Definition at line 762 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CW_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CW_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CW_MASK)

Definition at line 770 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CW_MASK   (0x01U)

Transceiver event status register, CAN wake-up.

Definition at line 768 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_CW_SHIFT   (0U)

Definition at line 769 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_MASK)

Definition at line 778 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_MASK
Value:
#define SBC_UJA_TRANS_EVNT_STAT_CBS_MASK
Transceiver event status register, CAN-bus status macros.
Definition: UJA1169.h:754
#define SBC_UJA_TRANS_EVNT_STAT_CW_MASK
Transceiver event status register, CAN wake-up.
Definition: UJA1169.h:768
#define SBC_UJA_TRANS_EVNT_STAT_CF_MASK
Transceiver event status register, CAN failure.
Definition: UJA1169.h:761
#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK
Transceiver event status register, partial networking frame detection error macros.
Definition: UJA1169.h:747

Transceiver event status register macros.

Definition at line 775 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_PNFDE_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK)

Definition at line 749 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK   (0x20U)

Transceiver event status register, partial networking frame detection error macros.

Definition at line 747 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_SHIFT   (5U)

Definition at line 748 of file UJA1169.h.

#define SBC_UJA_TRANS_EVNT_STAT_SHIFT   (0U)

Definition at line 777 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CBSS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CBSS_SHIFT)&SBC_UJA_TRANS_STAT_CBSS_MASK)

Definition at line 401 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CBSS_MASK   (0x08U)

Transceiver status register, CAN-bus silence status macros.

Definition at line 399 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CBSS_SHIFT   (3U)

Definition at line 400 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CFS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CFS_SHIFT)&SBC_UJA_TRANS_STAT_CFS_MASK)

Definition at line 415 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CFS_MASK   (0x01U)

Transceiver status register, CAN failure status macros.

Definition at line 413 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CFS_SHIFT   (0U)

Definition at line 414 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_COSCS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_COSCS_SHIFT)&SBC_UJA_TRANS_STAT_COSCS_MASK)

Definition at line 394 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_COSCS_MASK   (0x10U)

Transceiver status register, CAN oscillator status macros.

Definition at line 392 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_COSCS_SHIFT   (4U)

Definition at line 393 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CPNERR_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CPNERR_SHIFT)&SBC_UJA_TRANS_STAT_CPNERR_MASK)

Definition at line 380 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CPNERR_MASK   (0x40U)

Transceiver status register, CAN partial networking error macros.

Definition at line 378 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CPNERR_SHIFT   (6U)

Definition at line 379 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CPNS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CPNS_SHIFT)&SBC_UJA_TRANS_STAT_CPNS_MASK)

Definition at line 387 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CPNS_MASK   (0x20U)

Transceiver status register, CAN partial networking status macros.

Definition at line 385 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CPNS_SHIFT   (5U)

Definition at line 386 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CTS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CTS_SHIFT)&SBC_UJA_TRANS_STAT_CTS_MASK)

Definition at line 373 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CTS_MASK   (0x80U)

Transceiver status register, CAN transceiver status macros.

Definition at line 371 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_CTS_SHIFT   (7U)

Definition at line 372 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_SHIFT)&SBC_UJA_TRANS_STAT_MASK)

Definition at line 425 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_MASK
Value:
#define SBC_UJA_TRANS_STAT_CPNS_MASK
Transceiver status register, CAN partial networking status macros.
Definition: UJA1169.h:385
#define SBC_UJA_TRANS_STAT_COSCS_MASK
Transceiver status register, CAN oscillator status macros.
Definition: UJA1169.h:392
#define SBC_UJA_TRANS_STAT_VCS_MASK
Transceiver status register, VCAN status macros.
Definition: UJA1169.h:406
#define SBC_UJA_TRANS_STAT_CPNERR_MASK
Transceiver status register, CAN partial networking error macros.
Definition: UJA1169.h:378
#define SBC_UJA_TRANS_STAT_CTS_MASK
Transceiver status register, CAN transceiver status macros.
Definition: UJA1169.h:371
#define SBC_UJA_TRANS_STAT_CBSS_MASK
Transceiver status register, CAN-bus silence status macros.
Definition: UJA1169.h:399
#define SBC_UJA_TRANS_STAT_CFS_MASK
Transceiver status register, CAN failure status macros.
Definition: UJA1169.h:413

Transceiver status register macros.

Definition at line 420 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_SHIFT   (0U)

Definition at line 424 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_VCS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_VCS_SHIFT)&SBC_UJA_TRANS_STAT_VCS_MASK)

Definition at line 408 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_VCS_MASK   (0x02U)

Transceiver status register, VCAN status macros.

Definition at line 406 of file UJA1169.h.

#define SBC_UJA_TRANS_STAT_VCS_SHIFT   (1U)

Definition at line 407 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_SHIFT)&SBC_UJA_WAKE_EN_MASK)

Definition at line 640 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_MASK   (SBC_UJA_WAKE_EN_WPRE_MASK | SBC_UJA_WAKE_EN_WPFE_MASK)

WAKE pin event capture enable register macros.

Definition at line 638 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_SHIFT   (0U)

Definition at line 639 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_WPFE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_WPFE_SHIFT)&SBC_UJA_WAKE_EN_WPFE_MASK)

Definition at line 633 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_WPFE_MASK   (0x01U)

WAKE pin event capture enable register, WAKE pin falling-edge enable macros.

Definition at line 631 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_WPFE_SHIFT   (0U)

Definition at line 632 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_WPRE_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_WPRE_SHIFT)&SBC_UJA_WAKE_EN_WPRE_MASK)

Definition at line 625 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_WPRE_MASK   (0x02U)

WAKE pin event capture enable register, WAKE pin rising-edge enable macros.

Definition at line 623 of file UJA1169.h.

#define SBC_UJA_WAKE_EN_WPRE_SHIFT   (1U)

Definition at line 624 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_MASK)

Definition at line 799 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_MASK   (SBC_UJA_WAKE_EVNT_STAT_WPR_MASK | SBC_UJA_WAKE_EVNT_STAT_WPF_MASK)

WAKE pin event status register macros.

Definition at line 797 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_SHIFT   (0U)

Definition at line 798 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_WPF_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_WPF_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_WPF_MASK)

Definition at line 792 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_WPF_MASK   (0x01U)

WAKE pin event status register, WAKE pin falling edge macros.

Definition at line 790 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_WPF_SHIFT   (0U)

Definition at line 791 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_WPR_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_WPR_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_WPR_MASK)

Definition at line 785 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_WPR_MASK   (0x02U)

WAKE pin event status register, WAKE pin rising edge macros.

Definition at line 783 of file UJA1169.h.

#define SBC_UJA_WAKE_EVNT_STAT_WPR_SHIFT   (1U)

Definition at line 784 of file UJA1169.h.

#define SBC_UJA_WAKE_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_STAT_SHIFT)&SBC_UJA_WAKE_STAT_MASK)

Definition at line 617 of file UJA1169.h.

#define SBC_UJA_WAKE_STAT_MASK   (SBC_UJA_WAKE_STAT_WPVS_MASK)

WAKE pin status register.

Definition at line 615 of file UJA1169.h.

#define SBC_UJA_WAKE_STAT_SHIFT   (SBC_UJA_WAKE_STAT_WPVS_SHIFT)

Definition at line 616 of file UJA1169.h.

#define SBC_UJA_WAKE_STAT_WPVS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_STAT_WPVS_SHIFT)&SBC_UJA_WAKE_STAT_WPVS_MASK)

Definition at line 610 of file UJA1169.h.

#define SBC_UJA_WAKE_STAT_WPVS_MASK   (0x02FU)

WAKE pin status register, WAKE pin status macros.

Definition at line 608 of file UJA1169.h.

#define SBC_UJA_WAKE_STAT_WPVS_SHIFT   (1U)

Definition at line 609 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_SHIFT)&SBC_UJA_WTDOG_CTR_MASK)

Definition at line 71 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_MASK   (SBC_UJA_WTDOG_CTR_WMC_MASK | SBC_UJA_WTDOG_CTR_NWP_MASK)

Watchdog control macros.

Definition at line 69 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_NWP_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_NWP_SHIFT)&SBC_UJA_WTDOG_CTR_NWP_MASK)

Definition at line 64 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_NWP_MASK   (0x0FU)

Watchdog mode control, nominal watchdog period macros.

Definition at line 62 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_NWP_SHIFT   (0U)

Definition at line 63 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_SHIFT   (0U)

Definition at line 70 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_WMC_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_WMC_SHIFT)&SBC_UJA_WTDOG_CTR_WMC_MASK)

Definition at line 57 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_WMC_MASK   (0xE0U)

Watchdog mode control, watchdog mode control macros.

Definition at line 55 of file UJA1169.h.

#define SBC_UJA_WTDOG_CTR_WMC_SHIFT   (5U)

Definition at line 56 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_SHIFT)&SBC_UJA_WTDOG_STAT_MASK)

Definition at line 184 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_FNMS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_FNMS_SHIFT)&SBC_UJA_WTDOG_STAT_FNMS_MASK)

Definition at line 162 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_FNMS_MASK   (0x08U)

Watchdog status register, forced Normal mode status macros.

Definition at line 160 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_FNMS_SHIFT   (3U)

Definition at line 161 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_MASK
Value:
#define SBC_UJA_WTDOG_STAT_FNMS_MASK
Watchdog status register, forced Normal mode status macros.
Definition: UJA1169.h:160
#define SBC_UJA_WTDOG_STAT_SDMS_MASK
Watchdog status register, Software Development mode status macros.
Definition: UJA1169.h:167
#define SBC_UJA_WTDOG_STAT_WDS_MASK
Watchdog status register, watchdog status macros.
Definition: UJA1169.h:174

Watchdog status macros.

Definition at line 181 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_SDMS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_SDMS_SHIFT)&SBC_UJA_WTDOG_STAT_SDMS_MASK)

Definition at line 169 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_SDMS_MASK   (0x04U)

Watchdog status register, Software Development mode status macros.

Definition at line 167 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_SDMS_SHIFT   (2U)

Definition at line 168 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_SHIFT   (0U)

Definition at line 183 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_WDS_F (   x)    ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_WDS_SHIFT)&SBC_UJA_WTDOG_STAT_WDS_MASK)

Definition at line 176 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_WDS_MASK   (0x03U)

Watchdog status register, watchdog status macros.

Definition at line 174 of file UJA1169.h.

#define SBC_UJA_WTDOG_STAT_WDS_SHIFT   (0U)

Definition at line 175 of file UJA1169.h.