20 #include "flexio_hw_access.h"
100 #define DIVIDER_MIN_VALUE 1U
101 #define DIVIDER_MAX_VALUE 0xFFU
105 #define TX_SHIFTER(x) (x)
106 #define RX_SHIFTER(x) (uint8_t)((x) + 1U)
107 #define SCK_TIMER(x) (x)
108 #define WS_TIMER(x) (uint8_t)((x) + 1U)
120 static uint8_t FLEXIO_I2S_DRV_ComputeByteWidth(uint8_t bitsWidth)
128 else if (bitsWidth <= 16U)
146 static void FLEXIO_I2S_DRV_MasterComputeBaudRateDivider(uint32_t baudRate,
153 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 1U;
155 if (tmpDiv < DIVIDER_MIN_VALUE)
157 tmpDiv = DIVIDER_MIN_VALUE;
159 if (tmpDiv > DIVIDER_MAX_VALUE)
161 tmpDiv = DIVIDER_MAX_VALUE;
164 *divider = (uint16_t)tmpDiv;
181 uint8_t resourceIndex;
184 resourceIndex = master->flexioCommon.resourceIndex;
187 FLEXIO_I2S_DRV_MasterComputeBaudRateDivider(userConfigPtr->
baudRate, ÷r, inputClock);
191 FLEXIO_SetShifterConfig(baseAddr,
192 TX_SHIFTER(resourceIndex),
193 FLEXIO_SHIFTER_START_BIT_DISABLED_SH,
194 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
195 FLEXIO_SHIFTER_SOURCE_PIN);
196 FLEXIO_SetShifterControl(baseAddr,
197 TX_SHIFTER(resourceIndex),
198 FLEXIO_SHIFTER_MODE_DISABLED,
199 userConfigPtr->
txPin,
200 FLEXIO_PIN_POLARITY_HIGH,
201 FLEXIO_PIN_CONFIG_DISABLED,
202 SCK_TIMER(resourceIndex),
203 FLEXIO_TIMER_POLARITY_POSEDGE);
206 FLEXIO_SetShifterConfig(baseAddr,
207 RX_SHIFTER(resourceIndex),
208 FLEXIO_SHIFTER_START_BIT_DISABLED,
209 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
210 FLEXIO_SHIFTER_SOURCE_PIN);
211 FLEXIO_SetShifterControl(baseAddr,
212 RX_SHIFTER(resourceIndex),
213 FLEXIO_SHIFTER_MODE_DISABLED,
214 userConfigPtr->
rxPin,
215 FLEXIO_PIN_POLARITY_HIGH,
216 FLEXIO_PIN_CONFIG_DISABLED,
217 SCK_TIMER(resourceIndex),
218 FLEXIO_TIMER_POLARITY_NEGEDGE);
221 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)((((bits << 1U) - 1U) << 8U) + divider));
222 FLEXIO_SetTimerConfig(baseAddr,
223 SCK_TIMER(resourceIndex),
224 FLEXIO_TIMER_START_BIT_ENABLED,
225 FLEXIO_TIMER_STOP_BIT_DISABLED,
226 FLEXIO_TIMER_ENABLE_TRG_HIGH,
227 FLEXIO_TIMER_DISABLE_NEVER,
228 FLEXIO_TIMER_RESET_NEVER,
229 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
230 FLEXIO_TIMER_INITOUT_ONE);
231 FLEXIO_SetTimerControl(baseAddr,
232 SCK_TIMER(resourceIndex),
233 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
234 FLEXIO_TRIGGER_POLARITY_LOW,
235 FLEXIO_TRIGGER_SOURCE_INTERNAL,
237 FLEXIO_PIN_POLARITY_LOW,
238 FLEXIO_PIN_CONFIG_OUTPUT,
239 FLEXIO_TIMER_MODE_DISABLED);
243 FLEXIO_SetTimerCompare(baseAddr, WS_TIMER(resourceIndex), (uint16_t)((bits * ((divider + 1U) * 2U)) - 1U));
244 FLEXIO_SetTimerConfig(baseAddr,
245 WS_TIMER(resourceIndex),
246 FLEXIO_TIMER_START_BIT_DISABLED,
247 FLEXIO_TIMER_STOP_BIT_DISABLED,
248 FLEXIO_TIMER_ENABLE_TIM_ENABLE,
249 FLEXIO_TIMER_DISABLE_NEVER,
250 FLEXIO_TIMER_RESET_NEVER,
251 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
252 FLEXIO_TIMER_INITOUT_ONE);
253 FLEXIO_SetTimerControl(baseAddr,
254 WS_TIMER(resourceIndex),
256 FLEXIO_TRIGGER_POLARITY_HIGH,
257 FLEXIO_TRIGGER_SOURCE_EXTERNAL,
258 userConfigPtr->
wsPin,
259 FLEXIO_PIN_POLARITY_LOW,
260 FLEXIO_PIN_CONFIG_OUTPUT,
261 FLEXIO_TIMER_MODE_DISABLED);
276 uint8_t resourceIndex;
279 resourceIndex = slave->flexioCommon.resourceIndex;
284 FLEXIO_SetShifterConfig(baseAddr,
285 TX_SHIFTER(resourceIndex),
286 FLEXIO_SHIFTER_START_BIT_DISABLED,
287 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
288 FLEXIO_SHIFTER_SOURCE_PIN);
289 FLEXIO_SetShifterControl(baseAddr,
290 TX_SHIFTER(resourceIndex),
291 FLEXIO_SHIFTER_MODE_DISABLED,
292 userConfigPtr->
txPin,
293 FLEXIO_PIN_POLARITY_HIGH,
294 FLEXIO_PIN_CONFIG_DISABLED,
295 WS_TIMER(resourceIndex),
296 FLEXIO_TIMER_POLARITY_POSEDGE);
299 FLEXIO_SetShifterConfig(baseAddr,
300 RX_SHIFTER(resourceIndex),
301 FLEXIO_SHIFTER_START_BIT_DISABLED,
302 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
303 FLEXIO_SHIFTER_SOURCE_PIN);
304 FLEXIO_SetShifterControl(baseAddr,
305 RX_SHIFTER(resourceIndex),
306 FLEXIO_SHIFTER_MODE_DISABLED,
307 userConfigPtr->
rxPin,
308 FLEXIO_PIN_POLARITY_HIGH,
309 FLEXIO_PIN_CONFIG_DISABLED,
310 WS_TIMER(resourceIndex),
311 FLEXIO_TIMER_POLARITY_NEGEDGE);
314 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)((bits << 2U) - 3U));
315 FLEXIO_SetTimerConfig(baseAddr,
316 SCK_TIMER(resourceIndex),
317 FLEXIO_TIMER_START_BIT_DISABLED,
318 FLEXIO_TIMER_STOP_BIT_DISABLED,
319 FLEXIO_TIMER_ENABLE_PIN_POSEDGE,
320 FLEXIO_TIMER_DISABLE_TIM_CMP,
321 FLEXIO_TIMER_RESET_NEVER,
322 FLEXIO_TIMER_DECREMENT_TRG_SHIFT_TRG,
323 FLEXIO_TIMER_INITOUT_ONE);
324 FLEXIO_SetTimerControl(baseAddr,
325 SCK_TIMER(resourceIndex),
326 (uint8_t)(userConfigPtr->
sckPin << 1U),
327 FLEXIO_TRIGGER_POLARITY_LOW,
328 FLEXIO_TRIGGER_SOURCE_INTERNAL,
329 userConfigPtr->
wsPin,
330 FLEXIO_PIN_POLARITY_LOW,
331 FLEXIO_PIN_CONFIG_DISABLED,
332 FLEXIO_TIMER_MODE_DISABLED);
335 FLEXIO_SetTimerCompare(baseAddr, WS_TIMER(resourceIndex), (uint16_t)((bits << 1U) - 1U));
336 FLEXIO_SetTimerConfig(baseAddr,
337 WS_TIMER(resourceIndex),
338 FLEXIO_TIMER_START_BIT_DISABLED,
339 FLEXIO_TIMER_STOP_BIT_DISABLED,
340 FLEXIO_TIMER_ENABLE_PIN_POSEDGE_TRG_HIGH,
341 FLEXIO_TIMER_DISABLE_TIM_CMP_TRG_LOW,
342 FLEXIO_TIMER_RESET_NEVER,
343 FLEXIO_TIMER_DECREMENT_PIN_SHIFT_PIN,
344 FLEXIO_TIMER_INITOUT_ONE);
345 FLEXIO_SetTimerControl(baseAddr,
346 WS_TIMER(resourceIndex),
347 (uint8_t)((SCK_TIMER(resourceIndex) << 2U) + 3U),
348 FLEXIO_TRIGGER_POLARITY_HIGH,
349 FLEXIO_TRIGGER_SOURCE_INTERNAL,
351 FLEXIO_PIN_POLARITY_LOW,
352 FLEXIO_PIN_CONFIG_DISABLED,
353 FLEXIO_TIMER_MODE_DISABLED);
366 uint8_t resourceIndex;
369 resourceIndex = master->flexioCommon.resourceIndex;
372 switch (master->driverType)
376 FLEXIO_SetShifterInterrupt(baseAddr,
377 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
379 FLEXIO_SetShifterErrorInterrupt(baseAddr,
380 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
391 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
false);
398 master->driverIdle =
true;
399 master->txData = NULL;
400 master->rxData = NULL;
401 master->txRemainingBytes = 0U;
402 master->rxRemainingBytes = 0U;
405 if (master->blocking ==
true)
421 uint8_t resourceIndex;
423 resourceIndex = master->flexioCommon.resourceIndex;
427 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_TRANSMIT);
428 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_RECEIVE);
431 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_8BIT_BAUD);
435 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_16BIT);
437 FLEXIO_SetTimerMode(baseAddr, WS_TIMER(resourceIndex), FLEXIO_TIMER_MODE_16BIT);
450 uint8_t resourceIndex;
452 resourceIndex = master->flexioCommon.resourceIndex;
456 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
457 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
458 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
459 FLEXIO_SetTimerMode(baseAddr, WS_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
461 FLEXIO_SetShifterPinConfig(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_PIN_CONFIG_DISABLED);
464 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
465 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
467 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
470 FLEXIO_I2S_DRV_MasterEndTransfer(master);
484 switch (master->driverType)
488 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
495 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
503 master->blocking =
false;
508 FLEXIO_I2S_DRV_MasterStopTransfer(master);
511 return master->status;
525 uint8_t resourceIndex;
528 resourceIndex = master->flexioCommon.resourceIndex;
531 data = FLEXIO_ReadShifterBuffer(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
533 if (master->rxRemainingBytes > 0U)
535 if (master->rxData != NULL)
537 switch (master->byteWidth)
540 *(uint8_t *)master->rxData = (uint8_t)data;
543 *(uint16_t *)master->rxData = (uint16_t)data;
546 *(uint32_t *)master->rxData = (uint32_t)data;
550 master->rxData = &master->rxData[master->byteWidth];
553 master->rxRemainingBytes -= (uint32_t)(master->byteWidth);
572 uint8_t resourceIndex;
575 resourceIndex = master->flexioCommon.resourceIndex;
577 if (master->txRemainingBytes == 0U)
584 switch (master->byteWidth)
587 data = (uint32_t)(*(
const uint8_t *)master->txData);
590 data = (uint32_t)(*(
const uint16_t *)master->txData);
593 data = (uint32_t)(*(
const uint32_t *)master->txData);
596 master->txData = &master->txData[master->byteWidth];
597 master->txRemainingBytes -= (uint32_t)(master->byteWidth);
601 data <<= 32U - (uint32_t)(master->bitsWidth);
602 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), data, FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
614 static void FLEXIO_I2S_DRV_MasterCheckStatus(
void *stateStruct)
617 uint8_t resourceIndex;
624 resourceIndex = master->flexioCommon.resourceIndex;
627 if (master->txData != NULL)
629 if(FLEXIO_GetShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex)))
632 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
636 if (master->rxData != NULL)
638 if (FLEXIO_GetShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex)))
641 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
646 if (FLEXIO_GetShifterStatus(baseAddr, RX_SHIFTER(resourceIndex)))
648 FLEXIO_I2S_DRV_ReadData(master);
649 if ((master->rxData != NULL) && (master->rxRemainingBytes == 0U))
652 if (master->callback != NULL)
659 if (master->txData != NULL)
661 if (FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)))
663 FLEXIO_I2S_DRV_WriteData(master);
664 if (master->txRemainingBytes == 0U)
667 if (master->callback != NULL)
671 if (master->txRemainingBytes == 0U)
677 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
678 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
680 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
682 master->txData = NULL;
689 if (master->rxRemainingBytes == 0U)
697 FLEXIO_I2S_DRV_MasterStopTransfer(master);
699 if (master->callback != NULL)
713 static void FLEXIO_I2S_DRV_MasterEndDmaTxTransfer(
void *stateStruct,
edma_chn_status_t status)
724 if (master->callback != NULL)
728 if (master->txRemainingBytes == 0U)
731 master->txData = NULL;
737 dmaChn = master->txDMAChannel;
741 master->txRemainingBytes = 0U;
754 static void FLEXIO_I2S_DRV_MasterEndDmaRxTransfer(
void *stateStruct,
edma_chn_status_t status)
766 if ((master->rxData != NULL) && (master->callback != NULL))
770 if (master->rxRemainingBytes == 0U)
775 FLEXIO_I2S_DRV_MasterStopTransfer(master);
777 if (master->callback != NULL)
786 dmaChn = master->rxDMAChannel;
787 if (master->rxData != NULL)
789 addr = (uint32_t)(master->rxData);
794 addr = (uint32_t)(&(master->dummyDmaData));
799 master->rxRemainingBytes = 0U;
819 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
820 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter])) + (
sizeof(uint32_t) - master->byteWidth);
838 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
839 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter]));
852 uint8_t resourceIndex;
855 uint8_t requestMask = 0U;
862 resourceIndex = master->flexioCommon.resourceIndex;
865 if (master->txData != NULL)
870 (uint32_t)(master->txData),
871 FLEXIO_I2S_DRV_MasterComputeTxRegAddr(master),
872 dmaTransferSize[master->byteWidth - 1U],
874 master->txRemainingBytes / master->byteWidth,
877 master->txRemainingBytes = 0U;
885 requestMask = (uint8_t)(1U << TX_SHIFTER(resourceIndex));
888 if (master->rxData != NULL)
890 addr = (uint32_t)(master->rxData);
895 addr = (uint32_t)(&(master->dummyDmaData));
900 FLEXIO_I2S_DRV_MasterComputeRxRegAddr(master),
902 dmaTransferSize[master->byteWidth - 1U],
904 master->rxRemainingBytes / master->byteWidth,
906 if (master->rxData == NULL)
912 master->rxRemainingBytes = 0U;
920 requestMask |= (uint8_t)(1U << RX_SHIFTER(resourceIndex));
923 FLEXIO_SetShifterDMARequest(baseAddr, requestMask,
true);
961 master->flexioCommon.resourceCount = 2U;
976 master->driverType = userConfigPtr->
driverType;
977 master->bitsWidth = userConfigPtr->
bitsWidth;
978 master->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(userConfigPtr->
bitsWidth);
979 master->driverIdle =
true;
980 master->callback = userConfigPtr->
callback;
982 master->blocking =
false;
983 master->txData = NULL;
984 master->txRemainingBytes = 0U;
985 master->rxData = NULL;
986 master->rxRemainingBytes = 0U;
987 master->master =
true;
991 FLEXIO_I2S_DRV_MasterConfigure(master, userConfigPtr, inputClock);
994 switch (master->driverType)
997 master->flexioCommon.isr = FLEXIO_I2S_DRV_MasterCheckStatus;
1007 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(master->flexioCommon.resourceIndex)];
1008 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(master->flexioCommon.resourceIndex)];
1059 uint32_t inputClock;
1061 uint8_t resourceIndex;
1067 (bitsWidth != 8U) && (bitsWidth != 16U) && (bitsWidth != 32U)
1070 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1071 resourceIndex = master->flexioCommon.resourceIndex;
1081 FLEXIO_I2S_DRV_MasterComputeBaudRateDivider(baudRate, ÷r, inputClock);
1084 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)(((((uint16_t)bitsWidth << 1U) - 1U) << 8U) + divider));
1086 FLEXIO_SetTimerCompare(baseAddr, WS_TIMER(resourceIndex), (uint16_t)((bitsWidth * ((divider + 1U) * 2U)) - 1U));
1088 master->bitsWidth = bitsWidth;
1089 master->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(bitsWidth);
1106 uint32_t inputClock;
1110 uint8_t resourceIndex;
1115 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1116 resourceIndex = master->flexioCommon.resourceIndex;
1124 timerCmp = FLEXIO_GetTimerCompare(baseAddr, SCK_TIMER(resourceIndex));
1125 divider = (uint16_t)(timerCmp & 0x00FFU);
1128 *baudRate = (inputClock + (uint32_t)divider + 1U) / (2U * ((uint32_t)divider + 1U));
1144 const uint8_t * txBuff,
1148 uint8_t resourceIndex;
1153 DEV_ASSERT((txSize % (uint32_t)(master->byteWidth)) == 0U);
1155 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1156 resourceIndex = master->flexioCommon.resourceIndex;
1161 master->txData = txBuff;
1162 master->txRemainingBytes = txSize;
1164 master->rxRemainingBytes = txSize;
1165 master->rxData = NULL;
1167 master->driverIdle =
false;
1170 FLEXIO_SetShifterPinConfig(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_PIN_CONFIG_OUTPUT);
1172 FLEXIO_I2S_DRV_MasterEnableTransfer(master);
1174 switch (master->driverType)
1178 FLEXIO_SetShifterInterrupt(baseAddr,
1179 (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
1181 FLEXIO_SetShifterErrorInterrupt(baseAddr,
1182 (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
1187 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1190 FLEXIO_I2S_DRV_MasterStartDmaTransfer(master);
1209 const uint8_t * txBuff,
1218 master->blocking =
true;
1225 master->blocking =
false;
1230 return FLEXIO_I2S_DRV_MasterWaitTransferEnd(master, timeout);
1246 uint8_t resourceIndex;
1251 DEV_ASSERT((rxSize % (uint32_t)(master->byteWidth)) == 0U);
1253 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1254 resourceIndex = master->flexioCommon.resourceIndex;
1259 master->rxData = rxBuff;
1260 master->rxRemainingBytes = rxSize;
1261 master->txData = NULL;
1262 master->txRemainingBytes = 0U;
1264 master->driverIdle =
false;
1267 FLEXIO_I2S_DRV_MasterEnableTransfer(master);
1270 switch (master->driverType)
1274 FLEXIO_SetShifterInterrupt(baseAddr,
1275 (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
1277 FLEXIO_SetShifterErrorInterrupt(baseAddr,
1278 (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
1283 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1286 FLEXIO_I2S_DRV_MasterStartDmaTransfer(master);
1295 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), 0x0, FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
1318 master->blocking =
true;
1325 master->blocking =
false;
1330 return FLEXIO_I2S_DRV_MasterWaitTransferEnd(master, timeout);
1346 if (master->driverIdle)
1352 FLEXIO_I2S_DRV_MasterStopTransfer(master);
1367 uint32_t remainingBytes;
1373 remainingBytes = master->rxRemainingBytes;
1375 if (!master->driverIdle)
1377 switch(master->driverType)
1381 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1397 if (bytesRemaining != NULL)
1399 *bytesRemaining = remainingBytes;
1402 if (!master->driverIdle)
1408 return master->status;
1428 master->rxData = rxBuff;
1429 master->rxRemainingBytes = rxSize;
1443 const uint8_t * txBuff,
1450 master->txData = txBuff;
1451 master->txRemainingBytes = txSize;
1453 master->rxRemainingBytes += txSize;
1481 slave->flexioCommon.resourceCount = 2U;
1495 slave->driverType = userConfigPtr->
driverType;
1496 slave->bitsWidth = userConfigPtr->
bitsWidth;
1497 slave->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(userConfigPtr->
bitsWidth);
1498 slave->driverIdle =
true;
1499 slave->callback = userConfigPtr->
callback;
1501 slave->blocking =
false;
1502 slave->txData = NULL;
1503 slave->txRemainingBytes = 0U;
1504 slave->rxData = NULL;
1505 slave->rxRemainingBytes = 0U;
1506 slave->master =
false;
1510 FLEXIO_I2S_DRV_SlaveConfigure(slave, userConfigPtr);
1513 switch (slave->driverType)
1516 slave->flexioCommon.isr = FLEXIO_I2S_DRV_MasterCheckStatus;
1526 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(slave->flexioCommon.resourceIndex)];
1527 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(slave->flexioCommon.resourceIndex)];
1552 uint8_t resourceIndex;
1558 (bitsWidth != 8U) && (bitsWidth != 16U) && (bitsWidth != 32U)
1562 resourceIndex = slave->flexioCommon.resourceIndex;
1567 slave->bitsWidth = bitsWidth;
1568 slave->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(bitsWidth);
1571 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)(((uint16_t)bitsWidth << 2U) - 3U));
1573 FLEXIO_SetTimerCompare(baseAddr, WS_TIMER(resourceIndex), (uint16_t)(((uint16_t)bitsWidth << 1U) - 1U));
void EDMA_DRV_SetMajorLoopIterationCount(uint8_t virtualChannel, uint32_t majorLoopCount)
Configures the number of major loop iterations.
status_t FLEXIO_I2S_DRV_MasterReceiveDataBlocking(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking receive transaction on the I2S bus.
uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t virtualChannel)
Returns the remaining major loop iteration count.
status_t FLEXIO_I2S_DRV_MasterReceiveData(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking receive transaction on the I2S bus.
status_t EDMA_DRV_InstallCallback(uint8_t virtualChannel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t virtualChannel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t FLEXIO_I2S_DRV_MasterSetTxBuffer(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
#define FLEXIO_INSTANCE_COUNT
status_t FLEXIO_I2S_DRV_MasterSendData(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking send transaction on the I2S bus.
Master internal context structure.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
Slave configuration structure.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
void EDMA_DRV_SetDestOffset(uint8_t virtualChannel, int16_t offset)
Configures the destination address signed offset for the eDMA channel.
status_t FLEXIO_I2S_DRV_MasterDeinit(flexio_i2s_master_state_t *master)
De-initialize the FLEXIO_I2S master mode driver.
status_t EDMA_DRV_StopChannel(uint8_t virtualChannel)
Stops the eDMA channel.
status_t FLEXIO_I2S_DRV_SlaveInit(uint32_t instance, const flexio_i2s_slave_user_config_t *userConfigPtr, flexio_i2s_slave_state_t *slave)
Initialize the FLEXIO_I2S slave mode driver.
edma_chn_status_t
Channel status for eDMA channel.
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
volatile uint32_t SHIFTBUFBIS[4u]
void EDMA_DRV_SetDestAddr(uint8_t virtualChannel, uint32_t address)
Configures the destination address for the eDMA channel.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
const clock_names_t g_flexioClock[(1u)]
status_t FLEXIO_I2S_DRV_MasterSendDataBlocking(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking send transaction on the I2S bus.
status_t FLEXIO_I2S_DRV_MasterSetConfig(flexio_i2s_master_state_t *master, uint32_t baudRate, uint8_t bitsWidth)
Set the baud rate and bit width for any subsequent I2S communication.
status_t FLEXIO_I2S_DRV_MasterGetStatus(flexio_i2s_master_state_t *master, uint32_t *bytesRemaining)
Get the status of the current non-blocking I2S master transaction.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
FLEXIO_Type *const g_flexioBase[(1u)]
const uint8_t g_flexioDMASrc[(1u)][(4U)]
flexio_driver_type_t driverType
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
void EDMA_DRV_SetSrcAddr(uint8_t virtualChannel, uint32_t address)
Configures the source address for the eDMA channel.
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t FLEXIO_I2S_DRV_MasterInit(uint32_t instance, const flexio_i2s_master_user_config_t *userConfigPtr, flexio_i2s_master_state_t *master)
Initialize the FLEXIO_I2S master mode driver.
flexio_device_state_t * g_flexioDeviceStatePtr[(1u)]
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
flexio_driver_type_t driverType
status_t EDMA_DRV_StartChannel(uint8_t virtualChannel)
Starts an eDMA channel.
status_t FLEXIO_I2S_DRV_MasterSetRxBuffer(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
status_t EDMA_DRV_SetChannelRequest(uint8_t virtualChannel, uint8_t req)
Configures the DMA request for the eDMA channel.
Master configuration structure.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
status_t FLEXIO_I2S_DRV_MasterGetBaudRate(flexio_i2s_master_state_t *master, uint32_t *baudRate)
Get the currently configured baud rate.
status_t FLEXIO_I2S_DRV_MasterTransferAbort(flexio_i2s_master_state_t *master)
Aborts a non-blocking I2S master transaction.
status_t FLEXIO_I2S_DRV_SlaveSetConfig(flexio_i2s_slave_state_t *slave, uint8_t bitsWidth)
Set the bit width for any subsequent I2S communication.