timing_irq.h
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #ifndef TIMING_IRQ_H
20 #define TIMING_IRQ_H
21 
22 #include "device_registers.h"
23 #include "timing_pal_mapping.h"
24 #include "interrupt_manager.h"
25 
26 /*******************************************************************************
27  * Variables
28  ******************************************************************************/
29 
30 #if (defined (TIMING_OVER_FTM))
31 
32 extern FTM_Type * const ftmBase[FTM_INSTANCE_COUNT];
33 /* Table to save FTM channel running status */
34 extern bool g_ftmChannelRunning[FTM_INSTANCE_COUNT][FTM_CONTROLS_COUNT];
35 #endif /* TIMING_OVER_FTM */
36 
37 /*******************************************************************************
38  * Prototypes
39  ******************************************************************************/
40 #if (defined (TIMING_OVER_LPIT))
41 void TIMING_Lpit_IrqHandler(uint32_t instance, uint8_t channel);
42 #endif
43 
44 #if (defined (TIMING_OVER_LPTMR))
45 void TIMING_Lptmr_IrqHandler(uint32_t instance, uint8_t channel);
46 #endif
47 
48 #if (defined (TIMING_OVER_FTM))
49 void TIMING_Ftm_IrqHandler(uint32_t instance, uint8_t channel);
50 #endif
51 
52 #if (defined (TIMING_OVER_PIT))
53 void TIMING_Pit_IrqHandler(uint32_t instance, uint8_t channel);
54 #endif
55 
56 #if (defined (TIMING_OVER_STM))
57 void TIMING_Stm_IrqHandler(uint32_t instance, uint8_t channel);
58 #endif
59 /*******************************************************************************
60  * Default interrupt handlers signatures
61  ******************************************************************************/
62 
63 /* Define TIMING PAL over FTM */
64 #if (defined(TIMING_OVER_FTM))
65 
66 #if (FTM_INSTANCE_COUNT > 0U)
67 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
68 void FTM0_Ch0_7_IrqHandler(void);
69 #else
70 void FTM0_Ch0_Ch1_IrqHandler(void);
71 
72 void FTM0_Ch2_Ch3_IrqHandler(void);
73 
74 void FTM0_Ch4_Ch5_IrqHandler(void);
75 
76 void FTM0_Ch6_Ch7_IrqHandler(void);
77 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
78 #endif /* FTM_INSTANCE_COUNT > 0U */
79 
80 #if (FTM_INSTANCE_COUNT > 1U)
81 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
82 void FTM1_Ch0_7_IrqHandler(void);
83 #else
84 void FTM1_Ch0_Ch1_IrqHandler(void);
85 
86 void FTM1_Ch2_Ch3_IrqHandler(void);
87 
88 void FTM1_Ch4_Ch5_IrqHandler(void);
89 
90 void FTM1_Ch6_Ch7_IrqHandler(void);
91 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
92 #endif /* FTM_INSTANCE_COUNT > 1U */
93 
94 #if (FTM_INSTANCE_COUNT > 2U)
95 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
96 void FTM2_Ch0_7_IrqHandler(void);
97 #else
98 void FTM2_Ch0_Ch1_IrqHandler(void);
99 
100 void FTM2_Ch2_Ch3_IrqHandler(void);
101 
102 void FTM2_Ch4_Ch5_IrqHandler(void);
103 
104 void FTM2_Ch6_Ch7_IrqHandler(void);
105 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
106 #endif /* FTM_INSTANCE_COUNT > 2U */
107 
108 #if (FTM_INSTANCE_COUNT > 3U)
109 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
110 void FTM3_Ch0_7_IrqHandler(void);
111 #else
112 void FTM3_Ch0_Ch1_IrqHandler(void);
113 
114 void FTM3_Ch2_Ch3_IrqHandler(void);
115 
116 void FTM3_Ch4_Ch5_IrqHandler(void);
117 
118 void FTM3_Ch6_Ch7_IrqHandler(void);
119 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
120 #endif /* FTM_INSTANCE_COUNT > 3U */
121 
122 #if (FTM_INSTANCE_COUNT > 4U)
123 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
124 void FTM4_Ch0_7_IrqHandler(void);
125 #else
126 void FTM4_Ch0_Ch1_IrqHandler(void);
127 
128 void FTM4_Ch2_Ch3_IrqHandler(void);
129 
130 void FTM4_Ch4_Ch5_IrqHandler(void);
131 
132 void FTM4_Ch6_Ch7_IrqHandler(void);
133 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
134 #endif /* FTM_INSTANCE_COUNT > 4U */
135 
136 #if (FTM_INSTANCE_COUNT > 5U)
137 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
138 void FTM5_Ch0_7_IrqHandler(void);
139 #else
140 void FTM5_Ch0_Ch1_IrqHandler(void);
141 
142 void FTM5_Ch2_Ch3_IrqHandler(void);
143 
144 void FTM5_Ch4_Ch5_IrqHandler(void);
145 
146 void FTM5_Ch6_Ch7_IrqHandler(void);
147 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
148 #endif /* FTM_INSTANCE_COUNT > 5U */
149 
150 #if (FTM_INSTANCE_COUNT > 6U)
151 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
152 void FTM6_Ch0_7_IrqHandler(void);
153 #else
154 void FTM6_Ch0_Ch1_IrqHandler(void);
155 
156 void FTM6_Ch2_Ch3_IrqHandler(void);
157 
158 void FTM6_Ch4_Ch5_IrqHandler(void);
159 
160 void FTM6_Ch6_Ch7_IrqHandler(void);
161 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
162 #endif /* FTM_INSTANCE_COUNT > 6U */
163 
164 #if (FTM_INSTANCE_COUNT > 7U)
165 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
166 void FTM7_Ch0_7_IrqHandler(void);
167 #else
168 void FTM7_Ch0_Ch1_IrqHandler(void);
169 
170 void FTM7_Ch2_Ch3_IrqHandler(void);
171 
172 void FTM7_Ch4_Ch5_IrqHandler(void);
173 
174 void FTM7_Ch6_Ch7_IrqHandler(void);
175 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
176 #endif /* FTM_INSTANCE_COUNT > 7U */
177 /* Array storing references to TIMING over FTM irq handlers */
178 extern const isr_t s_timingOverFtmIsr[FTM_INSTANCE_COUNT][FTM_CONTROLS_COUNT];
179 
180 #endif /* TIMING_OVER_FTM */
181 
182 #endif /* TIMING_IRQ_H */
183 /*******************************************************************************
184  * EOF
185  ******************************************************************************/
#define FTM_CONTROLS_COUNT
Definition: S32K118.h:3822
#define FTM_INSTANCE_COUNT
Definition: S32K118.h:3868
void(* isr_t)(void)
Interrupt handler type.