60 #if !defined(S32K118_FEATURES_H)
61 #define S32K118_FEATURES_H
70 #define NUMBER_OF_CORES (1u)
75 #define FEATURE_SOC_PORT_COUNT (5)
77 #define FEATURE_SOC_SCG_COUNT (1)
80 #define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U)
83 #define FEATURE_SCG_FIRC_FREQ0 (48000000U)
85 #define FEATURE_SCB_VECTKEY (0x05FAU)
90 #define FEATURE_FLS_IS_FTFA (0u)
92 #define FEATURE_FLS_IS_FTFC (1u)
94 #define FEATURE_FLS_IS_FTFE (0u)
96 #define FEATURE_FLS_IS_FTFL (0u)
98 #define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u)
100 #define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u)
102 #define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u)
104 #define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u)
106 #define FEATURE_FLS_PF_BLOCK_COUNT (1u)
108 #define FEATURE_FLS_PF_BLOCK_SIZE (262144)
110 #define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (2048u)
112 #define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u)
114 #define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u)
116 #define FEATURE_FLS_HAS_FLEX_NVM (1u)
118 #define FEATURE_FLS_DF_BLOCK_COUNT (1u)
120 #define FEATURE_FLS_DF_BLOCK_SIZE (32768u)
122 #define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (2048u)
124 #define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u)
126 #define FEATURE_FLS_DF_START_ADDRESS (0x10000000u)
128 #define FEATURE_FLS_HAS_FLEX_RAM (1u)
130 #define FEATURE_FLS_FLEX_RAM_SIZE (2048u)
132 #define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u)
134 #define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u)
136 #define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u)
138 #define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u)
140 #define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u)
142 #define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u)
144 #define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u)
146 #define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u)
148 #define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u)
150 #define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u)
152 #define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u)
154 #define FEATURE_FLS_HAS_READ_ONCE_CMD (1u)
156 #define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u)
158 #define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u)
160 #define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u)
162 #define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u)
164 #define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u)
166 #define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u)
168 #define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u)
170 #define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
172 #define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
174 #define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
176 #define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
178 #define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
180 #define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u)
182 #define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
184 #define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
186 #define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
188 #define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
190 #define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
192 #define FEATURE_FLS_DF_SIZE_0000 (0x00008000u)
194 #define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu)
196 #define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu)
198 #define FEATURE_FLS_DF_SIZE_0011 (0x00000000u)
200 #define FEATURE_FLS_DF_SIZE_0100 (0xFFFFFFFFu)
202 #define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu)
204 #define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu)
206 #define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu)
208 #define FEATURE_FLS_DF_SIZE_1000 (0x00000000u)
210 #define FEATURE_FLS_DF_SIZE_1001 (0x00002000u)
212 #define FEATURE_FLS_DF_SIZE_1010 (0xFFFFFFFFu)
214 #define FEATURE_FLS_DF_SIZE_1011 (0x00008000u)
216 #define FEATURE_FLS_DF_SIZE_1100 (0xFFFFFFFFu)
218 #define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu)
220 #define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu)
222 #define FEATURE_FLS_DF_SIZE_1111 (0x00008000u)
224 #define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu)
226 #define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu)
228 #define FEATURE_FLS_EE_SIZE_0010 (0xFFFFu)
230 #define FEATURE_FLS_EE_SIZE_0011 (0x0800u)
232 #define FEATURE_FLS_EE_SIZE_0100 (0xFFFFu)
234 #define FEATURE_FLS_EE_SIZE_0101 (0xFFFFu)
236 #define FEATURE_FLS_EE_SIZE_0110 (0xFFFFu)
238 #define FEATURE_FLS_EE_SIZE_0111 (0xFFFFu)
240 #define FEATURE_FLS_EE_SIZE_1000 (0xFFFFu)
242 #define FEATURE_FLS_EE_SIZE_1001 (0xFFFFu)
244 #define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu)
246 #define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu)
248 #define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu)
250 #define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu)
252 #define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu)
254 #define FEATURE_FLS_EE_SIZE_1111 (0x0000u)
256 #define FEATURE_FLS_HAS_DETECT_ECC_ERROR (1)
258 #define FEATURE_FLS_HAS_INTERRUPT_DOUBLE_BIT_FAULT_IRQ (0)
263 #define FEATURE_SMC_HAS_STOPO (1)
265 #define FEATURE_SMC_HAS_PSTOPO (0)
267 #define FEATURE_SMC_HAS_WAIT_VLPW (0)
269 #define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
274 #define FEATURE_RCM_HAS_EXISTENCE_CMU_LOSS_OF_CLOCK (1)
276 #define FEATURE_RCM_HAS_CMU_LOSS_OF_CLOCK (1)
278 #define FEATURE_RCM_HAS_STICKY_CMU_LOSS_OF_CLOCK (1)
283 #define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U)
285 #define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U)
287 #define FEATURE_WDOG_TO_RESET_VALUE (0x400U)
289 #define FEATURE_WDOG_MINIMUM_TIMEOUT_VALUE (0x0U)
291 #define FEATURE_WDOG_WIN_RESET_VALUE (0x0U)
293 #define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U)
295 #define FEATURE_WDOG_CLK_FROM_LPO (0x1UL)
297 #define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U)
299 #define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U)
301 #define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U)
303 #define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U)
305 #define FEATURE_WDOG_CS_RESET_VALUE (0x2520U)
310 #define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn)
312 #define FEATURE_INTERRUPT_IRQ_MAX (LPUART0_RxTx_IRQn)
314 #define FEATURE_NVIC_PRIO_BITS (2U)
316 #define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u)
318 #define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u)
320 #define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (0u)
322 #define FEATURE_INTERRUPT_MULTICORE_SUPPORT (0u)
324 #define FEATURE_INTERRUPT_INT_VECTORS {&S32_SCB->VTOR}
329 #define FEATURE_FTM_CHANNEL_COUNT (8U)
331 #define FTM_FEATURE_FAULT_CHANNELS (4U)
333 #define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U)
335 #define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U)
337 #define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU)
339 #define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U)
341 #define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U)
343 #define FEATURE_FTM_HAS_NUM_IRQS_CHANS (1U)
348 #define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (1)
350 #define LPIT_CLOCK_NAMES {LPIT0_CLK}
355 #define LPI2C_DMA_INSTANCE 0U
358 #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}}
360 #define LPI2C_PCC_CLOCKS {LPI2C0_CLK}
363 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
364 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
365 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
370 #define LPI2C_DMA_INSTANCE 0U
373 #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}}
375 #define LPI2C_PCC_CLOCKS {LPI2C0_CLK}
378 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
379 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
380 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
385 #define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0)
387 #define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0)
393 #define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU)
396 #define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU)
399 #define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U)
402 #define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU)
405 #define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU)
408 #define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U)
411 #define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U)
413 #define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U)
416 #define FEATURE_CSEC_SREG_OFFSET (0x2FU)
419 #define FEATURE_CSEC_PAGE_0_OFFSET (0x0U)
421 #define FEATURE_CSEC_PAGE_1_OFFSET (0x10U)
423 #define FEATURE_CSEC_PAGE_2_OFFSET (0x20U)
425 #define FEATURE_CSEC_PAGE_3_OFFSET (0x30U)
427 #define FEATURE_CSEC_PAGE_4_OFFSET (0x40U)
429 #define FEATURE_CSEC_PAGE_5_OFFSET (0x50U)
431 #define FEATURE_CSEC_PAGE_6_OFFSET (0x60U)
433 #define FEATURE_CSEC_PAGE_7_OFFSET (0x70U)
438 #define FEATURE_CRC_DRIVER_SOFT_POLYNOMIAL
440 #define FEATURE_CRC_DEFAULT_WIDTH CRC_BITS_16
442 #define FEATURE_CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE
444 #define FEATURE_CRC_DEFAULT_WRITE_TRANSPOSE CRC_TRANSPOSE_NONE
446 #define FEATURE_CRC_DEFAULT_POLYNOMIAL (0x1021U)
448 #define FEATURE_CRC_DEFAULT_SEED (0xFFFFU)
452 #define FEATURE_PINS_DRIVER_USING_PORT (1)
454 #define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
456 #define FEATURE_PINS_HAS_OPEN_DRAIN (0)
458 #define FEATURE_PORT_HAS_DIGITAL_FILTER (1)
460 #define FEATURE_PORT_HAS_TRIGGER_OUT (0)
462 #define FEATURE_PORT_HAS_FLAG_SET_ONLY (0)
464 #define FEATURE_PINS_HAS_OVER_CURRENT (0)
466 #define FEATURE_PINS_HAS_PULL_SELECTION (1)
468 #define FEATURE_PINS_HAS_SLEW_RATE (0)
470 #define FEATURE_PORT_HAS_PASSIVE_FILTER (1)
472 #define FEATURE_PINS_HAS_DRIVE_STRENGTH (1)
474 #define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0)
476 #define FEATURE_PORT_HAS_INPUT_DISABLE (0)
481 #define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U)
483 #define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U)
485 #define FEATURE_MPU_MASTER_COUNT (3U)
489 #define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U)
493 #define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U)
499 #define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U)
503 #define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U)
506 #define FEATURE_MPU_MASTER_CORE (0U)
508 #define FEATURE_MPU_MASTER_DEBUGGER (1U)
510 #define FEATURE_MPU_MASTER_DMA (2U)
512 #define FEATURE_MPU_MASTER \
514 FEATURE_MPU_MASTER_CORE, \
515 FEATURE_MPU_MASTER_DEBUGGER, \
516 FEATURE_MPU_MASTER_DMA, \
520 #define FEATURE_MPU_SLAVE_COUNT (2U)
522 #define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U)
524 #define FEATURE_MPU_SLAVE_SRAM_MTB_DWT_MCM (1U)
526 #define FEATURE_MPU_SLAVE_MASK (0xC0000000U)
527 #define FEATURE_MPU_SLAVE_SHIFT (30u)
528 #define FEATURE_MPU_SLAVE_WIDTH (2u)
529 #define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<FEATURE_MPU_SLAVE_SHIFT))&FEATURE_MPU_SLAVE_MASK)
533 #define FEATURE_HAS_HIGH_SPEED_RUN_MODE (0U)
535 #define FEATURE_HAS_SPLL_CLK (0U)
540 #define FEATURE_CMP_HAS_HARD_BLOCK_OFFSET (1U)
542 #define FEATURE_CMP_DAC_FIX_SELECTION (0U)
544 #define FEATURE_CMP_HAS_INIT_DELAY (1U)
546 #define C0_RESET_VALUE (CMP_C0_DMAEN(0U) | CMP_C0_IER(0U) | CMP_C0_IEF(0U) | CMP_C0_CFR(1U) | \
547 CMP_C0_CFF(1U) | CMP_C0_FPR(0U) | CMP_C0_SE(0U) | CMP_C0_WE(0U) | \
548 CMP_C0_PMODE(0U) | CMP_C0_INVT(0U) | CMP_C0_COS(0U) | CMP_C0_OPE(0U) | \
549 CMP_C0_EN(0U) | CMP_C0_FILTER_CNT(0U) | CMP_C0_OFFSET(0U) | CMP_C0_HYSTCTR(0U))
551 #define C1_RESET_VALUE (CMP_C1_INPSEL(0U) | CMP_C1_INNSEL(0U) | CMP_C1_CHN7(0U) | CMP_C1_CHN6(0U) | \
552 CMP_C1_CHN5(0U) | CMP_C1_CHN4(0U) | CMP_C1_CHN3(0U) | CMP_C1_CHN2(0U) | \
553 CMP_C1_CHN1(0U) | CMP_C1_CHN0(0U) | CMP_C1_DACEN(0U) | CMP_C1_VRSEL(0U) | \
554 CMP_C1_PSEL(0U) | CMP_C1_MSEL(0U) | CMP_C1_VOSEL(0U))
556 #define C2_RESET_VALUE (CMP_C2_RRE(0U) | CMP_C2_RRIE(0U) | CMP_C2_FXMP(0U) | CMP_C2_FXMXCH(0U) | CMP_C2_CH7F(1U) | \
557 CMP_C2_CH6F(1U) | CMP_C2_CH5F(1U) | CMP_C2_CH4F(1U) | CMP_C2_CH3F(1U) | CMP_C2_CH2F(1U) | \
558 CMP_C2_CH1F(1U) | CMP_C2_CH0F(1U) | CMP_C2_NSAM(0U) | CMP_C2_NSAM(0U) | CMP_C2_INITMOD(0U) | \
561 #define CMP_DAC_SOURCE 0U
562 #define CMP_MUX_SOURCE 1U
563 #define CMP_DAC_RESOLUTION 255U
636 #define PCC_INVALID_INDEX 0
643 #define PCC_CLOCK_NAME_MAPPINGS \
696 PCC_FlexCAN0_INDEX, \
720 #define NO_PERIPHERAL_FEATURE (0U)
721 #define HAS_CLOCK_GATING_IN_SIM (1U << 0U)
722 #define HAS_MULTIPLIER (1U << 1U)
723 #define HAS_DIVIDER (1U << 2U)
724 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U)
725 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U)
726 #define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U)
727 #define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U)
728 #define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U)
734 #define PERIPHERAL_FEATURES \
736 (NO_PERIPHERAL_FEATURE), \
737 (NO_PERIPHERAL_FEATURE), \
738 (NO_PERIPHERAL_FEATURE), \
739 (NO_PERIPHERAL_FEATURE), \
740 (NO_PERIPHERAL_FEATURE), \
741 (NO_PERIPHERAL_FEATURE), \
742 (NO_PERIPHERAL_FEATURE), \
743 (NO_PERIPHERAL_FEATURE), \
744 (NO_PERIPHERAL_FEATURE), \
745 (NO_PERIPHERAL_FEATURE), \
746 (NO_PERIPHERAL_FEATURE), \
747 (NO_PERIPHERAL_FEATURE), \
748 (NO_PERIPHERAL_FEATURE), \
749 (NO_PERIPHERAL_FEATURE), \
750 (NO_PERIPHERAL_FEATURE), \
751 (NO_PERIPHERAL_FEATURE), \
752 (NO_PERIPHERAL_FEATURE), \
753 (NO_PERIPHERAL_FEATURE), \
754 (NO_PERIPHERAL_FEATURE), \
755 (NO_PERIPHERAL_FEATURE), \
756 (NO_PERIPHERAL_FEATURE), \
757 (NO_PERIPHERAL_FEATURE), \
758 (NO_PERIPHERAL_FEATURE), \
759 (NO_PERIPHERAL_FEATURE), \
760 (NO_PERIPHERAL_FEATURE), \
761 (NO_PERIPHERAL_FEATURE), \
762 (NO_PERIPHERAL_FEATURE), \
763 (NO_PERIPHERAL_FEATURE), \
764 (NO_PERIPHERAL_FEATURE), \
765 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
766 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
767 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
768 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
769 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
770 (NO_PERIPHERAL_FEATURE), \
771 (NO_PERIPHERAL_FEATURE), \
772 (NO_PERIPHERAL_FEATURE), \
773 (NO_PERIPHERAL_FEATURE), \
774 (NO_PERIPHERAL_FEATURE), \
775 (NO_PERIPHERAL_FEATURE), \
776 (NO_PERIPHERAL_FEATURE), \
777 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
778 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
779 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
780 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
781 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
782 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
783 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
784 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
785 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
786 (NO_PERIPHERAL_FEATURE), \
787 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
788 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
789 (NO_PERIPHERAL_FEATURE), \
790 (HAS_INT_CLOCK_FROM_SLOW_CLOCK), \
791 (NO_PERIPHERAL_FEATURE), \
792 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
793 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
794 (NO_PERIPHERAL_FEATURE), \
795 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
796 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
797 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
798 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
799 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
800 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
801 (HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
802 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
803 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
804 (NO_PERIPHERAL_FEATURE), \
805 (NO_PERIPHERAL_FEATURE), \
810 #define SIRC_STABILIZATION_TIMEOUT 100U
814 #define FIRC_STABILIZATION_TIMEOUT 20U
818 #define SOSC_STABILIZATION_TIMEOUT 3205000U;
822 #define SPLL_STABILIZATION_TIMEOUT 1000U;
835 #define TMP_SIRC_CLK 0U
836 #define TMP_FIRC_CLK 1U
837 #define TMP_SOSC_CLK 2U
838 #define TMP_SPLL_CLK 3U
840 #define TMP_SYS_DIV 0U
841 #define TMP_BUS_DIV 1U
842 #define TMP_SLOW_DIV 2U
844 #define TMP_SYS_CLK_NO 4U
845 #define TMP_SYS_DIV_NO 3U
847 #define TMP_SYSTEM_CLOCK_CONFIGS \
849 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
850 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, \
851 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
852 { SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
858 #define FEATURE_DMA_CHANNELS (4U)
860 #define FEATURE_DMA_VIRTUAL_CHANNELS ((uint32_t)FEATURE_DMA_CHANNELS * (uint32_t)DMA_INSTANCE_COUNT)
862 #define FEATURE_DMA_CHANNELS_INTERRUPT_LINES (4U)
864 #define FEATURE_DMA_VIRTUAL_CHANNELS_INTERRUPT_LINES ((uint32_t)FEATURE_DMA_CHANNELS_INTERRUPT_LINES * (uint32_t)DMA_INSTANCE_COUNT)
866 #define FEATURE_DMA_ERROR_INTERRUPT_LINES (1U)
868 #define FEATURE_DMA_VIRTUAL_ERROR_INTERRUPT_LINES ((uint32_t)FEATURE_DMA_ERROR_INTERRUPT_LINES * (uint32_t)DMA_INSTANCE_COUNT)
870 #define FEATURE_DMA_HAS_ERROR_IRQ
872 #define FEATURE_DMA_SEPARATE_IRQ_LINES_PER_CHN
874 #define FEATURE_DMA_CHN_TO_DCHPRI_INDEX(x) ((x) ^ 3U)
876 #define FEATURE_DMA_CHANNEL_GROUP_COUNT (1U)
878 #define FEATURE_DMA_CLOCK_NAMES {SIM_DMA_CLK}
880 #define FEATURE_DMA_CH_WIDTH (4U)
882 #define FEATURE_DMA_VCH_TO_INSTANCE(x) ((x) >> (uint32_t)FEATURE_DMA_CH_WIDTH)
884 #define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U))
886 #define FEATURE_DMA_4_CH_PRIORITIES
888 #define FEATURE_DMA_ENGINE_STALL
893 #define FEATURE_DMAMUX_CHANNELS (4U)
895 #define FEATURE_DMAMUX_HAS_TRIG (1)
897 #define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x)
899 #define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U)
901 #define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x)
903 #define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x)
905 #define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK}
1059 #define FEATURE_TRGMUX_TARGET_MODULE \
1061 TRGMUX_TARGET_MODULE_DMA_CH0, \
1062 TRGMUX_TARGET_MODULE_DMA_CH1, \
1063 TRGMUX_TARGET_MODULE_DMA_CH2, \
1064 TRGMUX_TARGET_MODULE_DMA_CH3, \
1065 TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \
1066 TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \
1067 TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \
1068 TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \
1069 TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \
1070 TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \
1071 TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \
1072 TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \
1073 TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \
1074 TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \
1075 TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \
1076 TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \
1077 TRGMUX_TARGET_MODULE_FTM0_FAULT0, \
1078 TRGMUX_TARGET_MODULE_FTM0_FAULT1, \
1079 TRGMUX_TARGET_MODULE_FTM0_FAULT2, \
1080 TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \
1081 TRGMUX_TARGET_MODULE_FTM1_FAULT0, \
1082 TRGMUX_TARGET_MODULE_FTM1_FAULT1, \
1083 TRGMUX_TARGET_MODULE_FTM1_FAULT2, \
1084 TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \
1085 TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \
1086 TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \
1087 TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \
1088 TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \
1089 TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \
1090 TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \
1091 TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \
1092 TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \
1093 TRGMUX_TARGET_MODULE_LPUART0_TRG, \
1094 TRGMUX_TARGET_MODULE_LPUART1_TRG, \
1095 TRGMUX_TARGET_MODULE_LPI2C0_TRG, \
1096 TRGMUX_TARGET_MODULE_LPSPI0_TRG, \
1097 TRGMUX_TARGET_MODULE_LPSPI1_TRG, \
1098 TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \
1104 #define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL}
1106 #define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK};
1111 #define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U)
1113 #define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0
1114 #define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1
1115 #define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2
1116 #define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3
1121 #define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1123 #define FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
1125 #define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
1127 #define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
1129 #define FEATURE_LPUART_FIFO_SIZE (4U)
1131 #define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
1133 #define FEATURE_LPUART_HAS_DMA_ENABLE (1)
1135 #define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U)
1137 #define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U)
1139 #define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U)
1141 #define FEATURE_LPUART_DEFAULT_OSR (0x0FUL)
1143 #define FEATURE_LPUART_DEFAULT_SBR (0x04UL)
1145 #define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK}
1151 #define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0)
1153 #define NUMBER_OF_ALT_CLOCKS ADC_CLK_ALT_1
1157 #define FEATURE_ADC_MAX_NUM_EXT_CHANS (16)
1158 #define FEATURE_ADC_HAS_CHANNEL_2 (1)
1159 #define FEATURE_ADC_HAS_CHANNEL_8 (1)
1160 #define ADC_CLOCKS {ADC0_CLK}
1162 #if FEATURE_ADC_HAS_EXTRA_NUM_REGS
1163 #define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT
1165 #define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT
1169 #define ADC_DEFAULT_SAMPLE_TIME (0x0CU)
1171 #define ADC_DEFAULT_USER_GAIN (0x04U)
1173 #define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u)
1175 #define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u)
1180 #define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U)
1182 #define FEATURE_CAN_RXFIFO_WARNING (6U)
1184 #define FEATURE_CAN_RXFIFO_OVERFLOW (7U)
1186 #define FEATURE_CAN0_HAS_FD (1)
1188 #define FEATURE_CAN0_MAX_MB_NUM (32U)
1190 #define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1)
1192 #define FEATURE_CAN_HAS_DMA_ENABLE (1)
1194 #define FEATURE_CAN_MAX_MB_NUM (32U)
1196 #define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM }
1198 #define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1)
1200 #define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0)
1202 #define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1)
1204 #define FEATURE_CAN_HAS_MBDSR1 (0)
1206 #define FEATURE_CAN_HAS_MBDSR2 (0)
1208 #define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0 }
1211 #define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U)
1213 #define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \
1214 CAN_ORed_16_31_MB_IRQS }
1216 #define FEATURE_CAN_HAS_WAKE_UP_IRQ (1)
1218 #define FEATURE_CAN_HAS_SELF_WAKE_UP (0)
1220 #define FEATURE_CAN_HAS_FD (1)
1222 #define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK
1227 #define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U)
1231 #define FEATURE_OSIF_USE_SYSTICK (1)
1232 #define FEATURE_OSIF_USE_PIT (0)
trgmux_trigger_source_e
Enumeration for trigger source module of TRGMUX.
trgmux_target_module_e
Enumeration for target module of TRGMUX.
clock_names_t
Clock names.
dma_request_source_t
Structure for the DMA hardware request.