20 #include "flexio_hw_access.h"
92 #define DIVIDER_MAX_VALUE 0xFFU
96 #define TX_SHIFTER(x) (x)
97 #define RX_SHIFTER(x) (x)
98 #define TX_TIMER(x) (x)
99 #define RX_TIMER(x) (x)
112 static void FLEXIO_UART_DRV_ComputeBaudRateDivider(uint32_t baudRate,
119 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 1U;
121 if (tmpDiv > DIVIDER_MAX_VALUE)
123 tmpDiv = DIVIDER_MAX_VALUE;
126 *divider = (uint16_t)tmpDiv;
143 uint8_t resourceIndex;
146 resourceIndex = state->flexioCommon.resourceIndex;
149 FLEXIO_UART_DRV_ComputeBaudRateDivider(userConfigPtr->
baudRate, ÷r, inputClock);
153 FLEXIO_SetShifterConfig(baseAddr,
154 TX_SHIFTER(resourceIndex),
155 FLEXIO_SHIFTER_START_BIT_0,
156 FLEXIO_SHIFTER_STOP_BIT_1,
157 FLEXIO_SHIFTER_SOURCE_PIN);
158 FLEXIO_SetShifterControl(baseAddr,
159 TX_SHIFTER(resourceIndex),
160 FLEXIO_SHIFTER_MODE_TRANSMIT,
162 FLEXIO_PIN_POLARITY_HIGH,
163 FLEXIO_PIN_CONFIG_OUTPUT,
164 TX_TIMER(resourceIndex),
165 FLEXIO_TIMER_POLARITY_POSEDGE);
168 FLEXIO_SetTimerCompare(baseAddr, TX_TIMER(resourceIndex), (uint16_t)((((bits << 1U) - 1U) << 8U) + divider));
169 FLEXIO_SetTimerConfig(baseAddr,
170 TX_TIMER(resourceIndex),
171 FLEXIO_TIMER_START_BIT_ENABLED,
172 FLEXIO_TIMER_STOP_BIT_TIM_DIS,
173 FLEXIO_TIMER_ENABLE_TRG_HIGH,
174 FLEXIO_TIMER_DISABLE_TIM_CMP,
175 FLEXIO_TIMER_RESET_NEVER,
176 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
177 FLEXIO_TIMER_INITOUT_ONE);
178 FLEXIO_SetTimerControl(baseAddr,
179 TX_TIMER(resourceIndex),
180 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
181 FLEXIO_TRIGGER_POLARITY_LOW,
182 FLEXIO_TRIGGER_SOURCE_INTERNAL,
184 FLEXIO_PIN_POLARITY_HIGH,
185 FLEXIO_PIN_CONFIG_DISABLED,
186 FLEXIO_TIMER_MODE_DISABLED);
204 uint8_t resourceIndex;
207 resourceIndex = state->flexioCommon.resourceIndex;
210 FLEXIO_UART_DRV_ComputeBaudRateDivider(userConfigPtr->
baudRate, ÷r, inputClock);
214 FLEXIO_SetShifterConfig(baseAddr,
215 RX_SHIFTER(resourceIndex),
216 FLEXIO_SHIFTER_START_BIT_0,
217 FLEXIO_SHIFTER_STOP_BIT_1,
218 FLEXIO_SHIFTER_SOURCE_PIN);
219 FLEXIO_SetShifterControl(baseAddr,
220 RX_SHIFTER(resourceIndex),
221 FLEXIO_SHIFTER_MODE_DISABLED,
223 FLEXIO_PIN_POLARITY_HIGH,
224 FLEXIO_PIN_CONFIG_DISABLED,
225 RX_TIMER(resourceIndex),
226 FLEXIO_TIMER_POLARITY_NEGEDGE);
229 FLEXIO_SetTimerCompare(baseAddr, RX_TIMER(resourceIndex), (uint16_t)((((bits << 1U) - 1U) << 8U) + divider));
230 FLEXIO_SetTimerConfig(baseAddr,
231 RX_TIMER(resourceIndex),
232 FLEXIO_TIMER_START_BIT_ENABLED,
233 FLEXIO_TIMER_STOP_BIT_TIM_DIS,
234 FLEXIO_TIMER_ENABLE_PIN_POSEDGE,
235 FLEXIO_TIMER_DISABLE_TIM_CMP,
236 FLEXIO_TIMER_RESET_PIN_RISING,
237 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
238 FLEXIO_TIMER_INITOUT_ONE_RESET);
239 FLEXIO_SetTimerControl(baseAddr,
240 RX_TIMER(resourceIndex),
242 FLEXIO_TRIGGER_POLARITY_HIGH,
243 FLEXIO_TRIGGER_SOURCE_EXTERNAL,
245 FLEXIO_PIN_POLARITY_LOW,
246 FLEXIO_PIN_CONFIG_DISABLED,
247 FLEXIO_TIMER_MODE_DISABLED);
260 uint8_t resourceIndex;
263 resourceIndex = state->flexioCommon.resourceIndex;
266 switch (state->driverType)
270 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
271 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
273 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << TX_TIMER(resourceIndex)),
false);
280 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << TX_TIMER(resourceIndex)),
false);
284 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
291 state->driverIdle =
true;
293 if (state->blocking ==
true)
309 uint8_t resourceIndex;
311 resourceIndex = state->flexioCommon.resourceIndex;
318 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
319 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_RECEIVE);
321 FLEXIO_SetTimerMode(baseAddr, TX_TIMER(resourceIndex), FLEXIO_TIMER_MODE_8BIT_BAUD);
334 uint8_t resourceIndex;
336 resourceIndex = state->flexioCommon.resourceIndex;
340 FLEXIO_SetTimerMode(baseAddr, TX_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
341 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
344 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
347 FLEXIO_UART_DRV_EndTransfer(state);
353 FLEXIO_SetShifterStartBit(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_START_BIT_0);
354 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_TRANSMIT);
369 switch (state->driverType)
389 state->blocking =
false;
394 FLEXIO_UART_DRV_StopTransfer(state);
397 return state->status;
411 uint8_t resourceIndex;
417 resourceIndex = state->flexioCommon.resourceIndex;
420 data = FLEXIO_ReadShifterBuffer(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_RW_MODE_NORMAL);
421 data >>= 32U - (uint32_t)(state->bitCount);
423 if (state->bitCount <= 8U)
425 *(uint8_t *)state->data = (uint8_t)data;
428 state->remainingBytes -= 1U;
433 *(uint16_t *)state->data = (uint16_t)data;
435 state->data = &state->data[2U];
436 state->remainingBytes -= 2U;
451 uint8_t resourceIndex;
456 resourceIndex = state->flexioCommon.resourceIndex;
458 if (state->remainingBytes == 0U)
464 if (state->bitCount <= 8U)
466 data = (uint32_t)(*(uint8_t *)state->data);
468 state->remainingBytes -= 1U;
473 data = (uint32_t)(*(uint16_t *)state->data);
474 state->data = &state->data[2U];
475 state->remainingBytes -= 2U;
478 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), data, FLEXIO_SHIFTER_RW_MODE_NORMAL);
490 static void FLEXIO_UART_DRV_CheckStatusTx(
void *stateStruct)
493 uint8_t resourceIndex;
500 resourceIndex = state->flexioCommon.resourceIndex;
504 if (state->remainingBytes == 0U)
506 if (FLEXIO_GetTimerStatus(baseAddr, TX_TIMER(resourceIndex)))
509 FLEXIO_ClearTimerStatus(baseAddr, TX_TIMER(resourceIndex));
511 if (state->txFlush == 0U)
519 FLEXIO_UART_DRV_StopTransfer(state);
521 if (state->callback != NULL)
526 else if (FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)))
532 FLEXIO_SetShifterStartBit(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_START_BIT_1);
533 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), 0xFFFFFFFFUL, FLEXIO_SHIFTER_RW_MODE_NORMAL);
543 else if (FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)) && (state->remainingBytes > 0U))
545 FLEXIO_UART_DRV_WriteData(state);
546 if (state->remainingBytes == 0U)
549 if (state->callback != NULL)
554 if (state->remainingBytes == 0U)
559 FLEXIO_ClearTimerStatus(baseAddr, TX_TIMER(resourceIndex));
563 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
565 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << TX_TIMER(resourceIndex)),
true);
584 static void FLEXIO_UART_DRV_CheckStatusRx(
void *stateStruct)
587 uint8_t resourceIndex;
594 resourceIndex = state->flexioCommon.resourceIndex;
597 if (FLEXIO_GetShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex)))
600 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
601 state->remainingBytes = 0U;
605 else if (FLEXIO_GetShifterStatus(baseAddr, RX_SHIFTER(resourceIndex)))
607 FLEXIO_UART_DRV_ReadData(state);
608 if (state->remainingBytes == 0U)
611 if (state->callback != NULL)
622 if (state->remainingBytes == 0U)
630 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
632 FLEXIO_UART_DRV_StopTransfer(state);
634 if (state->callback != NULL)
649 static void FLEXIO_UART_DRV_CheckStatus(
void *stateStruct)
658 FLEXIO_UART_DRV_CheckStatusTx(stateStruct);
662 FLEXIO_UART_DRV_CheckStatusRx(stateStruct);
673 static void FLEXIO_UART_DRV_EndDmaTxTransfer(
void *stateStruct,
edma_chn_status_t status)
687 if (state->callback != NULL)
691 if (state->remainingBytes == 0U)
695 FLEXIO_ClearTimerStatus(baseAddr, TX_TIMER(state->flexioCommon.resourceIndex));
696 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << TX_TIMER(state->flexioCommon.resourceIndex)),
true);
702 dmaChn = state->dmaChannel;
703 if (state->bitCount <= 8U)
714 state->remainingBytes = 0U;
727 static void FLEXIO_UART_DRV_EndDmaRxTransfer(
void *stateStruct,
edma_chn_status_t status)
739 if (state->callback != NULL)
743 if (state->remainingBytes == 0U)
747 FLEXIO_UART_DRV_StopTransfer(state);
749 if (state->callback != NULL)
758 dmaChn = state->dmaChannel;
759 if (state->bitCount <= 8U)
770 state->remainingBytes = 0U;
791 shifter = TX_SHIFTER(state->flexioCommon.resourceIndex);
792 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter]));
810 if (state->bitCount <= 8U)
819 shifter = RX_SHIFTER(state->flexioCommon.resourceIndex);
820 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter])) + (
sizeof(uint32_t) - byteCount);
833 uint8_t resourceIndex;
839 resourceIndex = state->flexioCommon.resourceIndex;
842 if (state->bitCount <= 8U)
854 (uint32_t)(state->data),
855 FLEXIO_UART_DRV_ComputeTxRegAddr(state),
858 state->remainingBytes / byteCount,
862 state->remainingBytes = 0U;
872 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
true);
884 uint8_t resourceIndex;
890 resourceIndex = state->flexioCommon.resourceIndex;
893 if (state->bitCount <= 8U)
905 FLEXIO_UART_DRV_ComputeRxRegAddr(state),
906 (uint32_t)(state->data),
909 state->remainingBytes / byteCount,
913 state->remainingBytes = 0U;
923 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
961 state->flexioCommon.resourceCount = 1U;
977 state->remainingBytes = 0U;
978 state->callback = userConfigPtr->
callback;
980 state->blocking =
false;
981 state->driverType = userConfigPtr->
driverType;
982 state->direction = userConfigPtr->
direction;
984 state->driverIdle =
true;
985 state->bitCount = userConfigPtr->
bitCount;
990 FLEXIO_UART_DRV_ConfigureTx(state, userConfigPtr, inputClock);
995 FLEXIO_UART_DRV_ConfigureRx(state, userConfigPtr, inputClock);
999 switch (state->driverType)
1004 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusTx;
1008 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusRx;
1016 state->dmaChannel = userConfigPtr->
dmaChannel;
1018 dmaReq =
g_flexioDMASrc[instance][TX_SHIFTER(state->flexioCommon.resourceIndex)];
1023 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusTx;
1049 if (!state->driverIdle)
1077 uint32_t inputClock;
1079 uint8_t resourceIndex;
1089 resourceIndex = state->flexioCommon.resourceIndex;
1092 if (!state->driverIdle)
1102 FLEXIO_UART_DRV_ComputeBaudRateDivider(baudRate, ÷r, inputClock);
1105 FLEXIO_SetTimerCompare(baseAddr, TX_TIMER(resourceIndex), (uint16_t)(((((uint16_t)bitCount << 1U) - 1U) << 8U) + divider));
1107 state->bitCount = bitCount;
1124 uint32_t inputClock;
1128 uint8_t resourceIndex;
1134 resourceIndex = state->flexioCommon.resourceIndex;
1142 timerCmp = FLEXIO_GetTimerCompare(baseAddr, TX_TIMER(resourceIndex));
1143 divider = (uint16_t)(timerCmp & 0x00FFU);
1146 *baudRate = (inputClock + (uint32_t)divider + 1U) / (2U * ((uint32_t)divider + 1U));
1162 const uint8_t * txBuff,
1166 uint8_t resourceIndex;
1173 DEV_ASSERT((state->bitCount <= 8U) || ((txSize & 1U) == 0U));
1176 resourceIndex = state->flexioCommon.resourceIndex;
1179 if (!state->driverIdle)
1184 state->data = (uint8_t *)txBuff;
1185 state->remainingBytes = txSize;
1187 state->driverIdle =
false;
1189 state->txFlush = (uint8_t)((txSize == 1U) ? 1U : 2U);
1192 FLEXIO_UART_DRV_EnableTransfer(state);
1194 switch (state->driverType)
1198 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
true);
1199 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
true);
1203 FLEXIO_UART_DRV_CheckStatus(state);
1206 FLEXIO_UART_DRV_StartTxDmaTransfer(state);
1225 const uint8_t * txBuff,
1234 state->blocking =
true;
1241 state->blocking =
false;
1246 return FLEXIO_UART_DRV_WaitTransferEnd(state, timeout);
1262 uint8_t resourceIndex;
1269 DEV_ASSERT((state->bitCount <= 8U) || ((rxSize & 1U) == 0U));
1272 resourceIndex = state->flexioCommon.resourceIndex;
1275 if (!state->driverIdle)
1280 state->data = rxBuff;
1281 state->remainingBytes = rxSize;
1283 state->driverIdle =
false;
1286 FLEXIO_UART_DRV_EnableTransfer(state);
1288 switch (state->driverType)
1292 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
1293 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
1297 FLEXIO_UART_DRV_CheckStatus(state);
1300 FLEXIO_UART_DRV_StartRxDmaTransfer(state);
1328 state->blocking =
true;
1335 state->blocking =
false;
1340 return FLEXIO_UART_DRV_WaitTransferEnd(state, timeout);
1356 if (state->driverIdle)
1362 FLEXIO_UART_DRV_StopTransfer(state);
1377 uint32_t remainingBytes;
1382 remainingBytes = state->remainingBytes;
1384 if(!state->driverIdle)
1386 switch(state->driverType)
1390 FLEXIO_UART_DRV_CheckStatus(state);
1405 if (bytesRemaining != NULL)
1407 *bytesRemaining = remainingBytes;
1410 if (!state->driverIdle)
1416 return state->status;
1436 state->data = rxBuff;
1437 state->remainingBytes = rxSize;
1451 const uint8_t * txBuff,
1458 state->data = (uint8_t *)txBuff;
1459 state->remainingBytes = txSize;
void EDMA_DRV_SetMajorLoopIterationCount(uint8_t virtualChannel, uint32_t majorLoopCount)
Configures the number of major loop iterations.
uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t virtualChannel)
Returns the remaining major loop iteration count.
status_t EDMA_DRV_InstallCallback(uint8_t virtualChannel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t virtualChannel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t FLEXIO_UART_DRV_ReceiveData(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking UART reception.
status_t FLEXIO_UART_DRV_SetTxBuffer(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
#define FLEXIO_INSTANCE_COUNT
status_t FLEXIO_UART_DRV_SetConfig(flexio_uart_state_t *state, uint32_t baudRate, uint8_t bitCount)
Set the baud rate and bit width for any subsequent UART communication.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
status_t EDMA_DRV_StopChannel(uint8_t virtualChannel)
Stops the eDMA channel.
status_t FLEXIO_UART_DRV_SendData(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking UART transmission.
status_t FLEXIO_UART_DRV_SendDataBlocking(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking UART transmission.
edma_chn_status_t
Channel status for eDMA channel.
flexio_uart_driver_direction_t direction
status_t FLEXIO_UART_DRV_ReceiveDataBlocking(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking UART reception.
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
status_t FLEXIO_UART_DRV_GetBaudRate(flexio_uart_state_t *state, uint32_t *baudRate)
Get the currently configured baud rate.
void EDMA_DRV_SetDestAddr(uint8_t virtualChannel, uint32_t address)
Configures the destination address for the eDMA channel.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
const clock_names_t g_flexioClock[(1u)]
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
FLEXIO_Type *const g_flexioBase[(1u)]
status_t FLEXIO_UART_DRV_GetStatus(flexio_uart_state_t *state, uint32_t *bytesRemaining)
Get the status of the current non-blocking UART transfer.
status_t FLEXIO_UART_DRV_SetRxBuffer(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
Driver internal context structure.
volatile uint32_t SHIFTBUF[4u]
status_t FLEXIO_UART_DRV_Deinit(flexio_uart_state_t *state)
De-initialize the FLEXIO_UART driver.
status_t FLEXIO_UART_DRV_TransferAbort(flexio_uart_state_t *state)
Aborts a non-blocking UART transfer.
const uint8_t g_flexioDMASrc[(1u)][(4U)]
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
void EDMA_DRV_SetSrcAddr(uint8_t virtualChannel, uint32_t address)
Configures the source address for the eDMA channel.
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
flexio_device_state_t * g_flexioDeviceStatePtr[(1u)]
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
status_t EDMA_DRV_StartChannel(uint8_t virtualChannel)
Starts an eDMA channel.
status_t EDMA_DRV_SetChannelRequest(uint8_t virtualChannel, uint8_t req)
Configures the DMA request for the eDMA channel.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
flexio_driver_type_t driverType
Driver configuration structure.
status_t FLEXIO_UART_DRV_Init(uint32_t instance, const flexio_uart_user_config_t *userConfigPtr, flexio_uart_state_t *state)
Initialize the FLEXIO_UART driver.