The S32 SDK provides a Peripheral Abstraction Layer for Watchdog (WDG PAL) modules of S32 SDK devices.
The Watchdog PAL driver allows to generate interrupt event to reset CPU or external circuit. It was designed to be portable across all platforms and IPs which support Watchdog Timer.
Unlike the other drivers, WDG PAL modules need to include a configuration file named wdg_pal_cfg.h, which allows the user to specify which IPSs are used and how many resources are allocated for each of them (state structures). The following code example shows how to configure one instance for each available WDG IPs.
The following table contains the matching between platforms and available IPs
IP/MCU | S32K11x | S32K14x | S32MTV | MPC574x |
---|---|---|---|---|
WDOG | YES | YES | YES | NO |
EWM | NO | YES | YES | NO |
SWT | NO | NO | NO | YES |
In order to use the WDG PAL driver it must be first initialized, using WDG_Init() function. Once initialized, it cannot be initialized again for the same WDG module instance until it is de-initialized, using WDG_Deinit(). Different WDG modules instances can function independently of each other.
After initialization, WDG PAL counter will count to timeout value. In window mode, when WDG PAL counter is refreshed, it will reset count to default value and count again. If WDG PAL counter count to timeout value, CPU or the external circuit will be reseted or placed into safe mode.
The configuration structure includes a special field named extension. It will be used only for WDG PAL over EWM peripheral and should contain a pointer to extension_ewm_for_wdg_t structure. The purpose of this structure is to configure which EWM_OUT pins and clock prescaler are used by the applications.
WDG PAL internal counter is
WDG PAL's counter over EWM and WDOG will start to count from 0 to timeout value. WDG PAL's counter over SWT will start to count from timeout value to 0.
Modules | |
WDG PAL | |
Watchdog Peripheral Abstraction Layer. | |