91 #include "lpi2c_hw_access.h"
101 #define CLKHI_MIN_VALUE 1U
102 #define CLKLO_MIN_VALUE 3U
103 #define CLKHI_MAX_VALUE (((1U << LPI2C_MCCR0_CLKHI_WIDTH) - 1U) >> 1U)
104 #define CLKLO_MAX_VALUE (CLKHI_MAX_VALUE << 1U)
105 #define DATAVD_MIN_VALUE 1U
106 #define SETHOLD_MIN_VALUE 2U
133 } lpi2c_transfer_direction_t;
146 uint32_t i2cDataRegAddr;
147 uint8_t *bufferTransfer;
148 uint32_t transferSize;
149 lpi2c_transfer_direction_t transferDirection;
169 return (master->cmdQueue.writeIdx == master->cmdQueue.readIdx);
183 master->cmdQueue.readIdx = 0U;
184 master->cmdQueue.writeIdx = 0U;
196 lpi2c_master_command_t cmd,
202 uint16_t txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
203 uint16_t txFIFOSize = LPI2C_Get_MasterTxFIFOSize(baseAddr);
206 if (txFIFOCount < txFIFOSize)
208 LPI2C_Cmd_MasterTransmit(baseAddr, cmd, data);
213 DEV_ASSERT(master->cmdQueue.writeIdx < LPI2C_MASTER_CMD_QUEUE_SIZE);
215 master->cmdQueue.cmd[master->cmdQueue.writeIdx] = cmd;
216 master->cmdQueue.data[master->cmdQueue.writeIdx] = data;
217 master->cmdQueue.writeIdx++;
233 uint16_t txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
234 uint16_t txFifoSize = LPI2C_Get_MasterTxFIFOSize(baseAddr);
238 LPI2C_Cmd_MasterTransmit(baseAddr,
239 master->cmdQueue.cmd[master->cmdQueue.readIdx],
240 master->cmdQueue.data[master->cmdQueue.readIdx]);
241 master->cmdQueue.readIdx++;
243 txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
266 lpi2c_master_command_t startCommand;
271 #if(LPI2C_HAS_HIGH_SPEED_MODE)
272 if ((master->operatingMode == LPI2C_HIGHSPEED_MODE) && (master->highSpeedInProgress ==
false))
276 master->highSpeedInProgress =
true;
279 if (master->highSpeedInProgress ==
true)
282 startCommand = LPI2C_MASTER_COMMAND_START_HS;
288 startCommand = LPI2C_MASTER_COMMAND_START;
291 if (master->is10bitAddr)
295 addrByte = (uint8_t)(0xF0U + ((master->slaveAddress >> 7U) & 0x6U) + (uint8_t)0U);
298 addrByte = (uint8_t)(master->slaveAddress & 0xFFU);
304 addrByte = (uint8_t)(0xF0U + ((master->slaveAddress >> 7U) & 0x6U) + (uint8_t)1U);
312 addrByte = (uint8_t)((master->slaveAddress << 1U) + (uint8_t)receive);
330 uint16_t txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
331 uint16_t txFifoSize = LPI2C_Get_MasterTxFIFOSize(baseAddr);
336 while ((master->txSize > 0U) && (txFIFOCount < txFifoSize))
338 LPI2C_Cmd_MasterTransmit(baseAddr, LPI2C_MASTER_COMMAND_TRANSMIT, master->txBuff[0U]);
342 txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
363 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
364 LPI2C_MASTER_ARBITRATION_LOST_INT |
365 LPI2C_MASTER_NACK_DETECT_INT |
366 LPI2C_MASTER_TRANSMIT_DATA_INT |
367 LPI2C_MASTER_RECEIVE_DATA_INT,
370 if (resetFIFO ==
true)
373 LPI2C_Reset_MasterTxFIFOCmd(baseAddr);
374 LPI2C_Reset_MasterRxFIFOCmd(baseAddr);
378 if (sendStop ==
true)
380 LPI2C_Cmd_MasterTransmit(baseAddr, LPI2C_MASTER_COMMAND_STOP, 0U);
381 #if(LPI2C_HAS_HIGH_SPEED_MODE)
382 master->highSpeedInProgress =
false;
389 if (master->rxSize != (uint16_t)0)
391 (void)LPI2C_Set_MasterRxDMA(baseAddr,
false);
395 (void)LPI2C_Set_MasterTxDMA(baseAddr,
false);
399 master->txBuff = NULL;
401 master->rxBuff = NULL;
403 master->i2cIdle =
true;
421 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
422 LPI2C_SLAVE_FIFO_ERROR_INT |
423 LPI2C_SLAVE_STOP_DETECT_INT |
424 LPI2C_SLAVE_REPEATED_START_INT |
425 LPI2C_SLAVE_ADDRESS_VALID_INT |
426 LPI2C_SLAVE_RECEIVE_DATA_INT |
427 LPI2C_SLAVE_TRANSMIT_DATA_INT,
433 if (slave->rxSize != (uint16_t)0)
435 (void)LPI2C_Set_SlaveRxDMA(baseAddr,
false);
439 (void)LPI2C_Set_SlaveTxDMA(baseAddr,
false);
444 LPI2C_Set_SlaveEnable(baseAddr,
false);
446 slave->isTransferInProgress =
false;
447 slave->rxBuff = NULL;
449 slave->txBuff = NULL;
451 slave->repeatedStarts = 0U;
466 baseAddr = g_lpi2cBase[instance];
467 master = g_lpi2cMasterStatePtr[instance];
470 #if(LPI2C_HAS_ULTRA_FAST_MODE)
471 if (operatingMode == LPI2C_ULTRAFAST_MODE)
473 LPI2C_Set_MasterPinConfig(baseAddr, LPI2C_CFG_2PIN_OUTPUT_ONLY);
474 LPI2C_Set_MasterNACKConfig(baseAddr, LPI2C_NACK_IGNORE);
479 LPI2C_Set_MasterPinConfig(baseAddr, LPI2C_CFG_2PIN_OPEN_DRAIN);
480 LPI2C_Set_MasterNACKConfig(baseAddr, LPI2C_NACK_RECEIVE);
483 master->operatingMode = operatingMode;
498 baseAddr = g_lpi2cBase[instance];
499 slave = g_lpi2cSlaveStatePtr[instance];
502 #if(LPI2C_HAS_ULTRA_FAST_MODE)
503 if (operatingMode == LPI2C_ULTRAFAST_MODE)
505 LPI2C_Set_SlaveIgnoreNACK(baseAddr, LPI2C_SLAVE_NACK_CONTINUE_TRANSFER);
506 LPI2C_Set_SlaveTransmitNACK(baseAddr, LPI2C_SLAVE_TRANSMIT_NACK);
508 LPI2C_Set_SlaveACKStall(baseAddr,
false);
509 LPI2C_Set_SlaveTXDStall(baseAddr,
false);
510 LPI2C_Set_SlaveRXStall(baseAddr,
false);
511 LPI2C_Set_SlaveAddrStall(baseAddr,
false);
516 LPI2C_Set_SlaveIgnoreNACK(baseAddr, LPI2C_SLAVE_NACK_END_TRANSFER);
517 LPI2C_Set_SlaveTransmitNACK(baseAddr, LPI2C_SLAVE_TRANSMIT_ACK);
519 LPI2C_Set_SlaveACKStall(baseAddr,
false);
520 LPI2C_Set_SlaveTXDStall(baseAddr,
true);
521 LPI2C_Set_SlaveRXStall(baseAddr,
true);
522 LPI2C_Set_SlaveAddrStall(baseAddr,
true);
525 #if(LPI2C_HAS_HIGH_SPEED_MODE)
526 if (operatingMode == LPI2C_HIGHSPEED_MODE)
529 LPI2C_Set_SlaveHighSpeedModeDetect(baseAddr,
true);
535 LPI2C_Set_SlaveHighSpeedModeDetect(baseAddr,
false);
538 slave->operatingMode = operatingMode;
551 if (dmaTransParams->transferDirection == LPI2C_TX_REQ)
556 (uint32_t)dmaTransParams->transferSize,
false);
563 (uint32_t)dmaTransParams->transferSize,
false);
579 bool receive =
false;
581 dmaTransParams.dmaChannel = master->dmaChannel;
582 if (master->txSize > 0U)
585 uint32_t txBytes = LPI2C_Get_MasterTxFIFOSize(baseAddr);
586 if (txBytes > master->txSize)
588 txBytes = master->txSize;
590 LPI2C_Set_MasterTxFIFOWatermark(baseAddr, (uint16_t)(txBytes - 1U));
593 dmaTransParams.i2cDataRegAddr = (uint32_t)(&(baseAddr->
MTDR));
594 dmaTransParams.bufferTransfer = (uint8_t *)master->txBuff;
595 dmaTransParams.transferDirection = LPI2C_TX_REQ;
596 dmaTransParams.transferSize = master->txSize;
602 LPI2C_Set_MasterRxFIFOWatermark(baseAddr, 0U);
607 dmaTransParams.i2cDataRegAddr = (uint32_t)(&(baseAddr->
MRDR));
608 dmaTransParams.bufferTransfer = master->rxBuff;
609 dmaTransParams.transferDirection = LPI2C_RX_REQ;
610 dmaTransParams.transferSize = master->rxSize;
627 if (master->txSize > (uint32_t)0U)
629 (void)LPI2C_Set_MasterTxDMA(baseAddr,
true);
634 (void)LPI2C_Set_MasterRxDMA(baseAddr,
true);
651 if (slave->txSize > (uint32_t)0U)
653 dmaTransParams.dmaChannel = slave->dmaChannel;
655 dmaTransParams.i2cDataRegAddr = (uint32_t)(&(baseAddr->
STDR));
656 dmaTransParams.bufferTransfer = (uint8_t*)slave->txBuff;
657 dmaTransParams.transferDirection = LPI2C_TX_REQ;
658 dmaTransParams.transferSize = slave->txSize;
662 dmaTransParams.dmaChannel = slave->dmaChannel;
664 dmaTransParams.i2cDataRegAddr = (uint32_t)(&(baseAddr->
SRDR));
665 dmaTransParams.bufferTransfer = slave->rxBuff;
666 dmaTransParams.transferDirection = LPI2C_RX_REQ;
667 dmaTransParams.transferSize = slave->rxSize;
678 if (slave->txSize > (uint32_t)0U)
680 (void)LPI2C_Set_SlaveTxDMA(baseAddr,
true);
684 (void)LPI2C_Set_SlaveRxDMA(baseAddr,
true);
704 uint32_t instance = (uint32_t)parameter;
706 baseAddr = g_lpi2cBase[instance];
707 master = g_lpi2cMasterStatePtr[instance];
709 if(master->txSize > 0U)
713 LPI2C_Set_MasterTxFIFOWatermark(baseAddr, 0U);
716 (void)LPI2C_Set_MasterTxDMA(baseAddr,
false);
719 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_TRANSMIT_DATA_INT,
true);
726 if (master->blocking ==
true)
748 baseAddr = g_lpi2cBase[instance];
749 master = g_lpi2cMasterStatePtr[instance];
752 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
761 master->blocking =
false;
762 return master->status;
778 baseAddr = g_lpi2cBase[instance];
779 slave = g_lpi2cSlaveStatePtr[instance];
791 slave->blocking =
false;
792 return slave->status;
810 else if (master->txBuff != NULL)
813 if (master->txSize == 0U)
819 if (master->blocking ==
true)
826 if (master->masterCallback != NULL)
840 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_TRANSMIT_DATA_INT,
false);
857 while ((LPI2C_Get_MasterRxFIFOCount(baseAddr) > 0U) && (master->rxSize > 0U))
859 master->rxBuff[0U] = LPI2C_Get_MasterRxData(baseAddr);
863 if (master->rxSize == 0U)
869 if (master->blocking ==
true)
876 if (master->masterCallback != NULL)
881 else if (master->rxSize <= LPI2C_Get_MasterRxFIFOWatermark(baseAddr))
884 LPI2C_Set_MasterRxFIFOWatermark(baseAddr, (uint16_t)(master->rxSize - 1U));
901 uint16_t receivedAddr;
903 receivedAddr = LPI2C_Get_SlaveReceivedAddr(baseAddr);
904 if ((receivedAddr & 1U) != (uint16_t)0U)
907 if ((slave->slaveCallback != NULL) && slave->slaveListening)
912 #if defined(ERRATA_E10792)
915 LPI2C_Set_SlaveInt(g_lpi2cBase[instance], LPI2C_SLAVE_TRANSMIT_DATA_INT,
true);
919 slave->txUnderrunWarning =
false;
930 if ((slave->slaveCallback != NULL) && slave->slaveListening)
953 if (slave->txUnderrunWarning ==
true)
959 if (slave->txSize == 0U)
962 if (slave->slaveCallback != NULL)
968 if (slave->txSize == 0U)
976 slave->txUnderrunWarning =
true;
977 LPI2C_Transmit_SlaveData(baseAddr, (uint8_t)0xFFU);
981 LPI2C_Transmit_SlaveData(baseAddr, slave->txBuff[0U]);
996 if (slave->rxSize == 0U)
999 if (slave->slaveCallback != NULL)
1005 if (slave->rxSize == 0U)
1009 (void)LPI2C_Get_SlaveData(baseAddr);
1013 slave->rxBuff[0U] = LPI2C_Get_SlaveData(baseAddr);
1038 uint32_t inputClock;
1046 DEV_ASSERT(g_lpi2cMasterStatePtr[instance] == NULL);
1053 baseAddr = g_lpi2cBase[instance];
1054 g_lpi2cMasterStatePtr[instance] = master;
1057 master->rxBuff = NULL;
1058 master->rxSize = 0U;
1059 master->txBuff = NULL;
1060 master->txSize = 0U;
1062 master->i2cIdle =
true;
1067 master->dmaChannel = userConfigPtr->
dmaChannel;
1070 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1071 master->masterCode = userConfigPtr->masterCode;
1072 master->highSpeedInProgress =
false;
1074 master->blocking =
false;
1086 LPI2C_Init(baseAddr);
1090 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1091 baudRate.baudRateHS = userConfigPtr->baudRateHS;
1099 LPI2C_Set_MasterEnable(baseAddr,
true);
1121 baseAddr = g_lpi2cBase[instance];
1122 master = g_lpi2cMasterStatePtr[instance];
1128 g_lpi2cMasterStatePtr[instance] = NULL;
1131 LPI2C_Set_MasterEnable(baseAddr,
false);
1155 uint32_t inputClock;
1159 baseAddr = g_lpi2cBase[instance];
1160 master = g_lpi2cMasterStatePtr[instance];
1171 prescaler = LPI2C_Get_MasterPrescaler(baseAddr);
1172 clkHi =LPI2C_Get_MasterClockHighPeriod(baseAddr);
1173 clkLo = LPI2C_Get_MasterClockLowPeriod(baseAddr);
1175 baudRate->
baudRate = inputClock / (((uint32_t)1U << prescaler) * (clkLo + clkHi + (uint32_t)2U));
1177 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1178 if (master->operatingMode == LPI2C_HIGHSPEED_MODE)
1180 clkHi =LPI2C_Get_MasterClockHighPeriodHS(baseAddr);
1181 clkLo = LPI2C_Get_MasterClockLowPeriodHS(baseAddr);
1183 baudRate->baudRateHS = inputClock / (((uint32_t)1U << prescaler) * (clkLo + clkHi + (uint32_t)2U));
1206 uint32_t inputClock;
1207 uint32_t minPrescaler;
1217 baseAddr = g_lpi2cBase[instance];
1218 master = g_lpi2cMasterStatePtr[instance];
1230 LPI2C_Set_MasterEnable(baseAddr,
false);
1237 minPrescaler = ((inputClock - 1U) / (baudRate.
baudRate * (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U))) + (uint32_t)1U;
1238 for (prescaler = 0U; prescaler < 7U; prescaler++)
1240 if (((uint32_t)1U << prescaler) >= minPrescaler)
1247 clkTotal = (inputClock + ((baudRate.
baudRate << prescaler) >> 1U)) / (baudRate.
baudRate << prescaler);
1248 if (clkTotal > (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U))
1250 clkTotal = (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U);
1265 clkHi = (clkTotal - 2U) / 3U;
1266 clkLo = clkTotal - 2U - clkHi;
1269 if (clkHi < CLKHI_MIN_VALUE)
1271 clkHi = CLKHI_MIN_VALUE;
1273 if (clkLo < CLKLO_MIN_VALUE)
1275 clkLo = CLKLO_MIN_VALUE;
1280 dataVd = clkHi >> 1U;
1281 if (setHold < SETHOLD_MIN_VALUE)
1283 setHold = SETHOLD_MIN_VALUE;
1285 if (dataVd < DATAVD_MIN_VALUE)
1287 dataVd = DATAVD_MIN_VALUE;
1291 LPI2C_Set_MasterPrescaler(baseAddr, (lpi2c_master_prescaler_t)prescaler);
1292 LPI2C_Set_MasterDataValidDelay(baseAddr, (uint8_t)dataVd);
1293 LPI2C_Set_MasterSetupHoldDelay(baseAddr, (uint8_t)setHold);
1294 LPI2C_Set_MasterClockHighPeriod(baseAddr, (uint8_t)clkHi);
1295 LPI2C_Set_MasterClockLowPeriod(baseAddr, (uint8_t)clkLo);
1297 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1298 if (operatingMode == LPI2C_HIGHSPEED_MODE)
1302 clkTotal = (inputClock + ((baudRate.baudRateHS << prescaler) >> 1U)) / (baudRate.baudRateHS << prescaler);
1303 if (clkTotal > (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U))
1305 clkTotal = (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U);
1308 clkHi = (clkTotal - 2U) / 3U;
1309 clkLo = clkTotal - 2U - clkHi;
1310 if (clkHi < CLKHI_MIN_VALUE)
1312 clkHi = CLKHI_MIN_VALUE;
1314 if (clkLo < CLKLO_MIN_VALUE)
1316 clkLo = CLKLO_MIN_VALUE;
1321 dataVd = clkHi >> 1U;
1322 if (setHold < SETHOLD_MIN_VALUE)
1324 setHold = SETHOLD_MIN_VALUE;
1326 if (dataVd < DATAVD_MIN_VALUE)
1328 dataVd = DATAVD_MIN_VALUE;
1332 LPI2C_Set_MasterDataValidDelayHS(baseAddr, (uint8_t)dataVd);
1333 LPI2C_Set_MasterSetupHoldDelayHS(baseAddr, (uint8_t)setHold);
1334 LPI2C_Set_MasterClockHighPeriodHS(baseAddr, (uint8_t)clkHi);
1335 LPI2C_Set_MasterClockLowPeriodHS(baseAddr, (uint8_t)clkLo);
1343 LPI2C_Set_MasterEnable(baseAddr,
true);
1363 master = g_lpi2cMasterStatePtr[instance];
1366 master->slaveAddress = address;
1367 master->is10bitAddr = is10bitAddr;
1379 const uint8_t * txBuff,
1390 baseAddr = g_lpi2cBase[instance];
1391 master = g_lpi2cMasterStatePtr[instance];
1398 master->txBuff = txBuff;
1399 master->txSize = txSize;
1400 master->sendStop = sendStop;
1401 master->i2cIdle =
false;
1406 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1407 LPI2C_MASTER_ARBITRATION_LOST_INT |
1408 LPI2C_MASTER_NACK_DETECT_INT,
1422 LPI2C_Set_MasterTxFIFOWatermark(baseAddr, 0U);
1425 #if(LPI2C_HAS_ULTRA_FAST_MODE)
1426 if (master->operatingMode == LPI2C_ULTRAFAST_MODE)
1429 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1430 LPI2C_MASTER_ARBITRATION_LOST_INT |
1431 LPI2C_MASTER_TRANSMIT_DATA_INT,
1437 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1438 LPI2C_MASTER_ARBITRATION_LOST_INT |
1439 LPI2C_MASTER_NACK_DETECT_INT |
1440 LPI2C_MASTER_TRANSMIT_DATA_INT,
1457 const uint8_t * txBuff,
1472 master->blocking =
true;
1477 master->blocking =
false;
1500 baseAddr = g_lpi2cBase[instance];
1501 master = g_lpi2cMasterStatePtr[instance];
1506 if (master->rxBuff != NULL)
1543 baseAddr = g_lpi2cBase[instance];
1544 master = g_lpi2cMasterStatePtr[instance];
1550 #if(LPI2C_HAS_ULTRA_FAST_MODE)
1551 if (master->operatingMode == LPI2C_ULTRAFAST_MODE)
1559 master->rxSize = rxSize;
1560 master->i2cIdle =
false;
1561 master->sendStop = sendStop;
1562 master->rxBuff = rxBuff;
1567 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1568 LPI2C_MASTER_ARBITRATION_LOST_INT |
1569 LPI2C_MASTER_NACK_DETECT_INT,
1582 rxBytes = LPI2C_Get_MasterRxFIFOSize(baseAddr);
1583 if (rxBytes > rxSize)
1585 rxBytes = (uint8_t)rxSize;
1587 LPI2C_Set_MasterRxFIFOWatermark(baseAddr, (uint16_t)(rxBytes - 1U));
1593 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1594 LPI2C_MASTER_ARBITRATION_LOST_INT |
1595 LPI2C_MASTER_NACK_DETECT_INT |
1596 LPI2C_MASTER_TRANSMIT_DATA_INT |
1597 LPI2C_MASTER_RECEIVE_DATA_INT,
1602 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1603 LPI2C_MASTER_ARBITRATION_LOST_INT |
1604 LPI2C_MASTER_NACK_DETECT_INT |
1605 LPI2C_MASTER_RECEIVE_DATA_INT,
1637 master->blocking =
true;
1642 master->blocking =
false;
1663 uint32_t *bytesRemaining)
1670 baseAddr = g_lpi2cBase[instance];
1671 master = g_lpi2cMasterStatePtr[instance];
1676 if (master->txSize > 0U)
1680 *bytesRemaining = master->txSize + LPI2C_Get_MasterTxFIFOCount(baseAddr);
1682 else if (master->rxSize > 0U)
1686 *bytesRemaining = master->rxSize - LPI2C_Get_MasterRxFIFOCount(baseAddr);
1690 *bytesRemaining = 0U;
1694 return master->status;
1711 baseAddr = g_lpi2cBase[instance];
1712 master = g_lpi2cMasterStatePtr[instance];
1716 if (LPI2C_Get_MasterTransmitDataRequestEvent(baseAddr))
1721 if (LPI2C_Get_MasterReceiveDataReadyEvent(baseAddr))
1726 if (LPI2C_Get_MasterFIFOErrorEvent(baseAddr))
1729 LPI2C_Clear_MasterFIFOErrorEvent(baseAddr);
1731 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1733 master->highSpeedInProgress =
false;
1742 if (master->blocking ==
true)
1747 if (master->masterCallback != NULL)
1753 if (LPI2C_Get_MasterArbitrationLostEvent(baseAddr))
1756 LPI2C_Clear_MasterArbitrationLostEvent(baseAddr);
1763 if (master->blocking ==
true)
1770 if (master->masterCallback != NULL)
1776 if (LPI2C_Get_MasterNACKDetectEvent(baseAddr))
1779 LPI2C_Clear_MasterNACKDetectEvent(baseAddr);
1781 #if(LPI2C_HAS_ULTRA_FAST_MODE)
1783 if (master->operatingMode != LPI2C_ULTRAFAST_MODE)
1787 if (master->blocking ==
true)
1792 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1794 master->highSpeedInProgress =
false;
1802 if (master->masterCallback != NULL)
1806 #if(LPI2C_HAS_ULTRA_FAST_MODE)
1826 uint32_t inputClock;
1832 DEV_ASSERT(g_lpi2cSlaveStatePtr[instance] == NULL);
1842 baseAddr = g_lpi2cBase[instance];
1843 g_lpi2cSlaveStatePtr[instance] = slave;
1850 slave->txBuff = NULL;
1851 slave->rxBuff = NULL;
1856 slave->dmaChannel = userConfigPtr->
dmaChannel;
1857 slave->isTransferInProgress =
false;
1858 slave->blocking =
false;
1859 slave->is10bitAddress = userConfigPtr->
is10bitAddr;
1860 slave->repeatedStarts = 0U;
1870 LPI2C_Init(baseAddr);
1873 LPI2C_Set_SlaveAddr0(baseAddr, userConfigPtr->
slaveAddress);
1876 LPI2C_Set_SlaveAddrConfig(baseAddr, LPI2C_SLAVE_ADDR_MATCH_0_10BIT);
1880 LPI2C_Set_SlaveAddrConfig(baseAddr, LPI2C_SLAVE_ADDR_MATCH_0_7BIT);
1891 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
1892 LPI2C_SLAVE_FIFO_ERROR_INT |
1893 LPI2C_SLAVE_STOP_DETECT_INT |
1894 LPI2C_SLAVE_REPEATED_START_INT |
1895 LPI2C_SLAVE_ADDRESS_VALID_INT,
1901 #if defined(ERRATA_E10792)
1902 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
1903 LPI2C_SLAVE_FIFO_ERROR_INT |
1904 LPI2C_SLAVE_STOP_DETECT_INT |
1905 LPI2C_SLAVE_REPEATED_START_INT |
1906 LPI2C_SLAVE_ADDRESS_VALID_INT |
1907 LPI2C_SLAVE_RECEIVE_DATA_INT,
1911 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
1912 LPI2C_SLAVE_FIFO_ERROR_INT |
1913 LPI2C_SLAVE_STOP_DETECT_INT |
1914 LPI2C_SLAVE_REPEATED_START_INT |
1915 LPI2C_SLAVE_ADDRESS_VALID_INT |
1916 LPI2C_SLAVE_RECEIVE_DATA_INT |
1917 LPI2C_SLAVE_TRANSMIT_DATA_INT,
1925 LPI2C_Set_SlaveEnable(baseAddr,
true);
1947 baseAddr = g_lpi2cBase[instance];
1954 if ((slave->transferType ==
LPI2C_USING_DMA) && slave->slaveListening)
1957 (void)LPI2C_Set_SlaveRxDMA(baseAddr,
false);
1958 (void)LPI2C_Set_SlaveTxDMA(baseAddr,
false);
1961 g_lpi2cSlaveStatePtr[instance] = NULL;
1964 LPI2C_Set_SlaveEnable(baseAddr,
false);
1981 const uint8_t * txBuff,
1990 slave = g_lpi2cSlaveStatePtr[instance];
1993 slave->txBuff = txBuff;
1994 slave->txSize = txSize;
2017 slave = g_lpi2cSlaveStatePtr[instance];
2020 slave->rxBuff = rxBuff;
2021 slave->rxSize = rxSize;
2035 const uint8_t * txBuff,
2046 baseAddr = g_lpi2cBase[instance];
2047 slave = g_lpi2cSlaveStatePtr[instance];
2054 DEV_ASSERT(slave->isTransferInProgress ==
false);
2056 slave->txBuff = txBuff;
2057 slave->txSize = txSize;
2063 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2064 LPI2C_SLAVE_FIFO_ERROR_INT |
2065 LPI2C_SLAVE_STOP_DETECT_INT |
2066 LPI2C_SLAVE_REPEATED_START_INT |
2067 LPI2C_SLAVE_ADDRESS_VALID_INT,
2071 LPI2C_Set_SlaveEnable(baseAddr,
true);
2073 slave->isTransferInProgress =
true;
2080 #if defined(ERRATA_E10792)
2082 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2083 LPI2C_SLAVE_FIFO_ERROR_INT |
2084 LPI2C_SLAVE_STOP_DETECT_INT |
2085 LPI2C_SLAVE_REPEATED_START_INT |
2086 LPI2C_SLAVE_ADDRESS_VALID_INT,
2090 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2091 LPI2C_SLAVE_FIFO_ERROR_INT |
2092 LPI2C_SLAVE_STOP_DETECT_INT |
2093 LPI2C_SLAVE_REPEATED_START_INT |
2094 LPI2C_SLAVE_ADDRESS_VALID_INT |
2095 LPI2C_SLAVE_TRANSMIT_DATA_INT,
2101 LPI2C_Set_SlaveEnable(baseAddr,
true);
2103 slave->isTransferInProgress =
true;
2118 const uint8_t * txBuff,
2132 slave->blocking =
true;
2163 baseAddr = g_lpi2cBase[instance];
2164 slave = g_lpi2cSlaveStatePtr[instance];
2171 DEV_ASSERT(slave->isTransferInProgress ==
false);
2173 slave->rxBuff = rxBuff;
2174 slave->rxSize = rxSize;
2180 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2181 LPI2C_SLAVE_FIFO_ERROR_INT |
2182 LPI2C_SLAVE_STOP_DETECT_INT |
2183 LPI2C_SLAVE_REPEATED_START_INT |
2184 LPI2C_SLAVE_ADDRESS_VALID_INT,
2188 LPI2C_Set_SlaveEnable(baseAddr,
true);
2190 slave->isTransferInProgress =
true;
2196 slave->isTransferInProgress =
true;
2199 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2200 LPI2C_SLAVE_FIFO_ERROR_INT |
2201 LPI2C_SLAVE_STOP_DETECT_INT |
2202 LPI2C_SLAVE_REPEATED_START_INT |
2203 LPI2C_SLAVE_ADDRESS_VALID_INT |
2204 LPI2C_SLAVE_RECEIVE_DATA_INT,
2208 LPI2C_Set_SlaveEnable(baseAddr,
true);
2237 slave->blocking =
true;
2262 uint32_t *bytesRemaining)
2268 slave = g_lpi2cSlaveStatePtr[instance];
2273 if (slave->txSize > 0U)
2276 *bytesRemaining = slave->txSize;
2278 else if (slave->rxSize > 0U)
2281 *bytesRemaining = slave->rxSize;
2285 *bytesRemaining = 0U;
2289 return slave->status;
2307 baseAddr = g_lpi2cBase[instance];
2308 slave = g_lpi2cSlaveStatePtr[instance];
2311 if (!slave->slaveListening)
2313 DEV_ASSERT(slave->isTransferInProgress ==
true);
2333 bool stopDetect =
false, repeatStartDetect =
false;
2337 baseAddr = g_lpi2cBase[instance];
2338 slave = g_lpi2cSlaveStatePtr[instance];
2342 if (LPI2C_Get_SlaveAddressValidEvent(baseAddr))
2348 if (LPI2C_Get_SlaveTransmitDataEvent(baseAddr))
2350 if (LPI2C_Get_SlaveInt(baseAddr, LPI2C_SLAVE_TRANSMIT_DATA_INT))
2356 if (LPI2C_Get_SlaveReceiveDataEvent(baseAddr))
2358 if (LPI2C_Get_SlaveInt(baseAddr, LPI2C_SLAVE_RECEIVE_DATA_INT))
2364 stopDetect = LPI2C_Get_SlaveSTOPDetectEvent(baseAddr);
2365 repeatStartDetect = LPI2C_Get_SlaveRepeatedStartEvent(baseAddr);
2367 if (repeatStartDetect)
2369 slave->repeatedStarts++;
2371 if ((slave->repeatedStarts == 1U) && (slave->is10bitAddress))
2373 repeatStartDetect =
false;
2374 LPI2C_Clear_SlaveRepeatedStartEvent(baseAddr);
2379 if ((stopDetect ==
true) || (repeatStartDetect ==
true))
2382 LPI2C_Clear_SlaveSTOPDetectEvent(baseAddr);
2383 LPI2C_Clear_SlaveRepeatedStartEvent(baseAddr);
2385 #if defined(ERRATA_E10792)
2387 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_TRANSMIT_DATA_INT,
false);
2401 if ((!slave->slaveListening))
2406 if (slave->blocking ==
true)
2412 if(slave->slaveCallback != NULL)
2418 if (LPI2C_Get_SlaveBitErrorEvent(baseAddr))
2421 LPI2C_Clear_SlaveBitErrorEvent(baseAddr);
2423 #if defined(ERRATA_E10792)
2425 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_TRANSMIT_DATA_INT,
false);
2432 if (!slave->slaveListening){
2437 if (slave->blocking ==
true)
2443 if(slave->slaveCallback != NULL)
2449 if (LPI2C_Get_SlaveFIFOErrorEvent(baseAddr))
2454 LPI2C_Clear_SlaveFIFOErrorEvent(baseAddr);
2456 #if defined(ERRATA_E10792)
2458 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_TRANSMIT_DATA_INT,
false);
2465 if (!slave->slaveListening)
2470 if (slave->blocking ==
true)
2476 if(slave->slaveCallback != NULL)
2483 #if defined(S32K11x_SERIES)
2489 if (g_lpi2cSlaveStatePtr[instance] == NULL)
static void LPI2C_DRV_SlaveSetOperatingMode(uint32_t instance, lpi2c_mode_t operatingMode)
status_t LPI2C_DRV_SlaveGetTransferStatus(uint32_t instance, uint32_t *bytesRemaining)
Return the current status of the I2C slave transfer.
static void LPI2C_DRV_MasterEndTransfer(LPI2C_Type *baseAddr, lpi2c_master_state_t *master, bool sendStop, bool resetFIFO)
static void LPI2C_DRV_SlaveHandleTransmitDataEvent(LPI2C_Type *baseAddr, lpi2c_slave_state_t *slave)
volatile const uint32_t MRDR
lpi2c_mode_t operatingMode
status_t EDMA_DRV_InstallCallback(uint8_t virtualChannel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
status_t LPI2C_DRV_MasterGetTransferStatus(uint32_t instance, uint32_t *bytesRemaining)
Return the current status of the I2C master transfer.
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
status_t LPI2C_DRV_MasterAbortTransferData(uint32_t instance)
Abort a non-blocking I2C Master transmission or reception.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t virtualChannel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
edma_transfer_type_t
A type for the DMA transfer. Implements : edma_transfer_type_t_Class.
static void LPI2C_DRV_MasterQueueCmd(LPI2C_Type *baseAddr, lpi2c_master_state_t *master, lpi2c_master_command_t cmd, uint8_t data)
static bool LPI2C_DRV_MasterCmdQueueEmpty(const lpi2c_master_state_t *master)
static status_t LPI2C_DRV_SlaveWaitTransferEnd(uint32_t instance, uint32_t timeout)
lpi2c_transfer_type_t transferType
static void LPI2C_DRV_MasterQueueData(LPI2C_Type *baseAddr, lpi2c_master_state_t *master)
static void LPI2C_DRV_SlaveStartDmaTransfer(uint32_t instance)
status_t LPI2C_DRV_SlaveReceiveData(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking receive transaction on the I2C bus.
static void LPI2C_DRV_SlaveHandleAddressValidEvent(uint32_t instance, const LPI2C_Type *baseAddr, lpi2c_slave_state_t *slave)
static void LPI2C_DRV_MasterSendQueuedCmd(LPI2C_Type *baseAddr, lpi2c_master_state_t *master)
void EDMA_DRV_SetSrcLastAddrAdjustment(uint8_t virtualChannel, int32_t adjust)
Configures the source address last adjustment.
status_t LPI2C_DRV_SlaveSendDataBlocking(uint32_t instance, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking send transaction on the I2C bus.
static void LPI2C_DRV_MasterHandleTransmitDataRequest(LPI2C_Type *baseAddr, lpi2c_master_state_t *master)
i2c_master_callback_t masterCallback
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
static void LPI2C_DRV_MasterCompleteDMATransfer(void *parameter, edma_chn_status_t status)
lpi2c_transfer_type_t transferType
lpi2c_mode_t
I2C operating modes Implements : lpi2c_mode_t_Class.
void LPI2C_DRV_MasterSetSlaveAddr(uint32_t instance, const uint16_t address, const bool is10bitAddr)
Set the slave address for any subsequent I2C communication.
#define LPI2C_MASTER_IRQS
status_t LPI2C_DRV_SlaveSetRxBuffer(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
static void LPI2C_DRV_ConfigureDmaTransfer(uint32_t instance, const lpi2c_dma_transfer_params_t *dmaTransParams)
status_t EDMA_DRV_StopChannel(uint8_t virtualChannel)
Stops the eDMA channel.
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
void LPI2C_DRV_MasterGetBaudRate(uint32_t instance, lpi2c_baud_rate_params_t *baudRate)
Get the currently configured baud rate.
status_t LPI2C_DRV_MasterReceiveDataBlocking(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize, bool sendStop, uint32_t timeout)
Perform a blocking receive transaction on the I2C bus.
void EDMA_DRV_DisableRequestsOnTransferComplete(uint8_t virtualChannel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
status_t LPI2C_DRV_MasterSendData(uint32_t instance, const uint8_t *txBuff, uint32_t txSize, bool sendStop)
Perform a non-blocking send transaction on the I2C bus.
static void LPI2C_DRV_MasterResetQueue(lpi2c_master_state_t *master)
status_t LPI2C_DRV_SlaveSetTxBuffer(uint32_t instance, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
edma_chn_status_t
Channel status for eDMA channel.
Slave configuration structure.
Slave internal context structure.
static void LPI2C_DRV_MasterStartDmaTransfer(uint32_t instance)
status_t LPI2C_DRV_SlaveSendData(uint32_t instance, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking send transaction on the I2C bus.
status_t LPI2C_DRV_SlaveAbortTransferData(uint32_t instance)
Abort a non-blocking I2C Master transmission or reception.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
static void LPI2C_DRV_MasterSendAddress(LPI2C_Type *baseAddr, lpi2c_master_state_t *master, bool receive)
void LPI2C_DRV_MasterIRQHandler(uint32_t instance)
Handle master operation when I2C interrupt occurs.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
IRQn_Type
Defines the Interrupt Numbers definitions.
status_t LPI2C_DRV_MasterInit(uint32_t instance, const lpi2c_master_user_config_t *userConfigPtr, lpi2c_master_state_t *master)
Initialize the LPI2C master mode driver.
status_t LPI2C_DRV_MasterDeinit(uint32_t instance)
De-initialize the LPI2C master mode driver.
volatile const uint32_t SRDR
void LPI2C_DRV_SlaveIRQHandler(uint32_t instance)
Handle slave operation when I2C interrupt occurs.
Defines the example structure.
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t LPI2C_DRV_SlaveDeinit(uint32_t instance)
De-initialize the I2C slave mode driver.
static status_t LPI2C_DRV_MasterWaitTransferEnd(uint32_t instance, uint32_t timeout)
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
static void LPI2C_DRV_SlaveHandleReceiveDataEvent(const LPI2C_Type *baseAddr, lpi2c_slave_state_t *slave)
lpi2c_mode_t operatingMode
status_t EDMA_DRV_StartChannel(uint8_t virtualChannel)
Starts an eDMA channel.
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
status_t EDMA_DRV_SetChannelRequest(uint8_t virtualChannel, uint8_t req)
Configures the DMA request for the eDMA channel.
void LPI2C_DRV_MasterSetBaudRate(uint32_t instance, const lpi2c_mode_t operatingMode, const lpi2c_baud_rate_params_t baudRate)
Set the baud rate for any subsequent I2C communication.
lpi2c_dma_transfer_params_t
Master internal context structure.
status_t LPI2C_DRV_MasterReceiveData(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize, bool sendStop)
Perform a non-blocking receive transaction on the I2C bus.
static void LPI2C_DRV_MasterHandleReceiveDataReadyEvent(LPI2C_Type *baseAddr, lpi2c_master_state_t *master)
clock_names_t
Clock names.
status_t LPI2C_DRV_SlaveReceiveDataBlocking(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking receive transaction on the I2C bus.
status_t LPI2C_DRV_SlaveInit(uint32_t instance, const lpi2c_slave_user_config_t *userConfigPtr, lpi2c_slave_state_t *slave)
Initialize the I2C slave mode driver.
static void LPI2C_DRV_MasterSetOperatingMode(uint32_t instance, lpi2c_mode_t operatingMode)
status_t LPI2C_DRV_MasterSendDataBlocking(uint32_t instance, const uint8_t *txBuff, uint32_t txSize, bool sendStop, uint32_t timeout)
Perform a blocking send transaction on the I2C bus.
i2c_slave_callback_t slaveCallback
#define LPI2C_INSTANCE_COUNT
void LPI2C_DRV_ModuleIRQHandler(uint32_t instance)
Handler for both slave and master operation when I2C interrupt occurs.
static void LPI2C_DRV_SlaveEndTransfer(LPI2C_Type *baseAddr, lpi2c_slave_state_t *slave)