#define MPU_CESR_HRL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK) |
#define MPU_CESR_NRGD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK) |
#define MPU_CESR_NSP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK) |
#define MPU_CESR_SPERR0 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR0_SHIFT))&MPU_CESR_SPERR0_MASK) |
#define MPU_CESR_SPERR1 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR1_SHIFT))&MPU_CESR_SPERR1_MASK) |
#define MPU_CESR_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK) |
#define MPU_EAR_EADDR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK) |
#define MPU_EDR_EACD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK) |
#define MPU_EDR_EATTR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK) |
#define MPU_EDR_EMN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK) |
#define MPU_EDR_EPID | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK) |
#define MPU_EDR_ERW | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK) |
#define MPU_RGD_WORD0_SRTADDR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD0_SRTADDR_SHIFT))&MPU_RGD_WORD0_SRTADDR_MASK) |
#define MPU_RGD_WORD1_ENDADDR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD1_ENDADDR_SHIFT))&MPU_RGD_WORD1_ENDADDR_MASK) |
#define MPU_RGD_WORD2_M0PE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0PE_SHIFT))&MPU_RGD_WORD2_M0PE_MASK) |
#define MPU_RGD_WORD2_M0SM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0SM_SHIFT))&MPU_RGD_WORD2_M0SM_MASK) |
#define MPU_RGD_WORD2_M0UM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0UM_SHIFT))&MPU_RGD_WORD2_M0UM_MASK) |
#define MPU_RGD_WORD2_M1SM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1SM_SHIFT))&MPU_RGD_WORD2_M1SM_MASK) |
#define MPU_RGD_WORD2_M1UM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1UM_SHIFT))&MPU_RGD_WORD2_M1UM_MASK) |
#define MPU_RGD_WORD2_M2SM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2SM_SHIFT))&MPU_RGD_WORD2_M2SM_MASK) |
#define MPU_RGD_WORD2_M2UM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2UM_SHIFT))&MPU_RGD_WORD2_M2UM_MASK) |
#define MPU_RGD_WORD2_M3SM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3SM_SHIFT))&MPU_RGD_WORD2_M3SM_MASK) |
#define MPU_RGD_WORD2_M3UM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3UM_SHIFT))&MPU_RGD_WORD2_M3UM_MASK) |
#define MPU_RGD_WORD2_M4RE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4RE_SHIFT))&MPU_RGD_WORD2_M4RE_MASK) |
#define MPU_RGD_WORD2_M4WE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4WE_SHIFT))&MPU_RGD_WORD2_M4WE_MASK) |
#define MPU_RGD_WORD2_M5RE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5RE_SHIFT))&MPU_RGD_WORD2_M5RE_MASK) |
#define MPU_RGD_WORD2_M5WE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5WE_SHIFT))&MPU_RGD_WORD2_M5WE_MASK) |
#define MPU_RGD_WORD2_M6RE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6RE_SHIFT))&MPU_RGD_WORD2_M6RE_MASK) |
#define MPU_RGD_WORD2_M6WE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6WE_SHIFT))&MPU_RGD_WORD2_M6WE_MASK) |
#define MPU_RGD_WORD2_M7RE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7RE_SHIFT))&MPU_RGD_WORD2_M7RE_MASK) |
#define MPU_RGD_WORD2_M7WE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7WE_SHIFT))&MPU_RGD_WORD2_M7WE_MASK) |
#define MPU_RGD_WORD3_PID | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PID_SHIFT))&MPU_RGD_WORD3_PID_MASK) |
#define MPU_RGD_WORD3_PIDMASK | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PIDMASK_SHIFT))&MPU_RGD_WORD3_PIDMASK_MASK) |
#define MPU_RGD_WORD3_VLD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_VLD_SHIFT))&MPU_RGD_WORD3_VLD_MASK) |
#define MPU_RGDAAC_M0PE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK) |
#define MPU_RGDAAC_M0SM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK) |
#define MPU_RGDAAC_M0UM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK) |
#define MPU_RGDAAC_M1SM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK) |
#define MPU_RGDAAC_M1UM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK) |
#define MPU_RGDAAC_M2SM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK) |
#define MPU_RGDAAC_M2UM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK) |
#define MPU_RGDAAC_M3SM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK) |
#define MPU_RGDAAC_M3UM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK) |
#define MPU_RGDAAC_M4RE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK) |
#define MPU_RGDAAC_M4WE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK) |
#define MPU_RGDAAC_M5RE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK) |
#define MPU_RGDAAC_M5WE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK) |
#define MPU_RGDAAC_M6RE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK) |
#define MPU_RGDAAC_M6WE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK) |
#define MPU_RGDAAC_M7RE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK) |
#define MPU_RGDAAC_M7WE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK) |