oc_irq.c
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1 /*
2  * Copyright 2017 -2018 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
32 #include "oc_irq.h"
33 
34 
35 /*******************************************************************************
36  * Code
37  ******************************************************************************/
38 
39 /* Define interrupt handler for the output compare instance */
40 
41 /* Define OC PAL over FTM */
42 #if (defined(OC_PAL_OVER_FTM))
43 
44 #if (OC_PAL_INSTANCES_MAX > 0U)
45 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
46 void FTM0_Ch0_7_IrqHandler(void)
47 {
48  const FTM_Type * const base = g_ftmBase[0];
49  bool chanIntFlag;
50  uint8_t index;
51 
52  for (index = 0U; index < OC_PAL_NUM_OF_CHANNEL_MAX;index++)
53  {
54  chanIntFlag = FTM_DRV_GetChnEventStatus(base, index);
55  if (chanIntFlag)
56  {
57  OC_IrqHandler(0U, index);
58  }
59  }
60 }
61 #else
62 void FTM0_Ch0_Ch1_IrqHandler(void)
63 {
64  const FTM_Type * const base = g_ftmBase[0];
65  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(0U);
66  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
67  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
68  bool chan0EnabledInt = ((enabledInterrupts & (1UL << 0U)) != 0U) ? true : false;
69  bool chan1EnabledInt = ((enabledInterrupts & (1UL << 1U)) != 0U) ? true : false;
70 
71  if (chan0EnabledInt && chan0IntFlag)
72  {
73  OC_IrqHandler(0U, 0U);
74  }
75 
76  if (chan1EnabledInt && chan1IntFlag)
77  {
78  OC_IrqHandler(0U, 1U);
79  }
80 }
81 
82 void FTM0_Ch2_Ch3_IrqHandler(void)
83 {
84  const FTM_Type * const base = g_ftmBase[0];
85  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(0U);
86  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
87  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
88  bool chan2EnabledInt = ((enabledInterrupts & (1UL << 2U)) != 0U) ? true : false;
89  bool chan3EnabledInt = ((enabledInterrupts & (1UL << 3U)) != 0U) ? true : false;
90 
91  if (chan2EnabledInt && chan2IntFlag)
92  {
93  OC_IrqHandler(0U, 2U);
94  }
95 
96  if (chan3EnabledInt && chan3IntFlag)
97  {
98  OC_IrqHandler(0U, 3U);
99  }
100 }
101 
102 void FTM0_Ch4_Ch5_IrqHandler(void)
103 {
104  const FTM_Type * const base = g_ftmBase[0];
105  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(0U);
106  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
107  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
108  bool chan4EnabledInt = ((enabledInterrupts & (1UL << 4U)) != 0U) ? true : false;
109  bool chan5EnabledInt = ((enabledInterrupts & (1UL << 5U)) != 0U) ? true : false;
110 
111  if (chan4EnabledInt && chan4IntFlag)
112  {
113  OC_IrqHandler(0U, 4U);
114  }
115 
116  if (chan5EnabledInt && chan5IntFlag)
117  {
118  OC_IrqHandler(0U, 5U);
119  }
120 }
121 
122 void FTM0_Ch6_Ch7_IrqHandler(void)
123 {
124  const FTM_Type * const base = g_ftmBase[0];
125  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(0U);
126  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
127  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
128  bool chan6EnabledInt = ((enabledInterrupts & (1UL << 6U)) != 0U) ? true : false;
129  bool chan7EnabledInt = ((enabledInterrupts & (1UL << 7U)) != 0U) ? true : false;
130 
131  if (chan6EnabledInt && chan6IntFlag)
132  {
133  OC_IrqHandler(0U, 6U);
134  }
135 
136  if (chan7EnabledInt && chan7IntFlag)
137  {
138  OC_IrqHandler(0U, 7U);
139  }
140 }
141 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
142 #endif /* OC_PAL_INSTANCES_MAX > 0U */
143 
144 #if (OC_PAL_INSTANCES_MAX > 1U)
145 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
146 void FTM1_Ch0_7_IrqHandler(void)
147 {
148  const FTM_Type * const base = g_ftmBase[1];
149  bool chanIntFlag;
150  uint8_t index;
151 
152  for (index = 0U; index < OC_PAL_NUM_OF_CHANNEL_MAX;index++)
153  {
154  chanIntFlag = FTM_DRV_GetChnEventStatus(base, index);
155  if (chanIntFlag)
156  {
157  OC_IrqHandler(1U, index);
158  }
159  }
160 }
161 #else
162 void FTM1_Ch0_Ch1_IrqHandler(void)
163 {
164  const FTM_Type * const base = g_ftmBase[1];
165  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(1U);
166  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
167  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
168  bool chan0EnabledInt = ((enabledInterrupts & (1UL << 0U)) != 0U) ? true : false;
169  bool chan1EnabledInt = ((enabledInterrupts & (1UL << 1U)) != 0U) ? true : false;
170 
171  if (chan0EnabledInt && chan0IntFlag)
172  {
173  OC_IrqHandler(1U, 0U);
174  }
175 
176  if (chan1EnabledInt && chan1IntFlag)
177  {
178  OC_IrqHandler(1U, 1U);
179  }
180 }
181 
182 void FTM1_Ch2_Ch3_IrqHandler(void)
183 {
184  const FTM_Type * const base = g_ftmBase[1];
185  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(1U);
186  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
187  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
188  bool chan2EnabledInt = ((enabledInterrupts & (1UL << 2U)) != 0U) ? true : false;
189  bool chan3EnabledInt = ((enabledInterrupts & (1UL << 3U)) != 0U) ? true : false;
190 
191  if (chan2EnabledInt && chan2IntFlag)
192  {
193  OC_IrqHandler(1U, 2U);
194  }
195 
196  if (chan3EnabledInt && chan3IntFlag)
197  {
198  OC_IrqHandler(1U, 3U);
199  }
200 }
201 
202 void FTM1_Ch4_Ch5_IrqHandler(void)
203 {
204  const FTM_Type * const base = g_ftmBase[1];
205  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(1U);
206  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
207  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
208  bool chan4EnabledInt = ((enabledInterrupts & (1UL << 4U)) != 0U) ? true : false;
209  bool chan5EnabledInt = ((enabledInterrupts & (1UL << 5U)) != 0U) ? true : false;
210 
211  if (chan4EnabledInt && chan4IntFlag)
212  {
213  OC_IrqHandler(1U, 4U);
214  }
215 
216  if (chan5EnabledInt && chan5IntFlag)
217  {
218  OC_IrqHandler(1U, 5U);
219  }
220 }
221 
222 void FTM1_Ch6_Ch7_IrqHandler(void)
223 {
224  const FTM_Type * const base = g_ftmBase[1];
225  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(1U);
226  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
227  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
228  bool chan6EnabledInt = ((enabledInterrupts & (1UL << 6U)) != 0U) ? true : false;
229  bool chan7EnabledInt = ((enabledInterrupts & (1UL << 7U)) != 0U) ? true : false;
230 
231  if (chan6EnabledInt && chan6IntFlag)
232  {
233  OC_IrqHandler(1U, 6U);
234  }
235 
236  if (chan7EnabledInt && chan7IntFlag)
237  {
238  OC_IrqHandler(1U, 7U);
239  }
240 }
241 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
242 #endif /* OC_PAL_INSTANCES_MAX > 1U */
243 
244 #if (OC_PAL_INSTANCES_MAX > 2U)
245 void FTM2_Ch0_Ch1_IrqHandler(void)
246 {
247  const FTM_Type * const base = g_ftmBase[2];
248  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(2U);
249  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
250  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
251  bool chan0EnabledInt = ((enabledInterrupts & (1UL << 0U)) != 0U) ? true : false;
252  bool chan1EnabledInt = ((enabledInterrupts & (1UL << 1U)) != 0U) ? true : false;
253 
254  if (chan0EnabledInt && chan0IntFlag)
255  {
256  OC_IrqHandler(2U, 0U);
257  }
258 
259  if (chan1EnabledInt && chan1IntFlag)
260  {
261  OC_IrqHandler(2U, 1U);
262  }
263 }
264 
265 void FTM2_Ch2_Ch3_IrqHandler(void)
266 {
267  const FTM_Type * const base = g_ftmBase[2];
268  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(2U);
269  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
270  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
271  bool chan2EnabledInt = ((enabledInterrupts & (1UL << 2U)) != 0U) ? true : false;
272  bool chan3EnabledInt = ((enabledInterrupts & (1UL << 3U)) != 0U) ? true : false;
273 
274  if (chan2EnabledInt && chan2IntFlag)
275  {
276  OC_IrqHandler(2U, 2U);
277  }
278 
279  if (chan3EnabledInt && chan3IntFlag)
280  {
281  OC_IrqHandler(2U, 3U);
282  }
283 }
284 
285 void FTM2_Ch4_Ch5_IrqHandler(void)
286 {
287  const FTM_Type * const base = g_ftmBase[2];
288  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(2U);
289  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
290  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
291  bool chan4EnabledInt = ((enabledInterrupts & (1UL << 4U)) != 0U) ? true : false;
292  bool chan5EnabledInt = ((enabledInterrupts & (1UL << 5U)) != 0U) ? true : false;
293 
294  if (chan4EnabledInt && chan4IntFlag)
295  {
296  OC_IrqHandler(2U, 4U);
297  }
298 
299  if (chan5EnabledInt && chan5IntFlag)
300  {
301  OC_IrqHandler(2U, 5U);
302  }
303 }
304 
305 void FTM2_Ch6_Ch7_IrqHandler(void)
306 {
307  const FTM_Type * const base = g_ftmBase[2];
308  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(2U);
309  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
310  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
311  bool chan6EnabledInt = ((enabledInterrupts & (1UL << 6U)) != 0U) ? true : false;
312  bool chan7EnabledInt = ((enabledInterrupts & (1UL << 7U)) != 0U) ? true : false;
313 
314  if (chan6EnabledInt && chan6IntFlag)
315  {
316  OC_IrqHandler(2U, 6U);
317  }
318 
319  if (chan7EnabledInt && chan7IntFlag)
320  {
321  OC_IrqHandler(2U, 7U);
322  }
323 }
324 #endif /* OC_PAL_INSTANCES_MAX > 2U */
325 
326 #if (OC_PAL_INSTANCES_MAX > 3U)
327 void FTM3_Ch0_Ch1_IrqHandler(void)
328 {
329  const FTM_Type * const base = g_ftmBase[3];
330  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(3U);
331  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
332  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
333  bool chan0EnabledInt = ((enabledInterrupts & (1UL << 0U)) != 0U) ? true : false;
334  bool chan1EnabledInt = ((enabledInterrupts & (1UL << 1U)) != 0U) ? true : false;
335 
336  if (chan0EnabledInt && chan0IntFlag)
337  {
338  OC_IrqHandler(3U, 0U);
339  }
340 
341  if (chan1EnabledInt && chan1IntFlag)
342  {
343  OC_IrqHandler(3U, 1U);
344  }
345 }
346 
347 void FTM3_Ch2_Ch3_IrqHandler(void)
348 {
349  const FTM_Type * const base = g_ftmBase[3];
350  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(3U);
351  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
352  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
353  bool chan2EnabledInt = ((enabledInterrupts & (1UL << 2U)) != 0U) ? true : false;
354  bool chan3EnabledInt = ((enabledInterrupts & (1UL << 3U)) != 0U) ? true : false;
355 
356  if (chan2EnabledInt && chan2IntFlag)
357  {
358  OC_IrqHandler(3U, 2U);
359  }
360 
361  if (chan3EnabledInt && chan3IntFlag)
362  {
363  OC_IrqHandler(3U, 3U);
364  }
365 }
366 
367 void FTM3_Ch4_Ch5_IrqHandler(void)
368 {
369  const FTM_Type * const base = g_ftmBase[3];
370  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(3U);
371  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
372  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
373  bool chan4EnabledInt = ((enabledInterrupts & (1UL << 4U)) != 0U) ? true : false;
374  bool chan5EnabledInt = ((enabledInterrupts & (1UL << 5U)) != 0U) ? true : false;
375 
376  if (chan4EnabledInt && chan4IntFlag)
377  {
378  OC_IrqHandler(3U, 4U);
379  }
380 
381  if (chan5EnabledInt && chan5IntFlag)
382  {
383  OC_IrqHandler(3U, 5U);
384  }
385 }
386 
387 void FTM3_Ch6_Ch7_IrqHandler(void)
388 {
389  const FTM_Type * const base = g_ftmBase[3];
390  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(3U);
391  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
392  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
393  bool chan6EnabledInt = ((enabledInterrupts & (1UL << 6U)) != 0U) ? true : false;
394  bool chan7EnabledInt = ((enabledInterrupts & (1UL << 7U)) != 0U) ? true : false;
395 
396  if (chan6EnabledInt && chan6IntFlag)
397  {
398  OC_IrqHandler(3U, 6U);
399  }
400 
401  if (chan7EnabledInt && chan7IntFlag)
402  {
403  OC_IrqHandler(3U, 7U);
404  }
405 }
406 #endif /* OC_PAL_INSTANCES_MAX > 3U */
407 
408 #if (OC_PAL_INSTANCES_MAX > 4U)
409 void FTM4_Ch0_Ch1_IrqHandler(void)
410 {
411  const FTM_Type * const base = g_ftmBase[4];
412  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(4U);
413  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
414  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
415  bool chan0EnabledInt = ((enabledInterrupts & (1UL << 0U)) != 0U) ? true : false;
416  bool chan1EnabledInt = ((enabledInterrupts & (1UL << 1U)) != 0U) ? true : false;
417 
418  if (chan0EnabledInt && chan0IntFlag)
419  {
420  OC_IrqHandler(4U, 0U);
421  }
422 
423  if (chan1EnabledInt && chan1IntFlag)
424  {
425  OC_IrqHandler(4U, 1U);
426  }
427 }
428 
429 void FTM4_Ch2_Ch3_IrqHandler(void)
430 {
431  const FTM_Type * const base = g_ftmBase[4];
432  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(4U);
433  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
434  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
435  bool chan2EnabledInt = ((enabledInterrupts & (1UL << 2U)) != 0U) ? true : false;
436  bool chan3EnabledInt = ((enabledInterrupts & (1UL << 3U)) != 0U) ? true : false;
437 
438  if (chan2EnabledInt && chan2IntFlag)
439  {
440  OC_IrqHandler(4U, 2U);
441  }
442 
443  if (chan3EnabledInt && chan3IntFlag)
444  {
445  OC_IrqHandler(4U, 3U);
446  }
447 }
448 
449 void FTM4_Ch4_Ch5_IrqHandler(void)
450 {
451  const FTM_Type * const base = g_ftmBase[4];
452  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(4U);
453  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
454  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
455  bool chan4EnabledInt = ((enabledInterrupts & (1UL << 4U)) != 0U) ? true : false;
456  bool chan5EnabledInt = ((enabledInterrupts & (1UL << 5U)) != 0U) ? true : false;
457 
458  if (chan4EnabledInt && chan4IntFlag)
459  {
460  OC_IrqHandler(4U, 4U);
461  }
462 
463  if (chan5EnabledInt && chan5IntFlag)
464  {
465  OC_IrqHandler(4U, 5U);
466  }
467 }
468 
469 void FTM4_Ch6_Ch7_IrqHandler(void)
470 {
471  const FTM_Type * const base = g_ftmBase[4];
472  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(4U);
473  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
474  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
475  bool chan6EnabledInt = ((enabledInterrupts & (1UL << 6U)) != 0U) ? true : false;
476  bool chan7EnabledInt = ((enabledInterrupts & (1UL << 7U)) != 0U) ? true : false;
477 
478  if (chan6EnabledInt && chan6IntFlag)
479  {
480  OC_IrqHandler(4U, 6U);
481  }
482 
483  if (chan7EnabledInt && chan7IntFlag)
484  {
485  OC_IrqHandler(4U, 7U);
486  }
487 }
488 #endif /* OC_PAL_INSTANCES_MAX > 4U */
489 
490 #if (OC_PAL_INSTANCES_MAX > 5U)
491 void FTM5_Ch0_Ch1_IrqHandler(void)
492 {
493  const FTM_Type * const base = g_ftmBase[5];
494  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(5U);
495  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
496  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
497  bool chan0EnabledInt = ((enabledInterrupts & (1UL << 0U)) != 0U) ? true : false;
498  bool chan1EnabledInt = ((enabledInterrupts & (1UL << 1U)) != 0U) ? true : false;
499 
500  if (chan0EnabledInt && chan0IntFlag)
501  {
502  OC_IrqHandler(5U, 0U);
503  }
504 
505  if (chan1EnabledInt && chan1IntFlag)
506  {
507  OC_IrqHandler(5U, 1U);
508  }
509 }
510 
511 void FTM5_Ch2_Ch3_IrqHandler(void)
512 {
513  const FTM_Type * const base = g_ftmBase[5];
514  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(5U);
515  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
516  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
517  bool chan2EnabledInt = ((enabledInterrupts & (1UL << 2U)) != 0U) ? true : false;
518  bool chan3EnabledInt = ((enabledInterrupts & (1UL << 3U)) != 0U) ? true : false;
519 
520  if (chan2EnabledInt && chan2IntFlag)
521  {
522  OC_IrqHandler(5U, 2U);
523  }
524 
525  if (chan3EnabledInt && chan3IntFlag)
526  {
527  OC_IrqHandler(5U, 3U);
528  }
529 }
530 
531 void FTM5_Ch4_Ch5_IrqHandler(void)
532 {
533  const FTM_Type * const base = g_ftmBase[5];
534  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(5U);
535  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
536  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
537  bool chan4EnabledInt = ((enabledInterrupts & (1UL << 4U)) != 0U) ? true : false;
538  bool chan5EnabledInt = ((enabledInterrupts & (1UL << 5U)) != 0U) ? true : false;
539 
540  if (chan4EnabledInt && chan4IntFlag)
541  {
542  OC_IrqHandler(5U, 4U);
543  }
544 
545  if (chan5EnabledInt && chan5IntFlag)
546  {
547  OC_IrqHandler(5U, 5U);
548  }
549 }
550 
551 void FTM5_Ch6_Ch7_IrqHandler(void)
552 {
553  const FTM_Type * const base = g_ftmBase[5];
554  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(5U);
555  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
556  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
557  bool chan6EnabledInt = ((enabledInterrupts & (1UL << 6U)) != 0U) ? true : false;
558  bool chan7EnabledInt = ((enabledInterrupts & (1UL << 7U)) != 0U) ? true : false;
559 
560  if (chan6EnabledInt && chan6IntFlag)
561  {
562  OC_IrqHandler(5U, 6U);
563  }
564 
565  if (chan7EnabledInt && chan7IntFlag)
566  {
567  OC_IrqHandler(5U, 7U);
568  }
569 }
570 #endif /* OC_PAL_INSTANCES_MAX > 5U */
571 
572 #if (OC_PAL_INSTANCES_MAX > 6U)
573 void FTM6_Ch0_Ch1_IrqHandler(void)
574 {
575  const FTM_Type * const base = g_ftmBase[6];
576  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(6U);
577  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
578  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
579  bool chan0EnabledInt = ((enabledInterrupts & (1UL << 0U)) != 0U) ? true : false;
580  bool chan1EnabledInt = ((enabledInterrupts & (1UL << 1U)) != 0U) ? true : false;
581 
582  if (chan0EnabledInt && chan0IntFlag)
583  {
584  OC_IrqHandler(6U, 0U);
585  }
586 
587  if (chan1EnabledInt && chan1IntFlag)
588  {
589  OC_IrqHandler(6U, 1U);
590  }
591 }
592 
593 void FTM6_Ch2_Ch3_IrqHandler(void)
594 {
595  const FTM_Type * const base = g_ftmBase[6];
596  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(6U);
597  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
598  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
599  bool chan2EnabledInt = ((enabledInterrupts & (1UL << 2U)) != 0U) ? true : false;
600  bool chan3EnabledInt = ((enabledInterrupts & (1UL << 3U)) != 0U) ? true : false;
601 
602  if (chan2EnabledInt && chan2IntFlag)
603  {
604  OC_IrqHandler(6U, 2U);
605  }
606 
607  if (chan3EnabledInt && chan3IntFlag)
608  {
609  OC_IrqHandler(6U, 3U);
610  }
611 }
612 
613 void FTM6_Ch4_Ch5_IrqHandler(void)
614 {
615  const FTM_Type * const base = g_ftmBase[6];
616  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(6U);
617  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
618  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
619  bool chan4EnabledInt = ((enabledInterrupts & (1UL << 4U)) != 0U) ? true : false;
620  bool chan5EnabledInt = ((enabledInterrupts & (1UL << 5U)) != 0U) ? true : false;
621 
622  if (chan4EnabledInt && chan4IntFlag)
623  {
624  OC_IrqHandler(6U, 4U);
625  }
626 
627  if (chan5EnabledInt && chan5IntFlag)
628  {
629  OC_IrqHandler(6U, 5U);
630  }
631 }
632 
633 void FTM6_Ch6_Ch7_IrqHandler(void)
634 {
635  const FTM_Type * const base = g_ftmBase[6];
636  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(6U);
637  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 6U);
638  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 7U);
639  bool chan6EnabledInt = ((enabledInterrupts & (1UL << 6U)) != 0U) ? true : false;
640  bool chan7EnabledInt = ((enabledInterrupts & (1UL << 7U)) != 0U) ? true : false;
641 
642  if (chan6EnabledInt && chan6IntFlag)
643  {
644  OC_IrqHandler(6U, 6U);
645  }
646 
647  if (chan7EnabledInt && chan7IntFlag)
648  {
649  OC_IrqHandler(6U, 7U);
650  }
651 }
652 #endif /* OC_PAL_INSTANCES_MAX > 6U */
653 
654 #if (OC_PAL_INSTANCES_MAX > 7U)
655 void FTM7_Ch0_Ch1_IrqHandler(void)
656 {
657  const FTM_Type * const base = g_ftmBase[7];
658  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(7U);
659  bool chan0IntFlag = FTM_DRV_GetChnEventStatus(base, 0U);
660  bool chan1IntFlag = FTM_DRV_GetChnEventStatus(base, 1U);
661  bool chan0EnabledInt = ((enabledInterrupts & (1UL << 0U)) != 0U) ? true : false;
662  bool chan1EnabledInt = ((enabledInterrupts & (1UL << 1U)) != 0U) ? true : false;
663 
664  if (chan0EnabledInt && chan0IntFlag)
665  {
666  OC_IrqHandler(7U, 0U);
667  }
668 
669  if (chan1EnabledInt && chan1IntFlag)
670  {
671  OC_IrqHandler(7U, 1U);
672  }
673 }
674 
675 void FTM7_Ch2_Ch3_IrqHandler(void)
676 {
677  const FTM_Type * const base = g_ftmBase[7];
678  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(7U);
679  bool chan2IntFlag = FTM_DRV_GetChnEventStatus(base, 2U);
680  bool chan3IntFlag = FTM_DRV_GetChnEventStatus(base, 3U);
681  bool chan2EnabledInt = ((enabledInterrupts & (1UL << 2U)) != 0U) ? true : false;
682  bool chan3EnabledInt = ((enabledInterrupts & (1UL << 3U)) != 0U) ? true : false;
683 
684  if (chan2EnabledInt && chan2IntFlag)
685  {
686  OC_IrqHandler(7U, 2U);
687  }
688 
689  if (chan3EnabledInt && chan3IntFlag)
690  {
691  OC_IrqHandler(7U, 3U);
692  }
693 }
694 
695 void FTM7_Ch4_Ch5_IrqHandler(void)
696 {
697  const FTM_Type * const base = g_ftmBase[7];
698  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(7U);
699  bool chan4IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
700  bool chan5IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
701  bool chan4EnabledInt = ((enabledInterrupts & (1UL << 4U)) != 0U) ? true : false;
702  bool chan5EnabledInt = ((enabledInterrupts & (1UL << 5U)) != 0U) ? true : false;
703 
704  if (chan4EnabledInt && chan4IntFlag)
705  {
706  OC_IrqHandler(7U, 4U);
707  }
708 
709  if (chan5EnabledInt && chan5IntFlag)
710  {
711  OC_IrqHandler(7U, 5U);
712  }
713 }
714 
715 void FTM7_Ch6_Ch7_IrqHandler(void)
716 {
717  const FTM_Type * const base = g_ftmBase[7];
718  uint32_t enabledInterrupts = FTM_DRV_GetEnabledInterrupts(7U);
719  bool chan6IntFlag = FTM_DRV_GetChnEventStatus(base, 4U);
720  bool chan7IntFlag = FTM_DRV_GetChnEventStatus(base, 5U);
721  bool chan6EnabledInt = ((enabledInterrupts & (1UL << 6U)) != 0U) ? true : false;
722  bool chan7EnabledInt = ((enabledInterrupts & (1UL << 7U)) != 0U) ? true : false;
723 
724  if (chan6EnabledInt && chan6IntFlag)
725  {
726  OC_IrqHandler(7U, 6U);
727  }
728 
729  if (chan7EnabledInt && chan7IntFlag)
730  {
731  OC_IrqHandler(7U, 7U);
732  }
733 }
734 #endif /* OC_PAL_INSTANCES_MAX > 7U */
735 
736 /* Array storing references to OC PAL over FTM irq handlers */
737 const isr_t s_ocOverFtmIsr[OC_PAL_INSTANCES_MAX][FTM_CONTROLS_COUNT] =
738 {
739 #if (OC_PAL_INSTANCES_MAX > 0U)
740 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
741  {FTM0_Ch0_7_IrqHandler,
742  FTM0_Ch0_7_IrqHandler,
743  FTM0_Ch0_7_IrqHandler,
744  FTM0_Ch0_7_IrqHandler,
745  FTM0_Ch0_7_IrqHandler,
746  FTM0_Ch0_7_IrqHandler,
747  FTM0_Ch0_7_IrqHandler,
748  FTM0_Ch0_7_IrqHandler},
749 #else
750  {FTM0_Ch0_Ch1_IrqHandler,
751  FTM0_Ch0_Ch1_IrqHandler,
752  FTM0_Ch2_Ch3_IrqHandler,
753  FTM0_Ch2_Ch3_IrqHandler,
754  FTM0_Ch4_Ch5_IrqHandler,
755  FTM0_Ch4_Ch5_IrqHandler,
756  FTM0_Ch6_Ch7_IrqHandler,
757  FTM0_Ch6_Ch7_IrqHandler},
758 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
759 #endif /* OC_PAL_INSTANCES_MAX > 0U */
760 #if (OC_PAL_INSTANCES_MAX > 1U)
761 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
762  {FTM1_Ch0_7_IrqHandler,
763  FTM1_Ch0_7_IrqHandler,
764  FTM1_Ch0_7_IrqHandler,
765  FTM1_Ch0_7_IrqHandler,
766  FTM1_Ch0_7_IrqHandler,
767  FTM1_Ch0_7_IrqHandler,
768  FTM1_Ch0_7_IrqHandler,
769  FTM1_Ch0_7_IrqHandler},
770 #else
771  {FTM1_Ch0_Ch1_IrqHandler,
772  FTM1_Ch0_Ch1_IrqHandler,
773  FTM1_Ch2_Ch3_IrqHandler,
774  FTM1_Ch2_Ch3_IrqHandler,
775  FTM1_Ch4_Ch5_IrqHandler,
776  FTM1_Ch4_Ch5_IrqHandler,
777  FTM1_Ch6_Ch7_IrqHandler,
778  FTM1_Ch6_Ch7_IrqHandler},
779 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
780 #endif /* OC_PAL_INSTANCES_MAX > 1U */
781 #if (OC_PAL_INSTANCES_MAX > 2U)
782  {FTM2_Ch0_Ch1_IrqHandler,
783  FTM2_Ch0_Ch1_IrqHandler,
784  FTM2_Ch2_Ch3_IrqHandler,
785  FTM2_Ch2_Ch3_IrqHandler,
786  FTM2_Ch4_Ch5_IrqHandler,
787  FTM2_Ch4_Ch5_IrqHandler,
788  FTM2_Ch6_Ch7_IrqHandler,
789  FTM2_Ch6_Ch7_IrqHandler},
790 #endif
791 #if (OC_PAL_INSTANCES_MAX > 3U)
792  {FTM3_Ch0_Ch1_IrqHandler,
793  FTM3_Ch0_Ch1_IrqHandler,
794  FTM3_Ch2_Ch3_IrqHandler,
795  FTM3_Ch2_Ch3_IrqHandler,
796  FTM3_Ch4_Ch5_IrqHandler,
797  FTM3_Ch4_Ch5_IrqHandler,
798  FTM3_Ch6_Ch7_IrqHandler,
799  FTM3_Ch6_Ch7_IrqHandler},
800 #endif
801 #if (OC_PAL_INSTANCES_MAX > 4U)
802  {FTM4_Ch0_Ch1_IrqHandler,
803  FTM4_Ch0_Ch1_IrqHandler,
804  FTM4_Ch2_Ch3_IrqHandler,
805  FTM4_Ch2_Ch3_IrqHandler,
806  FTM4_Ch4_Ch5_IrqHandler,
807  FTM4_Ch4_Ch5_IrqHandler,
808  FTM4_Ch6_Ch7_IrqHandler,
809  FTM4_Ch6_Ch7_IrqHandler},
810 #endif
811 #if (OC_PAL_INSTANCES_MAX > 5U)
812  {FTM5_Ch0_Ch1_IrqHandler,
813  FTM5_Ch0_Ch1_IrqHandler,
814  FTM5_Ch2_Ch3_IrqHandler,
815  FTM5_Ch2_Ch3_IrqHandler,
816  FTM5_Ch4_Ch5_IrqHandler,
817  FTM5_Ch4_Ch5_IrqHandler,
818  FTM5_Ch6_Ch7_IrqHandler,
819  FTM5_Ch6_Ch7_IrqHandler},
820 #endif
821 #if (OC_PAL_INSTANCES_MAX > 6U)
822  {FTM6_Ch0_Ch1_IrqHandler,
823  FTM6_Ch0_Ch1_IrqHandler,
824  FTM6_Ch2_Ch3_IrqHandler,
825  FTM6_Ch2_Ch3_IrqHandler,
826  FTM6_Ch4_Ch5_IrqHandler,
827  FTM6_Ch4_Ch5_IrqHandler,
828  FTM6_Ch6_Ch7_IrqHandler,
829  FTM6_Ch6_Ch7_IrqHandler},
830 #endif
831 #if (OC_PAL_INSTANCES_MAX > 7U)
832  {FTM7_Ch0_Ch1_IrqHandler,
833  FTM7_Ch0_Ch1_IrqHandler,
834  FTM7_Ch2_Ch3_IrqHandler,
835  FTM7_Ch2_Ch3_IrqHandler,
836  FTM7_Ch4_Ch5_IrqHandler,
837  FTM7_Ch4_Ch5_IrqHandler,
838  FTM7_Ch6_Ch7_IrqHandler,
839  FTM7_Ch6_Ch7_IrqHandler}
840 #endif
841 };
842 
843 #endif /* OC_PAL_OVER_FTM */
844 
845 #if (defined(OC_PAL_OVER_EMIOS))
846 
847 #if (OC_PAL_INSTANCES_MAX > 0U)
848 /* The interrupt function for channel 0, 1 on EMIOS0 */
849 void EMIOS0_00_01_IRQHandler(void)
850 {
851  /* Check the FLAG bit is set or not */
852  if (EMIOS_DRV_ReadFlagState(0U, 0U) == true)
853  {
854  OC_IrqHandler(0U, 0U);
855  }
856 
857  /* Check the FLAG bit is set or not */
858  if (EMIOS_DRV_ReadFlagState(0U, 1U) == true)
859  {
860  OC_IrqHandler(0U, 1U);
861  }
862 }
863 
864 /* The interrupt function for channel 2, 3 on EMIOS0 */
865 void EMIOS0_02_03_IRQHandler(void)
866 {
867  /* Check the FLAG bit is set or not */
868  if (EMIOS_DRV_ReadFlagState(0U, 2U) == true)
869  {
870  OC_IrqHandler(0U, 2U);
871  }
872 
873  /* Check the FLAG bit is set or not */
874  if (EMIOS_DRV_ReadFlagState(0U, 3U) == true)
875  {
876  OC_IrqHandler(0U, 3U);
877  }
878 }
879 
880 /* The interrupt function for channel 4, 5 on EMIOS0 */
881 void EMIOS0_04_05_IRQHandler(void)
882 {
883  /* Check the FLAG bit is set or not */
884  if (EMIOS_DRV_ReadFlagState(0U, 4U) == true)
885  {
886  OC_IrqHandler(0U, 4U);
887  }
888 
889  /* Check the FLAG bit is set or not */
890  if (EMIOS_DRV_ReadFlagState(0U, 5U) == true)
891  {
892  OC_IrqHandler(0U, 5U);
893  }
894 }
895 
896 /* The interrupt function for channel 6, 7 on EMIOS0 */
897 void EMIOS0_06_07_IRQHandler(void)
898 {
899  /* Check the FLAG bit is set or not */
900  if (EMIOS_DRV_ReadFlagState(0U, 6U) == true)
901  {
902  OC_IrqHandler(0U, 6U);
903  }
904 
905  /* Check the FLAG bit is set or not */
906  if (EMIOS_DRV_ReadFlagState(0U, 7U) == true)
907  {
908  OC_IrqHandler(0U, 7U);
909  }
910 }
911 
912 /* The interrupt function for channel 8, 9 on EMIOS0 */
913 void EMIOS0_08_09_IRQHandler(void)
914 {
915  /* Check the FLAG bit is set or not */
916  if (EMIOS_DRV_ReadFlagState(0U, 8U) == true)
917  {
918  OC_IrqHandler(0U, 8U);
919  }
920 
921  /* Check the FLAG bit is set or not */
922  if (EMIOS_DRV_ReadFlagState(0U, 9U) == true)
923  {
924  OC_IrqHandler(0U, 9U);
925  }
926 }
927 
928 /* The interrupt function for channel 10, 11 on EMIOS0 */
929 void EMIOS0_10_11_IRQHandler(void)
930 {
931  /* Check the FLAG bit is set or not */
932  if (EMIOS_DRV_ReadFlagState(0U, 10U) == true)
933  {
934  OC_IrqHandler(0U, 10U);
935  }
936 
937  /* Check the FLAG bit is set or not */
938  if (EMIOS_DRV_ReadFlagState(0U, 11U) == true)
939  {
940  OC_IrqHandler(0U, 11U);
941  }
942 }
943 
944 /* The interrupt function for channel 12, 13 on EMIOS0 */
945 void EMIOS0_12_13_IRQHandler(void)
946 {
947  /* Check the FLAG bit is set or not */
948  if (EMIOS_DRV_ReadFlagState(0U, 12U) == true)
949  {
950  OC_IrqHandler(0U, 12U);
951  }
952 
953  /* Check the FLAG bit is set or not */
954  if (EMIOS_DRV_ReadFlagState(0U, 13U) == true)
955  {
956  OC_IrqHandler(0U, 13U);
957  }
958 }
959 
960 /* The interrupt function for channel 14, 15 on EMIOS0 */
961 void EMIOS0_14_15_IRQHandler(void)
962 {
963  /* Check the FLAG bit is set or not */
964  if (EMIOS_DRV_ReadFlagState(0U, 14U) == true)
965  {
966  OC_IrqHandler(0U, 14U);
967  }
968 
969  /* Check the FLAG bit is set or not */
970  if (EMIOS_DRV_ReadFlagState(0U, 15U) == true)
971  {
972  OC_IrqHandler(0U, 15U);
973  }
974 }
975 
976 /* The interrupt function for channel 16, 17 on EMIOS0 */
977 void EMIOS0_16_17_IRQHandler(void)
978 {
979  /* Check the FLAG bit is set or not */
980  if (EMIOS_DRV_ReadFlagState(0U, 16U) == true)
981  {
982  OC_IrqHandler(0U, 16U);
983  }
984 
985  /* Check the FLAG bit is set or not */
986  if (EMIOS_DRV_ReadFlagState(0U, 17U) == true)
987  {
988  OC_IrqHandler(0U, 17U);
989  }
990 }
991 
992 /* The interrupt function for channel 18, 19 on EMIOS0 */
993 void EMIOS0_18_19_IRQHandler(void)
994 {
995  /* Check the FLAG bit is set or not */
996  if (EMIOS_DRV_ReadFlagState(0U, 18U) == true)
997  {
998  OC_IrqHandler(0U, 18U);
999  }
1000 
1001  /* Check the FLAG bit is set or not */
1002  if (EMIOS_DRV_ReadFlagState(0U, 19U) == true)
1003  {
1004  OC_IrqHandler(0U, 19U);
1005  }
1006 }
1007 
1008 /* The interrupt function for channel 20, 21 on EMIOS0 */
1009 void EMIOS0_20_21_IRQHandler(void)
1010 {
1011  /* Check the FLAG bit is set or not */
1012  if (EMIOS_DRV_ReadFlagState(0U, 20U) == true)
1013  {
1014  OC_IrqHandler(0U, 20U);
1015  }
1016 
1017  /* Check the FLAG bit is set or not */
1018  if (EMIOS_DRV_ReadFlagState(0U, 21U) == true)
1019  {
1020  OC_IrqHandler(0U, 21U);
1021  }
1022 }
1023 
1024 /* The interrupt function for channel 22, 23 on EMIOS0 */
1025 void EMIOS0_22_23_IRQHandler(void)
1026 {
1027  /* Check the FLAG bit is set or not */
1028  if (EMIOS_DRV_ReadFlagState(0U, 22U) == true)
1029  {
1030  OC_IrqHandler(0U, 22U);
1031  }
1032 
1033  /* Check the FLAG bit is set or not */
1034  if (EMIOS_DRV_ReadFlagState(0U, 23U) == true)
1035  {
1036  OC_IrqHandler(0U, 23U);
1037  }
1038 }
1039 
1040 /* The interrupt function for channel 24, 25 on EMIOS0 */
1041 void EMIOS0_24_25_IRQHandler(void)
1042 {
1043  /* Check the FLAG bit is set or not */
1044  if (EMIOS_DRV_ReadFlagState(0U, 24U) == true)
1045  {
1046  OC_IrqHandler(0U, 24U);
1047  }
1048 
1049  /* Check the FLAG bit is set or not */
1050  if (EMIOS_DRV_ReadFlagState(0U, 25U) == true)
1051  {
1052  OC_IrqHandler(0U, 25U);
1053  }
1054 }
1055 
1056 /* The interrupt function for channel 26, 27 on EMIOS0 */
1057 void EMIOS0_26_27_IRQHandler(void)
1058 {
1059  /* Check the FLAG bit is set or not */
1060  if (EMIOS_DRV_ReadFlagState(0U, 26U) == true)
1061  {
1062  OC_IrqHandler(0U, 26U);
1063  }
1064 
1065  /* Check the FLAG bit is set or not */
1066  if (EMIOS_DRV_ReadFlagState(0U, 27U) == true)
1067  {
1068  OC_IrqHandler(0U, 27U);
1069  }
1070 }
1071 
1072 /* The interrupt function for channel 28, 29 on EMIOS0 */
1073 void EMIOS0_28_29_IRQHandler(void)
1074 {
1075  /* Check the FLAG bit is set or not */
1076  if (EMIOS_DRV_ReadFlagState(0U, 28U) == true)
1077  {
1078  OC_IrqHandler(0U, 28U);
1079  }
1080 
1081  /* Check the FLAG bit is set or not */
1082  if (EMIOS_DRV_ReadFlagState(0U, 29U) == true)
1083  {
1084  OC_IrqHandler(0U, 29U);
1085  }
1086 }
1087 
1088 /* The interrupt function for channel 30, 31 on EMIOS0 */
1089 void EMIOS0_30_31_IRQHandler(void)
1090 {
1091  /* Check the FLAG bit is set or not */
1092  if (EMIOS_DRV_ReadFlagState(0U, 30U) == true)
1093  {
1094  OC_IrqHandler(0U, 30U);
1095  }
1096 
1097  /* Check the FLAG bit is set or not */
1098  if (EMIOS_DRV_ReadFlagState(0U, 31U) == true)
1099  {
1100  OC_IrqHandler(0U, 31U);
1101  }
1102 }
1103 #endif /* End of (OC_PAL_INSTANCES_MAX > 0U) */
1104 
1105 #if (OC_PAL_INSTANCES_MAX > 1U)
1106 /* The interrupt function for channel 0, 1 on EMIOS1 */
1107 void EMIOS1_00_01_IRQHandler(void)
1108 {
1109  /* Check the FLAG bit is set or not */
1110  if (EMIOS_DRV_ReadFlagState(1U, 0U) == true)
1111  {
1112  OC_IrqHandler(1U, 0U);
1113  }
1114 
1115  /* Check the FLAG bit is set or not */
1116  if (EMIOS_DRV_ReadFlagState(1U, 1U) == true)
1117  {
1118  OC_IrqHandler(1U, 1U);
1119  }
1120 }
1121 
1122 /* The interrupt function for channel 2, 3 on EMIOS1 */
1123 void EMIOS1_02_03_IRQHandler(void)
1124 {
1125  /* Check the FLAG bit is set or not */
1126  if (EMIOS_DRV_ReadFlagState(1U, 2U) == true)
1127  {
1128  OC_IrqHandler(1U, 2U);
1129  }
1130 
1131  /* Check the FLAG bit is set or not */
1132  if (EMIOS_DRV_ReadFlagState(1U, 3U) == true)
1133  {
1134  OC_IrqHandler(1U, 3U);
1135  }
1136 }
1137 
1138 /* The interrupt function for channel 4, 5 on EMIOS1 */
1139 void EMIOS1_04_05_IRQHandler(void)
1140 {
1141  /* Check the FLAG bit is set or not */
1142  if (EMIOS_DRV_ReadFlagState(1U, 4U) == true)
1143  {
1144  OC_IrqHandler(1U, 4U);
1145  }
1146 
1147  /* Check the FLAG bit is set or not */
1148  if (EMIOS_DRV_ReadFlagState(1U, 5U) == true)
1149  {
1150  OC_IrqHandler(1U, 5U);
1151  }
1152 }
1153 
1154 /* The interrupt function for channel 6, 7 on EMIOS1 */
1155 void EMIOS1_06_07_IRQHandler(void)
1156 {
1157  /* Check the FLAG bit is set or not */
1158  if (EMIOS_DRV_ReadFlagState(1U, 6U) == true)
1159  {
1160  OC_IrqHandler(1U, 6U);
1161  }
1162 
1163  /* Check the FLAG bit is set or not */
1164  if (EMIOS_DRV_ReadFlagState(1U, 7U) == true)
1165  {
1166  OC_IrqHandler(1U, 7U);
1167  }
1168 }
1169 
1170 /* The interrupt function for channel 8, 9 on EMIOS1 */
1171 void EMIOS1_08_09_IRQHandler(void)
1172 {
1173  /* Check the FLAG bit is set or not */
1174  if (EMIOS_DRV_ReadFlagState(1U, 8U) == true)
1175  {
1176  OC_IrqHandler(1U, 8U);
1177  }
1178 
1179  /* Check the FLAG bit is set or not */
1180  if (EMIOS_DRV_ReadFlagState(1U, 9U) == true)
1181  {
1182  OC_IrqHandler(1U, 9U);
1183  }
1184 }
1185 
1186 /* The interrupt function for channel 10, 11 on EMIOS1 */
1187 void EMIOS1_10_11_IRQHandler(void)
1188 {
1189  /* Check the FLAG bit is set or not */
1190  if (EMIOS_DRV_ReadFlagState(1U, 10U) == true)
1191  {
1192  OC_IrqHandler(1U, 10U);
1193  }
1194 
1195  /* Check the FLAG bit is set or not */
1196  if (EMIOS_DRV_ReadFlagState(1U, 11U) == true)
1197  {
1198  OC_IrqHandler(1U, 11U);
1199  }
1200 }
1201 
1202 /* The interrupt function for channel 12, 13 on EMIOS1 */
1203 void EMIOS1_12_13_IRQHandler(void)
1204 {
1205  /* Check the FLAG bit is set or not */
1206  if (EMIOS_DRV_ReadFlagState(1U, 12U) == true)
1207  {
1208  OC_IrqHandler(1U, 12U);
1209  }
1210 
1211  /* Check the FLAG bit is set or not */
1212  if (EMIOS_DRV_ReadFlagState(1U, 13U) == true)
1213  {
1214  OC_IrqHandler(1U, 13U);
1215  }
1216 }
1217 
1218 /* The interrupt function for channel 14, 15 on EMIOS1 */
1219 void EMIOS1_14_15_IRQHandler(void)
1220 {
1221  /* Check the FLAG bit is set or not */
1222  if (EMIOS_DRV_ReadFlagState(1U, 14U) == true)
1223  {
1224  OC_IrqHandler(1U, 14U);
1225  }
1226 
1227  /* Check the FLAG bit is set or not */
1228  if (EMIOS_DRV_ReadFlagState(1U, 15U) == true)
1229  {
1230  OC_IrqHandler(1U, 15U);
1231  }
1232 }
1233 
1234 /* The interrupt function for channel 16, 17 on EMIOS1 */
1235 void EMIOS1_16_17_IRQHandler(void)
1236 {
1237  /* Check the FLAG bit is set or not */
1238  if (EMIOS_DRV_ReadFlagState(1U, 16U) == true)
1239  {
1240  OC_IrqHandler(1U, 16U);
1241  }
1242 
1243  /* Check the FLAG bit is set or not */
1244  if (EMIOS_DRV_ReadFlagState(1U, 17U) == true)
1245  {
1246  OC_IrqHandler(1U, 17U);
1247  }
1248 }
1249 
1250 /* The interrupt function for channel 18, 19 on EMIOS1 */
1251 void EMIOS1_18_19_IRQHandler(void)
1252 {
1253  /* Check the FLAG bit is set or not */
1254  if (EMIOS_DRV_ReadFlagState(1U, 18U) == true)
1255  {
1256  OC_IrqHandler(1U, 18U);
1257  }
1258 
1259  /* Check the FLAG bit is set or not */
1260  if (EMIOS_DRV_ReadFlagState(1U, 19U) == true)
1261  {
1262  OC_IrqHandler(1U, 19U);
1263  }
1264 }
1265 
1266 /* The interrupt function for channel 20, 21 on EMIOS1 */
1267 void EMIOS1_20_21_IRQHandler(void)
1268 {
1269  /* Check the FLAG bit is set or not */
1270  if (EMIOS_DRV_ReadFlagState(1U, 20U) == true)
1271  {
1272  OC_IrqHandler(1U, 20U);
1273  }
1274 
1275  /* Check the FLAG bit is set or not */
1276  if (EMIOS_DRV_ReadFlagState(1U, 21U) == true)
1277  {
1278  OC_IrqHandler(1U, 21U);
1279  }
1280 }
1281 
1282 /* The interrupt function for channel 22, 23 on EMIOS1 */
1283 void EMIOS1_22_23_IRQHandler(void)
1284 {
1285  /* Check the FLAG bit is set or not */
1286  if (EMIOS_DRV_ReadFlagState(1U, 22U) == true)
1287  {
1288  OC_IrqHandler(1U, 22U);
1289  }
1290 
1291  /* Check the FLAG bit is set or not */
1292  if (EMIOS_DRV_ReadFlagState(1U, 23U) == true)
1293  {
1294  OC_IrqHandler(1U, 23U);
1295  }
1296 }
1297 
1298 /* The interrupt function for channel 24, 25 on EMIOS1 */
1299 void EMIOS1_24_25_IRQHandler(void)
1300 {
1301  /* Check the FLAG bit is set or not */
1302  if (EMIOS_DRV_ReadFlagState(1U, 24U) == true)
1303  {
1304  OC_IrqHandler(1U, 24U);
1305  }
1306 
1307  /* Check the FLAG bit is set or not */
1308  if (EMIOS_DRV_ReadFlagState(1U, 25U) == true)
1309  {
1310  OC_IrqHandler(1U, 25U);
1311  }
1312 }
1313 
1314 /* The interrupt function for channel 26, 27 on EMIOS1 */
1315 void EMIOS1_26_27_IRQHandler(void)
1316 {
1317  /* Check the FLAG bit is set or not */
1318  if (EMIOS_DRV_ReadFlagState(1U, 26U) == true)
1319  {
1320  OC_IrqHandler(1U, 26U);
1321  }
1322 
1323  /* Check the FLAG bit is set or not */
1324  if (EMIOS_DRV_ReadFlagState(1U, 27U) == true)
1325  {
1326  OC_IrqHandler(1U, 27U);
1327  }
1328 }
1329 
1330 /* The interrupt function for channel 28, 29 on EMIOS1 */
1331 void EMIOS1_28_29_IRQHandler(void)
1332 {
1333  /* Check the FLAG bit is set or not */
1334  if (EMIOS_DRV_ReadFlagState(1U, 28U) == true)
1335  {
1336  OC_IrqHandler(1U, 28U);
1337  }
1338 
1339  /* Check the FLAG bit is set or not */
1340  if (EMIOS_DRV_ReadFlagState(1U, 29U) == true)
1341  {
1342  OC_IrqHandler(1U, 29U);
1343  }
1344 }
1345 
1346 /* The interrupt function for channel 30, 31 on EMIOS1 */
1347 void EMIOS1_30_31_IRQHandler(void)
1348 {
1349  /* Check the FLAG bit is set or not */
1350  if (EMIOS_DRV_ReadFlagState(1U, 30U) == true)
1351  {
1352  OC_IrqHandler(1U, 30U);
1353  }
1354 
1355  /* Check the FLAG bit is set or not */
1356  if (EMIOS_DRV_ReadFlagState(1U, 31U) == true)
1357  {
1358  OC_IrqHandler(1U, 31U);
1359  }
1360 }
1361 #endif /* End of (OC_PAL_INSTANCES_MAX > 1U) */
1362 
1363 #if (OC_PAL_INSTANCES_MAX > 2U)
1364 /* The interrupt function for channel 0, 1 on EMIOS2 */
1365 void EMIOS2_00_01_IRQHandler(void)
1366 {
1367  /* Check the FLAG bit is set or not */
1368  if (EMIOS_DRV_ReadFlagState(2U, 0U) == true)
1369  {
1370  OC_IrqHandler(2U, 0U);
1371  }
1372 
1373  /* Check the FLAG bit is set or not */
1374  if (EMIOS_DRV_ReadFlagState(2U, 1U) == true)
1375  {
1376  OC_IrqHandler(2U, 1U);
1377  }
1378 }
1379 
1380 /* The interrupt function for channel 2, 3 on EMIOS2 */
1381 void EMIOS2_02_03_IRQHandler(void)
1382 {
1383  /* Check the FLAG bit is set or not */
1384  if (EMIOS_DRV_ReadFlagState(2U, 2U) == true)
1385  {
1386  OC_IrqHandler(2U, 2U);
1387  }
1388 
1389  /* Check the FLAG bit is set or not */
1390  if (EMIOS_DRV_ReadFlagState(2U, 3U) == true)
1391  {
1392  OC_IrqHandler(2U, 3U);
1393  }
1394 }
1395 
1396 /* The interrupt function for channel 4, 5 on EMIOS2 */
1397 void EMIOS2_04_05_IRQHandler(void)
1398 {
1399  /* Check the FLAG bit is set or not */
1400  if (EMIOS_DRV_ReadFlagState(2U, 4U) == true)
1401  {
1402  OC_IrqHandler(2U, 4U);
1403  }
1404 
1405  /* Check the FLAG bit is set or not */
1406  if (EMIOS_DRV_ReadFlagState(2U, 5U) == true)
1407  {
1408  OC_IrqHandler(2U, 5U);
1409  }
1410 }
1411 
1412 /* The interrupt function for channel 6, 7 on EMIOS2 */
1413 void EMIOS2_06_07_IRQHandler(void)
1414 {
1415  /* Check the FLAG bit is set or not */
1416  if (EMIOS_DRV_ReadFlagState(2U, 6U) == true)
1417  {
1418  OC_IrqHandler(2U, 6U);
1419  }
1420 
1421  /* Check the FLAG bit is set or not */
1422  if (EMIOS_DRV_ReadFlagState(2U, 7U) == true)
1423  {
1424  OC_IrqHandler(2U, 7U);
1425  }
1426 }
1427 
1428 /* The interrupt function for channel 8, 9 on EMIOS2 */
1429 void EMIOS2_08_09_IRQHandler(void)
1430 {
1431  /* Check the FLAG bit is set or not */
1432  if (EMIOS_DRV_ReadFlagState(2U, 8U) == true)
1433  {
1434  OC_IrqHandler(2U, 8U);
1435  }
1436 
1437  /* Check the FLAG bit is set or not */
1438  if (EMIOS_DRV_ReadFlagState(2U, 9U) == true)
1439  {
1440  OC_IrqHandler(2U, 9U);
1441  }
1442 }
1443 
1444 /* The interrupt function for channel 10, 11 on EMIOS2 */
1445 void EMIOS2_10_11_IRQHandler(void)
1446 {
1447  /* Check the FLAG bit is set or not */
1448  if (EMIOS_DRV_ReadFlagState(2U, 10U) == true)
1449  {
1450  OC_IrqHandler(2U, 10U);
1451  }
1452 
1453  /* Check the FLAG bit is set or not */
1454  if (EMIOS_DRV_ReadFlagState(2U, 11U) == true)
1455  {
1456  OC_IrqHandler(2U, 11U);
1457  }
1458 }
1459 
1460 /* The interrupt function for channel 12, 13 on EMIOS2 */
1461 void EMIOS2_12_13_IRQHandler(void)
1462 {
1463  /* Check the FLAG bit is set or not */
1464  if (EMIOS_DRV_ReadFlagState(2U, 12U) == true)
1465  {
1466  OC_IrqHandler(2U, 12U);
1467  }
1468 
1469  /* Check the FLAG bit is set or not */
1470  if (EMIOS_DRV_ReadFlagState(2U, 13U) == true)
1471  {
1472  OC_IrqHandler(2U, 13U);
1473  }
1474 }
1475 
1476 /* The interrupt function for channel 14, 15 on EMIOS2 */
1477 void EMIOS2_14_15_IRQHandler(void)
1478 {
1479  /* Check the FLAG bit is set or not */
1480  if (EMIOS_DRV_ReadFlagState(2U, 14U) == true)
1481  {
1482  OC_IrqHandler(2U, 14U);
1483  }
1484 
1485  /* Check the FLAG bit is set or not */
1486  if (EMIOS_DRV_ReadFlagState(2U, 15U) == true)
1487  {
1488  OC_IrqHandler(2U, 15U);
1489  }
1490 }
1491 
1492 /* The interrupt function for channel 16, 17 on EMIOS2 */
1493 void EMIOS2_16_17_IRQHandler(void)
1494 {
1495  /* Check the FLAG bit is set or not */
1496  if (EMIOS_DRV_ReadFlagState(2U, 16U) == true)
1497  {
1498  OC_IrqHandler(2U, 16U);
1499  }
1500 
1501  /* Check the FLAG bit is set or not */
1502  if (EMIOS_DRV_ReadFlagState(2U, 17U) == true)
1503  {
1504  OC_IrqHandler(2U, 17U);
1505  }
1506 }
1507 
1508 /* The interrupt function for channel 18, 19 on EMIOS2 */
1509 void EMIOS2_18_19_IRQHandler(void)
1510 {
1511  /* Check the FLAG bit is set or not */
1512  if (EMIOS_DRV_ReadFlagState(2U, 18U) == true)
1513  {
1514  OC_IrqHandler(2U, 18U);
1515  }
1516 
1517  /* Check the FLAG bit is set or not */
1518  if (EMIOS_DRV_ReadFlagState(2U, 19U) == true)
1519  {
1520  OC_IrqHandler(2U, 19U);
1521  }
1522 }
1523 
1524 /* The interrupt function for channel 20, 21 on EMIOS2 */
1525 void EMIOS2_20_21_IRQHandler(void)
1526 {
1527  /* Check the FLAG bit is set or not */
1528  if (EMIOS_DRV_ReadFlagState(2U, 20U) == true)
1529  {
1530  OC_IrqHandler(2U, 20U);
1531  }
1532 
1533  /* Check the FLAG bit is set or not */
1534  if (EMIOS_DRV_ReadFlagState(2U, 21U) == true)
1535  {
1536  OC_IrqHandler(2U, 21U);
1537  }
1538 }
1539 
1540 /* The interrupt function for channel 22, 23 on EMIOS2 */
1541 void EMIOS2_22_23_IRQHandler(void)
1542 {
1543  /* Check the FLAG bit is set or not */
1544  if (EMIOS_DRV_ReadFlagState(2U, 22U) == true)
1545  {
1546  OC_IrqHandler(2U, 22U);
1547  }
1548 
1549  /* Check the FLAG bit is set or not */
1550  if (EMIOS_DRV_ReadFlagState(2U, 23U) == true)
1551  {
1552  OC_IrqHandler(2U, 23U);
1553  }
1554 }
1555 
1556 /* The interrupt function for channel 24, 25 on EMIOS2 */
1557 void EMIOS2_24_25_IRQHandler(void)
1558 {
1559  /* Check the FLAG bit is set or not */
1560  if (EMIOS_DRV_ReadFlagState(2U, 24U) == true)
1561  {
1562  OC_IrqHandler(2U, 24U);
1563  }
1564 
1565  /* Check the FLAG bit is set or not */
1566  if (EMIOS_DRV_ReadFlagState(2U, 25U) == true)
1567  {
1568  OC_IrqHandler(2U, 25U);
1569  }
1570 }
1571 
1572 /* The interrupt function for channel 26, 27 on EMIOS2 */
1573 void EMIOS2_26_27_IRQHandler(void)
1574 {
1575  /* Check the FLAG bit is set or not */
1576  if (EMIOS_DRV_ReadFlagState(2U, 26U) == true)
1577  {
1578  OC_IrqHandler(2U, 26U);
1579  }
1580 
1581  /* Check the FLAG bit is set or not */
1582  if (EMIOS_DRV_ReadFlagState(2U, 27U) == true)
1583  {
1584  OC_IrqHandler(2U, 27U);
1585  }
1586 }
1587 
1588 /* The interrupt function for channel 28, 29 on EMIOS2 */
1589 void EMIOS2_28_29_IRQHandler(void)
1590 {
1591  /* Check the FLAG bit is set or not */
1592  if (EMIOS_DRV_ReadFlagState(2U, 28U) == true)
1593  {
1594  OC_IrqHandler(2U, 28U);
1595  }
1596 
1597  /* Check the FLAG bit is set or not */
1598  if (EMIOS_DRV_ReadFlagState(2U, 29U) == true)
1599  {
1600  OC_IrqHandler(2U, 29U);
1601  }
1602 }
1603 
1604 /* The interrupt function for channel 30, 31 on EMIOS2 */
1605 void EMIOS2_30_31_IRQHandler(void)
1606 {
1607  /* Check the FLAG bit is set or not */
1608  if (EMIOS_DRV_ReadFlagState(2U, 30U) == true)
1609  {
1610  OC_IrqHandler(2U, 30U);
1611  }
1612 
1613  /* Check the FLAG bit is set or not */
1614  if (EMIOS_DRV_ReadFlagState(2U, 31U) == true)
1615  {
1616  OC_IrqHandler(2U, 31U);
1617  }
1618 }
1619 #endif /* End of (OC_PAL_INSTANCES_MAX > 2U) */
1620 
1621 #endif /* End of defined(OC_PAL_OVER_EMIOS) */
1622 
1623 
1624 #if (defined(OC_PAL_OVER_ETIMER))
1625 #if (OC_PAL_INSTANCES_MAX > 0U)
1626 void ETIMER0_TC0IR_IRQHandler(void)
1627 {
1628  OC_IrqHandler(0U, 0U);
1629 }
1630 
1631 void ETIMER0_TC1IR_IRQHandler(void)
1632 {
1633  OC_IrqHandler(0U, 1U);
1634 }
1635 
1636 void ETIMER0_TC2IR_IRQHandler(void)
1637 {
1638  OC_IrqHandler(0U, 2U);
1639 }
1640 
1641 void ETIMER0_TC3IR_IRQHandler(void)
1642 {
1643  OC_IrqHandler(0U, 3U);
1644 }
1645 
1646 void ETIMER0_TC4IR_IRQHandler(void)
1647 {
1648  OC_IrqHandler(0U, 4U);
1649 }
1650 
1651 void ETIMER0_TC5IR_IRQHandler(void)
1652 {
1653  OC_IrqHandler(0U, 5U);
1654 }
1655 #endif
1656 
1657 #if (OC_PAL_INSTANCES_MAX > 1U)
1658 void ETIMER1_TC0IR_IRQHandler(void)
1659 {
1660  OC_IrqHandler(1U, 0U);
1661 }
1662 
1663 void ETIMER1_TC1IR_IRQHandler(void)
1664 {
1665  OC_IrqHandler(1U, 1U);
1666 }
1667 
1668 void ETIMER1_TC2IR_IRQHandler(void)
1669 {
1670  OC_IrqHandler(1U, 2U);
1671 }
1672 
1673 void ETIMER1_TC3IR_IRQHandler(void)
1674 {
1675  OC_IrqHandler(1U, 3U);
1676 }
1677 
1678 void ETIMER1_TC4IR_IRQHandler(void)
1679 {
1680  OC_IrqHandler(1U, 4U);
1681 }
1682 
1683 void ETIMER1_TC5IR_IRQHandler(void)
1684 {
1685  OC_IrqHandler(1U, 5U);
1686 }
1687 #endif
1688 
1689 #if (OC_PAL_INSTANCES_MAX > 2U)
1690 void ETIMER2_TC0IR_IRQHandler(void)
1691 {
1692  OC_IrqHandler(2U, 0U);
1693 }
1694 
1695 void ETIMER2_TC1IR_IRQHandler(void)
1696 {
1697  OC_IrqHandler(2U, 1U);
1698 }
1699 
1700 void ETIMER2_TC2IR_IRQHandler(void)
1701 {
1702  OC_IrqHandler(2U, 2U);
1703 }
1704 
1705 void ETIMER2_TC3IR_IRQHandler(void)
1706 {
1707  OC_IrqHandler(2U, 3U);
1708 }
1709 
1710 void ETIMER2_TC4IR_IRQHandler(void)
1711 {
1712  OC_IrqHandler(2U, 4U);
1713 }
1714 
1715 void ETIMER2_TC5IR_IRQHandler(void)
1716 {
1717  OC_IrqHandler(2U, 5U);
1718 }
1719 #endif
1720 #endif /* defined(OC_PAL_OVER_ETIMER) */
1721 /*******************************************************************************
1722  * EOF
1723  ******************************************************************************/
#define FTM_CONTROLS_COUNT
Definition: S32K118.h:3822
static bool FTM_DRV_GetChnEventStatus(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel event status.
Definition: ftm_common.h:766
void OC_IrqHandler(uint32_t instance, uint8_t channel)
Definition: oc_pal.c:1194
uint32_t FTM_DRV_GetEnabledInterrupts(uint32_t instance)
This function will get the enabled FTM interrupts.
Definition: ftm_common.c:585
void(* isr_t)(void)
Interrupt handler type.
FTM_Type *const g_ftmBase[(2u)]
Table of base addresses for FTM instances.
Definition: ftm_common.c:71