mpu_pal.h
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1 /*
2  * Copyright 2017-2018 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
28 #ifndef MPU_PAL_H
29 #define MPU_PAL_H
30 
31 #include "status.h"
32 #include "mpu_pal_mapping.h"
33 
41 /*******************************************************************************
42  * Definitions
43  ******************************************************************************/
48 typedef enum
49 {
53 
58 typedef enum
59 {
65 
70 typedef struct
71 {
72  uint8_t master;
73  bool overrun;
76  uint32_t accessCtr;
77  uint32_t addr;
78  uint8_t processId;
80 
81 #if defined(MPU_OVER_MPU)
82 
129 typedef mpu_access_rights_t mpu_access_permission_t; /* Should be made enum inside MPU driver */
130 #elif defined(MPU_OVER_SMPU)
131 typedef enum
132 {
133  MPU_NONE = 0U,
134  MPU_W_OR_SET_1 = 1U,
135  MPU_R_OR_SET_2 = 2U,
136  MPU_RW_OR_SET_3 = 3U
137 } mpu_access_permission_t;
138 #endif /* defined(MPU_OVER_MPU) & defined(MPU_OVER_SMPU) */
139 
144 typedef struct
145 {
146  uint8_t masterNum;
147  mpu_access_permission_t accessRight;
149 
154 typedef struct
155 {
156  uint32_t startAddr;
157  uint32_t endAddr;
159  uint8_t processIdEnable;
163  uint8_t processIdMask;
165  void *extension;
168 
169 #if defined(MPU_OVER_SMPU)
170  #if (FEATURE_SMPU_HAS_SPECIFIC_ACCESS_RIGHT_COUNT != 0U)
171 
182  typedef enum
183  {
184  MPU_SUPERVISOR_NONE_USER_NONE = 0x00U,
185  MPU_SUPERVISOR_NONE_USER_X = 0x01U,
186  MPU_SUPERVISOR_NONE_USER_W = 0x02U,
187  MPU_SUPERVISOR_NONE_USER_WX = 0x03U,
188  MPU_SUPERVISOR_NONE_USER_R = 0x04U,
189  MPU_SUPERVISOR_NONE_USER_RX = 0x05U,
190  MPU_SUPERVISOR_NONE_USER_RW = 0x06U,
191  MPU_SUPERVISOR_NONE_USER_RWX = 0x07U,
192  MPU_SUPERVISOR_X_USER_NONE = 0x08U,
193  MPU_SUPERVISOR_X_USER_X = 0x09U,
194  MPU_SUPERVISOR_X_USER_W = 0x0AU,
195  MPU_SUPERVISOR_X_USER_WX = 0x0BU,
196  MPU_SUPERVISOR_X_USER_R = 0x0CU,
197  MPU_SUPERVISOR_X_USER_RX = 0x0DU,
198  MPU_SUPERVISOR_X_USER_RW = 0x0EU,
199  MPU_SUPERVISOR_X_USER_RWX = 0x0FU,
200  MPU_SUPERVISOR_W_USER_NONE = 0x10U,
201  MPU_SUPERVISOR_W_USER_X = 0x11U,
202  MPU_SUPERVISOR_W_USER_W = 0x12U,
203  MPU_SUPERVISOR_W_USER_WX = 0x13U,
204  MPU_SUPERVISOR_W_USER_R = 0x14U,
205  MPU_SUPERVISOR_W_USER_RX = 0x15U,
206  MPU_SUPERVISOR_W_USER_RW = 0x16U,
207  MPU_SUPERVISOR_W_USER_RWX = 0x17U,
208  MPU_SUPERVISOR_WX_USER_NONE = 0x18U,
209  MPU_SUPERVISOR_WX_USER_X = 0x19U,
210  MPU_SUPERVISOR_WX_USER_W = 0x1AU,
211  MPU_SUPERVISOR_WX_USER_WX = 0x1BU,
212  MPU_SUPERVISOR_WX_USER_R = 0x1CU,
213  MPU_SUPERVISOR_WX_USER_RX = 0x1DU,
214  MPU_SUPERVISOR_WX_USER_RW = 0x1EU,
215  MPU_SUPERVISOR_WX_USER_RWX = 0x1FU,
216  MPU_SUPERVISOR_R_USER_NONE = 0x20U,
217  MPU_SUPERVISOR_R_USER_X = 0x21U,
218  MPU_SUPERVISOR_R_USER_W = 0x22U,
219  MPU_SUPERVISOR_R_USER_WX = 0x23U,
220  MPU_SUPERVISOR_R_USER_R = 0x24U,
221  MPU_SUPERVISOR_R_USER_RX = 0x25U,
222  MPU_SUPERVISOR_R_USER_RW = 0x26U,
223  MPU_SUPERVISOR_R_USER_RWX = 0x27U,
225  MPU_SUPERVISOR_RX_USER_X = 0x29U,
226  MPU_SUPERVISOR_RX_USER_W = 0x2AU,
227  MPU_SUPERVISOR_RX_USER_WX = 0x2BU,
228  MPU_SUPERVISOR_RX_USER_R = 0x2CU,
229  MPU_SUPERVISOR_RX_USER_RX = 0x2DU,
230  MPU_SUPERVISOR_RX_USER_RW = 0x2EU,
233  MPU_SUPERVISOR_RW_USER_X = 0x31U,
234  MPU_SUPERVISOR_RW_USER_W = 0x32U,
235  MPU_SUPERVISOR_RW_USER_WX = 0x33U,
236  MPU_SUPERVISOR_RW_USER_R = 0x34U,
237  MPU_SUPERVISOR_RW_USER_RX = 0x35U,
238  MPU_SUPERVISOR_RW_USER_RW = 0x36U,
241  MPU_SUPERVISOR_RWX_USER_X = 0x39U,
242  MPU_SUPERVISOR_RWX_USER_W = 0x3AU,
244  MPU_SUPERVISOR_RWX_USER_R = 0x3CU,
248  } mpu_specific_access_permission_t;
249  #endif
250 
255 typedef enum
256 {
257  MPU_UNLOCK = 0U,
258 #if FEATURE_SMPU_HAS_OWNER_LOCK
259  MPU_OWNER_LOCK = 1U,
261 #endif/* FEATURE_SMPU_HAS_OWNER_LOCK */
262  MPU_ALL_LOCK = 3U
263 } mpu_lock_t;
264 
269 typedef struct
270 {
271  uint8_t regionNum;
272 #if FEATURE_SMPU_HAS_OWNER_LOCK
273  uint8_t masterOwner;
274 #endif /* FEATURE_SMPU_HAS_OWNER_LOCK */
275  mpu_lock_t lockConfig;
276 } mpu_region_lock_t;
277 
282 typedef struct
283 {
284 #if (FEATURE_SMPU_HAS_SPECIFIC_ACCESS_RIGHT_COUNT != 0U)
285  bool specAccessEnable;
286  const mpu_specific_access_permission_t *specAccessSet;
287 #endif
288  bool cacheInhibitEnable;
289  mpu_lock_t lockConfig;
290 } mpu_extension_smpu_region_t;
291 #endif /* defined(MPU_OVER_SMPU) */
292 
293 /*******************************************************************************
294  * API
295  ******************************************************************************/
301 #if defined(__cplusplus)
302 extern "C" {
303 #endif
304 
319 status_t MPU_Init(const mpu_instance_t * const instance,
320  uint8_t regionCnt,
321  const mpu_region_config_t * configPtr);
322 
334 status_t MPU_Deinit(const mpu_instance_t * const instance);
335 
348 status_t MPU_GetDefautRegionConfig(const mpu_instance_t * const instance,
349  mpu_master_access_permission_t * masterAccRight,
350  mpu_region_config_t * regionConfig);
351 
365 status_t MPU_UpdateRegion(const mpu_instance_t * const instance,
366  uint8_t regionNum,
367  const mpu_region_config_t * configPtr);
368 
383 status_t MPU_EnableRegion(const mpu_instance_t * const instance,
384  uint8_t regionNum,
385  bool enable);
386 
401 bool MPU_GetError(const mpu_instance_t * const instance,
402  uint8_t channel,
403  mpu_error_info_t * errPtr);
404 
405 #if defined(MPU_OVER_SMPU)
406 
418 status_t MPU_UpdateRegionLock(const mpu_instance_t * const instance,
419  uint8_t regionNum,
420  mpu_lock_t lockConfig);
421 
432 status_t MPU_GetRegionLockInfo(const mpu_instance_t * const instance,
433  uint8_t regionNum,
434  mpu_region_lock_t * regionLock);
435 #endif /* defined(MPU_OVER_SMPU) */
436 
437 
440 #if defined(__cplusplus)
441 }
442 #endif
443 
446 #endif /* MPU_PAL_H */
447 /*******************************************************************************
448  * EOF
449  ******************************************************************************/
uint8_t processIdentifier
Definition: mpu_pal.h:162
uint32_t endAddr
Definition: mpu_pal.h:157
MPU master access permission. Implements : mpu_master_access_permission_t_Class.
Definition: mpu_pal.h:144
Structure storing PAL instance information.
uint8_t processIdEnable
Definition: mpu_pal.h:159
mpu_access_permission_t accessRight
Definition: mpu_pal.h:147
uint32_t addr
Definition: mpu_pal.h:77
status_t MPU_Init(const mpu_instance_t *const instance, uint8_t regionCnt, const mpu_region_config_t *configPtr)
Initializes memory protection unit by allocating regions and granting access rights for masters...
Definition: mpu_pal.c:216
status_t MPU_Deinit(const mpu_instance_t *const instance)
De-initializes memory protection unit by reseting all regions and masters to default and disable modu...
Definition: mpu_pal.c:279
mpu_access_rights_t
MPU access rights. Code Supervisor User Description MPU_SUPERVISOR_RWX_USER_NONE r w x - - - Allow R...
Definition: mpu_driver.h:124
uint8_t processId
Definition: mpu_pal.h:78
status_t MPU_UpdateRegion(const mpu_instance_t *const instance, uint8_t regionNum, const mpu_region_config_t *configPtr)
Updates region configuration.
Definition: mpu_pal.c:383
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
status_t MPU_GetDefautRegionConfig(const mpu_instance_t *const instance, mpu_master_access_permission_t *masterAccRight, mpu_region_config_t *regionConfig)
Gets default region configuration. Grants all access rights for masters; disable PID and cache; unloc...
Definition: mpu_pal.c:314
uint32_t startAddr
Definition: mpu_pal.h:156
MPU detail error access info Implements : mpu_error_info_t_Class.
Definition: mpu_pal.h:70
uint32_t accessCtr
Definition: mpu_pal.h:76
mpu_error_access_type_t
MPU access error Implements : mpu_error_access_type_t_Class.
Definition: mpu_pal.h:48
mpu_error_attributes_t attributes
Definition: mpu_pal.h:74
mpu_error_access_type_t accessType
Definition: mpu_pal.h:75
uint8_t processIdMask
Definition: mpu_pal.h:163
const mpu_master_access_permission_t * masterAccRight
Definition: mpu_pal.h:158
status_t MPU_EnableRegion(const mpu_instance_t *const instance, uint8_t regionNum, bool enable)
Enables or disables an exist region configuration.
Definition: mpu_pal.c:428
mpu_error_attributes_t
MPU access error attributes Implements : mpu_error_attributes_t_Class.
Definition: mpu_pal.h:58
uint8_t master
Definition: mpu_pal.h:72
MPU region configuration structure. Implements : mpu_region_config_t_Class.
Definition: mpu_pal.h:154
bool MPU_GetError(const mpu_instance_t *const instance, uint8_t channel, mpu_error_info_t *errPtr)
Checks and gets the access error detail information then clear error flag if the error caused by a ma...
Definition: mpu_pal.c:465