#include "device_registers.h"
#include "sim_hw_access.h"
#include "scg_hw_access.h"
#include "pcc_hw_access.h"
#include "pmc_hw_access.h"
#include "smc_hw_access.h"
#include "clock_manager.h"
#include <stddef.h>
Go to the source code of this file.
Enumerations | |
enum | scg_system_clock_type_t { SCG_SYSTEM_CLOCK_CORE, SCG_SYSTEM_CLOCK_BUS, SCG_SYSTEM_CLOCK_SLOW, SCG_SYSTEM_CLOCK_MAX } |
SCG system clock type. Implements scg_system_clock_type_t_Class. More... | |
enum | scg_async_clock_type_t { SCG_ASYNC_CLOCK_DIV1 = 0U, SCG_ASYNC_CLOCK_DIV2 = 1U, SCG_ASYNC_CLOCK_MAX = 2U } |
SCG asynchronous clock type. Implements scg_async_clock_type_t_Class. More... | |
enum | scg_system_clock_mode_t { SCG_SYSTEM_CLOCK_MODE_CURRENT = 0U, SCG_SYSTEM_CLOCK_MODE_RUN = 1U, SCG_SYSTEM_CLOCK_MODE_VLPR = 2U, SCG_SYSTEM_CLOCK_MODE_HSRUN = 3U, SCG_SYSTEM_CLOCK_MODE_NONE } |
SCG system clock modes. Implements scg_system_clock_mode_t_Class. More... | |
Variables | |
uint32_t | g_TClkFreq [NUMBER_OF_TCLK_INPUTS] |
uint32_t | g_RtcClkInFreq |
RTC_CLKIN clock frequency. More... | |
uint32_t | g_xtal0ClkFreq |
EXTAL0 clock frequency. More... | |
const uint16_t | clockNameMappings [] = { 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 115 , 50 , 33 , 73 , 74 , 75 , 76 , 77 , 61 , 0 , 36 , 54 , 0 , 32 , 0 , 56 , 57 , 0 , 59 , 90 , 102 , 55 , 44 , 45 , 64 , 106 , 107 , 0 , 0 , } |
Clock name mappings Constant array storing the mappings between clock names and peripheral clock control indexes. If there is no peripheral clock control index for a clock name, then the corresponding value is PCC_INVALID_INDEX. More... | |
const uint8_t | peripheralFeaturesList [] = { ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (1U << 0U) | (1U << 6U) ), ( (1U << 0U) | (1U << 6U) ), ( (1U << 0U) | (1U << 6U) ), ( (1U << 0U) | (1U << 6U) ), ( (1U << 0U) | (1U << 6U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (0U) ), ( (1U << 5U) ), ( (1U << 5U) ), ( (1U << 5U) ), ( (1U << 5U) ), ( (1U << 5U) ), ( (1U << 5U) ), ( (1U << 5U) ), ( (1U << 5U) ), ( (1U << 5U) ), ( (0U) ), ( (1U << 6U) ), ( (1U << 6U) ), ( (0U) ), ( (1U << 7U) ), ( (0U) ), ( (1U << 3U) | (1U << 6U) ), ( (1U << 3U) | (1U << 6U) ), ( (0U) ), ( (1U << 4U) | (1U << 5U) ), ( (1U << 4U) | (1U << 5U) ), ( (1U << 4U) | (1U << 5U) ), ( (1U << 4U) | (1U << 5U) ), ( (1U << 4U) | (1U << 5U) ), ( (1U << 4U) | (1U << 5U) ), ( (1U << 1U) | (1U << 2U) | (1U << 4U) | (1U << 5U) ), ( (1U << 4U) | (1U << 5U) ), ( (1U << 4U) | (1U << 5U) ), ( (0U) ), ( (0U) ), } |
Peripheral features list Constant array storing the mappings between clock names of the peripherals and feature lists. More... | |
#define CLOCK_MAX_FREQUENCIES_RUN_MODE |
Definition at line 139 of file clock_S32K1xx.c.
#define CLOCK_MAX_FREQUENCIES_VLPR_MODE |
Definition at line 129 of file clock_S32K1xx.c.
#define CLOCK_PERIPHERALS_COUNT (TMP_FTFC + TMP_DMAMUX + TMP_FlexCAN0 + TMP_FlexCAN1 + TMP_FTM3 + TMP_ADC1 + TMP_FlexCAN2 + TMP_LPSPI0 + TMP_LPSPI1 + TMP_LPSPI2 + TMP_PDB1 + TMP_CRC + TMP_PDB0 + TMP_LPIT + TMP_FTM0 + TMP_FTM1 + TMP_FTM2 + TMP_ADC0 + TMP_RTC + TMP_LPTMR0 + TMP_PORTA + TMP_PORTB + TMP_PORTC + TMP_PORTD + TMP_PORTE + TMP_SAI0 + TMP_SAI1 + TMP_FlexIO + TMP_EWM + TMP_LPI2C0 + TMP_LPI2C1 + TMP_LPUART0 + TMP_LPUART1 + TMP_LPUART2 + TMP_FTM4 + TMP_FTM5 + TMP_FTM6 + TMP_FTM7 + TMP_CMP0 + TMP_QSPI + TMP_ENET) |
Definition at line 371 of file clock_S32K1xx.c.
#define HIGH_SPEED_RUNNING_MODE (1UL << 7U) |
Definition at line 123 of file clock_S32K1xx.c.
#define LPO_128K_FREQUENCY 128000UL |
Definition at line 108 of file clock_S32K1xx.c.
#define LPO_1K_FREQUENCY 1000UL |
Definition at line 118 of file clock_S32K1xx.c.
#define LPO_32K_FREQUENCY 32000UL |
Definition at line 113 of file clock_S32K1xx.c.
#define MODES_MAX_NO 7U |
Definition at line 128 of file clock_S32K1xx.c.
#define RUN_SPEED_RUNNING_MODE (1UL << 0U) |
Definition at line 124 of file clock_S32K1xx.c.
#define TMP_ADC0 1U |
Definition at line 251 of file clock_S32K1xx.c.
#define TMP_ADC1 0U |
Definition at line 193 of file clock_S32K1xx.c.
#define TMP_CMP0 1U |
Definition at line 356 of file clock_S32K1xx.c.
#define TMP_CRC 1U |
Definition at line 221 of file clock_S32K1xx.c.
#define TMP_DMAMUX 1U |
Definition at line 171 of file clock_S32K1xx.c.
#define TMP_ENET 0U |
Definition at line 368 of file clock_S32K1xx.c.
#define TMP_EWM 0U |
Definition at line 308 of file clock_S32K1xx.c.
#define TMP_FlexCAN0 1U |
Definition at line 176 of file clock_S32K1xx.c.
#define TMP_FlexCAN1 0U |
Definition at line 183 of file clock_S32K1xx.c.
#define TMP_FlexCAN2 0U |
Definition at line 198 of file clock_S32K1xx.c.
#define TMP_FlexIO 1U |
Definition at line 301 of file clock_S32K1xx.c.
#define TMP_FTFC 1U |
Definition at line 166 of file clock_S32K1xx.c.
#define TMP_FTM0 1U |
Definition at line 236 of file clock_S32K1xx.c.
#define TMP_FTM1 1U |
Definition at line 241 of file clock_S32K1xx.c.
#define TMP_FTM2 0U |
Definition at line 248 of file clock_S32K1xx.c.
#define TMP_FTM3 0U |
Definition at line 188 of file clock_S32K1xx.c.
#define TMP_FTM4 0U |
Definition at line 338 of file clock_S32K1xx.c.
#define TMP_FTM5 0U |
Definition at line 343 of file clock_S32K1xx.c.
#define TMP_FTM6 0U |
Definition at line 348 of file clock_S32K1xx.c.
#define TMP_FTM7 0U |
Definition at line 353 of file clock_S32K1xx.c.
#define TMP_LPI2C0 1U |
Definition at line 311 of file clock_S32K1xx.c.
#define TMP_LPI2C1 0U |
Definition at line 318 of file clock_S32K1xx.c.
#define TMP_LPIT 1U |
Definition at line 231 of file clock_S32K1xx.c.
#define TMP_LPSPI0 1U |
Definition at line 201 of file clock_S32K1xx.c.
#define TMP_LPSPI1 1U |
Definition at line 206 of file clock_S32K1xx.c.
#define TMP_LPSPI2 0U |
Definition at line 213 of file clock_S32K1xx.c.
#define TMP_LPTMR0 1U |
Definition at line 261 of file clock_S32K1xx.c.
#define TMP_LPUART0 1U |
Definition at line 321 of file clock_S32K1xx.c.
#define TMP_LPUART1 1U |
Definition at line 326 of file clock_S32K1xx.c.
#define TMP_LPUART2 0U |
Definition at line 333 of file clock_S32K1xx.c.
#define TMP_PDB0 1U |
Definition at line 226 of file clock_S32K1xx.c.
#define TMP_PDB1 0U |
Definition at line 218 of file clock_S32K1xx.c.
#define TMP_PORTA 1U |
Definition at line 266 of file clock_S32K1xx.c.
#define TMP_PORTB 1U |
Definition at line 271 of file clock_S32K1xx.c.
#define TMP_PORTC 1U |
Definition at line 276 of file clock_S32K1xx.c.
#define TMP_PORTD 1U |
Definition at line 281 of file clock_S32K1xx.c.
#define TMP_PORTE 1U |
Definition at line 286 of file clock_S32K1xx.c.
#define TMP_QSPI 0U |
Definition at line 363 of file clock_S32K1xx.c.
#define TMP_RTC 1U |
Definition at line 256 of file clock_S32K1xx.c.
#define TMP_SAI0 0U |
Definition at line 293 of file clock_S32K1xx.c.
#define TMP_SAI1 0U |
Definition at line 298 of file clock_S32K1xx.c.
#define VLPR_SPEED_RUNNING_MODE (1UL << 2U) |
Definition at line 125 of file clock_S32K1xx.c.
SCG asynchronous clock type. Implements scg_async_clock_type_t_Class.
Enumerator | |
---|---|
SCG_ASYNC_CLOCK_DIV1 |
Clock divider 1 |
SCG_ASYNC_CLOCK_DIV2 |
Clock divider 2 |
SCG_ASYNC_CLOCK_MAX |
Max value. |
Definition at line 402 of file clock_S32K1xx.c.
SCG system clock modes. Implements scg_system_clock_mode_t_Class.
Definition at line 413 of file clock_S32K1xx.c.
SCG system clock type. Implements scg_system_clock_type_t_Class.
Enumerator | |
---|---|
SCG_SYSTEM_CLOCK_CORE |
Core clock. |
SCG_SYSTEM_CLOCK_BUS |
BUS clock. |
SCG_SYSTEM_CLOCK_SLOW |
System slow clock. |
SCG_SYSTEM_CLOCK_MAX |
Max value. |
Definition at line 390 of file clock_S32K1xx.c.
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Definition at line 2077 of file clock_S32K1xx.c.
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< Dividers for SIRC
< Dividers for FIRC
< Dividers for SOSC
< Dividers for SPLL
Definition at line 2389 of file clock_S32K1xx.c.
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Definition at line 2004 of file clock_S32K1xx.c.
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Definition at line 2149 of file clock_S32K1xx.c.
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< Dividers for SIRC
< Dividers for FIRC
< Dividers for SOSC
< Dividers for SPLL
Definition at line 2352 of file clock_S32K1xx.c.
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Definition at line 3022 of file clock_S32K1xx.c.
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Definition at line 1780 of file clock_S32K1xx.c.
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Definition at line 2969 of file clock_S32K1xx.c.
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< Initialize
< SIRCSTEN
< SIRCLPEN
< LK
< RANGE - High range (8 MHz)
< SIRCDIV1
< SIRCDIV2
< Initialize
< FIRCREGOFF
< LK
< RANGE
< FIRCDIV1
< FIRCDIV2
< Initialize
< RTC_CLKIN
< Initialize
< Frequency
< SOSCCM
< LK
< EREFS
< HGO
< RANGE
< SOSCDIV1
< SOSCDIV2
< Initialize
< SPLLCM
< LK
< PREDIV
< MULT
< SOURCE
< SPLLDIV1
< SPLLDIV2
< Initialize
< SCG CLKOUTSEL
< Initialize
< RCCR - Run Clock Control Register
< SCS
< DIVCORE
< DIVBUS
< DIVSLOW
< VCCR - VLPR Clock Control Register
< SCS
< DIVCORE
< DIVBUS
< DIVSLOW
< Peripheral clock control configurations
< Number of the peripheral clock control configurations
< Clock Out configuration.
< Initialize
< CLKOUTEN
< CLKOUTSEL
< CLKOUTDIV
< Low Power Clock configuration.
< Initialize
< LPO1KCLKEN
< LPO32KCLKEN
< LPOCLKSEL
< RTCCLKSEL
< Platform Gate Clock configuration.
< Initialize
< CGCMSCM
< CGCMPU
< CGCDMA
< CGCERM
< CGCMEIM
< Quad Spi Internal Reference Clock Gating.
< Qspi reference clock gating
< TCLK CLOCK configuration.
< Initialize
< TCLK0
< TCLK0
< TCLK0
< Debug trace Clock Configuration.
< Initialize
< TRACEDIVEN
< TRACECLK_SEL
< TRACEDIV
< TRACEFRAC
< Low Power Clock configuration.
< Initialize
< Enable/disable LPO
< Trimming value for LPO
Definition at line 751 of file clock_S32K1xx.c.
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Definition at line 2825 of file clock_S32K1xx.c.
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Definition at line 2881 of file clock_S32K1xx.c.
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Definition at line 1611 of file clock_S32K1xx.c.
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Definition at line 1733 of file clock_S32K1xx.c.
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Definition at line 1936 of file clock_S32K1xx.c.
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Definition at line 1248 of file clock_S32K1xx.c.
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Definition at line 1860 of file clock_S32K1xx.c.
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Definition at line 1416 of file clock_S32K1xx.c.
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Definition at line 1972 of file clock_S32K1xx.c.
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Definition at line 2806 of file clock_S32K1xx.c.
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Definition at line 2676 of file clock_S32K1xx.c.
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Definition at line 2787 of file clock_S32K1xx.c.
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Definition at line 2521 of file clock_S32K1xx.c.
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Definition at line 625 of file clock_S32K1xx.c.
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Definition at line 727 of file clock_S32K1xx.c.
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Definition at line 563 of file clock_S32K1xx.c.
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Definition at line 656 of file clock_S32K1xx.c.
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< Invalid entry
< Maximum frequencies when system clock is SOSC
< Maximum frequencies when system clock is SIRC
< Maximum frequencies when system clock is FIRC
< Invalid entry
< Invalid entry
< Maximum frequencies when system clock is SPLL
< Invalid entry
< Maximum frequencies when system clock is SOSC
< Maximum frequencies when system clock is SIRC
< Maximum frequencies when system clock is FIRC
< Invalid entry
< Invalid entry
< Maximum frequencies when system clock is SPLL
< Run mode.
< Very Low Power Run mode.
Definition at line 2575 of file clock_S32K1xx.c.
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Definition at line 1813 of file clock_S32K1xx.c.
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< Dividers for SIRC
< Dividers for FIRC
< Dividers for SOSC
< Dividers for SPLL
Definition at line 2912 of file clock_S32K1xx.c.
const uint16_t clockNameMappings[] = { 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 115 , 50 , 33 , 73 , 74 , 75 , 76 , 77 , 61 , 0 , 36 , 54 , 0 , 32 , 0 , 56 , 57 , 0 , 59 , 90 , 102 , 55 , 44 , 45 , 64 , 106 , 107 , 0 , 0 , } |
Clock name mappings Constant array storing the mappings between clock names and peripheral clock control indexes. If there is no peripheral clock control index for a clock name, then the corresponding value is PCC_INVALID_INDEX.
Definition at line 379 of file clock_S32K1xx.c.