36 #if defined(FEATURE_PINS_DRIVER_USING_PORT)
43 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
69 #if FEATURE_PINS_HAS_PULL_SELECTION
82 #if FEATURE_PINS_HAS_OPEN_DRAIN
89 PORT_OPEN_DRAIN_DISABLED = 0U,
90 PORT_OPEN_DRAIN_ENABLED = 1U
94 #if FEATURE_PINS_HAS_DRIVE_STRENGTH
101 #if FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL
102 PORT_STRENGTH_DISABLED = 0U,
104 PORT_STR1_DRIVE_STRENGTH = 1U,
105 PORT_STR2_DRIVE_STRENGTH = 2U,
106 PORT_STR3_DRIVE_STRENGTH = 3U,
107 PORT_STR4_DRIVE_STRENGTH = 4U,
108 PORT_STR5_DRIVE_STRENGTH = 5U,
109 PORT_STR6_DRIVE_STRENGTH = 6U,
110 PORT_STR7_DRIVE_STRENGTH = 7U,
113 PORT_LOW_DRIVE_STRENGTH = 0U,
114 PORT_HIGH_DRIVE_STRENGTH = 1U
119 #ifdef FEATURE_PINS_DRIVER_USING_PORT
146 #if FEATURE_PORT_HAS_FLAG_SET_ONLY
147 PORT_FLAG_RISING_EDGE = 0x5U,
148 PORT_FLAG_FALLING_EDGE = 0x6U,
149 PORT_FLAG_EITHER_EDGE = 0x7U,
156 #if FEATURE_PORT_HAS_TRIGGER_OUT
157 PORT_HIGH_TRIGGER_OUT = 0xDU,
158 PORT_LOW_TRIGGER_OUT = 0xEU
162 #if FEATURE_PINS_HAS_SLEW_RATE
169 PORT_FAST_SLEW_RATE = 0U,
170 PORT_SLOW_SLEW_RATE = 1U
204 #if FEATURE_PINS_HAS_OVER_CURRENT
211 PORT_OVER_CURRENT_DISABLED = 0U,
212 PORT_OVER_CURRENT_INT_DISABLED = 1U,
213 PORT_OVER_CURRENT_INT_ENABLED = 2U
214 } port_over_current_config_t;
217 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
218 #if FEATURE_SIUL2_HAS_DDR_PAD
227 DDR_DDR3_MODE = 0x0U,
228 DDR_LPDDR2_MODE = 0x2U
241 DDR_MIN_DELAY = 0x0U,
242 DDR_50PS_DELAY = 0x1U,
243 DDR_100PS_DELAY = 0x2U,
244 DDR_150PS_DELAY = 0x3U
245 } port_ddr_trim_delay_t;
257 DDR_NO_CRPOINT = 0x0U,
258 DDR_MINUS_CRPOINT = 0x1U,
259 DDR_PLUS_CRPOINT = 0x2U,
260 DDR_DOUBLE_CRPOINT = 0x3U
261 } port_ddr_crpoint_t;
274 DDR_LEFT_TRIM = 0x1U,
275 DDR_RIGHT_TRIM = 0x2U
284 PORT_DDR_INPUT_CMOS = 0U,
285 PORT_DDR_INPUT_DIFFERENTIAL = 1U
294 PORT_STR0_ON_DIE_TERMINATION = 0U,
295 PORT_STR1_ON_DIE_TERMINATION = 1U,
296 PORT_STR2_ON_DIE_TERMINATION = 2U,
297 PORT_STR3_ON_DIE_TERMINATION = 3U,
298 PORT_STR4_ON_DIE_TERMINATION = 4U,
299 PORT_STR5_ON_DIE_TERMINATION = 5U,
300 PORT_STR6_ON_DIE_TERMINATION = 6U,
301 PORT_STR7_ON_DIE_TERMINATION = 7U
302 } port_on_die_termination_t;
312 port_ddr_type_t ddrSelection;
313 port_ddr_trim_delay_t trimmingDelay;
314 port_ddr_crpoint_t crosspointAdjustment;
315 port_ddr_trim_t trimmingAdjustment;
336 PORT_MUX_ALT10 = 10U,
337 PORT_MUX_ALT11 = 11U,
338 PORT_MUX_ALT12 = 12U,
339 PORT_MUX_ALT13 = 13U,
340 PORT_MUX_ALT14 = 14U,
350 SIUL2_INT_DISABLE = 0x0U,
351 SIUL2_INT_RISING_EDGE = 0x1U,
352 SIUL2_INT_FALLING_EDGE = 0x2U,
353 SIUL2_INT_EITHER_EDGE = 0x3U
354 } siul2_interrupt_type_t;
356 #if FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA
363 SIUL2_INT_USING_INTERUPT = 0x0U,
364 SIUL2_INT_USING_DMA = 0x1U
365 } siul2_interrupt_dma_select_t;
375 siul2_interrupt_type_t intEdgeSel;
378 #if FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA
379 siul2_interrupt_dma_select_t intExeSel;
381 } siul2_interrupt_config_t;
389 PORT_OUTPUT_BUFFER_DISABLED = 0U,
390 PORT_OUTPUT_BUFFER_ENABLED = 1U
391 } port_output_buffer_t;
399 PORT_INPUT_BUFFER_DISABLED = 0U,
400 PORT_INPUT_BUFFER_ENABLED = 1U
401 } port_input_buffer_t;
403 #if FEATURE_SIUL2_HAS_HYSTERESIS
410 PORT_HYSTERESYS_CMOS = 0U,
411 PORT_HYSTERESYS_SCHMITT = 1U,
412 PORT_HYSTERESYS_DISABLED = 0U,
413 PORT_HYSTERESYS_ENABLED = 1U
417 #if FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT
424 PORT_INVERT_OUTPUT_DISABLED = 0U,
425 PORT_INVERT_OUTPUT_ENABLED = 1U
426 } port_invert_output_t;
429 #if FEATURE_SIUL2_HAS_INVERT_DATA_INPUT
436 PORT_INVERT_INPUT_DISABLED = 0U,
437 PORT_INVERT_INPUT_ENABLED = 1U
438 } port_invert_input_t;
441 #if FEATURE_SIUL2_HAS_PULL_KEEPER
448 PORT_PULL_KEEP_DISABLED = 0U,
449 PORT_PULL_KEEP_ENABLED = 1U
458 PORT_KEEPER_ENABLED = 0U,
459 PORT_PULL_ENABLED = 1U
460 } port_pull_keeper_select_t;
468 PORT_PULL_DOWN_ENABLED = 0U,
469 PORT_PULL_UP_MEDIUM = 1U,
470 PORT_PULL_UP_HIGH = 2U,
471 PORT_PULL_UP_LOW = 3U
472 } port_pull_up_down_t;
476 #if FEATURE_SIUL2_HAS_ANALOG_PAD
483 PORT_ANALOG_PAD_CONTROL_DISABLED = 0U,
484 PORT_ANALOG_PAD_CONTROL_ENABLED = 1U
494 PORT_INPUT_MUX_ALT0 = 0U,
495 PORT_INPUT_MUX_ALT1 = 1U,
496 PORT_INPUT_MUX_ALT2 = 2U,
497 PORT_INPUT_MUX_ALT3 = 3U,
498 PORT_INPUT_MUX_ALT4 = 4U,
499 PORT_INPUT_MUX_ALT5 = 5U,
500 PORT_INPUT_MUX_ALT6 = 6U,
501 PORT_INPUT_MUX_ALT7 = 7U,
502 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 4U)
503 PORT_INPUT_MUX_ALT8 = 8U,
504 PORT_INPUT_MUX_ALT9 = 9U,
505 PORT_INPUT_MUX_ALT10 = 10U,
506 PORT_INPUT_MUX_ALT11 = 11U,
507 PORT_INPUT_MUX_ALT12 = 12U,
508 PORT_INPUT_MUX_ALT13 = 13U,
509 PORT_INPUT_MUX_ALT14 = 14U,
510 PORT_INPUT_MUX_ALT15 = 15U,
512 PORT_INPUT_MUX_NO_INIT
521 PORT_SAFE_MODE_DISABLED = 0U,
523 PORT_SAFE_MODE_ENABLED = 1U
526 #if FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL
533 HALF_STRENGTH_WITH_SLEWRATE_CONTROL = 0u,
534 FULL_STRENGTH_WITH_SLEWRATE_CONTROL = 1u,
535 HALF_STRENGTH_WITHOUT_SLEWRATE_CONTROL = 2u,
536 FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL = 3u
537 } port_slew_rate_control_t;
540 #if FEATURE_PINS_HAS_SLEW_RATE
547 PORT_LOW_SLEW_RATE = 0U,
548 PORT_MEDIUM_SLEW_RATE = 1U,
549 PORT_MEDIUM_SLEW_RATE2 = 2U,
550 PORT_HIGH_SLEW_RATE = 3U
564 #ifdef FEATURE_PINS_DRIVER_USING_PORT
566 #elif defined FEATURE_PINS_DRIVER_USING_SIUL2
570 #if FEATURE_PINS_HAS_PULL_SELECTION
573 #if FEATURE_PINS_HAS_SLEW_RATE
574 port_slew_rate_t rateSelect;
576 #if FEATURE_PORT_HAS_PASSIVE_FILTER
579 #if FEATURE_PINS_HAS_OPEN_DRAIN
580 port_open_drain_t openDrain;
582 #if FEATURE_PINS_HAS_DRIVE_STRENGTH
586 #if FEATURE_PORT_HAS_PIN_CONTROL_LOCK
589 #ifdef FEATURE_PINS_DRIVER_USING_PORT
593 #if FEATURE_PINS_HAS_OVER_CURRENT
595 port_over_current_config_t overCurConfig;
600 #ifdef FEATURE_PINS_DRIVER_USING_SIUL2
601 port_input_mux_t inputMux[FEATURE_SIUL2_INPUT_MUX_WIDTH];
602 #if FEATURE_SIUL2_HAS_INVERT_DATA_INPUT
603 port_invert_input_t inputInvert[FEATURE_SIUL2_INPUT_MUX_WIDTH];
605 uint32_t inputMuxReg[FEATURE_SIUL2_INPUT_MUX_WIDTH];
606 port_output_buffer_t outputBuffer;
607 port_input_buffer_t inputBuffer;
609 #if FEATURE_SIUL2_HAS_SAFE_MODE_CONTROL
610 port_safe_mode_t safeMode;
612 #if FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL
613 port_slew_rate_control_t slewRateCtrlSel;
615 #if FEATURE_SIUL2_HAS_HYSTERESIS
616 port_hysteresis_t hysteresisSelect;
618 #if FEATURE_SIUL2_HAS_DDR_PAD
619 pin_ddr_config_t ddrConfiguration;
620 port_ddr_input_t inputMode;
621 port_on_die_termination_t odtSelect;
623 #if FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT
624 port_invert_output_t invertOutput;
626 #if FEATURE_SIUL2_HAS_PULL_KEEPER
627 port_pull_keep_t pullKeepEnable;
628 port_pull_keeper_select_t pullKeepSelect;
629 port_pull_up_down_t pullSelect;
631 #if FEATURE_SIUL2_HAS_ANALOG_PAD
632 port_analog_pad_t analogPadCtrlSel;
646 #if defined(__cplusplus)
663 #ifdef FEATURE_PINS_DRIVER_USING_PORT
664 #if FEATURE_PINS_HAS_PULL_SELECTION
827 #if FEATURE_PINS_HAS_OVER_CURRENT
836 uint32_t PINS_DRV_GetOverCurPortIntFlag(
const PORT_Type *
const base);
845 void PINS_DRV_ClearOverCurPortIntFlag(
PORT_Type *
const base);
905 #if FEATURE_PORT_HAS_INPUT_DISABLE
920 void PINS_DRV_SetPortInputDisable(
GPIO_Type *
const base,
939 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
940 #if FEATURE_PINS_HAS_PULL_SELECTION
966 void PINS_DRV_SetOutputBuffer(
PORT_Type *
const base,
982 void PINS_DRV_SetInputBuffer(
PORT_Type *
const base,
985 uint32_t inputMuxReg,
986 port_input_mux_t inputMux);
995 void PINS_DRV_ConfigIntFilterClock(uint8_t prescaler);
1004 void PINS_DRV_SetExInt(siul2_interrupt_config_t intConfig);
1013 void PINS_DRV_ClearPinExIntFlag(uint32_t eirqPinIdx);
1023 bool PINS_DRV_GetPinExIntFlag(uint32_t eirqPinIdx);
1030 void PINS_DRV_ClearExIntFlag(
void);
1039 uint32_t PINS_DRV_GetExIntFlag(
void);
1150 #if defined(__cplusplus)
rtc_interrupt_config_t * intConfig
status_t PINS_DRV_Init(uint32_t pinCount, const pin_settings_config_t config[])
Initializes the pins with the given configuration structure.
The digital filter configuration Implements : port_digital_filter_config_t_Class. ...
void PINS_DRV_SetGlobalIntControl(PORT_Type *const base, uint16_t pins, uint16_t value, port_global_control_pins_t halfPort)
Quickly configures multiple pins with the same interrupt configuration.
port_global_control_pins_t
The port global pin/interuppt control registers Implements : port_global_control_pins_t_Class.
uint32_t PINS_DRV_GetPortIntFlag(const PORT_Type *const base)
Reads the entire port interrupt status flag.
uint32_t pins_channel_type_t
Type of a GPIO channel representation Implements : pins_channel_type_t_Class.
port_pull_config_t pullConfig
port_interrupt_config_t intConfig
port_digital_filter_clock_t
Clock source for the digital input filters Implements : port_digital_filter_clock_t_Class.
void PINS_DRV_DisableDigitalFilter(PORT_Type *const base, uint32_t pin)
Disables digital filter for digital pin muxing.
void PINS_DRV_ClearPinIntFlagCmd(PORT_Type *const base, uint32_t pin)
Clears the individual pin-interrupt status flag.
port_drive_strength_t
Configures the drive strength. Implements : port_drive_strength_t_Class.
pins_channel_type_t PINS_DRV_GetPinsOutput(const GPIO_Type *const base)
Get the current output from a port.
port_interrupt_config_t
Configures the interrupt generation condition. Implements : port_interrupt_config_t_Class.
void PINS_DRV_SetPullSel(PORT_Type *const base, uint32_t pin, port_pull_config_t pullConfig)
Configures the internal resistor.
port_mux_t mux
Pin (C55: Out) mux selection.
void PINS_DRV_WritePin(GPIO_Type *const base, pins_channel_type_t pin, pins_level_type_t value)
Write a pin of a port with a given value.
void PINS_DRV_TogglePins(GPIO_Type *const base, pins_channel_type_t pins)
Toggle pins value.
void PINS_DRV_SetPinDirection(GPIO_Type *const base, pins_channel_type_t pin, pins_level_type_t direction)
Configure the direction for a certain pin from a port.
port_drive_strength_t driveSelect
Configures the drive strength.
void PINS_DRV_WritePins(GPIO_Type *const base, pins_channel_type_t pins)
Write all pins of a port.
void PINS_DRV_SetPinsDirection(GPIO_Type *const base, pins_channel_type_t pins)
Set the pins directions configuration for a port.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
port_data_direction_t
Configures the port data direction Implements : port_data_direction_t_Class.
port_pull_config_t
Internal resistor pull feature selection Implements : port_pull_config_t_Class.
void PINS_DRV_EnableDigitalFilter(PORT_Type *const base, uint32_t pin)
Enables digital filter for digital pin muxing.
Defines the converter configuration.
void PINS_DRV_SetPins(GPIO_Type *const base, pins_channel_type_t pins)
Write pins with 'Set' value.
void PINS_DRV_ConfigDigitalFilter(PORT_Type *const base, const port_digital_filter_config_t *const config)
Configures digital filter for port with given configuration.
port_mux_t
Configures the Pin mux selection Implements : port_mux_t_Class.
void PINS_DRV_SetGlobalPinControl(PORT_Type *const base, uint16_t pins, uint16_t value, port_global_control_pins_t halfPort)
Quickly configures multiple pins with the same pin configuration.
pins_level_type_t initValue
pins_channel_type_t PINS_DRV_ReadPins(const GPIO_Type *const base)
Read input pins.
port_data_direction_t direction
pins_channel_type_t PINS_DRV_GetPinsDirection(const GPIO_Type *const base)
Get the pins directions configuration for a port.
uint8_t pins_level_type_t
Type of a port levels representation. Implements : pins_level_type_t_Class.
port_interrupt_config_t PINS_DRV_GetPinIntSel(const PORT_Type *const base, uint32_t pin)
Gets the current port pin interrupt/DMA request configuration.
void PINS_DRV_SetMuxModeSel(PORT_Type *const base, uint32_t pin, port_mux_t mux)
Configures the pin muxing.
void PINS_DRV_ClearPortIntFlagCmd(PORT_Type *const base)
Clears the entire port interrupt status flag.
port_digital_filter_clock_t clock
void PINS_DRV_SetPinIntSel(PORT_Type *const base, uint32_t pin, port_interrupt_config_t intConfig)
Configures the port pin interrupt/DMA request.
void PINS_DRV_ClearPins(GPIO_Type *const base, pins_channel_type_t pins)
Write pins to 'Clear' value.