#include <platform/devices/S32K118/include/S32K118.h>

Data Fields

uint8_t RESERVED_0 [8]
 
volatile const uint16_t PLASC
 
volatile const uint16_t PLAMC
 
volatile uint32_t CPCR
 
uint8_t RESERVED_1 [32]
 
volatile uint32_t PID
 
uint8_t RESERVED_2 [12]
 
volatile uint32_t CPO
 
uint8_t RESERVED_3 [956]
 
volatile uint32_t LMDR [2u]
 
volatile uint32_t LMDR2
 
uint8_t RESERVED_4 [116]
 
volatile uint32_t LMPECR
 
uint8_t RESERVED_5 [4]
 
volatile uint32_t LMPEIR
 
uint8_t RESERVED_6 [4]
 
volatile const uint32_t LMFAR
 
volatile const uint32_t LMFATR
 
uint8_t RESERVED_7 [8]
 
volatile const uint32_t LMFDHR
 
volatile const uint32_t LMFDLR
 

Detailed Description

MCM - Register Layout Typedef

Definition at line 7043 of file S32K118.h.

Field Documentation

volatile uint32_t CPCR

< Defines 'read / write' permissions Core Platform Control Register, offset: 0xC

Definition at line 7047 of file S32K118.h.

volatile uint32_t CPO

< Defines 'read / write' permissions Compute Operation Control Register, offset: 0x40

Definition at line 7051 of file S32K118.h.

volatile uint32_t LMDR[2u]

< Defines 'read / write' permissions Local Memory Descriptor Register, array offset: 0x400, array step: 0x4

Definition at line 7053 of file S32K118.h.

volatile uint32_t LMDR2

< Defines 'read / write' permissions Local Memory Descriptor Register2, offset: 0x408

Definition at line 7054 of file S32K118.h.

volatile const uint32_t LMFAR

< Defines 'read only' permissions LMEM Fault Address Register, offset: 0x490

Definition at line 7060 of file S32K118.h.

volatile const uint32_t LMFATR

< Defines 'read only' permissions LMEM Fault Attribute Register, offset: 0x494

Definition at line 7061 of file S32K118.h.

volatile const uint32_t LMFDHR

< Defines 'read only' permissions LMEM Fault Data High Register, offset: 0x4A0

Definition at line 7063 of file S32K118.h.

volatile const uint32_t LMFDLR

< Defines 'read only' permissions LMEM Fault Data Low Register, offset: 0x4A4

Definition at line 7064 of file S32K118.h.

volatile uint32_t LMPECR

< Defines 'read / write' permissions LMEM Parity and ECC Control Register, offset: 0x480

Definition at line 7056 of file S32K118.h.

volatile uint32_t LMPEIR

< Defines 'read / write' permissions LMEM Parity and ECC Interrupt Register, offset: 0x488

Definition at line 7058 of file S32K118.h.

volatile uint32_t PID

< Defines 'read / write' permissions Process ID Register, offset: 0x30

Definition at line 7049 of file S32K118.h.

volatile const uint16_t PLAMC

< Defines 'read only' permissions Crossbar Switch (AXBS) Master Configuration, offset: 0xA

Definition at line 7046 of file S32K118.h.

volatile const uint16_t PLASC

< Defines 'read only' permissions Crossbar Switch (AXBS) Slave Configuration, offset: 0x8

Definition at line 7045 of file S32K118.h.

uint8_t RESERVED_0[8]

Definition at line 7044 of file S32K118.h.

uint8_t RESERVED_1[32]

Definition at line 7048 of file S32K118.h.

uint8_t RESERVED_2[12]

Definition at line 7050 of file S32K118.h.

uint8_t RESERVED_3[956]

Definition at line 7052 of file S32K118.h.

uint8_t RESERVED_4[116]

Definition at line 7055 of file S32K118.h.

uint8_t RESERVED_5[4]

Definition at line 7057 of file S32K118.h.

uint8_t RESERVED_6[4]

Definition at line 7059 of file S32K118.h.

uint8_t RESERVED_7[8]

Definition at line 7062 of file S32K118.h.


The documentation for this struct was generated from the following file: