S32K118_features.h
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1 /*
2  * Copyright 2018 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
60 #if !defined(S32K118_FEATURES_H)
61 #define S32K118_FEATURES_H
62 
63 
64 /* ERRATA sections*/
65 /* @brief Errata workaround: System clock status register may be a erroneous status during the system clock switch.
66  * Read system clock source twice. */
67 #define ERRATA_E10777
68 
69 /* @brief Number of cores. */
70 #define NUMBER_OF_CORES (1u)
71 
72 /* SOC module features */
73 
74 /* @brief PORT availability on the SoC. */
75 #define FEATURE_SOC_PORT_COUNT (5)
76 
77 #define FEATURE_SOC_SCG_COUNT (1)
78 
79 /* @brief Slow IRC high range clock frequency. */
80 #define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U)
81 
82 /* @brief Fast IRC trimmed clock frequency(48MHz). */
83 #define FEATURE_SCG_FIRC_FREQ0 (48000000U)
84 /* @brief VECTKEY value so that AIRCR register write is not ignored. */
85 #define FEATURE_SCB_VECTKEY (0x05FAU)
86 
87 /* FLASH module features */
88 
89 /* @brief Is of type FTFA. */
90 #define FEATURE_FLS_IS_FTFA (0u)
91 /* @brief Is of type FTFC. */
92 #define FEATURE_FLS_IS_FTFC (1u)
93 /* @brief Is of type FTFE. */
94 #define FEATURE_FLS_IS_FTFE (0u)
95 /* @brief Is of type FTFL. */
96 #define FEATURE_FLS_IS_FTFL (0u)
97 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
98 #define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u)
99 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
100 #define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u)
101 /* @brief Has EEPROM region protection (register FEPROT). */
102 #define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u)
103 /* @brief Has data flash region protection (register FDPROT). */
104 #define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u)
105 /* @brief P-Flash block count. */
106 #define FEATURE_FLS_PF_BLOCK_COUNT (1u)
107 /* @brief P-Flash block size. */
108 #define FEATURE_FLS_PF_BLOCK_SIZE (262144)
109 /* @brief P-Flash sector size. */
110 #define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (2048u)
111 /* @brief P-Flash write unit size. */
112 #define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u)
113 /* @brief P-Flash block swap feature. */
114 #define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u)
115 /* @brief Has FlexNVM memory. */
116 #define FEATURE_FLS_HAS_FLEX_NVM (1u)
117 /* @brief FlexNVM block count. */
118 #define FEATURE_FLS_DF_BLOCK_COUNT (1u)
119 /* @brief FlexNVM block size. */
120 #define FEATURE_FLS_DF_BLOCK_SIZE (32768u)
121 /* @brief FlexNVM sector size. */
122 #define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (2048u)
123 /* @brief FlexNVM write unit size. */
124 #define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u)
125 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
126 #define FEATURE_FLS_DF_START_ADDRESS (0x10000000u)
127 /* @brief Has FlexRAM memory. */
128 #define FEATURE_FLS_HAS_FLEX_RAM (1u)
129 /* @brief FlexRAM size. */
130 #define FEATURE_FLS_FLEX_RAM_SIZE (2048u)
131 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
132 #define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u)
133 /* @brief Has 0x00 Read 1s Block command. */
134 #define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u)
135 /* @brief Has 0x01 Read 1s Section command. */
136 #define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u)
137 /* @brief Has 0x02 Program Check command. */
138 #define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u)
139 /* @brief Has 0x03 Read Resource command. */
140 #define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u)
141 /* @brief Has 0x06 Program Longword command. */
142 #define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u)
143 /* @brief Has 0x07 Program Phrase command. */
144 #define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u)
145 /* @brief Has 0x08 Erase Flash Block command. */
146 #define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u)
147 /* @brief Has 0x09 Erase Flash Sector command. */
148 #define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u)
149 /* @brief Has 0x0B Program Section command. */
150 #define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u)
151 /* @brief Has 0x40 Read 1s All Blocks command. */
152 #define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u)
153 /* @brief Has 0x41 Read Once command. */
154 #define FEATURE_FLS_HAS_READ_ONCE_CMD (1u)
155 /* @brief Has 0x43 Program Once command. */
156 #define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u)
157 /* @brief Has 0x44 Erase All Blocks command. */
158 #define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u)
159 /* @brief Has 0x45 Verify Backdoor Access Key command. */
160 #define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u)
161 /* @brief Has 0x46 Swap Control command. */
162 #define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u)
163 /* @brief Has 0x49 Erase All Blocks unsecure command. */
164 #define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u)
165 /* @brief Has 0x80 Program Partition command. */
166 #define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u)
167 /* @brief Has 0x81 Set FlexRAM Function command. */
168 #define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u)
169 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
170 #define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
171 /* @brief P-Flash Erase sector command address alignment. */
172 #define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
173 /* @brief P-Flash Program/Verify section command address alignment. */
174 #define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
175 /* @brief P-Flash Read resource command address alignment. */
176 #define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
177 /* @brief P-Flash Program check command address alignment. */
178 #define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
179 /* @brief P-Flash Program check command address alignment. */
180 #define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u)
181 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
182 #define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
183 /* @brief FlexNVM Erase sector command address alignment. */
184 #define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
185 /* @brief FlexNVM Program/Verify section command address alignment. */
186 #define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
187 /* @brief FlexNVM Read resource command address alignment. */
188 #define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
189 /* @brief FlexNVM Program check command address alignment. */
190 #define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
191 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
192 #define FEATURE_FLS_DF_SIZE_0000 (0x00008000u)
193 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
194 #define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu)
195 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
196 #define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu)
197 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
198 #define FEATURE_FLS_DF_SIZE_0011 (0x00000000u)
199 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
200 #define FEATURE_FLS_DF_SIZE_0100 (0xFFFFFFFFu)
201 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
202 #define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu)
203 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
204 #define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu)
205 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
206 #define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu)
207 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
208 #define FEATURE_FLS_DF_SIZE_1000 (0x00000000u)
209 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
210 #define FEATURE_FLS_DF_SIZE_1001 (0x00002000u)
211 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
212 #define FEATURE_FLS_DF_SIZE_1010 (0xFFFFFFFFu)
213 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
214 #define FEATURE_FLS_DF_SIZE_1011 (0x00008000u)
215 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
216 #define FEATURE_FLS_DF_SIZE_1100 (0xFFFFFFFFu)
217 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
218 #define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu)
219 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
220 #define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu)
221 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
222 #define FEATURE_FLS_DF_SIZE_1111 (0x00008000u)
223 /* @brief Emulated EEPROM size code 0000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
224 #define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu)
225 /* @brief Emulated EEPROM size code 0001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
226 #define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu)
227 /* @brief Emulated EEPROM size code 0010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
228 #define FEATURE_FLS_EE_SIZE_0010 (0xFFFFu)
229 /* @brief Emulated EEPROM size code 0011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
230 #define FEATURE_FLS_EE_SIZE_0011 (0x0800u)
231 /* @brief Emulated EEPROM size code 0100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
232 #define FEATURE_FLS_EE_SIZE_0100 (0xFFFFu)
233 /* @brief Emulated EEPROM size code 0101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
234 #define FEATURE_FLS_EE_SIZE_0101 (0xFFFFu)
235 /* @brief Emulated EEPROM size code 0110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
236 #define FEATURE_FLS_EE_SIZE_0110 (0xFFFFu)
237 /* @brief Emulated EEPROM size code 0111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
238 #define FEATURE_FLS_EE_SIZE_0111 (0xFFFFu)
239 /* @brief Emulated EEPROM size code 1000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
240 #define FEATURE_FLS_EE_SIZE_1000 (0xFFFFu)
241 /* @brief Emulated EEPROM size code 1001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
242 #define FEATURE_FLS_EE_SIZE_1001 (0xFFFFu)
243 /* @brief Emulated EEPROM size code 1010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
244 #define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu)
245 /* @brief Emulated EEPROM size code 1011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
246 #define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu)
247 /* @brief Emulated EEPROM size code 1100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
248 #define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu)
249 /* @brief Emulated EEPROM size code 1101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
250 #define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu)
251 /* @brief Emulated EEPROM size code 1110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
252 #define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu)
253 /* @brief Emulated EEPROM size code 1111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
254 #define FEATURE_FLS_EE_SIZE_1111 (0x0000u)
255 /* @brief Has the detection of uncorrected ECC errors. */
256 #define FEATURE_FLS_HAS_DETECT_ECC_ERROR (1)
257 /* @brief Has the interrupt double bit fault detect. */
258 #define FEATURE_FLS_HAS_INTERRUPT_DOUBLE_BIT_FAULT_IRQ (0)
259 
260 /* SMC module features */
261 
262 /* @brief Has stop option (register bit STOPCTRL[STOPO]). */
263 #define FEATURE_SMC_HAS_STOPO (1)
264 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
265 #define FEATURE_SMC_HAS_PSTOPO (0)
266 /* @brief Has WAIT and VLPW options. */
267 #define FEATURE_SMC_HAS_WAIT_VLPW (0)
268 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
269 #define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
270 
271 /* RCM module feature */
272 
273 /* @brief Has existence of CMU loss of clock as reset source */
274 #define FEATURE_RCM_HAS_EXISTENCE_CMU_LOSS_OF_CLOCK (1)
275 /* @brief Has CMU loss of clock as reset source */
276 #define FEATURE_RCM_HAS_CMU_LOSS_OF_CLOCK (1)
277 /* @brief Has sticky CMU loss of clock as reset source */
278 #define FEATURE_RCM_HAS_STICKY_CMU_LOSS_OF_CLOCK (1)
279 
280 /* WDOG module features */
281 
282 /* @brief The 32-bit value used for unlocking the WDOG. */
283 #define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U)
284 /* @brief The 32-bit value used for resetting the WDOG counter. */
285 #define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U)
286 /* @brief The reset value of the timeout register. */
287 #define FEATURE_WDOG_TO_RESET_VALUE (0x400U)
288 /* @brief The value minimum of the timeout register. */
289 #define FEATURE_WDOG_MINIMUM_TIMEOUT_VALUE (0x0U)
290 /* @brief The reset value of the window register. */
291 #define FEATURE_WDOG_WIN_RESET_VALUE (0x0U)
292 /* @brief The mask of the reserved bit in the CS register. */
293 #define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U)
294 /* @brief The value used to set WDOG source clock from LPO. */
295 #define FEATURE_WDOG_CLK_FROM_LPO (0x1UL)
296 /* @brief The first 16-bit value used for unlocking the WDOG. */
297 #define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U)
298 /* @brief The second 16-bit value used for unlocking the WDOG. */
299 #define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U)
300 /* @brief The first 16-bit value used for resetting the WDOG counter. */
301 #define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U)
302 /* @brief The second 16-bit value used for resetting the WDOG counter. */
303 #define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U)
304 /* @brief Default reset value of the CS register. */
305 #define FEATURE_WDOG_CS_RESET_VALUE (0x2520U)
306 
307 /* Interrupt module features */
308 
309 /* @brief Lowest interrupt request number. */
310 #define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn)
311 /* @brief Highest interrupt request number. */
312 #define FEATURE_INTERRUPT_IRQ_MAX (LPUART0_RxTx_IRQn)
313 
314 #define FEATURE_NVIC_PRIO_BITS (2U)
315 /* @brief Has software interrupt. */
316 #define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u)
317 /* @brief Has pending interrupt state. */
318 #define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u)
319 /* @brief Has active interrupt state. */
320 #define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (0u)
321 /* @brief Multicore support for interrupts */
322 #define FEATURE_INTERRUPT_MULTICORE_SUPPORT (0u)
323 /* @brief Registers in which the start of interrupt vector table needs to be configured */
324 #define FEATURE_INTERRUPT_INT_VECTORS {&S32_SCB->VTOR}
325 
326 /* FTM module features */
327 
328 /* @brief Number of PWM channels */
329 #define FEATURE_FTM_CHANNEL_COUNT (8U)
330 /* @brief Number of fault channels */
331 #define FTM_FEATURE_FAULT_CHANNELS (4U)
332 /* @brief Width of control channel */
333 #define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U)
334 /* @brief Output channel offset */
335 #define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U)
336 /* @brief Max counter value */
337 #define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU)
338 /* @brief Input capture for single shot */
339 #define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U)
340 /* @brief Dithering has supported on the generated PWM signals */
341 #define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U)
342 /* @brief Number of interrupt vector for channels of the FTM module. */
343 #define FEATURE_FTM_HAS_NUM_IRQS_CHANS (1U)
344 
345 /* LPIT module features */
346 
348 #define FEATURE_LPIT_HAS_NUM_IRQS_CHANS (1)
349 
350 #define LPIT_CLOCK_NAMES {LPIT0_CLK}
351 
352 /* LPI2C module features */
353 
354 /* @brief DMA instance used for LPI2C module */
355 #define LPI2C_DMA_INSTANCE 0U
356 
357 /* @brief EDMA requests for LPI2C module. */
358 #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}}
359 /* @brief PCC clocks for LPI2C module. */
360 #define LPI2C_PCC_CLOCKS {LPI2C0_CLK}
361 
362 /* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */
363 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
364 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
365 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
366 
367 /* LPI2C module features */
368 
369 /* @brief DMA instance used for LPI2C module */
370 #define LPI2C_DMA_INSTANCE 0U
371 
372 /* @brief EDMA requests for LPI2C module. */
373 #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}}
374 /* @brief PCC clocks for LPI2C module. */
375 #define LPI2C_PCC_CLOCKS {LPI2C0_CLK}
376 
377 /* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */
378 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
379 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
380 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
381 
382 /* MSCM module features */
383 
384 /* @brief Has interrupt router control registers (IRSPRCn). */
385 #define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0)
386 /* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */
387 #define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0)
388 
389 /* CSEc module features */
390 
393 #define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU)
394 
396 #define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU)
397 
399 #define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U)
400 
402 #define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU)
403 
405 #define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU)
406 
408 #define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U)
409 
411 #define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U)
412 
413 #define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U)
414 
416 #define FEATURE_CSEC_SREG_OFFSET (0x2FU)
417 
419 #define FEATURE_CSEC_PAGE_0_OFFSET (0x0U)
420 
421 #define FEATURE_CSEC_PAGE_1_OFFSET (0x10U)
422 
423 #define FEATURE_CSEC_PAGE_2_OFFSET (0x20U)
424 
425 #define FEATURE_CSEC_PAGE_3_OFFSET (0x30U)
426 
427 #define FEATURE_CSEC_PAGE_4_OFFSET (0x40U)
428 
429 #define FEATURE_CSEC_PAGE_5_OFFSET (0x50U)
430 
431 #define FEATURE_CSEC_PAGE_6_OFFSET (0x60U)
432 
433 #define FEATURE_CSEC_PAGE_7_OFFSET (0x70U)
434 
435 /* CRC module features */
436 
437 /* @brief CRC module use for S32K. */
438 #define FEATURE_CRC_DRIVER_SOFT_POLYNOMIAL
439 /* @brief Default CRC bit width */
440 #define FEATURE_CRC_DEFAULT_WIDTH CRC_BITS_16
441 /* @brief Default CRC read transpose */
442 #define FEATURE_CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE
443 /* @brief Default CRC write transpose */
444 #define FEATURE_CRC_DEFAULT_WRITE_TRANSPOSE CRC_TRANSPOSE_NONE
445 /* @brief Default polynomial 0x1021U */
446 #define FEATURE_CRC_DEFAULT_POLYNOMIAL (0x1021U)
447 /* @brief Default seed value is 0xFFFFU */
448 #define FEATURE_CRC_DEFAULT_SEED (0xFFFFU)
449 
450 /* PORT module features */
452 #define FEATURE_PINS_DRIVER_USING_PORT (1)
453 /* @brief Has control lock (register bit PCR[LK]). */
454 #define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
455 /* @brief Has open drain control (register bit PCR[ODE]). */
456 #define FEATURE_PINS_HAS_OPEN_DRAIN (0)
457 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
458 #define FEATURE_PORT_HAS_DIGITAL_FILTER (1)
459 /* @brief Has trigger output to trigger other peripherals (register bit field PCR[IRQC] values). */
460 #define FEATURE_PORT_HAS_TRIGGER_OUT (0)
461 /* @brief Has setting flag only (register bit field PCR[IRQC] values). */
462 #define FEATURE_PORT_HAS_FLAG_SET_ONLY (0)
463 /* @brief Has over-current feature (register bit field PCR[OCIE] values). */
464 #define FEATURE_PINS_HAS_OVER_CURRENT (0)
465 /* @brief Has pull resistor selection available. */
466 #define FEATURE_PINS_HAS_PULL_SELECTION (1)
467 /* @brief Has slew rate control (register bit PCR[SRE]). */
468 #define FEATURE_PINS_HAS_SLEW_RATE (0)
469 /* @brief Has passive filter (register bit field PCR[PFE]). */
470 #define FEATURE_PORT_HAS_PASSIVE_FILTER (1)
471 /* @brief Has drive strength (register bit PCR[DSE]). */
472 #define FEATURE_PINS_HAS_DRIVE_STRENGTH (1)
473 /* @brief Has drive strength control bits*/
474 #define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0)
475 /* @brief Has port input disable control bits*/
476 #define FEATURE_PORT_HAS_INPUT_DISABLE (0)
477 
478 /* MPU module features */
479 
480 /* @brief Specifies hardware revision level. */
481 #define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U)
482 /* @brief Has process identifier support. */
483 #define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U)
484 /* @brief Specifies total number of bus masters. */
485 #define FEATURE_MPU_MASTER_COUNT (3U)
486 /* @brief Specifies maximum number of masters which have separated
487 privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K1xx).
488 */
489 #define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U)
490 /* @brief Specifies maximum number of masters which have only
491 read and write permissions (e.g. master4~7 in S32K1xx).
492 */
493 #define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U)
494 
495 /* @brief Specifies number of set access control right bits for
496  masters which have separated privilege rights for user and
497  supervisor mode accesses (e.g. master0~3 in S32K1xx).
498 */
499 #define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U)
500 /* @brief Specifies number of set access control right bits for
501  masters which have only read and write permissions(e.g. master4~7 in S32K1xx).
502 */
503 #define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U)
504 
505 /* @brief The MPU Logical Bus Master Number for core bus master. */
506 #define FEATURE_MPU_MASTER_CORE (0U)
507 /* @brief The MPU Logical Bus Master Number for Debugger master. */
508 #define FEATURE_MPU_MASTER_DEBUGGER (1U)
509 /* @brief The MPU Logical Bus Master Number for DMA master. */
510 #define FEATURE_MPU_MASTER_DMA (2U)
511 /* @brief Specifies master number. */
512 #define FEATURE_MPU_MASTER \
513 { \
514  FEATURE_MPU_MASTER_CORE, \
515  FEATURE_MPU_MASTER_DEBUGGER, \
516  FEATURE_MPU_MASTER_DMA, \
517 }
518 
519 /* @brief Specifies total number of slave ports. */
520 #define FEATURE_MPU_SLAVE_COUNT (2U)
521 /* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */
522 #define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U)
523 /* @brief The MPU Slave Port Assignment for SRAM, MTB, DWT and MCM. */
524 #define FEATURE_MPU_SLAVE_SRAM_MTB_DWT_MCM (1U)
525 /* @brief The MPU Slave Port mask. */
526 #define FEATURE_MPU_SLAVE_MASK (0xC0000000U)
527 #define FEATURE_MPU_SLAVE_SHIFT (30u)
528 #define FEATURE_MPU_SLAVE_WIDTH (2u)
529 #define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<FEATURE_MPU_SLAVE_SHIFT))&FEATURE_MPU_SLAVE_MASK)
530 
531 
532 /* @brief Supports high speed run mode. */
533 #define FEATURE_HAS_HIGH_SPEED_RUN_MODE (0U)
534 /* @brief Supports SPLL clock source. */
535 #define FEATURE_HAS_SPLL_CLK (0U)
536 
537 /* CMP module features */
538 
539 /* @brief Comparator hard block offset control */
540 #define FEATURE_CMP_HAS_HARD_BLOCK_OFFSET (1U)
541 /* @brief Comparator fix DAC input to mux side */
542 #define FEATURE_CMP_DAC_FIX_SELECTION (0U)
543 /* @brief Comparator initialization delay */
544 #define FEATURE_CMP_HAS_INIT_DELAY (1U)
545 
546 #define C0_RESET_VALUE (CMP_C0_DMAEN(0U) | CMP_C0_IER(0U) | CMP_C0_IEF(0U) | CMP_C0_CFR(1U) | \
547  CMP_C0_CFF(1U) | CMP_C0_FPR(0U) | CMP_C0_SE(0U) | CMP_C0_WE(0U) | \
548  CMP_C0_PMODE(0U) | CMP_C0_INVT(0U) | CMP_C0_COS(0U) | CMP_C0_OPE(0U) | \
549  CMP_C0_EN(0U) | CMP_C0_FILTER_CNT(0U) | CMP_C0_OFFSET(0U) | CMP_C0_HYSTCTR(0U))
550 
551 #define C1_RESET_VALUE (CMP_C1_INPSEL(0U) | CMP_C1_INNSEL(0U) | CMP_C1_CHN7(0U) | CMP_C1_CHN6(0U) | \
552  CMP_C1_CHN5(0U) | CMP_C1_CHN4(0U) | CMP_C1_CHN3(0U) | CMP_C1_CHN2(0U) | \
553  CMP_C1_CHN1(0U) | CMP_C1_CHN0(0U) | CMP_C1_DACEN(0U) | CMP_C1_VRSEL(0U) | \
554  CMP_C1_PSEL(0U) | CMP_C1_MSEL(0U) | CMP_C1_VOSEL(0U))
555 
556 #define C2_RESET_VALUE (CMP_C2_RRE(0U) | CMP_C2_RRIE(0U) | CMP_C2_FXMP(0U) | CMP_C2_FXMXCH(0U) | CMP_C2_CH7F(1U) | \
557  CMP_C2_CH6F(1U) | CMP_C2_CH5F(1U) | CMP_C2_CH4F(1U) | CMP_C2_CH3F(1U) | CMP_C2_CH2F(1U) | \
558  CMP_C2_CH1F(1U) | CMP_C2_CH0F(1U) | CMP_C2_NSAM(0U) | CMP_C2_NSAM(0U) | CMP_C2_INITMOD(0U) | \
559  CMP_C2_ACOn(0U))
560 
561 #define CMP_DAC_SOURCE 0U
562 #define CMP_MUX_SOURCE 1U
563 #define CMP_DAC_RESOLUTION 255U
564 
566 typedef enum {
567  /* Main clocks */
568  CORE_CLK = 0u,
569  BUS_CLK = 1u,
570  SLOW_CLK = 2u,
571  CLKOUT_CLK = 3u,
573  /* Other internal clocks used by peripherals. */
574  SIRC_CLK = 4u,
575  FIRC_CLK = 5u,
576  SOSC_CLK = 6u,
579  SIRCDIV1_CLK = 10u,
580  SIRCDIV2_CLK = 11u,
581  FIRCDIV1_CLK = 12u,
582  FIRCDIV2_CLK = 13u,
583  SOSCDIV1_CLK = 14u,
584  SOSCDIV2_CLK = 15u,
588  /* SIM clocks */
593  SIM_LPO_CLK = 25u,
597  SIM_EIM_CLK = 29u,
598  SIM_ERM_CLK = 30u,
599  SIM_DMA_CLK = 31u,
600  SIM_MPU_CLK = 32u,
601  SIM_MSCM_CLK = 33u,
604  CMP0_CLK = 41u,
605  CRC0_CLK = 42u,
606  DMAMUX0_CLK = 43u,
607  PORTA_CLK = 44u,
608  PORTB_CLK = 45u,
609  PORTC_CLK = 46u,
610  PORTD_CLK = 47u,
611  PORTE_CLK = 48u,
612  RTC0_CLK = 49u,
614  FlexCAN0_CLK = 51u,
615  PDB0_CLK = 52u,
617  FTFC0_CLK = 54u,
619  FTM0_CLK = 56u,
620  FTM1_CLK = 57u,
622  ADC0_CLK = 59u,
623  FLEXIO0_CLK = 60u,
624  LPI2C0_CLK = 61u,
625  LPIT0_CLK = 62u,
626  LPSPI0_CLK = 63u,
627  LPSPI1_CLK = 64u,
628  LPTMR0_CLK = 65u,
629  LPUART0_CLK = 66u,
630  LPUART1_CLK = 67u,
634 } clock_names_t;
635 
636 #define PCC_INVALID_INDEX 0
637 
643 #define PCC_CLOCK_NAME_MAPPINGS \
644 { \
645 PCC_INVALID_INDEX, \
646 PCC_INVALID_INDEX, \
647 PCC_INVALID_INDEX, \
648 PCC_INVALID_INDEX, \
649 PCC_INVALID_INDEX, \
650 PCC_INVALID_INDEX, \
651 PCC_INVALID_INDEX, \
652 PCC_INVALID_INDEX, \
653 PCC_INVALID_INDEX, \
654 PCC_INVALID_INDEX, \
655 PCC_INVALID_INDEX, \
656 PCC_INVALID_INDEX, \
657 PCC_INVALID_INDEX, \
658 PCC_INVALID_INDEX, \
659 PCC_INVALID_INDEX, \
660 PCC_INVALID_INDEX, \
661 PCC_INVALID_INDEX, \
662 PCC_INVALID_INDEX, \
663 PCC_INVALID_INDEX, \
664 PCC_INVALID_INDEX, \
665 PCC_INVALID_INDEX, \
666 PCC_INVALID_INDEX, \
667 PCC_INVALID_INDEX, \
668 PCC_INVALID_INDEX, \
669 PCC_INVALID_INDEX, \
670 PCC_INVALID_INDEX, \
671 PCC_INVALID_INDEX, \
672 PCC_INVALID_INDEX, \
673 PCC_INVALID_INDEX, \
674 PCC_INVALID_INDEX, \
675 PCC_INVALID_INDEX, \
676 PCC_INVALID_INDEX, \
677 PCC_INVALID_INDEX, \
678 PCC_INVALID_INDEX, \
679 PCC_INVALID_INDEX, \
680 PCC_INVALID_INDEX, \
681 PCC_INVALID_INDEX, \
682 PCC_INVALID_INDEX, \
683 PCC_INVALID_INDEX, \
684 PCC_INVALID_INDEX, \
685 PCC_INVALID_INDEX, \
686 PCC_CMP0_INDEX, \
687 PCC_CRC_INDEX, \
688 PCC_DMAMUX_INDEX, \
689 PCC_PORTA_INDEX, \
690 PCC_PORTB_INDEX, \
691 PCC_PORTC_INDEX, \
692 PCC_PORTD_INDEX, \
693 PCC_PORTE_INDEX, \
694 PCC_RTC_INDEX, \
695 PCC_INVALID_INDEX, \
696 PCC_FlexCAN0_INDEX, \
697 PCC_PDB0_INDEX, \
698 PCC_INVALID_INDEX, \
699 PCC_FTFC_INDEX, \
700 PCC_INVALID_INDEX, \
701 PCC_FTM0_INDEX, \
702 PCC_FTM1_INDEX, \
703 PCC_INVALID_INDEX, \
704 PCC_ADC0_INDEX, \
705 PCC_FlexIO_INDEX, \
706 PCC_LPI2C0_INDEX, \
707 PCC_LPIT_INDEX, \
708 PCC_LPSPI0_INDEX, \
709 PCC_LPSPI1_INDEX, \
710 PCC_LPTMR0_INDEX, \
711 PCC_LPUART0_INDEX, \
712 PCC_LPUART1_INDEX, \
713 PCC_INVALID_INDEX, \
714 PCC_INVALID_INDEX, \
715 }
716 
720 #define NO_PERIPHERAL_FEATURE (0U) /* It's not a peripheral instance, there is no peripheral feature. */
721 #define HAS_CLOCK_GATING_IN_SIM (1U << 0U) /* Clock gating is implemented in SIM (it's not in PCC) */
722 #define HAS_MULTIPLIER (1U << 1U) /* Multiplier is implemented in PCC */
723 #define HAS_DIVIDER (1U << 2U) /* Divider is implemented in PCC */
724 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U) /* Functional clock source is provided by the first asynchronous clock. */
725 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U) /* Functional clock source is provided by the second asynchronous clock. */
726 #define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U) /* Interface clock is provided by the bus clock. */
727 #define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U) /* Interface clock is provided by the sys clock. */
728 #define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U) /* Interface clock is provided by the slow clock. */
729 
734 #define PERIPHERAL_FEATURES \
735 { \
736 (NO_PERIPHERAL_FEATURE), \
737 (NO_PERIPHERAL_FEATURE), \
738 (NO_PERIPHERAL_FEATURE), \
739 (NO_PERIPHERAL_FEATURE), \
740 (NO_PERIPHERAL_FEATURE), \
741 (NO_PERIPHERAL_FEATURE), \
742 (NO_PERIPHERAL_FEATURE), \
743 (NO_PERIPHERAL_FEATURE), \
744 (NO_PERIPHERAL_FEATURE), \
745 (NO_PERIPHERAL_FEATURE), \
746 (NO_PERIPHERAL_FEATURE), \
747 (NO_PERIPHERAL_FEATURE), \
748 (NO_PERIPHERAL_FEATURE), \
749 (NO_PERIPHERAL_FEATURE), \
750 (NO_PERIPHERAL_FEATURE), \
751 (NO_PERIPHERAL_FEATURE), \
752 (NO_PERIPHERAL_FEATURE), \
753 (NO_PERIPHERAL_FEATURE), \
754 (NO_PERIPHERAL_FEATURE), \
755 (NO_PERIPHERAL_FEATURE), \
756 (NO_PERIPHERAL_FEATURE), \
757 (NO_PERIPHERAL_FEATURE), \
758 (NO_PERIPHERAL_FEATURE), \
759 (NO_PERIPHERAL_FEATURE), \
760 (NO_PERIPHERAL_FEATURE), \
761 (NO_PERIPHERAL_FEATURE), \
762 (NO_PERIPHERAL_FEATURE), \
763 (NO_PERIPHERAL_FEATURE), \
764 (NO_PERIPHERAL_FEATURE), \
765 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
766 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
767 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
768 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
769 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
770 (NO_PERIPHERAL_FEATURE), \
771 (NO_PERIPHERAL_FEATURE), \
772 (NO_PERIPHERAL_FEATURE), \
773 (NO_PERIPHERAL_FEATURE), \
774 (NO_PERIPHERAL_FEATURE), \
775 (NO_PERIPHERAL_FEATURE), \
776 (NO_PERIPHERAL_FEATURE), \
777 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
778 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
779 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
780 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
781 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
782 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
783 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
784 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
785 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
786 (NO_PERIPHERAL_FEATURE), \
787 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
788 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
789 (NO_PERIPHERAL_FEATURE), \
790 (HAS_INT_CLOCK_FROM_SLOW_CLOCK), \
791 (NO_PERIPHERAL_FEATURE), \
792 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
793 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
794 (NO_PERIPHERAL_FEATURE), \
795 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
796 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
797 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
798 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
799 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
800 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
801 (HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
802 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
803 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
804 (NO_PERIPHERAL_FEATURE), \
805 (NO_PERIPHERAL_FEATURE), \
806 }
807 
808 /* Time to wait for SIRC to stabilize (number of
809  * cycles when core runs at maximum speed - 112 MHz */
810 #define SIRC_STABILIZATION_TIMEOUT 100U
811 
812 /* Time to wait for FIRC to stabilize (number of
813  * cycles when core runs at maximum speed - 112 MHz */
814 #define FIRC_STABILIZATION_TIMEOUT 20U
815 
816 /* Time to wait for SOSC to stabilize (number of
817  * cycles when core runs at maximum speed - 112 MHz */
818 #define SOSC_STABILIZATION_TIMEOUT 3205000U;
819 
820 /* Time to wait for SPLL to stabilize (number of
821  * cycles when core runs at maximum speed - 112 MHz */
822 #define SPLL_STABILIZATION_TIMEOUT 1000U;
823 
824 
835 #define TMP_SIRC_CLK 0U
836 #define TMP_FIRC_CLK 1U
837 #define TMP_SOSC_CLK 2U
838 #define TMP_SPLL_CLK 3U
839 
840 #define TMP_SYS_DIV 0U
841 #define TMP_BUS_DIV 1U
842 #define TMP_SLOW_DIV 2U
843 
844 #define TMP_SYS_CLK_NO 4U
845 #define TMP_SYS_DIV_NO 3U
846 
847 #define TMP_SYSTEM_CLOCK_CONFIGS \
848 { /* SYS_CLK BUS_CLK SLOW_CLK */ \
849 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
850 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, \
851 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
852 { SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
853 }
854 
855 /* DMA module features */
856 
857 /* @brief Number of DMA channels. */
858 #define FEATURE_DMA_CHANNELS (4U)
859 /* @brief Number of DMA virtual channels. */
860 #define FEATURE_DMA_VIRTUAL_CHANNELS ((uint32_t)FEATURE_DMA_CHANNELS * (uint32_t)DMA_INSTANCE_COUNT)
861 /* @brief Number of DMA interrupt lines. */
862 #define FEATURE_DMA_CHANNELS_INTERRUPT_LINES (4U)
863 /* @brief Number of DMA virtual interrupt lines. */
864 #define FEATURE_DMA_VIRTUAL_CHANNELS_INTERRUPT_LINES ((uint32_t)FEATURE_DMA_CHANNELS_INTERRUPT_LINES * (uint32_t)DMA_INSTANCE_COUNT)
865 /* @brief Number of DMA error interrupt lines. */
866 #define FEATURE_DMA_ERROR_INTERRUPT_LINES (1U)
867 /* @brief Number of DMA virtual error interrupt lines. */
868 #define FEATURE_DMA_VIRTUAL_ERROR_INTERRUPT_LINES ((uint32_t)FEATURE_DMA_ERROR_INTERRUPT_LINES * (uint32_t)DMA_INSTANCE_COUNT)
869 /* @brief DMA module has error interrupt. */
870 #define FEATURE_DMA_HAS_ERROR_IRQ
871 /* @brief DMA module separate interrupt lines for each channel */
872 #define FEATURE_DMA_SEPARATE_IRQ_LINES_PER_CHN
873 /* @brief Conversion from channel index to DCHPRI index. */
874 #define FEATURE_DMA_CHN_TO_DCHPRI_INDEX(x) ((x) ^ 3U)
875 /* @brief DMA channel groups count. */
876 #define FEATURE_DMA_CHANNEL_GROUP_COUNT (1U)
877 /* @brief Clock name for DMA */
878 #define FEATURE_DMA_CLOCK_NAMES {SIM_DMA_CLK}
879 /* @brief DMA channel width based on number of TCDs: 2^N, N=4,5,... */
880 #define FEATURE_DMA_CH_WIDTH (4U)
881 /* @brief DMA channel to instance */
882 #define FEATURE_DMA_VCH_TO_INSTANCE(x) ((x) >> (uint32_t)FEATURE_DMA_CH_WIDTH)
883 /* @brief DMA virtual channel to channel */
884 #define FEATURE_DMA_VCH_TO_CH(x) ((x) & ((uint32_t)FEATURE_DMA_CHANNELS - 1U))
885 /* @brief DMA supports the following particular channel priorities: */
886 #define FEATURE_DMA_4_CH_PRIORITIES
887 /* @brief DMA supports bus bandwidth control. */
888 #define FEATURE_DMA_ENGINE_STALL
889 
890 /* DMAMUX module features */
891 
892 /* @brief Number of DMA channels. */
893 #define FEATURE_DMAMUX_CHANNELS (4U)
894 /* @brief Has the periodic trigger capability */
895 #define FEATURE_DMAMUX_HAS_TRIG (1)
896 /* @brief Conversion from request source to the actual DMAMUX channel */
897 #define FEATURE_DMAMUX_REQ_SRC_TO_CH(x) (x)
898 /* @brief Mapping between request source and DMAMUX instance */
899 #define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U)
900 /* @brief Conversion from eDMA channel index to DMAMUX channel. */
901 #define FEATURE_DMAMUX_DMA_CH_TO_CH(x) (x)
902 /* @brief Conversion from DMAMUX channel DMAMUX register index. */
903 #define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x)
904 /* @brief Clock names for DMAMUX. */
905 #define FEATURE_DMAMUX_CLOCK_NAMES {DMAMUX0_CLK}
906 
914 typedef enum {
952 
953 
954 /* TRGMUX module features */
962 {
1008 };
1009 
1017 {
1056 };
1057 
1058 /* @brief Constant array storing the value of all TRGMUX output(target module) identifiers */
1059 #define FEATURE_TRGMUX_TARGET_MODULE \
1060 { \
1061  TRGMUX_TARGET_MODULE_DMA_CH0, \
1062  TRGMUX_TARGET_MODULE_DMA_CH1, \
1063  TRGMUX_TARGET_MODULE_DMA_CH2, \
1064  TRGMUX_TARGET_MODULE_DMA_CH3, \
1065  TRGMUX_TARGET_MODULE_TRGMUX_OUT0, \
1066  TRGMUX_TARGET_MODULE_TRGMUX_OUT1, \
1067  TRGMUX_TARGET_MODULE_TRGMUX_OUT2, \
1068  TRGMUX_TARGET_MODULE_TRGMUX_OUT3, \
1069  TRGMUX_TARGET_MODULE_TRGMUX_OUT4, \
1070  TRGMUX_TARGET_MODULE_TRGMUX_OUT5, \
1071  TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA0, \
1072  TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA1, \
1073  TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA2, \
1074  TRGMUX_TARGET_MODULE_ADC0_ADHWT_TLA3, \
1075  TRGMUX_TARGET_MODULE_CMP0_SAMPLE, \
1076  TRGMUX_TARGET_MODULE_FTM0_HWTRIG0, \
1077  TRGMUX_TARGET_MODULE_FTM0_FAULT0, \
1078  TRGMUX_TARGET_MODULE_FTM0_FAULT1, \
1079  TRGMUX_TARGET_MODULE_FTM0_FAULT2, \
1080  TRGMUX_TARGET_MODULE_FTM1_HWTRIG0, \
1081  TRGMUX_TARGET_MODULE_FTM1_FAULT0, \
1082  TRGMUX_TARGET_MODULE_FTM1_FAULT1, \
1083  TRGMUX_TARGET_MODULE_FTM1_FAULT2, \
1084  TRGMUX_TARGET_MODULE_PDB0_TRG_IN, \
1085  TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM0, \
1086  TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM1, \
1087  TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM2, \
1088  TRGMUX_TARGET_MODULE_FLEXIO_TRG_TIM3, \
1089  TRGMUX_TARGET_MODULE_LPIT_TRG_CH0, \
1090  TRGMUX_TARGET_MODULE_LPIT_TRG_CH1, \
1091  TRGMUX_TARGET_MODULE_LPIT_TRG_CH2, \
1092  TRGMUX_TARGET_MODULE_LPIT_TRG_CH3, \
1093  TRGMUX_TARGET_MODULE_LPUART0_TRG, \
1094  TRGMUX_TARGET_MODULE_LPUART1_TRG, \
1095  TRGMUX_TARGET_MODULE_LPI2C0_TRG, \
1096  TRGMUX_TARGET_MODULE_LPSPI0_TRG, \
1097  TRGMUX_TARGET_MODULE_LPSPI1_TRG, \
1098  TRGMUX_TARGET_MODULE_LPTMR0_ALT0 \
1099 }
1100 
1101 
1102 /* LPSPI module features */
1103 /* @brief Initial value for state structure */
1104 #define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL}
1105 /* @brief Clock indexes for LPSPI clock */
1106 #define FEATURE_LPSPI_CLOCKS_NAMES {LPSPI0_CLK, LPSPI1_CLK};
1107 
1108 /* FlexIO module features */
1109 
1110 /* @brief Define the maximum number of shifters for any FlexIO instance. */
1111 #define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U)
1112 /* @brief Define DMA request names for Flexio. */
1113 #define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0
1114 #define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1
1115 #define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2
1116 #define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3
1117 
1118 /* LPUART module features */
1119 
1120 /* @brief Has extended data register ED. */
1121 #define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1122 /* @brief Hardware flow control (RTS, CTS) is supported. */
1123 #define FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
1124 /* @brief Baud rate oversampling is available. */
1125 #define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
1126 /* @brief Baud rate oversampling is available. */
1127 #define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
1128 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1129 #define FEATURE_LPUART_FIFO_SIZE (4U)
1130 /* @brief Supports two match addresses to filter incoming frames. */
1131 #define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
1132 /* @brief Has transmitter/receiver DMA enable bits. */
1133 #define FEATURE_LPUART_HAS_DMA_ENABLE (1)
1134 /* @brief Flag clearance mask for STAT register. */
1135 #define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U)
1136 /* @brief Flag clearance mask for FIFO register. */
1137 #define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U)
1138 /* @brief Reset mask for FIFO register. */
1139 #define FEATURE_LPUART_FIFO_RESET_MASK (0x0003C000U)
1140 /* @brief Default oversampling ratio. */
1141 #define FEATURE_LPUART_DEFAULT_OSR (0x0FUL)
1142 /* @brief Default baud rate modulo divisor. */
1143 #define FEATURE_LPUART_DEFAULT_SBR (0x04UL)
1144 /* @brief Clock names for LPUART. */
1145 #define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK}
1146 
1147 /* ADC module features */
1148 
1151 #define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0)
1152 
1153 #define NUMBER_OF_ALT_CLOCKS ADC_CLK_ALT_1
1154 
1157 #define FEATURE_ADC_MAX_NUM_EXT_CHANS (16)
1158 #define FEATURE_ADC_HAS_CHANNEL_2 (1)
1159 #define FEATURE_ADC_HAS_CHANNEL_8 (1)
1160 #define ADC_CLOCKS {ADC0_CLK}
1161 
1162 #if FEATURE_ADC_HAS_EXTRA_NUM_REGS
1163 #define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT
1164 #else
1165 #define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT
1166 #endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */
1167 
1169 #define ADC_DEFAULT_SAMPLE_TIME (0x0CU)
1170 
1171 #define ADC_DEFAULT_USER_GAIN (0x04U)
1172 /* @brief Max of adc clock frequency */
1173 #define ADC_CLOCK_FREQ_MAX_RUNTIME (50000000u)
1174 /* @brief Min of adc clock frequency */
1175 #define ADC_CLOCK_FREQ_MIN_RUNTIME (2000000u)
1176 
1177 /* CAN module features */
1178 
1179 /* @brief Frames available in Rx FIFO flag shift */
1180 #define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U)
1181 /* @brief Rx FIFO warning flag shift */
1182 #define FEATURE_CAN_RXFIFO_WARNING (6U)
1183 /* @brief Rx FIFO overflow flag shift */
1184 #define FEATURE_CAN_RXFIFO_OVERFLOW (7U)
1185 /* @brief Has Flexible Data Rate for CAN0 */
1186 #define FEATURE_CAN0_HAS_FD (1)
1187 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */
1188 #define FEATURE_CAN0_MAX_MB_NUM (32U)
1189 /* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */
1190 #define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1)
1191 /* @brief Has DMA enable (bit field MCR[DMA]). */
1192 #define FEATURE_CAN_HAS_DMA_ENABLE (1)
1193 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
1194 #define FEATURE_CAN_MAX_MB_NUM (32U)
1195 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
1196 #define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM }
1197 /* @brief Has Pretending Networking mode */
1198 #define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1)
1199 /* @brief Has Stuff Bit Count Enable Bit */
1200 #define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0)
1201 /* @brief Has ISO CAN FD Enable Bit */
1202 #define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1)
1203 /* @brief Has Message Buffer Data Size Region 1 */
1204 #define FEATURE_CAN_HAS_MBDSR1 (0)
1205 /* @brief Has Message Buffer Data Size Region 2 */
1206 #define FEATURE_CAN_HAS_MBDSR2 (0)
1207 /* @brief DMA hardware requests for all FlexCAN instances */
1208 #define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0 }
1209 
1210 /* @brief Maximum number of Message Buffers IRQs */
1211 #define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U)
1212 /* @brief Message Buffers IRQs */
1213 #define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \
1214  CAN_ORed_16_31_MB_IRQS }
1215 /* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */
1216 #define FEATURE_CAN_HAS_WAKE_UP_IRQ (1)
1217 /* @brief Has Self Wake Up mode */
1218 #define FEATURE_CAN_HAS_SELF_WAKE_UP (0)
1219 /* @brief Has Flexible Data Rate */
1220 #define FEATURE_CAN_HAS_FD (1)
1221 /* @brief Clock name for the PE oscillator clock source */
1222 #define FEATURE_CAN_PE_OSC_CLK_NAME SOSC_CLK
1223 
1224 /* LPTMR module features */
1225 
1226 /* @brief LPTMR pulse counter input options */
1227 #define FEATURE_LPTMR_HAS_INPUT_ALT1_SELECTION (1U)
1228 
1229 /* OSIF module features */
1230 
1231 #define FEATURE_OSIF_USE_SYSTICK (1)
1232 #define FEATURE_OSIF_USE_PIT (0)
1233 
1234 #endif /* S32K118_FEATURES_H */
1235 
1236 /*******************************************************************************
1237  * EOF
1238  ******************************************************************************/
trgmux_trigger_source_e
Enumeration for trigger source module of TRGMUX.
trgmux_target_module_e
Enumeration for target module of TRGMUX.
clock_names_t
Clock names.
dma_request_source_t
Structure for the DMA hardware request.