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#define | SBC_UJA_REG_ADDR_MASK (0xFEU) |
| Register address macros. More...
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#define | SBC_UJA_REG_ADDR_SHIFT (1U) |
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#define | SBC_UJA_REG_ADDR_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_REG_ADDR_SHIFT)&SBC_UJA_REG_ADDR_MASK) |
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#define | SBC_UJA_WTDOG_CTR_WMC_MASK (0xE0U) |
| Watchdog mode control, watchdog mode control macros. More...
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#define | SBC_UJA_WTDOG_CTR_WMC_SHIFT (5U) |
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#define | SBC_UJA_WTDOG_CTR_WMC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_WMC_SHIFT)&SBC_UJA_WTDOG_CTR_WMC_MASK) |
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#define | SBC_UJA_WTDOG_CTR_NWP_MASK (0x0FU) |
| Watchdog mode control, nominal watchdog period macros. More...
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#define | SBC_UJA_WTDOG_CTR_NWP_SHIFT (0U) |
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#define | SBC_UJA_WTDOG_CTR_NWP_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_NWP_SHIFT)&SBC_UJA_WTDOG_CTR_NWP_MASK) |
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#define | SBC_UJA_WTDOG_CTR_MASK (SBC_UJA_WTDOG_CTR_WMC_MASK | SBC_UJA_WTDOG_CTR_NWP_MASK) |
| Watchdog control macros. More...
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#define | SBC_UJA_WTDOG_CTR_SHIFT (0U) |
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#define | SBC_UJA_WTDOG_CTR_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_CTR_SHIFT)&SBC_UJA_WTDOG_CTR_MASK) |
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#define | SBC_UJA_MODE_MC_MASK (0x07U) |
| Mode control, mode control macros. More...
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#define | SBC_UJA_MODE_MC_SHIFT (0U) |
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#define | SBC_UJA_MODE_MC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MODE_MC_SHIFT)&SBC_UJA_MODE_MC_MASK) |
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#define | SBC_UJA_MODE_MASK (SBC_UJA_MODE_MC_MASK) |
| Mode control macros. More...
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#define | SBC_UJA_MODE_SHIFT (SBC_UJA_MODE_MC_SHIFT) |
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#define | SBC_UJA_MODE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MODE_SHIFT)&SBC_UJA_MODE_MASK) |
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#define | SBC_UJA_FAIL_SAFE_LHC_MASK (0x04U) |
| Fail-safe control register, LIMP home control macros. More...
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#define | SBC_UJA_FAIL_SAFE_LHC_SHIFT (2U) |
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#define | SBC_UJA_FAIL_SAFE_LHC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_LHC_SHIFT)&SBC_UJA_FAIL_SAFE_LHC_MASK) |
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#define | SBC_UJA_FAIL_SAFE_RCC_MASK (0x03U) |
| Fail-safe control register, reset counter control macros. More...
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#define | SBC_UJA_FAIL_SAFE_RCC_SHIFT (0U) |
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#define | SBC_UJA_FAIL_SAFE_RCC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_RCC_SHIFT)&SBC_UJA_FAIL_SAFE_RCC_MASK) |
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#define | SBC_UJA_FAIL_SAFE_MASK (SBC_UJA_FAIL_SAFE_LHC_MASK | SBC_UJA_FAIL_SAFE_RCC_MASK) |
| Fail-safe control register macros. More...
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#define | SBC_UJA_FAIL_SAFE_SHIFT (0U) |
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#define | SBC_UJA_FAIL_SAFE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_FAIL_SAFE_SHIFT)&SBC_UJA_FAIL_SAFE_MASK) |
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#define | SBC_UJA_MAIN_OTWS_MASK (0x40U) |
| Main status register, Overtemperature warning status macros. More...
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#define | SBC_UJA_MAIN_OTWS_SHIFT (6U) |
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#define | SBC_UJA_MAIN_OTWS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_OTWS_SHIFT)&SBC_UJA_MAIN_OTWS_MASK) |
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#define | SBC_UJA_MAIN_NMS_MASK (0x20U) |
| Main status register, Normal mode status macros. More...
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#define | SBC_UJA_MAIN_NMS_SHIFT (5U) |
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#define | SBC_UJA_MAIN_NMS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_NMS_SHIFT)&SBC_UJA_MAIN_NMS_MASK) |
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#define | SBC_UJA_MAIN_RSS_MASK (0x1FU) |
| Main status register, Reset source status macros. More...
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#define | SBC_UJA_MAIN_RSS_SHIFT (0U) |
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#define | SBC_UJA_MAIN_RSS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_RSS_SHIFT)&SBC_UJA_MAIN_RSS_MASK) |
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#define | SBC_UJA_MAIN_MASK (SBC_UJA_MAIN_OTWS_MASK | SBC_UJA_MAIN_NMS_MASK | SBC_UJA_MAIN_RSS_MASK) |
| Main status macros. More...
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#define | SBC_UJA_MAIN_SHIFT (0U) |
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#define | SBC_UJA_MAIN_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MAIN_SHIFT)&SBC_UJA_MAIN_MASK) |
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#define | SBC_UJA_SYS_EVNT_OTWE_MASK (0x04U) |
| System event capture enable, overtemperature warning enable macros. More...
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#define | SBC_UJA_SYS_EVNT_OTWE_SHIFT (2U) |
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#define | SBC_UJA_SYS_EVNT_OTWE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_OTWE_SHIFT)&SBC_UJA_SYS_EVNT_OTWE_MASK) |
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#define | SBC_UJA_SYS_EVNT_SPIFE_MASK (0x02U) |
| System event capture enable, SPI failure enable. More...
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#define | SBC_UJA_SYS_EVNT_SPIFE_SHIFT (1U) |
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#define | SBC_UJA_SYS_EVNT_SPIFE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_SPIFE_SHIFT)&SBC_UJA_SYS_EVNT_SPIFE_MASK) |
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#define | SBC_UJA_SYS_EVNT_MASK (SBC_UJA_SYS_EVNT_OTWE_MASK | SBC_UJA_SYS_EVNT_SPIFE_MASK) |
| System event capture enable. More...
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#define | SBC_UJA_SYS_EVNT_SHIFT (1U) |
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#define | SBC_UJA_SYS_EVNT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_SHIFT)&SBC_UJA_SYS_EVNT_MASK) |
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#define | SBC_UJA_WTDOG_STAT_FNMS_MASK (0x08U) |
| Watchdog status register, forced Normal mode status macros. More...
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#define | SBC_UJA_WTDOG_STAT_FNMS_SHIFT (3U) |
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#define | SBC_UJA_WTDOG_STAT_FNMS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_FNMS_SHIFT)&SBC_UJA_WTDOG_STAT_FNMS_MASK) |
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#define | SBC_UJA_WTDOG_STAT_SDMS_MASK (0x04U) |
| Watchdog status register, Software Development mode status macros. More...
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#define | SBC_UJA_WTDOG_STAT_SDMS_SHIFT (2U) |
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#define | SBC_UJA_WTDOG_STAT_SDMS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_SDMS_SHIFT)&SBC_UJA_WTDOG_STAT_SDMS_MASK) |
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#define | SBC_UJA_WTDOG_STAT_WDS_MASK (0x03U) |
| Watchdog status register, watchdog status macros. More...
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#define | SBC_UJA_WTDOG_STAT_WDS_SHIFT (0U) |
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#define | SBC_UJA_WTDOG_STAT_WDS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_WDS_SHIFT)&SBC_UJA_WTDOG_STAT_WDS_MASK) |
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#define | SBC_UJA_WTDOG_STAT_MASK |
| Watchdog status macros. More...
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#define | SBC_UJA_WTDOG_STAT_SHIFT (0U) |
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#define | SBC_UJA_WTDOG_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WTDOG_STAT_SHIFT)&SBC_UJA_WTDOG_STAT_MASK) |
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#define | SBC_UJA_MEMORY_X_MASK (0xFFU) |
| Memory X macros. More...
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#define | SBC_UJA_MEMORY_X_SHIFT (0U) |
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#define | SBC_UJA_MEMORY_X_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MEMORY_X_SHIFT)&SBC_UJA_MEMORY_X_MASK) |
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#define | SBC_UJA_LOCK_LK6C_MASK (0x40U) |
| Lock control 6: address area 0x68 to 0x6F macros. More...
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#define | SBC_UJA_LOCK_LK6C_SHIFT (6U) |
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#define | SBC_UJA_LOCK_LK6C_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK6C_SHIFT)&SBC_UJA_LOCK_LK6C_MASK) |
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#define | SBC_UJA_LOCK_LK5C_MASK (0x20U) |
| Lock control control 5: address area 0x50 to 0x5F - unused register range macros. More...
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#define | SBC_UJA_LOCK_LK5C_SHIFT (5U) |
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#define | SBC_UJA_LOCK_LK5C_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK5C_SHIFT)&SBC_UJA_LOCK_LK5C_MASK) |
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#define | SBC_UJA_LOCK_LK4C_MASK (0x10U) |
| Lock control 4: address area 0x40 to 0x4F - WAKE pin control macros. More...
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#define | SBC_UJA_LOCK_LK4C_SHIFT (4U) |
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#define | SBC_UJA_LOCK_LK4C_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK4C_SHIFT)&SBC_UJA_LOCK_LK4C_MASK) |
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#define | SBC_UJA_LOCK_LK3C_MASK (0x08U) |
| Lock control 3: address area 0x30 to 0x3F - unused register range macros. More...
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#define | SBC_UJA_LOCK_LK3C_SHIFT (3U) |
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#define | SBC_UJA_LOCK_LK3C_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK3C_SHIFT)&SBC_UJA_LOCK_LK3C_MASK) |
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#define | SBC_UJA_LOCK_LK2C_MASK (0x04U) |
| Lock control 2: address area 0x20 to 0x2F - transceiver control macros. More...
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#define | SBC_UJA_LOCK_LK2C_SHIFT (2U) |
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#define | SBC_UJA_LOCK_LK2C_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK2C_SHIFT)&SBC_UJA_LOCK_LK2C_MASK) |
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#define | SBC_UJA_LOCK_LK1C_MASK (0x02U) |
| Lock control 1: address area 0x10 to 0x1F - regulator control macros. More...
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#define | SBC_UJA_LOCK_LK1C_SHIFT (1U) |
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#define | SBC_UJA_LOCK_LK1C_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK1C_SHIFT)&SBC_UJA_LOCK_LK1C_MASK) |
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#define | SBC_UJA_LOCK_LK0C_MASK (0x01U) |
| Lock control 0: address area 0x06 to 0x09 - general-purpose memory macros. More...
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#define | SBC_UJA_LOCK_LK0C_SHIFT (0U) |
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#define | SBC_UJA_LOCK_LK0C_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LK0C_SHIFT)&SBC_UJA_LOCK_LK0C_MASK) |
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#define | SBC_UJA_LOCK_LKNC_MASK |
| Lock control N macros. More...
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#define | SBC_UJA_LOCK_LKNC_SHIFT (0U) |
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#define | SBC_UJA_LOCK_LKNC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_LOCK_LKNC_SHIFT)&SBC_UJA_LOCK_LKNC_MASK) |
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#define | SBC_UJA_REGULATOR_PDC_MASK (0x40U) |
| Regulator control register, power distribution control macros. More...
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#define | SBC_UJA_REGULATOR_PDC_SHIFT (6U) |
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#define | SBC_UJA_REGULATOR_PDC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_PDC_SHIFT)&SBC_UJA_REGULATOR_PDC_MASK) |
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#define | SBC_UJA_REGULATOR_V2C_MASK (0x0CU) |
| Regulator control register, V2/VEXT configuration macros. More...
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#define | SBC_UJA_REGULATOR_V2C_SHIFT (2U) |
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#define | SBC_UJA_REGULATOR_V2C_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_V2C_SHIFT)&SBC_UJA_REGULATOR_V2C_MASK) |
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#define | SBC_UJA_REGULATOR_V1RTC_MASK (0x03U) |
| Regulator control register, set V1 reset threshold macros. More...
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#define | SBC_UJA_REGULATOR_V1RTC_SHIFT (0U) |
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#define | SBC_UJA_REGULATOR_V1RTC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_V1RTC_SHIFT)&SBC_UJA_REGULATOR_V1RTC_MASK) |
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#define | SBC_UJA_REGULATOR_MASK (SBC_UJA_REGULATOR_PDC_MASK | SBC_UJA_REGULATOR_V2C_MASK | SBC_UJA_REGULATOR_V1RTC_MASK) |
| Regulator control register macros. More...
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#define | SBC_UJA_REGULATOR_SHIFT (0U) |
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#define | SBC_UJA_REGULATOR_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_REGULATOR_SHIFT)&SBC_UJA_REGULATOR_MASK) |
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#define | SBC_UJA_SUPPLY_STAT_V2S_MASK (0x06U) |
| Supply voltage status register, V2/VEXT status macros. More...
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#define | SBC_UJA_SUPPLY_STAT_V2S_SHIFT (1U) |
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#define | SBC_UJA_SUPPLY_STAT_V2S_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_V2S_SHIFT)&SBC_UJA_SUPPLY_STAT_V2S_MASK) |
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#define | SBC_UJA_SUPPLY_STAT_V1S_MASK (0x01U) |
| Supply voltage status register, V1 status macros. More...
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#define | SBC_UJA_SUPPLY_STAT_V1S_SHIFT (0U) |
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#define | SBC_UJA_SUPPLY_STAT_V1S_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_V1S_SHIFT)&SBC_UJA_SUPPLY_STAT_V1S_MASK) |
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#define | SBC_UJA_SUPPLY_STAT_MASK (SBC_UJA_SUPPLY_STAT_V2S_MASK | SBC_UJA_SUPPLY_STAT_V1S_MASK) |
| Supply voltage status register macros. More...
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#define | SBC_UJA_SUPPLY_STAT_SHIFT (0U) |
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#define | SBC_UJA_SUPPLY_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_STAT_SHIFT)&SBC_UJA_SUPPLY_STAT_MASK) |
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#define | SBC_UJA_SUPPLY_EVNT_V2OE_MASK (0x04U) |
| Supply event capture enable register, V2/VEXT overvoltage enable macros. More...
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#define | SBC_UJA_SUPPLY_EVNT_V2OE_SHIFT (2U) |
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#define | SBC_UJA_SUPPLY_EVNT_V2OE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V2OE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V2OE_MASK) |
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#define | SBC_UJA_SUPPLY_EVNT_V2UE_MASK (0x02U) |
| Supply event capture enable register, V2/VEXT undervoltage enable macros. More...
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#define | SBC_UJA_SUPPLY_EVNT_V2UE_SHIFT (1U) |
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#define | SBC_UJA_SUPPLY_EVNT_V2UE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V2UE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V2UE_MASK) |
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#define | SBC_UJA_SUPPLY_EVNT_V1UE_MASK (0x01U) |
| Supply event capture enable register, V1 undervoltage enable macros. More...
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#define | SBC_UJA_SUPPLY_EVNT_V1UE_SHIFT (0U) |
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#define | SBC_UJA_SUPPLY_EVNT_V1UE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_V1UE_SHIFT)&SBC_UJA_SUPPLY_EVNT_V1UE_MASK) |
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#define | SBC_UJA_SUPPLY_EVNT_MASK |
| Supply event capture enable register macros. More...
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#define | SBC_UJA_SUPPLY_EVNT_SHIFT (0U) |
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#define | SBC_UJA_SUPPLY_EVNT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUPPLY_EVNT_SHIFT)&SBC_UJA_SUPPLY_EVNT_MASK) |
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#define | SBC_UJA_CAN_CFDC_MASK (0x40U) |
| CAN control register, CAN FD control macros. More...
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#define | SBC_UJA_CAN_CFDC_SHIFT (6U) |
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#define | SBC_UJA_CAN_CFDC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CFDC_SHIFT)&SBC_UJA_CAN_CFDC_MASK) |
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#define | SBC_UJA_CAN_PNCOK_MASK (0x20U) |
| CAN control register, CAN partial networking configuration OK macros. More...
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#define | SBC_UJA_CAN_PNCOK_SHIFT (5U) |
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#define | SBC_UJA_CAN_PNCOK_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_PNCOK_SHIFT)&SBC_UJA_CAN_PNCOK_MASK) |
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#define | SBC_UJA_CAN_CPNC_MASK (0x10U) |
| CAN control register, CAN partial networking control macros. More...
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#define | SBC_UJA_CAN_CPNC_SHIFT (4U) |
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#define | SBC_UJA_CAN_CPNC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CPNC_SHIFT)&SBC_UJA_CAN_CPNC_MASK) |
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#define | SBC_UJA_CAN_CMC_MASK (0x03U) |
| CAN control register, CAN mode control macros. More...
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#define | SBC_UJA_CAN_CMC_SHIFT (0U) |
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#define | SBC_UJA_CAN_CMC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_CMC_SHIFT)&SBC_UJA_CAN_CMC_MASK) |
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#define | SBC_UJA_CAN_MASK |
| CAN control register macros. More...
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#define | SBC_UJA_CAN_SHIFT (0U) |
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#define | SBC_UJA_CAN_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_CAN_SHIFT)&SBC_UJA_CAN_MASK) |
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#define | SBC_UJA_TRANS_STAT_CTS_MASK (0x80U) |
| Transceiver status register, CAN transceiver status macros. More...
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#define | SBC_UJA_TRANS_STAT_CTS_SHIFT (7U) |
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#define | SBC_UJA_TRANS_STAT_CTS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CTS_SHIFT)&SBC_UJA_TRANS_STAT_CTS_MASK) |
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#define | SBC_UJA_TRANS_STAT_CPNERR_MASK (0x40U) |
| Transceiver status register, CAN partial networking error macros. More...
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#define | SBC_UJA_TRANS_STAT_CPNERR_SHIFT (6U) |
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#define | SBC_UJA_TRANS_STAT_CPNERR_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CPNERR_SHIFT)&SBC_UJA_TRANS_STAT_CPNERR_MASK) |
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#define | SBC_UJA_TRANS_STAT_CPNS_MASK (0x20U) |
| Transceiver status register, CAN partial networking status macros. More...
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#define | SBC_UJA_TRANS_STAT_CPNS_SHIFT (5U) |
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#define | SBC_UJA_TRANS_STAT_CPNS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CPNS_SHIFT)&SBC_UJA_TRANS_STAT_CPNS_MASK) |
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#define | SBC_UJA_TRANS_STAT_COSCS_MASK (0x10U) |
| Transceiver status register, CAN oscillator status macros. More...
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#define | SBC_UJA_TRANS_STAT_COSCS_SHIFT (4U) |
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#define | SBC_UJA_TRANS_STAT_COSCS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_COSCS_SHIFT)&SBC_UJA_TRANS_STAT_COSCS_MASK) |
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#define | SBC_UJA_TRANS_STAT_CBSS_MASK (0x08U) |
| Transceiver status register, CAN-bus silence status macros. More...
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#define | SBC_UJA_TRANS_STAT_CBSS_SHIFT (3U) |
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#define | SBC_UJA_TRANS_STAT_CBSS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CBSS_SHIFT)&SBC_UJA_TRANS_STAT_CBSS_MASK) |
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#define | SBC_UJA_TRANS_STAT_VCS_MASK (0x02U) |
| Transceiver status register, VCAN status macros. More...
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#define | SBC_UJA_TRANS_STAT_VCS_SHIFT (1U) |
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#define | SBC_UJA_TRANS_STAT_VCS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_VCS_SHIFT)&SBC_UJA_TRANS_STAT_VCS_MASK) |
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#define | SBC_UJA_TRANS_STAT_CFS_MASK (0x01U) |
| Transceiver status register, CAN failure status macros. More...
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#define | SBC_UJA_TRANS_STAT_CFS_SHIFT (0U) |
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#define | SBC_UJA_TRANS_STAT_CFS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_CFS_SHIFT)&SBC_UJA_TRANS_STAT_CFS_MASK) |
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#define | SBC_UJA_TRANS_STAT_MASK |
| Transceiver status register macros. More...
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#define | SBC_UJA_TRANS_STAT_SHIFT (0U) |
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#define | SBC_UJA_TRANS_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_STAT_SHIFT)&SBC_UJA_TRANS_STAT_MASK) |
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#define | SBC_UJA_TRANS_EVNT_CBSE_MASK (0x10U) |
| Transceiver event capture enable register, CAN-bus silence enable macros. More...
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#define | SBC_UJA_TRANS_EVNT_CBSE_SHIFT (4U) |
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#define | SBC_UJA_TRANS_EVNT_CBSE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CBSE_SHIFT)&SBC_UJA_TRANS_EVNT_CBSE_MASK) |
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#define | SBC_UJA_TRANS_EVNT_CFE_MASK (0x02U) |
| Transceiver event capture enable register, CAN failure enable macros. More...
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#define | SBC_UJA_TRANS_EVNT_CFE_SHIFT (1U) |
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#define | SBC_UJA_TRANS_EVNT_CFE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CFE_SHIFT)&SBC_UJA_TRANS_EVNT_CFE_MASK) |
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#define | SBC_UJA_TRANS_EVNT_CWE_MASK (0x01U) |
| Transceiver event capture enable register, CAN wake-up enable. More...
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#define | SBC_UJA_TRANS_EVNT_CWE_SHIFT (0U) |
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#define | SBC_UJA_TRANS_EVNT_CWE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_CWE_SHIFT)&SBC_UJA_TRANS_EVNT_CWE_MASK) |
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#define | SBC_UJA_TRANS_EVNT_MASK |
| Transceiver event capture enable register macros. More...
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#define | SBC_UJA_TRANS_EVNT_SHIFT (0U) |
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#define | SBC_UJA_TRANS_EVNT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_SHIFT)&SBC_UJA_TRANS_EVNT_MASK) |
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#define | SBC_UJA_DAT_RATE_CDR_MASK (0x07U) |
| Data rate register, CAN data rate selection macros. More...
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#define | SBC_UJA_DAT_RATE_CDR_SHIFT (0U) |
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#define | SBC_UJA_DAT_RATE_CDR_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_DAT_RATE_CDR_SHIFT)&SBC_UJA_DAT_RATE_CDR_MASK) |
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#define | SBC_UJA_DAT_RATE_MASK (SBC_UJA_DAT_RATE_CDR_MASK) |
| Data rate register macros. More...
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#define | SBC_UJA_DAT_RATE_SHIFT (SBC_UJA_DAT_RATE_CDR_SHIFT) |
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#define | SBC_UJA_DAT_RATE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_DAT_RATE_SHIFT)&SBC_UJA_DAT_RATE_MASK) |
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#define | SBC_UJA_IDENTIF_0700_MASK (0xFFU) |
| Identifier 0x27 - ID07:ID00 bits macros. More...
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#define | SBC_UJA_IDENTIF_0700_SHIFT (0U) |
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#define | SBC_UJA_IDENTIF_0700_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_0700_SHIFT)&SBC_UJA_IDENTIF_0700_MASK) |
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#define | SBC_UJA_IDENTIF_1508_MASK (0xFFU) |
| Identifier 0x28 - ID15:ID08 bits macros. More...
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#define | SBC_UJA_IDENTIF_1508_SHIFT (0U) |
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#define | SBC_UJA_IDENTIF_1508_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_1508_SHIFT)&SBC_UJA_IDENTIF_1508_MASK) |
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#define | SBC_UJA_IDENTIF_2318_MASK (0xFCU) |
| Identifier 0x29 - ID23:ID18 bits macros. More...
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#define | SBC_UJA_IDENTIF_2318_SHIFT (2U) |
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#define | SBC_UJA_IDENTIF_2318_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2318_SHIFT)&SBC_UJA_IDENTIF_2318_MASK) |
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#define | SBC_UJA_IDENTIF_1716_MASK (0x03U) |
| Identifier 0x29 - ID17:ID16 bits macros. More...
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#define | SBC_UJA_IDENTIF_1716_SHIFT (0U) |
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#define | SBC_UJA_IDENTIF_1716_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_1716_SHIFT)&SBC_UJA_IDENTIF_1716_MASK) |
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#define | SBC_UJA_IDENTIF_2316_MASK (0xFFU) |
| Identifier 0x29 - ID23:ID16 bits macros. More...
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#define | SBC_UJA_IDENTIF_2316_SHIFT (0U) |
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#define | SBC_UJA_IDENTIF_2316_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2316_SHIFT)&SBC_UJA_IDENTIF_2316_MASK) |
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#define | SBC_UJA_IDENTIF_2824_MASK (0x1FU) |
| Identifier 0x2A - ID28:ID24 bits macros. More...
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#define | SBC_UJA_IDENTIF_2824_SHIFT (0U) |
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#define | SBC_UJA_IDENTIF_2824_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_2824_SHIFT)&SBC_UJA_IDENTIF_2824_MASK) |
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#define | SBC_UJA_IDENTIF_X_MASK (0xFFU) |
| Identifier X macros (0x27-0x2Ah). More...
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#define | SBC_UJA_IDENTIF_X_SHIFT (0U) |
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#define | SBC_UJA_IDENTIF_X_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_0_SHIFT)&SBC_UJA_IDENTIF_0_MASK) |
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#define | SBC_UJA_MASK_0700_MASK (0xFFU) |
| Mask 0x2b - M07:M00 macros. More...
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#define | SBC_UJA_MASK_0700_SHIFT (0U) |
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#define | SBC_UJA_MASK_0700_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_0700_SHIFT)&SBC_UJA_MASK_0700_MASK) |
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#define | SBC_UJA_MASK_1508_MASK (0xFFU) |
| Mask 0x2c - M15:M08 macros. More...
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#define | SBC_UJA_MASK_1508_SHIFT (0U) |
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#define | SBC_UJA_MASK_1508_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_1508_SHIFT)&SBC_UJA_MASK_1508_MASK) |
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#define | SBC_UJA_MASK_2318_MASK (0xFCU) |
| Mask 0x2d - M23:M18 macros. More...
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#define | SBC_UJA_MASK_2318_SHIFT (2U) |
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#define | SBC_UJA_MASK_2318_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2318_SHIFT)&SBC_UJA_MASK_2318_MASK) |
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#define | SBC_UJA_MASK_1716_MASK (0x03U) |
| Mask 0x2d - M17:M16 macros. More...
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#define | SBC_UJA_MASK_1716_SHIFT (2U) |
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#define | SBC_UJA_MASK_1716_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_1716_SHIFT)&SBC_UJA_MASK_1716_MASK) |
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#define | SBC_UJA_MASK_2316_MASK (0xFFU) |
| Mask 0x2d - M23:M16 macros. More...
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#define | SBC_UJA_MASK_2316_SHIFT (0U) |
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#define | SBC_UJA_MASK_2316_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2316_SHIFT)&SBC_UJA_MASK_2316_MASK) |
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#define | SBC_UJA_MASK_2824_MASK (0x1FU) |
| Mask 0x2e - M28:M24 macros. More...
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#define | SBC_UJA_MASK_2824_SHIFT (0U) |
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#define | SBC_UJA_MASK_2824_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_2824_SHIFT)&SBC_UJA_MASK_2824_MASK) |
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#define | SBC_UJA_MASK_X_MASK (0xFFU) |
| Mask X macros (0x2b-0x2e). More...
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#define | SBC_UJA_MASK_X_SHIFT (0U) |
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#define | SBC_UJA_MASK_X_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MASK_X_SHIFT)&SBC_UJA_MASK_X_MASK) |
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#define | SBC_UJA_FRAME_CTR_IDE_MASK (0x80U) |
| Frame control register, identifier format macros. More...
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#define | SBC_UJA_FRAME_CTR_IDE_SHIFT (7U) |
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#define | SBC_UJA_FRAME_CTR_IDE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_IDE_SHIFT)&SBC_UJA_FRAME_CTR_IDE_MASK) |
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#define | SBC_UJA_FRAME_CTR_PNDM_MASK (0x40U) |
| Frame control register, partial networking data mask macros. More...
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#define | SBC_UJA_FRAME_CTR_PNDM_SHIFT (6U) |
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#define | SBC_UJA_FRAME_CTR_PNDM_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_PNDM_SHIFT)&SBC_UJA_FRAME_CTR_PNDM_MASK) |
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#define | SBC_UJA_FRAME_CTR_DLC_MASK (0x0FU) |
| Frame control register, number of data bytes expected in a CAN frame macros. More...
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#define | SBC_UJA_FRAME_CTR_DLC_SHIFT (0U) |
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#define | SBC_UJA_FRAME_CTR_DLC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_DLC_SHIFT)&SBC_UJA_FRAME_CTR_DLC_MASK) |
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#define | SBC_UJA_FRAME_CTR_MASK |
| Frame control register. More...
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#define | SBC_UJA_FRAME_CTR_SHIFT (0U) |
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#define | SBC_UJA_FRAME_CTR_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_FRAME_CTR_SHIFT)&SBC_UJA_FRAME_CTR_MASK) |
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#define | SBC_UJA_DATA_MASK_X_MASK (0xFFU) |
| Data mask registers (0x68 to 0x6F) macros Data mask 0-7 configuration. More...
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#define | SBC_UJA_DATA_MASK_X_SHIFT (0U) |
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#define | SBC_UJA_DATA_MASK_X_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_DATA_MASK_X_SHIFT)&SBC_UJA_DATA_MASK_X_MASK) |
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#define | SBC_UJA_WAKE_STAT_WPVS_MASK (0x02FU) |
| WAKE pin status register, WAKE pin status macros. More...
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#define | SBC_UJA_WAKE_STAT_WPVS_SHIFT (1U) |
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#define | SBC_UJA_WAKE_STAT_WPVS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_STAT_WPVS_SHIFT)&SBC_UJA_WAKE_STAT_WPVS_MASK) |
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#define | SBC_UJA_WAKE_STAT_MASK (SBC_UJA_WAKE_STAT_WPVS_MASK) |
| WAKE pin status register. More...
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#define | SBC_UJA_WAKE_STAT_SHIFT (SBC_UJA_WAKE_STAT_WPVS_SHIFT) |
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#define | SBC_UJA_WAKE_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_STAT_SHIFT)&SBC_UJA_WAKE_STAT_MASK) |
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#define | SBC_UJA_WAKE_EN_WPRE_MASK (0x02U) |
| WAKE pin event capture enable register, WAKE pin rising-edge enable macros. More...
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#define | SBC_UJA_WAKE_EN_WPRE_SHIFT (1U) |
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#define | SBC_UJA_WAKE_EN_WPRE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_WPRE_SHIFT)&SBC_UJA_WAKE_EN_WPRE_MASK) |
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#define | SBC_UJA_WAKE_EN_WPFE_MASK (0x01U) |
| WAKE pin event capture enable register, WAKE pin falling-edge enable macros. More...
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#define | SBC_UJA_WAKE_EN_WPFE_SHIFT (0U) |
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#define | SBC_UJA_WAKE_EN_WPFE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_WPFE_SHIFT)&SBC_UJA_WAKE_EN_WPFE_MASK) |
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#define | SBC_UJA_WAKE_EN_MASK (SBC_UJA_WAKE_EN_WPRE_MASK | SBC_UJA_WAKE_EN_WPFE_MASK) |
| WAKE pin event capture enable register macros. More...
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#define | SBC_UJA_WAKE_EN_SHIFT (0U) |
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#define | SBC_UJA_WAKE_EN_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EN_SHIFT)&SBC_UJA_WAKE_EN_MASK) |
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#define | SBC_UJA_GL_EVNT_STAT_WPE_MASK (0x08U) |
| Global event status register, WAKE pin event macros. More...
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#define | SBC_UJA_GL_EVNT_STAT_WPE_SHIFT (3U) |
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#define | SBC_UJA_GL_EVNT_STAT_WPE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_WPE_SHIFT)&SBC_UJA_GL_EVNT_STAT_WPE_MASK) |
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#define | SBC_UJA_GL_EVNT_STAT_TRXE_MASK (0x04U) |
| Global event status register, transceiver event macros. More...
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#define | SBC_UJA_GL_EVNT_STAT_TRXE_SHIFT (2U) |
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#define | SBC_UJA_GL_EVNT_STAT_TRXE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_TRXE_SHIFT)&SBC_UJA_GL_EVNT_STAT_TRXE_MASK) |
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#define | SBC_UJA_GL_EVNT_STAT_SUPE_MASK (0x02U) |
| Global event status register, supply event macros. More...
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#define | SBC_UJA_GL_EVNT_STAT_SUPE_SHIFT (1U) |
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#define | SBC_UJA_GL_EVNT_STAT_SUPE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SUPE_SHIFT)&SBC_UJA_GL_EVNT_STAT_SUPE_MASK) |
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#define | SBC_UJA_GL_EVNT_STAT_SYSE_MASK (0x01U) |
| Global event status register, system event macros. More...
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#define | SBC_UJA_GL_EVNT_STAT_SYSE_SHIFT (0U) |
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#define | SBC_UJA_GL_EVNT_STAT_SYSE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SYSE_SHIFT)&SBC_UJA_GL_EVNT_STAT_SYSE_MASK) |
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#define | SBC_UJA_GL_EVNT_STAT_MASK |
| Global event status register macros. More...
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#define | SBC_UJA_GL_EVNT_STAT_SHIFT (0U) |
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#define | SBC_UJA_GL_EVNT_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_GL_EVNT_STAT_SHIFT)&SBC_UJA_GL_EVNT_STAT_MASK) |
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#define | SBC_UJA_SYS_EVNT_STAT_PO_MASK (0x10U) |
| System event status register, power-on macros. More...
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#define | SBC_UJA_SYS_EVNT_STAT_PO_SHIFT (4U) |
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#define | SBC_UJA_SYS_EVNT_STAT_PO_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_PO_SHIFT)&SBC_UJA_SYS_EVNT_STAT_PO_MASK) |
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#define | SBC_UJA_SYS_EVNT_STAT_OTW_MASK (0x04U) |
| System event status register, overtemperature warning macros. More...
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#define | SBC_UJA_SYS_EVNT_STAT_OTW_SHIFT (2U) |
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#define | SBC_UJA_SYS_EVNT_STAT_OTW_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_OTW_SHIFT)&SBC_UJA_SYS_EVNT_STAT_OTW_MASK) |
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#define | SBC_UJA_SYS_EVNT_STAT_SPIF_MASK (0x02U) |
| System event status register, SPI failure macros. More...
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#define | SBC_UJA_SYS_EVNT_STAT_SPIF_SHIFT (1U) |
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#define | SBC_UJA_SYS_EVNT_STAT_SPIF_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_SPIF_SHIFT)&SBC_UJA_SYS_EVNT_STAT_SPIF_MASK) |
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#define | SBC_UJA_SYS_EVNT_STAT_WDF_MASK (0x01U) |
| System event status register, watchdog failure macros. More...
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#define | SBC_UJA_SYS_EVNT_STAT_WDF_SHIFT (0U) |
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#define | SBC_UJA_SYS_EVNT_STAT_WDF_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_WDF_SHIFT)&SBC_UJA_SYS_EVNT_STAT_WDF_MASK) |
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#define | SBC_UJA_SYS_EVNT_STAT_MASK |
| System event status register macros. More...
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#define | SBC_UJA_SYS_EVNT_STAT_SHIFT (0U) |
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#define | SBC_UJA_SYS_EVNT_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SYS_EVNT_STAT_SHIFT)&SBC_UJA_SYS_EVNT_STAT_MASK) |
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#define | SBC_UJA_SUP_EVNT_STAT_V2O_MASK (0x04U) |
| Supply event status register, V2/VEXT overvoltage macros. More...
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#define | SBC_UJA_SUP_EVNT_STAT_V2O_SHIFT (2U) |
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#define | SBC_UJA_SUP_EVNT_STAT_V2O_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V2O_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V2O_MASK) |
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#define | SBC_UJA_SUP_EVNT_STAT_V2U_MASK (0x02U) |
| Supply event status register, V2/VEXT undervoltage macros. More...
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#define | SBC_UJA_SUP_EVNT_STAT_V2U_SHIFT (1U) |
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#define | SBC_UJA_SUP_EVNT_STAT_V2U_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V2U_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V2U_MASK) |
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#define | SBC_UJA_SUP_EVNT_STAT_V1U_MASK (0x01U) |
| Supply event status register, V1 undervoltage: macros. More...
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#define | SBC_UJA_SUP_EVNT_STAT_V1U_SHIFT (0U) |
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#define | SBC_UJA_SUP_EVNT_STAT_V1U_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_V1U_SHIFT)&SBC_UJA_SUP_EVNT_STAT_V1U_MASK) |
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#define | SBC_UJA_SUP_EVNT_STAT_MASK |
| Supply event status register macros. More...
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#define | SBC_UJA_SUP_EVNT_STAT_SHIFT (0U) |
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#define | SBC_UJA_SUP_EVNT_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SUP_EVNT_STAT_SHIFT)&SBC_UJA_SUP_EVNT_STAT_MASK) |
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#define | SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK (0x20U) |
| Transceiver event status register, partial networking frame detection error macros. More...
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#define | SBC_UJA_TRANS_EVNT_STAT_PNFDE_SHIFT (5U) |
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#define | SBC_UJA_TRANS_EVNT_STAT_PNFDE_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_PNFDE_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK) |
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#define | SBC_UJA_TRANS_EVNT_STAT_CBS_MASK (0x10U) |
| Transceiver event status register, CAN-bus status macros. More...
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#define | SBC_UJA_TRANS_EVNT_STAT_CBS_SHIFT (4U) |
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#define | SBC_UJA_TRANS_EVNT_STAT_CBS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CBS_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CBS_MASK) |
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#define | SBC_UJA_TRANS_EVNT_STAT_CF_MASK (0x02U) |
| Transceiver event status register, CAN failure. More...
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#define | SBC_UJA_TRANS_EVNT_STAT_CF_SHIFT (1U) |
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#define | SBC_UJA_TRANS_EVNT_STAT_CF_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CF_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CF_MASK) |
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#define | SBC_UJA_TRANS_EVNT_STAT_CW_MASK (0x01U) |
| Transceiver event status register, CAN wake-up. More...
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#define | SBC_UJA_TRANS_EVNT_STAT_CW_SHIFT (0U) |
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#define | SBC_UJA_TRANS_EVNT_STAT_CW_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_CW_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_CW_MASK) |
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#define | SBC_UJA_TRANS_EVNT_STAT_MASK |
| Transceiver event status register macros. More...
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#define | SBC_UJA_TRANS_EVNT_STAT_SHIFT (0U) |
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#define | SBC_UJA_TRANS_EVNT_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_TRANS_EVNT_STAT_SHIFT)&SBC_UJA_TRANS_EVNT_STAT_MASK) |
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#define | SBC_UJA_WAKE_EVNT_STAT_WPR_MASK (0x02U) |
| WAKE pin event status register, WAKE pin rising edge macros. More...
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#define | SBC_UJA_WAKE_EVNT_STAT_WPR_SHIFT (1U) |
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#define | SBC_UJA_WAKE_EVNT_STAT_WPR_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_WPR_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_WPR_MASK) |
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#define | SBC_UJA_WAKE_EVNT_STAT_WPF_MASK (0x01U) |
| WAKE pin event status register, WAKE pin falling edge macros. More...
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#define | SBC_UJA_WAKE_EVNT_STAT_WPF_SHIFT (0U) |
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#define | SBC_UJA_WAKE_EVNT_STAT_WPF_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_WPF_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_WPF_MASK) |
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#define | SBC_UJA_WAKE_EVNT_STAT_MASK (SBC_UJA_WAKE_EVNT_STAT_WPR_MASK | SBC_UJA_WAKE_EVNT_STAT_WPF_MASK) |
| WAKE pin event status register macros. More...
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#define | SBC_UJA_WAKE_EVNT_STAT_SHIFT (0U) |
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#define | SBC_UJA_WAKE_EVNT_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_WAKE_EVNT_STAT_SHIFT)&SBC_UJA_WAKE_EVNT_STAT_MASK) |
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#define | SBC_UJA_MTPNV_STAT_WRCNTS_MASK (0xFCU) |
| MTPNV status register, write counter status macros. More...
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#define | SBC_UJA_MTPNV_STAT_WRCNTS_SHIFT (2U) |
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#define | SBC_UJA_MTPNV_STAT_WRCNTS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_WRCNTS_SHIFT)&SBC_UJA_MTPNV_STAT_WRCNTS_MASK) |
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#define | SBC_UJA_MTPNV_STAT_ECCS_MASK (0x02U) |
| MTPNV status register, error correction code status. More...
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#define | SBC_UJA_MTPNV_STAT_ECCS_SHIFT (1U) |
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#define | SBC_UJA_MTPNV_STAT_ECCS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_ECCS_SHIFT)&SBC_UJA_MTPNV_STAT_ECCS_MASK) |
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#define | SBC_UJA_MTPNV_STAT_NVMPS_MASK (0x01U) |
| MTPNV status register, non-volatile memory programming status. More...
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#define | SBC_UJA_MTPNV_STAT_NVMPS_SHIFT (0U) |
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#define | SBC_UJA_MTPNV_STAT_NVMPS_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_NVMPS_SHIFT)&SBC_UJA_MTPNV_STAT_NVMPS_MASK) |
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#define | SBC_UJA_MTPNV_STAT_MASK |
| MTPNV status register macros. More...
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#define | SBC_UJA_MTPNV_STAT_SHIFT (0U) |
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#define | SBC_UJA_MTPNV_STAT_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_STAT_SHIFT)&SBC_UJA_MTPNV_STAT_MASK) |
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#define | SBC_UJA_START_UP_RLC_MASK (0x30U) |
| Start-up control register, RSTN output reset pulse width macros. More...
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#define | SBC_UJA_START_UP_RLC_SHIFT (4U) |
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#define | SBC_UJA_START_UP_RLC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_RLC_SHIFT)&SBC_UJA_START_UP_RLC_MASK) |
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#define | SBC_UJA_START_UP_V2SUC_MASK (0x08U) |
| Start-up control register, V2/VEXT start-up control macros. More...
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#define | SBC_UJA_START_UP_V2SUC_SHIFT (3U) |
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#define | SBC_UJA_START_UP_V2SUC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_V2SUC_SHIFT)&SBC_UJA_START_UP_V2SUC_MASK) |
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#define | SBC_UJA_START_UP_MASK (SBC_UJA_START_UP_RLC_MASK | SBC_UJA_START_UP_V2SUC_MASK) |
| Start-up control register macros. More...
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#define | SBC_UJA_START_UP_SHIFT (3U) |
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#define | SBC_UJA_START_UP_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_START_UP_SHIFT)&SBC_UJA_START_UP_MASK) |
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#define | SBC_UJA_SBC_V1RTSUC_MASK (0x30U) |
| SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up macros. More...
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#define | SBC_UJA_SBC_V1RTSUC_SHIFT (4U) |
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#define | SBC_UJA_SBC_V1RTSUC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_V1RTSUC_SHIFT)&SBC_UJA_SBC_V1RTSUC_MASK) |
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#define | SBC_UJA_SBC_FNMC_MASK (0x08U) |
| SBC configuration control register, Forced Normal mode control macros. More...
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#define | SBC_UJA_SBC_FNMC_SHIFT (3U) |
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#define | SBC_UJA_SBC_FNMC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_FNMC_SHIFT)&SBC_UJA_SBC_FNMC_MASK) |
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#define | SBC_UJA_SBC_SDMC_MASK (0x04U) |
| SBC configuration control register, Software Development mode control macros. More...
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#define | SBC_UJA_SBC_SDMC_SHIFT (2U) |
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#define | SBC_UJA_SBC_SDMC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SDMC_SHIFT)&SBC_UJA_SBC_SDMC_MASK) |
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#define | SBC_UJA_SBC_SLPC_MASK (0x01U) |
| SBC configuration control register, Sleep control macros. More...
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#define | SBC_UJA_SBC_SLPC_SHIFT (0U) |
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#define | SBC_UJA_SBC_SLPC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SLPC_SHIFT)&SBC_UJA_SBC_SLPC_MASK) |
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#define | SBC_UJA_SBC_MASK |
| SBC configuration control register macros. More...
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#define | SBC_UJA_SBC_SHIFT (0U) |
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#define | SBC_UJA_SBC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_SBC_SHIFT)&SBC_UJA_SBC_MASK) |
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#define | SBC_UJA_MTPNV_CRC_MASK (0xFFU) |
| MTPNV CRC control register macros. More...
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#define | SBC_UJA_MTPNV_CRC_SHIFT (0U) |
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#define | SBC_UJA_MTPNV_CRC_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_MTPNV_CRC_SHIFT)&SBC_UJA_MTPNV_CRC_MASK) |
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#define | SBC_UJA_IDENTIF_MASK (0xFFU) |
| Device identification register macros. More...
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#define | SBC_UJA_IDENTIF_SHIFT (0U) |
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#define | SBC_UJA_IDENTIF_F(x) ((uint8_t)((uint8_t)(x)<<SBC_UJA_IDENTIF_SHIFT)&SBC_UJA_IDENTIF_MASK) |
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