57 #ifdef FEATURE_DMA_HWV3
68 #if defined FEATURE_DMA_HAS_ERROR_IRQ
83 #if defined FEATURE_DMA_HAS_ERROR_IRQ
88 #ifdef DEV_ERROR_DETECT
105 #ifdef DEV_ERROR_DETECT
130 #ifdef DEV_ERROR_DETECT
136 DEV_ASSERT((edmaState != NULL) && (userConfig != NULL));
141 #ifdef DEV_ERROR_DETECT
157 s_virtEdmaState = edmaState;
160 volatile uint8_t *clearStructPtr = (
volatile uint8_t *)s_virtEdmaState;
162 while (clearSize > 0U)
172 edmaRegBase = s_edmaBase[index];
175 EDMA_Init(edmaRegBase);
177 #ifdef FEATURE_DMA_HWV3
179 EDMA_SetChannelArbitrationMode(edmaRegBase, userConfig->
chnArbitration);
182 EDMA_SetChannelArbitrationMode(edmaRegBase, userConfig->
chnArbitration);
183 #if (FEATURE_DMA_CHANNEL_GROUP_COUNT > 0x1U)
184 EDMA_SetGroupArbitrationMode(edmaRegBase, userConfig->groupArbitration);
185 EDMA_SetGroupPriority(edmaRegBase, userConfig->groupPriority);
189 EDMA_SetHaltOnErrorCmd(edmaRegBase, userConfig->
haltOnError);
192 #if defined FEATURE_DMA_HAS_ERROR_IRQ
197 irqNumber = s_edmaErrIrqId[index];
213 DMAMUX_Init(s_dmaMuxBase[index]);
217 if ((chnStateArray != NULL) && (chnConfigArray != NULL))
219 for (index = 0U; index < chnCount; index++)
224 edmaStatus = chnInitStatus;
245 #if defined FEATURE_DMA_HAS_ERROR_IRQ
250 irqNumber = s_edmaErrIrqId[index];
255 if (s_virtEdmaState != NULL)
262 if (chnState != NULL)
275 s_virtEdmaState = NULL;
291 DEV_ASSERT((edmaChannelState != NULL) && (edmaChannelConfig != NULL));
311 DMA_Type * edmaRegBase = s_edmaBase[dmaInstance];
312 #ifdef FEATURE_DMA_HWV3
314 EDMA_SetChannelPriorityGroup(edmaRegBase, dmaChannel, edmaChannelConfig->groupPriority);
320 EDMA_SetChannelPriority(edmaRegBase, dmaChannel, edmaChannelConfig->
channelPriority);
378 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
379 DMAMUX_Type *dmaMuxRegBase = s_dmaMuxBase[dmaMuxInstance];
388 uint8_t *clearStructPtr = (uint8_t *)reqChn;
390 while (clearSize > 0U)
398 reqChn->
virtChn = virtualChannel;
401 EDMA_SetErrorIntCmd(edmaRegBase, dmaChannel,
true);
404 DMAMUX_SetChannelCmd(dmaMuxRegBase, dmaMuxChannel,
false);
405 DMAMUX_SetChannelSource(dmaMuxRegBase, dmaMuxChannel, sourceDmamuxChannel);
406 DMAMUX_SetChannelCmd(dmaMuxRegBase, dmaMuxChannel,
true);
409 EDMA_TCDClearReg(edmaRegBase, dmaChannel);
441 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
444 EDMA_SetDmaRequestCmd(edmaRegBase, dmaChannel,
false);
447 uint8_t *clearStructPtr = (uint8_t *)chnState;
449 while (clearSize > 0U)
475 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
476 EDMA_ClearDoneStatusFlag(edmaRegBase, dmaChannel);
477 EDMA_ClearIntStatusFlag(edmaRegBase, dmaChannel);
488 uint8_t *byteAccess = (uint8_t *)stcd;
490 while (clearSize > 0U)
509 if (chnState != NULL)
531 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
532 EDMA_SetDmaRequestCmd(edmaRegBase, dmaChannel,
false);
534 if (chnState != NULL)
537 EDMA_ClearErrorIntStatusFlag(edmaRegBase, dmaChannel);
544 EDMA_SetHaltCmd(edmaRegBase,
false);
559 uint32_t dataBufferSize)
570 #ifdef DEV_ERROR_DETECT
572 DEV_ASSERT(EDMA_DRV_ValidTransferSize(transferSize));
581 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
582 uint8_t transferOffset;
591 transferOffset = (uint8_t) (1U << ((uint8_t)transferSize));
596 if ((dataBufferSize % transferOffset) != 0U)
604 EDMA_TCDClearReg(edmaRegBase, dmaChannel);
606 #ifdef FEATURE_DMA_ENGINE_STALL
608 EDMA_TCDSetEngineStall(edmaRegBase, dmaChannel, EDMA_ENGINE_STALL_4_CYCLES);
612 EDMA_TCDSetSrcAddr(edmaRegBase, dmaChannel, srcAddr);
613 EDMA_TCDSetDestAddr(edmaRegBase, dmaChannel, destAddr);
622 EDMA_TCDSetSrcOffset(edmaRegBase, dmaChannel, 0);
623 EDMA_TCDSetDestOffset(edmaRegBase, dmaChannel, (int8_t) transferOffset);
626 EDMA_TCDSetSrcOffset(edmaRegBase, dmaChannel, (int8_t) transferOffset);
627 EDMA_TCDSetDestOffset(edmaRegBase, dmaChannel, 0);
630 EDMA_TCDSetSrcOffset(edmaRegBase, dmaChannel, (int8_t) transferOffset);
631 EDMA_TCDSetDestOffset(edmaRegBase, dmaChannel, (int8_t) transferOffset);
634 EDMA_TCDSetSrcOffset(edmaRegBase, dmaChannel, 0);
635 EDMA_TCDSetDestOffset(edmaRegBase, dmaChannel, 0);
643 EDMA_TCDSetNbytes(edmaRegBase, dmaChannel, dataBufferSize);
646 EDMA_TCDSetMajorCount(edmaRegBase, dmaChannel, 1U);
649 EDMA_TCDSetMajorCompleteIntCmd(edmaRegBase, dmaChannel,
true);
669 bool disableReqOnCompletion)
690 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
693 EDMA_TCDSetMajorCount(edmaRegBase, dmaChannel, blockCount);
696 EDMA_TCDSetDisableDmaRequestAfterTCDDoneCmd(edmaRegBase, dmaChannel, disableReqOnCompletion);
728 ((transferConfig->
srcAddr % (((uint32_t)1U) << (uint32_t)transferConfig->
srcModulo)) == 0U));
730 ((transferConfig->
destAddr % (((uint32_t)1U) << (uint32_t)transferConfig->
destModulo)) == 0U));
735 #ifdef FEATURE_DMA_HWV3
741 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
742 #ifdef FEATURE_DMA_HWV3
743 EDMA_SetMinorLoopMappingCmd(edmaRegBase, dmaChannel,
true);
745 EDMA_SetMinorLoopMappingCmd(edmaRegBase,
true);
764 uint32_t bytesOnEachRequest,
779 DEV_ASSERT((stcd != NULL) && (srcList != NULL) && (destList != NULL));
781 #ifdef DEV_ERROR_DETECT
783 DEV_ASSERT(EDMA_DRV_ValidTransferSize(transferSize));
787 uint16_t transferOffset = 0U;
788 uint32_t stcdAlignedAddr =
STCD_ADDR(stcd);
800 transferOffset = (uint16_t) (1UL << ((uint16_t)transferSize));
805 if ((bytesOnEachRequest % transferOffset) != 0U)
811 uint8_t *clearStructPtr = (uint8_t *)(&edmaTransferConfig);
813 while (clearSize > 0U)
820 clearStructPtr = (uint8_t *)(&edmaLoopConfig);
822 while (clearSize > 0U)
846 for (i = 0U; (i < tcdCount) && (retStatus ==
STATUS_SUCCESS); i++)
850 if ((srcList[i].length != destList[i].length) || (srcList[i].
type != destList[i].
type))
857 switch (srcList[i].type)
863 edmaTransferConfig.
destOffset = (int16_t) transferOffset;
867 edmaTransferConfig.
srcOffset = (int16_t) transferOffset;
873 edmaTransferConfig.
srcOffset = (int16_t) transferOffset;
875 edmaTransferConfig.
destOffset = (int16_t) transferOffset;
889 if (i == ((uint8_t)(tcdCount - 1U)))
939 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
940 EDMA_SetDmaRequestCmd(edmaRegBase, dmaChannel,
true);
970 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
971 EDMA_SetDmaRequestCmd(edmaRegBase, dmaChannel,
false);
1002 DMAMUX_Type *dmaMuxRegBase = s_dmaMuxBase[dmaMuxInstance];
1005 DMAMUX_SetChannelSource(dmaMuxRegBase, dmaMuxChannel, dmaMuxRequest);
1035 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1036 EDMA_TCDClearReg(edmaRegBase, dmaChannel);
1065 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1066 EDMA_TCDSetSrcAddr(edmaRegBase, dmaChannel, address);
1095 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1096 EDMA_TCDSetSrcOffset(edmaRegBase, dmaChannel, offset);
1125 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1126 EDMA_TCDSetSrcTransferSize(edmaRegBase, dmaChannel, size);
1155 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1156 EDMA_TCDSetSrcLastAdjust(edmaRegBase, dmaChannel, adjust);
1185 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1186 EDMA_TCDSetDestLastAdjust(edmaRegBase, dmaChannel, adjust);
1215 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1216 EDMA_TCDSetDestAddr(edmaRegBase, dmaChannel, address);
1245 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1246 EDMA_TCDSetDestOffset(edmaRegBase, dmaChannel, offset);
1275 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1276 EDMA_TCDSetDestTransferSize(edmaRegBase, dmaChannel, size);
1305 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1306 EDMA_TCDSetNbytes(edmaRegBase, dmaChannel, nbytes);
1317 uint32_t majorLoopCount)
1335 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1336 EDMA_TCDSetMajorCount(edmaRegBase, dmaChannel, majorLoopCount);
1364 const DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1365 uint32_t count = EDMA_TCDGetCurrentMajorCount(edmaRegBase, dmaChannel);
1378 uint32_t nextTCDAddr)
1396 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1397 EDMA_TCDSetScatterGatherLink(edmaRegBase, dmaChannel, nextTCDAddr);
1426 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1427 EDMA_TCDSetDisableDmaRequestAfterTCDDoneCmd(edmaRegBase, dmaChannel, disable);
1457 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1462 EDMA_SetErrorIntCmd(edmaRegBase, dmaChannel, enable);
1466 EDMA_TCDSetMajorHalfCompleteIntCmd(edmaRegBase, dmaChannel, enable);
1470 EDMA_TCDSetMajorCompleteIntCmd(edmaRegBase, dmaChannel, enable);
1490 uint32_t dmaInstance = 0U;
1495 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1498 EDMA_CancelTransferWithError(edmaRegBase);
1502 EDMA_CancelTransfer(edmaRegBase);
1532 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1533 EDMA_TriggerChannelStart(edmaRegBase, dmaChannel);
1546 if ((config != NULL) && (stcd != NULL))
1569 #ifdef FEATURE_DMA_HWV3
1608 DMA_Type *edmaRegBase = s_edmaBase[dmaInstance];
1611 EDMA_TCDClearReg(edmaRegBase, dmaChannel);
1613 #ifdef FEATURE_DMA_ENGINE_STALL
1615 EDMA_TCDSetEngineStall(edmaRegBase, dmaChannel, EDMA_ENGINE_STALL_4_CYCLES);
1619 EDMA_TCDSetSrcAddr(edmaRegBase, dmaChannel, tcd->
srcAddr);
1620 EDMA_TCDSetDestAddr(edmaRegBase, dmaChannel, tcd->
destAddr);
1628 EDMA_TCDSetSrcOffset(edmaRegBase, dmaChannel, tcd->
srcOffset);
1629 EDMA_TCDSetDestOffset(edmaRegBase, dmaChannel, tcd->
destOffset);
1633 EDMA_TCDSetScatterGatherCmd(edmaRegBase, dmaChannel,
true);
1638 EDMA_TCDSetScatterGatherCmd(edmaRegBase, dmaChannel,
false);
1643 EDMA_TCDSetMajorCompleteIntCmd(edmaRegBase, dmaChannel, tcd->
interruptEnable);
1666 #ifdef DEV_ERROR_DETECT
1681 #ifdef FEATURE_DMA_TRANSFER_SIZE_8B
1682 case EDMA_TRANSFER_SIZE_8B:
1684 #ifdef FEATURE_DMA_TRANSFER_SIZE_16B
1685 case EDMA_TRANSFER_SIZE_16B:
1687 #ifdef FEATURE_DMA_TRANSFER_SIZE_32B
1688 case EDMA_TRANSFER_SIZE_32B:
1690 #ifdef FEATURE_DMA_TRANSFER_SIZE_64B
1691 case EDMA_TRANSFER_SIZE_64B:
1736 return s_edmaBase[instance];
void EDMA_DRV_PushConfigToSTCD(const edma_transfer_config_t *config, edma_software_tcd_t *stcd)
Copies the channel configuration to the software TCD structure.
void EDMA_DRV_SetMajorLoopIterationCount(uint8_t virtualChannel, uint32_t majorLoopCount)
Configures the number of major loop iterations.
eDMA TCD Implements : edma_software_tcd_t_Class
#define DMA_TCD_ATTR_SSIZE(x)
uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t virtualChannel)
Returns the remaining major loop iteration count.
uint32_t minorByteTransferCount
#define DMAMUX_INSTANCE_COUNT
#define DMA_INSTANCE_COUNT
static const IRQn_Type s_edmaIrqId[FEATURE_DMA_VIRTUAL_CHANNELS_INTERRUPT_LINES]
Array of default DMA channel interrupt handlers.
status_t EDMA_DRV_InstallCallback(uint8_t virtualChannel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
#define FEATURE_DMA_VIRTUAL_CHANNELS_INTERRUPT_LINES
#define FEATURE_DMA_VCH_TO_INSTANCE(x)
uint8_t minorLoopChnLinkNumber
status_t EDMA_DRV_ConfigLoopTransfer(uint8_t virtualChannel, const edma_transfer_config_t *transferConfig)
Configures the DMA transfer in loop mode.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t virtualChannel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
The user configuration structure for the eDMA driver.
edma_transfer_type_t
A type for the DMA transfer. Implements : edma_transfer_type_t_Class.
void EDMA_DRV_SetDestWriteChunkSize(uint8_t virtualChannel, edma_transfer_size_t size)
Configures the destination data chunk size (transferred in a write sequence).
status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t virtualChannel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t dataBufferSize)
Configures a simple single block data transfer with DMA.
void EDMA_DRV_PushConfigToReg(uint8_t virtualChannel, const edma_transfer_config_t *tcd)
Copies the channel configuration to the TCD registers.
static status_t EDMA_DRV_RequestChannel(uint8_t virtualChannel, dma_request_source_t reqSrc, edma_chn_state_t *reqChn)
#define FEATURE_DMA_VIRTUAL_ERROR_INTERRUPT_LINES
The user configuration structure for the an eDMA driver channel.
uint8_t majorLoopChnLinkNumber
status_t EDMA_DRV_Deinit(void)
De-initializes the eDMA module.
void EDMA_DRV_SetScatterGatherLink(uint8_t virtualChannel, uint32_t nextTCDAddr)
Configures the memory address of the next TCD, in scatter/gather mode.
void EDMA_DRV_SetSrcLastAddrAdjustment(uint8_t virtualChannel, int32_t adjust)
Configures the source address last adjustment.
void EDMA_DRV_ConfigureInterrupt(uint8_t virtualChannel, edma_channel_interrupt_t intSrc, bool enable)
Disables/Enables the channel interrupt requests.
void EDMA_DRV_TriggerSwRequest(uint8_t virtualChannel)
Triggers a sw request for the current channel.
void EDMA_DRV_SetDestOffset(uint8_t virtualChannel, int16_t offset)
Configures the destination address signed offset for the eDMA channel.
status_t EDMA_DRV_StopChannel(uint8_t virtualChannel)
Stops the eDMA channel.
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
edma_channel_interrupt_t
eDMA channel interrupts. Implements : edma_channel_interrupt_t_Class
uint32_t scatterGatherNextDescAddr
static DMAMUX_Type *const s_dmaMuxBase[DMAMUX_INSTANCE_COUNT]
Array of base addresses for DMAMUX instances.
#define DMA_TCD_ATTR_DSIZE(x)
#define STCD_ADDR(address)
void EDMA_DRV_DisableRequestsOnTransferComplete(uint8_t virtualChannel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
status_t EDMA_DRV_ChannelInit(edma_chn_state_t *edmaChannelState, const edma_channel_config_t *edmaChannelConfig)
Initializes an eDMA channel.
Runtime state structure for the eDMA driver.
edma_chn_status_t
Channel status for eDMA channel.
edma_chn_status_t EDMA_DRV_GetChannelStatus(uint8_t virtualChannel)
Gets the eDMA channel status.
edma_transfer_size_t destTransferSize
bool majorLoopChnLinkEnable
int32_t srcLastAddrAdjust
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
#define DMA_TCD_CSR_ESG_SHIFT
void EDMA_DRV_SetDestAddr(uint8_t virtualChannel, uint32_t address)
Configures the destination address for the eDMA channel.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
#define DMA_TCD_ATTR_DMOD(x)
edma_arbitration_algorithm_t chnArbitration
uint32_t majorLoopIterationCount
#define FEATURE_DMA_CLOCK_NAMES
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
IRQn_Type
Defines the Interrupt Numbers definitions.
#define FEATURE_DMAMUX_REQ_SRC_TO_CH(x)
#define FEATURE_DMAMUX_CLOCK_NAMES
edma_channel_priority_t channelPriority
status_t EDMA_DRV_ReleaseChannel(uint8_t virtualChannel)
Releases an eDMA channel.
void EDMA_DRV_SetSrcOffset(uint8_t virtualChannel, int16_t offset)
Configures the source address signed offset for the eDMA channel.
edma_transfer_size_t srcTransferSize
Data structure for configuring a discrete memory transfer. Implements : edma_scatter_gather_list_t_Cl...
volatile edma_chn_status_t status
DMA_Type * EDMA_DRV_GetDmaRegBaseAddr(uint32_t instance)
void EDMA_DRV_SetSrcReadChunkSize(uint8_t virtualChannel, edma_transfer_size_t size)
Configures the source data chunk size (transferred in a read sequence).
edma_transfer_type_t type
void EDMA_DRV_SetSrcAddr(uint8_t virtualChannel, uint32_t address)
Configures the source address for the eDMA channel.
status_t EDMA_DRV_ConfigScatterGatherTransfer(uint8_t virtualChannel, edma_software_tcd_t *stcd, edma_transfer_size_t transferSize, uint32_t bytesOnEachRequest, const edma_scatter_gather_list_t *srcList, const edma_scatter_gather_list_t *destList, uint8_t tcdCount)
Configures the DMA transfer in a scatter-gather mode.
void EDMA_DRV_IRQHandler(uint8_t virtualChannel)
DMA channel interrupt handler, implemented in driver c file.
#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x)
void EDMA_DRV_SetMinorLoopBlockSize(uint8_t virtualChannel, uint32_t nbytes)
Configures the number of bytes to be transferred in each service request of the channel.
status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t *userConfig, edma_chn_state_t *const chnStateArray[], const edma_channel_config_t *const chnConfigArray[], uint32_t chnCount)
Initializes the eDMA module.
static void EDMA_DRV_ClearIntStatus(uint8_t virtualChannel)
void EDMA_DRV_ErrorIRQHandler(uint8_t virtualChannel)
status_t EDMA_DRV_StartChannel(uint8_t virtualChannel)
Starts an eDMA channel.
static edma_state_t * s_virtEdmaState
Array of default DMA error interrupt handlers.
int32_t destLastAddrAdjust
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
#define DMA_TCD_CSR_INTMAJOR_SHIFT
status_t EDMA_DRV_SetChannelRequest(uint8_t virtualChannel, uint8_t req)
Configures the DMA request for the eDMA channel.
#define FEATURE_DMA_VIRTUAL_CHANNELS
#define FEATURE_DMA_VCH_TO_CH(x)
void EDMA_DRV_CancelTransfer(bool error)
Cancel the running transfer.
bool minorLoopChnLinkEnable
edma_chn_state_t *volatile virtChnState[(uint32_t)((uint32_t)(4U)*(uint32_t)(1u))]
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
dma_request_source_t source
void EDMA_DRV_SetDestLastAddrAdjustment(uint8_t virtualChannel, int32_t adjust)
Configures the destination address last adjustment.
void EDMA_DRV_ClearTCD(uint8_t virtualChannel)
Clears all registers to 0 for the channel's TCD.
static void EDMA_DRV_ClearSoftwareTCD(edma_software_tcd_t *stcd)
eDMA loop transfer configuration.
#define FEATURE_DMAMUX_DMA_CH_TO_CH(x)
clock_names_t
Clock names.
eDMA transfer size configuration.
edma_loop_transfer_config_t * loopTransferConfig
#define DMA_TCD_ATTR_SMOD(x)
dma_request_source_t
Structure for the DMA hardware request.
static DMA_Type *const s_edmaBase[DMA_INSTANCE_COUNT]
Array of base addresses for DMA instances.
Data structure for the eDMA channel state. Implements : edma_chn_state_t_Class.