The S32 SDK provides Peripheral Driver for the Memory Protection Unit (MPU) module of S32 SDK devices.
The memory protection unit (MPU) provides hardware access control for all memory references generated in the device.
The MPU concurrently monitors all system bus transactions and evaluates their appropriateness using pre-programmed region descriptors that define memory spaces and their access rights. Memory references that have sufficient access control rights are allowed to complete, while references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response.
The MPU implements a two-dimensional hardware array of memory region descriptors and the crossbar slave ports to continuously monitor the legality of every memory reference generated by each bus master in the system.
The feature set includes:
Logical Bus Master Assignments and Possible Access Types
ID | Master | User | Supervisor | Data | Instruction | Read | Write | Execute | PID |
---|---|---|---|---|---|---|---|---|---|
0 | Core | x | x | x | x | x | x | x | x |
1 | Debugger | x | x | x | x | x | x | x | x |
2 | DMA | x | x | x | x | ||||
3 | ENET | x | x | x | x |
ID | S32K1xx | S32MTV |
---|---|---|
0 | x | x |
1 | x | x |
2 | x | x |
3 | x(1) |
1: S32K148 only.
Logical Slave Port Assignments
Port | Source | Destination |
---|---|---|
0 | Crossbar slave port 0 | Flash Controller |
1 | Crossbar slave port 1 | SRAM backdoor |
2 | Code Bus | SRAM_L frontdoor |
3 | System Bus | SRAM_U frontdoor |
4 | Crossbar slave port 3 | QuadSPI |
Port | S32K11x | S32K14x | S32MTV |
---|---|---|---|
0 | x | x | x |
1 | x(1) | x | x |
2 | x | x | |
3 | x | x | |
4 | x(2) |
1: Destination: SRAM controller/MTB/DWT/MCM. 2: S32K148 only.
AHB-AP provides the debugger access to all memory and registers in the system.
The MPU includes default settings and protections for the Region Descriptor 0 (RGD0) such that the Debugger always has access to the entire address space and those rights cannot be changed by the core or any other bus master.
The MPU requires a special programming sequence to protect the QSPI space as it is unable to see the two MSB bits of the QSPI address on slave port 4.
This programming sequence requires 2 Region Descriptors [RGDx]:
Modules | |
MPU Driver | |
Memory Protection Unit Peripheral Driver. | |