99 const isr_t newHandler,
100 isr_t*
const oldHandler)
103 #if (defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT))
106 int32_t dev_irqNumber = (int32_t)irqNumber;
116 if (oldHandler != (
isr_t *) 0)
121 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
123 #if (defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT))
125 DEV_ASSERT((uint32_t)irqNumber < MSCM_IRSPRC_COUNT);
127 uint16_t cpu_enable = (uint16_t)(1UL << (
MSCM->CPXNUM));
128 if ((
MSCM->IRSPRC[irqNumber] & cpu_enable) == 0U)
130 DEV_ASSERT((
MSCM->IRSPRC[irqNumber] & (uint16_t)(MSCM_IRSPRC_RO_MASK)) == (uint16_t)MSCM_IRSPRC_RO(0));
138 __VECTOR_RAM[((int32_t)irqNumber) + 16] = (uint32_t)newHandler;
160 S32_NVIC->ISER[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
162 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
165 uint16_t cpu_enable = (uint16_t)(1UL << (
MSCM->CPXNUM));
166 MSCM->IRSPRC[irqNumber] |= cpu_enable;
188 S32_NVIC->ICER[((uint32_t)(irqNumber) >> 5U)] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
190 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
193 uint16_t cpu_enable = (uint16_t)(1UL << (
MSCM->CPXNUM));
194 MSCM->IRSPRC[irqNumber] &= (uint16_t)~(cpu_enable);
252 #if (defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT))
255 int32_t dev_irqNumber = (int32_t)irqNumber;
263 if ((int32_t)irqNumber < 0)
265 uint32_t intVectorId = ((uint32_t)(irqNumber) & 0xFU);
266 uint32_t regId = intVectorId / 4U;
269 #if defined (S32K11x_SERIES)
272 volatile uint32_t * shpr_reg_ptr = ((regId == 2U) ? (
volatile uint32_t *)&
S32_SCB->SHPR2 : (
volatile uint32_t *)&
S32_SCB->SHPR3);
273 uint8_t priByteShift = ((uint8_t)(intVectorId) & 0x3U) << 3U;
276 *shpr_reg_ptr &= ~(0xFFUL << priByteShift);
279 *shpr_reg_ptr |= ((uint32_t)(((((uint32_t)priority) << shift)) & 0xFFUL)) << priByteShift;
281 volatile uint8_t * shpr_reg_ptr = ((regId == 1U) ? (
volatile uint8_t *)&
S32_SCB->SHPR1 : ((regId == 2U) ? (
volatile uint8_t *)&
S32_SCB->SHPR2 : (
volatile uint8_t *)&
S32_SCB->SHPR3));
284 shpr_reg_ptr[intVectorId % 4U] = (uint8_t)(((((uint32_t)priority) << shift)) & 0xffUL);
290 #if defined (S32K11x_SERIES)
291 uint32_t iprVectorId = (uint32_t)(irqNumber) >> 2U;
292 uint8_t priByteShift = (((uint8_t)(irqNumber)) & 0x3U) << 3U;
295 S32_NVIC->IPR[iprVectorId] &= ~(0xFFUL << priByteShift);
297 S32_NVIC->IPR[iprVectorId] |= ((uint32_t)(((((uint32_t)priority) << shift)) & 0xFFUL)) << priByteShift;
299 S32_NVIC->IP[(uint32_t)(irqNumber)] = (uint8_t)(((((uint32_t)priority) << shift)) & 0xFFUL);
316 #if (defined(DEV_ERROR_DETECT) || defined(CUSTOM_DEVASSERT))
319 int32_t dev_irqNumber = (int32_t)irqNumber;
324 uint8_t priority = 0U;
327 if ((int32_t)irqNumber < 0)
329 uint32_t intVectorId = ((uint32_t)(irqNumber) & 0xFU);
330 uint32_t regId = intVectorId / 4U;
333 #if defined (S32K11x_SERIES)
336 volatile const uint32_t * shpr_reg_ptr = ((regId == 2U) ? (
volatile uint32_t *)&
S32_SCB->SHPR2 : (
volatile uint32_t *)&
S32_SCB->SHPR3);
337 uint8_t priByteShift = ((uint8_t)(intVectorId) & 0x3U) << 3U;
339 priority = ((uint8_t)(*shpr_reg_ptr >> priByteShift)) >> shift;
341 volatile const uint8_t * shpr_reg_ptr = ((regId == 1U) ? (
volatile uint8_t *)&
S32_SCB->SHPR1 : ((regId == 2U) ? (
volatile uint8_t *)&
S32_SCB->SHPR2 : (
volatile uint8_t *)&
S32_SCB->SHPR3));
344 priority = (uint8_t)(shpr_reg_ptr[intVectorId % 4U] >> (shift));
350 #if defined (S32K11x_SERIES)
351 uint32_t iprVectorId = (uint32_t)(irqNumber) >> 2U;
352 uint8_t priByteShift = (((uint8_t)(irqNumber)) & 0x3U) << 3U;
353 priority = ((uint8_t)(
S32_NVIC->IPR[iprVectorId] >> priByteShift)) >> shift;
355 priority = (uint8_t)(
S32_NVIC->IP[(uint32_t)(irqNumber)] >> shift);
362 #if FEATURE_INTERRUPT_HAS_PENDING_STATE
379 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
381 if ((FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber) && (irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX))
384 switch (
MSCM->CPXNUM)
387 MSCM->IRCP0IR |= (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN));
390 MSCM->IRCP1IR |= (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN));
399 S32_NVIC->ICPR[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
418 S32_NVIC->ISPR[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
437 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
440 if ((FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber) && (irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX))
442 return (((((
MSCM->CPXNUM != 0UL) ?
MSCM->IRCP1IR :
MSCM->IRCP0IR) &
443 (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN))) != 0UL) ? 1UL : 0UL);
449 return ((uint32_t)(((
S32_NVIC->ISPR[(((uint32_t)irqNumber) >> 5UL)] & (1UL << (((uint32_t)irqNumber) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
453 #if FEATURE_INTERRUPT_HAS_ACTIVE_STATE
462 uint32_t INT_SYS_GetActive(
IRQn_Type irqNumber)
470 return ((uint32_t)(((
S32_NVIC->IABR[(((uint32_t)irqNumber) >> 5UL)] & (1UL << (((uint32_t)irqNumber) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
474 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
493 void INT_SYS_GenerateDirectedCpuInterrupt(
IRQn_Type irqNumber, interrupt_manager_cpu_targets_t cpu_target)
497 DEV_ASSERT(FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber);
498 DEV_ASSERT(irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX);
500 uint32_t reg_val = MSCM_IRCPGIR_INTID((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN);
504 case INTERRUPT_MANAGER_TARGET_SELF:
505 reg_val |= MSCM_IRCPGIR_TLF(2);
507 case INTERRUPT_MANAGER_TARGET_OTHERS:
508 reg_val |= MSCM_IRCPGIR_TLF(1);
510 case INTERRUPT_MANAGER_TARGET_NONE:
511 case INTERRUPT_MANAGER_TARGET_CP0:
512 case INTERRUPT_MANAGER_TARGET_CP1:
513 case INTERRUPT_MANAGER_TARGET_CP0_CP1:
514 reg_val |= (MSCM_IRCPGIR_TLF(0) | MSCM_IRCPGIR_CPUTL(cpu_target));
522 MSCM->IRCPGIR = reg_val;
uint32_t __VECTOR_RAM[((uint32_t)(FEATURE_INTERRUPT_IRQ_MAX))+16U+1U]
Declaration of vector table. FEATURE_INTERRUPT_IRQ_MAX is the highest interrupt request number...
void INT_SYS_SetPending(IRQn_Type irqNumber)
Set Pending Interrupt.
#define DISABLE_INTERRUPTS()
Disable interrupts.
uint32_t INT_SYS_GetPending(IRQn_Type irqNumber)
Get Pending Interrupt.
#define FEATURE_NVIC_PRIO_BITS
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
void INT_SYS_DisableIRQGlobal(void)
Disable system interrupt.
static int32_t g_interruptDisableCount
Counter to manage the nested callings of global disable/enable interrupt.
IRQn_Type
Defines the Interrupt Numbers definitions.
void INT_SYS_SetPriority(IRQn_Type irqNumber, uint8_t priority)
Set Interrupt Priority.
#define FEATURE_INTERRUPT_IRQ_MAX
void INT_SYS_ClearPending(IRQn_Type irqNumber)
Clear Pending Interrupt.
void INT_SYS_EnableIRQGlobal(void)
Enables system interrupt.
#define ENABLE_INTERRUPTS()
Enable interrupts.
uint8_t INT_SYS_GetPriority(IRQn_Type irqNumber)
Get Interrupt Priority.
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
#define FEATURE_INTERRUPT_IRQ_MIN
void(* isr_t)(void)
Interrupt handler type.
void INT_SYS_InstallHandler(IRQn_Type irqNumber, const isr_t newHandler, isr_t *const oldHandler)
Installs an interrupt handler routine for a given IRQ number.