20 #include "flexio_hw_access.h"
84 #define DIVIDER_MIN_VALUE 1U
85 #define DIVIDER_MAX_VALUE 0xFFU
89 #define TX_SHIFTER(x) (x)
90 #define RX_SHIFTER(x) (uint8_t)((x) + 1U)
91 #define SCK_TIMER(x) (x)
92 #define SS_TIMER(x) (uint8_t)((x) + 1U)
95 #define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU)
107 static void FLEXIO_SPI_DRV_MasterComputeBaudRateDivider(uint32_t baudRate,
114 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 1U;
116 if (tmpDiv < DIVIDER_MIN_VALUE)
118 tmpDiv = DIVIDER_MIN_VALUE;
120 if (tmpDiv > DIVIDER_MAX_VALUE)
122 tmpDiv = DIVIDER_MAX_VALUE;
125 *divider = (uint16_t)tmpDiv;
140 flexio_pin_polarity_t clockPolarity;
141 flexio_timer_polarity_t txShifterPolarity;
142 flexio_timer_polarity_t rxShifterPolarity;
144 flexio_shifter_stop_t stopBit;
145 flexio_shifter_start_t startBit;
146 uint8_t resourceIndex;
149 resourceIndex = master->flexioCommon.resourceIndex;
151 FLEXIO_SPI_DRV_MasterComputeBaudRateDivider(userConfigPtr->
baudRate, ÷r, inputClock);
153 divider += (uint16_t)((((uint16_t)(userConfigPtr->
transferSize) * 8U * 2U) - 1U) << 8U);
158 clockPolarity = FLEXIO_PIN_POLARITY_HIGH;
163 clockPolarity = FLEXIO_PIN_POLARITY_LOW;
169 txShifterPolarity = FLEXIO_TIMER_POLARITY_NEGEDGE;
170 rxShifterPolarity = FLEXIO_TIMER_POLARITY_POSEDGE;
171 stopBit = FLEXIO_SHIFTER_STOP_BIT_DISABLED;
172 startBit = FLEXIO_SHIFTER_START_BIT_DISABLED;
177 txShifterPolarity = FLEXIO_TIMER_POLARITY_POSEDGE;
178 rxShifterPolarity = FLEXIO_TIMER_POLARITY_NEGEDGE;
179 stopBit = FLEXIO_SHIFTER_STOP_BIT_0;
180 startBit = FLEXIO_SHIFTER_START_BIT_DISABLED_SH;
184 FLEXIO_SetShifterControl(baseAddr,
185 TX_SHIFTER(resourceIndex),
186 FLEXIO_SHIFTER_MODE_DISABLED,
188 FLEXIO_PIN_POLARITY_HIGH,
189 FLEXIO_PIN_CONFIG_OUTPUT,
190 SCK_TIMER(resourceIndex),
192 FLEXIO_SetShifterConfig(baseAddr,
193 TX_SHIFTER(resourceIndex),
196 FLEXIO_SHIFTER_SOURCE_PIN);
199 FLEXIO_SetShifterControl(baseAddr,
200 RX_SHIFTER(resourceIndex),
201 FLEXIO_SHIFTER_MODE_DISABLED,
203 FLEXIO_PIN_POLARITY_HIGH,
204 FLEXIO_PIN_CONFIG_DISABLED,
205 SCK_TIMER(resourceIndex),
207 FLEXIO_SetShifterConfig(baseAddr,
208 RX_SHIFTER(resourceIndex),
209 FLEXIO_SHIFTER_START_BIT_DISABLED,
210 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
211 FLEXIO_SHIFTER_SOURCE_PIN);
214 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), divider);
215 FLEXIO_SetTimerConfig(baseAddr,
216 SCK_TIMER(resourceIndex),
217 FLEXIO_TIMER_START_BIT_ENABLED,
218 FLEXIO_TIMER_STOP_BIT_TIM_DIS,
219 FLEXIO_TIMER_ENABLE_TRG_HIGH,
220 FLEXIO_TIMER_DISABLE_TIM_CMP,
221 FLEXIO_TIMER_RESET_NEVER,
222 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
223 FLEXIO_TIMER_INITOUT_ZERO);
224 FLEXIO_SetTimerControl(baseAddr,
225 SCK_TIMER(resourceIndex),
226 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
227 FLEXIO_TRIGGER_POLARITY_LOW,
228 FLEXIO_TRIGGER_SOURCE_INTERNAL,
231 FLEXIO_PIN_CONFIG_OUTPUT,
232 FLEXIO_TIMER_MODE_DISABLED);
235 FLEXIO_SetTimerCompare(baseAddr, SS_TIMER(resourceIndex), 0xFFFFU);
236 FLEXIO_SetTimerConfig(baseAddr,
237 SS_TIMER(resourceIndex),
238 FLEXIO_TIMER_START_BIT_DISABLED,
239 FLEXIO_TIMER_STOP_BIT_DISABLED,
240 FLEXIO_TIMER_ENABLE_TIM_ENABLE,
241 FLEXIO_TIMER_DISABLE_TIM_DISABLE,
242 FLEXIO_TIMER_RESET_NEVER,
243 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
244 FLEXIO_TIMER_INITOUT_ONE);
245 FLEXIO_SetTimerControl(baseAddr,
246 SS_TIMER(resourceIndex),
248 FLEXIO_TRIGGER_POLARITY_HIGH,
249 FLEXIO_TRIGGER_SOURCE_EXTERNAL,
250 userConfigPtr->
ssPin,
251 FLEXIO_PIN_POLARITY_LOW,
252 FLEXIO_PIN_CONFIG_OUTPUT,
253 FLEXIO_TIMER_MODE_DISABLED);
266 uint8_t resourceIndex;
271 resourceIndex = master->flexioCommon.resourceIndex;
274 switch (master->driverType)
278 FLEXIO_SetShifterInterrupt(baseAddr,
279 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
281 FLEXIO_SetShifterErrorInterrupt(baseAddr,
282 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
293 FLEXIO_SetShifterDMARequest(baseAddr,
294 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
302 master->driverIdle =
true;
303 master->txRemainingBytes = 0U;
304 master->rxRemainingBytes = 0U;
307 if (master->blocking ==
true)
323 uint8_t resourceIndex;
325 resourceIndex = master->flexioCommon.resourceIndex;
329 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_TRANSMIT);
330 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_RECEIVE);
333 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_8BIT_BAUD);
334 FLEXIO_SetTimerMode(baseAddr, SS_TIMER(resourceIndex), FLEXIO_TIMER_MODE_16BIT);
338 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_16BIT);
352 uint8_t resourceIndex;
354 resourceIndex = master->flexioCommon.resourceIndex;
358 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
359 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
360 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
361 FLEXIO_SetTimerMode(baseAddr, SS_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
364 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
365 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
367 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
370 FLEXIO_SPI_DRV_MasterEndTransfer(master);
386 switch (master->driverType)
390 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
399 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
407 master->blocking =
false;
412 FLEXIO_SPI_DRV_MasterStopTransfer(master);
415 return master->status;
425 static void FLEXIO_SPI_DRV_MasterEndDmaTransfer(
void *stateStruct,
edma_chn_status_t status)
442 FLEXIO_SPI_DRV_MasterStopTransfer(master);
444 if (master->callback != NULL)
461 flexio_pin_polarity_t clockPolarity;
462 flexio_timer_polarity_t txShifterPolarity;
463 flexio_timer_polarity_t rxShifterPolarity;
464 flexio_shifter_start_t startBit;
465 uint8_t resourceIndex;
468 resourceIndex = slave->flexioCommon.resourceIndex;
473 clockPolarity = FLEXIO_PIN_POLARITY_HIGH;
478 clockPolarity = FLEXIO_PIN_POLARITY_LOW;
484 txShifterPolarity = FLEXIO_TIMER_POLARITY_NEGEDGE;
485 rxShifterPolarity = FLEXIO_TIMER_POLARITY_POSEDGE;
486 startBit = FLEXIO_SHIFTER_START_BIT_DISABLED;
491 txShifterPolarity = FLEXIO_TIMER_POLARITY_POSEDGE;
492 rxShifterPolarity = FLEXIO_TIMER_POLARITY_NEGEDGE;
493 startBit = FLEXIO_SHIFTER_START_BIT_DISABLED_SH;
497 FLEXIO_SetShifterControl(baseAddr,
498 TX_SHIFTER(resourceIndex),
499 FLEXIO_SHIFTER_MODE_DISABLED,
501 FLEXIO_PIN_POLARITY_HIGH,
502 FLEXIO_PIN_CONFIG_OUTPUT,
503 SCK_TIMER(resourceIndex),
505 FLEXIO_SetShifterConfig(baseAddr,
506 TX_SHIFTER(resourceIndex),
508 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
509 FLEXIO_SHIFTER_SOURCE_PIN);
512 FLEXIO_SetShifterControl(baseAddr,
513 RX_SHIFTER(resourceIndex),
514 FLEXIO_SHIFTER_MODE_DISABLED,
516 FLEXIO_PIN_POLARITY_HIGH,
517 FLEXIO_PIN_CONFIG_DISABLED,
518 SCK_TIMER(resourceIndex),
520 FLEXIO_SetShifterConfig(baseAddr,
521 RX_SHIFTER(resourceIndex),
522 FLEXIO_SHIFTER_START_BIT_DISABLED,
523 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
524 FLEXIO_SHIFTER_SOURCE_PIN);
527 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), 0xFFFFU);
528 FLEXIO_SetTimerConfig(baseAddr,
529 SCK_TIMER(resourceIndex),
530 FLEXIO_TIMER_START_BIT_DISABLED,
531 FLEXIO_TIMER_STOP_BIT_DISABLED,
532 FLEXIO_TIMER_ENABLE_TRG_POSEDGE,
533 FLEXIO_TIMER_DISABLE_TRG,
534 FLEXIO_TIMER_RESET_NEVER,
535 FLEXIO_TIMER_DECREMENT_PIN_SHIFT_PIN,
536 FLEXIO_TIMER_INITOUT_ZERO);
537 FLEXIO_SetTimerControl(baseAddr,
538 SCK_TIMER(resourceIndex),
539 (uint8_t)(userConfigPtr->
ssPin << 1U),
540 FLEXIO_TRIGGER_POLARITY_LOW,
541 FLEXIO_TRIGGER_SOURCE_INTERNAL,
544 FLEXIO_PIN_CONFIG_DISABLED,
545 FLEXIO_TIMER_MODE_DISABLED);
559 uint8_t resourceIndex;
562 resourceIndex = master->flexioCommon.resourceIndex;
568 data = FLEXIO_ReadShifterBuffer(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_RW_MODE_NORMAL);
569 data >>= (32U - (8U * (uint32_t)(master->transferSize)));
573 data = FLEXIO_ReadShifterBuffer(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
576 if ((master->rxRemainingBytes > 0U) && (master->rxData != NULL))
578 switch (master->transferSize)
581 *(uint8_t *)master->rxData = (uint8_t)data;
584 *(uint16_t *)master->rxData = (uint16_t)data;
587 *(uint32_t *)master->rxData = (uint32_t)data;
594 master->rxData = &master->rxData[(master->transferSize)];
595 master->rxRemainingBytes -= (uint32_t)(master->transferSize);
613 uint32_t data = FLEXIO_SPI_DUMMYDATA;
614 uint8_t resourceIndex;
617 resourceIndex = master->flexioCommon.resourceIndex;
619 if (master->txRemainingBytes == 0U)
625 if ((master->txRemainingBytes > 0U) && (master->txData != NULL))
628 switch (master->transferSize)
631 data = (uint32_t)(*(
const uint8_t *)master->txData);
634 data = (uint32_t)(*(
const uint16_t *)master->txData);
637 data = (uint32_t)(*(
const uint32_t *)master->txData);
644 master->txData = &master->txData[master->transferSize];
645 master->txRemainingBytes -= (uint32_t)(master->transferSize);
649 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), data, FLEXIO_SHIFTER_RW_MODE_NORMAL);
654 data <<= 32U - (8U * (uint32_t)(master->transferSize));
655 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), data, FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
661 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SPI_DUMMYDATA, FLEXIO_SHIFTER_RW_MODE_NORMAL);
675 static void FLEXIO_SPI_DRV_MasterCheckStatus(
void *stateStruct)
679 uint8_t resourceIndex;
685 resourceIndex = master->flexioCommon.resourceIndex;
688 if (FLEXIO_GetShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex)))
692 FLEXIO_SPI_DRV_MasterStopTransfer(master);
694 if (master->callback != NULL)
700 if (FLEXIO_GetShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex)))
704 FLEXIO_SPI_DRV_MasterStopTransfer(master);
706 if (master->callback != NULL)
713 if (FLEXIO_GetShifterStatus(baseAddr, RX_SHIFTER(resourceIndex)))
715 FLEXIO_SPI_DRV_ReadData(master);
718 if (FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)))
720 FLEXIO_SPI_DRV_WriteData(master);
721 if (master->txRemainingBytes == 0U)
724 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
725 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
730 if ((master->txRemainingBytes == 0U) && (master->rxRemainingBytes == 0U))
738 FLEXIO_SPI_DRV_MasterStopTransfer(master);
740 if (master->callback != NULL)
761 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
764 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter]));
768 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter])) + (
sizeof(uint32_t) - (uint32_t)master->transferSize);
787 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
790 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter])) + (
sizeof(uint32_t) - (uint32_t)master->transferSize);
794 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter]));
808 uint8_t resourceIndex;
817 resourceIndex = master->flexioCommon.resourceIndex;
819 if (master->txData != NULL)
821 addr = (uint32_t)(master->txData);
826 master->dummyDmaData = FLEXIO_SPI_DUMMYDATA;
827 addr = (uint32_t)(&(master->dummyDmaData));
834 FLEXIO_SPI_DRV_MasterComputeTxRegAddr(master),
835 dmaTransferSize[(uint32_t)master->transferSize - 1U],
836 (uint32_t)master->transferSize,
837 master->txRemainingBytes / (uint32_t)master->transferSize,
839 if (master->txData == NULL)
845 if (master->rxData != NULL)
847 addr = (uint32_t)(master->rxData);
852 addr = (uint32_t)(&(master->dummyDmaData));
858 FLEXIO_SPI_DRV_MasterComputeRxRegAddr(master),
860 dmaTransferSize[(uint32_t)master->transferSize - 1U],
861 (uint32_t)master->transferSize,
862 master->rxRemainingBytes / (uint32_t)master->transferSize,
864 if (master->rxData == NULL)
879 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
true);
921 master->flexioCommon.resourceCount = 2U;
936 master->driverType = userConfigPtr->
driverType;
937 master->bitOrder = userConfigPtr->
bitOrder;
939 master->callback = userConfigPtr->
callback;
941 master->blocking =
false;
942 master->driverIdle =
true;
943 master->master =
true;
947 FLEXIO_SPI_DRV_MasterConfigure(master, userConfigPtr, inputClock);
953 master->flexioCommon.isr = FLEXIO_SPI_DRV_MasterCheckStatus;
963 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(master->flexioCommon.resourceIndex)];
964 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(master->flexioCommon.resourceIndex)];
1014 uint32_t inputClock;
1016 uint8_t resourceIndex;
1020 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1021 resourceIndex = master->flexioCommon.resourceIndex;
1031 FLEXIO_SPI_DRV_MasterComputeBaudRateDivider(baudRate, ÷r, inputClock);
1034 timerCmp = FLEXIO_GetTimerCompare(baseAddr, SCK_TIMER(resourceIndex));
1035 timerCmp = (uint16_t)((timerCmp & 0xFF00U) | divider);
1036 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), timerCmp);
1056 uint32_t inputClock;
1058 uint8_t resourceIndex;
1063 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1064 resourceIndex = master->flexioCommon.resourceIndex;
1072 timerCmp = FLEXIO_GetTimerCompare(baseAddr, SCK_TIMER(resourceIndex));
1073 divider = (uint16_t)(timerCmp & 0x00FFU);
1076 *baudRate = (inputClock + divider + 1U) / (2U * ((uint32_t)divider + 1U));
1093 const uint8_t *txData,
1098 uint8_t resourceIndex;
1101 DEV_ASSERT((dataSize % (uint32_t)(master->transferSize)) == 0U);
1102 DEV_ASSERT((txData != NULL) || (rxData != NULL));
1104 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1105 resourceIndex = master->flexioCommon.resourceIndex;
1110 master->txData = txData;
1111 master->rxData = rxData;
1112 master->txRemainingBytes = dataSize;
1113 master->rxRemainingBytes = dataSize;
1114 master->driverIdle =
false;
1118 FLEXIO_SPI_DRV_MasterEnableTransfer(master);
1120 switch (master->driverType)
1124 FLEXIO_SetShifterInterrupt(baseAddr,
1125 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
1127 FLEXIO_SetShifterErrorInterrupt(baseAddr,
1128 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
1133 FLEXIO_SPI_DRV_MasterCheckStatus(master);
1136 FLEXIO_SPI_DRV_MasterStartDmaTransfer(master);
1155 const uint8_t *txData,
1165 master->blocking =
true;
1171 master->blocking =
false;
1176 return FLEXIO_SPI_DRV_MasterWaitTransferEnd(master, timeout);
1192 if (master->driverIdle)
1198 FLEXIO_SPI_DRV_MasterStopTransfer(master);
1213 uint32_t remainingBytes;
1218 remainingBytes = master->rxRemainingBytes;
1220 if (!master->driverIdle)
1222 switch(master->driverType)
1226 FLEXIO_SPI_DRV_MasterCheckStatus(master);
1242 if (bytesRemaining != NULL)
1244 *bytesRemaining = remainingBytes;
1247 return master->status;
1274 slave->flexioCommon.resourceCount = 2U;
1289 slave->driverType = userConfigPtr->
driverType;
1290 slave->bitOrder = userConfigPtr->
bitOrder;
1292 slave->callback = userConfigPtr->
callback;
1294 slave->blocking =
false;
1295 slave->driverIdle =
true;
1296 slave->master =
false;
1300 FLEXIO_SPI_DRV_SlaveConfigure(slave, userConfigPtr);
1306 slave->flexioCommon.isr = FLEXIO_SPI_DRV_MasterCheckStatus;
1316 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(slave->flexioCommon.resourceIndex)];
1317 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(slave->flexioCommon.resourceIndex)];
status_t FLEXIO_SPI_DRV_MasterGetBaudRate(flexio_spi_master_state_t *master, uint32_t *baudRate)
Get the currently configured baud rate.
uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t virtualChannel)
Returns the remaining major loop iteration count.
status_t EDMA_DRV_InstallCallback(uint8_t virtualChannel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
flexio_spi_transfer_size_t transferSize
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
status_t FLEXIO_SPI_DRV_MasterTransferBlocking(flexio_spi_master_state_t *master, const uint8_t *txData, uint8_t *rxData, uint32_t dataSize, uint32_t timeout)
Perform a blocking SPI master transaction.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t virtualChannel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t FLEXIO_SPI_DRV_MasterTransfer(flexio_spi_master_state_t *master, const uint8_t *txData, uint8_t *rxData, uint32_t dataSize)
Perform a non-blocking SPI master transaction.
#define FLEXIO_INSTANCE_COUNT
flexio_spi_transfer_bit_order_t bitOrder
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
void EDMA_DRV_SetDestOffset(uint8_t virtualChannel, int16_t offset)
Configures the destination address signed offset for the eDMA channel.
status_t EDMA_DRV_StopChannel(uint8_t virtualChannel)
Stops the eDMA channel.
status_t FLEXIO_SPI_DRV_MasterGetStatus(flexio_spi_master_state_t *master, uint32_t *bytesRemaining)
Get the status of the current non-blocking SPI master transaction.
Slave configuration structure.
flexio_driver_type_t driverType
edma_chn_status_t
Channel status for eDMA channel.
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
volatile uint32_t SHIFTBUFBIS[4u]
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
const clock_names_t g_flexioClock[(1u)]
flexio_spi_transfer_size_t transferSize
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
FLEXIO_Type *const g_flexioBase[(1u)]
Master configuration structure.
status_t FLEXIO_SPI_DRV_MasterSetBaudRate(flexio_spi_master_state_t *master, uint32_t baudRate)
Set the baud rate for any subsequent SPI communication.
void EDMA_DRV_SetSrcOffset(uint8_t virtualChannel, int16_t offset)
Configures the source address signed offset for the eDMA channel.
volatile uint32_t SHIFTBUF[4u]
status_t FLEXIO_SPI_DRV_SlaveInit(uint32_t instance, const flexio_spi_slave_user_config_t *userConfigPtr, flexio_spi_slave_state_t *slave)
Initialize the FLEXIO_SPI slave mode driver.
const uint8_t g_flexioDMASrc[(1u)][(4U)]
flexio_spi_transfer_bit_order_t bitOrder
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
flexio_device_state_t * g_flexioDeviceStatePtr[(1u)]
status_t FLEXIO_SPI_DRV_MasterInit(uint32_t instance, const flexio_spi_master_user_config_t *userConfigPtr, flexio_spi_master_state_t *master)
Initialize the FLEXIO_SPI master mode driver.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
status_t EDMA_DRV_StartChannel(uint8_t virtualChannel)
Starts an eDMA channel.
status_t FLEXIO_SPI_DRV_MasterDeinit(flexio_spi_master_state_t *master)
De-initialize the FLEXIO_SPI master mode driver.
status_t EDMA_DRV_SetChannelRequest(uint8_t virtualChannel, uint8_t req)
Configures the DMA request for the eDMA channel.
status_t FLEXIO_SPI_DRV_MasterTransferAbort(flexio_spi_master_state_t *master)
Aborts a non-blocking SPI master transaction.
Master internal context structure.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
flexio_driver_type_t driverType