ic_irq.c
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1 /*
2  * Copyright 2018 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
28 #include "ic_irq.h"
29 
30 /*******************************************************************************
31  * Code
32  ******************************************************************************/
33 
34 #if (defined(IC_PAL_OVER_EMIOS))
35 
36 #if (IC_PAL_INSTANCE_MAX > 0U)
37 /* The interrupt function for channel 0, 1 on EMIOS0 */
38 void EMIOS0_00_01_IRQHandler(void)
39 {
40  /* Check the FLAG bit is set or not */
41  if (EMIOS_DRV_ReadFlagState(0U, 0U) == true)
42  {
43  IC_IrqHandler(0U, 0U);
44  }
45 
46  /* Check the FLAG bit is set or not */
47  if (EMIOS_DRV_ReadFlagState(0U, 1U) == true)
48  {
49  IC_IrqHandler(0U, 1U);
50  }
51 }
52 
53 /* The interrupt function for channel 2, 3 on EMIOS0 */
54 void EMIOS0_02_03_IRQHandler(void)
55 {
56  /* Check the FLAG bit is set or not */
57  if (EMIOS_DRV_ReadFlagState(0U, 2U) == true)
58  {
59  IC_IrqHandler(0U, 2U);
60  }
61 
62  /* Check the FLAG bit is set or not */
63  if (EMIOS_DRV_ReadFlagState(0U, 3U) == true)
64  {
65  IC_IrqHandler(0U, 3U);
66  }
67 }
68 
69 /* The interrupt function for channel 4, 5 on EMIOS0 */
70 void EMIOS0_04_05_IRQHandler(void)
71 {
72  /* Check the FLAG bit is set or not */
73  if (EMIOS_DRV_ReadFlagState(0U, 4U) == true)
74  {
75  IC_IrqHandler(0U, 4U);
76  }
77 
78  /* Check the FLAG bit is set or not */
79  if (EMIOS_DRV_ReadFlagState(0U, 5U) == true)
80  {
81  IC_IrqHandler(0U, 5U);
82  }
83 }
84 
85 /* The interrupt function for channel 6, 7 on EMIOS0 */
86 void EMIOS0_06_07_IRQHandler(void)
87 {
88  /* Check the FLAG bit is set or not */
89  if (EMIOS_DRV_ReadFlagState(0U, 6U) == true)
90  {
91  IC_IrqHandler(0U, 6U);
92  }
93 
94  /* Check the FLAG bit is set or not */
95  if (EMIOS_DRV_ReadFlagState(0U, 7U) == true)
96  {
97  IC_IrqHandler(0U, 7U);
98  }
99 }
100 
101 /* The interrupt function for channel 8, 9 on EMIOS0 */
102 void EMIOS0_08_09_IRQHandler(void)
103 {
104  /* Check the FLAG bit is set or not */
105  if (EMIOS_DRV_ReadFlagState(0U, 8U) == true)
106  {
107  IC_IrqHandler(0U, 8U);
108  }
109 
110  /* Check the FLAG bit is set or not */
111  if (EMIOS_DRV_ReadFlagState(0U, 9U) == true)
112  {
113  IC_IrqHandler(0U, 9U);
114  }
115 }
116 
117 /* The interrupt function for channel 10, 11 on EMIOS0 */
118 void EMIOS0_10_11_IRQHandler(void)
119 {
120  /* Check the FLAG bit is set or not */
121  if (EMIOS_DRV_ReadFlagState(0U, 10U) == true)
122  {
123  IC_IrqHandler(0U, 10U);
124  }
125 
126  /* Check the FLAG bit is set or not */
127  if (EMIOS_DRV_ReadFlagState(0U, 11U) == true)
128  {
129  IC_IrqHandler(0U, 11U);
130  }
131 }
132 
133 /* The interrupt function for channel 12, 13 on EMIOS0 */
134 void EMIOS0_12_13_IRQHandler(void)
135 {
136  /* Check the FLAG bit is set or not */
137  if (EMIOS_DRV_ReadFlagState(0U, 12U) == true)
138  {
139  IC_IrqHandler(0U, 12U);
140  }
141 
142  /* Check the FLAG bit is set or not */
143  if (EMIOS_DRV_ReadFlagState(0U, 13U) == true)
144  {
145  IC_IrqHandler(0U, 13U);
146  }
147 }
148 
149 /* The interrupt function for channel 14, 15 on EMIOS0 */
150 void EMIOS0_14_15_IRQHandler(void)
151 {
152  /* Check the FLAG bit is set or not */
153  if (EMIOS_DRV_ReadFlagState(0U, 14U) == true)
154  {
155  IC_IrqHandler(0U, 14U);
156  }
157 
158  /* Check the FLAG bit is set or not */
159  if (EMIOS_DRV_ReadFlagState(0U, 15U) == true)
160  {
161  IC_IrqHandler(0U, 15U);
162  }
163 }
164 
165 /* The interrupt function for channel 16, 17 on EMIOS0 */
166 void EMIOS0_16_17_IRQHandler(void)
167 {
168  /* Check the FLAG bit is set or not */
169  if (EMIOS_DRV_ReadFlagState(0U, 16U) == true)
170  {
171  IC_IrqHandler(0U, 16U);
172  }
173 
174  /* Check the FLAG bit is set or not */
175  if (EMIOS_DRV_ReadFlagState(0U, 17U) == true)
176  {
177  IC_IrqHandler(0U, 17U);
178  }
179 }
180 
181 /* The interrupt function for channel 18, 19 on EMIOS0 */
182 void EMIOS0_18_19_IRQHandler(void)
183 {
184  /* Check the FLAG bit is set or not */
185  if (EMIOS_DRV_ReadFlagState(0U, 18U) == true)
186  {
187  IC_IrqHandler(0U, 18U);
188  }
189 
190  /* Check the FLAG bit is set or not */
191  if (EMIOS_DRV_ReadFlagState(0U, 19U) == true)
192  {
193  IC_IrqHandler(0U, 19U);
194  }
195 }
196 
197 /* The interrupt function for channel 20, 21 on EMIOS0 */
198 void EMIOS0_20_21_IRQHandler(void)
199 {
200  /* Check the FLAG bit is set or not */
201  if (EMIOS_DRV_ReadFlagState(0U, 20U) == true)
202  {
203  IC_IrqHandler(0U, 20U);
204  }
205 
206  /* Check the FLAG bit is set or not */
207  if (EMIOS_DRV_ReadFlagState(0U, 21U) == true)
208  {
209  IC_IrqHandler(0U, 21U);
210  }
211 }
212 
213 /* The interrupt function for channel 22, 23 on EMIOS0 */
214 void EMIOS0_22_23_IRQHandler(void)
215 {
216  /* Check the FLAG bit is set or not */
217  if (EMIOS_DRV_ReadFlagState(0U, 22U) == true)
218  {
219  IC_IrqHandler(0U, 22U);
220  }
221 
222  /* Check the FLAG bit is set or not */
223  if (EMIOS_DRV_ReadFlagState(0U, 23U) == true)
224  {
225  IC_IrqHandler(0U, 23U);
226  }
227 }
228 
229 /* The interrupt function for channel 24, 25 on EMIOS0 */
230 void EMIOS0_24_25_IRQHandler(void)
231 {
232  /* Check the FLAG bit is set or not */
233  if (EMIOS_DRV_ReadFlagState(0U, 24U) == true)
234  {
235  IC_IrqHandler(0U, 24U);
236  }
237 
238  /* Check the FLAG bit is set or not */
239  if (EMIOS_DRV_ReadFlagState(0U, 25U) == true)
240  {
241  IC_IrqHandler(0U, 25U);
242  }
243 }
244 
245 /* The interrupt function for channel 26, 27 on EMIOS0 */
246 void EMIOS0_26_27_IRQHandler(void)
247 {
248  /* Check the FLAG bit is set or not */
249  if (EMIOS_DRV_ReadFlagState(0U, 26U) == true)
250  {
251  IC_IrqHandler(0U, 26U);
252  }
253 
254  /* Check the FLAG bit is set or not */
255  if (EMIOS_DRV_ReadFlagState(0U, 27U) == true)
256  {
257  IC_IrqHandler(0U, 27U);
258  }
259 }
260 
261 /* The interrupt function for channel 28, 29 on EMIOS0 */
262 void EMIOS0_28_29_IRQHandler(void)
263 {
264  /* Check the FLAG bit is set or not */
265  if (EMIOS_DRV_ReadFlagState(0U, 28U) == true)
266  {
267  IC_IrqHandler(0U, 28U);
268  }
269 
270  /* Check the FLAG bit is set or not */
271  if (EMIOS_DRV_ReadFlagState(0U, 29U) == true)
272  {
273  IC_IrqHandler(0U, 29U);
274  }
275 }
276 
277 /* The interrupt function for channel 30, 31 on EMIOS0 */
278 void EMIOS0_30_31_IRQHandler(void)
279 {
280  /* Check the FLAG bit is set or not */
281  if (EMIOS_DRV_ReadFlagState(0U, 30U) == true)
282  {
283  IC_IrqHandler(0U, 30U);
284  }
285 
286  /* Check the FLAG bit is set or not */
287  if (EMIOS_DRV_ReadFlagState(0U, 31U) == true)
288  {
289  IC_IrqHandler(0U, 31U);
290  }
291 }
292 #endif /* End of (IC_PAL_INSTANCE_MAX > 0U) */
293 
294 #if (IC_PAL_INSTANCE_MAX > 1U)
295 /* The interrupt function for channel 0, 1 on EMIOS1 */
296 void EMIOS1_00_01_IRQHandler(void)
297 {
298  /* Check the FLAG bit is set or not */
299  if (EMIOS_DRV_ReadFlagState(1U, 0U) == true)
300  {
301  IC_IrqHandler(1U, 0U);
302  }
303 
304  /* Check the FLAG bit is set or not */
305  if (EMIOS_DRV_ReadFlagState(1U, 1U) == true)
306  {
307  IC_IrqHandler(1U, 1U);
308  }
309 }
310 
311 /* The interrupt function for channel 2, 3 on EMIOS1 */
312 void EMIOS1_02_03_IRQHandler(void)
313 {
314  /* Check the FLAG bit is set or not */
315  if (EMIOS_DRV_ReadFlagState(1U, 2U) == true)
316  {
317  IC_IrqHandler(1U, 2U);
318  }
319 
320  /* Check the FLAG bit is set or not */
321  if (EMIOS_DRV_ReadFlagState(1U, 3U) == true)
322  {
323  IC_IrqHandler(1U, 3U);
324  }
325 }
326 
327 /* The interrupt function for channel 4, 5 on EMIOS1 */
328 void EMIOS1_04_05_IRQHandler(void)
329 {
330  /* Check the FLAG bit is set or not */
331  if (EMIOS_DRV_ReadFlagState(1U, 4U) == true)
332  {
333  IC_IrqHandler(1U, 4U);
334  }
335 
336  /* Check the FLAG bit is set or not */
337  if (EMIOS_DRV_ReadFlagState(1U, 5U) == true)
338  {
339  IC_IrqHandler(1U, 5U);
340  }
341 }
342 
343 /* The interrupt function for channel 6, 7 on EMIOS1 */
344 void EMIOS1_06_07_IRQHandler(void)
345 {
346  /* Check the FLAG bit is set or not */
347  if (EMIOS_DRV_ReadFlagState(1U, 6U) == true)
348  {
349  IC_IrqHandler(1U, 6U);
350  }
351 
352  /* Check the FLAG bit is set or not */
353  if (EMIOS_DRV_ReadFlagState(1U, 7U) == true)
354  {
355  IC_IrqHandler(1U, 7U);
356  }
357 }
358 
359 /* The interrupt function for channel 8, 9 on EMIOS1 */
360 void EMIOS1_08_09_IRQHandler(void)
361 {
362  /* Check the FLAG bit is set or not */
363  if (EMIOS_DRV_ReadFlagState(1U, 8U) == true)
364  {
365  IC_IrqHandler(1U, 8U);
366  }
367 
368  /* Check the FLAG bit is set or not */
369  if (EMIOS_DRV_ReadFlagState(1U, 9U) == true)
370  {
371  IC_IrqHandler(1U, 9U);
372  }
373 }
374 
375 /* The interrupt function for channel 10, 11 on EMIOS1 */
376 void EMIOS1_10_11_IRQHandler(void)
377 {
378  /* Check the FLAG bit is set or not */
379  if (EMIOS_DRV_ReadFlagState(1U, 10U) == true)
380  {
381  IC_IrqHandler(1U, 10U);
382  }
383 
384  /* Check the FLAG bit is set or not */
385  if (EMIOS_DRV_ReadFlagState(1U, 11U) == true)
386  {
387  IC_IrqHandler(1U, 11U);
388  }
389 }
390 
391 /* The interrupt function for channel 12, 13 on EMIOS1 */
392 void EMIOS1_12_13_IRQHandler(void)
393 {
394  /* Check the FLAG bit is set or not */
395  if (EMIOS_DRV_ReadFlagState(1U, 12U) == true)
396  {
397  IC_IrqHandler(1U, 12U);
398  }
399 
400  /* Check the FLAG bit is set or not */
401  if (EMIOS_DRV_ReadFlagState(1U, 13U) == true)
402  {
403  IC_IrqHandler(1U, 13U);
404  }
405 }
406 
407 /* The interrupt function for channel 14, 15 on EMIOS1 */
408 void EMIOS1_14_15_IRQHandler(void)
409 {
410  /* Check the FLAG bit is set or not */
411  if (EMIOS_DRV_ReadFlagState(1U, 14U) == true)
412  {
413  IC_IrqHandler(1U, 14U);
414  }
415 
416  /* Check the FLAG bit is set or not */
417  if (EMIOS_DRV_ReadFlagState(1U, 15U) == true)
418  {
419  IC_IrqHandler(1U, 15U);
420  }
421 }
422 
423 /* The interrupt function for channel 16, 17 on EMIOS1 */
424 void EMIOS1_16_17_IRQHandler(void)
425 {
426  /* Check the FLAG bit is set or not */
427  if (EMIOS_DRV_ReadFlagState(1U, 16U) == true)
428  {
429  IC_IrqHandler(1U, 16U);
430  }
431 
432  /* Check the FLAG bit is set or not */
433  if (EMIOS_DRV_ReadFlagState(1U, 17U) == true)
434  {
435  IC_IrqHandler(1U, 17U);
436  }
437 }
438 
439 /* The interrupt function for channel 18, 19 on EMIOS1 */
440 void EMIOS1_18_19_IRQHandler(void)
441 {
442  /* Check the FLAG bit is set or not */
443  if (EMIOS_DRV_ReadFlagState(1U, 18U) == true)
444  {
445  IC_IrqHandler(1U, 18U);
446  }
447 
448  /* Check the FLAG bit is set or not */
449  if (EMIOS_DRV_ReadFlagState(1U, 19U) == true)
450  {
451  IC_IrqHandler(1U, 19U);
452  }
453 }
454 
455 /* The interrupt function for channel 20, 21 on EMIOS1 */
456 void EMIOS1_20_21_IRQHandler(void)
457 {
458  /* Check the FLAG bit is set or not */
459  if (EMIOS_DRV_ReadFlagState(1U, 20U) == true)
460  {
461  IC_IrqHandler(1U, 20U);
462  }
463 
464  /* Check the FLAG bit is set or not */
465  if (EMIOS_DRV_ReadFlagState(1U, 21U) == true)
466  {
467  IC_IrqHandler(1U, 21U);
468  }
469 }
470 
471 /* The interrupt function for channel 22, 23 on EMIOS1 */
472 void EMIOS1_22_23_IRQHandler(void)
473 {
474  /* Check the FLAG bit is set or not */
475  if (EMIOS_DRV_ReadFlagState(1U, 22U) == true)
476  {
477  IC_IrqHandler(1U, 22U);
478  }
479 
480  /* Check the FLAG bit is set or not */
481  if (EMIOS_DRV_ReadFlagState(1U, 23U) == true)
482  {
483  IC_IrqHandler(1U, 23U);
484  }
485 }
486 
487 /* The interrupt function for channel 24, 25 on EMIOS1 */
488 void EMIOS1_24_25_IRQHandler(void)
489 {
490  /* Check the FLAG bit is set or not */
491  if (EMIOS_DRV_ReadFlagState(1U, 24U) == true)
492  {
493  IC_IrqHandler(1U, 24U);
494  }
495 
496  /* Check the FLAG bit is set or not */
497  if (EMIOS_DRV_ReadFlagState(1U, 25U) == true)
498  {
499  IC_IrqHandler(1U, 25U);
500  }
501 }
502 
503 /* The interrupt function for channel 26, 27 on EMIOS1 */
504 void EMIOS1_26_27_IRQHandler(void)
505 {
506  /* Check the FLAG bit is set or not */
507  if (EMIOS_DRV_ReadFlagState(1U, 26U) == true)
508  {
509  IC_IrqHandler(1U, 26U);
510  }
511 
512  /* Check the FLAG bit is set or not */
513  if (EMIOS_DRV_ReadFlagState(1U, 27U) == true)
514  {
515  IC_IrqHandler(1U, 27U);
516  }
517 }
518 
519 /* The interrupt function for channel 28, 29 on EMIOS1 */
520 void EMIOS1_28_29_IRQHandler(void)
521 {
522  /* Check the FLAG bit is set or not */
523  if (EMIOS_DRV_ReadFlagState(1U, 28U) == true)
524  {
525  IC_IrqHandler(1U, 28U);
526  }
527 
528  /* Check the FLAG bit is set or not */
529  if (EMIOS_DRV_ReadFlagState(1U, 29U) == true)
530  {
531  IC_IrqHandler(1U, 29U);
532  }
533 }
534 
535 /* The interrupt function for channel 30, 31 on EMIOS1 */
536 void EMIOS1_30_31_IRQHandler(void)
537 {
538  /* Check the FLAG bit is set or not */
539  if (EMIOS_DRV_ReadFlagState(1U, 30U) == true)
540  {
541  IC_IrqHandler(1U, 30U);
542  }
543 
544  /* Check the FLAG bit is set or not */
545  if (EMIOS_DRV_ReadFlagState(1U, 31U) == true)
546  {
547  IC_IrqHandler(1U, 31U);
548  }
549 }
550 #endif /* End of (IC_PAL_INSTANCE_MAX > 1U) */
551 
552 #if (IC_PAL_INSTANCE_MAX > 2U)
553 /* The interrupt function for channel 0, 1 on EMIOS2 */
554 void EMIOS2_00_01_IRQHandler(void)
555 {
556  /* Check the FLAG bit is set or not */
557  if (EMIOS_DRV_ReadFlagState(2U, 0U) == true)
558  {
559  IC_IrqHandler(2U, 0U);
560  }
561 
562  /* Check the FLAG bit is set or not */
563  if (EMIOS_DRV_ReadFlagState(2U, 1U) == true)
564  {
565  IC_IrqHandler(2U, 1U);
566  }
567 }
568 
569 /* The interrupt function for channel 2, 3 on EMIOS2 */
570 void EMIOS2_02_03_IRQHandler(void)
571 {
572  /* Check the FLAG bit is set or not */
573  if (EMIOS_DRV_ReadFlagState(2U, 2U) == true)
574  {
575  IC_IrqHandler(2U, 2U);
576  }
577 
578  /* Check the FLAG bit is set or not */
579  if (EMIOS_DRV_ReadFlagState(2U, 3U) == true)
580  {
581  IC_IrqHandler(2U, 3U);
582  }
583 }
584 
585 /* The interrupt function for channel 4, 5 on EMIOS2 */
586 void EMIOS2_04_05_IRQHandler(void)
587 {
588  /* Check the FLAG bit is set or not */
589  if (EMIOS_DRV_ReadFlagState(2U, 4U) == true)
590  {
591  IC_IrqHandler(2U, 4U);
592  }
593 
594  /* Check the FLAG bit is set or not */
595  if (EMIOS_DRV_ReadFlagState(2U, 5U) == true)
596  {
597  IC_IrqHandler(2U, 5U);
598  }
599 }
600 
601 /* The interrupt function for channel 6, 7 on EMIOS2 */
602 void EMIOS2_06_07_IRQHandler(void)
603 {
604  /* Check the FLAG bit is set or not */
605  if (EMIOS_DRV_ReadFlagState(2U, 6U) == true)
606  {
607  IC_IrqHandler(2U, 6U);
608  }
609 
610  /* Check the FLAG bit is set or not */
611  if (EMIOS_DRV_ReadFlagState(2U, 7U) == true)
612  {
613  IC_IrqHandler(2U, 7U);
614  }
615 }
616 
617 /* The interrupt function for channel 8, 9 on EMIOS2 */
618 void EMIOS2_08_09_IRQHandler(void)
619 {
620  /* Check the FLAG bit is set or not */
621  if (EMIOS_DRV_ReadFlagState(2U, 8U) == true)
622  {
623  IC_IrqHandler(2U, 8U);
624  }
625 
626  /* Check the FLAG bit is set or not */
627  if (EMIOS_DRV_ReadFlagState(2U, 9U) == true)
628  {
629  IC_IrqHandler(2U, 9U);
630  }
631 }
632 
633 /* The interrupt function for channel 10, 11 on EMIOS2 */
634 void EMIOS2_10_11_IRQHandler(void)
635 {
636  /* Check the FLAG bit is set or not */
637  if (EMIOS_DRV_ReadFlagState(2U, 10U) == true)
638  {
639  IC_IrqHandler(2U, 10U);
640  }
641 
642  /* Check the FLAG bit is set or not */
643  if (EMIOS_DRV_ReadFlagState(2U, 11U) == true)
644  {
645  IC_IrqHandler(2U, 11U);
646  }
647 }
648 
649 /* The interrupt function for channel 12, 13 on EMIOS2 */
650 void EMIOS2_12_13_IRQHandler(void)
651 {
652  /* Check the FLAG bit is set or not */
653  if (EMIOS_DRV_ReadFlagState(2U, 12U) == true)
654  {
655  IC_IrqHandler(2U, 12U);
656  }
657 
658  /* Check the FLAG bit is set or not */
659  if (EMIOS_DRV_ReadFlagState(2U, 13U) == true)
660  {
661  IC_IrqHandler(2U, 13U);
662  }
663 }
664 
665 /* The interrupt function for channel 14, 15 on EMIOS2 */
666 void EMIOS2_14_15_IRQHandler(void)
667 {
668  /* Check the FLAG bit is set or not */
669  if (EMIOS_DRV_ReadFlagState(2U, 14U) == true)
670  {
671  IC_IrqHandler(2U, 14U);
672  }
673 
674  /* Check the FLAG bit is set or not */
675  if (EMIOS_DRV_ReadFlagState(2U, 15U) == true)
676  {
677  IC_IrqHandler(2U, 15U);
678  }
679 }
680 
681 /* The interrupt function for channel 16, 17 on EMIOS2 */
682 void EMIOS2_16_17_IRQHandler(void)
683 {
684  /* Check the FLAG bit is set or not */
685  if (EMIOS_DRV_ReadFlagState(2U, 16U) == true)
686  {
687  IC_IrqHandler(2U, 16U);
688  }
689 
690  /* Check the FLAG bit is set or not */
691  if (EMIOS_DRV_ReadFlagState(2U, 17U) == true)
692  {
693  IC_IrqHandler(2U, 17U);
694  }
695 }
696 
697 /* The interrupt function for channel 18, 19 on EMIOS2 */
698 void EMIOS2_18_19_IRQHandler(void)
699 {
700  /* Check the FLAG bit is set or not */
701  if (EMIOS_DRV_ReadFlagState(2U, 18U) == true)
702  {
703  IC_IrqHandler(2U, 18U);
704  }
705 
706  /* Check the FLAG bit is set or not */
707  if (EMIOS_DRV_ReadFlagState(2U, 19U) == true)
708  {
709  IC_IrqHandler(2U, 19U);
710  }
711 }
712 
713 /* The interrupt function for channel 20, 21 on EMIOS2 */
714 void EMIOS2_20_21_IRQHandler(void)
715 {
716  /* Check the FLAG bit is set or not */
717  if (EMIOS_DRV_ReadFlagState(2U, 20U) == true)
718  {
719  IC_IrqHandler(2U, 20U);
720  }
721 
722  /* Check the FLAG bit is set or not */
723  if (EMIOS_DRV_ReadFlagState(2U, 21U) == true)
724  {
725  IC_IrqHandler(2U, 21U);
726  }
727 }
728 
729 /* The interrupt function for channel 22, 23 on EMIOS2 */
730 void EMIOS2_22_23_IRQHandler(void)
731 {
732  /* Check the FLAG bit is set or not */
733  if (EMIOS_DRV_ReadFlagState(2U, 22U) == true)
734  {
735  IC_IrqHandler(2U, 22U);
736  }
737 
738  /* Check the FLAG bit is set or not */
739  if (EMIOS_DRV_ReadFlagState(2U, 23U) == true)
740  {
741  IC_IrqHandler(2U, 23U);
742  }
743 }
744 
745 /* The interrupt function for channel 24, 25 on EMIOS2 */
746 void EMIOS2_24_25_IRQHandler(void)
747 {
748  /* Check the FLAG bit is set or not */
749  if (EMIOS_DRV_ReadFlagState(2U, 24U) == true)
750  {
751  IC_IrqHandler(2U, 24U);
752  }
753 
754  /* Check the FLAG bit is set or not */
755  if (EMIOS_DRV_ReadFlagState(2U, 25U) == true)
756  {
757  IC_IrqHandler(2U, 25U);
758  }
759 }
760 
761 /* The interrupt function for channel 26, 27 on EMIOS2 */
762 void EMIOS2_26_27_IRQHandler(void)
763 {
764  /* Check the FLAG bit is set or not */
765  if (EMIOS_DRV_ReadFlagState(2U, 26U) == true)
766  {
767  IC_IrqHandler(2U, 26U);
768  }
769 
770  /* Check the FLAG bit is set or not */
771  if (EMIOS_DRV_ReadFlagState(2U, 27U) == true)
772  {
773  IC_IrqHandler(2U, 27U);
774  }
775 }
776 
777 /* The interrupt function for channel 28, 29 on EMIOS2 */
778 void EMIOS2_28_29_IRQHandler(void)
779 {
780  /* Check the FLAG bit is set or not */
781  if (EMIOS_DRV_ReadFlagState(2U, 28U) == true)
782  {
783  IC_IrqHandler(2U, 28U);
784  }
785 
786  /* Check the FLAG bit is set or not */
787  if (EMIOS_DRV_ReadFlagState(2U, 29U) == true)
788  {
789  IC_IrqHandler(2U, 29U);
790  }
791 }
792 
793 /* The interrupt function for channel 30, 31 on EMIOS2 */
794 void EMIOS2_30_31_IRQHandler(void)
795 {
796  /* Check the FLAG bit is set or not */
797  if (EMIOS_DRV_ReadFlagState(2U, 30U) == true)
798  {
799  IC_IrqHandler(2U, 30U);
800  }
801 
802  /* Check the FLAG bit is set or not */
803  if (EMIOS_DRV_ReadFlagState(2U, 31U) == true)
804  {
805  IC_IrqHandler(2U, 31U);
806  }
807 }
808 #endif /* End of (IC_PAL_INSTANCE_MAX > 2U) */
809 
810 #endif /* End of defined(IC_PAL_OVER_EMIOS) */
811 
812 
813 #if (defined(IC_PAL_OVER_ETIMER))
814 #if (IC_PAL_INSTANCE_MAX > 0U)
815 void ETIMER0_TC0IR_IRQHandler(void)
816 {
817  IC_IrqHandler(0U, 0U);
818 }
819 
820 void ETIMER0_TC1IR_IRQHandler(void)
821 {
822  IC_IrqHandler(0U, 1U);
823 }
824 
825 void ETIMER0_TC2IR_IRQHandler(void)
826 {
827  IC_IrqHandler(0U, 2U);
828 }
829 
830 void ETIMER0_TC3IR_IRQHandler(void)
831 {
832  IC_IrqHandler(0U, 3U);
833 }
834 
835 void ETIMER0_TC4IR_IRQHandler(void)
836 {
837  IC_IrqHandler(0U, 4U);
838 }
839 
840 void ETIMER0_TC5IR_IRQHandler(void)
841 {
842  IC_IrqHandler(0U, 5U);
843 }
844 #endif
845 
846 #if (IC_PAL_INSTANCE_MAX > 1U)
847 void ETIMER1_TC0IR_IRQHandler(void)
848 {
849  IC_IrqHandler(1U, 0U);
850 }
851 
852 void ETIMER1_TC1IR_IRQHandler(void)
853 {
854  IC_IrqHandler(1U, 1U);
855 }
856 
857 void ETIMER1_TC2IR_IRQHandler(void)
858 {
859  IC_IrqHandler(1U, 2U);
860 }
861 
862 void ETIMER1_TC3IR_IRQHandler(void)
863 {
864  IC_IrqHandler(1U, 3U);
865 }
866 
867 void ETIMER1_TC4IR_IRQHandler(void)
868 {
869  IC_IrqHandler(1U, 4U);
870 }
871 
872 void ETIMER1_TC5IR_IRQHandler(void)
873 {
874  IC_IrqHandler(1U, 5U);
875 }
876 #endif
877 
878 #if (IC_PAL_INSTANCE_MAX > 2U)
879 void ETIMER2_TC0IR_IRQHandler(void)
880 {
881  IC_IrqHandler(2U, 0U);
882 }
883 
884 void ETIMER2_TC1IR_IRQHandler(void)
885 {
886  IC_IrqHandler(2U, 1U);
887 }
888 
889 void ETIMER2_TC2IR_IRQHandler(void)
890 {
891  IC_IrqHandler(2U, 2U);
892 }
893 
894 void ETIMER2_TC3IR_IRQHandler(void)
895 {
896  IC_IrqHandler(2U, 3U);
897 }
898 
899 void ETIMER2_TC4IR_IRQHandler(void)
900 {
901  IC_IrqHandler(2U, 4U);
902 }
903 
904 void ETIMER2_TC5IR_IRQHandler(void)
905 {
906  IC_IrqHandler(2U, 5U);
907 }
908 #endif
909 #endif /* defined(IC_PAL_OVER_ETIMER) */
910 
911 /*******************************************************************************
912  * EOF
913  ******************************************************************************/
void IC_IrqHandler(uint32_t instance, uint8_t channel)
Definition: ic_pal.c:1093