S32K118.h
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1 /*
2 ** ###################################################################
3 ** Processor: S32K118_64
4 ** Reference manual: S32K1XXRM Rev. 6, 12/2017
5 ** Version: rev. 1.1, 2018-02-08
6 ** Build: b180208
7 **
8 ** Abstract:
9 ** Peripheral Access Layer for S32K118
10 **
11 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
12 ** Copyright 2016-2018 NXP
13 ** All rights reserved.
14 **
15 ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
16 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
19 ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
25 ** THE POSSIBILITY OF SUCH DAMAGE.
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 1.0 (2017-12-14) - Mihai Volmer
32 ** Initial version based on S32K1XXRM Rev. 6, 12/2017.
33 ** - rev. 1.1 (2018-02-08) - Mihai Volmer
34 ** Renamed the NVIC register array IP to IPR to reflect the register access difference from Cortex-M4 NVIC registers
35 ** Fixed CSE_PRAM base address
36 **
37 ** ###################################################################
38 */
39 
88 /* ----------------------------------------------------------------------------
89  -- MCU activation
90  ---------------------------------------------------------------------------- */
91 
92 /* Prevention from multiple including the same memory map */
93 #if !defined(S32K118_H_) /* Check if memory map has not been already included */
94 #define S32K118_H_
95 #define MCU_S32K118
96 
97 /* Check if another memory map has not been also included */
98 #if (defined(MCU_ACTIVE))
99  #error S32K118 memory map: There is already included another memory map. Only one memory map can be included.
100 #endif /* (defined(MCU_ACTIVE)) */
101 #define MCU_ACTIVE
102 
103 #include <stdint.h>
104 
107 #define MCU_MEM_MAP_VERSION 0x0100u
108 
109 #define MCU_MEM_MAP_VERSION_MINOR 0x0001u
110 
111 /* ----------------------------------------------------------------------------
112  -- Generic macros
113  ---------------------------------------------------------------------------- */
114 
115 /* IO definitions (access restrictions to peripheral registers) */
121 #ifndef __IO
122 #ifdef __cplusplus
123  #define __I volatile
124 #else
125  #define __I volatile const
126 #endif
127 #define __O volatile
128 #define __IO volatile
129 #endif
130 
131 
135 #if !defined(REG_READ32)
136  #define REG_READ32(address) (*(volatile uint32_t*)(address))
137 #endif
138 
142 #if !defined(REG_WRITE32)
143  #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value))
144 #endif
145 
149 #if !defined(REG_BIT_SET32)
150  #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask))
151 #endif
152 
156 #if !defined(REG_BIT_CLEAR32)
157  #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask))))
158 #endif
159 
164 #if !defined(REG_RMW32)
165  #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value)))))
166 #endif
167 
168 
169 /* ----------------------------------------------------------------------------
170  -- Interrupt vector numbers for S32K118
171  ---------------------------------------------------------------------------- */
172 
179 #define NUMBER_OF_INT_VECTORS 48u
188 typedef enum
189 {
190  /* Auxiliary constants */
191  NotAvail_IRQn = -128,
193  /* Core interrupts */
196  SVCall_IRQn = -5,
197  PendSV_IRQn = -2,
200  /* Device specific interrupts */
201  DMA0_IRQn = 0u,
202  DMA1_IRQn = 1u,
203  DMA2_IRQn = 2u,
204  DMA3_IRQn = 3u,
207  RTC_IRQn = 6u,
209  LPTMR0_IRQn = 8u,
210  PORT_IRQn = 9u,
219  FTFC_IRQn = 18u,
220  PDB0_IRQn = 19u,
221  LPIT0_IRQn = 20u,
223  WDOG_IRQn = 22u,
224  RCM_IRQn = 23u,
226  FLEXIO_IRQn = 25u,
227  LPSPI0_IRQn = 26u,
228  LPSPI1_IRQn = 27u,
229  ADC0_IRQn = 28u,
230  CMP0_IRQn = 29u,
233 } IRQn_Type;
234  /* end of group Interrupt_vector_numbers_S32K118 */
238 
239 
240 /* ----------------------------------------------------------------------------
241  -- Device Peripheral Access Layer for S32K118
242  ---------------------------------------------------------------------------- */
243 
249 /* @brief This module covers memory mapped registers available on SoC */
250 
251 /* ----------------------------------------------------------------------------
252  -- ADC Peripheral Access Layer
253  ---------------------------------------------------------------------------- */
254 
262 #define ADC_SC1_COUNT 16u
263 #define ADC_R_COUNT 16u
264 #define ADC_CV_COUNT 2u
265 
267 typedef struct {
268  __IO uint32_t SC1[ADC_SC1_COUNT];
269  __IO uint32_t CFG1;
270  __IO uint32_t CFG2;
271  __I uint32_t R[ADC_R_COUNT];
272  __IO uint32_t CV[ADC_CV_COUNT];
273  __IO uint32_t SC2;
274  __IO uint32_t SC3;
275  __IO uint32_t BASE_OFS;
276  __IO uint32_t OFS;
277  __IO uint32_t USR_OFS;
278  __IO uint32_t XOFS;
279  __IO uint32_t YOFS;
280  __IO uint32_t G;
281  __IO uint32_t UG;
282  __IO uint32_t CLPS;
283  __IO uint32_t CLP3;
284  __IO uint32_t CLP2;
285  __IO uint32_t CLP1;
286  __IO uint32_t CLP0;
287  __IO uint32_t CLPX;
288  __IO uint32_t CLP9;
289  __IO uint32_t CLPS_OFS;
290  __IO uint32_t CLP3_OFS;
291  __IO uint32_t CLP2_OFS;
292  __IO uint32_t CLP1_OFS;
293  __IO uint32_t CLP0_OFS;
294  __IO uint32_t CLPX_OFS;
295  __IO uint32_t CLP9_OFS;
297 
299 #define ADC_INSTANCE_COUNT (1u)
300 
301 
302 /* ADC - Peripheral instance base addresses */
304 #define ADC0_BASE (0x4003B000u)
305 
306 #define ADC0 ((ADC_Type *)ADC0_BASE)
307 
308 #define ADC_BASE_ADDRS { ADC0_BASE }
309 
310 #define ADC_BASE_PTRS { ADC0 }
311 
312 #define ADC_IRQS_ARR_COUNT (1u)
313 
314 #define ADC_IRQS_CH_COUNT (1u)
315 
316 #define ADC_IRQS { ADC0_IRQn }
317 
318 /* ----------------------------------------------------------------------------
319  -- ADC Register Masks
320  ---------------------------------------------------------------------------- */
321 
327 /* SC1 Bit Fields */
328 #define ADC_SC1_ADCH_MASK 0x1Fu
329 #define ADC_SC1_ADCH_SHIFT 0u
330 #define ADC_SC1_ADCH_WIDTH 5u
331 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
332 #define ADC_SC1_AIEN_MASK 0x40u
333 #define ADC_SC1_AIEN_SHIFT 6u
334 #define ADC_SC1_AIEN_WIDTH 1u
335 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
336 #define ADC_SC1_COCO_MASK 0x80u
337 #define ADC_SC1_COCO_SHIFT 7u
338 #define ADC_SC1_COCO_WIDTH 1u
339 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
340 /* CFG1 Bit Fields */
341 #define ADC_CFG1_ADICLK_MASK 0x3u
342 #define ADC_CFG1_ADICLK_SHIFT 0u
343 #define ADC_CFG1_ADICLK_WIDTH 2u
344 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
345 #define ADC_CFG1_MODE_MASK 0xCu
346 #define ADC_CFG1_MODE_SHIFT 2u
347 #define ADC_CFG1_MODE_WIDTH 2u
348 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
349 #define ADC_CFG1_ADIV_MASK 0x60u
350 #define ADC_CFG1_ADIV_SHIFT 5u
351 #define ADC_CFG1_ADIV_WIDTH 2u
352 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
353 #define ADC_CFG1_CLRLTRG_MASK 0x100u
354 #define ADC_CFG1_CLRLTRG_SHIFT 8u
355 #define ADC_CFG1_CLRLTRG_WIDTH 1u
356 #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_CLRLTRG_SHIFT))&ADC_CFG1_CLRLTRG_MASK)
357 /* CFG2 Bit Fields */
358 #define ADC_CFG2_SMPLTS_MASK 0xFFu
359 #define ADC_CFG2_SMPLTS_SHIFT 0u
360 #define ADC_CFG2_SMPLTS_WIDTH 8u
361 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_SMPLTS_SHIFT))&ADC_CFG2_SMPLTS_MASK)
362 /* R Bit Fields */
363 #define ADC_R_D_MASK 0xFFFu
364 #define ADC_R_D_SHIFT 0u
365 #define ADC_R_D_WIDTH 12u
366 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
367 /* CV Bit Fields */
368 #define ADC_CV_CV_MASK 0xFFFFu
369 #define ADC_CV_CV_SHIFT 0u
370 #define ADC_CV_CV_WIDTH 16u
371 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV_SHIFT))&ADC_CV_CV_MASK)
372 /* SC2 Bit Fields */
373 #define ADC_SC2_REFSEL_MASK 0x3u
374 #define ADC_SC2_REFSEL_SHIFT 0u
375 #define ADC_SC2_REFSEL_WIDTH 2u
376 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
377 #define ADC_SC2_DMAEN_MASK 0x4u
378 #define ADC_SC2_DMAEN_SHIFT 2u
379 #define ADC_SC2_DMAEN_WIDTH 1u
380 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
381 #define ADC_SC2_ACREN_MASK 0x8u
382 #define ADC_SC2_ACREN_SHIFT 3u
383 #define ADC_SC2_ACREN_WIDTH 1u
384 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
385 #define ADC_SC2_ACFGT_MASK 0x10u
386 #define ADC_SC2_ACFGT_SHIFT 4u
387 #define ADC_SC2_ACFGT_WIDTH 1u
388 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
389 #define ADC_SC2_ACFE_MASK 0x20u
390 #define ADC_SC2_ACFE_SHIFT 5u
391 #define ADC_SC2_ACFE_WIDTH 1u
392 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
393 #define ADC_SC2_ADTRG_MASK 0x40u
394 #define ADC_SC2_ADTRG_SHIFT 6u
395 #define ADC_SC2_ADTRG_WIDTH 1u
396 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
397 #define ADC_SC2_ADACT_MASK 0x80u
398 #define ADC_SC2_ADACT_SHIFT 7u
399 #define ADC_SC2_ADACT_WIDTH 1u
400 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
401 #define ADC_SC2_TRGPRNUM_MASK 0x6000u
402 #define ADC_SC2_TRGPRNUM_SHIFT 13u
403 #define ADC_SC2_TRGPRNUM_WIDTH 2u
404 #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGPRNUM_SHIFT))&ADC_SC2_TRGPRNUM_MASK)
405 #define ADC_SC2_TRGSTLAT_MASK 0xF0000u
406 #define ADC_SC2_TRGSTLAT_SHIFT 16u
407 #define ADC_SC2_TRGSTLAT_WIDTH 4u
408 #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTLAT_SHIFT))&ADC_SC2_TRGSTLAT_MASK)
409 #define ADC_SC2_TRGSTERR_MASK 0xF000000u
410 #define ADC_SC2_TRGSTERR_SHIFT 24u
411 #define ADC_SC2_TRGSTERR_WIDTH 4u
412 #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTERR_SHIFT))&ADC_SC2_TRGSTERR_MASK)
413 /* SC3 Bit Fields */
414 #define ADC_SC3_AVGS_MASK 0x3u
415 #define ADC_SC3_AVGS_SHIFT 0u
416 #define ADC_SC3_AVGS_WIDTH 2u
417 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
418 #define ADC_SC3_AVGE_MASK 0x4u
419 #define ADC_SC3_AVGE_SHIFT 2u
420 #define ADC_SC3_AVGE_WIDTH 1u
421 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
422 #define ADC_SC3_ADCO_MASK 0x8u
423 #define ADC_SC3_ADCO_SHIFT 3u
424 #define ADC_SC3_ADCO_WIDTH 1u
425 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
426 #define ADC_SC3_CAL_MASK 0x80u
427 #define ADC_SC3_CAL_SHIFT 7u
428 #define ADC_SC3_CAL_WIDTH 1u
429 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
430 /* BASE_OFS Bit Fields */
431 #define ADC_BASE_OFS_BA_OFS_MASK 0xFFu
432 #define ADC_BASE_OFS_BA_OFS_SHIFT 0u
433 #define ADC_BASE_OFS_BA_OFS_WIDTH 8u
434 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_BASE_OFS_BA_OFS_SHIFT))&ADC_BASE_OFS_BA_OFS_MASK)
435 /* OFS Bit Fields */
436 #define ADC_OFS_OFS_MASK 0xFFFFu
437 #define ADC_OFS_OFS_SHIFT 0u
438 #define ADC_OFS_OFS_WIDTH 16u
439 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
440 /* USR_OFS Bit Fields */
441 #define ADC_USR_OFS_USR_OFS_MASK 0xFFu
442 #define ADC_USR_OFS_USR_OFS_SHIFT 0u
443 #define ADC_USR_OFS_USR_OFS_WIDTH 8u
444 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_USR_OFS_USR_OFS_SHIFT))&ADC_USR_OFS_USR_OFS_MASK)
445 /* XOFS Bit Fields */
446 #define ADC_XOFS_XOFS_MASK 0x3Fu
447 #define ADC_XOFS_XOFS_SHIFT 0u
448 #define ADC_XOFS_XOFS_WIDTH 6u
449 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_XOFS_XOFS_SHIFT))&ADC_XOFS_XOFS_MASK)
450 /* YOFS Bit Fields */
451 #define ADC_YOFS_YOFS_MASK 0xFFu
452 #define ADC_YOFS_YOFS_SHIFT 0u
453 #define ADC_YOFS_YOFS_WIDTH 8u
454 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_YOFS_YOFS_SHIFT))&ADC_YOFS_YOFS_MASK)
455 /* G Bit Fields */
456 #define ADC_G_G_MASK 0x7FFu
457 #define ADC_G_G_SHIFT 0u
458 #define ADC_G_G_WIDTH 11u
459 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x))<<ADC_G_G_SHIFT))&ADC_G_G_MASK)
460 /* UG Bit Fields */
461 #define ADC_UG_UG_MASK 0x3FFu
462 #define ADC_UG_UG_SHIFT 0u
463 #define ADC_UG_UG_WIDTH 10u
464 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x))<<ADC_UG_UG_SHIFT))&ADC_UG_UG_MASK)
465 /* CLPS Bit Fields */
466 #define ADC_CLPS_CLPS_MASK 0x7Fu
467 #define ADC_CLPS_CLPS_SHIFT 0u
468 #define ADC_CLPS_CLPS_WIDTH 7u
469 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
470 /* CLP3 Bit Fields */
471 #define ADC_CLP3_CLP3_MASK 0x3FFu
472 #define ADC_CLP3_CLP3_SHIFT 0u
473 #define ADC_CLP3_CLP3_WIDTH 10u
474 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
475 /* CLP2 Bit Fields */
476 #define ADC_CLP2_CLP2_MASK 0x3FFu
477 #define ADC_CLP2_CLP2_SHIFT 0u
478 #define ADC_CLP2_CLP2_WIDTH 10u
479 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
480 /* CLP1 Bit Fields */
481 #define ADC_CLP1_CLP1_MASK 0x1FFu
482 #define ADC_CLP1_CLP1_SHIFT 0u
483 #define ADC_CLP1_CLP1_WIDTH 9u
484 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
485 /* CLP0 Bit Fields */
486 #define ADC_CLP0_CLP0_MASK 0xFFu
487 #define ADC_CLP0_CLP0_SHIFT 0u
488 #define ADC_CLP0_CLP0_WIDTH 8u
489 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
490 /* CLPX Bit Fields */
491 #define ADC_CLPX_CLPX_MASK 0x7Fu
492 #define ADC_CLPX_CLPX_SHIFT 0u
493 #define ADC_CLPX_CLPX_WIDTH 7u
494 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_CLPX_SHIFT))&ADC_CLPX_CLPX_MASK)
495 /* CLP9 Bit Fields */
496 #define ADC_CLP9_CLP9_MASK 0x7Fu
497 #define ADC_CLP9_CLP9_SHIFT 0u
498 #define ADC_CLP9_CLP9_WIDTH 7u
499 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_CLP9_SHIFT))&ADC_CLP9_CLP9_MASK)
500 /* CLPS_OFS Bit Fields */
501 #define ADC_CLPS_OFS_CLPS_OFS_MASK 0xFu
502 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT 0u
503 #define ADC_CLPS_OFS_CLPS_OFS_WIDTH 4u
504 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_OFS_CLPS_OFS_SHIFT))&ADC_CLPS_OFS_CLPS_OFS_MASK)
505 /* CLP3_OFS Bit Fields */
506 #define ADC_CLP3_OFS_CLP3_OFS_MASK 0xFu
507 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT 0u
508 #define ADC_CLP3_OFS_CLP3_OFS_WIDTH 4u
509 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_OFS_CLP3_OFS_SHIFT))&ADC_CLP3_OFS_CLP3_OFS_MASK)
510 /* CLP2_OFS Bit Fields */
511 #define ADC_CLP2_OFS_CLP2_OFS_MASK 0xFu
512 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT 0u
513 #define ADC_CLP2_OFS_CLP2_OFS_WIDTH 4u
514 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_OFS_CLP2_OFS_SHIFT))&ADC_CLP2_OFS_CLP2_OFS_MASK)
515 /* CLP1_OFS Bit Fields */
516 #define ADC_CLP1_OFS_CLP1_OFS_MASK 0xFu
517 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT 0u
518 #define ADC_CLP1_OFS_CLP1_OFS_WIDTH 4u
519 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_OFS_CLP1_OFS_SHIFT))&ADC_CLP1_OFS_CLP1_OFS_MASK)
520 /* CLP0_OFS Bit Fields */
521 #define ADC_CLP0_OFS_CLP0_OFS_MASK 0xFu
522 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT 0u
523 #define ADC_CLP0_OFS_CLP0_OFS_WIDTH 4u
524 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_OFS_CLP0_OFS_SHIFT))&ADC_CLP0_OFS_CLP0_OFS_MASK)
525 /* CLPX_OFS Bit Fields */
526 #define ADC_CLPX_OFS_CLPX_OFS_MASK 0xFFFu
527 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT 0u
528 #define ADC_CLPX_OFS_CLPX_OFS_WIDTH 12u
529 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_OFS_CLPX_OFS_SHIFT))&ADC_CLPX_OFS_CLPX_OFS_MASK)
530 /* CLP9_OFS Bit Fields */
531 #define ADC_CLP9_OFS_CLP9_OFS_MASK 0xFFFu
532 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT 0u
533 #define ADC_CLP9_OFS_CLP9_OFS_WIDTH 12u
534 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_OFS_CLP9_OFS_SHIFT))&ADC_CLP9_OFS_CLP9_OFS_MASK)
535  /* end of group ADC_Register_Masks */
539 
540  /* end of group ADC_Peripheral_Access_Layer */
544 
545 
546 /* ----------------------------------------------------------------------------
547  -- AIPS Peripheral Access Layer
548  ---------------------------------------------------------------------------- */
549 
557 #define AIPS_PACR_COUNT 4u
558 #define AIPS_OPACR_COUNT 12u
559 
561 typedef struct {
562  __IO uint32_t MPRA;
563  uint8_t RESERVED_0[28];
564  __IO uint32_t PACR[AIPS_PACR_COUNT];
565  uint8_t RESERVED_1[16];
566  __IO uint32_t OPACR[AIPS_OPACR_COUNT];
568 
570 #define AIPS_INSTANCE_COUNT (1u)
571 
572 
573 /* AIPS - Peripheral instance base addresses */
575 #define AIPS_BASE (0x40000000u)
576 
577 #define AIPS ((AIPS_Type *)AIPS_BASE)
578 
579 #define AIPS_BASE_ADDRS { AIPS_BASE }
580 
581 #define AIPS_BASE_PTRS { AIPS }
582 
583 /* ----------------------------------------------------------------------------
584  -- AIPS Register Masks
585  ---------------------------------------------------------------------------- */
586 
592 /* MPRA Bit Fields */
593 #define AIPS_MPRA_MPL2_MASK 0x100000u
594 #define AIPS_MPRA_MPL2_SHIFT 20u
595 #define AIPS_MPRA_MPL2_WIDTH 1u
596 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
597 #define AIPS_MPRA_MTW2_MASK 0x200000u
598 #define AIPS_MPRA_MTW2_SHIFT 21u
599 #define AIPS_MPRA_MTW2_WIDTH 1u
600 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
601 #define AIPS_MPRA_MTR2_MASK 0x400000u
602 #define AIPS_MPRA_MTR2_SHIFT 22u
603 #define AIPS_MPRA_MTR2_WIDTH 1u
604 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
605 #define AIPS_MPRA_MPL1_MASK 0x1000000u
606 #define AIPS_MPRA_MPL1_SHIFT 24u
607 #define AIPS_MPRA_MPL1_WIDTH 1u
608 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
609 #define AIPS_MPRA_MTW1_MASK 0x2000000u
610 #define AIPS_MPRA_MTW1_SHIFT 25u
611 #define AIPS_MPRA_MTW1_WIDTH 1u
612 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
613 #define AIPS_MPRA_MTR1_MASK 0x4000000u
614 #define AIPS_MPRA_MTR1_SHIFT 26u
615 #define AIPS_MPRA_MTR1_WIDTH 1u
616 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
617 #define AIPS_MPRA_MPL0_MASK 0x10000000u
618 #define AIPS_MPRA_MPL0_SHIFT 28u
619 #define AIPS_MPRA_MPL0_WIDTH 1u
620 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
621 #define AIPS_MPRA_MTW0_MASK 0x20000000u
622 #define AIPS_MPRA_MTW0_SHIFT 29u
623 #define AIPS_MPRA_MTW0_WIDTH 1u
624 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
625 #define AIPS_MPRA_MTR0_MASK 0x40000000u
626 #define AIPS_MPRA_MTR0_SHIFT 30u
627 #define AIPS_MPRA_MTR0_WIDTH 1u
628 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
629 /* PACR Bit Fields */
630 #define AIPS_PACR_TP5_MASK 0x100u
631 #define AIPS_PACR_TP5_SHIFT 8u
632 #define AIPS_PACR_TP5_WIDTH 1u
633 #define AIPS_PACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP5_SHIFT))&AIPS_PACR_TP5_MASK)
634 #define AIPS_PACR_WP5_MASK 0x200u
635 #define AIPS_PACR_WP5_SHIFT 9u
636 #define AIPS_PACR_WP5_WIDTH 1u
637 #define AIPS_PACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP5_SHIFT))&AIPS_PACR_WP5_MASK)
638 #define AIPS_PACR_SP5_MASK 0x400u
639 #define AIPS_PACR_SP5_SHIFT 10u
640 #define AIPS_PACR_SP5_WIDTH 1u
641 #define AIPS_PACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP5_SHIFT))&AIPS_PACR_SP5_MASK)
642 #define AIPS_PACR_TP1_MASK 0x1000000u
643 #define AIPS_PACR_TP1_SHIFT 24u
644 #define AIPS_PACR_TP1_WIDTH 1u
645 #define AIPS_PACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP1_SHIFT))&AIPS_PACR_TP1_MASK)
646 #define AIPS_PACR_WP1_MASK 0x2000000u
647 #define AIPS_PACR_WP1_SHIFT 25u
648 #define AIPS_PACR_WP1_WIDTH 1u
649 #define AIPS_PACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP1_SHIFT))&AIPS_PACR_WP1_MASK)
650 #define AIPS_PACR_SP1_MASK 0x4000000u
651 #define AIPS_PACR_SP1_SHIFT 26u
652 #define AIPS_PACR_SP1_WIDTH 1u
653 #define AIPS_PACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP1_SHIFT))&AIPS_PACR_SP1_MASK)
654 #define AIPS_PACR_TP0_MASK 0x10000000u
655 #define AIPS_PACR_TP0_SHIFT 28u
656 #define AIPS_PACR_TP0_WIDTH 1u
657 #define AIPS_PACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP0_SHIFT))&AIPS_PACR_TP0_MASK)
658 #define AIPS_PACR_WP0_MASK 0x20000000u
659 #define AIPS_PACR_WP0_SHIFT 29u
660 #define AIPS_PACR_WP0_WIDTH 1u
661 #define AIPS_PACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP0_SHIFT))&AIPS_PACR_WP0_MASK)
662 #define AIPS_PACR_SP0_MASK 0x40000000u
663 #define AIPS_PACR_SP0_SHIFT 30u
664 #define AIPS_PACR_SP0_WIDTH 1u
665 #define AIPS_PACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP0_SHIFT))&AIPS_PACR_SP0_MASK)
666 /* OPACR Bit Fields */
667 #define AIPS_OPACR_TP7_MASK 0x1u
668 #define AIPS_OPACR_TP7_SHIFT 0u
669 #define AIPS_OPACR_TP7_WIDTH 1u
670 #define AIPS_OPACR_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP7_SHIFT))&AIPS_OPACR_TP7_MASK)
671 #define AIPS_OPACR_WP7_MASK 0x2u
672 #define AIPS_OPACR_WP7_SHIFT 1u
673 #define AIPS_OPACR_WP7_WIDTH 1u
674 #define AIPS_OPACR_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP7_SHIFT))&AIPS_OPACR_WP7_MASK)
675 #define AIPS_OPACR_SP7_MASK 0x4u
676 #define AIPS_OPACR_SP7_SHIFT 2u
677 #define AIPS_OPACR_SP7_WIDTH 1u
678 #define AIPS_OPACR_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP7_SHIFT))&AIPS_OPACR_SP7_MASK)
679 #define AIPS_OPACR_TP6_MASK 0x10u
680 #define AIPS_OPACR_TP6_SHIFT 4u
681 #define AIPS_OPACR_TP6_WIDTH 1u
682 #define AIPS_OPACR_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP6_SHIFT))&AIPS_OPACR_TP6_MASK)
683 #define AIPS_OPACR_WP6_MASK 0x20u
684 #define AIPS_OPACR_WP6_SHIFT 5u
685 #define AIPS_OPACR_WP6_WIDTH 1u
686 #define AIPS_OPACR_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP6_SHIFT))&AIPS_OPACR_WP6_MASK)
687 #define AIPS_OPACR_SP6_MASK 0x40u
688 #define AIPS_OPACR_SP6_SHIFT 6u
689 #define AIPS_OPACR_SP6_WIDTH 1u
690 #define AIPS_OPACR_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP6_SHIFT))&AIPS_OPACR_SP6_MASK)
691 #define AIPS_OPACR_TP5_MASK 0x100u
692 #define AIPS_OPACR_TP5_SHIFT 8u
693 #define AIPS_OPACR_TP5_WIDTH 1u
694 #define AIPS_OPACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP5_SHIFT))&AIPS_OPACR_TP5_MASK)
695 #define AIPS_OPACR_WP5_MASK 0x200u
696 #define AIPS_OPACR_WP5_SHIFT 9u
697 #define AIPS_OPACR_WP5_WIDTH 1u
698 #define AIPS_OPACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP5_SHIFT))&AIPS_OPACR_WP5_MASK)
699 #define AIPS_OPACR_SP5_MASK 0x400u
700 #define AIPS_OPACR_SP5_SHIFT 10u
701 #define AIPS_OPACR_SP5_WIDTH 1u
702 #define AIPS_OPACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP5_SHIFT))&AIPS_OPACR_SP5_MASK)
703 #define AIPS_OPACR_TP4_MASK 0x1000u
704 #define AIPS_OPACR_TP4_SHIFT 12u
705 #define AIPS_OPACR_TP4_WIDTH 1u
706 #define AIPS_OPACR_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP4_SHIFT))&AIPS_OPACR_TP4_MASK)
707 #define AIPS_OPACR_WP4_MASK 0x2000u
708 #define AIPS_OPACR_WP4_SHIFT 13u
709 #define AIPS_OPACR_WP4_WIDTH 1u
710 #define AIPS_OPACR_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP4_SHIFT))&AIPS_OPACR_WP4_MASK)
711 #define AIPS_OPACR_SP4_MASK 0x4000u
712 #define AIPS_OPACR_SP4_SHIFT 14u
713 #define AIPS_OPACR_SP4_WIDTH 1u
714 #define AIPS_OPACR_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP4_SHIFT))&AIPS_OPACR_SP4_MASK)
715 #define AIPS_OPACR_TP3_MASK 0x10000u
716 #define AIPS_OPACR_TP3_SHIFT 16u
717 #define AIPS_OPACR_TP3_WIDTH 1u
718 #define AIPS_OPACR_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP3_SHIFT))&AIPS_OPACR_TP3_MASK)
719 #define AIPS_OPACR_WP3_MASK 0x20000u
720 #define AIPS_OPACR_WP3_SHIFT 17u
721 #define AIPS_OPACR_WP3_WIDTH 1u
722 #define AIPS_OPACR_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP3_SHIFT))&AIPS_OPACR_WP3_MASK)
723 #define AIPS_OPACR_SP3_MASK 0x40000u
724 #define AIPS_OPACR_SP3_SHIFT 18u
725 #define AIPS_OPACR_SP3_WIDTH 1u
726 #define AIPS_OPACR_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP3_SHIFT))&AIPS_OPACR_SP3_MASK)
727 #define AIPS_OPACR_TP2_MASK 0x100000u
728 #define AIPS_OPACR_TP2_SHIFT 20u
729 #define AIPS_OPACR_TP2_WIDTH 1u
730 #define AIPS_OPACR_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP2_SHIFT))&AIPS_OPACR_TP2_MASK)
731 #define AIPS_OPACR_WP2_MASK 0x200000u
732 #define AIPS_OPACR_WP2_SHIFT 21u
733 #define AIPS_OPACR_WP2_WIDTH 1u
734 #define AIPS_OPACR_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP2_SHIFT))&AIPS_OPACR_WP2_MASK)
735 #define AIPS_OPACR_SP2_MASK 0x400000u
736 #define AIPS_OPACR_SP2_SHIFT 22u
737 #define AIPS_OPACR_SP2_WIDTH 1u
738 #define AIPS_OPACR_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP2_SHIFT))&AIPS_OPACR_SP2_MASK)
739 #define AIPS_OPACR_TP1_MASK 0x1000000u
740 #define AIPS_OPACR_TP1_SHIFT 24u
741 #define AIPS_OPACR_TP1_WIDTH 1u
742 #define AIPS_OPACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP1_SHIFT))&AIPS_OPACR_TP1_MASK)
743 #define AIPS_OPACR_WP1_MASK 0x2000000u
744 #define AIPS_OPACR_WP1_SHIFT 25u
745 #define AIPS_OPACR_WP1_WIDTH 1u
746 #define AIPS_OPACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP1_SHIFT))&AIPS_OPACR_WP1_MASK)
747 #define AIPS_OPACR_SP1_MASK 0x4000000u
748 #define AIPS_OPACR_SP1_SHIFT 26u
749 #define AIPS_OPACR_SP1_WIDTH 1u
750 #define AIPS_OPACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP1_SHIFT))&AIPS_OPACR_SP1_MASK)
751 #define AIPS_OPACR_TP0_MASK 0x10000000u
752 #define AIPS_OPACR_TP0_SHIFT 28u
753 #define AIPS_OPACR_TP0_WIDTH 1u
754 #define AIPS_OPACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP0_SHIFT))&AIPS_OPACR_TP0_MASK)
755 #define AIPS_OPACR_WP0_MASK 0x20000000u
756 #define AIPS_OPACR_WP0_SHIFT 29u
757 #define AIPS_OPACR_WP0_WIDTH 1u
758 #define AIPS_OPACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP0_SHIFT))&AIPS_OPACR_WP0_MASK)
759 #define AIPS_OPACR_SP0_MASK 0x40000000u
760 #define AIPS_OPACR_SP0_SHIFT 30u
761 #define AIPS_OPACR_SP0_WIDTH 1u
762 #define AIPS_OPACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP0_SHIFT))&AIPS_OPACR_SP0_MASK)
763  /* end of group AIPS_Register_Masks */
767 
768  /* end of group AIPS_Peripheral_Access_Layer */
772 
773 
774 /* ----------------------------------------------------------------------------
775  -- CAN Peripheral Access Layer
776  ---------------------------------------------------------------------------- */
777 
785 #define CAN_RAMn_COUNT 128u
786 #define CAN_RXIMR_COUNT 32u
787 #define CAN_WMB_COUNT 4u
788 
790 typedef struct {
791  __IO uint32_t MCR;
792  __IO uint32_t CTRL1;
793  __IO uint32_t TIMER;
794  uint8_t RESERVED_0[4];
795  __IO uint32_t RXMGMASK;
796  __IO uint32_t RX14MASK;
797  __IO uint32_t RX15MASK;
798  __IO uint32_t ECR;
799  __IO uint32_t ESR1;
800  uint8_t RESERVED_1[4];
801  __IO uint32_t IMASK1;
802  uint8_t RESERVED_2[4];
803  __IO uint32_t IFLAG1;
804  __IO uint32_t CTRL2;
805  __I uint32_t ESR2;
806  uint8_t RESERVED_3[8];
807  __I uint32_t CRCR;
808  __IO uint32_t RXFGMASK;
809  __I uint32_t RXFIR;
810  __IO uint32_t CBT;
811  uint8_t RESERVED_4[44];
812  __IO uint32_t RAMn[CAN_RAMn_COUNT];
813  uint8_t RESERVED_5[1536];
814  __IO uint32_t RXIMR[CAN_RXIMR_COUNT];
815  uint8_t RESERVED_6[512];
816  __IO uint32_t CTRL1_PN;
817  __IO uint32_t CTRL2_PN;
818  __IO uint32_t WU_MTC;
819  __IO uint32_t FLT_ID1;
820  __IO uint32_t FLT_DLC;
821  __IO uint32_t PL1_LO;
822  __IO uint32_t PL1_HI;
823  __IO uint32_t FLT_ID2_IDMASK;
824  __IO uint32_t PL2_PLMASK_LO;
825  __IO uint32_t PL2_PLMASK_HI;
826  uint8_t RESERVED_7[24];
827  struct { /* offset: 0xB40, array step: 0x10 */
828  __I uint32_t WMBn_CS;
829  __I uint32_t WMBn_ID;
830  __I uint32_t WMBn_D03;
831  __I uint32_t WMBn_D47;
832  } WMB[CAN_WMB_COUNT];
833  uint8_t RESERVED_8[128];
834  __IO uint32_t FDCTRL;
835  __IO uint32_t FDCBT;
836  __I uint32_t FDCRC;
838 
840 #define CAN_INSTANCE_COUNT (1u)
841 
842 
843 /* CAN - Peripheral instance base addresses */
845 #define CAN0_BASE (0x40024000u)
846 
847 #define CAN0 ((CAN_Type *)CAN0_BASE)
848 
849 #define CAN_BASE_ADDRS { CAN0_BASE }
850 
851 #define CAN_BASE_PTRS { CAN0 }
852 
853 #define CAN_IRQS_ARR_COUNT (7u)
854 
855 #define CAN_Rx_Warning_IRQS_CH_COUNT (1u)
856 
857 #define CAN_Tx_Warning_IRQS_CH_COUNT (1u)
858 
859 #define CAN_Wake_Up_IRQS_CH_COUNT (1u)
860 
861 #define CAN_Error_IRQS_CH_COUNT (1u)
862 
863 #define CAN_Bus_Off_IRQS_CH_COUNT (1u)
864 
865 #define CAN_ORed_0_15_MB_IRQS_CH_COUNT (1u)
866 
867 #define CAN_ORed_16_31_MB_IRQS_CH_COUNT (1u)
868 
869 #define CAN_Rx_Warning_IRQS { CAN0_ORed_Err_Wakeup_IRQn }
870 #define CAN_Tx_Warning_IRQS { CAN0_ORed_Err_Wakeup_IRQn }
871 #define CAN_Wake_Up_IRQS { CAN0_ORed_Err_Wakeup_IRQn }
872 #define CAN_Error_IRQS { CAN0_ORed_Err_Wakeup_IRQn }
873 #define CAN_Bus_Off_IRQS { CAN0_ORed_Err_Wakeup_IRQn }
874 #define CAN_ORed_0_15_MB_IRQS { CAN0_ORed_0_31_MB_IRQn }
875 #define CAN_ORed_16_31_MB_IRQS { CAN0_ORed_0_31_MB_IRQn }
876 
877 /* ----------------------------------------------------------------------------
878  -- CAN Register Masks
879  ---------------------------------------------------------------------------- */
880 
886 /* MCR Bit Fields */
887 #define CAN_MCR_MAXMB_MASK 0x7Fu
888 #define CAN_MCR_MAXMB_SHIFT 0u
889 #define CAN_MCR_MAXMB_WIDTH 7u
890 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
891 #define CAN_MCR_IDAM_MASK 0x300u
892 #define CAN_MCR_IDAM_SHIFT 8u
893 #define CAN_MCR_IDAM_WIDTH 2u
894 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
895 #define CAN_MCR_FDEN_MASK 0x800u
896 #define CAN_MCR_FDEN_SHIFT 11u
897 #define CAN_MCR_FDEN_WIDTH 1u
898 #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FDEN_SHIFT))&CAN_MCR_FDEN_MASK)
899 #define CAN_MCR_AEN_MASK 0x1000u
900 #define CAN_MCR_AEN_SHIFT 12u
901 #define CAN_MCR_AEN_WIDTH 1u
902 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
903 #define CAN_MCR_LPRIOEN_MASK 0x2000u
904 #define CAN_MCR_LPRIOEN_SHIFT 13u
905 #define CAN_MCR_LPRIOEN_WIDTH 1u
906 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
907 #define CAN_MCR_PNET_EN_MASK 0x4000u
908 #define CAN_MCR_PNET_EN_SHIFT 14u
909 #define CAN_MCR_PNET_EN_WIDTH 1u
910 #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_PNET_EN_SHIFT))&CAN_MCR_PNET_EN_MASK)
911 #define CAN_MCR_DMA_MASK 0x8000u
912 #define CAN_MCR_DMA_SHIFT 15u
913 #define CAN_MCR_DMA_WIDTH 1u
914 #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DMA_SHIFT))&CAN_MCR_DMA_MASK)
915 #define CAN_MCR_IRMQ_MASK 0x10000u
916 #define CAN_MCR_IRMQ_SHIFT 16u
917 #define CAN_MCR_IRMQ_WIDTH 1u
918 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
919 #define CAN_MCR_SRXDIS_MASK 0x20000u
920 #define CAN_MCR_SRXDIS_SHIFT 17u
921 #define CAN_MCR_SRXDIS_WIDTH 1u
922 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
923 #define CAN_MCR_LPMACK_MASK 0x100000u
924 #define CAN_MCR_LPMACK_SHIFT 20u
925 #define CAN_MCR_LPMACK_WIDTH 1u
926 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
927 #define CAN_MCR_WRNEN_MASK 0x200000u
928 #define CAN_MCR_WRNEN_SHIFT 21u
929 #define CAN_MCR_WRNEN_WIDTH 1u
930 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
931 #define CAN_MCR_SUPV_MASK 0x800000u
932 #define CAN_MCR_SUPV_SHIFT 23u
933 #define CAN_MCR_SUPV_WIDTH 1u
934 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
935 #define CAN_MCR_FRZACK_MASK 0x1000000u
936 #define CAN_MCR_FRZACK_SHIFT 24u
937 #define CAN_MCR_FRZACK_WIDTH 1u
938 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
939 #define CAN_MCR_SOFTRST_MASK 0x2000000u
940 #define CAN_MCR_SOFTRST_SHIFT 25u
941 #define CAN_MCR_SOFTRST_WIDTH 1u
942 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
943 #define CAN_MCR_NOTRDY_MASK 0x8000000u
944 #define CAN_MCR_NOTRDY_SHIFT 27u
945 #define CAN_MCR_NOTRDY_WIDTH 1u
946 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
947 #define CAN_MCR_HALT_MASK 0x10000000u
948 #define CAN_MCR_HALT_SHIFT 28u
949 #define CAN_MCR_HALT_WIDTH 1u
950 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
951 #define CAN_MCR_RFEN_MASK 0x20000000u
952 #define CAN_MCR_RFEN_SHIFT 29u
953 #define CAN_MCR_RFEN_WIDTH 1u
954 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
955 #define CAN_MCR_FRZ_MASK 0x40000000u
956 #define CAN_MCR_FRZ_SHIFT 30u
957 #define CAN_MCR_FRZ_WIDTH 1u
958 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
959 #define CAN_MCR_MDIS_MASK 0x80000000u
960 #define CAN_MCR_MDIS_SHIFT 31u
961 #define CAN_MCR_MDIS_WIDTH 1u
962 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
963 /* CTRL1 Bit Fields */
964 #define CAN_CTRL1_PROPSEG_MASK 0x7u
965 #define CAN_CTRL1_PROPSEG_SHIFT 0u
966 #define CAN_CTRL1_PROPSEG_WIDTH 3u
967 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
968 #define CAN_CTRL1_LOM_MASK 0x8u
969 #define CAN_CTRL1_LOM_SHIFT 3u
970 #define CAN_CTRL1_LOM_WIDTH 1u
971 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
972 #define CAN_CTRL1_LBUF_MASK 0x10u
973 #define CAN_CTRL1_LBUF_SHIFT 4u
974 #define CAN_CTRL1_LBUF_WIDTH 1u
975 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
976 #define CAN_CTRL1_TSYN_MASK 0x20u
977 #define CAN_CTRL1_TSYN_SHIFT 5u
978 #define CAN_CTRL1_TSYN_WIDTH 1u
979 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
980 #define CAN_CTRL1_BOFFREC_MASK 0x40u
981 #define CAN_CTRL1_BOFFREC_SHIFT 6u
982 #define CAN_CTRL1_BOFFREC_WIDTH 1u
983 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
984 #define CAN_CTRL1_SMP_MASK 0x80u
985 #define CAN_CTRL1_SMP_SHIFT 7u
986 #define CAN_CTRL1_SMP_WIDTH 1u
987 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
988 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
989 #define CAN_CTRL1_RWRNMSK_SHIFT 10u
990 #define CAN_CTRL1_RWRNMSK_WIDTH 1u
991 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
992 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
993 #define CAN_CTRL1_TWRNMSK_SHIFT 11u
994 #define CAN_CTRL1_TWRNMSK_WIDTH 1u
995 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
996 #define CAN_CTRL1_LPB_MASK 0x1000u
997 #define CAN_CTRL1_LPB_SHIFT 12u
998 #define CAN_CTRL1_LPB_WIDTH 1u
999 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
1000 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
1001 #define CAN_CTRL1_CLKSRC_SHIFT 13u
1002 #define CAN_CTRL1_CLKSRC_WIDTH 1u
1003 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
1004 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
1005 #define CAN_CTRL1_ERRMSK_SHIFT 14u
1006 #define CAN_CTRL1_ERRMSK_WIDTH 1u
1007 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
1008 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
1009 #define CAN_CTRL1_BOFFMSK_SHIFT 15u
1010 #define CAN_CTRL1_BOFFMSK_WIDTH 1u
1011 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
1012 #define CAN_CTRL1_PSEG2_MASK 0x70000u
1013 #define CAN_CTRL1_PSEG2_SHIFT 16u
1014 #define CAN_CTRL1_PSEG2_WIDTH 3u
1015 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
1016 #define CAN_CTRL1_PSEG1_MASK 0x380000u
1017 #define CAN_CTRL1_PSEG1_SHIFT 19u
1018 #define CAN_CTRL1_PSEG1_WIDTH 3u
1019 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
1020 #define CAN_CTRL1_RJW_MASK 0xC00000u
1021 #define CAN_CTRL1_RJW_SHIFT 22u
1022 #define CAN_CTRL1_RJW_WIDTH 2u
1023 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
1024 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
1025 #define CAN_CTRL1_PRESDIV_SHIFT 24u
1026 #define CAN_CTRL1_PRESDIV_WIDTH 8u
1027 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
1028 /* TIMER Bit Fields */
1029 #define CAN_TIMER_TIMER_MASK 0xFFFFu
1030 #define CAN_TIMER_TIMER_SHIFT 0u
1031 #define CAN_TIMER_TIMER_WIDTH 16u
1032 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
1033 /* RXMGMASK Bit Fields */
1034 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
1035 #define CAN_RXMGMASK_MG_SHIFT 0u
1036 #define CAN_RXMGMASK_MG_WIDTH 32u
1037 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
1038 /* RX14MASK Bit Fields */
1039 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
1040 #define CAN_RX14MASK_RX14M_SHIFT 0u
1041 #define CAN_RX14MASK_RX14M_WIDTH 32u
1042 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
1043 /* RX15MASK Bit Fields */
1044 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
1045 #define CAN_RX15MASK_RX15M_SHIFT 0u
1046 #define CAN_RX15MASK_RX15M_WIDTH 32u
1047 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
1048 /* ECR Bit Fields */
1049 #define CAN_ECR_TXERRCNT_MASK 0xFFu
1050 #define CAN_ECR_TXERRCNT_SHIFT 0u
1051 #define CAN_ECR_TXERRCNT_WIDTH 8u
1052 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
1053 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
1054 #define CAN_ECR_RXERRCNT_SHIFT 8u
1055 #define CAN_ECR_RXERRCNT_WIDTH 8u
1056 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
1057 #define CAN_ECR_TXERRCNT_FAST_MASK 0xFF0000u
1058 #define CAN_ECR_TXERRCNT_FAST_SHIFT 16u
1059 #define CAN_ECR_TXERRCNT_FAST_WIDTH 8u
1060 #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_FAST_SHIFT))&CAN_ECR_TXERRCNT_FAST_MASK)
1061 #define CAN_ECR_RXERRCNT_FAST_MASK 0xFF000000u
1062 #define CAN_ECR_RXERRCNT_FAST_SHIFT 24u
1063 #define CAN_ECR_RXERRCNT_FAST_WIDTH 8u
1064 #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_FAST_SHIFT))&CAN_ECR_RXERRCNT_FAST_MASK)
1065 /* ESR1 Bit Fields */
1066 #define CAN_ESR1_ERRINT_MASK 0x2u
1067 #define CAN_ESR1_ERRINT_SHIFT 1u
1068 #define CAN_ESR1_ERRINT_WIDTH 1u
1069 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
1070 #define CAN_ESR1_BOFFINT_MASK 0x4u
1071 #define CAN_ESR1_BOFFINT_SHIFT 2u
1072 #define CAN_ESR1_BOFFINT_WIDTH 1u
1073 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
1074 #define CAN_ESR1_RX_MASK 0x8u
1075 #define CAN_ESR1_RX_SHIFT 3u
1076 #define CAN_ESR1_RX_WIDTH 1u
1077 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
1078 #define CAN_ESR1_FLTCONF_MASK 0x30u
1079 #define CAN_ESR1_FLTCONF_SHIFT 4u
1080 #define CAN_ESR1_FLTCONF_WIDTH 2u
1081 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
1082 #define CAN_ESR1_TX_MASK 0x40u
1083 #define CAN_ESR1_TX_SHIFT 6u
1084 #define CAN_ESR1_TX_WIDTH 1u
1085 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
1086 #define CAN_ESR1_IDLE_MASK 0x80u
1087 #define CAN_ESR1_IDLE_SHIFT 7u
1088 #define CAN_ESR1_IDLE_WIDTH 1u
1089 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
1090 #define CAN_ESR1_RXWRN_MASK 0x100u
1091 #define CAN_ESR1_RXWRN_SHIFT 8u
1092 #define CAN_ESR1_RXWRN_WIDTH 1u
1093 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
1094 #define CAN_ESR1_TXWRN_MASK 0x200u
1095 #define CAN_ESR1_TXWRN_SHIFT 9u
1096 #define CAN_ESR1_TXWRN_WIDTH 1u
1097 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
1098 #define CAN_ESR1_STFERR_MASK 0x400u
1099 #define CAN_ESR1_STFERR_SHIFT 10u
1100 #define CAN_ESR1_STFERR_WIDTH 1u
1101 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
1102 #define CAN_ESR1_FRMERR_MASK 0x800u
1103 #define CAN_ESR1_FRMERR_SHIFT 11u
1104 #define CAN_ESR1_FRMERR_WIDTH 1u
1105 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
1106 #define CAN_ESR1_CRCERR_MASK 0x1000u
1107 #define CAN_ESR1_CRCERR_SHIFT 12u
1108 #define CAN_ESR1_CRCERR_WIDTH 1u
1109 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
1110 #define CAN_ESR1_ACKERR_MASK 0x2000u
1111 #define CAN_ESR1_ACKERR_SHIFT 13u
1112 #define CAN_ESR1_ACKERR_WIDTH 1u
1113 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
1114 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
1115 #define CAN_ESR1_BIT0ERR_SHIFT 14u
1116 #define CAN_ESR1_BIT0ERR_WIDTH 1u
1117 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
1118 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
1119 #define CAN_ESR1_BIT1ERR_SHIFT 15u
1120 #define CAN_ESR1_BIT1ERR_WIDTH 1u
1121 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
1122 #define CAN_ESR1_RWRNINT_MASK 0x10000u
1123 #define CAN_ESR1_RWRNINT_SHIFT 16u
1124 #define CAN_ESR1_RWRNINT_WIDTH 1u
1125 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
1126 #define CAN_ESR1_TWRNINT_MASK 0x20000u
1127 #define CAN_ESR1_TWRNINT_SHIFT 17u
1128 #define CAN_ESR1_TWRNINT_WIDTH 1u
1129 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
1130 #define CAN_ESR1_SYNCH_MASK 0x40000u
1131 #define CAN_ESR1_SYNCH_SHIFT 18u
1132 #define CAN_ESR1_SYNCH_WIDTH 1u
1133 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
1134 #define CAN_ESR1_BOFFDONEINT_MASK 0x80000u
1135 #define CAN_ESR1_BOFFDONEINT_SHIFT 19u
1136 #define CAN_ESR1_BOFFDONEINT_WIDTH 1u
1137 #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFDONEINT_SHIFT))&CAN_ESR1_BOFFDONEINT_MASK)
1138 #define CAN_ESR1_ERRINT_FAST_MASK 0x100000u
1139 #define CAN_ESR1_ERRINT_FAST_SHIFT 20u
1140 #define CAN_ESR1_ERRINT_FAST_WIDTH 1u
1141 #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_FAST_SHIFT))&CAN_ESR1_ERRINT_FAST_MASK)
1142 #define CAN_ESR1_ERROVR_MASK 0x200000u
1143 #define CAN_ESR1_ERROVR_SHIFT 21u
1144 #define CAN_ESR1_ERROVR_WIDTH 1u
1145 #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERROVR_SHIFT))&CAN_ESR1_ERROVR_MASK)
1146 #define CAN_ESR1_STFERR_FAST_MASK 0x4000000u
1147 #define CAN_ESR1_STFERR_FAST_SHIFT 26u
1148 #define CAN_ESR1_STFERR_FAST_WIDTH 1u
1149 #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_FAST_SHIFT))&CAN_ESR1_STFERR_FAST_MASK)
1150 #define CAN_ESR1_FRMERR_FAST_MASK 0x8000000u
1151 #define CAN_ESR1_FRMERR_FAST_SHIFT 27u
1152 #define CAN_ESR1_FRMERR_FAST_WIDTH 1u
1153 #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_FAST_SHIFT))&CAN_ESR1_FRMERR_FAST_MASK)
1154 #define CAN_ESR1_CRCERR_FAST_MASK 0x10000000u
1155 #define CAN_ESR1_CRCERR_FAST_SHIFT 28u
1156 #define CAN_ESR1_CRCERR_FAST_WIDTH 1u
1157 #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_FAST_SHIFT))&CAN_ESR1_CRCERR_FAST_MASK)
1158 #define CAN_ESR1_BIT0ERR_FAST_MASK 0x40000000u
1159 #define CAN_ESR1_BIT0ERR_FAST_SHIFT 30u
1160 #define CAN_ESR1_BIT0ERR_FAST_WIDTH 1u
1161 #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_FAST_SHIFT))&CAN_ESR1_BIT0ERR_FAST_MASK)
1162 #define CAN_ESR1_BIT1ERR_FAST_MASK 0x80000000u
1163 #define CAN_ESR1_BIT1ERR_FAST_SHIFT 31u
1164 #define CAN_ESR1_BIT1ERR_FAST_WIDTH 1u
1165 #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_FAST_SHIFT))&CAN_ESR1_BIT1ERR_FAST_MASK)
1166 /* IMASK1 Bit Fields */
1167 #define CAN_IMASK1_BUF31TO0M_MASK 0xFFFFFFFFu
1168 #define CAN_IMASK1_BUF31TO0M_SHIFT 0u
1169 #define CAN_IMASK1_BUF31TO0M_WIDTH 32u
1170 #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31TO0M_SHIFT))&CAN_IMASK1_BUF31TO0M_MASK)
1171 /* IFLAG1 Bit Fields */
1172 #define CAN_IFLAG1_BUF0I_MASK 0x1u
1173 #define CAN_IFLAG1_BUF0I_SHIFT 0u
1174 #define CAN_IFLAG1_BUF0I_WIDTH 1u
1175 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
1176 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
1177 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1u
1178 #define CAN_IFLAG1_BUF4TO1I_WIDTH 4u
1179 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
1180 #define CAN_IFLAG1_BUF5I_MASK 0x20u
1181 #define CAN_IFLAG1_BUF5I_SHIFT 5u
1182 #define CAN_IFLAG1_BUF5I_WIDTH 1u
1183 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
1184 #define CAN_IFLAG1_BUF6I_MASK 0x40u
1185 #define CAN_IFLAG1_BUF6I_SHIFT 6u
1186 #define CAN_IFLAG1_BUF6I_WIDTH 1u
1187 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
1188 #define CAN_IFLAG1_BUF7I_MASK 0x80u
1189 #define CAN_IFLAG1_BUF7I_SHIFT 7u
1190 #define CAN_IFLAG1_BUF7I_WIDTH 1u
1191 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
1192 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
1193 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8u
1194 #define CAN_IFLAG1_BUF31TO8I_WIDTH 24u
1195 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
1196 /* CTRL2 Bit Fields */
1197 #define CAN_CTRL2_EDFLTDIS_MASK 0x800u
1198 #define CAN_CTRL2_EDFLTDIS_SHIFT 11u
1199 #define CAN_CTRL2_EDFLTDIS_WIDTH 1u
1200 #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EDFLTDIS_SHIFT))&CAN_CTRL2_EDFLTDIS_MASK)
1201 #define CAN_CTRL2_ISOCANFDEN_MASK 0x1000u
1202 #define CAN_CTRL2_ISOCANFDEN_SHIFT 12u
1203 #define CAN_CTRL2_ISOCANFDEN_WIDTH 1u
1204 #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ISOCANFDEN_SHIFT))&CAN_CTRL2_ISOCANFDEN_MASK)
1205 #define CAN_CTRL2_PREXCEN_MASK 0x4000u
1206 #define CAN_CTRL2_PREXCEN_SHIFT 14u
1207 #define CAN_CTRL2_PREXCEN_WIDTH 1u
1208 #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PREXCEN_SHIFT))&CAN_CTRL2_PREXCEN_MASK)
1209 #define CAN_CTRL2_TIMER_SRC_MASK 0x8000u
1210 #define CAN_CTRL2_TIMER_SRC_SHIFT 15u
1211 #define CAN_CTRL2_TIMER_SRC_WIDTH 1u
1212 #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TIMER_SRC_SHIFT))&CAN_CTRL2_TIMER_SRC_MASK)
1213 #define CAN_CTRL2_EACEN_MASK 0x10000u
1214 #define CAN_CTRL2_EACEN_SHIFT 16u
1215 #define CAN_CTRL2_EACEN_WIDTH 1u
1216 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
1217 #define CAN_CTRL2_RRS_MASK 0x20000u
1218 #define CAN_CTRL2_RRS_SHIFT 17u
1219 #define CAN_CTRL2_RRS_WIDTH 1u
1220 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
1221 #define CAN_CTRL2_MRP_MASK 0x40000u
1222 #define CAN_CTRL2_MRP_SHIFT 18u
1223 #define CAN_CTRL2_MRP_WIDTH 1u
1224 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
1225 #define CAN_CTRL2_TASD_MASK 0xF80000u
1226 #define CAN_CTRL2_TASD_SHIFT 19u
1227 #define CAN_CTRL2_TASD_WIDTH 5u
1228 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
1229 #define CAN_CTRL2_RFFN_MASK 0xF000000u
1230 #define CAN_CTRL2_RFFN_SHIFT 24u
1231 #define CAN_CTRL2_RFFN_WIDTH 4u
1232 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
1233 #define CAN_CTRL2_BOFFDONEMSK_MASK 0x40000000u
1234 #define CAN_CTRL2_BOFFDONEMSK_SHIFT 30u
1235 #define CAN_CTRL2_BOFFDONEMSK_WIDTH 1u
1236 #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_BOFFDONEMSK_SHIFT))&CAN_CTRL2_BOFFDONEMSK_MASK)
1237 #define CAN_CTRL2_ERRMSK_FAST_MASK 0x80000000u
1238 #define CAN_CTRL2_ERRMSK_FAST_SHIFT 31u
1239 #define CAN_CTRL2_ERRMSK_FAST_WIDTH 1u
1240 #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ERRMSK_FAST_SHIFT))&CAN_CTRL2_ERRMSK_FAST_MASK)
1241 /* ESR2 Bit Fields */
1242 #define CAN_ESR2_IMB_MASK 0x2000u
1243 #define CAN_ESR2_IMB_SHIFT 13u
1244 #define CAN_ESR2_IMB_WIDTH 1u
1245 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
1246 #define CAN_ESR2_VPS_MASK 0x4000u
1247 #define CAN_ESR2_VPS_SHIFT 14u
1248 #define CAN_ESR2_VPS_WIDTH 1u
1249 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
1250 #define CAN_ESR2_LPTM_MASK 0x7F0000u
1251 #define CAN_ESR2_LPTM_SHIFT 16u
1252 #define CAN_ESR2_LPTM_WIDTH 7u
1253 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
1254 /* CRCR Bit Fields */
1255 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
1256 #define CAN_CRCR_TXCRC_SHIFT 0u
1257 #define CAN_CRCR_TXCRC_WIDTH 15u
1258 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
1259 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
1260 #define CAN_CRCR_MBCRC_SHIFT 16u
1261 #define CAN_CRCR_MBCRC_WIDTH 7u
1262 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
1263 /* RXFGMASK Bit Fields */
1264 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
1265 #define CAN_RXFGMASK_FGM_SHIFT 0u
1266 #define CAN_RXFGMASK_FGM_WIDTH 32u
1267 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
1268 /* RXFIR Bit Fields */
1269 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
1270 #define CAN_RXFIR_IDHIT_SHIFT 0u
1271 #define CAN_RXFIR_IDHIT_WIDTH 9u
1272 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
1273 /* CBT Bit Fields */
1274 #define CAN_CBT_EPSEG2_MASK 0x1Fu
1275 #define CAN_CBT_EPSEG2_SHIFT 0u
1276 #define CAN_CBT_EPSEG2_WIDTH 5u
1277 #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG2_SHIFT))&CAN_CBT_EPSEG2_MASK)
1278 #define CAN_CBT_EPSEG1_MASK 0x3E0u
1279 #define CAN_CBT_EPSEG1_SHIFT 5u
1280 #define CAN_CBT_EPSEG1_WIDTH 5u
1281 #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG1_SHIFT))&CAN_CBT_EPSEG1_MASK)
1282 #define CAN_CBT_EPROPSEG_MASK 0xFC00u
1283 #define CAN_CBT_EPROPSEG_SHIFT 10u
1284 #define CAN_CBT_EPROPSEG_WIDTH 6u
1285 #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPROPSEG_SHIFT))&CAN_CBT_EPROPSEG_MASK)
1286 #define CAN_CBT_ERJW_MASK 0x1F0000u
1287 #define CAN_CBT_ERJW_SHIFT 16u
1288 #define CAN_CBT_ERJW_WIDTH 5u
1289 #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_ERJW_SHIFT))&CAN_CBT_ERJW_MASK)
1290 #define CAN_CBT_EPRESDIV_MASK 0x7FE00000u
1291 #define CAN_CBT_EPRESDIV_SHIFT 21u
1292 #define CAN_CBT_EPRESDIV_WIDTH 10u
1293 #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPRESDIV_SHIFT))&CAN_CBT_EPRESDIV_MASK)
1294 #define CAN_CBT_BTF_MASK 0x80000000u
1295 #define CAN_CBT_BTF_SHIFT 31u
1296 #define CAN_CBT_BTF_WIDTH 1u
1297 #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_BTF_SHIFT))&CAN_CBT_BTF_MASK)
1298 /* RAMn Bit Fields */
1299 #define CAN_RAMn_DATA_BYTE_3_MASK 0xFFu
1300 #define CAN_RAMn_DATA_BYTE_3_SHIFT 0u
1301 #define CAN_RAMn_DATA_BYTE_3_WIDTH 8u
1302 #define CAN_RAMn_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_3_SHIFT))&CAN_RAMn_DATA_BYTE_3_MASK)
1303 #define CAN_RAMn_DATA_BYTE_2_MASK 0xFF00u
1304 #define CAN_RAMn_DATA_BYTE_2_SHIFT 8u
1305 #define CAN_RAMn_DATA_BYTE_2_WIDTH 8u
1306 #define CAN_RAMn_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_2_SHIFT))&CAN_RAMn_DATA_BYTE_2_MASK)
1307 #define CAN_RAMn_DATA_BYTE_1_MASK 0xFF0000u
1308 #define CAN_RAMn_DATA_BYTE_1_SHIFT 16u
1309 #define CAN_RAMn_DATA_BYTE_1_WIDTH 8u
1310 #define CAN_RAMn_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_1_SHIFT))&CAN_RAMn_DATA_BYTE_1_MASK)
1311 #define CAN_RAMn_DATA_BYTE_0_MASK 0xFF000000u
1312 #define CAN_RAMn_DATA_BYTE_0_SHIFT 24u
1313 #define CAN_RAMn_DATA_BYTE_0_WIDTH 8u
1314 #define CAN_RAMn_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_0_SHIFT))&CAN_RAMn_DATA_BYTE_0_MASK)
1315 /* RXIMR Bit Fields */
1316 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
1317 #define CAN_RXIMR_MI_SHIFT 0u
1318 #define CAN_RXIMR_MI_WIDTH 32u
1319 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
1320 /* CTRL1_PN Bit Fields */
1321 #define CAN_CTRL1_PN_FCS_MASK 0x3u
1322 #define CAN_CTRL1_PN_FCS_SHIFT 0u
1323 #define CAN_CTRL1_PN_FCS_WIDTH 2u
1324 #define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_FCS_SHIFT))&CAN_CTRL1_PN_FCS_MASK)
1325 #define CAN_CTRL1_PN_IDFS_MASK 0xCu
1326 #define CAN_CTRL1_PN_IDFS_SHIFT 2u
1327 #define CAN_CTRL1_PN_IDFS_WIDTH 2u
1328 #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_IDFS_SHIFT))&CAN_CTRL1_PN_IDFS_MASK)
1329 #define CAN_CTRL1_PN_PLFS_MASK 0x30u
1330 #define CAN_CTRL1_PN_PLFS_SHIFT 4u
1331 #define CAN_CTRL1_PN_PLFS_WIDTH 2u
1332 #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_PLFS_SHIFT))&CAN_CTRL1_PN_PLFS_MASK)
1333 #define CAN_CTRL1_PN_NMATCH_MASK 0xFF00u
1334 #define CAN_CTRL1_PN_NMATCH_SHIFT 8u
1335 #define CAN_CTRL1_PN_NMATCH_WIDTH 8u
1336 #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_NMATCH_SHIFT))&CAN_CTRL1_PN_NMATCH_MASK)
1337 #define CAN_CTRL1_PN_WUMF_MSK_MASK 0x10000u
1338 #define CAN_CTRL1_PN_WUMF_MSK_SHIFT 16u
1339 #define CAN_CTRL1_PN_WUMF_MSK_WIDTH 1u
1340 #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WUMF_MSK_SHIFT))&CAN_CTRL1_PN_WUMF_MSK_MASK)
1341 #define CAN_CTRL1_PN_WTOF_MSK_MASK 0x20000u
1342 #define CAN_CTRL1_PN_WTOF_MSK_SHIFT 17u
1343 #define CAN_CTRL1_PN_WTOF_MSK_WIDTH 1u
1344 #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WTOF_MSK_SHIFT))&CAN_CTRL1_PN_WTOF_MSK_MASK)
1345 /* CTRL2_PN Bit Fields */
1346 #define CAN_CTRL2_PN_MATCHTO_MASK 0xFFFFu
1347 #define CAN_CTRL2_PN_MATCHTO_SHIFT 0u
1348 #define CAN_CTRL2_PN_MATCHTO_WIDTH 16u
1349 #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PN_MATCHTO_SHIFT))&CAN_CTRL2_PN_MATCHTO_MASK)
1350 /* WU_MTC Bit Fields */
1351 #define CAN_WU_MTC_MCOUNTER_MASK 0xFF00u
1352 #define CAN_WU_MTC_MCOUNTER_SHIFT 8u
1353 #define CAN_WU_MTC_MCOUNTER_WIDTH 8u
1354 #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_MCOUNTER_SHIFT))&CAN_WU_MTC_MCOUNTER_MASK)
1355 #define CAN_WU_MTC_WUMF_MASK 0x10000u
1356 #define CAN_WU_MTC_WUMF_SHIFT 16u
1357 #define CAN_WU_MTC_WUMF_WIDTH 1u
1358 #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WUMF_SHIFT))&CAN_WU_MTC_WUMF_MASK)
1359 #define CAN_WU_MTC_WTOF_MASK 0x20000u
1360 #define CAN_WU_MTC_WTOF_SHIFT 17u
1361 #define CAN_WU_MTC_WTOF_WIDTH 1u
1362 #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WTOF_SHIFT))&CAN_WU_MTC_WTOF_MASK)
1363 /* FLT_ID1 Bit Fields */
1364 #define CAN_FLT_ID1_FLT_ID1_MASK 0x1FFFFFFFu
1365 #define CAN_FLT_ID1_FLT_ID1_SHIFT 0u
1366 #define CAN_FLT_ID1_FLT_ID1_WIDTH 29u
1367 #define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_ID1_SHIFT))&CAN_FLT_ID1_FLT_ID1_MASK)
1368 #define CAN_FLT_ID1_FLT_RTR_MASK 0x20000000u
1369 #define CAN_FLT_ID1_FLT_RTR_SHIFT 29u
1370 #define CAN_FLT_ID1_FLT_RTR_WIDTH 1u
1371 #define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_RTR_SHIFT))&CAN_FLT_ID1_FLT_RTR_MASK)
1372 #define CAN_FLT_ID1_FLT_IDE_MASK 0x40000000u
1373 #define CAN_FLT_ID1_FLT_IDE_SHIFT 30u
1374 #define CAN_FLT_ID1_FLT_IDE_WIDTH 1u
1375 #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_IDE_SHIFT))&CAN_FLT_ID1_FLT_IDE_MASK)
1376 /* FLT_DLC Bit Fields */
1377 #define CAN_FLT_DLC_FLT_DLC_HI_MASK 0xFu
1378 #define CAN_FLT_DLC_FLT_DLC_HI_SHIFT 0u
1379 #define CAN_FLT_DLC_FLT_DLC_HI_WIDTH 4u
1380 #define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_HI_SHIFT))&CAN_FLT_DLC_FLT_DLC_HI_MASK)
1381 #define CAN_FLT_DLC_FLT_DLC_LO_MASK 0xF0000u
1382 #define CAN_FLT_DLC_FLT_DLC_LO_SHIFT 16u
1383 #define CAN_FLT_DLC_FLT_DLC_LO_WIDTH 4u
1384 #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_LO_SHIFT))&CAN_FLT_DLC_FLT_DLC_LO_MASK)
1385 /* PL1_LO Bit Fields */
1386 #define CAN_PL1_LO_Data_byte_3_MASK 0xFFu
1387 #define CAN_PL1_LO_Data_byte_3_SHIFT 0u
1388 #define CAN_PL1_LO_Data_byte_3_WIDTH 8u
1389 #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_3_SHIFT))&CAN_PL1_LO_Data_byte_3_MASK)
1390 #define CAN_PL1_LO_Data_byte_2_MASK 0xFF00u
1391 #define CAN_PL1_LO_Data_byte_2_SHIFT 8u
1392 #define CAN_PL1_LO_Data_byte_2_WIDTH 8u
1393 #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_2_SHIFT))&CAN_PL1_LO_Data_byte_2_MASK)
1394 #define CAN_PL1_LO_Data_byte_1_MASK 0xFF0000u
1395 #define CAN_PL1_LO_Data_byte_1_SHIFT 16u
1396 #define CAN_PL1_LO_Data_byte_1_WIDTH 8u
1397 #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_1_SHIFT))&CAN_PL1_LO_Data_byte_1_MASK)
1398 #define CAN_PL1_LO_Data_byte_0_MASK 0xFF000000u
1399 #define CAN_PL1_LO_Data_byte_0_SHIFT 24u
1400 #define CAN_PL1_LO_Data_byte_0_WIDTH 8u
1401 #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_0_SHIFT))&CAN_PL1_LO_Data_byte_0_MASK)
1402 /* PL1_HI Bit Fields */
1403 #define CAN_PL1_HI_Data_byte_7_MASK 0xFFu
1404 #define CAN_PL1_HI_Data_byte_7_SHIFT 0u
1405 #define CAN_PL1_HI_Data_byte_7_WIDTH 8u
1406 #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_7_SHIFT))&CAN_PL1_HI_Data_byte_7_MASK)
1407 #define CAN_PL1_HI_Data_byte_6_MASK 0xFF00u
1408 #define CAN_PL1_HI_Data_byte_6_SHIFT 8u
1409 #define CAN_PL1_HI_Data_byte_6_WIDTH 8u
1410 #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_6_SHIFT))&CAN_PL1_HI_Data_byte_6_MASK)
1411 #define CAN_PL1_HI_Data_byte_5_MASK 0xFF0000u
1412 #define CAN_PL1_HI_Data_byte_5_SHIFT 16u
1413 #define CAN_PL1_HI_Data_byte_5_WIDTH 8u
1414 #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_5_SHIFT))&CAN_PL1_HI_Data_byte_5_MASK)
1415 #define CAN_PL1_HI_Data_byte_4_MASK 0xFF000000u
1416 #define CAN_PL1_HI_Data_byte_4_SHIFT 24u
1417 #define CAN_PL1_HI_Data_byte_4_WIDTH 8u
1418 #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_4_SHIFT))&CAN_PL1_HI_Data_byte_4_MASK)
1419 /* FLT_ID2_IDMASK Bit Fields */
1420 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK 0x1FFFFFFFu
1421 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT 0u
1422 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_WIDTH 29u
1423 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT))&CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)
1424 #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK 0x20000000u
1425 #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT 29u
1426 #define CAN_FLT_ID2_IDMASK_RTR_MSK_WIDTH 1u
1427 #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)
1428 #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK 0x40000000u
1429 #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT 30u
1430 #define CAN_FLT_ID2_IDMASK_IDE_MSK_WIDTH 1u
1431 #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
1432 /* PL2_PLMASK_LO Bit Fields */
1433 #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK 0xFFu
1434 #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT 0u
1435 #define CAN_PL2_PLMASK_LO_Data_byte_3_WIDTH 8u
1436 #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_3_MASK)
1437 #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK 0xFF00u
1438 #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT 8u
1439 #define CAN_PL2_PLMASK_LO_Data_byte_2_WIDTH 8u
1440 #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_2_MASK)
1441 #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK 0xFF0000u
1442 #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT 16u
1443 #define CAN_PL2_PLMASK_LO_Data_byte_1_WIDTH 8u
1444 #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_1_MASK)
1445 #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK 0xFF000000u
1446 #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT 24u
1447 #define CAN_PL2_PLMASK_LO_Data_byte_0_WIDTH 8u
1448 #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
1449 /* PL2_PLMASK_HI Bit Fields */
1450 #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK 0xFFu
1451 #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT 0u
1452 #define CAN_PL2_PLMASK_HI_Data_byte_7_WIDTH 8u
1453 #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_7_MASK)
1454 #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK 0xFF00u
1455 #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT 8u
1456 #define CAN_PL2_PLMASK_HI_Data_byte_6_WIDTH 8u
1457 #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_6_MASK)
1458 #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK 0xFF0000u
1459 #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT 16u
1460 #define CAN_PL2_PLMASK_HI_Data_byte_5_WIDTH 8u
1461 #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_5_MASK)
1462 #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK 0xFF000000u
1463 #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT 24u
1464 #define CAN_PL2_PLMASK_HI_Data_byte_4_WIDTH 8u
1465 #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
1466 /* WMBn_CS Bit Fields */
1467 #define CAN_WMBn_CS_DLC_MASK 0xF0000u
1468 #define CAN_WMBn_CS_DLC_SHIFT 16u
1469 #define CAN_WMBn_CS_DLC_WIDTH 4u
1470 #define CAN_WMBn_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_DLC_SHIFT))&CAN_WMBn_CS_DLC_MASK)
1471 #define CAN_WMBn_CS_RTR_MASK 0x100000u
1472 #define CAN_WMBn_CS_RTR_SHIFT 20u
1473 #define CAN_WMBn_CS_RTR_WIDTH 1u
1474 #define CAN_WMBn_CS_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_RTR_SHIFT))&CAN_WMBn_CS_RTR_MASK)
1475 #define CAN_WMBn_CS_IDE_MASK 0x200000u
1476 #define CAN_WMBn_CS_IDE_SHIFT 21u
1477 #define CAN_WMBn_CS_IDE_WIDTH 1u
1478 #define CAN_WMBn_CS_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_IDE_SHIFT))&CAN_WMBn_CS_IDE_MASK)
1479 #define CAN_WMBn_CS_SRR_MASK 0x400000u
1480 #define CAN_WMBn_CS_SRR_SHIFT 22u
1481 #define CAN_WMBn_CS_SRR_WIDTH 1u
1482 #define CAN_WMBn_CS_SRR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_SRR_SHIFT))&CAN_WMBn_CS_SRR_MASK)
1483 /* WMBn_ID Bit Fields */
1484 #define CAN_WMBn_ID_ID_MASK 0x1FFFFFFFu
1485 #define CAN_WMBn_ID_ID_SHIFT 0u
1486 #define CAN_WMBn_ID_ID_WIDTH 29u
1487 #define CAN_WMBn_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_ID_ID_SHIFT))&CAN_WMBn_ID_ID_MASK)
1488 /* WMBn_D03 Bit Fields */
1489 #define CAN_WMBn_D03_Data_byte_3_MASK 0xFFu
1490 #define CAN_WMBn_D03_Data_byte_3_SHIFT 0u
1491 #define CAN_WMBn_D03_Data_byte_3_WIDTH 8u
1492 #define CAN_WMBn_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_3_SHIFT))&CAN_WMBn_D03_Data_byte_3_MASK)
1493 #define CAN_WMBn_D03_Data_byte_2_MASK 0xFF00u
1494 #define CAN_WMBn_D03_Data_byte_2_SHIFT 8u
1495 #define CAN_WMBn_D03_Data_byte_2_WIDTH 8u
1496 #define CAN_WMBn_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_2_SHIFT))&CAN_WMBn_D03_Data_byte_2_MASK)
1497 #define CAN_WMBn_D03_Data_byte_1_MASK 0xFF0000u
1498 #define CAN_WMBn_D03_Data_byte_1_SHIFT 16u
1499 #define CAN_WMBn_D03_Data_byte_1_WIDTH 8u
1500 #define CAN_WMBn_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_1_SHIFT))&CAN_WMBn_D03_Data_byte_1_MASK)
1501 #define CAN_WMBn_D03_Data_byte_0_MASK 0xFF000000u
1502 #define CAN_WMBn_D03_Data_byte_0_SHIFT 24u
1503 #define CAN_WMBn_D03_Data_byte_0_WIDTH 8u
1504 #define CAN_WMBn_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_0_SHIFT))&CAN_WMBn_D03_Data_byte_0_MASK)
1505 /* WMBn_D47 Bit Fields */
1506 #define CAN_WMBn_D47_Data_byte_7_MASK 0xFFu
1507 #define CAN_WMBn_D47_Data_byte_7_SHIFT 0u
1508 #define CAN_WMBn_D47_Data_byte_7_WIDTH 8u
1509 #define CAN_WMBn_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_7_SHIFT))&CAN_WMBn_D47_Data_byte_7_MASK)
1510 #define CAN_WMBn_D47_Data_byte_6_MASK 0xFF00u
1511 #define CAN_WMBn_D47_Data_byte_6_SHIFT 8u
1512 #define CAN_WMBn_D47_Data_byte_6_WIDTH 8u
1513 #define CAN_WMBn_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_6_SHIFT))&CAN_WMBn_D47_Data_byte_6_MASK)
1514 #define CAN_WMBn_D47_Data_byte_5_MASK 0xFF0000u
1515 #define CAN_WMBn_D47_Data_byte_5_SHIFT 16u
1516 #define CAN_WMBn_D47_Data_byte_5_WIDTH 8u
1517 #define CAN_WMBn_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_5_SHIFT))&CAN_WMBn_D47_Data_byte_5_MASK)
1518 #define CAN_WMBn_D47_Data_byte_4_MASK 0xFF000000u
1519 #define CAN_WMBn_D47_Data_byte_4_SHIFT 24u
1520 #define CAN_WMBn_D47_Data_byte_4_WIDTH 8u
1521 #define CAN_WMBn_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_4_SHIFT))&CAN_WMBn_D47_Data_byte_4_MASK)
1522 /* FDCTRL Bit Fields */
1523 #define CAN_FDCTRL_TDCVAL_MASK 0x3Fu
1524 #define CAN_FDCTRL_TDCVAL_SHIFT 0u
1525 #define CAN_FDCTRL_TDCVAL_WIDTH 6u
1526 #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCVAL_SHIFT))&CAN_FDCTRL_TDCVAL_MASK)
1527 #define CAN_FDCTRL_TDCOFF_MASK 0x1F00u
1528 #define CAN_FDCTRL_TDCOFF_SHIFT 8u
1529 #define CAN_FDCTRL_TDCOFF_WIDTH 5u
1530 #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCOFF_SHIFT))&CAN_FDCTRL_TDCOFF_MASK)
1531 #define CAN_FDCTRL_TDCFAIL_MASK 0x4000u
1532 #define CAN_FDCTRL_TDCFAIL_SHIFT 14u
1533 #define CAN_FDCTRL_TDCFAIL_WIDTH 1u
1534 #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCFAIL_SHIFT))&CAN_FDCTRL_TDCFAIL_MASK)
1535 #define CAN_FDCTRL_TDCEN_MASK 0x8000u
1536 #define CAN_FDCTRL_TDCEN_SHIFT 15u
1537 #define CAN_FDCTRL_TDCEN_WIDTH 1u
1538 #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCEN_SHIFT))&CAN_FDCTRL_TDCEN_MASK)
1539 #define CAN_FDCTRL_MBDSR0_MASK 0x30000u
1540 #define CAN_FDCTRL_MBDSR0_SHIFT 16u
1541 #define CAN_FDCTRL_MBDSR0_WIDTH 2u
1542 #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_MBDSR0_SHIFT))&CAN_FDCTRL_MBDSR0_MASK)
1543 #define CAN_FDCTRL_FDRATE_MASK 0x80000000u
1544 #define CAN_FDCTRL_FDRATE_SHIFT 31u
1545 #define CAN_FDCTRL_FDRATE_WIDTH 1u
1546 #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_FDRATE_SHIFT))&CAN_FDCTRL_FDRATE_MASK)
1547 /* FDCBT Bit Fields */
1548 #define CAN_FDCBT_FPSEG2_MASK 0x7u
1549 #define CAN_FDCBT_FPSEG2_SHIFT 0u
1550 #define CAN_FDCBT_FPSEG2_WIDTH 3u
1551 #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG2_SHIFT))&CAN_FDCBT_FPSEG2_MASK)
1552 #define CAN_FDCBT_FPSEG1_MASK 0xE0u
1553 #define CAN_FDCBT_FPSEG1_SHIFT 5u
1554 #define CAN_FDCBT_FPSEG1_WIDTH 3u
1555 #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG1_SHIFT))&CAN_FDCBT_FPSEG1_MASK)
1556 #define CAN_FDCBT_FPROPSEG_MASK 0x7C00u
1557 #define CAN_FDCBT_FPROPSEG_SHIFT 10u
1558 #define CAN_FDCBT_FPROPSEG_WIDTH 5u
1559 #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPROPSEG_SHIFT))&CAN_FDCBT_FPROPSEG_MASK)
1560 #define CAN_FDCBT_FRJW_MASK 0x70000u
1561 #define CAN_FDCBT_FRJW_SHIFT 16u
1562 #define CAN_FDCBT_FRJW_WIDTH 3u
1563 #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FRJW_SHIFT))&CAN_FDCBT_FRJW_MASK)
1564 #define CAN_FDCBT_FPRESDIV_MASK 0x3FF00000u
1565 #define CAN_FDCBT_FPRESDIV_SHIFT 20u
1566 #define CAN_FDCBT_FPRESDIV_WIDTH 10u
1567 #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPRESDIV_SHIFT))&CAN_FDCBT_FPRESDIV_MASK)
1568 /* FDCRC Bit Fields */
1569 #define CAN_FDCRC_FD_TXCRC_MASK 0x1FFFFFu
1570 #define CAN_FDCRC_FD_TXCRC_SHIFT 0u
1571 #define CAN_FDCRC_FD_TXCRC_WIDTH 21u
1572 #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_TXCRC_SHIFT))&CAN_FDCRC_FD_TXCRC_MASK)
1573 #define CAN_FDCRC_FD_MBCRC_MASK 0x7F000000u
1574 #define CAN_FDCRC_FD_MBCRC_SHIFT 24u
1575 #define CAN_FDCRC_FD_MBCRC_WIDTH 7u
1576 #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_MBCRC_SHIFT))&CAN_FDCRC_FD_MBCRC_MASK)
1577  /* end of group CAN_Register_Masks */
1581 
1582  /* end of group CAN_Peripheral_Access_Layer */
1586 
1587 
1588 /* ----------------------------------------------------------------------------
1589  -- CMP Peripheral Access Layer
1590  ---------------------------------------------------------------------------- */
1591 
1601 typedef struct {
1602  __IO uint32_t C0;
1603  __IO uint32_t C1;
1604  __IO uint32_t C2;
1606 
1608 #define CMP_INSTANCE_COUNT (1u)
1609 
1610 
1611 /* CMP - Peripheral instance base addresses */
1613 #define CMP0_BASE (0x40073000u)
1614 
1615 #define CMP0 ((CMP_Type *)CMP0_BASE)
1616 
1617 #define CMP_BASE_ADDRS { CMP0_BASE }
1618 
1619 #define CMP_BASE_PTRS { CMP0 }
1620 
1621 #define CMP_IRQS_ARR_COUNT (1u)
1622 
1623 #define CMP_IRQS_CH_COUNT (1u)
1624 
1625 #define CMP_IRQS { CMP0_IRQn }
1626 
1627 /* ----------------------------------------------------------------------------
1628  -- CMP Register Masks
1629  ---------------------------------------------------------------------------- */
1630 
1636 /* C0 Bit Fields */
1637 #define CMP_C0_HYSTCTR_MASK 0x3u
1638 #define CMP_C0_HYSTCTR_SHIFT 0u
1639 #define CMP_C0_HYSTCTR_WIDTH 2u
1640 #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_HYSTCTR_SHIFT))&CMP_C0_HYSTCTR_MASK)
1641 #define CMP_C0_OFFSET_MASK 0x4u
1642 #define CMP_C0_OFFSET_SHIFT 2u
1643 #define CMP_C0_OFFSET_WIDTH 1u
1644 #define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OFFSET_SHIFT))&CMP_C0_OFFSET_MASK)
1645 #define CMP_C0_FILTER_CNT_MASK 0x70u
1646 #define CMP_C0_FILTER_CNT_SHIFT 4u
1647 #define CMP_C0_FILTER_CNT_WIDTH 3u
1648 #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FILTER_CNT_SHIFT))&CMP_C0_FILTER_CNT_MASK)
1649 #define CMP_C0_EN_MASK 0x100u
1650 #define CMP_C0_EN_SHIFT 8u
1651 #define CMP_C0_EN_WIDTH 1u
1652 #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_EN_SHIFT))&CMP_C0_EN_MASK)
1653 #define CMP_C0_OPE_MASK 0x200u
1654 #define CMP_C0_OPE_SHIFT 9u
1655 #define CMP_C0_OPE_WIDTH 1u
1656 #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OPE_SHIFT))&CMP_C0_OPE_MASK)
1657 #define CMP_C0_COS_MASK 0x400u
1658 #define CMP_C0_COS_SHIFT 10u
1659 #define CMP_C0_COS_WIDTH 1u
1660 #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COS_SHIFT))&CMP_C0_COS_MASK)
1661 #define CMP_C0_INVT_MASK 0x800u
1662 #define CMP_C0_INVT_SHIFT 11u
1663 #define CMP_C0_INVT_WIDTH 1u
1664 #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_INVT_SHIFT))&CMP_C0_INVT_MASK)
1665 #define CMP_C0_PMODE_MASK 0x1000u
1666 #define CMP_C0_PMODE_SHIFT 12u
1667 #define CMP_C0_PMODE_WIDTH 1u
1668 #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_PMODE_SHIFT))&CMP_C0_PMODE_MASK)
1669 #define CMP_C0_WE_MASK 0x4000u
1670 #define CMP_C0_WE_SHIFT 14u
1671 #define CMP_C0_WE_WIDTH 1u
1672 #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_WE_SHIFT))&CMP_C0_WE_MASK)
1673 #define CMP_C0_SE_MASK 0x8000u
1674 #define CMP_C0_SE_SHIFT 15u
1675 #define CMP_C0_SE_WIDTH 1u
1676 #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_SE_SHIFT))&CMP_C0_SE_MASK)
1677 #define CMP_C0_FPR_MASK 0xFF0000u
1678 #define CMP_C0_FPR_SHIFT 16u
1679 #define CMP_C0_FPR_WIDTH 8u
1680 #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FPR_SHIFT))&CMP_C0_FPR_MASK)
1681 #define CMP_C0_COUT_MASK 0x1000000u
1682 #define CMP_C0_COUT_SHIFT 24u
1683 #define CMP_C0_COUT_WIDTH 1u
1684 #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COUT_SHIFT))&CMP_C0_COUT_MASK)
1685 #define CMP_C0_CFF_MASK 0x2000000u
1686 #define CMP_C0_CFF_SHIFT 25u
1687 #define CMP_C0_CFF_WIDTH 1u
1688 #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFF_SHIFT))&CMP_C0_CFF_MASK)
1689 #define CMP_C0_CFR_MASK 0x4000000u
1690 #define CMP_C0_CFR_SHIFT 26u
1691 #define CMP_C0_CFR_WIDTH 1u
1692 #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFR_SHIFT))&CMP_C0_CFR_MASK)
1693 #define CMP_C0_IEF_MASK 0x8000000u
1694 #define CMP_C0_IEF_SHIFT 27u
1695 #define CMP_C0_IEF_WIDTH 1u
1696 #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IEF_SHIFT))&CMP_C0_IEF_MASK)
1697 #define CMP_C0_IER_MASK 0x10000000u
1698 #define CMP_C0_IER_SHIFT 28u
1699 #define CMP_C0_IER_WIDTH 1u
1700 #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IER_SHIFT))&CMP_C0_IER_MASK)
1701 #define CMP_C0_DMAEN_MASK 0x40000000u
1702 #define CMP_C0_DMAEN_SHIFT 30u
1703 #define CMP_C0_DMAEN_WIDTH 1u
1704 #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_DMAEN_SHIFT))&CMP_C0_DMAEN_MASK)
1705 /* C1 Bit Fields */
1706 #define CMP_C1_VOSEL_MASK 0xFFu
1707 #define CMP_C1_VOSEL_SHIFT 0u
1708 #define CMP_C1_VOSEL_WIDTH 8u
1709 #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VOSEL_SHIFT))&CMP_C1_VOSEL_MASK)
1710 #define CMP_C1_MSEL_MASK 0x700u
1711 #define CMP_C1_MSEL_SHIFT 8u
1712 #define CMP_C1_MSEL_WIDTH 3u
1713 #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_MSEL_SHIFT))&CMP_C1_MSEL_MASK)
1714 #define CMP_C1_PSEL_MASK 0x3800u
1715 #define CMP_C1_PSEL_SHIFT 11u
1716 #define CMP_C1_PSEL_WIDTH 3u
1717 #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_PSEL_SHIFT))&CMP_C1_PSEL_MASK)
1718 #define CMP_C1_VRSEL_MASK 0x4000u
1719 #define CMP_C1_VRSEL_SHIFT 14u
1720 #define CMP_C1_VRSEL_WIDTH 1u
1721 #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VRSEL_SHIFT))&CMP_C1_VRSEL_MASK)
1722 #define CMP_C1_DACEN_MASK 0x8000u
1723 #define CMP_C1_DACEN_SHIFT 15u
1724 #define CMP_C1_DACEN_WIDTH 1u
1725 #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_DACEN_SHIFT))&CMP_C1_DACEN_MASK)
1726 #define CMP_C1_CHN0_MASK 0x10000u
1727 #define CMP_C1_CHN0_SHIFT 16u
1728 #define CMP_C1_CHN0_WIDTH 1u
1729 #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN0_SHIFT))&CMP_C1_CHN0_MASK)
1730 #define CMP_C1_CHN1_MASK 0x20000u
1731 #define CMP_C1_CHN1_SHIFT 17u
1732 #define CMP_C1_CHN1_WIDTH 1u
1733 #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN1_SHIFT))&CMP_C1_CHN1_MASK)
1734 #define CMP_C1_CHN2_MASK 0x40000u
1735 #define CMP_C1_CHN2_SHIFT 18u
1736 #define CMP_C1_CHN2_WIDTH 1u
1737 #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN2_SHIFT))&CMP_C1_CHN2_MASK)
1738 #define CMP_C1_CHN3_MASK 0x80000u
1739 #define CMP_C1_CHN3_SHIFT 19u
1740 #define CMP_C1_CHN3_WIDTH 1u
1741 #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN3_SHIFT))&CMP_C1_CHN3_MASK)
1742 #define CMP_C1_CHN4_MASK 0x100000u
1743 #define CMP_C1_CHN4_SHIFT 20u
1744 #define CMP_C1_CHN4_WIDTH 1u
1745 #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN4_SHIFT))&CMP_C1_CHN4_MASK)
1746 #define CMP_C1_CHN5_MASK 0x200000u
1747 #define CMP_C1_CHN5_SHIFT 21u
1748 #define CMP_C1_CHN5_WIDTH 1u
1749 #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN5_SHIFT))&CMP_C1_CHN5_MASK)
1750 #define CMP_C1_CHN6_MASK 0x400000u
1751 #define CMP_C1_CHN6_SHIFT 22u
1752 #define CMP_C1_CHN6_WIDTH 1u
1753 #define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN6_SHIFT))&CMP_C1_CHN6_MASK)
1754 #define CMP_C1_CHN7_MASK 0x800000u
1755 #define CMP_C1_CHN7_SHIFT 23u
1756 #define CMP_C1_CHN7_WIDTH 1u
1757 #define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN7_SHIFT))&CMP_C1_CHN7_MASK)
1758 #define CMP_C1_INNSEL_MASK 0x3000000u
1759 #define CMP_C1_INNSEL_SHIFT 24u
1760 #define CMP_C1_INNSEL_WIDTH 2u
1761 #define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INNSEL_SHIFT))&CMP_C1_INNSEL_MASK)
1762 #define CMP_C1_INPSEL_MASK 0x18000000u
1763 #define CMP_C1_INPSEL_SHIFT 27u
1764 #define CMP_C1_INPSEL_WIDTH 2u
1765 #define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INPSEL_SHIFT))&CMP_C1_INPSEL_MASK)
1766 /* C2 Bit Fields */
1767 #define CMP_C2_ACOn_MASK 0xFFu
1768 #define CMP_C2_ACOn_SHIFT 0u
1769 #define CMP_C2_ACOn_WIDTH 8u
1770 #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_ACOn_SHIFT))&CMP_C2_ACOn_MASK)
1771 #define CMP_C2_INITMOD_MASK 0x3F00u
1772 #define CMP_C2_INITMOD_SHIFT 8u
1773 #define CMP_C2_INITMOD_WIDTH 6u
1774 #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_INITMOD_SHIFT))&CMP_C2_INITMOD_MASK)
1775 #define CMP_C2_NSAM_MASK 0xC000u
1776 #define CMP_C2_NSAM_SHIFT 14u
1777 #define CMP_C2_NSAM_WIDTH 2u
1778 #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_NSAM_SHIFT))&CMP_C2_NSAM_MASK)
1779 #define CMP_C2_CH0F_MASK 0x10000u
1780 #define CMP_C2_CH0F_SHIFT 16u
1781 #define CMP_C2_CH0F_WIDTH 1u
1782 #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH0F_SHIFT))&CMP_C2_CH0F_MASK)
1783 #define CMP_C2_CH1F_MASK 0x20000u
1784 #define CMP_C2_CH1F_SHIFT 17u
1785 #define CMP_C2_CH1F_WIDTH 1u
1786 #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH1F_SHIFT))&CMP_C2_CH1F_MASK)
1787 #define CMP_C2_CH2F_MASK 0x40000u
1788 #define CMP_C2_CH2F_SHIFT 18u
1789 #define CMP_C2_CH2F_WIDTH 1u
1790 #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH2F_SHIFT))&CMP_C2_CH2F_MASK)
1791 #define CMP_C2_CH3F_MASK 0x80000u
1792 #define CMP_C2_CH3F_SHIFT 19u
1793 #define CMP_C2_CH3F_WIDTH 1u
1794 #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH3F_SHIFT))&CMP_C2_CH3F_MASK)
1795 #define CMP_C2_CH4F_MASK 0x100000u
1796 #define CMP_C2_CH4F_SHIFT 20u
1797 #define CMP_C2_CH4F_WIDTH 1u
1798 #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH4F_SHIFT))&CMP_C2_CH4F_MASK)
1799 #define CMP_C2_CH5F_MASK 0x200000u
1800 #define CMP_C2_CH5F_SHIFT 21u
1801 #define CMP_C2_CH5F_WIDTH 1u
1802 #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH5F_SHIFT))&CMP_C2_CH5F_MASK)
1803 #define CMP_C2_CH6F_MASK 0x400000u
1804 #define CMP_C2_CH6F_SHIFT 22u
1805 #define CMP_C2_CH6F_WIDTH 1u
1806 #define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH6F_SHIFT))&CMP_C2_CH6F_MASK)
1807 #define CMP_C2_CH7F_MASK 0x800000u
1808 #define CMP_C2_CH7F_SHIFT 23u
1809 #define CMP_C2_CH7F_WIDTH 1u
1810 #define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH7F_SHIFT))&CMP_C2_CH7F_MASK)
1811 #define CMP_C2_FXMXCH_MASK 0xE000000u
1812 #define CMP_C2_FXMXCH_SHIFT 25u
1813 #define CMP_C2_FXMXCH_WIDTH 3u
1814 #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMXCH_SHIFT))&CMP_C2_FXMXCH_MASK)
1815 #define CMP_C2_FXMP_MASK 0x20000000u
1816 #define CMP_C2_FXMP_SHIFT 29u
1817 #define CMP_C2_FXMP_WIDTH 1u
1818 #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMP_SHIFT))&CMP_C2_FXMP_MASK)
1819 #define CMP_C2_RRIE_MASK 0x40000000u
1820 #define CMP_C2_RRIE_SHIFT 30u
1821 #define CMP_C2_RRIE_WIDTH 1u
1822 #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRIE_SHIFT))&CMP_C2_RRIE_MASK)
1823 #define CMP_C2_RRE_MASK 0x80000000u
1824 #define CMP_C2_RRE_SHIFT 31u
1825 #define CMP_C2_RRE_WIDTH 1u
1826 #define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRE_SHIFT))&CMP_C2_RRE_MASK)
1827  /* end of group CMP_Register_Masks */
1831 
1832  /* end of group CMP_Peripheral_Access_Layer */
1836 
1837 
1838 /* ----------------------------------------------------------------------------
1839  -- CMU_FC Peripheral Access Layer
1840  ---------------------------------------------------------------------------- */
1841 
1851 typedef struct {
1852  __IO uint32_t GCR;
1853  __IO uint32_t RCCR;
1854  __IO uint32_t HTCR;
1855  __IO uint32_t LTCR;
1856  __IO uint32_t SR;
1857  __IO uint32_t IER;
1859 
1861 #define CMU_FC_INSTANCE_COUNT (2u)
1862 
1863 
1864 /* CMU_FC - Peripheral instance base addresses */
1866 #define CMU_FC_0_BASE (0x4003E000u)
1867 
1868 #define CMU_FC_0 ((CMU_FC_Type *)CMU_FC_0_BASE)
1869 
1870 #define CMU_FC_1_BASE (0x4003F000u)
1871 
1872 #define CMU_FC_1 ((CMU_FC_Type *)CMU_FC_1_BASE)
1873 
1874 #define CMU_FC_BASE_ADDRS { CMU_FC_0_BASE, CMU_FC_1_BASE }
1875 
1876 #define CMU_FC_BASE_PTRS { CMU_FC_0, CMU_FC_1 }
1877 
1878 #define CMU_FC_IRQS_ARR_COUNT (1u)
1879 
1880 #define CMU_FC_IRQS_CH_COUNT (1u)
1881 
1882 #define CMU_FC_IRQS { SCG_CMU_LVD_LVWSCG_IRQn, SCG_CMU_LVD_LVWSCG_IRQn }
1883 
1884 /* ----------------------------------------------------------------------------
1885  -- CMU_FC Register Masks
1886  ---------------------------------------------------------------------------- */
1887 
1893 /* GCR Bit Fields */
1894 #define CMU_FC_GCR_FCE_MASK 0x1u
1895 #define CMU_FC_GCR_FCE_SHIFT 0u
1896 #define CMU_FC_GCR_FCE_WIDTH 1u
1897 #define CMU_FC_GCR_FCE(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_GCR_FCE_SHIFT))&CMU_FC_GCR_FCE_MASK)
1898 /* RCCR Bit Fields */
1899 #define CMU_FC_RCCR_REF_CNT_MASK 0xFFFFu
1900 #define CMU_FC_RCCR_REF_CNT_SHIFT 0u
1901 #define CMU_FC_RCCR_REF_CNT_WIDTH 16u
1902 #define CMU_FC_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_RCCR_REF_CNT_SHIFT))&CMU_FC_RCCR_REF_CNT_MASK)
1903 /* HTCR Bit Fields */
1904 #define CMU_FC_HTCR_HFREF_MASK 0xFFFFFFu
1905 #define CMU_FC_HTCR_HFREF_SHIFT 0u
1906 #define CMU_FC_HTCR_HFREF_WIDTH 24u
1907 #define CMU_FC_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_HTCR_HFREF_SHIFT))&CMU_FC_HTCR_HFREF_MASK)
1908 /* LTCR Bit Fields */
1909 #define CMU_FC_LTCR_LFREF_MASK 0xFFFFFFu
1910 #define CMU_FC_LTCR_LFREF_SHIFT 0u
1911 #define CMU_FC_LTCR_LFREF_WIDTH 24u
1912 #define CMU_FC_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_LTCR_LFREF_SHIFT))&CMU_FC_LTCR_LFREF_MASK)
1913 /* SR Bit Fields */
1914 #define CMU_FC_SR_FLL_MASK 0x1u
1915 #define CMU_FC_SR_FLL_SHIFT 0u
1916 #define CMU_FC_SR_FLL_WIDTH 1u
1917 #define CMU_FC_SR_FLL(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_SR_FLL_SHIFT))&CMU_FC_SR_FLL_MASK)
1918 #define CMU_FC_SR_FHH_MASK 0x2u
1919 #define CMU_FC_SR_FHH_SHIFT 1u
1920 #define CMU_FC_SR_FHH_WIDTH 1u
1921 #define CMU_FC_SR_FHH(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_SR_FHH_SHIFT))&CMU_FC_SR_FHH_MASK)
1922 #define CMU_FC_SR_STATE_MASK 0xCu
1923 #define CMU_FC_SR_STATE_SHIFT 2u
1924 #define CMU_FC_SR_STATE_WIDTH 2u
1925 #define CMU_FC_SR_STATE(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_SR_STATE_SHIFT))&CMU_FC_SR_STATE_MASK)
1926 #define CMU_FC_SR_RS_MASK 0x10u
1927 #define CMU_FC_SR_RS_SHIFT 4u
1928 #define CMU_FC_SR_RS_WIDTH 1u
1929 #define CMU_FC_SR_RS(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_SR_RS_SHIFT))&CMU_FC_SR_RS_MASK)
1930 /* IER Bit Fields */
1931 #define CMU_FC_IER_FLLIE_MASK 0x1u
1932 #define CMU_FC_IER_FLLIE_SHIFT 0u
1933 #define CMU_FC_IER_FLLIE_WIDTH 1u
1934 #define CMU_FC_IER_FLLIE(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_IER_FLLIE_SHIFT))&CMU_FC_IER_FLLIE_MASK)
1935 #define CMU_FC_IER_FHHIE_MASK 0x2u
1936 #define CMU_FC_IER_FHHIE_SHIFT 1u
1937 #define CMU_FC_IER_FHHIE_WIDTH 1u
1938 #define CMU_FC_IER_FHHIE(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_IER_FHHIE_SHIFT))&CMU_FC_IER_FHHIE_MASK)
1939 #define CMU_FC_IER_FLLAEE_MASK 0x4u
1940 #define CMU_FC_IER_FLLAEE_SHIFT 2u
1941 #define CMU_FC_IER_FLLAEE_WIDTH 1u
1942 #define CMU_FC_IER_FLLAEE(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_IER_FLLAEE_SHIFT))&CMU_FC_IER_FLLAEE_MASK)
1943 #define CMU_FC_IER_FHHAEE_MASK 0x8u
1944 #define CMU_FC_IER_FHHAEE_SHIFT 3u
1945 #define CMU_FC_IER_FHHAEE_WIDTH 1u
1946 #define CMU_FC_IER_FHHAEE(x) (((uint32_t)(((uint32_t)(x))<<CMU_FC_IER_FHHAEE_SHIFT))&CMU_FC_IER_FHHAEE_MASK)
1947  /* end of group CMU_FC_Register_Masks */
1951 
1952  /* end of group CMU_FC_Peripheral_Access_Layer */
1956 
1957 
1958 /* ----------------------------------------------------------------------------
1959  -- CRC Peripheral Access Layer
1960  ---------------------------------------------------------------------------- */
1961 
1971 typedef struct {
1972  union { /* offset: 0x0 */
1973  __IO uint32_t DATA;
1974  struct { /* offset: 0x0 */
1975  __IO uint16_t L;
1976  __IO uint16_t H;
1977  } DATA_16;
1978  struct { /* offset: 0x0 */
1979  __IO uint8_t LL;
1980  __IO uint8_t LU;
1981  __IO uint8_t HL;
1982  __IO uint8_t HU;
1983  } DATA_8;
1984  } DATAu;
1985  __IO uint32_t GPOLY;
1986  __IO uint32_t CTRL;
1988 
1990 #define CRC_INSTANCE_COUNT (1u)
1991 
1992 
1993 /* CRC - Peripheral instance base addresses */
1995 #define CRC_BASE (0x40032000u)
1996 
1997 #define CRC ((CRC_Type *)CRC_BASE)
1998 
1999 #define CRC_BASE_ADDRS { CRC_BASE }
2000 
2001 #define CRC_BASE_PTRS { CRC }
2002 
2003 /* ----------------------------------------------------------------------------
2004  -- CRC Register Masks
2005  ---------------------------------------------------------------------------- */
2006 
2012 /* DATAu_DATA Bit Fields */
2013 #define CRC_DATAu_DATA_LL_MASK 0xFFu
2014 #define CRC_DATAu_DATA_LL_SHIFT 0u
2015 #define CRC_DATAu_DATA_LL_WIDTH 8u
2016 #define CRC_DATAu_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LL_SHIFT))&CRC_DATAu_DATA_LL_MASK)
2017 #define CRC_DATAu_DATA_LU_MASK 0xFF00u
2018 #define CRC_DATAu_DATA_LU_SHIFT 8u
2019 #define CRC_DATAu_DATA_LU_WIDTH 8u
2020 #define CRC_DATAu_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LU_SHIFT))&CRC_DATAu_DATA_LU_MASK)
2021 #define CRC_DATAu_DATA_HL_MASK 0xFF0000u
2022 #define CRC_DATAu_DATA_HL_SHIFT 16u
2023 #define CRC_DATAu_DATA_HL_WIDTH 8u
2024 #define CRC_DATAu_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HL_SHIFT))&CRC_DATAu_DATA_HL_MASK)
2025 #define CRC_DATAu_DATA_HU_MASK 0xFF000000u
2026 #define CRC_DATAu_DATA_HU_SHIFT 24u
2027 #define CRC_DATAu_DATA_HU_WIDTH 8u
2028 #define CRC_DATAu_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HU_SHIFT))&CRC_DATAu_DATA_HU_MASK)
2029 /* DATAu_DATA_16_L Bit Fields */
2030 #define CRC_DATAu_DATA_16_L_DATAL_MASK 0xFFFFu
2031 #define CRC_DATAu_DATA_16_L_DATAL_SHIFT 0u
2032 #define CRC_DATAu_DATA_16_L_DATAL_WIDTH 16u
2033 #define CRC_DATAu_DATA_16_L_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_L_DATAL_SHIFT))&CRC_DATAu_DATA_16_L_DATAL_MASK)
2034 /* DATAu_DATA_16_H Bit Fields */
2035 #define CRC_DATAu_DATA_16_H_DATAH_MASK 0xFFFFu
2036 #define CRC_DATAu_DATA_16_H_DATAH_SHIFT 0u
2037 #define CRC_DATAu_DATA_16_H_DATAH_WIDTH 16u
2038 #define CRC_DATAu_DATA_16_H_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_H_DATAH_SHIFT))&CRC_DATAu_DATA_16_H_DATAH_MASK)
2039 /* DATAu_DATA_8_LL Bit Fields */
2040 #define CRC_DATAu_DATA_8_LL_DATALL_MASK 0xFFu
2041 #define CRC_DATAu_DATA_8_LL_DATALL_SHIFT 0u
2042 #define CRC_DATAu_DATA_8_LL_DATALL_WIDTH 8u
2043 #define CRC_DATAu_DATA_8_LL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LL_DATALL_SHIFT))&CRC_DATAu_DATA_8_LL_DATALL_MASK)
2044 /* DATAu_DATA_8_LU Bit Fields */
2045 #define CRC_DATAu_DATA_8_LU_DATALU_MASK 0xFFu
2046 #define CRC_DATAu_DATA_8_LU_DATALU_SHIFT 0u
2047 #define CRC_DATAu_DATA_8_LU_DATALU_WIDTH 8u
2048 #define CRC_DATAu_DATA_8_LU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LU_DATALU_SHIFT))&CRC_DATAu_DATA_8_LU_DATALU_MASK)
2049 /* DATAu_DATA_8_HL Bit Fields */
2050 #define CRC_DATAu_DATA_8_HL_DATAHL_MASK 0xFFu
2051 #define CRC_DATAu_DATA_8_HL_DATAHL_SHIFT 0u
2052 #define CRC_DATAu_DATA_8_HL_DATAHL_WIDTH 8u
2053 #define CRC_DATAu_DATA_8_HL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HL_DATAHL_SHIFT))&CRC_DATAu_DATA_8_HL_DATAHL_MASK)
2054 /* DATAu_DATA_8_HU Bit Fields */
2055 #define CRC_DATAu_DATA_8_HU_DATAHU_MASK 0xFFu
2056 #define CRC_DATAu_DATA_8_HU_DATAHU_SHIFT 0u
2057 #define CRC_DATAu_DATA_8_HU_DATAHU_WIDTH 8u
2058 #define CRC_DATAu_DATA_8_HU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HU_DATAHU_SHIFT))&CRC_DATAu_DATA_8_HU_DATAHU_MASK)
2059 /* GPOLY Bit Fields */
2060 #define CRC_GPOLY_LOW_MASK 0xFFFFu
2061 #define CRC_GPOLY_LOW_SHIFT 0u
2062 #define CRC_GPOLY_LOW_WIDTH 16u
2063 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
2064 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
2065 #define CRC_GPOLY_HIGH_SHIFT 16u
2066 #define CRC_GPOLY_HIGH_WIDTH 16u
2067 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
2068 /* CTRL Bit Fields */
2069 #define CRC_CTRL_TCRC_MASK 0x1000000u
2070 #define CRC_CTRL_TCRC_SHIFT 24u
2071 #define CRC_CTRL_TCRC_WIDTH 1u
2072 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
2073 #define CRC_CTRL_WAS_MASK 0x2000000u
2074 #define CRC_CTRL_WAS_SHIFT 25u
2075 #define CRC_CTRL_WAS_WIDTH 1u
2076 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
2077 #define CRC_CTRL_FXOR_MASK 0x4000000u
2078 #define CRC_CTRL_FXOR_SHIFT 26u
2079 #define CRC_CTRL_FXOR_WIDTH 1u
2080 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
2081 #define CRC_CTRL_TOTR_MASK 0x30000000u
2082 #define CRC_CTRL_TOTR_SHIFT 28u
2083 #define CRC_CTRL_TOTR_WIDTH 2u
2084 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
2085 #define CRC_CTRL_TOT_MASK 0xC0000000u
2086 #define CRC_CTRL_TOT_SHIFT 30u
2087 #define CRC_CTRL_TOT_WIDTH 2u
2088 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
2089  /* end of group CRC_Register_Masks */
2093 
2094  /* end of group CRC_Peripheral_Access_Layer */
2098 
2099 
2100 /* ----------------------------------------------------------------------------
2101  -- CSE_PRAM Peripheral Access Layer
2102  ---------------------------------------------------------------------------- */
2103 
2111 #define CSE_PRAM_RAMn_COUNT 32u
2112 
2114 typedef struct {
2115  union { /* offset: 0x0, array step: 0x4 */
2116  __IO uint32_t DATA_32;
2117  struct { /* offset: 0x0, array step: 0x4 */
2118  __IO uint8_t DATA_8LL;
2119  __IO uint8_t DATA_8LU;
2120  __IO uint8_t DATA_8HL;
2121  __IO uint8_t DATA_8HU;
2122  } ACCESS8BIT;
2123  } RAMn[CSE_PRAM_RAMn_COUNT];
2125 
2127 #define CSE_PRAM_INSTANCE_COUNT (1u)
2128 
2129 
2130 /* CSE_PRAM - Peripheral instance base addresses */
2132 #define CSE_PRAM_BASE (0x14000800u)
2133 
2134 #define CSE_PRAM ((CSE_PRAM_Type *)CSE_PRAM_BASE)
2135 
2136 #define CSE_PRAM_BASE_ADDRS { CSE_PRAM_BASE }
2137 
2138 #define CSE_PRAM_BASE_PTRS { CSE_PRAM }
2139 
2140 /* ----------------------------------------------------------------------------
2141  -- CSE_PRAM Register Masks
2142  ---------------------------------------------------------------------------- */
2143 
2149 /* RAMn_DATA_32 Bit Fields */
2150 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK 0xFFu
2151 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT 0u
2152 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_WIDTH 8u
2153 #define CSE_PRAM_RAMn_DATA_32_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK)
2154 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK 0xFF00u
2155 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT 8u
2156 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_WIDTH 8u
2157 #define CSE_PRAM_RAMn_DATA_32_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK)
2158 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK 0xFF0000u
2159 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT 16u
2160 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_WIDTH 8u
2161 #define CSE_PRAM_RAMn_DATA_32_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK)
2162 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK 0xFF000000u
2163 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT 24u
2164 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_WIDTH 8u
2165 #define CSE_PRAM_RAMn_DATA_32_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK)
2166 /* RAMn_ACCESS8BIT_DATA_8LL Bit Fields */
2167 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK 0xFFu
2168 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT 0u
2169 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_WIDTH 8u
2170 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK)
2171 /* RAMn_ACCESS8BIT_DATA_8LU Bit Fields */
2172 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK 0xFFu
2173 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT 0u
2174 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_WIDTH 8u
2175 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK)
2176 /* RAMn_ACCESS8BIT_DATA_8HL Bit Fields */
2177 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK 0xFFu
2178 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT 0u
2179 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_WIDTH 8u
2180 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK)
2181 /* RAMn_ACCESS8BIT_DATA_8HU Bit Fields */
2182 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK 0xFFu
2183 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT 0u
2184 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_WIDTH 8u
2185 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK)
2186  /* end of group CSE_PRAM_Register_Masks */
2190 
2191  /* end of group CSE_PRAM_Peripheral_Access_Layer */
2195 
2196 
2197 /* ----------------------------------------------------------------------------
2198  -- DMA Peripheral Access Layer
2199  ---------------------------------------------------------------------------- */
2200 
2208 #define DMA_DCHPRI_COUNT 4u
2209 #define DMA_TCD_COUNT 4u
2210 
2212 typedef struct {
2213  __IO uint32_t CR;
2214  __I uint32_t ES;
2215  uint8_t RESERVED_0[4];
2216  __IO uint32_t ERQ;
2217  uint8_t RESERVED_1[4];
2218  __IO uint32_t EEI;
2219  __O uint8_t CEEI;
2220  __O uint8_t SEEI;
2221  __O uint8_t CERQ;
2222  __O uint8_t SERQ;
2223  __O uint8_t CDNE;
2224  __O uint8_t SSRT;
2225  __O uint8_t CERR;
2226  __O uint8_t CINT;
2227  uint8_t RESERVED_2[4];
2228  __IO uint32_t INT;
2229  uint8_t RESERVED_3[4];
2230  __IO uint32_t ERR;
2231  uint8_t RESERVED_4[4];
2232  __I uint32_t HRS;
2233  uint8_t RESERVED_5[12];
2234  __IO uint32_t EARS;
2235  uint8_t RESERVED_6[184];
2236  __IO uint8_t DCHPRI[DMA_DCHPRI_COUNT];
2237  uint8_t RESERVED_7[3836];
2238  struct { /* offset: 0x1000, array step: 0x20 */
2239  __IO uint32_t SADDR;
2240  __IO uint16_t SOFF;
2241  __IO uint16_t ATTR;
2242  union { /* offset: 0x1008, array step: 0x20 */
2243  __IO uint32_t MLNO;
2244  __IO uint32_t MLOFFNO;
2245  __IO uint32_t MLOFFYES;
2246  } NBYTES;
2247  __IO uint32_t SLAST;
2248  __IO uint32_t DADDR;
2249  __IO uint16_t DOFF;
2250  union { /* offset: 0x1016, array step: 0x20 */
2251  __IO uint16_t ELINKNO;
2252  __IO uint16_t ELINKYES;
2253  } CITER;
2254  __IO uint32_t DLASTSGA;
2255  __IO uint16_t CSR;
2256  union { /* offset: 0x101E, array step: 0x20 */
2257  __IO uint16_t ELINKNO;
2258  __IO uint16_t ELINKYES;
2259  } BITER;
2260  } TCD[DMA_TCD_COUNT];
2262 
2264 #define DMA_INSTANCE_COUNT (1u)
2265 
2266 
2267 /* DMA - Peripheral instance base addresses */
2269 #define DMA_BASE (0x40008000u)
2270 
2271 #define DMA ((DMA_Type *)DMA_BASE)
2272 
2273 #define DMA_BASE_ADDRS { DMA_BASE }
2274 
2275 #define DMA_BASE_PTRS { DMA }
2276 
2277 #define DMA_IRQS_ARR_COUNT (2u)
2278 
2279 #define DMA_CHN_IRQS_CH_COUNT (4u)
2280 
2281 #define DMA_ERROR_IRQS_CH_COUNT (1u)
2282 
2283 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
2284 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
2285 
2286 /* ----------------------------------------------------------------------------
2287  -- DMA Register Masks
2288  ---------------------------------------------------------------------------- */
2289 
2295 /* CR Bit Fields */
2296 #define DMA_CR_EDBG_MASK 0x2u
2297 #define DMA_CR_EDBG_SHIFT 1u
2298 #define DMA_CR_EDBG_WIDTH 1u
2299 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
2300 #define DMA_CR_ERCA_MASK 0x4u
2301 #define DMA_CR_ERCA_SHIFT 2u
2302 #define DMA_CR_ERCA_WIDTH 1u
2303 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
2304 #define DMA_CR_HOE_MASK 0x10u
2305 #define DMA_CR_HOE_SHIFT 4u
2306 #define DMA_CR_HOE_WIDTH 1u
2307 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
2308 #define DMA_CR_HALT_MASK 0x20u
2309 #define DMA_CR_HALT_SHIFT 5u
2310 #define DMA_CR_HALT_WIDTH 1u
2311 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
2312 #define DMA_CR_CLM_MASK 0x40u
2313 #define DMA_CR_CLM_SHIFT 6u
2314 #define DMA_CR_CLM_WIDTH 1u
2315 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
2316 #define DMA_CR_EMLM_MASK 0x80u
2317 #define DMA_CR_EMLM_SHIFT 7u
2318 #define DMA_CR_EMLM_WIDTH 1u
2319 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
2320 #define DMA_CR_ECX_MASK 0x10000u
2321 #define DMA_CR_ECX_SHIFT 16u
2322 #define DMA_CR_ECX_WIDTH 1u
2323 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
2324 #define DMA_CR_CX_MASK 0x20000u
2325 #define DMA_CR_CX_SHIFT 17u
2326 #define DMA_CR_CX_WIDTH 1u
2327 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
2328 /* ES Bit Fields */
2329 #define DMA_ES_DBE_MASK 0x1u
2330 #define DMA_ES_DBE_SHIFT 0u
2331 #define DMA_ES_DBE_WIDTH 1u
2332 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
2333 #define DMA_ES_SBE_MASK 0x2u
2334 #define DMA_ES_SBE_SHIFT 1u
2335 #define DMA_ES_SBE_WIDTH 1u
2336 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
2337 #define DMA_ES_SGE_MASK 0x4u
2338 #define DMA_ES_SGE_SHIFT 2u
2339 #define DMA_ES_SGE_WIDTH 1u
2340 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
2341 #define DMA_ES_NCE_MASK 0x8u
2342 #define DMA_ES_NCE_SHIFT 3u
2343 #define DMA_ES_NCE_WIDTH 1u
2344 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
2345 #define DMA_ES_DOE_MASK 0x10u
2346 #define DMA_ES_DOE_SHIFT 4u
2347 #define DMA_ES_DOE_WIDTH 1u
2348 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
2349 #define DMA_ES_DAE_MASK 0x20u
2350 #define DMA_ES_DAE_SHIFT 5u
2351 #define DMA_ES_DAE_WIDTH 1u
2352 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
2353 #define DMA_ES_SOE_MASK 0x40u
2354 #define DMA_ES_SOE_SHIFT 6u
2355 #define DMA_ES_SOE_WIDTH 1u
2356 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
2357 #define DMA_ES_SAE_MASK 0x80u
2358 #define DMA_ES_SAE_SHIFT 7u
2359 #define DMA_ES_SAE_WIDTH 1u
2360 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
2361 #define DMA_ES_ERRCHN_MASK 0xF00u
2362 #define DMA_ES_ERRCHN_SHIFT 8u
2363 #define DMA_ES_ERRCHN_WIDTH 4u
2364 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
2365 #define DMA_ES_CPE_MASK 0x4000u
2366 #define DMA_ES_CPE_SHIFT 14u
2367 #define DMA_ES_CPE_WIDTH 1u
2368 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
2369 #define DMA_ES_ECX_MASK 0x10000u
2370 #define DMA_ES_ECX_SHIFT 16u
2371 #define DMA_ES_ECX_WIDTH 1u
2372 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
2373 #define DMA_ES_VLD_MASK 0x80000000u
2374 #define DMA_ES_VLD_SHIFT 31u
2375 #define DMA_ES_VLD_WIDTH 1u
2376 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
2377 /* ERQ Bit Fields */
2378 #define DMA_ERQ_ERQ0_MASK 0x1u
2379 #define DMA_ERQ_ERQ0_SHIFT 0u
2380 #define DMA_ERQ_ERQ0_WIDTH 1u
2381 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
2382 #define DMA_ERQ_ERQ1_MASK 0x2u
2383 #define DMA_ERQ_ERQ1_SHIFT 1u
2384 #define DMA_ERQ_ERQ1_WIDTH 1u
2385 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
2386 #define DMA_ERQ_ERQ2_MASK 0x4u
2387 #define DMA_ERQ_ERQ2_SHIFT 2u
2388 #define DMA_ERQ_ERQ2_WIDTH 1u
2389 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
2390 #define DMA_ERQ_ERQ3_MASK 0x8u
2391 #define DMA_ERQ_ERQ3_SHIFT 3u
2392 #define DMA_ERQ_ERQ3_WIDTH 1u
2393 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
2394 #define DMA_ERQ_ERQ4_MASK 0x10u
2395 #define DMA_ERQ_ERQ4_SHIFT 4u
2396 #define DMA_ERQ_ERQ4_WIDTH 1u
2397 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
2398 #define DMA_ERQ_ERQ5_MASK 0x20u
2399 #define DMA_ERQ_ERQ5_SHIFT 5u
2400 #define DMA_ERQ_ERQ5_WIDTH 1u
2401 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
2402 #define DMA_ERQ_ERQ6_MASK 0x40u
2403 #define DMA_ERQ_ERQ6_SHIFT 6u
2404 #define DMA_ERQ_ERQ6_WIDTH 1u
2405 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
2406 #define DMA_ERQ_ERQ7_MASK 0x80u
2407 #define DMA_ERQ_ERQ7_SHIFT 7u
2408 #define DMA_ERQ_ERQ7_WIDTH 1u
2409 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
2410 #define DMA_ERQ_ERQ8_MASK 0x100u
2411 #define DMA_ERQ_ERQ8_SHIFT 8u
2412 #define DMA_ERQ_ERQ8_WIDTH 1u
2413 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
2414 #define DMA_ERQ_ERQ9_MASK 0x200u
2415 #define DMA_ERQ_ERQ9_SHIFT 9u
2416 #define DMA_ERQ_ERQ9_WIDTH 1u
2417 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
2418 #define DMA_ERQ_ERQ10_MASK 0x400u
2419 #define DMA_ERQ_ERQ10_SHIFT 10u
2420 #define DMA_ERQ_ERQ10_WIDTH 1u
2421 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
2422 #define DMA_ERQ_ERQ11_MASK 0x800u
2423 #define DMA_ERQ_ERQ11_SHIFT 11u
2424 #define DMA_ERQ_ERQ11_WIDTH 1u
2425 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
2426 #define DMA_ERQ_ERQ12_MASK 0x1000u
2427 #define DMA_ERQ_ERQ12_SHIFT 12u
2428 #define DMA_ERQ_ERQ12_WIDTH 1u
2429 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
2430 #define DMA_ERQ_ERQ13_MASK 0x2000u
2431 #define DMA_ERQ_ERQ13_SHIFT 13u
2432 #define DMA_ERQ_ERQ13_WIDTH 1u
2433 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
2434 #define DMA_ERQ_ERQ14_MASK 0x4000u
2435 #define DMA_ERQ_ERQ14_SHIFT 14u
2436 #define DMA_ERQ_ERQ14_WIDTH 1u
2437 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
2438 #define DMA_ERQ_ERQ15_MASK 0x8000u
2439 #define DMA_ERQ_ERQ15_SHIFT 15u
2440 #define DMA_ERQ_ERQ15_WIDTH 1u
2441 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
2442 /* EEI Bit Fields */
2443 #define DMA_EEI_EEI0_MASK 0x1u
2444 #define DMA_EEI_EEI0_SHIFT 0u
2445 #define DMA_EEI_EEI0_WIDTH 1u
2446 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
2447 #define DMA_EEI_EEI1_MASK 0x2u
2448 #define DMA_EEI_EEI1_SHIFT 1u
2449 #define DMA_EEI_EEI1_WIDTH 1u
2450 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
2451 #define DMA_EEI_EEI2_MASK 0x4u
2452 #define DMA_EEI_EEI2_SHIFT 2u
2453 #define DMA_EEI_EEI2_WIDTH 1u
2454 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
2455 #define DMA_EEI_EEI3_MASK 0x8u
2456 #define DMA_EEI_EEI3_SHIFT 3u
2457 #define DMA_EEI_EEI3_WIDTH 1u
2458 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
2459 #define DMA_EEI_EEI4_MASK 0x10u
2460 #define DMA_EEI_EEI4_SHIFT 4u
2461 #define DMA_EEI_EEI4_WIDTH 1u
2462 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
2463 #define DMA_EEI_EEI5_MASK 0x20u
2464 #define DMA_EEI_EEI5_SHIFT 5u
2465 #define DMA_EEI_EEI5_WIDTH 1u
2466 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
2467 #define DMA_EEI_EEI6_MASK 0x40u
2468 #define DMA_EEI_EEI6_SHIFT 6u
2469 #define DMA_EEI_EEI6_WIDTH 1u
2470 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
2471 #define DMA_EEI_EEI7_MASK 0x80u
2472 #define DMA_EEI_EEI7_SHIFT 7u
2473 #define DMA_EEI_EEI7_WIDTH 1u
2474 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
2475 #define DMA_EEI_EEI8_MASK 0x100u
2476 #define DMA_EEI_EEI8_SHIFT 8u
2477 #define DMA_EEI_EEI8_WIDTH 1u
2478 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
2479 #define DMA_EEI_EEI9_MASK 0x200u
2480 #define DMA_EEI_EEI9_SHIFT 9u
2481 #define DMA_EEI_EEI9_WIDTH 1u
2482 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
2483 #define DMA_EEI_EEI10_MASK 0x400u
2484 #define DMA_EEI_EEI10_SHIFT 10u
2485 #define DMA_EEI_EEI10_WIDTH 1u
2486 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
2487 #define DMA_EEI_EEI11_MASK 0x800u
2488 #define DMA_EEI_EEI11_SHIFT 11u
2489 #define DMA_EEI_EEI11_WIDTH 1u
2490 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
2491 #define DMA_EEI_EEI12_MASK 0x1000u
2492 #define DMA_EEI_EEI12_SHIFT 12u
2493 #define DMA_EEI_EEI12_WIDTH 1u
2494 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
2495 #define DMA_EEI_EEI13_MASK 0x2000u
2496 #define DMA_EEI_EEI13_SHIFT 13u
2497 #define DMA_EEI_EEI13_WIDTH 1u
2498 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
2499 #define DMA_EEI_EEI14_MASK 0x4000u
2500 #define DMA_EEI_EEI14_SHIFT 14u
2501 #define DMA_EEI_EEI14_WIDTH 1u
2502 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
2503 #define DMA_EEI_EEI15_MASK 0x8000u
2504 #define DMA_EEI_EEI15_SHIFT 15u
2505 #define DMA_EEI_EEI15_WIDTH 1u
2506 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
2507 /* CEEI Bit Fields */
2508 #define DMA_CEEI_CEEI_MASK 0xFu
2509 #define DMA_CEEI_CEEI_SHIFT 0u
2510 #define DMA_CEEI_CEEI_WIDTH 4u
2511 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
2512 #define DMA_CEEI_CAEE_MASK 0x40u
2513 #define DMA_CEEI_CAEE_SHIFT 6u
2514 #define DMA_CEEI_CAEE_WIDTH 1u
2515 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
2516 #define DMA_CEEI_NOP_MASK 0x80u
2517 #define DMA_CEEI_NOP_SHIFT 7u
2518 #define DMA_CEEI_NOP_WIDTH 1u
2519 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
2520 /* SEEI Bit Fields */
2521 #define DMA_SEEI_SEEI_MASK 0xFu
2522 #define DMA_SEEI_SEEI_SHIFT 0u
2523 #define DMA_SEEI_SEEI_WIDTH 4u
2524 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
2525 #define DMA_SEEI_SAEE_MASK 0x40u
2526 #define DMA_SEEI_SAEE_SHIFT 6u
2527 #define DMA_SEEI_SAEE_WIDTH 1u
2528 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
2529 #define DMA_SEEI_NOP_MASK 0x80u
2530 #define DMA_SEEI_NOP_SHIFT 7u
2531 #define DMA_SEEI_NOP_WIDTH 1u
2532 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
2533 /* CERQ Bit Fields */
2534 #define DMA_CERQ_CERQ_MASK 0xFu
2535 #define DMA_CERQ_CERQ_SHIFT 0u
2536 #define DMA_CERQ_CERQ_WIDTH 4u
2537 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
2538 #define DMA_CERQ_CAER_MASK 0x40u
2539 #define DMA_CERQ_CAER_SHIFT 6u
2540 #define DMA_CERQ_CAER_WIDTH 1u
2541 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
2542 #define DMA_CERQ_NOP_MASK 0x80u
2543 #define DMA_CERQ_NOP_SHIFT 7u
2544 #define DMA_CERQ_NOP_WIDTH 1u
2545 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
2546 /* SERQ Bit Fields */
2547 #define DMA_SERQ_SERQ_MASK 0xFu
2548 #define DMA_SERQ_SERQ_SHIFT 0u
2549 #define DMA_SERQ_SERQ_WIDTH 4u
2550 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
2551 #define DMA_SERQ_SAER_MASK 0x40u
2552 #define DMA_SERQ_SAER_SHIFT 6u
2553 #define DMA_SERQ_SAER_WIDTH 1u
2554 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
2555 #define DMA_SERQ_NOP_MASK 0x80u
2556 #define DMA_SERQ_NOP_SHIFT 7u
2557 #define DMA_SERQ_NOP_WIDTH 1u
2558 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
2559 /* CDNE Bit Fields */
2560 #define DMA_CDNE_CDNE_MASK 0xFu
2561 #define DMA_CDNE_CDNE_SHIFT 0u
2562 #define DMA_CDNE_CDNE_WIDTH 4u
2563 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
2564 #define DMA_CDNE_CADN_MASK 0x40u
2565 #define DMA_CDNE_CADN_SHIFT 6u
2566 #define DMA_CDNE_CADN_WIDTH 1u
2567 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
2568 #define DMA_CDNE_NOP_MASK 0x80u
2569 #define DMA_CDNE_NOP_SHIFT 7u
2570 #define DMA_CDNE_NOP_WIDTH 1u
2571 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
2572 /* SSRT Bit Fields */
2573 #define DMA_SSRT_SSRT_MASK 0xFu
2574 #define DMA_SSRT_SSRT_SHIFT 0u
2575 #define DMA_SSRT_SSRT_WIDTH 4u
2576 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
2577 #define DMA_SSRT_SAST_MASK 0x40u
2578 #define DMA_SSRT_SAST_SHIFT 6u
2579 #define DMA_SSRT_SAST_WIDTH 1u
2580 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
2581 #define DMA_SSRT_NOP_MASK 0x80u
2582 #define DMA_SSRT_NOP_SHIFT 7u
2583 #define DMA_SSRT_NOP_WIDTH 1u
2584 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
2585 /* CERR Bit Fields */
2586 #define DMA_CERR_CERR_MASK 0xFu
2587 #define DMA_CERR_CERR_SHIFT 0u
2588 #define DMA_CERR_CERR_WIDTH 4u
2589 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
2590 #define DMA_CERR_CAEI_MASK 0x40u
2591 #define DMA_CERR_CAEI_SHIFT 6u
2592 #define DMA_CERR_CAEI_WIDTH 1u
2593 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
2594 #define DMA_CERR_NOP_MASK 0x80u
2595 #define DMA_CERR_NOP_SHIFT 7u
2596 #define DMA_CERR_NOP_WIDTH 1u
2597 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
2598 /* CINT Bit Fields */
2599 #define DMA_CINT_CINT_MASK 0xFu
2600 #define DMA_CINT_CINT_SHIFT 0u
2601 #define DMA_CINT_CINT_WIDTH 4u
2602 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
2603 #define DMA_CINT_CAIR_MASK 0x40u
2604 #define DMA_CINT_CAIR_SHIFT 6u
2605 #define DMA_CINT_CAIR_WIDTH 1u
2606 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
2607 #define DMA_CINT_NOP_MASK 0x80u
2608 #define DMA_CINT_NOP_SHIFT 7u
2609 #define DMA_CINT_NOP_WIDTH 1u
2610 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
2611 /* INT Bit Fields */
2612 #define DMA_INT_INT0_MASK 0x1u
2613 #define DMA_INT_INT0_SHIFT 0u
2614 #define DMA_INT_INT0_WIDTH 1u
2615 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
2616 #define DMA_INT_INT1_MASK 0x2u
2617 #define DMA_INT_INT1_SHIFT 1u
2618 #define DMA_INT_INT1_WIDTH 1u
2619 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
2620 #define DMA_INT_INT2_MASK 0x4u
2621 #define DMA_INT_INT2_SHIFT 2u
2622 #define DMA_INT_INT2_WIDTH 1u
2623 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
2624 #define DMA_INT_INT3_MASK 0x8u
2625 #define DMA_INT_INT3_SHIFT 3u
2626 #define DMA_INT_INT3_WIDTH 1u
2627 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
2628 #define DMA_INT_INT4_MASK 0x10u
2629 #define DMA_INT_INT4_SHIFT 4u
2630 #define DMA_INT_INT4_WIDTH 1u
2631 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
2632 #define DMA_INT_INT5_MASK 0x20u
2633 #define DMA_INT_INT5_SHIFT 5u
2634 #define DMA_INT_INT5_WIDTH 1u
2635 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
2636 #define DMA_INT_INT6_MASK 0x40u
2637 #define DMA_INT_INT6_SHIFT 6u
2638 #define DMA_INT_INT6_WIDTH 1u
2639 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
2640 #define DMA_INT_INT7_MASK 0x80u
2641 #define DMA_INT_INT7_SHIFT 7u
2642 #define DMA_INT_INT7_WIDTH 1u
2643 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
2644 #define DMA_INT_INT8_MASK 0x100u
2645 #define DMA_INT_INT8_SHIFT 8u
2646 #define DMA_INT_INT8_WIDTH 1u
2647 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
2648 #define DMA_INT_INT9_MASK 0x200u
2649 #define DMA_INT_INT9_SHIFT 9u
2650 #define DMA_INT_INT9_WIDTH 1u
2651 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
2652 #define DMA_INT_INT10_MASK 0x400u
2653 #define DMA_INT_INT10_SHIFT 10u
2654 #define DMA_INT_INT10_WIDTH 1u
2655 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
2656 #define DMA_INT_INT11_MASK 0x800u
2657 #define DMA_INT_INT11_SHIFT 11u
2658 #define DMA_INT_INT11_WIDTH 1u
2659 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
2660 #define DMA_INT_INT12_MASK 0x1000u
2661 #define DMA_INT_INT12_SHIFT 12u
2662 #define DMA_INT_INT12_WIDTH 1u
2663 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
2664 #define DMA_INT_INT13_MASK 0x2000u
2665 #define DMA_INT_INT13_SHIFT 13u
2666 #define DMA_INT_INT13_WIDTH 1u
2667 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
2668 #define DMA_INT_INT14_MASK 0x4000u
2669 #define DMA_INT_INT14_SHIFT 14u
2670 #define DMA_INT_INT14_WIDTH 1u
2671 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
2672 #define DMA_INT_INT15_MASK 0x8000u
2673 #define DMA_INT_INT15_SHIFT 15u
2674 #define DMA_INT_INT15_WIDTH 1u
2675 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
2676 /* ERR Bit Fields */
2677 #define DMA_ERR_ERR0_MASK 0x1u
2678 #define DMA_ERR_ERR0_SHIFT 0u
2679 #define DMA_ERR_ERR0_WIDTH 1u
2680 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
2681 #define DMA_ERR_ERR1_MASK 0x2u
2682 #define DMA_ERR_ERR1_SHIFT 1u
2683 #define DMA_ERR_ERR1_WIDTH 1u
2684 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
2685 #define DMA_ERR_ERR2_MASK 0x4u
2686 #define DMA_ERR_ERR2_SHIFT 2u
2687 #define DMA_ERR_ERR2_WIDTH 1u
2688 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
2689 #define DMA_ERR_ERR3_MASK 0x8u
2690 #define DMA_ERR_ERR3_SHIFT 3u
2691 #define DMA_ERR_ERR3_WIDTH 1u
2692 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
2693 #define DMA_ERR_ERR4_MASK 0x10u
2694 #define DMA_ERR_ERR4_SHIFT 4u
2695 #define DMA_ERR_ERR4_WIDTH 1u
2696 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
2697 #define DMA_ERR_ERR5_MASK 0x20u
2698 #define DMA_ERR_ERR5_SHIFT 5u
2699 #define DMA_ERR_ERR5_WIDTH 1u
2700 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
2701 #define DMA_ERR_ERR6_MASK 0x40u
2702 #define DMA_ERR_ERR6_SHIFT 6u
2703 #define DMA_ERR_ERR6_WIDTH 1u
2704 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
2705 #define DMA_ERR_ERR7_MASK 0x80u
2706 #define DMA_ERR_ERR7_SHIFT 7u
2707 #define DMA_ERR_ERR7_WIDTH 1u
2708 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
2709 #define DMA_ERR_ERR8_MASK 0x100u
2710 #define DMA_ERR_ERR8_SHIFT 8u
2711 #define DMA_ERR_ERR8_WIDTH 1u
2712 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
2713 #define DMA_ERR_ERR9_MASK 0x200u
2714 #define DMA_ERR_ERR9_SHIFT 9u
2715 #define DMA_ERR_ERR9_WIDTH 1u
2716 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
2717 #define DMA_ERR_ERR10_MASK 0x400u
2718 #define DMA_ERR_ERR10_SHIFT 10u
2719 #define DMA_ERR_ERR10_WIDTH 1u
2720 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
2721 #define DMA_ERR_ERR11_MASK 0x800u
2722 #define DMA_ERR_ERR11_SHIFT 11u
2723 #define DMA_ERR_ERR11_WIDTH 1u
2724 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
2725 #define DMA_ERR_ERR12_MASK 0x1000u
2726 #define DMA_ERR_ERR12_SHIFT 12u
2727 #define DMA_ERR_ERR12_WIDTH 1u
2728 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
2729 #define DMA_ERR_ERR13_MASK 0x2000u
2730 #define DMA_ERR_ERR13_SHIFT 13u
2731 #define DMA_ERR_ERR13_WIDTH 1u
2732 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
2733 #define DMA_ERR_ERR14_MASK 0x4000u
2734 #define DMA_ERR_ERR14_SHIFT 14u
2735 #define DMA_ERR_ERR14_WIDTH 1u
2736 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
2737 #define DMA_ERR_ERR15_MASK 0x8000u
2738 #define DMA_ERR_ERR15_SHIFT 15u
2739 #define DMA_ERR_ERR15_WIDTH 1u
2740 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
2741 /* HRS Bit Fields */
2742 #define DMA_HRS_HRS0_MASK 0x1u
2743 #define DMA_HRS_HRS0_SHIFT 0u
2744 #define DMA_HRS_HRS0_WIDTH 1u
2745 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
2746 #define DMA_HRS_HRS1_MASK 0x2u
2747 #define DMA_HRS_HRS1_SHIFT 1u
2748 #define DMA_HRS_HRS1_WIDTH 1u
2749 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
2750 #define DMA_HRS_HRS2_MASK 0x4u
2751 #define DMA_HRS_HRS2_SHIFT 2u
2752 #define DMA_HRS_HRS2_WIDTH 1u
2753 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
2754 #define DMA_HRS_HRS3_MASK 0x8u
2755 #define DMA_HRS_HRS3_SHIFT 3u
2756 #define DMA_HRS_HRS3_WIDTH 1u
2757 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
2758 #define DMA_HRS_HRS4_MASK 0x10u
2759 #define DMA_HRS_HRS4_SHIFT 4u
2760 #define DMA_HRS_HRS4_WIDTH 1u
2761 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
2762 #define DMA_HRS_HRS5_MASK 0x20u
2763 #define DMA_HRS_HRS5_SHIFT 5u
2764 #define DMA_HRS_HRS5_WIDTH 1u
2765 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
2766 #define DMA_HRS_HRS6_MASK 0x40u
2767 #define DMA_HRS_HRS6_SHIFT 6u
2768 #define DMA_HRS_HRS6_WIDTH 1u
2769 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
2770 #define DMA_HRS_HRS7_MASK 0x80u
2771 #define DMA_HRS_HRS7_SHIFT 7u
2772 #define DMA_HRS_HRS7_WIDTH 1u
2773 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
2774 #define DMA_HRS_HRS8_MASK 0x100u
2775 #define DMA_HRS_HRS8_SHIFT 8u
2776 #define DMA_HRS_HRS8_WIDTH 1u
2777 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
2778 #define DMA_HRS_HRS9_MASK 0x200u
2779 #define DMA_HRS_HRS9_SHIFT 9u
2780 #define DMA_HRS_HRS9_WIDTH 1u
2781 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
2782 #define DMA_HRS_HRS10_MASK 0x400u
2783 #define DMA_HRS_HRS10_SHIFT 10u
2784 #define DMA_HRS_HRS10_WIDTH 1u
2785 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
2786 #define DMA_HRS_HRS11_MASK 0x800u
2787 #define DMA_HRS_HRS11_SHIFT 11u
2788 #define DMA_HRS_HRS11_WIDTH 1u
2789 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
2790 #define DMA_HRS_HRS12_MASK 0x1000u
2791 #define DMA_HRS_HRS12_SHIFT 12u
2792 #define DMA_HRS_HRS12_WIDTH 1u
2793 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
2794 #define DMA_HRS_HRS13_MASK 0x2000u
2795 #define DMA_HRS_HRS13_SHIFT 13u
2796 #define DMA_HRS_HRS13_WIDTH 1u
2797 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
2798 #define DMA_HRS_HRS14_MASK 0x4000u
2799 #define DMA_HRS_HRS14_SHIFT 14u
2800 #define DMA_HRS_HRS14_WIDTH 1u
2801 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
2802 #define DMA_HRS_HRS15_MASK 0x8000u
2803 #define DMA_HRS_HRS15_SHIFT 15u
2804 #define DMA_HRS_HRS15_WIDTH 1u
2805 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
2806 /* EARS Bit Fields */
2807 #define DMA_EARS_EDREQ_0_MASK 0x1u
2808 #define DMA_EARS_EDREQ_0_SHIFT 0u
2809 #define DMA_EARS_EDREQ_0_WIDTH 1u
2810 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
2811 #define DMA_EARS_EDREQ_1_MASK 0x2u
2812 #define DMA_EARS_EDREQ_1_SHIFT 1u
2813 #define DMA_EARS_EDREQ_1_WIDTH 1u
2814 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
2815 #define DMA_EARS_EDREQ_2_MASK 0x4u
2816 #define DMA_EARS_EDREQ_2_SHIFT 2u
2817 #define DMA_EARS_EDREQ_2_WIDTH 1u
2818 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
2819 #define DMA_EARS_EDREQ_3_MASK 0x8u
2820 #define DMA_EARS_EDREQ_3_SHIFT 3u
2821 #define DMA_EARS_EDREQ_3_WIDTH 1u
2822 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
2823 #define DMA_EARS_EDREQ_4_MASK 0x10u
2824 #define DMA_EARS_EDREQ_4_SHIFT 4u
2825 #define DMA_EARS_EDREQ_4_WIDTH 1u
2826 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
2827 #define DMA_EARS_EDREQ_5_MASK 0x20u
2828 #define DMA_EARS_EDREQ_5_SHIFT 5u
2829 #define DMA_EARS_EDREQ_5_WIDTH 1u
2830 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
2831 #define DMA_EARS_EDREQ_6_MASK 0x40u
2832 #define DMA_EARS_EDREQ_6_SHIFT 6u
2833 #define DMA_EARS_EDREQ_6_WIDTH 1u
2834 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
2835 #define DMA_EARS_EDREQ_7_MASK 0x80u
2836 #define DMA_EARS_EDREQ_7_SHIFT 7u
2837 #define DMA_EARS_EDREQ_7_WIDTH 1u
2838 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
2839 #define DMA_EARS_EDREQ_8_MASK 0x100u
2840 #define DMA_EARS_EDREQ_8_SHIFT 8u
2841 #define DMA_EARS_EDREQ_8_WIDTH 1u
2842 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_8_SHIFT))&DMA_EARS_EDREQ_8_MASK)
2843 #define DMA_EARS_EDREQ_9_MASK 0x200u
2844 #define DMA_EARS_EDREQ_9_SHIFT 9u
2845 #define DMA_EARS_EDREQ_9_WIDTH 1u
2846 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_9_SHIFT))&DMA_EARS_EDREQ_9_MASK)
2847 #define DMA_EARS_EDREQ_10_MASK 0x400u
2848 #define DMA_EARS_EDREQ_10_SHIFT 10u
2849 #define DMA_EARS_EDREQ_10_WIDTH 1u
2850 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_10_SHIFT))&DMA_EARS_EDREQ_10_MASK)
2851 #define DMA_EARS_EDREQ_11_MASK 0x800u
2852 #define DMA_EARS_EDREQ_11_SHIFT 11u
2853 #define DMA_EARS_EDREQ_11_WIDTH 1u
2854 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_11_SHIFT))&DMA_EARS_EDREQ_11_MASK)
2855 #define DMA_EARS_EDREQ_12_MASK 0x1000u
2856 #define DMA_EARS_EDREQ_12_SHIFT 12u
2857 #define DMA_EARS_EDREQ_12_WIDTH 1u
2858 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_12_SHIFT))&DMA_EARS_EDREQ_12_MASK)
2859 #define DMA_EARS_EDREQ_13_MASK 0x2000u
2860 #define DMA_EARS_EDREQ_13_SHIFT 13u
2861 #define DMA_EARS_EDREQ_13_WIDTH 1u
2862 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_13_SHIFT))&DMA_EARS_EDREQ_13_MASK)
2863 #define DMA_EARS_EDREQ_14_MASK 0x4000u
2864 #define DMA_EARS_EDREQ_14_SHIFT 14u
2865 #define DMA_EARS_EDREQ_14_WIDTH 1u
2866 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_14_SHIFT))&DMA_EARS_EDREQ_14_MASK)
2867 #define DMA_EARS_EDREQ_15_MASK 0x8000u
2868 #define DMA_EARS_EDREQ_15_SHIFT 15u
2869 #define DMA_EARS_EDREQ_15_WIDTH 1u
2870 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_15_SHIFT))&DMA_EARS_EDREQ_15_MASK)
2871 /* DCHPRI Bit Fields */
2872 #define DMA_DCHPRI_CHPRI_MASK 0xFu
2873 #define DMA_DCHPRI_CHPRI_SHIFT 0u
2874 #define DMA_DCHPRI_CHPRI_WIDTH 4u
2875 #define DMA_DCHPRI_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_CHPRI_SHIFT))&DMA_DCHPRI_CHPRI_MASK)
2876 #define DMA_DCHPRI_DPA_MASK 0x40u
2877 #define DMA_DCHPRI_DPA_SHIFT 6u
2878 #define DMA_DCHPRI_DPA_WIDTH 1u
2879 #define DMA_DCHPRI_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_DPA_SHIFT))&DMA_DCHPRI_DPA_MASK)
2880 #define DMA_DCHPRI_ECP_MASK 0x80u
2881 #define DMA_DCHPRI_ECP_SHIFT 7u
2882 #define DMA_DCHPRI_ECP_WIDTH 1u
2883 #define DMA_DCHPRI_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_ECP_SHIFT))&DMA_DCHPRI_ECP_MASK)
2884 /* TCD_SADDR Bit Fields */
2885 #define DMA_TCD_SADDR_SADDR_MASK 0xFFFFFFFFu
2886 #define DMA_TCD_SADDR_SADDR_SHIFT 0u
2887 #define DMA_TCD_SADDR_SADDR_WIDTH 32u
2888 #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SADDR_SADDR_SHIFT))&DMA_TCD_SADDR_SADDR_MASK)
2889 /* TCD_SOFF Bit Fields */
2890 #define DMA_TCD_SOFF_SOFF_MASK 0xFFFFu
2891 #define DMA_TCD_SOFF_SOFF_SHIFT 0u
2892 #define DMA_TCD_SOFF_SOFF_WIDTH 16u
2893 #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_SOFF_SOFF_SHIFT))&DMA_TCD_SOFF_SOFF_MASK)
2894 /* TCD_ATTR Bit Fields */
2895 #define DMA_TCD_ATTR_DSIZE_MASK 0x7u
2896 #define DMA_TCD_ATTR_DSIZE_SHIFT 0u
2897 #define DMA_TCD_ATTR_DSIZE_WIDTH 3u
2898 #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DSIZE_SHIFT))&DMA_TCD_ATTR_DSIZE_MASK)
2899 #define DMA_TCD_ATTR_DMOD_MASK 0xF8u
2900 #define DMA_TCD_ATTR_DMOD_SHIFT 3u
2901 #define DMA_TCD_ATTR_DMOD_WIDTH 5u
2902 #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DMOD_SHIFT))&DMA_TCD_ATTR_DMOD_MASK)
2903 #define DMA_TCD_ATTR_SSIZE_MASK 0x700u
2904 #define DMA_TCD_ATTR_SSIZE_SHIFT 8u
2905 #define DMA_TCD_ATTR_SSIZE_WIDTH 3u
2906 #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SSIZE_SHIFT))&DMA_TCD_ATTR_SSIZE_MASK)
2907 #define DMA_TCD_ATTR_SMOD_MASK 0xF800u
2908 #define DMA_TCD_ATTR_SMOD_SHIFT 11u
2909 #define DMA_TCD_ATTR_SMOD_WIDTH 5u
2910 #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SMOD_SHIFT))&DMA_TCD_ATTR_SMOD_MASK)
2911 /* TCD_NBYTES_MLNO Bit Fields */
2912 #define DMA_TCD_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
2913 #define DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT 0u
2914 #define DMA_TCD_NBYTES_MLNO_NBYTES_WIDTH 32u
2915 #define DMA_TCD_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLNO_NBYTES_MASK)
2916 /* TCD_NBYTES_MLOFFNO Bit Fields */
2917 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
2918 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT 0u
2919 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH 30u
2920 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
2921 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
2922 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT 30u
2923 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH 1u
2924 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
2925 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
2926 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT 31u
2927 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH 1u
2928 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
2929 /* TCD_NBYTES_MLOFFYES Bit Fields */
2930 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
2931 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT 0u
2932 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH 10u
2933 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
2934 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
2935 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT 10u
2936 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH 20u
2937 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
2938 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
2939 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT 30u
2940 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH 1u
2941 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
2942 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
2943 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT 31u
2944 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH 1u
2945 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
2946 /* TCD_SLAST Bit Fields */
2947 #define DMA_TCD_SLAST_SLAST_MASK 0xFFFFFFFFu
2948 #define DMA_TCD_SLAST_SLAST_SHIFT 0u
2949 #define DMA_TCD_SLAST_SLAST_WIDTH 32u
2950 #define DMA_TCD_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SLAST_SLAST_SHIFT))&DMA_TCD_SLAST_SLAST_MASK)
2951 /* TCD_DADDR Bit Fields */
2952 #define DMA_TCD_DADDR_DADDR_MASK 0xFFFFFFFFu
2953 #define DMA_TCD_DADDR_DADDR_SHIFT 0u
2954 #define DMA_TCD_DADDR_DADDR_WIDTH 32u
2955 #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DADDR_DADDR_SHIFT))&DMA_TCD_DADDR_DADDR_MASK)
2956 /* TCD_DOFF Bit Fields */
2957 #define DMA_TCD_DOFF_DOFF_MASK 0xFFFFu
2958 #define DMA_TCD_DOFF_DOFF_SHIFT 0u
2959 #define DMA_TCD_DOFF_DOFF_WIDTH 16u
2960 #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_DOFF_DOFF_SHIFT))&DMA_TCD_DOFF_DOFF_MASK)
2961 /* TCD_CITER_ELINKNO Bit Fields */
2962 #define DMA_TCD_CITER_ELINKNO_CITER_MASK 0x7FFFu
2963 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT 0u
2964 #define DMA_TCD_CITER_ELINKNO_CITER_WIDTH 15u
2965 #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_CITER_SHIFT))&DMA_TCD_CITER_ELINKNO_CITER_MASK)
2966 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK 0x8000u
2967 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT 15u
2968 #define DMA_TCD_CITER_ELINKNO_ELINK_WIDTH 1u
2969 #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_CITER_ELINKNO_ELINK_MASK)
2970 /* TCD_CITER_ELINKYES Bit Fields */
2971 #define DMA_TCD_CITER_ELINKYES_CITER_LE_MASK 0x1FFu
2972 #define DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT 0u
2973 #define DMA_TCD_CITER_ELINKYES_CITER_LE_WIDTH 9u
2974 #define DMA_TCD_CITER_ELINKYES_CITER_LE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT))&DMA_TCD_CITER_ELINKYES_CITER_LE_MASK)
2975 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK 0x1E00u
2976 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT 9u
2977 #define DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH 4u
2978 #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
2979 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK 0x8000u
2980 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT 15u
2981 #define DMA_TCD_CITER_ELINKYES_ELINK_WIDTH 1u
2982 #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_CITER_ELINKYES_ELINK_MASK)
2983 /* TCD_DLASTSGA Bit Fields */
2984 #define DMA_TCD_DLASTSGA_DLASTSGA_MASK 0xFFFFFFFFu
2985 #define DMA_TCD_DLASTSGA_DLASTSGA_SHIFT 0u
2986 #define DMA_TCD_DLASTSGA_DLASTSGA_WIDTH 32u
2987 #define DMA_TCD_DLASTSGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DLASTSGA_DLASTSGA_SHIFT))&DMA_TCD_DLASTSGA_DLASTSGA_MASK)
2988 /* TCD_CSR Bit Fields */
2989 #define DMA_TCD_CSR_START_MASK 0x1u
2990 #define DMA_TCD_CSR_START_SHIFT 0u
2991 #define DMA_TCD_CSR_START_WIDTH 1u
2992 #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_START_SHIFT))&DMA_TCD_CSR_START_MASK)
2993 #define DMA_TCD_CSR_INTMAJOR_MASK 0x2u
2994 #define DMA_TCD_CSR_INTMAJOR_SHIFT 1u
2995 #define DMA_TCD_CSR_INTMAJOR_WIDTH 1u
2996 #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTMAJOR_SHIFT))&DMA_TCD_CSR_INTMAJOR_MASK)
2997 #define DMA_TCD_CSR_INTHALF_MASK 0x4u
2998 #define DMA_TCD_CSR_INTHALF_SHIFT 2u
2999 #define DMA_TCD_CSR_INTHALF_WIDTH 1u
3000 #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTHALF_SHIFT))&DMA_TCD_CSR_INTHALF_MASK)
3001 #define DMA_TCD_CSR_DREQ_MASK 0x8u
3002 #define DMA_TCD_CSR_DREQ_SHIFT 3u
3003 #define DMA_TCD_CSR_DREQ_WIDTH 1u
3004 #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DREQ_SHIFT))&DMA_TCD_CSR_DREQ_MASK)
3005 #define DMA_TCD_CSR_ESG_MASK 0x10u
3006 #define DMA_TCD_CSR_ESG_SHIFT 4u
3007 #define DMA_TCD_CSR_ESG_WIDTH 1u
3008 #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ESG_SHIFT))&DMA_TCD_CSR_ESG_MASK)
3009 #define DMA_TCD_CSR_MAJORELINK_MASK 0x20u
3010 #define DMA_TCD_CSR_MAJORELINK_SHIFT 5u
3011 #define DMA_TCD_CSR_MAJORELINK_WIDTH 1u
3012 #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORELINK_SHIFT))&DMA_TCD_CSR_MAJORELINK_MASK)
3013 #define DMA_TCD_CSR_ACTIVE_MASK 0x40u
3014 #define DMA_TCD_CSR_ACTIVE_SHIFT 6u
3015 #define DMA_TCD_CSR_ACTIVE_WIDTH 1u
3016 #define DMA_TCD_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ACTIVE_SHIFT))&DMA_TCD_CSR_ACTIVE_MASK)
3017 #define DMA_TCD_CSR_DONE_MASK 0x80u
3018 #define DMA_TCD_CSR_DONE_SHIFT 7u
3019 #define DMA_TCD_CSR_DONE_WIDTH 1u
3020 #define DMA_TCD_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DONE_SHIFT))&DMA_TCD_CSR_DONE_MASK)
3021 #define DMA_TCD_CSR_MAJORLINKCH_MASK 0xF00u
3022 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT 8u
3023 #define DMA_TCD_CSR_MAJORLINKCH_WIDTH 4u
3024 #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORLINKCH_SHIFT))&DMA_TCD_CSR_MAJORLINKCH_MASK)
3025 #define DMA_TCD_CSR_BWC_MASK 0xC000u
3026 #define DMA_TCD_CSR_BWC_SHIFT 14u
3027 #define DMA_TCD_CSR_BWC_WIDTH 2u
3028 #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_BWC_SHIFT))&DMA_TCD_CSR_BWC_MASK)
3029 /* TCD_BITER_ELINKNO Bit Fields */
3030 #define DMA_TCD_BITER_ELINKNO_BITER_MASK 0x7FFFu
3031 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT 0u
3032 #define DMA_TCD_BITER_ELINKNO_BITER_WIDTH 15u
3033 #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_BITER_SHIFT))&DMA_TCD_BITER_ELINKNO_BITER_MASK)
3034 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK 0x8000u
3035 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT 15u
3036 #define DMA_TCD_BITER_ELINKNO_ELINK_WIDTH 1u
3037 #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_BITER_ELINKNO_ELINK_MASK)
3038 /* TCD_BITER_ELINKYES Bit Fields */
3039 #define DMA_TCD_BITER_ELINKYES_BITER_MASK 0x1FFu
3040 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT 0u
3041 #define DMA_TCD_BITER_ELINKYES_BITER_WIDTH 9u
3042 #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_BITER_SHIFT))&DMA_TCD_BITER_ELINKYES_BITER_MASK)
3043 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK 0x1E00u
3044 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT 9u
3045 #define DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH 4u
3046 #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
3047 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK 0x8000u
3048 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT 15u
3049 #define DMA_TCD_BITER_ELINKYES_ELINK_WIDTH 1u
3050 #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_BITER_ELINKYES_ELINK_MASK)
3051  /* end of group DMA_Register_Masks */
3055 
3056  /* end of group DMA_Peripheral_Access_Layer */
3060 
3061 
3062 /* ----------------------------------------------------------------------------
3063  -- DMAMUX Peripheral Access Layer
3064  ---------------------------------------------------------------------------- */
3065 
3073 #define DMAMUX_CHCFG_COUNT 4u
3074 
3076 typedef struct {
3077  __IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT];
3079 
3081 #define DMAMUX_INSTANCE_COUNT (1u)
3082 
3083 
3084 /* DMAMUX - Peripheral instance base addresses */
3086 #define DMAMUX_BASE (0x40021000u)
3087 
3088 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
3089 
3090 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
3091 
3092 #define DMAMUX_BASE_PTRS { DMAMUX }
3093 
3094 /* ----------------------------------------------------------------------------
3095  -- DMAMUX Register Masks
3096  ---------------------------------------------------------------------------- */
3097 
3103 /* CHCFG Bit Fields */
3104 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
3105 #define DMAMUX_CHCFG_SOURCE_SHIFT 0u
3106 #define DMAMUX_CHCFG_SOURCE_WIDTH 6u
3107 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
3108 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
3109 #define DMAMUX_CHCFG_TRIG_SHIFT 6u
3110 #define DMAMUX_CHCFG_TRIG_WIDTH 1u
3111 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
3112 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
3113 #define DMAMUX_CHCFG_ENBL_SHIFT 7u
3114 #define DMAMUX_CHCFG_ENBL_WIDTH 1u
3115 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
3116  /* end of group DMAMUX_Register_Masks */
3120 
3121  /* end of group DMAMUX_Peripheral_Access_Layer */
3125 
3126 
3127 /* ----------------------------------------------------------------------------
3128  -- EIM Peripheral Access Layer
3129  ---------------------------------------------------------------------------- */
3130 
3138 #define EIM_EICHDn_COUNT 1u
3139 
3141 typedef struct {
3142  __IO uint32_t EIMCR;
3143  __IO uint32_t EICHEN;
3144  uint8_t RESERVED_0[248];
3145  struct { /* offset: 0x100, array step: 0x8 */
3146  __IO uint32_t WORD0;
3147  __IO uint32_t WORD1;
3148  } EICHDn[EIM_EICHDn_COUNT];
3150 
3152 #define EIM_INSTANCE_COUNT (1u)
3153 
3154 
3155 /* EIM - Peripheral instance base addresses */
3157 #define EIM_BASE (0x40019000u)
3158 
3159 #define EIM ((EIM_Type *)EIM_BASE)
3160 
3161 #define EIM_BASE_ADDRS { EIM_BASE }
3162 
3163 #define EIM_BASE_PTRS { EIM }
3164 
3165 /* ----------------------------------------------------------------------------
3166  -- EIM Register Masks
3167  ---------------------------------------------------------------------------- */
3168 
3174 /* EIMCR Bit Fields */
3175 #define EIM_EIMCR_GEIEN_MASK 0x1u
3176 #define EIM_EIMCR_GEIEN_SHIFT 0u
3177 #define EIM_EIMCR_GEIEN_WIDTH 1u
3178 #define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EIMCR_GEIEN_SHIFT))&EIM_EIMCR_GEIEN_MASK)
3179 /* EICHEN Bit Fields */
3180 #define EIM_EICHEN_EICH0EN_MASK 0x80000000u
3181 #define EIM_EICHEN_EICH0EN_SHIFT 31u
3182 #define EIM_EICHEN_EICH0EN_WIDTH 1u
3183 #define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH0EN_SHIFT))&EIM_EICHEN_EICH0EN_MASK)
3184 /* EICHDn_WORD0 Bit Fields */
3185 #define EIM_EICHDn_WORD0_CHKBIT_MASK_MASK 0xFE000000u
3186 #define EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT 25u
3187 #define EIM_EICHDn_WORD0_CHKBIT_MASK_WIDTH 7u
3188 #define EIM_EICHDn_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT))&EIM_EICHDn_WORD0_CHKBIT_MASK_MASK)
3189 /* EICHDn_WORD1 Bit Fields */
3190 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK 0xFFFFFFFFu
3191 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT 0u
3192 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_WIDTH 32u
3193 #define EIM_EICHDn_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT))&EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK)
3194  /* end of group EIM_Register_Masks */
3198 
3199  /* end of group EIM_Peripheral_Access_Layer */
3203 
3204 
3205 /* ----------------------------------------------------------------------------
3206  -- ERM Peripheral Access Layer
3207  ---------------------------------------------------------------------------- */
3208 
3216 #define ERM_EARn_COUNT 1u
3217 
3219 typedef struct {
3220  __IO uint32_t CR0;
3221  uint8_t RESERVED_0[12];
3222  __IO uint32_t SR0;
3223  uint8_t RESERVED_1[236];
3224  __I uint32_t EARn[ERM_EARn_COUNT];
3226 
3228 #define ERM_INSTANCE_COUNT (1u)
3229 
3230 
3231 /* ERM - Peripheral instance base addresses */
3233 #define ERM_BASE (0x40018000u)
3234 
3235 #define ERM ((ERM_Type *)ERM_BASE)
3236 
3237 #define ERM_BASE_ADDRS { ERM_BASE }
3238 
3239 #define ERM_BASE_PTRS { ERM }
3240 
3241 #define ERM_IRQS_ARR_COUNT (2u)
3242 
3243 #define ERM_SINGLE_IRQS_CH_COUNT (1u)
3244 
3245 #define ERM_DOUBLE_IRQS_CH_COUNT (1u)
3246 
3247 #define ERM_SINGLE_IRQS { ERM_fault_IRQn }
3248 #define ERM_DOUBLE_IRQS { ERM_fault_IRQn }
3249 
3250 /* ----------------------------------------------------------------------------
3251  -- ERM Register Masks
3252  ---------------------------------------------------------------------------- */
3253 
3259 /* CR0 Bit Fields */
3260 #define ERM_CR0_ENCIE0_MASK 0x40000000u
3261 #define ERM_CR0_ENCIE0_SHIFT 30u
3262 #define ERM_CR0_ENCIE0_WIDTH 1u
3263 #define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE0_SHIFT))&ERM_CR0_ENCIE0_MASK)
3264 #define ERM_CR0_ESCIE0_MASK 0x80000000u
3265 #define ERM_CR0_ESCIE0_SHIFT 31u
3266 #define ERM_CR0_ESCIE0_WIDTH 1u
3267 #define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE0_SHIFT))&ERM_CR0_ESCIE0_MASK)
3268 /* SR0 Bit Fields */
3269 #define ERM_SR0_NCE0_MASK 0x40000000u
3270 #define ERM_SR0_NCE0_SHIFT 30u
3271 #define ERM_SR0_NCE0_WIDTH 1u
3272 #define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE0_SHIFT))&ERM_SR0_NCE0_MASK)
3273 #define ERM_SR0_SBC0_MASK 0x80000000u
3274 #define ERM_SR0_SBC0_SHIFT 31u
3275 #define ERM_SR0_SBC0_WIDTH 1u
3276 #define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC0_SHIFT))&ERM_SR0_SBC0_MASK)
3277 /* EARn Bit Fields */
3278 #define ERM_EARn_EAR_MASK 0xFFFFFFFFu
3279 #define ERM_EARn_EAR_SHIFT 0u
3280 #define ERM_EARn_EAR_WIDTH 32u
3281 #define ERM_EARn_EAR(x) (((uint32_t)(((uint32_t)(x))<<ERM_EARn_EAR_SHIFT))&ERM_EARn_EAR_MASK)
3282  /* end of group ERM_Register_Masks */
3286 
3287  /* end of group ERM_Peripheral_Access_Layer */
3291 
3292 
3293 /* ----------------------------------------------------------------------------
3294  -- FLEXIO Peripheral Access Layer
3295  ---------------------------------------------------------------------------- */
3296 
3304 #define FLEXIO_SHIFTCTL_COUNT 4u
3305 #define FLEXIO_SHIFTCFG_COUNT 4u
3306 #define FLEXIO_SHIFTBUF_COUNT 4u
3307 #define FLEXIO_SHIFTBUFBIS_COUNT 4u
3308 #define FLEXIO_SHIFTBUFBYS_COUNT 4u
3309 #define FLEXIO_SHIFTBUFBBS_COUNT 4u
3310 #define FLEXIO_TIMCTL_COUNT 4u
3311 #define FLEXIO_TIMCFG_COUNT 4u
3312 #define FLEXIO_TIMCMP_COUNT 4u
3313 
3315 typedef struct {
3316  __I uint32_t VERID;
3317  __I uint32_t PARAM;
3318  __IO uint32_t CTRL;
3319  __I uint32_t PIN;
3320  __IO uint32_t SHIFTSTAT;
3321  __IO uint32_t SHIFTERR;
3322  __IO uint32_t TIMSTAT;
3323  uint8_t RESERVED_0[4];
3324  __IO uint32_t SHIFTSIEN;
3325  __IO uint32_t SHIFTEIEN;
3326  __IO uint32_t TIMIEN;
3327  uint8_t RESERVED_1[4];
3328  __IO uint32_t SHIFTSDEN;
3329  uint8_t RESERVED_2[76];
3330  __IO uint32_t SHIFTCTL[FLEXIO_SHIFTCTL_COUNT];
3331  uint8_t RESERVED_3[112];
3332  __IO uint32_t SHIFTCFG[FLEXIO_SHIFTCFG_COUNT];
3333  uint8_t RESERVED_4[240];
3334  __IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT];
3335  uint8_t RESERVED_5[112];
3336  __IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT];
3337  uint8_t RESERVED_6[112];
3338  __IO uint32_t SHIFTBUFBYS[FLEXIO_SHIFTBUFBYS_COUNT];
3339  uint8_t RESERVED_7[112];
3340  __IO uint32_t SHIFTBUFBBS[FLEXIO_SHIFTBUFBBS_COUNT];
3341  uint8_t RESERVED_8[112];
3342  __IO uint32_t TIMCTL[FLEXIO_TIMCTL_COUNT];
3343  uint8_t RESERVED_9[112];
3344  __IO uint32_t TIMCFG[FLEXIO_TIMCFG_COUNT];
3345  uint8_t RESERVED_10[112];
3346  __IO uint32_t TIMCMP[FLEXIO_TIMCMP_COUNT];
3348 
3350 #define FLEXIO_INSTANCE_COUNT (1u)
3351 
3352 
3353 /* FLEXIO - Peripheral instance base addresses */
3355 #define FLEXIO_BASE (0x4005A000u)
3356 
3357 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
3358 
3359 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
3360 
3361 #define FLEXIO_BASE_PTRS { FLEXIO }
3362 
3363 #define FLEXIO_IRQS_ARR_COUNT (1u)
3364 
3365 #define FLEXIO_IRQS_CH_COUNT (1u)
3366 
3367 #define FLEXIO_IRQS { FLEXIO_IRQn }
3368 
3369 /* ----------------------------------------------------------------------------
3370  -- FLEXIO Register Masks
3371  ---------------------------------------------------------------------------- */
3372 
3378 /* VERID Bit Fields */
3379 #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
3380 #define FLEXIO_VERID_FEATURE_SHIFT 0u
3381 #define FLEXIO_VERID_FEATURE_WIDTH 16u
3382 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
3383 #define FLEXIO_VERID_MINOR_MASK 0xFF0000u
3384 #define FLEXIO_VERID_MINOR_SHIFT 16u
3385 #define FLEXIO_VERID_MINOR_WIDTH 8u
3386 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
3387 #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
3388 #define FLEXIO_VERID_MAJOR_SHIFT 24u
3389 #define FLEXIO_VERID_MAJOR_WIDTH 8u
3390 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
3391 /* PARAM Bit Fields */
3392 #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
3393 #define FLEXIO_PARAM_SHIFTER_SHIFT 0u
3394 #define FLEXIO_PARAM_SHIFTER_WIDTH 8u
3395 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
3396 #define FLEXIO_PARAM_TIMER_MASK 0xFF00u
3397 #define FLEXIO_PARAM_TIMER_SHIFT 8u
3398 #define FLEXIO_PARAM_TIMER_WIDTH 8u
3399 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
3400 #define FLEXIO_PARAM_PIN_MASK 0xFF0000u
3401 #define FLEXIO_PARAM_PIN_SHIFT 16u
3402 #define FLEXIO_PARAM_PIN_WIDTH 8u
3403 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
3404 #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
3405 #define FLEXIO_PARAM_TRIGGER_SHIFT 24u
3406 #define FLEXIO_PARAM_TRIGGER_WIDTH 8u
3407 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
3408 /* CTRL Bit Fields */
3409 #define FLEXIO_CTRL_FLEXEN_MASK 0x1u
3410 #define FLEXIO_CTRL_FLEXEN_SHIFT 0u
3411 #define FLEXIO_CTRL_FLEXEN_WIDTH 1u
3412 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
3413 #define FLEXIO_CTRL_SWRST_MASK 0x2u
3414 #define FLEXIO_CTRL_SWRST_SHIFT 1u
3415 #define FLEXIO_CTRL_SWRST_WIDTH 1u
3416 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
3417 #define FLEXIO_CTRL_FASTACC_MASK 0x4u
3418 #define FLEXIO_CTRL_FASTACC_SHIFT 2u
3419 #define FLEXIO_CTRL_FASTACC_WIDTH 1u
3420 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
3421 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u
3422 #define FLEXIO_CTRL_DBGE_SHIFT 30u
3423 #define FLEXIO_CTRL_DBGE_WIDTH 1u
3424 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
3425 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
3426 #define FLEXIO_CTRL_DOZEN_SHIFT 31u
3427 #define FLEXIO_CTRL_DOZEN_WIDTH 1u
3428 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
3429 /* PIN Bit Fields */
3430 #define FLEXIO_PIN_PDI_MASK 0xFFu
3431 #define FLEXIO_PIN_PDI_SHIFT 0u
3432 #define FLEXIO_PIN_PDI_WIDTH 8u
3433 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PIN_PDI_SHIFT))&FLEXIO_PIN_PDI_MASK)
3434 /* SHIFTSTAT Bit Fields */
3435 #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
3436 #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0u
3437 #define FLEXIO_SHIFTSTAT_SSF_WIDTH 4u
3438 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
3439 /* SHIFTERR Bit Fields */
3440 #define FLEXIO_SHIFTERR_SEF_MASK 0xFu
3441 #define FLEXIO_SHIFTERR_SEF_SHIFT 0u
3442 #define FLEXIO_SHIFTERR_SEF_WIDTH 4u
3443 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
3444 /* TIMSTAT Bit Fields */
3445 #define FLEXIO_TIMSTAT_TSF_MASK 0xFu
3446 #define FLEXIO_TIMSTAT_TSF_SHIFT 0u
3447 #define FLEXIO_TIMSTAT_TSF_WIDTH 4u
3448 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
3449 /* SHIFTSIEN Bit Fields */
3450 #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
3451 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0u
3452 #define FLEXIO_SHIFTSIEN_SSIE_WIDTH 4u
3453 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
3454 /* SHIFTEIEN Bit Fields */
3455 #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
3456 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0u
3457 #define FLEXIO_SHIFTEIEN_SEIE_WIDTH 4u
3458 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
3459 /* TIMIEN Bit Fields */
3460 #define FLEXIO_TIMIEN_TEIE_MASK 0xFu
3461 #define FLEXIO_TIMIEN_TEIE_SHIFT 0u
3462 #define FLEXIO_TIMIEN_TEIE_WIDTH 4u
3463 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
3464 /* SHIFTSDEN Bit Fields */
3465 #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
3466 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0u
3467 #define FLEXIO_SHIFTSDEN_SSDE_WIDTH 4u
3468 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
3469 /* SHIFTCTL Bit Fields */
3470 #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
3471 #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0u
3472 #define FLEXIO_SHIFTCTL_SMOD_WIDTH 3u
3473 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
3474 #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
3475 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7u
3476 #define FLEXIO_SHIFTCTL_PINPOL_WIDTH 1u
3477 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
3478 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
3479 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8u
3480 #define FLEXIO_SHIFTCTL_PINSEL_WIDTH 3u
3481 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
3482 #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
3483 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16u
3484 #define FLEXIO_SHIFTCTL_PINCFG_WIDTH 2u
3485 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
3486 #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
3487 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23u
3488 #define FLEXIO_SHIFTCTL_TIMPOL_WIDTH 1u
3489 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
3490 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
3491 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24u
3492 #define FLEXIO_SHIFTCTL_TIMSEL_WIDTH 2u
3493 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
3494 /* SHIFTCFG Bit Fields */
3495 #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
3496 #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0u
3497 #define FLEXIO_SHIFTCFG_SSTART_WIDTH 2u
3498 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
3499 #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
3500 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4u
3501 #define FLEXIO_SHIFTCFG_SSTOP_WIDTH 2u
3502 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
3503 #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
3504 #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8u
3505 #define FLEXIO_SHIFTCFG_INSRC_WIDTH 1u
3506 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
3507 /* SHIFTBUF Bit Fields */
3508 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
3509 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0u
3510 #define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH 32u
3511 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
3512 /* SHIFTBUFBIS Bit Fields */
3513 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
3514 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0u
3515 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH 32u
3516 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
3517 /* SHIFTBUFBYS Bit Fields */
3518 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
3519 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0u
3520 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH 32u
3521 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
3522 /* SHIFTBUFBBS Bit Fields */
3523 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
3524 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0u
3525 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH 32u
3526 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
3527 /* TIMCTL Bit Fields */
3528 #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
3529 #define FLEXIO_TIMCTL_TIMOD_SHIFT 0u
3530 #define FLEXIO_TIMCTL_TIMOD_WIDTH 2u
3531 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
3532 #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
3533 #define FLEXIO_TIMCTL_PINPOL_SHIFT 7u
3534 #define FLEXIO_TIMCTL_PINPOL_WIDTH 1u
3535 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
3536 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
3537 #define FLEXIO_TIMCTL_PINSEL_SHIFT 8u
3538 #define FLEXIO_TIMCTL_PINSEL_WIDTH 3u
3539 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
3540 #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
3541 #define FLEXIO_TIMCTL_PINCFG_SHIFT 16u
3542 #define FLEXIO_TIMCTL_PINCFG_WIDTH 2u
3543 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
3544 #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
3545 #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22u
3546 #define FLEXIO_TIMCTL_TRGSRC_WIDTH 1u
3547 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
3548 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
3549 #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23u
3550 #define FLEXIO_TIMCTL_TRGPOL_WIDTH 1u
3551 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
3552 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
3553 #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24u
3554 #define FLEXIO_TIMCTL_TRGSEL_WIDTH 4u
3555 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
3556 /* TIMCFG Bit Fields */
3557 #define FLEXIO_TIMCFG_TSTART_MASK 0x2u
3558 #define FLEXIO_TIMCFG_TSTART_SHIFT 1u
3559 #define FLEXIO_TIMCFG_TSTART_WIDTH 1u
3560 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
3561 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
3562 #define FLEXIO_TIMCFG_TSTOP_SHIFT 4u
3563 #define FLEXIO_TIMCFG_TSTOP_WIDTH 2u
3564 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
3565 #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
3566 #define FLEXIO_TIMCFG_TIMENA_SHIFT 8u
3567 #define FLEXIO_TIMCFG_TIMENA_WIDTH 3u
3568 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
3569 #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
3570 #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12u
3571 #define FLEXIO_TIMCFG_TIMDIS_WIDTH 3u
3572 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
3573 #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
3574 #define FLEXIO_TIMCFG_TIMRST_SHIFT 16u
3575 #define FLEXIO_TIMCFG_TIMRST_WIDTH 3u
3576 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
3577 #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
3578 #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20u
3579 #define FLEXIO_TIMCFG_TIMDEC_WIDTH 2u
3580 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
3581 #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
3582 #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24u
3583 #define FLEXIO_TIMCFG_TIMOUT_WIDTH 2u
3584 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
3585 /* TIMCMP Bit Fields */
3586 #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
3587 #define FLEXIO_TIMCMP_CMP_SHIFT 0u
3588 #define FLEXIO_TIMCMP_CMP_WIDTH 16u
3589 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
3590  /* end of group FLEXIO_Register_Masks */
3594 
3595  /* end of group FLEXIO_Peripheral_Access_Layer */
3599 
3600 
3601 /* ----------------------------------------------------------------------------
3602  -- FTFC Peripheral Access Layer
3603  ---------------------------------------------------------------------------- */
3604 
3612 #define FTFC_FCCOB_COUNT 12u
3613 #define FTFC_FPROT_COUNT 4u
3614 
3616 typedef struct {
3617  __IO uint8_t FSTAT;
3618  __IO uint8_t FCNFG;
3619  __I uint8_t FSEC;
3620  __I uint8_t FOPT;
3621  __IO uint8_t FCCOB[FTFC_FCCOB_COUNT];
3622  __IO uint8_t FPROT[FTFC_FPROT_COUNT];
3623  uint8_t RESERVED_0[2];
3624  __IO uint8_t FEPROT;
3625  __IO uint8_t FDPROT;
3626  uint8_t RESERVED_1[20];
3627  __I uint8_t FCSESTAT;
3628  uint8_t RESERVED_2[1];
3629  __IO uint8_t FERSTAT;
3630  __IO uint8_t FERCNFG;
3632 
3634 #define FTFC_INSTANCE_COUNT (1u)
3635 
3636 
3637 /* FTFC - Peripheral instance base addresses */
3639 #define FTFC_BASE (0x40020000u)
3640 
3641 #define FTFC ((FTFC_Type *)FTFC_BASE)
3642 
3643 #define FTFC_BASE_ADDRS { FTFC_BASE }
3644 
3645 #define FTFC_BASE_PTRS { FTFC }
3646 
3647 #define FTFC_IRQS_ARR_COUNT (2u)
3648 
3649 #define FTFC_COMMAND_COMPLETE_IRQS_CH_COUNT (1u)
3650 
3651 #define FTFC_READ_COLLISION_IRQS_CH_COUNT (1u)
3652 
3653 #define FTFC_COMMAND_COMPLETE_IRQS { FTFC_IRQn }
3654 #define FTFC_READ_COLLISION_IRQS { FTFC_IRQn }
3655 
3656 /* ----------------------------------------------------------------------------
3657  -- FTFC Register Masks
3658  ---------------------------------------------------------------------------- */
3659 
3665 /* FSTAT Bit Fields */
3666 #define FTFC_FSTAT_MGSTAT0_MASK 0x1u
3667 #define FTFC_FSTAT_MGSTAT0_SHIFT 0u
3668 #define FTFC_FSTAT_MGSTAT0_WIDTH 1u
3669 #define FTFC_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_MGSTAT0_SHIFT))&FTFC_FSTAT_MGSTAT0_MASK)
3670 #define FTFC_FSTAT_FPVIOL_MASK 0x10u
3671 #define FTFC_FSTAT_FPVIOL_SHIFT 4u
3672 #define FTFC_FSTAT_FPVIOL_WIDTH 1u
3673 #define FTFC_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_FPVIOL_SHIFT))&FTFC_FSTAT_FPVIOL_MASK)
3674 #define FTFC_FSTAT_ACCERR_MASK 0x20u
3675 #define FTFC_FSTAT_ACCERR_SHIFT 5u
3676 #define FTFC_FSTAT_ACCERR_WIDTH 1u
3677 #define FTFC_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_ACCERR_SHIFT))&FTFC_FSTAT_ACCERR_MASK)
3678 #define FTFC_FSTAT_RDCOLERR_MASK 0x40u
3679 #define FTFC_FSTAT_RDCOLERR_SHIFT 6u
3680 #define FTFC_FSTAT_RDCOLERR_WIDTH 1u
3681 #define FTFC_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_RDCOLERR_SHIFT))&FTFC_FSTAT_RDCOLERR_MASK)
3682 #define FTFC_FSTAT_CCIF_MASK 0x80u
3683 #define FTFC_FSTAT_CCIF_SHIFT 7u
3684 #define FTFC_FSTAT_CCIF_WIDTH 1u
3685 #define FTFC_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_CCIF_SHIFT))&FTFC_FSTAT_CCIF_MASK)
3686 /* FCNFG Bit Fields */
3687 #define FTFC_FCNFG_EEERDY_MASK 0x1u
3688 #define FTFC_FCNFG_EEERDY_SHIFT 0u
3689 #define FTFC_FCNFG_EEERDY_WIDTH 1u
3690 #define FTFC_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_EEERDY_SHIFT))&FTFC_FCNFG_EEERDY_MASK)
3691 #define FTFC_FCNFG_RAMRDY_MASK 0x2u
3692 #define FTFC_FCNFG_RAMRDY_SHIFT 1u
3693 #define FTFC_FCNFG_RAMRDY_WIDTH 1u
3694 #define FTFC_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RAMRDY_SHIFT))&FTFC_FCNFG_RAMRDY_MASK)
3695 #define FTFC_FCNFG_ERSSUSP_MASK 0x10u
3696 #define FTFC_FCNFG_ERSSUSP_SHIFT 4u
3697 #define FTFC_FCNFG_ERSSUSP_WIDTH 1u
3698 #define FTFC_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSSUSP_SHIFT))&FTFC_FCNFG_ERSSUSP_MASK)
3699 #define FTFC_FCNFG_ERSAREQ_MASK 0x20u
3700 #define FTFC_FCNFG_ERSAREQ_SHIFT 5u
3701 #define FTFC_FCNFG_ERSAREQ_WIDTH 1u
3702 #define FTFC_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSAREQ_SHIFT))&FTFC_FCNFG_ERSAREQ_MASK)
3703 #define FTFC_FCNFG_RDCOLLIE_MASK 0x40u
3704 #define FTFC_FCNFG_RDCOLLIE_SHIFT 6u
3705 #define FTFC_FCNFG_RDCOLLIE_WIDTH 1u
3706 #define FTFC_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RDCOLLIE_SHIFT))&FTFC_FCNFG_RDCOLLIE_MASK)
3707 #define FTFC_FCNFG_CCIE_MASK 0x80u
3708 #define FTFC_FCNFG_CCIE_SHIFT 7u
3709 #define FTFC_FCNFG_CCIE_WIDTH 1u
3710 #define FTFC_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_CCIE_SHIFT))&FTFC_FCNFG_CCIE_MASK)
3711 /* FSEC Bit Fields */
3712 #define FTFC_FSEC_SEC_MASK 0x3u
3713 #define FTFC_FSEC_SEC_SHIFT 0u
3714 #define FTFC_FSEC_SEC_WIDTH 2u
3715 #define FTFC_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_SEC_SHIFT))&FTFC_FSEC_SEC_MASK)
3716 #define FTFC_FSEC_FSLACC_MASK 0xCu
3717 #define FTFC_FSEC_FSLACC_SHIFT 2u
3718 #define FTFC_FSEC_FSLACC_WIDTH 2u
3719 #define FTFC_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_FSLACC_SHIFT))&FTFC_FSEC_FSLACC_MASK)
3720 #define FTFC_FSEC_MEEN_MASK 0x30u
3721 #define FTFC_FSEC_MEEN_SHIFT 4u
3722 #define FTFC_FSEC_MEEN_WIDTH 2u
3723 #define FTFC_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_MEEN_SHIFT))&FTFC_FSEC_MEEN_MASK)
3724 #define FTFC_FSEC_KEYEN_MASK 0xC0u
3725 #define FTFC_FSEC_KEYEN_SHIFT 6u
3726 #define FTFC_FSEC_KEYEN_WIDTH 2u
3727 #define FTFC_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_KEYEN_SHIFT))&FTFC_FSEC_KEYEN_MASK)
3728 /* FOPT Bit Fields */
3729 #define FTFC_FOPT_OPT_MASK 0xFFu
3730 #define FTFC_FOPT_OPT_SHIFT 0u
3731 #define FTFC_FOPT_OPT_WIDTH 8u
3732 #define FTFC_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FOPT_OPT_SHIFT))&FTFC_FOPT_OPT_MASK)
3733 /* FCCOB Bit Fields */
3734 #define FTFC_FCCOB_CCOBn_MASK 0xFFu
3735 #define FTFC_FCCOB_CCOBn_SHIFT 0u
3736 #define FTFC_FCCOB_CCOBn_WIDTH 8u
3737 #define FTFC_FCCOB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCCOB_CCOBn_SHIFT))&FTFC_FCCOB_CCOBn_MASK)
3738 /* FPROT Bit Fields */
3739 #define FTFC_FPROT_PROT_MASK 0xFFu
3740 #define FTFC_FPROT_PROT_SHIFT 0u
3741 #define FTFC_FPROT_PROT_WIDTH 8u
3742 #define FTFC_FPROT_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FPROT_PROT_SHIFT))&FTFC_FPROT_PROT_MASK)
3743 /* FEPROT Bit Fields */
3744 #define FTFC_FEPROT_EPROT_MASK 0xFFu
3745 #define FTFC_FEPROT_EPROT_SHIFT 0u
3746 #define FTFC_FEPROT_EPROT_WIDTH 8u
3747 #define FTFC_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FEPROT_EPROT_SHIFT))&FTFC_FEPROT_EPROT_MASK)
3748 /* FDPROT Bit Fields */
3749 #define FTFC_FDPROT_DPROT_MASK 0xFFu
3750 #define FTFC_FDPROT_DPROT_SHIFT 0u
3751 #define FTFC_FDPROT_DPROT_WIDTH 8u
3752 #define FTFC_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FDPROT_DPROT_SHIFT))&FTFC_FDPROT_DPROT_MASK)
3753 /* FCSESTAT Bit Fields */
3754 #define FTFC_FCSESTAT_BSY_MASK 0x1u
3755 #define FTFC_FCSESTAT_BSY_SHIFT 0u
3756 #define FTFC_FCSESTAT_BSY_WIDTH 1u
3757 #define FTFC_FCSESTAT_BSY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BSY_SHIFT))&FTFC_FCSESTAT_BSY_MASK)
3758 #define FTFC_FCSESTAT_SB_MASK 0x2u
3759 #define FTFC_FCSESTAT_SB_SHIFT 1u
3760 #define FTFC_FCSESTAT_SB_WIDTH 1u
3761 #define FTFC_FCSESTAT_SB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_SB_SHIFT))&FTFC_FCSESTAT_SB_MASK)
3762 #define FTFC_FCSESTAT_BIN_MASK 0x4u
3763 #define FTFC_FCSESTAT_BIN_SHIFT 2u
3764 #define FTFC_FCSESTAT_BIN_WIDTH 1u
3765 #define FTFC_FCSESTAT_BIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BIN_SHIFT))&FTFC_FCSESTAT_BIN_MASK)
3766 #define FTFC_FCSESTAT_BFN_MASK 0x8u
3767 #define FTFC_FCSESTAT_BFN_SHIFT 3u
3768 #define FTFC_FCSESTAT_BFN_WIDTH 1u
3769 #define FTFC_FCSESTAT_BFN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BFN_SHIFT))&FTFC_FCSESTAT_BFN_MASK)
3770 #define FTFC_FCSESTAT_BOK_MASK 0x10u
3771 #define FTFC_FCSESTAT_BOK_SHIFT 4u
3772 #define FTFC_FCSESTAT_BOK_WIDTH 1u
3773 #define FTFC_FCSESTAT_BOK(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BOK_SHIFT))&FTFC_FCSESTAT_BOK_MASK)
3774 #define FTFC_FCSESTAT_RIN_MASK 0x20u
3775 #define FTFC_FCSESTAT_RIN_SHIFT 5u
3776 #define FTFC_FCSESTAT_RIN_WIDTH 1u
3777 #define FTFC_FCSESTAT_RIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_RIN_SHIFT))&FTFC_FCSESTAT_RIN_MASK)
3778 #define FTFC_FCSESTAT_EDB_MASK 0x40u
3779 #define FTFC_FCSESTAT_EDB_SHIFT 6u
3780 #define FTFC_FCSESTAT_EDB_WIDTH 1u
3781 #define FTFC_FCSESTAT_EDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_EDB_SHIFT))&FTFC_FCSESTAT_EDB_MASK)
3782 #define FTFC_FCSESTAT_IDB_MASK 0x80u
3783 #define FTFC_FCSESTAT_IDB_SHIFT 7u
3784 #define FTFC_FCSESTAT_IDB_WIDTH 1u
3785 #define FTFC_FCSESTAT_IDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_IDB_SHIFT))&FTFC_FCSESTAT_IDB_MASK)
3786 /* FERSTAT Bit Fields */
3787 #define FTFC_FERSTAT_DFDIF_MASK 0x2u
3788 #define FTFC_FERSTAT_DFDIF_SHIFT 1u
3789 #define FTFC_FERSTAT_DFDIF_WIDTH 1u
3790 #define FTFC_FERSTAT_DFDIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERSTAT_DFDIF_SHIFT))&FTFC_FERSTAT_DFDIF_MASK)
3791 /* FERCNFG Bit Fields */
3792 #define FTFC_FERCNFG_DFDIE_MASK 0x2u
3793 #define FTFC_FERCNFG_DFDIE_SHIFT 1u
3794 #define FTFC_FERCNFG_DFDIE_WIDTH 1u
3795 #define FTFC_FERCNFG_DFDIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_DFDIE_SHIFT))&FTFC_FERCNFG_DFDIE_MASK)
3796 #define FTFC_FERCNFG_FDFD_MASK 0x20u
3797 #define FTFC_FERCNFG_FDFD_SHIFT 5u
3798 #define FTFC_FERCNFG_FDFD_WIDTH 1u
3799 #define FTFC_FERCNFG_FDFD(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_FDFD_SHIFT))&FTFC_FERCNFG_FDFD_MASK)
3800  /* end of group FTFC_Register_Masks */
3804 
3805  /* end of group FTFC_Peripheral_Access_Layer */
3809 
3810 
3811 /* ----------------------------------------------------------------------------
3812  -- FTM Peripheral Access Layer
3813  ---------------------------------------------------------------------------- */
3814 
3822 #define FTM_CONTROLS_COUNT 8u
3823 #define FTM_CV_MIRROR_COUNT 8u
3824 
3826 typedef struct {
3827  __IO uint32_t SC;
3828  __IO uint32_t CNT;
3829  __IO uint32_t MOD;
3830  struct { /* offset: 0xC, array step: 0x8 */
3831  __IO uint32_t CnSC;
3832  __IO uint32_t CnV;
3833  } CONTROLS[FTM_CONTROLS_COUNT];
3834  __IO uint32_t CNTIN;
3835  __IO uint32_t STATUS;
3836  __IO uint32_t MODE;
3837  __IO uint32_t SYNC;
3838  __IO uint32_t OUTINIT;
3839  __IO uint32_t OUTMASK;
3840  __IO uint32_t COMBINE;
3841  __IO uint32_t DEADTIME;
3842  __IO uint32_t EXTTRIG;
3843  __IO uint32_t POL;
3844  __IO uint32_t FMS;
3845  __IO uint32_t FILTER;
3846  __IO uint32_t FLTCTRL;
3847  __IO uint32_t QDCTRL;
3848  __IO uint32_t CONF;
3849  __IO uint32_t FLTPOL;
3850  __IO uint32_t SYNCONF;
3851  __IO uint32_t INVCTRL;
3852  __IO uint32_t SWOCTRL;
3853  __IO uint32_t PWMLOAD;
3854  __IO uint32_t HCR;
3855  __IO uint32_t PAIR0DEADTIME;
3856  uint8_t RESERVED_0[4];
3857  __IO uint32_t PAIR1DEADTIME;
3858  uint8_t RESERVED_1[4];
3859  __IO uint32_t PAIR2DEADTIME;
3860  uint8_t RESERVED_2[4];
3861  __IO uint32_t PAIR3DEADTIME;
3862  uint8_t RESERVED_3[324];
3863  __IO uint32_t MOD_MIRROR;
3864  __IO uint32_t CV_MIRROR[FTM_CV_MIRROR_COUNT];
3866 
3868 #define FTM_INSTANCE_COUNT (2u)
3869 
3870 
3871 /* FTM - Peripheral instance base addresses */
3873 #define FTM0_BASE (0x40038000u)
3874 
3875 #define FTM0 ((FTM_Type *)FTM0_BASE)
3876 
3877 #define FTM1_BASE (0x40039000u)
3878 
3879 #define FTM1 ((FTM_Type *)FTM1_BASE)
3880 
3881 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE }
3882 
3883 #define FTM_BASE_PTRS { FTM0, FTM1 }
3884 
3885 #define FTM_IRQS_ARR_COUNT (4u)
3886 
3887 #define FTM_IRQS_CH_COUNT (8u)
3888 
3889 #define FTM_Fault_IRQS_CH_COUNT (1u)
3890 
3891 #define FTM_Overflow_IRQS_CH_COUNT (1u)
3892 
3893 #define FTM_Reload_IRQS_CH_COUNT (1u)
3894 
3895 #define FTM_IRQS { { FTM0_Ch0_7_IRQn, FTM0_Ch0_7_IRQn, FTM0_Ch0_7_IRQn, FTM0_Ch0_7_IRQn, FTM0_Ch0_7_IRQn, FTM0_Ch0_7_IRQn, FTM0_Ch0_7_IRQn, FTM0_Ch0_7_IRQn }, \
3896  { FTM1_Ch0_7_IRQn, FTM1_Ch0_7_IRQn, FTM1_Ch0_7_IRQn, FTM1_Ch0_7_IRQn, FTM1_Ch0_7_IRQn, FTM1_Ch0_7_IRQn, FTM1_Ch0_7_IRQn, FTM1_Ch0_7_IRQn } }
3897 #define FTM_Fault_IRQS { FTM0_Fault_IRQn, FTM1_Fault_IRQn }
3898 #define FTM_Overflow_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn }
3899 #define FTM_Reload_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn }
3900 
3901 /* ----------------------------------------------------------------------------
3902  -- FTM Register Masks
3903  ---------------------------------------------------------------------------- */
3904 
3910 /* SC Bit Fields */
3911 #define FTM_SC_PS_MASK 0x7u
3912 #define FTM_SC_PS_SHIFT 0u
3913 #define FTM_SC_PS_WIDTH 3u
3914 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
3915 #define FTM_SC_CLKS_MASK 0x18u
3916 #define FTM_SC_CLKS_SHIFT 3u
3917 #define FTM_SC_CLKS_WIDTH 2u
3918 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
3919 #define FTM_SC_CPWMS_MASK 0x20u
3920 #define FTM_SC_CPWMS_SHIFT 5u
3921 #define FTM_SC_CPWMS_WIDTH 1u
3922 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
3923 #define FTM_SC_RIE_MASK 0x40u
3924 #define FTM_SC_RIE_SHIFT 6u
3925 #define FTM_SC_RIE_WIDTH 1u
3926 #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RIE_SHIFT))&FTM_SC_RIE_MASK)
3927 #define FTM_SC_RF_MASK 0x80u
3928 #define FTM_SC_RF_SHIFT 7u
3929 #define FTM_SC_RF_WIDTH 1u
3930 #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RF_SHIFT))&FTM_SC_RF_MASK)
3931 #define FTM_SC_TOIE_MASK 0x100u
3932 #define FTM_SC_TOIE_SHIFT 8u
3933 #define FTM_SC_TOIE_WIDTH 1u
3934 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
3935 #define FTM_SC_TOF_MASK 0x200u
3936 #define FTM_SC_TOF_SHIFT 9u
3937 #define FTM_SC_TOF_WIDTH 1u
3938 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
3939 #define FTM_SC_PWMEN0_MASK 0x10000u
3940 #define FTM_SC_PWMEN0_SHIFT 16u
3941 #define FTM_SC_PWMEN0_WIDTH 1u
3942 #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN0_SHIFT))&FTM_SC_PWMEN0_MASK)
3943 #define FTM_SC_PWMEN1_MASK 0x20000u
3944 #define FTM_SC_PWMEN1_SHIFT 17u
3945 #define FTM_SC_PWMEN1_WIDTH 1u
3946 #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN1_SHIFT))&FTM_SC_PWMEN1_MASK)
3947 #define FTM_SC_PWMEN2_MASK 0x40000u
3948 #define FTM_SC_PWMEN2_SHIFT 18u
3949 #define FTM_SC_PWMEN2_WIDTH 1u
3950 #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN2_SHIFT))&FTM_SC_PWMEN2_MASK)
3951 #define FTM_SC_PWMEN3_MASK 0x80000u
3952 #define FTM_SC_PWMEN3_SHIFT 19u
3953 #define FTM_SC_PWMEN3_WIDTH 1u
3954 #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN3_SHIFT))&FTM_SC_PWMEN3_MASK)
3955 #define FTM_SC_PWMEN4_MASK 0x100000u
3956 #define FTM_SC_PWMEN4_SHIFT 20u
3957 #define FTM_SC_PWMEN4_WIDTH 1u
3958 #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN4_SHIFT))&FTM_SC_PWMEN4_MASK)
3959 #define FTM_SC_PWMEN5_MASK 0x200000u
3960 #define FTM_SC_PWMEN5_SHIFT 21u
3961 #define FTM_SC_PWMEN5_WIDTH 1u
3962 #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN5_SHIFT))&FTM_SC_PWMEN5_MASK)
3963 #define FTM_SC_PWMEN6_MASK 0x400000u
3964 #define FTM_SC_PWMEN6_SHIFT 22u
3965 #define FTM_SC_PWMEN6_WIDTH 1u
3966 #define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN6_SHIFT))&FTM_SC_PWMEN6_MASK)
3967 #define FTM_SC_PWMEN7_MASK 0x800000u
3968 #define FTM_SC_PWMEN7_SHIFT 23u
3969 #define FTM_SC_PWMEN7_WIDTH 1u
3970 #define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN7_SHIFT))&FTM_SC_PWMEN7_MASK)
3971 #define FTM_SC_FLTPS_MASK 0xF000000u
3972 #define FTM_SC_FLTPS_SHIFT 24u
3973 #define FTM_SC_FLTPS_WIDTH 4u
3974 #define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_FLTPS_SHIFT))&FTM_SC_FLTPS_MASK)
3975 /* CNT Bit Fields */
3976 #define FTM_CNT_COUNT_MASK 0xFFFFu
3977 #define FTM_CNT_COUNT_SHIFT 0u
3978 #define FTM_CNT_COUNT_WIDTH 16u
3979 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
3980 /* MOD Bit Fields */
3981 #define FTM_MOD_MOD_MASK 0xFFFFu
3982 #define FTM_MOD_MOD_SHIFT 0u
3983 #define FTM_MOD_MOD_WIDTH 16u
3984 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
3985 /* CnSC Bit Fields */
3986 #define FTM_CnSC_DMA_MASK 0x1u
3987 #define FTM_CnSC_DMA_SHIFT 0u
3988 #define FTM_CnSC_DMA_WIDTH 1u
3989 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
3990 #define FTM_CnSC_ICRST_MASK 0x2u
3991 #define FTM_CnSC_ICRST_SHIFT 1u
3992 #define FTM_CnSC_ICRST_WIDTH 1u
3993 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ICRST_SHIFT))&FTM_CnSC_ICRST_MASK)
3994 #define FTM_CnSC_ELSA_MASK 0x4u
3995 #define FTM_CnSC_ELSA_SHIFT 2u
3996 #define FTM_CnSC_ELSA_WIDTH 1u
3997 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
3998 #define FTM_CnSC_ELSB_MASK 0x8u
3999 #define FTM_CnSC_ELSB_SHIFT 3u
4000 #define FTM_CnSC_ELSB_WIDTH 1u
4001 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
4002 #define FTM_CnSC_MSA_MASK 0x10u
4003 #define FTM_CnSC_MSA_SHIFT 4u
4004 #define FTM_CnSC_MSA_WIDTH 1u
4005 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
4006 #define FTM_CnSC_MSB_MASK 0x20u
4007 #define FTM_CnSC_MSB_SHIFT 5u
4008 #define FTM_CnSC_MSB_WIDTH 1u
4009 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
4010 #define FTM_CnSC_CHIE_MASK 0x40u
4011 #define FTM_CnSC_CHIE_SHIFT 6u
4012 #define FTM_CnSC_CHIE_WIDTH 1u
4013 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
4014 #define FTM_CnSC_CHF_MASK 0x80u
4015 #define FTM_CnSC_CHF_SHIFT 7u
4016 #define FTM_CnSC_CHF_WIDTH 1u
4017 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
4018 #define FTM_CnSC_TRIGMODE_MASK 0x100u
4019 #define FTM_CnSC_TRIGMODE_SHIFT 8u
4020 #define FTM_CnSC_TRIGMODE_WIDTH 1u
4021 #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_TRIGMODE_SHIFT))&FTM_CnSC_TRIGMODE_MASK)
4022 #define FTM_CnSC_CHIS_MASK 0x200u
4023 #define FTM_CnSC_CHIS_SHIFT 9u
4024 #define FTM_CnSC_CHIS_WIDTH 1u
4025 #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIS_SHIFT))&FTM_CnSC_CHIS_MASK)
4026 #define FTM_CnSC_CHOV_MASK 0x400u
4027 #define FTM_CnSC_CHOV_SHIFT 10u
4028 #define FTM_CnSC_CHOV_WIDTH 1u
4029 #define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHOV_SHIFT))&FTM_CnSC_CHOV_MASK)
4030 /* CnV Bit Fields */
4031 #define FTM_CnV_VAL_MASK 0xFFFFu
4032 #define FTM_CnV_VAL_SHIFT 0u
4033 #define FTM_CnV_VAL_WIDTH 16u
4034 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
4035 /* CNTIN Bit Fields */
4036 #define FTM_CNTIN_INIT_MASK 0xFFFFu
4037 #define FTM_CNTIN_INIT_SHIFT 0u
4038 #define FTM_CNTIN_INIT_WIDTH 16u
4039 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
4040 /* STATUS Bit Fields */
4041 #define FTM_STATUS_CH0F_MASK 0x1u
4042 #define FTM_STATUS_CH0F_SHIFT 0u
4043 #define FTM_STATUS_CH0F_WIDTH 1u
4044 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
4045 #define FTM_STATUS_CH1F_MASK 0x2u
4046 #define FTM_STATUS_CH1F_SHIFT 1u
4047 #define FTM_STATUS_CH1F_WIDTH 1u
4048 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
4049 #define FTM_STATUS_CH2F_MASK 0x4u
4050 #define FTM_STATUS_CH2F_SHIFT 2u
4051 #define FTM_STATUS_CH2F_WIDTH 1u
4052 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
4053 #define FTM_STATUS_CH3F_MASK 0x8u
4054 #define FTM_STATUS_CH3F_SHIFT 3u
4055 #define FTM_STATUS_CH3F_WIDTH 1u
4056 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
4057 #define FTM_STATUS_CH4F_MASK 0x10u
4058 #define FTM_STATUS_CH4F_SHIFT 4u
4059 #define FTM_STATUS_CH4F_WIDTH 1u
4060 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
4061 #define FTM_STATUS_CH5F_MASK 0x20u
4062 #define FTM_STATUS_CH5F_SHIFT 5u
4063 #define FTM_STATUS_CH5F_WIDTH 1u
4064 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
4065 #define FTM_STATUS_CH6F_MASK 0x40u
4066 #define FTM_STATUS_CH6F_SHIFT 6u
4067 #define FTM_STATUS_CH6F_WIDTH 1u
4068 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
4069 #define FTM_STATUS_CH7F_MASK 0x80u
4070 #define FTM_STATUS_CH7F_SHIFT 7u
4071 #define FTM_STATUS_CH7F_WIDTH 1u
4072 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
4073 /* MODE Bit Fields */
4074 #define FTM_MODE_FTMEN_MASK 0x1u
4075 #define FTM_MODE_FTMEN_SHIFT 0u
4076 #define FTM_MODE_FTMEN_WIDTH 1u
4077 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
4078 #define FTM_MODE_INIT_MASK 0x2u
4079 #define FTM_MODE_INIT_SHIFT 1u
4080 #define FTM_MODE_INIT_WIDTH 1u
4081 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
4082 #define FTM_MODE_WPDIS_MASK 0x4u
4083 #define FTM_MODE_WPDIS_SHIFT 2u
4084 #define FTM_MODE_WPDIS_WIDTH 1u
4085 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
4086 #define FTM_MODE_PWMSYNC_MASK 0x8u
4087 #define FTM_MODE_PWMSYNC_SHIFT 3u
4088 #define FTM_MODE_PWMSYNC_WIDTH 1u
4089 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
4090 #define FTM_MODE_CAPTEST_MASK 0x10u
4091 #define FTM_MODE_CAPTEST_SHIFT 4u
4092 #define FTM_MODE_CAPTEST_WIDTH 1u
4093 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
4094 #define FTM_MODE_FAULTM_MASK 0x60u
4095 #define FTM_MODE_FAULTM_SHIFT 5u
4096 #define FTM_MODE_FAULTM_WIDTH 2u
4097 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
4098 #define FTM_MODE_FAULTIE_MASK 0x80u
4099 #define FTM_MODE_FAULTIE_SHIFT 7u
4100 #define FTM_MODE_FAULTIE_WIDTH 1u
4101 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
4102 /* SYNC Bit Fields */
4103 #define FTM_SYNC_CNTMIN_MASK 0x1u
4104 #define FTM_SYNC_CNTMIN_SHIFT 0u
4105 #define FTM_SYNC_CNTMIN_WIDTH 1u
4106 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
4107 #define FTM_SYNC_CNTMAX_MASK 0x2u
4108 #define FTM_SYNC_CNTMAX_SHIFT 1u
4109 #define FTM_SYNC_CNTMAX_WIDTH 1u
4110 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
4111 #define FTM_SYNC_REINIT_MASK 0x4u
4112 #define FTM_SYNC_REINIT_SHIFT 2u
4113 #define FTM_SYNC_REINIT_WIDTH 1u
4114 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
4115 #define FTM_SYNC_SYNCHOM_MASK 0x8u
4116 #define FTM_SYNC_SYNCHOM_SHIFT 3u
4117 #define FTM_SYNC_SYNCHOM_WIDTH 1u
4118 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
4119 #define FTM_SYNC_TRIG0_MASK 0x10u
4120 #define FTM_SYNC_TRIG0_SHIFT 4u
4121 #define FTM_SYNC_TRIG0_WIDTH 1u
4122 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
4123 #define FTM_SYNC_TRIG1_MASK 0x20u
4124 #define FTM_SYNC_TRIG1_SHIFT 5u
4125 #define FTM_SYNC_TRIG1_WIDTH 1u
4126 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
4127 #define FTM_SYNC_TRIG2_MASK 0x40u
4128 #define FTM_SYNC_TRIG2_SHIFT 6u
4129 #define FTM_SYNC_TRIG2_WIDTH 1u
4130 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
4131 #define FTM_SYNC_SWSYNC_MASK 0x80u
4132 #define FTM_SYNC_SWSYNC_SHIFT 7u
4133 #define FTM_SYNC_SWSYNC_WIDTH 1u
4134 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
4135 /* OUTINIT Bit Fields */
4136 #define FTM_OUTINIT_CH0OI_MASK 0x1u
4137 #define FTM_OUTINIT_CH0OI_SHIFT 0u
4138 #define FTM_OUTINIT_CH0OI_WIDTH 1u
4139 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
4140 #define FTM_OUTINIT_CH1OI_MASK 0x2u
4141 #define FTM_OUTINIT_CH1OI_SHIFT 1u
4142 #define FTM_OUTINIT_CH1OI_WIDTH 1u
4143 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
4144 #define FTM_OUTINIT_CH2OI_MASK 0x4u
4145 #define FTM_OUTINIT_CH2OI_SHIFT 2u
4146 #define FTM_OUTINIT_CH2OI_WIDTH 1u
4147 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
4148 #define FTM_OUTINIT_CH3OI_MASK 0x8u
4149 #define FTM_OUTINIT_CH3OI_SHIFT 3u
4150 #define FTM_OUTINIT_CH3OI_WIDTH 1u
4151 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
4152 #define FTM_OUTINIT_CH4OI_MASK 0x10u
4153 #define FTM_OUTINIT_CH4OI_SHIFT 4u
4154 #define FTM_OUTINIT_CH4OI_WIDTH 1u
4155 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
4156 #define FTM_OUTINIT_CH5OI_MASK 0x20u
4157 #define FTM_OUTINIT_CH5OI_SHIFT 5u
4158 #define FTM_OUTINIT_CH5OI_WIDTH 1u
4159 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
4160 #define FTM_OUTINIT_CH6OI_MASK 0x40u
4161 #define FTM_OUTINIT_CH6OI_SHIFT 6u
4162 #define FTM_OUTINIT_CH6OI_WIDTH 1u
4163 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
4164 #define FTM_OUTINIT_CH7OI_MASK 0x80u
4165 #define FTM_OUTINIT_CH7OI_SHIFT 7u
4166 #define FTM_OUTINIT_CH7OI_WIDTH 1u
4167 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
4168 /* OUTMASK Bit Fields */
4169 #define FTM_OUTMASK_CH0OM_MASK 0x1u
4170 #define FTM_OUTMASK_CH0OM_SHIFT 0u
4171 #define FTM_OUTMASK_CH0OM_WIDTH 1u
4172 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
4173 #define FTM_OUTMASK_CH1OM_MASK 0x2u
4174 #define FTM_OUTMASK_CH1OM_SHIFT 1u
4175 #define FTM_OUTMASK_CH1OM_WIDTH 1u
4176 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
4177 #define FTM_OUTMASK_CH2OM_MASK 0x4u
4178 #define FTM_OUTMASK_CH2OM_SHIFT 2u
4179 #define FTM_OUTMASK_CH2OM_WIDTH 1u
4180 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
4181 #define FTM_OUTMASK_CH3OM_MASK 0x8u
4182 #define FTM_OUTMASK_CH3OM_SHIFT 3u
4183 #define FTM_OUTMASK_CH3OM_WIDTH 1u
4184 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
4185 #define FTM_OUTMASK_CH4OM_MASK 0x10u
4186 #define FTM_OUTMASK_CH4OM_SHIFT 4u
4187 #define FTM_OUTMASK_CH4OM_WIDTH 1u
4188 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
4189 #define FTM_OUTMASK_CH5OM_MASK 0x20u
4190 #define FTM_OUTMASK_CH5OM_SHIFT 5u
4191 #define FTM_OUTMASK_CH5OM_WIDTH 1u
4192 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
4193 #define FTM_OUTMASK_CH6OM_MASK 0x40u
4194 #define FTM_OUTMASK_CH6OM_SHIFT 6u
4195 #define FTM_OUTMASK_CH6OM_WIDTH 1u
4196 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
4197 #define FTM_OUTMASK_CH7OM_MASK 0x80u
4198 #define FTM_OUTMASK_CH7OM_SHIFT 7u
4199 #define FTM_OUTMASK_CH7OM_WIDTH 1u
4200 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
4201 /* COMBINE Bit Fields */
4202 #define FTM_COMBINE_COMBINE0_MASK 0x1u
4203 #define FTM_COMBINE_COMBINE0_SHIFT 0u
4204 #define FTM_COMBINE_COMBINE0_WIDTH 1u
4205 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
4206 #define FTM_COMBINE_COMP0_MASK 0x2u
4207 #define FTM_COMBINE_COMP0_SHIFT 1u
4208 #define FTM_COMBINE_COMP0_WIDTH 1u
4209 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
4210 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
4211 #define FTM_COMBINE_DECAPEN0_SHIFT 2u
4212 #define FTM_COMBINE_DECAPEN0_WIDTH 1u
4213 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
4214 #define FTM_COMBINE_DECAP0_MASK 0x8u
4215 #define FTM_COMBINE_DECAP0_SHIFT 3u
4216 #define FTM_COMBINE_DECAP0_WIDTH 1u
4217 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
4218 #define FTM_COMBINE_DTEN0_MASK 0x10u
4219 #define FTM_COMBINE_DTEN0_SHIFT 4u
4220 #define FTM_COMBINE_DTEN0_WIDTH 1u
4221 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
4222 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
4223 #define FTM_COMBINE_SYNCEN0_SHIFT 5u
4224 #define FTM_COMBINE_SYNCEN0_WIDTH 1u
4225 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
4226 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
4227 #define FTM_COMBINE_FAULTEN0_SHIFT 6u
4228 #define FTM_COMBINE_FAULTEN0_WIDTH 1u
4229 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
4230 #define FTM_COMBINE_MCOMBINE0_MASK 0x80u
4231 #define FTM_COMBINE_MCOMBINE0_SHIFT 7u
4232 #define FTM_COMBINE_MCOMBINE0_WIDTH 1u
4233 #define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE0_SHIFT))&FTM_COMBINE_MCOMBINE0_MASK)
4234 #define FTM_COMBINE_COMBINE1_MASK 0x100u
4235 #define FTM_COMBINE_COMBINE1_SHIFT 8u
4236 #define FTM_COMBINE_COMBINE1_WIDTH 1u
4237 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
4238 #define FTM_COMBINE_COMP1_MASK 0x200u
4239 #define FTM_COMBINE_COMP1_SHIFT 9u
4240 #define FTM_COMBINE_COMP1_WIDTH 1u
4241 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
4242 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
4243 #define FTM_COMBINE_DECAPEN1_SHIFT 10u
4244 #define FTM_COMBINE_DECAPEN1_WIDTH 1u
4245 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
4246 #define FTM_COMBINE_DECAP1_MASK 0x800u
4247 #define FTM_COMBINE_DECAP1_SHIFT 11u
4248 #define FTM_COMBINE_DECAP1_WIDTH 1u
4249 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
4250 #define FTM_COMBINE_DTEN1_MASK 0x1000u
4251 #define FTM_COMBINE_DTEN1_SHIFT 12u
4252 #define FTM_COMBINE_DTEN1_WIDTH 1u
4253 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
4254 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
4255 #define FTM_COMBINE_SYNCEN1_SHIFT 13u
4256 #define FTM_COMBINE_SYNCEN1_WIDTH 1u
4257 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
4258 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
4259 #define FTM_COMBINE_FAULTEN1_SHIFT 14u
4260 #define FTM_COMBINE_FAULTEN1_WIDTH 1u
4261 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
4262 #define FTM_COMBINE_MCOMBINE1_MASK 0x8000u
4263 #define FTM_COMBINE_MCOMBINE1_SHIFT 15u
4264 #define FTM_COMBINE_MCOMBINE1_WIDTH 1u
4265 #define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE1_SHIFT))&FTM_COMBINE_MCOMBINE1_MASK)
4266 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
4267 #define FTM_COMBINE_COMBINE2_SHIFT 16u
4268 #define FTM_COMBINE_COMBINE2_WIDTH 1u
4269 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
4270 #define FTM_COMBINE_COMP2_MASK 0x20000u
4271 #define FTM_COMBINE_COMP2_SHIFT 17u
4272 #define FTM_COMBINE_COMP2_WIDTH 1u
4273 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
4274 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
4275 #define FTM_COMBINE_DECAPEN2_SHIFT 18u
4276 #define FTM_COMBINE_DECAPEN2_WIDTH 1u
4277 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
4278 #define FTM_COMBINE_DECAP2_MASK 0x80000u
4279 #define FTM_COMBINE_DECAP2_SHIFT 19u
4280 #define FTM_COMBINE_DECAP2_WIDTH 1u
4281 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
4282 #define FTM_COMBINE_DTEN2_MASK 0x100000u
4283 #define FTM_COMBINE_DTEN2_SHIFT 20u
4284 #define FTM_COMBINE_DTEN2_WIDTH 1u
4285 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
4286 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
4287 #define FTM_COMBINE_SYNCEN2_SHIFT 21u
4288 #define FTM_COMBINE_SYNCEN2_WIDTH 1u
4289 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
4290 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
4291 #define FTM_COMBINE_FAULTEN2_SHIFT 22u
4292 #define FTM_COMBINE_FAULTEN2_WIDTH 1u
4293 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
4294 #define FTM_COMBINE_MCOMBINE2_MASK 0x800000u
4295 #define FTM_COMBINE_MCOMBINE2_SHIFT 23u
4296 #define FTM_COMBINE_MCOMBINE2_WIDTH 1u
4297 #define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE2_SHIFT))&FTM_COMBINE_MCOMBINE2_MASK)
4298 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
4299 #define FTM_COMBINE_COMBINE3_SHIFT 24u
4300 #define FTM_COMBINE_COMBINE3_WIDTH 1u
4301 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
4302 #define FTM_COMBINE_COMP3_MASK 0x2000000u
4303 #define FTM_COMBINE_COMP3_SHIFT 25u
4304 #define FTM_COMBINE_COMP3_WIDTH 1u
4305 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
4306 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
4307 #define FTM_COMBINE_DECAPEN3_SHIFT 26u
4308 #define FTM_COMBINE_DECAPEN3_WIDTH 1u
4309 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
4310 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
4311 #define FTM_COMBINE_DECAP3_SHIFT 27u
4312 #define FTM_COMBINE_DECAP3_WIDTH 1u
4313 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
4314 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
4315 #define FTM_COMBINE_DTEN3_SHIFT 28u
4316 #define FTM_COMBINE_DTEN3_WIDTH 1u
4317 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
4318 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
4319 #define FTM_COMBINE_SYNCEN3_SHIFT 29u
4320 #define FTM_COMBINE_SYNCEN3_WIDTH 1u
4321 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
4322 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
4323 #define FTM_COMBINE_FAULTEN3_SHIFT 30u
4324 #define FTM_COMBINE_FAULTEN3_WIDTH 1u
4325 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
4326 #define FTM_COMBINE_MCOMBINE3_MASK 0x80000000u
4327 #define FTM_COMBINE_MCOMBINE3_SHIFT 31u
4328 #define FTM_COMBINE_MCOMBINE3_WIDTH 1u
4329 #define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE3_SHIFT))&FTM_COMBINE_MCOMBINE3_MASK)
4330 /* DEADTIME Bit Fields */
4331 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
4332 #define FTM_DEADTIME_DTVAL_SHIFT 0u
4333 #define FTM_DEADTIME_DTVAL_WIDTH 6u
4334 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
4335 #define FTM_DEADTIME_DTPS_MASK 0xC0u
4336 #define FTM_DEADTIME_DTPS_SHIFT 6u
4337 #define FTM_DEADTIME_DTPS_WIDTH 2u
4338 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
4339 #define FTM_DEADTIME_DTVALEX_MASK 0xF0000u
4340 #define FTM_DEADTIME_DTVALEX_SHIFT 16u
4341 #define FTM_DEADTIME_DTVALEX_WIDTH 4u
4342 #define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVALEX_SHIFT))&FTM_DEADTIME_DTVALEX_MASK)
4343 /* EXTTRIG Bit Fields */
4344 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
4345 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0u
4346 #define FTM_EXTTRIG_CH2TRIG_WIDTH 1u
4347 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
4348 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
4349 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1u
4350 #define FTM_EXTTRIG_CH3TRIG_WIDTH 1u
4351 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
4352 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
4353 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2u
4354 #define FTM_EXTTRIG_CH4TRIG_WIDTH 1u
4355 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
4356 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
4357 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3u
4358 #define FTM_EXTTRIG_CH5TRIG_WIDTH 1u
4359 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
4360 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
4361 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4u
4362 #define FTM_EXTTRIG_CH0TRIG_WIDTH 1u
4363 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
4364 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
4365 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5u
4366 #define FTM_EXTTRIG_CH1TRIG_WIDTH 1u
4367 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
4368 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
4369 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6u
4370 #define FTM_EXTTRIG_INITTRIGEN_WIDTH 1u
4371 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
4372 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
4373 #define FTM_EXTTRIG_TRIGF_SHIFT 7u
4374 #define FTM_EXTTRIG_TRIGF_WIDTH 1u
4375 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
4376 #define FTM_EXTTRIG_CH6TRIG_MASK 0x100u
4377 #define FTM_EXTTRIG_CH6TRIG_SHIFT 8u
4378 #define FTM_EXTTRIG_CH6TRIG_WIDTH 1u
4379 #define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH6TRIG_SHIFT))&FTM_EXTTRIG_CH6TRIG_MASK)
4380 #define FTM_EXTTRIG_CH7TRIG_MASK 0x200u
4381 #define FTM_EXTTRIG_CH7TRIG_SHIFT 9u
4382 #define FTM_EXTTRIG_CH7TRIG_WIDTH 1u
4383 #define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH7TRIG_SHIFT))&FTM_EXTTRIG_CH7TRIG_MASK)
4384 /* POL Bit Fields */
4385 #define FTM_POL_POL0_MASK 0x1u
4386 #define FTM_POL_POL0_SHIFT 0u
4387 #define FTM_POL_POL0_WIDTH 1u
4388 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
4389 #define FTM_POL_POL1_MASK 0x2u
4390 #define FTM_POL_POL1_SHIFT 1u
4391 #define FTM_POL_POL1_WIDTH 1u
4392 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
4393 #define FTM_POL_POL2_MASK 0x4u
4394 #define FTM_POL_POL2_SHIFT 2u
4395 #define FTM_POL_POL2_WIDTH 1u
4396 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
4397 #define FTM_POL_POL3_MASK 0x8u
4398 #define FTM_POL_POL3_SHIFT 3u
4399 #define FTM_POL_POL3_WIDTH 1u
4400 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
4401 #define FTM_POL_POL4_MASK 0x10u
4402 #define FTM_POL_POL4_SHIFT 4u
4403 #define FTM_POL_POL4_WIDTH 1u
4404 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
4405 #define FTM_POL_POL5_MASK 0x20u
4406 #define FTM_POL_POL5_SHIFT 5u
4407 #define FTM_POL_POL5_WIDTH 1u
4408 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
4409 #define FTM_POL_POL6_MASK 0x40u
4410 #define FTM_POL_POL6_SHIFT 6u
4411 #define FTM_POL_POL6_WIDTH 1u
4412 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
4413 #define FTM_POL_POL7_MASK 0x80u
4414 #define FTM_POL_POL7_SHIFT 7u
4415 #define FTM_POL_POL7_WIDTH 1u
4416 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
4417 /* FMS Bit Fields */
4418 #define FTM_FMS_FAULTF0_MASK 0x1u
4419 #define FTM_FMS_FAULTF0_SHIFT 0u
4420 #define FTM_FMS_FAULTF0_WIDTH 1u
4421 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
4422 #define FTM_FMS_FAULTF1_MASK 0x2u
4423 #define FTM_FMS_FAULTF1_SHIFT 1u
4424 #define FTM_FMS_FAULTF1_WIDTH 1u
4425 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
4426 #define FTM_FMS_FAULTF2_MASK 0x4u
4427 #define FTM_FMS_FAULTF2_SHIFT 2u
4428 #define FTM_FMS_FAULTF2_WIDTH 1u
4429 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
4430 #define FTM_FMS_FAULTF3_MASK 0x8u
4431 #define FTM_FMS_FAULTF3_SHIFT 3u
4432 #define FTM_FMS_FAULTF3_WIDTH 1u
4433 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
4434 #define FTM_FMS_FAULTIN_MASK 0x20u
4435 #define FTM_FMS_FAULTIN_SHIFT 5u
4436 #define FTM_FMS_FAULTIN_WIDTH 1u
4437 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
4438 #define FTM_FMS_WPEN_MASK 0x40u
4439 #define FTM_FMS_WPEN_SHIFT 6u
4440 #define FTM_FMS_WPEN_WIDTH 1u
4441 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
4442 #define FTM_FMS_FAULTF_MASK 0x80u
4443 #define FTM_FMS_FAULTF_SHIFT 7u
4444 #define FTM_FMS_FAULTF_WIDTH 1u
4445 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
4446 /* FILTER Bit Fields */
4447 #define FTM_FILTER_CH0FVAL_MASK 0xFu
4448 #define FTM_FILTER_CH0FVAL_SHIFT 0u
4449 #define FTM_FILTER_CH0FVAL_WIDTH 4u
4450 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
4451 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
4452 #define FTM_FILTER_CH1FVAL_SHIFT 4u
4453 #define FTM_FILTER_CH1FVAL_WIDTH 4u
4454 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
4455 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
4456 #define FTM_FILTER_CH2FVAL_SHIFT 8u
4457 #define FTM_FILTER_CH2FVAL_WIDTH 4u
4458 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
4459 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
4460 #define FTM_FILTER_CH3FVAL_SHIFT 12u
4461 #define FTM_FILTER_CH3FVAL_WIDTH 4u
4462 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
4463 /* FLTCTRL Bit Fields */
4464 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
4465 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0u
4466 #define FTM_FLTCTRL_FAULT0EN_WIDTH 1u
4467 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
4468 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
4469 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1u
4470 #define FTM_FLTCTRL_FAULT1EN_WIDTH 1u
4471 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
4472 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
4473 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2u
4474 #define FTM_FLTCTRL_FAULT2EN_WIDTH 1u
4475 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
4476 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
4477 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3u
4478 #define FTM_FLTCTRL_FAULT3EN_WIDTH 1u
4479 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
4480 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
4481 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4u
4482 #define FTM_FLTCTRL_FFLTR0EN_WIDTH 1u
4483 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
4484 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
4485 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5u
4486 #define FTM_FLTCTRL_FFLTR1EN_WIDTH 1u
4487 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
4488 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
4489 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6u
4490 #define FTM_FLTCTRL_FFLTR2EN_WIDTH 1u
4491 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
4492 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
4493 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7u
4494 #define FTM_FLTCTRL_FFLTR3EN_WIDTH 1u
4495 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
4496 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
4497 #define FTM_FLTCTRL_FFVAL_SHIFT 8u
4498 #define FTM_FLTCTRL_FFVAL_WIDTH 4u
4499 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
4500 #define FTM_FLTCTRL_FSTATE_MASK 0x8000u
4501 #define FTM_FLTCTRL_FSTATE_SHIFT 15u
4502 #define FTM_FLTCTRL_FSTATE_WIDTH 1u
4503 #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FSTATE_SHIFT))&FTM_FLTCTRL_FSTATE_MASK)
4504 /* QDCTRL Bit Fields */
4505 #define FTM_QDCTRL_QUADEN_MASK 0x1u
4506 #define FTM_QDCTRL_QUADEN_SHIFT 0u
4507 #define FTM_QDCTRL_QUADEN_WIDTH 1u
4508 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
4509 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
4510 #define FTM_QDCTRL_TOFDIR_SHIFT 1u
4511 #define FTM_QDCTRL_TOFDIR_WIDTH 1u
4512 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
4513 #define FTM_QDCTRL_QUADIR_MASK 0x4u
4514 #define FTM_QDCTRL_QUADIR_SHIFT 2u
4515 #define FTM_QDCTRL_QUADIR_WIDTH 1u
4516 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
4517 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
4518 #define FTM_QDCTRL_QUADMODE_SHIFT 3u
4519 #define FTM_QDCTRL_QUADMODE_WIDTH 1u
4520 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
4521 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
4522 #define FTM_QDCTRL_PHBPOL_SHIFT 4u
4523 #define FTM_QDCTRL_PHBPOL_WIDTH 1u
4524 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
4525 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
4526 #define FTM_QDCTRL_PHAPOL_SHIFT 5u
4527 #define FTM_QDCTRL_PHAPOL_WIDTH 1u
4528 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
4529 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
4530 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6u
4531 #define FTM_QDCTRL_PHBFLTREN_WIDTH 1u
4532 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
4533 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
4534 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7u
4535 #define FTM_QDCTRL_PHAFLTREN_WIDTH 1u
4536 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
4537 /* CONF Bit Fields */
4538 #define FTM_CONF_LDFQ_MASK 0x1Fu
4539 #define FTM_CONF_LDFQ_SHIFT 0u
4540 #define FTM_CONF_LDFQ_WIDTH 5u
4541 #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_LDFQ_SHIFT))&FTM_CONF_LDFQ_MASK)
4542 #define FTM_CONF_BDMMODE_MASK 0xC0u
4543 #define FTM_CONF_BDMMODE_SHIFT 6u
4544 #define FTM_CONF_BDMMODE_WIDTH 2u
4545 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
4546 #define FTM_CONF_GTBEEN_MASK 0x200u
4547 #define FTM_CONF_GTBEEN_SHIFT 9u
4548 #define FTM_CONF_GTBEEN_WIDTH 1u
4549 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
4550 #define FTM_CONF_GTBEOUT_MASK 0x400u
4551 #define FTM_CONF_GTBEOUT_SHIFT 10u
4552 #define FTM_CONF_GTBEOUT_WIDTH 1u
4553 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
4554 #define FTM_CONF_ITRIGR_MASK 0x800u
4555 #define FTM_CONF_ITRIGR_SHIFT 11u
4556 #define FTM_CONF_ITRIGR_WIDTH 1u
4557 #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_ITRIGR_SHIFT))&FTM_CONF_ITRIGR_MASK)
4558 /* FLTPOL Bit Fields */
4559 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
4560 #define FTM_FLTPOL_FLT0POL_SHIFT 0u
4561 #define FTM_FLTPOL_FLT0POL_WIDTH 1u
4562 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
4563 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
4564 #define FTM_FLTPOL_FLT1POL_SHIFT 1u
4565 #define FTM_FLTPOL_FLT1POL_WIDTH 1u
4566 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
4567 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
4568 #define FTM_FLTPOL_FLT2POL_SHIFT 2u
4569 #define FTM_FLTPOL_FLT2POL_WIDTH 1u
4570 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
4571 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
4572 #define FTM_FLTPOL_FLT3POL_SHIFT 3u
4573 #define FTM_FLTPOL_FLT3POL_WIDTH 1u
4574 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
4575 /* SYNCONF Bit Fields */
4576 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
4577 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0u
4578 #define FTM_SYNCONF_HWTRIGMODE_WIDTH 1u
4579 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
4580 #define FTM_SYNCONF_CNTINC_MASK 0x4u
4581 #define FTM_SYNCONF_CNTINC_SHIFT 2u
4582 #define FTM_SYNCONF_CNTINC_WIDTH 1u
4583 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
4584 #define FTM_SYNCONF_INVC_MASK 0x10u
4585 #define FTM_SYNCONF_INVC_SHIFT 4u
4586 #define FTM_SYNCONF_INVC_WIDTH 1u
4587 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
4588 #define FTM_SYNCONF_SWOC_MASK 0x20u
4589 #define FTM_SYNCONF_SWOC_SHIFT 5u
4590 #define FTM_SYNCONF_SWOC_WIDTH 1u
4591 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
4592 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
4593 #define FTM_SYNCONF_SYNCMODE_SHIFT 7u
4594 #define FTM_SYNCONF_SYNCMODE_WIDTH 1u
4595 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
4596 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
4597 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8u
4598 #define FTM_SYNCONF_SWRSTCNT_WIDTH 1u
4599 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
4600 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
4601 #define FTM_SYNCONF_SWWRBUF_SHIFT 9u
4602 #define FTM_SYNCONF_SWWRBUF_WIDTH 1u
4603 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
4604 #define FTM_SYNCONF_SWOM_MASK 0x400u
4605 #define FTM_SYNCONF_SWOM_SHIFT 10u
4606 #define FTM_SYNCONF_SWOM_WIDTH 1u
4607 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
4608 #define FTM_SYNCONF_SWINVC_MASK 0x800u
4609 #define FTM_SYNCONF_SWINVC_SHIFT 11u
4610 #define FTM_SYNCONF_SWINVC_WIDTH 1u
4611 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
4612 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
4613 #define FTM_SYNCONF_SWSOC_SHIFT 12u
4614 #define FTM_SYNCONF_SWSOC_WIDTH 1u
4615 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
4616 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
4617 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16u
4618 #define FTM_SYNCONF_HWRSTCNT_WIDTH 1u
4619 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
4620 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
4621 #define FTM_SYNCONF_HWWRBUF_SHIFT 17u
4622 #define FTM_SYNCONF_HWWRBUF_WIDTH 1u
4623 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
4624 #define FTM_SYNCONF_HWOM_MASK 0x40000u
4625 #define FTM_SYNCONF_HWOM_SHIFT 18u
4626 #define FTM_SYNCONF_HWOM_WIDTH 1u
4627 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
4628 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
4629 #define FTM_SYNCONF_HWINVC_SHIFT 19u
4630 #define FTM_SYNCONF_HWINVC_WIDTH 1u
4631 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
4632 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
4633 #define FTM_SYNCONF_HWSOC_SHIFT 20u
4634 #define FTM_SYNCONF_HWSOC_WIDTH 1u
4635 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
4636 /* INVCTRL Bit Fields */
4637 #define FTM_INVCTRL_INV0EN_MASK 0x1u
4638 #define FTM_INVCTRL_INV0EN_SHIFT 0u
4639 #define FTM_INVCTRL_INV0EN_WIDTH 1u
4640 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
4641 #define FTM_INVCTRL_INV1EN_MASK 0x2u
4642 #define FTM_INVCTRL_INV1EN_SHIFT 1u
4643 #define FTM_INVCTRL_INV1EN_WIDTH 1u
4644 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
4645 #define FTM_INVCTRL_INV2EN_MASK 0x4u
4646 #define FTM_INVCTRL_INV2EN_SHIFT 2u
4647 #define FTM_INVCTRL_INV2EN_WIDTH 1u
4648 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
4649 #define FTM_INVCTRL_INV3EN_MASK 0x8u
4650 #define FTM_INVCTRL_INV3EN_SHIFT 3u
4651 #define FTM_INVCTRL_INV3EN_WIDTH 1u
4652 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
4653 /* SWOCTRL Bit Fields */
4654 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
4655 #define FTM_SWOCTRL_CH0OC_SHIFT 0u
4656 #define FTM_SWOCTRL_CH0OC_WIDTH 1u
4657 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
4658 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
4659 #define FTM_SWOCTRL_CH1OC_SHIFT 1u
4660 #define FTM_SWOCTRL_CH1OC_WIDTH 1u
4661 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
4662 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
4663 #define FTM_SWOCTRL_CH2OC_SHIFT 2u
4664 #define FTM_SWOCTRL_CH2OC_WIDTH 1u
4665 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
4666 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
4667 #define FTM_SWOCTRL_CH3OC_SHIFT 3u
4668 #define FTM_SWOCTRL_CH3OC_WIDTH 1u
4669 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
4670 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
4671 #define FTM_SWOCTRL_CH4OC_SHIFT 4u
4672 #define FTM_SWOCTRL_CH4OC_WIDTH 1u
4673 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
4674 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
4675 #define FTM_SWOCTRL_CH5OC_SHIFT 5u
4676 #define FTM_SWOCTRL_CH5OC_WIDTH 1u
4677 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
4678 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
4679 #define FTM_SWOCTRL_CH6OC_SHIFT 6u
4680 #define FTM_SWOCTRL_CH6OC_WIDTH 1u
4681 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
4682 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
4683 #define FTM_SWOCTRL_CH7OC_SHIFT 7u
4684 #define FTM_SWOCTRL_CH7OC_WIDTH 1u
4685 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
4686 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
4687 #define FTM_SWOCTRL_CH0OCV_SHIFT 8u
4688 #define FTM_SWOCTRL_CH0OCV_WIDTH 1u
4689 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
4690 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
4691 #define FTM_SWOCTRL_CH1OCV_SHIFT 9u
4692 #define FTM_SWOCTRL_CH1OCV_WIDTH 1u
4693 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
4694 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
4695 #define FTM_SWOCTRL_CH2OCV_SHIFT 10u
4696 #define FTM_SWOCTRL_CH2OCV_WIDTH 1u
4697 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
4698 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
4699 #define FTM_SWOCTRL_CH3OCV_SHIFT 11u
4700 #define FTM_SWOCTRL_CH3OCV_WIDTH 1u
4701 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
4702 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
4703 #define FTM_SWOCTRL_CH4OCV_SHIFT 12u
4704 #define FTM_SWOCTRL_CH4OCV_WIDTH 1u
4705 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
4706 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
4707 #define FTM_SWOCTRL_CH5OCV_SHIFT 13u
4708 #define FTM_SWOCTRL_CH5OCV_WIDTH 1u
4709 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
4710 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
4711 #define FTM_SWOCTRL_CH6OCV_SHIFT 14u
4712 #define FTM_SWOCTRL_CH6OCV_WIDTH 1u
4713 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
4714 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
4715 #define FTM_SWOCTRL_CH7OCV_SHIFT 15u
4716 #define FTM_SWOCTRL_CH7OCV_WIDTH 1u
4717 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
4718 /* PWMLOAD Bit Fields */
4719 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
4720 #define FTM_PWMLOAD_CH0SEL_SHIFT 0u
4721 #define FTM_PWMLOAD_CH0SEL_WIDTH 1u
4722 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
4723 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
4724 #define FTM_PWMLOAD_CH1SEL_SHIFT 1u
4725 #define FTM_PWMLOAD_CH1SEL_WIDTH 1u
4726 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
4727 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
4728 #define FTM_PWMLOAD_CH2SEL_SHIFT 2u
4729 #define FTM_PWMLOAD_CH2SEL_WIDTH 1u
4730 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
4731 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
4732 #define FTM_PWMLOAD_CH3SEL_SHIFT 3u
4733 #define FTM_PWMLOAD_CH3SEL_WIDTH 1u
4734 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
4735 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
4736 #define FTM_PWMLOAD_CH4SEL_SHIFT 4u
4737 #define FTM_PWMLOAD_CH4SEL_WIDTH 1u
4738 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
4739 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
4740 #define FTM_PWMLOAD_CH5SEL_SHIFT 5u
4741 #define FTM_PWMLOAD_CH5SEL_WIDTH 1u
4742 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
4743 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
4744 #define FTM_PWMLOAD_CH6SEL_SHIFT 6u
4745 #define FTM_PWMLOAD_CH6SEL_WIDTH 1u
4746 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
4747 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
4748 #define FTM_PWMLOAD_CH7SEL_SHIFT 7u
4749 #define FTM_PWMLOAD_CH7SEL_WIDTH 1u
4750 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
4751 #define FTM_PWMLOAD_HCSEL_MASK 0x100u
4752 #define FTM_PWMLOAD_HCSEL_SHIFT 8u
4753 #define FTM_PWMLOAD_HCSEL_WIDTH 1u
4754 #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_HCSEL_SHIFT))&FTM_PWMLOAD_HCSEL_MASK)
4755 #define FTM_PWMLOAD_LDOK_MASK 0x200u
4756 #define FTM_PWMLOAD_LDOK_SHIFT 9u
4757 #define FTM_PWMLOAD_LDOK_WIDTH 1u
4758 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
4759 #define FTM_PWMLOAD_GLEN_MASK 0x400u
4760 #define FTM_PWMLOAD_GLEN_SHIFT 10u
4761 #define FTM_PWMLOAD_GLEN_WIDTH 1u
4762 #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLEN_SHIFT))&FTM_PWMLOAD_GLEN_MASK)
4763 #define FTM_PWMLOAD_GLDOK_MASK 0x800u
4764 #define FTM_PWMLOAD_GLDOK_SHIFT 11u
4765 #define FTM_PWMLOAD_GLDOK_WIDTH 1u
4766 #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLDOK_SHIFT))&FTM_PWMLOAD_GLDOK_MASK)
4767 /* HCR Bit Fields */
4768 #define FTM_HCR_HCVAL_MASK 0xFFFFu
4769 #define FTM_HCR_HCVAL_SHIFT 0u
4770 #define FTM_HCR_HCVAL_WIDTH 16u
4771 #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_HCR_HCVAL_SHIFT))&FTM_HCR_HCVAL_MASK)
4772 /* PAIR0DEADTIME Bit Fields */
4773 #define FTM_PAIR0DEADTIME_DTVAL_MASK 0x3Fu
4774 #define FTM_PAIR0DEADTIME_DTVAL_SHIFT 0u
4775 #define FTM_PAIR0DEADTIME_DTVAL_WIDTH 6u
4776 #define FTM_PAIR0DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVAL_SHIFT))&FTM_PAIR0DEADTIME_DTVAL_MASK)
4777 #define FTM_PAIR0DEADTIME_DTPS_MASK 0xC0u
4778 #define FTM_PAIR0DEADTIME_DTPS_SHIFT 6u
4779 #define FTM_PAIR0DEADTIME_DTPS_WIDTH 2u
4780 #define FTM_PAIR0DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTPS_SHIFT))&FTM_PAIR0DEADTIME_DTPS_MASK)
4781 #define FTM_PAIR0DEADTIME_DTVALEX_MASK 0xF0000u
4782 #define FTM_PAIR0DEADTIME_DTVALEX_SHIFT 16u
4783 #define FTM_PAIR0DEADTIME_DTVALEX_WIDTH 4u
4784 #define FTM_PAIR0DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVALEX_SHIFT))&FTM_PAIR0DEADTIME_DTVALEX_MASK)
4785 /* PAIR1DEADTIME Bit Fields */
4786 #define FTM_PAIR1DEADTIME_DTVAL_MASK 0x3Fu
4787 #define FTM_PAIR1DEADTIME_DTVAL_SHIFT 0u
4788 #define FTM_PAIR1DEADTIME_DTVAL_WIDTH 6u
4789 #define FTM_PAIR1DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVAL_SHIFT))&FTM_PAIR1DEADTIME_DTVAL_MASK)
4790 #define FTM_PAIR1DEADTIME_DTPS_MASK 0xC0u
4791 #define FTM_PAIR1DEADTIME_DTPS_SHIFT 6u
4792 #define FTM_PAIR1DEADTIME_DTPS_WIDTH 2u
4793 #define FTM_PAIR1DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTPS_SHIFT))&FTM_PAIR1DEADTIME_DTPS_MASK)
4794 #define FTM_PAIR1DEADTIME_DTVALEX_MASK 0xF0000u
4795 #define FTM_PAIR1DEADTIME_DTVALEX_SHIFT 16u
4796 #define FTM_PAIR1DEADTIME_DTVALEX_WIDTH 4u
4797 #define FTM_PAIR1DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVALEX_SHIFT))&FTM_PAIR1DEADTIME_DTVALEX_MASK)
4798 /* PAIR2DEADTIME Bit Fields */
4799 #define FTM_PAIR2DEADTIME_DTVAL_MASK 0x3Fu
4800 #define FTM_PAIR2DEADTIME_DTVAL_SHIFT 0u
4801 #define FTM_PAIR2DEADTIME_DTVAL_WIDTH 6u
4802 #define FTM_PAIR2DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVAL_SHIFT))&FTM_PAIR2DEADTIME_DTVAL_MASK)
4803 #define FTM_PAIR2DEADTIME_DTPS_MASK 0xC0u
4804 #define FTM_PAIR2DEADTIME_DTPS_SHIFT 6u
4805 #define FTM_PAIR2DEADTIME_DTPS_WIDTH 2u
4806 #define FTM_PAIR2DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTPS_SHIFT))&FTM_PAIR2DEADTIME_DTPS_MASK)
4807 #define FTM_PAIR2DEADTIME_DTVALEX_MASK 0xF0000u
4808 #define FTM_PAIR2DEADTIME_DTVALEX_SHIFT 16u
4809 #define FTM_PAIR2DEADTIME_DTVALEX_WIDTH 4u
4810 #define FTM_PAIR2DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVALEX_SHIFT))&FTM_PAIR2DEADTIME_DTVALEX_MASK)
4811 /* PAIR3DEADTIME Bit Fields */
4812 #define FTM_PAIR3DEADTIME_DTVAL_MASK 0x3Fu
4813 #define FTM_PAIR3DEADTIME_DTVAL_SHIFT 0u
4814 #define FTM_PAIR3DEADTIME_DTVAL_WIDTH 6u
4815 #define FTM_PAIR3DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVAL_SHIFT))&FTM_PAIR3DEADTIME_DTVAL_MASK)
4816 #define FTM_PAIR3DEADTIME_DTPS_MASK 0xC0u
4817 #define FTM_PAIR3DEADTIME_DTPS_SHIFT 6u
4818 #define FTM_PAIR3DEADTIME_DTPS_WIDTH 2u
4819 #define FTM_PAIR3DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTPS_SHIFT))&FTM_PAIR3DEADTIME_DTPS_MASK)
4820 #define FTM_PAIR3DEADTIME_DTVALEX_MASK 0xF0000u
4821 #define FTM_PAIR3DEADTIME_DTVALEX_SHIFT 16u
4822 #define FTM_PAIR3DEADTIME_DTVALEX_WIDTH 4u
4823 #define FTM_PAIR3DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVALEX_SHIFT))&FTM_PAIR3DEADTIME_DTVALEX_MASK)
4824 /* MOD_MIRROR Bit Fields */
4825 #define FTM_MOD_MIRROR_FRACMOD_MASK 0xF800u
4826 #define FTM_MOD_MIRROR_FRACMOD_SHIFT 11u
4827 #define FTM_MOD_MIRROR_FRACMOD_WIDTH 5u
4828 #define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MIRROR_FRACMOD_SHIFT))&FTM_MOD_MIRROR_FRACMOD_MASK)
4829 #define FTM_MOD_MIRROR_MOD_MASK 0xFFFF0000u
4830 #define FTM_MOD_MIRROR_MOD_SHIFT 16u
4831 #define FTM_MOD_MIRROR_MOD_WIDTH 16u
4832 #define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MIRROR_MOD_SHIFT))&FTM_MOD_MIRROR_MOD_MASK)
4833 /* CV_MIRROR Bit Fields */
4834 #define FTM_CV_MIRROR_FRACVAL_MASK 0xF800u
4835 #define FTM_CV_MIRROR_FRACVAL_SHIFT 11u
4836 #define FTM_CV_MIRROR_FRACVAL_WIDTH 5u
4837 #define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_MIRROR_FRACVAL_SHIFT))&FTM_CV_MIRROR_FRACVAL_MASK)
4838 #define FTM_CV_MIRROR_VAL_MASK 0xFFFF0000u
4839 #define FTM_CV_MIRROR_VAL_SHIFT 16u
4840 #define FTM_CV_MIRROR_VAL_WIDTH 16u
4841 #define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_MIRROR_VAL_SHIFT))&FTM_CV_MIRROR_VAL_MASK)
4842  /* end of group FTM_Register_Masks */
4846 
4847  /* end of group FTM_Peripheral_Access_Layer */
4851 
4852 
4853 /* ----------------------------------------------------------------------------
4854  -- GPIO Peripheral Access Layer
4855  ---------------------------------------------------------------------------- */
4856 
4866 typedef struct {
4867  __IO uint32_t PDOR;
4868  __O uint32_t PSOR;
4869  __O uint32_t PCOR;
4870  __O uint32_t PTOR;
4871  __I uint32_t PDIR;
4872  __IO uint32_t PDDR;
4873  __IO uint32_t PIDR;
4875 
4877 #define GPIO_INSTANCE_COUNT (5u)
4878 
4879 
4880 /* GPIO - Peripheral instance base addresses */
4882 #define PTA_BASE (0x400FF000u)
4883 
4884 #define PTA ((GPIO_Type *)PTA_BASE)
4885 
4886 #define PTB_BASE (0x400FF040u)
4887 
4888 #define PTB ((GPIO_Type *)PTB_BASE)
4889 
4890 #define PTC_BASE (0x400FF080u)
4891 
4892 #define PTC ((GPIO_Type *)PTC_BASE)
4893 
4894 #define PTD_BASE (0x400FF0C0u)
4895 
4896 #define PTD ((GPIO_Type *)PTD_BASE)
4897 
4898 #define PTE_BASE (0x400FF100u)
4899 
4900 #define PTE ((GPIO_Type *)PTE_BASE)
4901 
4902 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
4903 
4904 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
4905 
4906 /* ----------------------------------------------------------------------------
4907  -- GPIO Register Masks
4908  ---------------------------------------------------------------------------- */
4909 
4915 /* PDOR Bit Fields */
4916 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
4917 #define GPIO_PDOR_PDO_SHIFT 0u
4918 #define GPIO_PDOR_PDO_WIDTH 32u
4919 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
4920 /* PSOR Bit Fields */
4921 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
4922 #define GPIO_PSOR_PTSO_SHIFT 0u
4923 #define GPIO_PSOR_PTSO_WIDTH 32u
4924 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
4925 /* PCOR Bit Fields */
4926 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
4927 #define GPIO_PCOR_PTCO_SHIFT 0u
4928 #define GPIO_PCOR_PTCO_WIDTH 32u
4929 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
4930 /* PTOR Bit Fields */
4931 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
4932 #define GPIO_PTOR_PTTO_SHIFT 0u
4933 #define GPIO_PTOR_PTTO_WIDTH 32u
4934 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
4935 /* PDIR Bit Fields */
4936 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
4937 #define GPIO_PDIR_PDI_SHIFT 0u
4938 #define GPIO_PDIR_PDI_WIDTH 32u
4939 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
4940 /* PDDR Bit Fields */
4941 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
4942 #define GPIO_PDDR_PDD_SHIFT 0u
4943 #define GPIO_PDDR_PDD_WIDTH 32u
4944 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
4945 /* PIDR Bit Fields */
4946 #define GPIO_PIDR_PID_MASK 0xFFFFFFFFu
4947 #define GPIO_PIDR_PID_SHIFT 0u
4948 #define GPIO_PIDR_PID_WIDTH 32u
4949 #define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
4950  /* end of group GPIO_Register_Masks */
4954 
4955  /* end of group GPIO_Peripheral_Access_Layer */
4959 
4960 
4961 /* ----------------------------------------------------------------------------
4962  -- LMEM Peripheral Access Layer
4963  ---------------------------------------------------------------------------- */
4964 
4974 typedef struct {
4975  __IO uint32_t PCCCR;
4976  __IO uint32_t PCCLCR;
4977  __IO uint32_t PCCSAR;
4978  __IO uint32_t PCCCVR;
4979  uint8_t RESERVED_0[16];
4980  __IO uint32_t PCCRMR;
4982 
4984 #define LMEM_INSTANCE_COUNT (1u)
4985 
4986 
4987 /* LMEM - Peripheral instance base addresses */
4989 #define LMEM_BASE (0xE0082000u)
4990 
4991 #define LMEM ((LMEM_Type *)LMEM_BASE)
4992 
4993 #define LMEM_BASE_ADDRS { LMEM_BASE }
4994 
4995 #define LMEM_BASE_PTRS { LMEM }
4996 
4997 /* ----------------------------------------------------------------------------
4998  -- LMEM Register Masks
4999  ---------------------------------------------------------------------------- */
5000 
5006 /* PCCCR Bit Fields */
5007 #define LMEM_PCCCR_ENCACHE_MASK 0x1u
5008 #define LMEM_PCCCR_ENCACHE_SHIFT 0u
5009 #define LMEM_PCCCR_ENCACHE_WIDTH 1u
5010 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_ENCACHE_SHIFT))&LMEM_PCCCR_ENCACHE_MASK)
5011 #define LMEM_PCCCR_PCCR2_MASK 0x4u
5012 #define LMEM_PCCCR_PCCR2_SHIFT 2u
5013 #define LMEM_PCCCR_PCCR2_WIDTH 1u
5014 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR2_SHIFT))&LMEM_PCCCR_PCCR2_MASK)
5015 #define LMEM_PCCCR_PCCR3_MASK 0x8u
5016 #define LMEM_PCCCR_PCCR3_SHIFT 3u
5017 #define LMEM_PCCCR_PCCR3_WIDTH 1u
5018 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR3_SHIFT))&LMEM_PCCCR_PCCR3_MASK)
5019 #define LMEM_PCCCR_INVW0_MASK 0x1000000u
5020 #define LMEM_PCCCR_INVW0_SHIFT 24u
5021 #define LMEM_PCCCR_INVW0_WIDTH 1u
5022 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW0_SHIFT))&LMEM_PCCCR_INVW0_MASK)
5023 #define LMEM_PCCCR_PUSHW0_MASK 0x2000000u
5024 #define LMEM_PCCCR_PUSHW0_SHIFT 25u
5025 #define LMEM_PCCCR_PUSHW0_WIDTH 1u
5026 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW0_SHIFT))&LMEM_PCCCR_PUSHW0_MASK)
5027 #define LMEM_PCCCR_INVW1_MASK 0x4000000u
5028 #define LMEM_PCCCR_INVW1_SHIFT 26u
5029 #define LMEM_PCCCR_INVW1_WIDTH 1u
5030 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW1_SHIFT))&LMEM_PCCCR_INVW1_MASK)
5031 #define LMEM_PCCCR_PUSHW1_MASK 0x8000000u
5032 #define LMEM_PCCCR_PUSHW1_SHIFT 27u
5033 #define LMEM_PCCCR_PUSHW1_WIDTH 1u
5034 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW1_SHIFT))&LMEM_PCCCR_PUSHW1_MASK)
5035 #define LMEM_PCCCR_GO_MASK 0x80000000u
5036 #define LMEM_PCCCR_GO_SHIFT 31u
5037 #define LMEM_PCCCR_GO_WIDTH 1u
5038 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_GO_SHIFT))&LMEM_PCCCR_GO_MASK)
5039 /* PCCLCR Bit Fields */
5040 #define LMEM_PCCLCR_LGO_MASK 0x1u
5041 #define LMEM_PCCLCR_LGO_SHIFT 0u
5042 #define LMEM_PCCLCR_LGO_WIDTH 1u
5043 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LGO_SHIFT))&LMEM_PCCLCR_LGO_MASK)
5044 #define LMEM_PCCLCR_CACHEADDR_MASK 0x3FFCu
5045 #define LMEM_PCCLCR_CACHEADDR_SHIFT 2u
5046 #define LMEM_PCCLCR_CACHEADDR_WIDTH 12u
5047 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)
5048 #define LMEM_PCCLCR_WSEL_MASK 0x4000u
5049 #define LMEM_PCCLCR_WSEL_SHIFT 14u
5050 #define LMEM_PCCLCR_WSEL_WIDTH 1u
5051 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_WSEL_SHIFT))&LMEM_PCCLCR_WSEL_MASK)
5052 #define LMEM_PCCLCR_TDSEL_MASK 0x10000u
5053 #define LMEM_PCCLCR_TDSEL_SHIFT 16u
5054 #define LMEM_PCCLCR_TDSEL_WIDTH 1u
5055 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_TDSEL_SHIFT))&LMEM_PCCLCR_TDSEL_MASK)
5056 #define LMEM_PCCLCR_LCIVB_MASK 0x100000u
5057 #define LMEM_PCCLCR_LCIVB_SHIFT 20u
5058 #define LMEM_PCCLCR_LCIVB_WIDTH 1u
5059 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIVB_SHIFT))&LMEM_PCCLCR_LCIVB_MASK)
5060 #define LMEM_PCCLCR_LCIMB_MASK 0x200000u
5061 #define LMEM_PCCLCR_LCIMB_SHIFT 21u
5062 #define LMEM_PCCLCR_LCIMB_WIDTH 1u
5063 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIMB_SHIFT))&LMEM_PCCLCR_LCIMB_MASK)
5064 #define LMEM_PCCLCR_LCWAY_MASK 0x400000u
5065 #define LMEM_PCCLCR_LCWAY_SHIFT 22u
5066 #define LMEM_PCCLCR_LCWAY_WIDTH 1u
5067 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCWAY_SHIFT))&LMEM_PCCLCR_LCWAY_MASK)
5068 #define LMEM_PCCLCR_LCMD_MASK 0x3000000u
5069 #define LMEM_PCCLCR_LCMD_SHIFT 24u
5070 #define LMEM_PCCLCR_LCMD_WIDTH 2u
5071 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)
5072 #define LMEM_PCCLCR_LADSEL_MASK 0x4000000u
5073 #define LMEM_PCCLCR_LADSEL_SHIFT 26u
5074 #define LMEM_PCCLCR_LADSEL_WIDTH 1u
5075 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LADSEL_SHIFT))&LMEM_PCCLCR_LADSEL_MASK)
5076 #define LMEM_PCCLCR_LACC_MASK 0x8000000u
5077 #define LMEM_PCCLCR_LACC_SHIFT 27u
5078 #define LMEM_PCCLCR_LACC_WIDTH 1u
5079 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LACC_SHIFT))&LMEM_PCCLCR_LACC_MASK)
5080 /* PCCSAR Bit Fields */
5081 #define LMEM_PCCSAR_LGO_MASK 0x1u
5082 #define LMEM_PCCSAR_LGO_SHIFT 0u
5083 #define LMEM_PCCSAR_LGO_WIDTH 1u
5084 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_LGO_SHIFT))&LMEM_PCCSAR_LGO_MASK)
5085 #define LMEM_PCCSAR_PHYADDR_MASK 0xFFFFFFFCu
5086 #define LMEM_PCCSAR_PHYADDR_SHIFT 2u
5087 #define LMEM_PCCSAR_PHYADDR_WIDTH 30u
5088 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)
5089 /* PCCCVR Bit Fields */
5090 #define LMEM_PCCCVR_DATA_MASK 0xFFFFFFFFu
5091 #define LMEM_PCCCVR_DATA_SHIFT 0u
5092 #define LMEM_PCCCVR_DATA_WIDTH 32u
5093 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)
5094 /* PCCRMR Bit Fields */
5095 #define LMEM_PCCRMR_R15_MASK 0x3u
5096 #define LMEM_PCCRMR_R15_SHIFT 0u
5097 #define LMEM_PCCRMR_R15_WIDTH 2u
5098 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R15_SHIFT))&LMEM_PCCRMR_R15_MASK)
5099 #define LMEM_PCCRMR_R14_MASK 0xCu
5100 #define LMEM_PCCRMR_R14_SHIFT 2u
5101 #define LMEM_PCCRMR_R14_WIDTH 2u
5102 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R14_SHIFT))&LMEM_PCCRMR_R14_MASK)
5103 #define LMEM_PCCRMR_R13_MASK 0x30u
5104 #define LMEM_PCCRMR_R13_SHIFT 4u
5105 #define LMEM_PCCRMR_R13_WIDTH 2u
5106 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R13_SHIFT))&LMEM_PCCRMR_R13_MASK)
5107 #define LMEM_PCCRMR_R12_MASK 0xC0u
5108 #define LMEM_PCCRMR_R12_SHIFT 6u
5109 #define LMEM_PCCRMR_R12_WIDTH 2u
5110 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R12_SHIFT))&LMEM_PCCRMR_R12_MASK)
5111 #define LMEM_PCCRMR_R11_MASK 0x300u
5112 #define LMEM_PCCRMR_R11_SHIFT 8u
5113 #define LMEM_PCCRMR_R11_WIDTH 2u
5114 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R11_SHIFT))&LMEM_PCCRMR_R11_MASK)
5115 #define LMEM_PCCRMR_R10_MASK 0xC00u
5116 #define LMEM_PCCRMR_R10_SHIFT 10u
5117 #define LMEM_PCCRMR_R10_WIDTH 2u
5118 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R10_SHIFT))&LMEM_PCCRMR_R10_MASK)
5119 #define LMEM_PCCRMR_R9_MASK 0x3000u
5120 #define LMEM_PCCRMR_R9_SHIFT 12u
5121 #define LMEM_PCCRMR_R9_WIDTH 2u
5122 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R9_SHIFT))&LMEM_PCCRMR_R9_MASK)
5123 #define LMEM_PCCRMR_R8_MASK 0xC000u
5124 #define LMEM_PCCRMR_R8_SHIFT 14u
5125 #define LMEM_PCCRMR_R8_WIDTH 2u
5126 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R8_SHIFT))&LMEM_PCCRMR_R8_MASK)
5127 #define LMEM_PCCRMR_R7_MASK 0x30000u
5128 #define LMEM_PCCRMR_R7_SHIFT 16u
5129 #define LMEM_PCCRMR_R7_WIDTH 2u
5130 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R7_SHIFT))&LMEM_PCCRMR_R7_MASK)
5131 #define LMEM_PCCRMR_R6_MASK 0xC0000u
5132 #define LMEM_PCCRMR_R6_SHIFT 18u
5133 #define LMEM_PCCRMR_R6_WIDTH 2u
5134 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R6_SHIFT))&LMEM_PCCRMR_R6_MASK)
5135 #define LMEM_PCCRMR_R5_MASK 0x300000u
5136 #define LMEM_PCCRMR_R5_SHIFT 20u
5137 #define LMEM_PCCRMR_R5_WIDTH 2u
5138 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R5_SHIFT))&LMEM_PCCRMR_R5_MASK)
5139 #define LMEM_PCCRMR_R4_MASK 0xC00000u
5140 #define LMEM_PCCRMR_R4_SHIFT 22u
5141 #define LMEM_PCCRMR_R4_WIDTH 2u
5142 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R4_SHIFT))&LMEM_PCCRMR_R4_MASK)
5143 #define LMEM_PCCRMR_R3_MASK 0x3000000u
5144 #define LMEM_PCCRMR_R3_SHIFT 24u
5145 #define LMEM_PCCRMR_R3_WIDTH 2u
5146 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R3_SHIFT))&LMEM_PCCRMR_R3_MASK)
5147 #define LMEM_PCCRMR_R2_MASK 0xC000000u
5148 #define LMEM_PCCRMR_R2_SHIFT 26u
5149 #define LMEM_PCCRMR_R2_WIDTH 2u
5150 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R2_SHIFT))&LMEM_PCCRMR_R2_MASK)
5151 #define LMEM_PCCRMR_R1_MASK 0x30000000u
5152 #define LMEM_PCCRMR_R1_SHIFT 28u
5153 #define LMEM_PCCRMR_R1_WIDTH 2u
5154 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R1_SHIFT))&LMEM_PCCRMR_R1_MASK)
5155 #define LMEM_PCCRMR_R0_MASK 0xC0000000u
5156 #define LMEM_PCCRMR_R0_SHIFT 30u
5157 #define LMEM_PCCRMR_R0_WIDTH 2u
5158 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R0_SHIFT))&LMEM_PCCRMR_R0_MASK)
5159  /* end of group LMEM_Register_Masks */
5163 
5164  /* end of group LMEM_Peripheral_Access_Layer */
5168 
5169 
5170 /* ----------------------------------------------------------------------------
5171  -- LPI2C Peripheral Access Layer
5172  ---------------------------------------------------------------------------- */
5173 
5183 typedef struct {
5184  __I uint32_t VERID;
5185  __I uint32_t PARAM;
5186  uint8_t RESERVED_0[8];
5187  __IO uint32_t MCR;
5188  __IO uint32_t MSR;
5189  __IO uint32_t MIER;
5190  __IO uint32_t MDER;
5191  __IO uint32_t MCFGR0;
5192  __IO uint32_t MCFGR1;
5193  __IO uint32_t MCFGR2;
5194  __IO uint32_t MCFGR3;
5195  uint8_t RESERVED_1[16];
5196  __IO uint32_t MDMR;
5197  uint8_t RESERVED_2[4];
5198  __IO uint32_t MCCR0;
5199  uint8_t RESERVED_3[4];
5200  __IO uint32_t MCCR1;
5201  uint8_t RESERVED_4[4];
5202  __IO uint32_t MFCR;
5203  __I uint32_t MFSR;
5204  __IO uint32_t MTDR;
5205  uint8_t RESERVED_5[12];
5206  __I uint32_t MRDR;
5207  uint8_t RESERVED_6[156];
5208  __IO uint32_t SCR;
5209  __IO uint32_t SSR;
5210  __IO uint32_t SIER;
5211  __IO uint32_t SDER;
5212  uint8_t RESERVED_7[4];
5213  __IO uint32_t SCFGR1;
5214  __IO uint32_t SCFGR2;
5215  uint8_t RESERVED_8[20];
5216  __IO uint32_t SAMR;
5217  uint8_t RESERVED_9[12];
5218  __I uint32_t SASR;
5219  __IO uint32_t STAR;
5220  uint8_t RESERVED_10[8];
5221  __IO uint32_t STDR;
5222  uint8_t RESERVED_11[12];
5223  __I uint32_t SRDR;
5225 
5227 #define LPI2C_INSTANCE_COUNT (1u)
5228 
5229 
5230 /* LPI2C - Peripheral instance base addresses */
5232 #define LPI2C0_BASE (0x40066000u)
5233 
5234 #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
5235 
5236 #define LPI2C_BASE_ADDRS { LPI2C0_BASE }
5237 
5238 #define LPI2C_BASE_PTRS { LPI2C0 }
5239 
5240 #define LPI2C_IRQS_ARR_COUNT (2u)
5241 
5242 #define LPI2C_MASTER_IRQS_CH_COUNT (1u)
5243 
5244 #define LPI2C_SLAVE_IRQS_CH_COUNT (1u)
5245 
5246 #define LPI2C_MASTER_IRQS { LPI2C0_Master_Slave_IRQn }
5247 #define LPI2C_SLAVE_IRQS { LPI2C0_Master_Slave_IRQn }
5248 
5249 /* ----------------------------------------------------------------------------
5250  -- LPI2C Register Masks
5251  ---------------------------------------------------------------------------- */
5252 
5258 /* VERID Bit Fields */
5259 #define LPI2C_VERID_FEATURE_MASK 0xFFFFu
5260 #define LPI2C_VERID_FEATURE_SHIFT 0u
5261 #define LPI2C_VERID_FEATURE_WIDTH 16u
5262 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_FEATURE_SHIFT))&LPI2C_VERID_FEATURE_MASK)
5263 #define LPI2C_VERID_MINOR_MASK 0xFF0000u
5264 #define LPI2C_VERID_MINOR_SHIFT 16u
5265 #define LPI2C_VERID_MINOR_WIDTH 8u
5266 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MINOR_SHIFT))&LPI2C_VERID_MINOR_MASK)
5267 #define LPI2C_VERID_MAJOR_MASK 0xFF000000u
5268 #define LPI2C_VERID_MAJOR_SHIFT 24u
5269 #define LPI2C_VERID_MAJOR_WIDTH 8u
5270 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MAJOR_SHIFT))&LPI2C_VERID_MAJOR_MASK)
5271 /* PARAM Bit Fields */
5272 #define LPI2C_PARAM_MTXFIFO_MASK 0xFu
5273 #define LPI2C_PARAM_MTXFIFO_SHIFT 0u
5274 #define LPI2C_PARAM_MTXFIFO_WIDTH 4u
5275 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MTXFIFO_SHIFT))&LPI2C_PARAM_MTXFIFO_MASK)
5276 #define LPI2C_PARAM_MRXFIFO_MASK 0xF00u
5277 #define LPI2C_PARAM_MRXFIFO_SHIFT 8u
5278 #define LPI2C_PARAM_MRXFIFO_WIDTH 4u
5279 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MRXFIFO_SHIFT))&LPI2C_PARAM_MRXFIFO_MASK)
5280 /* MCR Bit Fields */
5281 #define LPI2C_MCR_MEN_MASK 0x1u
5282 #define LPI2C_MCR_MEN_SHIFT 0u
5283 #define LPI2C_MCR_MEN_WIDTH 1u
5284 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_MEN_SHIFT))&LPI2C_MCR_MEN_MASK)
5285 #define LPI2C_MCR_RST_MASK 0x2u
5286 #define LPI2C_MCR_RST_SHIFT 1u
5287 #define LPI2C_MCR_RST_WIDTH 1u
5288 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RST_SHIFT))&LPI2C_MCR_RST_MASK)
5289 #define LPI2C_MCR_DOZEN_MASK 0x4u
5290 #define LPI2C_MCR_DOZEN_SHIFT 2u
5291 #define LPI2C_MCR_DOZEN_WIDTH 1u
5292 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DOZEN_SHIFT))&LPI2C_MCR_DOZEN_MASK)
5293 #define LPI2C_MCR_DBGEN_MASK 0x8u
5294 #define LPI2C_MCR_DBGEN_SHIFT 3u
5295 #define LPI2C_MCR_DBGEN_WIDTH 1u
5296 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DBGEN_SHIFT))&LPI2C_MCR_DBGEN_MASK)
5297 #define LPI2C_MCR_RTF_MASK 0x100u
5298 #define LPI2C_MCR_RTF_SHIFT 8u
5299 #define LPI2C_MCR_RTF_WIDTH 1u
5300 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RTF_SHIFT))&LPI2C_MCR_RTF_MASK)
5301 #define LPI2C_MCR_RRF_MASK 0x200u
5302 #define LPI2C_MCR_RRF_SHIFT 9u
5303 #define LPI2C_MCR_RRF_WIDTH 1u
5304 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RRF_SHIFT))&LPI2C_MCR_RRF_MASK)
5305 /* MSR Bit Fields */
5306 #define LPI2C_MSR_TDF_MASK 0x1u
5307 #define LPI2C_MSR_TDF_SHIFT 0u
5308 #define LPI2C_MSR_TDF_WIDTH 1u
5309 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_TDF_SHIFT))&LPI2C_MSR_TDF_MASK)
5310 #define LPI2C_MSR_RDF_MASK 0x2u
5311 #define LPI2C_MSR_RDF_SHIFT 1u
5312 #define LPI2C_MSR_RDF_WIDTH 1u
5313 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_RDF_SHIFT))&LPI2C_MSR_RDF_MASK)
5314 #define LPI2C_MSR_EPF_MASK 0x100u
5315 #define LPI2C_MSR_EPF_SHIFT 8u
5316 #define LPI2C_MSR_EPF_WIDTH 1u
5317 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_EPF_SHIFT))&LPI2C_MSR_EPF_MASK)
5318 #define LPI2C_MSR_SDF_MASK 0x200u
5319 #define LPI2C_MSR_SDF_SHIFT 9u
5320 #define LPI2C_MSR_SDF_WIDTH 1u
5321 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_SDF_SHIFT))&LPI2C_MSR_SDF_MASK)
5322 #define LPI2C_MSR_NDF_MASK 0x400u
5323 #define LPI2C_MSR_NDF_SHIFT 10u
5324 #define LPI2C_MSR_NDF_WIDTH 1u
5325 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_NDF_SHIFT))&LPI2C_MSR_NDF_MASK)
5326 #define LPI2C_MSR_ALF_MASK 0x800u
5327 #define LPI2C_MSR_ALF_SHIFT 11u
5328 #define LPI2C_MSR_ALF_WIDTH 1u
5329 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_ALF_SHIFT))&LPI2C_MSR_ALF_MASK)
5330 #define LPI2C_MSR_FEF_MASK 0x1000u
5331 #define LPI2C_MSR_FEF_SHIFT 12u
5332 #define LPI2C_MSR_FEF_WIDTH 1u
5333 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_FEF_SHIFT))&LPI2C_MSR_FEF_MASK)
5334 #define LPI2C_MSR_PLTF_MASK 0x2000u
5335 #define LPI2C_MSR_PLTF_SHIFT 13u
5336 #define LPI2C_MSR_PLTF_WIDTH 1u
5337 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_PLTF_SHIFT))&LPI2C_MSR_PLTF_MASK)
5338 #define LPI2C_MSR_DMF_MASK 0x4000u
5339 #define LPI2C_MSR_DMF_SHIFT 14u
5340 #define LPI2C_MSR_DMF_WIDTH 1u
5341 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_DMF_SHIFT))&LPI2C_MSR_DMF_MASK)
5342 #define LPI2C_MSR_MBF_MASK 0x1000000u
5343 #define LPI2C_MSR_MBF_SHIFT 24u
5344 #define LPI2C_MSR_MBF_WIDTH 1u
5345 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_MBF_SHIFT))&LPI2C_MSR_MBF_MASK)
5346 #define LPI2C_MSR_BBF_MASK 0x2000000u
5347 #define LPI2C_MSR_BBF_SHIFT 25u
5348 #define LPI2C_MSR_BBF_WIDTH 1u
5349 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_BBF_SHIFT))&LPI2C_MSR_BBF_MASK)
5350 /* MIER Bit Fields */
5351 #define LPI2C_MIER_TDIE_MASK 0x1u
5352 #define LPI2C_MIER_TDIE_SHIFT 0u
5353 #define LPI2C_MIER_TDIE_WIDTH 1u
5354 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_TDIE_SHIFT))&LPI2C_MIER_TDIE_MASK)
5355 #define LPI2C_MIER_RDIE_MASK 0x2u
5356 #define LPI2C_MIER_RDIE_SHIFT 1u
5357 #define LPI2C_MIER_RDIE_WIDTH 1u
5358 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_RDIE_SHIFT))&LPI2C_MIER_RDIE_MASK)
5359 #define LPI2C_MIER_EPIE_MASK 0x100u
5360 #define LPI2C_MIER_EPIE_SHIFT 8u
5361 #define LPI2C_MIER_EPIE_WIDTH 1u
5362 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_EPIE_SHIFT))&LPI2C_MIER_EPIE_MASK)
5363 #define LPI2C_MIER_SDIE_MASK 0x200u
5364 #define LPI2C_MIER_SDIE_SHIFT 9u
5365 #define LPI2C_MIER_SDIE_WIDTH 1u
5366 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_SDIE_SHIFT))&LPI2C_MIER_SDIE_MASK)
5367 #define LPI2C_MIER_NDIE_MASK 0x400u
5368 #define LPI2C_MIER_NDIE_SHIFT 10u
5369 #define LPI2C_MIER_NDIE_WIDTH 1u
5370 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_NDIE_SHIFT))&LPI2C_MIER_NDIE_MASK)
5371 #define LPI2C_MIER_ALIE_MASK 0x800u
5372 #define LPI2C_MIER_ALIE_SHIFT 11u
5373 #define LPI2C_MIER_ALIE_WIDTH 1u
5374 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_ALIE_SHIFT))&LPI2C_MIER_ALIE_MASK)
5375 #define LPI2C_MIER_FEIE_MASK 0x1000u
5376 #define LPI2C_MIER_FEIE_SHIFT 12u
5377 #define LPI2C_MIER_FEIE_WIDTH 1u
5378 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_FEIE_SHIFT))&LPI2C_MIER_FEIE_MASK)
5379 #define LPI2C_MIER_PLTIE_MASK 0x2000u
5380 #define LPI2C_MIER_PLTIE_SHIFT 13u
5381 #define LPI2C_MIER_PLTIE_WIDTH 1u
5382 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_PLTIE_SHIFT))&LPI2C_MIER_PLTIE_MASK)
5383 #define LPI2C_MIER_DMIE_MASK 0x4000u
5384 #define LPI2C_MIER_DMIE_SHIFT 14u
5385 #define LPI2C_MIER_DMIE_WIDTH 1u
5386 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_DMIE_SHIFT))&LPI2C_MIER_DMIE_MASK)
5387 /* MDER Bit Fields */
5388 #define LPI2C_MDER_TDDE_MASK 0x1u
5389 #define LPI2C_MDER_TDDE_SHIFT 0u
5390 #define LPI2C_MDER_TDDE_WIDTH 1u
5391 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_TDDE_SHIFT))&LPI2C_MDER_TDDE_MASK)
5392 #define LPI2C_MDER_RDDE_MASK 0x2u
5393 #define LPI2C_MDER_RDDE_SHIFT 1u
5394 #define LPI2C_MDER_RDDE_WIDTH 1u
5395 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_RDDE_SHIFT))&LPI2C_MDER_RDDE_MASK)
5396 /* MCFGR0 Bit Fields */
5397 #define LPI2C_MCFGR0_HREN_MASK 0x1u
5398 #define LPI2C_MCFGR0_HREN_SHIFT 0u
5399 #define LPI2C_MCFGR0_HREN_WIDTH 1u
5400 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HREN_SHIFT))&LPI2C_MCFGR0_HREN_MASK)
5401 #define LPI2C_MCFGR0_HRPOL_MASK 0x2u
5402 #define LPI2C_MCFGR0_HRPOL_SHIFT 1u
5403 #define LPI2C_MCFGR0_HRPOL_WIDTH 1u
5404 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRPOL_SHIFT))&LPI2C_MCFGR0_HRPOL_MASK)
5405 #define LPI2C_MCFGR0_HRSEL_MASK 0x4u
5406 #define LPI2C_MCFGR0_HRSEL_SHIFT 2u
5407 #define LPI2C_MCFGR0_HRSEL_WIDTH 1u
5408 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRSEL_SHIFT))&LPI2C_MCFGR0_HRSEL_MASK)
5409 #define LPI2C_MCFGR0_CIRFIFO_MASK 0x100u
5410 #define LPI2C_MCFGR0_CIRFIFO_SHIFT 8u
5411 #define LPI2C_MCFGR0_CIRFIFO_WIDTH 1u
5412 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_CIRFIFO_SHIFT))&LPI2C_MCFGR0_CIRFIFO_MASK)
5413 #define LPI2C_MCFGR0_RDMO_MASK 0x200u
5414 #define LPI2C_MCFGR0_RDMO_SHIFT 9u
5415 #define LPI2C_MCFGR0_RDMO_WIDTH 1u
5416 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_RDMO_SHIFT))&LPI2C_MCFGR0_RDMO_MASK)
5417 /* MCFGR1 Bit Fields */
5418 #define LPI2C_MCFGR1_PRESCALE_MASK 0x7u
5419 #define LPI2C_MCFGR1_PRESCALE_SHIFT 0u
5420 #define LPI2C_MCFGR1_PRESCALE_WIDTH 3u
5421 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PRESCALE_SHIFT))&LPI2C_MCFGR1_PRESCALE_MASK)
5422 #define LPI2C_MCFGR1_AUTOSTOP_MASK 0x100u
5423 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT 8u
5424 #define LPI2C_MCFGR1_AUTOSTOP_WIDTH 1u
5425 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_AUTOSTOP_SHIFT))&LPI2C_MCFGR1_AUTOSTOP_MASK)
5426 #define LPI2C_MCFGR1_IGNACK_MASK 0x200u
5427 #define LPI2C_MCFGR1_IGNACK_SHIFT 9u
5428 #define LPI2C_MCFGR1_IGNACK_WIDTH 1u
5429 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_IGNACK_SHIFT))&LPI2C_MCFGR1_IGNACK_MASK)
5430 #define LPI2C_MCFGR1_TIMECFG_MASK 0x400u
5431 #define LPI2C_MCFGR1_TIMECFG_SHIFT 10u
5432 #define LPI2C_MCFGR1_TIMECFG_WIDTH 1u
5433 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_TIMECFG_SHIFT))&LPI2C_MCFGR1_TIMECFG_MASK)
5434 #define LPI2C_MCFGR1_MATCFG_MASK 0x70000u
5435 #define LPI2C_MCFGR1_MATCFG_SHIFT 16u
5436 #define LPI2C_MCFGR1_MATCFG_WIDTH 3u
5437 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_MATCFG_SHIFT))&LPI2C_MCFGR1_MATCFG_MASK)
5438 #define LPI2C_MCFGR1_PINCFG_MASK 0x7000000u
5439 #define LPI2C_MCFGR1_PINCFG_SHIFT 24u
5440 #define LPI2C_MCFGR1_PINCFG_WIDTH 3u
5441 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PINCFG_SHIFT))&LPI2C_MCFGR1_PINCFG_MASK)
5442 /* MCFGR2 Bit Fields */
5443 #define LPI2C_MCFGR2_BUSIDLE_MASK 0xFFFu
5444 #define LPI2C_MCFGR2_BUSIDLE_SHIFT 0u
5445 #define LPI2C_MCFGR2_BUSIDLE_WIDTH 12u
5446 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_BUSIDLE_SHIFT))&LPI2C_MCFGR2_BUSIDLE_MASK)
5447 #define LPI2C_MCFGR2_FILTSCL_MASK 0xF0000u
5448 #define LPI2C_MCFGR2_FILTSCL_SHIFT 16u
5449 #define LPI2C_MCFGR2_FILTSCL_WIDTH 4u
5450 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSCL_SHIFT))&LPI2C_MCFGR2_FILTSCL_MASK)
5451 #define LPI2C_MCFGR2_FILTSDA_MASK 0xF000000u
5452 #define LPI2C_MCFGR2_FILTSDA_SHIFT 24u
5453 #define LPI2C_MCFGR2_FILTSDA_WIDTH 4u
5454 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSDA_SHIFT))&LPI2C_MCFGR2_FILTSDA_MASK)
5455 /* MCFGR3 Bit Fields */
5456 #define LPI2C_MCFGR3_PINLOW_MASK 0xFFF00u
5457 #define LPI2C_MCFGR3_PINLOW_SHIFT 8u
5458 #define LPI2C_MCFGR3_PINLOW_WIDTH 12u
5459 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR3_PINLOW_SHIFT))&LPI2C_MCFGR3_PINLOW_MASK)
5460 /* MDMR Bit Fields */
5461 #define LPI2C_MDMR_MATCH0_MASK 0xFFu
5462 #define LPI2C_MDMR_MATCH0_SHIFT 0u
5463 #define LPI2C_MDMR_MATCH0_WIDTH 8u
5464 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH0_SHIFT))&LPI2C_MDMR_MATCH0_MASK)
5465 #define LPI2C_MDMR_MATCH1_MASK 0xFF0000u
5466 #define LPI2C_MDMR_MATCH1_SHIFT 16u
5467 #define LPI2C_MDMR_MATCH1_WIDTH 8u
5468 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH1_SHIFT))&LPI2C_MDMR_MATCH1_MASK)
5469 /* MCCR0 Bit Fields */
5470 #define LPI2C_MCCR0_CLKLO_MASK 0x3Fu
5471 #define LPI2C_MCCR0_CLKLO_SHIFT 0u
5472 #define LPI2C_MCCR0_CLKLO_WIDTH 6u
5473 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKLO_SHIFT))&LPI2C_MCCR0_CLKLO_MASK)
5474 #define LPI2C_MCCR0_CLKHI_MASK 0x3F00u
5475 #define LPI2C_MCCR0_CLKHI_SHIFT 8u
5476 #define LPI2C_MCCR0_CLKHI_WIDTH 6u
5477 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKHI_SHIFT))&LPI2C_MCCR0_CLKHI_MASK)
5478 #define LPI2C_MCCR0_SETHOLD_MASK 0x3F0000u
5479 #define LPI2C_MCCR0_SETHOLD_SHIFT 16u
5480 #define LPI2C_MCCR0_SETHOLD_WIDTH 6u
5481 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_SETHOLD_SHIFT))&LPI2C_MCCR0_SETHOLD_MASK)
5482 #define LPI2C_MCCR0_DATAVD_MASK 0x3F000000u
5483 #define LPI2C_MCCR0_DATAVD_SHIFT 24u
5484 #define LPI2C_MCCR0_DATAVD_WIDTH 6u
5485 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_DATAVD_SHIFT))&LPI2C_MCCR0_DATAVD_MASK)
5486 /* MCCR1 Bit Fields */
5487 #define LPI2C_MCCR1_CLKLO_MASK 0x3Fu
5488 #define LPI2C_MCCR1_CLKLO_SHIFT 0u
5489 #define LPI2C_MCCR1_CLKLO_WIDTH 6u
5490 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKLO_SHIFT))&LPI2C_MCCR1_CLKLO_MASK)
5491 #define LPI2C_MCCR1_CLKHI_MASK 0x3F00u
5492 #define LPI2C_MCCR1_CLKHI_SHIFT 8u
5493 #define LPI2C_MCCR1_CLKHI_WIDTH 6u
5494 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKHI_SHIFT))&LPI2C_MCCR1_CLKHI_MASK)
5495 #define LPI2C_MCCR1_SETHOLD_MASK 0x3F0000u
5496 #define LPI2C_MCCR1_SETHOLD_SHIFT 16u
5497 #define LPI2C_MCCR1_SETHOLD_WIDTH 6u
5498 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_SETHOLD_SHIFT))&LPI2C_MCCR1_SETHOLD_MASK)
5499 #define LPI2C_MCCR1_DATAVD_MASK 0x3F000000u
5500 #define LPI2C_MCCR1_DATAVD_SHIFT 24u
5501 #define LPI2C_MCCR1_DATAVD_WIDTH 6u
5502 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_DATAVD_SHIFT))&LPI2C_MCCR1_DATAVD_MASK)
5503 /* MFCR Bit Fields */
5504 #define LPI2C_MFCR_TXWATER_MASK 0x3u
5505 #define LPI2C_MFCR_TXWATER_SHIFT 0u
5506 #define LPI2C_MFCR_TXWATER_WIDTH 2u
5507 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_TXWATER_SHIFT))&LPI2C_MFCR_TXWATER_MASK)
5508 #define LPI2C_MFCR_RXWATER_MASK 0x30000u
5509 #define LPI2C_MFCR_RXWATER_SHIFT 16u
5510 #define LPI2C_MFCR_RXWATER_WIDTH 2u
5511 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_RXWATER_SHIFT))&LPI2C_MFCR_RXWATER_MASK)
5512 /* MFSR Bit Fields */
5513 #define LPI2C_MFSR_TXCOUNT_MASK 0x7u
5514 #define LPI2C_MFSR_TXCOUNT_SHIFT 0u
5515 #define LPI2C_MFSR_TXCOUNT_WIDTH 3u
5516 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_TXCOUNT_SHIFT))&LPI2C_MFSR_TXCOUNT_MASK)
5517 #define LPI2C_MFSR_RXCOUNT_MASK 0x70000u
5518 #define LPI2C_MFSR_RXCOUNT_SHIFT 16u
5519 #define LPI2C_MFSR_RXCOUNT_WIDTH 3u
5520 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_RXCOUNT_SHIFT))&LPI2C_MFSR_RXCOUNT_MASK)
5521 /* MTDR Bit Fields */
5522 #define LPI2C_MTDR_DATA_MASK 0xFFu
5523 #define LPI2C_MTDR_DATA_SHIFT 0u
5524 #define LPI2C_MTDR_DATA_WIDTH 8u
5525 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_DATA_SHIFT))&LPI2C_MTDR_DATA_MASK)
5526 #define LPI2C_MTDR_CMD_MASK 0x700u
5527 #define LPI2C_MTDR_CMD_SHIFT 8u
5528 #define LPI2C_MTDR_CMD_WIDTH 3u
5529 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_CMD_SHIFT))&LPI2C_MTDR_CMD_MASK)
5530 /* MRDR Bit Fields */
5531 #define LPI2C_MRDR_DATA_MASK 0xFFu
5532 #define LPI2C_MRDR_DATA_SHIFT 0u
5533 #define LPI2C_MRDR_DATA_WIDTH 8u
5534 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_DATA_SHIFT))&LPI2C_MRDR_DATA_MASK)
5535 #define LPI2C_MRDR_RXEMPTY_MASK 0x4000u
5536 #define LPI2C_MRDR_RXEMPTY_SHIFT 14u
5537 #define LPI2C_MRDR_RXEMPTY_WIDTH 1u
5538 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_RXEMPTY_SHIFT))&LPI2C_MRDR_RXEMPTY_MASK)
5539 /* SCR Bit Fields */
5540 #define LPI2C_SCR_SEN_MASK 0x1u
5541 #define LPI2C_SCR_SEN_SHIFT 0u
5542 #define LPI2C_SCR_SEN_WIDTH 1u
5543 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_SEN_SHIFT))&LPI2C_SCR_SEN_MASK)
5544 #define LPI2C_SCR_RST_MASK 0x2u
5545 #define LPI2C_SCR_RST_SHIFT 1u
5546 #define LPI2C_SCR_RST_WIDTH 1u
5547 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RST_SHIFT))&LPI2C_SCR_RST_MASK)
5548 #define LPI2C_SCR_FILTEN_MASK 0x10u
5549 #define LPI2C_SCR_FILTEN_SHIFT 4u
5550 #define LPI2C_SCR_FILTEN_WIDTH 1u
5551 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTEN_SHIFT))&LPI2C_SCR_FILTEN_MASK)
5552 #define LPI2C_SCR_FILTDZ_MASK 0x20u
5553 #define LPI2C_SCR_FILTDZ_SHIFT 5u
5554 #define LPI2C_SCR_FILTDZ_WIDTH 1u
5555 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTDZ_SHIFT))&LPI2C_SCR_FILTDZ_MASK)
5556 /* SSR Bit Fields */
5557 #define LPI2C_SSR_TDF_MASK 0x1u
5558 #define LPI2C_SSR_TDF_SHIFT 0u
5559 #define LPI2C_SSR_TDF_WIDTH 1u
5560 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TDF_SHIFT))&LPI2C_SSR_TDF_MASK)
5561 #define LPI2C_SSR_RDF_MASK 0x2u
5562 #define LPI2C_SSR_RDF_SHIFT 1u
5563 #define LPI2C_SSR_RDF_WIDTH 1u
5564 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RDF_SHIFT))&LPI2C_SSR_RDF_MASK)
5565 #define LPI2C_SSR_AVF_MASK 0x4u
5566 #define LPI2C_SSR_AVF_SHIFT 2u
5567 #define LPI2C_SSR_AVF_WIDTH 1u
5568 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AVF_SHIFT))&LPI2C_SSR_AVF_MASK)
5569 #define LPI2C_SSR_TAF_MASK 0x8u
5570 #define LPI2C_SSR_TAF_SHIFT 3u
5571 #define LPI2C_SSR_TAF_WIDTH 1u
5572 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TAF_SHIFT))&LPI2C_SSR_TAF_MASK)
5573 #define LPI2C_SSR_RSF_MASK 0x100u
5574 #define LPI2C_SSR_RSF_SHIFT 8u
5575 #define LPI2C_SSR_RSF_WIDTH 1u
5576 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RSF_SHIFT))&LPI2C_SSR_RSF_MASK)
5577 #define LPI2C_SSR_SDF_MASK 0x200u
5578 #define LPI2C_SSR_SDF_SHIFT 9u
5579 #define LPI2C_SSR_SDF_WIDTH 1u
5580 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SDF_SHIFT))&LPI2C_SSR_SDF_MASK)
5581 #define LPI2C_SSR_BEF_MASK 0x400u
5582 #define LPI2C_SSR_BEF_SHIFT 10u
5583 #define LPI2C_SSR_BEF_WIDTH 1u
5584 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BEF_SHIFT))&LPI2C_SSR_BEF_MASK)
5585 #define LPI2C_SSR_FEF_MASK 0x800u
5586 #define LPI2C_SSR_FEF_SHIFT 11u
5587 #define LPI2C_SSR_FEF_WIDTH 1u
5588 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_FEF_SHIFT))&LPI2C_SSR_FEF_MASK)
5589 #define LPI2C_SSR_AM0F_MASK 0x1000u
5590 #define LPI2C_SSR_AM0F_SHIFT 12u
5591 #define LPI2C_SSR_AM0F_WIDTH 1u
5592 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM0F_SHIFT))&LPI2C_SSR_AM0F_MASK)
5593 #define LPI2C_SSR_AM1F_MASK 0x2000u
5594 #define LPI2C_SSR_AM1F_SHIFT 13u
5595 #define LPI2C_SSR_AM1F_WIDTH 1u
5596 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM1F_SHIFT))&LPI2C_SSR_AM1F_MASK)
5597 #define LPI2C_SSR_GCF_MASK 0x4000u
5598 #define LPI2C_SSR_GCF_SHIFT 14u
5599 #define LPI2C_SSR_GCF_WIDTH 1u
5600 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_GCF_SHIFT))&LPI2C_SSR_GCF_MASK)
5601 #define LPI2C_SSR_SARF_MASK 0x8000u
5602 #define LPI2C_SSR_SARF_SHIFT 15u
5603 #define LPI2C_SSR_SARF_WIDTH 1u
5604 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SARF_SHIFT))&LPI2C_SSR_SARF_MASK)
5605 #define LPI2C_SSR_SBF_MASK 0x1000000u
5606 #define LPI2C_SSR_SBF_SHIFT 24u
5607 #define LPI2C_SSR_SBF_WIDTH 1u
5608 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SBF_SHIFT))&LPI2C_SSR_SBF_MASK)
5609 #define LPI2C_SSR_BBF_MASK 0x2000000u
5610 #define LPI2C_SSR_BBF_SHIFT 25u
5611 #define LPI2C_SSR_BBF_WIDTH 1u
5612 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BBF_SHIFT))&LPI2C_SSR_BBF_MASK)
5613 /* SIER Bit Fields */
5614 #define LPI2C_SIER_TDIE_MASK 0x1u
5615 #define LPI2C_SIER_TDIE_SHIFT 0u
5616 #define LPI2C_SIER_TDIE_WIDTH 1u
5617 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TDIE_SHIFT))&LPI2C_SIER_TDIE_MASK)
5618 #define LPI2C_SIER_RDIE_MASK 0x2u
5619 #define LPI2C_SIER_RDIE_SHIFT 1u
5620 #define LPI2C_SIER_RDIE_WIDTH 1u
5621 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RDIE_SHIFT))&LPI2C_SIER_RDIE_MASK)
5622 #define LPI2C_SIER_AVIE_MASK 0x4u
5623 #define LPI2C_SIER_AVIE_SHIFT 2u
5624 #define LPI2C_SIER_AVIE_WIDTH 1u
5625 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AVIE_SHIFT))&LPI2C_SIER_AVIE_MASK)
5626 #define LPI2C_SIER_TAIE_MASK 0x8u
5627 #define LPI2C_SIER_TAIE_SHIFT 3u
5628 #define LPI2C_SIER_TAIE_WIDTH 1u
5629 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TAIE_SHIFT))&LPI2C_SIER_TAIE_MASK)
5630 #define LPI2C_SIER_RSIE_MASK 0x100u
5631 #define LPI2C_SIER_RSIE_SHIFT 8u
5632 #define LPI2C_SIER_RSIE_WIDTH 1u
5633 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RSIE_SHIFT))&LPI2C_SIER_RSIE_MASK)
5634 #define LPI2C_SIER_SDIE_MASK 0x200u
5635 #define LPI2C_SIER_SDIE_SHIFT 9u
5636 #define LPI2C_SIER_SDIE_WIDTH 1u
5637 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SDIE_SHIFT))&LPI2C_SIER_SDIE_MASK)
5638 #define LPI2C_SIER_BEIE_MASK 0x400u
5639 #define LPI2C_SIER_BEIE_SHIFT 10u
5640 #define LPI2C_SIER_BEIE_WIDTH 1u
5641 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_BEIE_SHIFT))&LPI2C_SIER_BEIE_MASK)
5642 #define LPI2C_SIER_FEIE_MASK 0x800u
5643 #define LPI2C_SIER_FEIE_SHIFT 11u
5644 #define LPI2C_SIER_FEIE_WIDTH 1u
5645 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_FEIE_SHIFT))&LPI2C_SIER_FEIE_MASK)
5646 #define LPI2C_SIER_AM0IE_MASK 0x1000u
5647 #define LPI2C_SIER_AM0IE_SHIFT 12u
5648 #define LPI2C_SIER_AM0IE_WIDTH 1u
5649 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM0IE_SHIFT))&LPI2C_SIER_AM0IE_MASK)
5650 #define LPI2C_SIER_AM1F_MASK 0x2000u
5651 #define LPI2C_SIER_AM1F_SHIFT 13u
5652 #define LPI2C_SIER_AM1F_WIDTH 1u
5653 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM1F_SHIFT))&LPI2C_SIER_AM1F_MASK)
5654 #define LPI2C_SIER_GCIE_MASK 0x4000u
5655 #define LPI2C_SIER_GCIE_SHIFT 14u
5656 #define LPI2C_SIER_GCIE_WIDTH 1u
5657 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_GCIE_SHIFT))&LPI2C_SIER_GCIE_MASK)
5658 #define LPI2C_SIER_SARIE_MASK 0x8000u
5659 #define LPI2C_SIER_SARIE_SHIFT 15u
5660 #define LPI2C_SIER_SARIE_WIDTH 1u
5661 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SARIE_SHIFT))&LPI2C_SIER_SARIE_MASK)
5662 /* SDER Bit Fields */
5663 #define LPI2C_SDER_TDDE_MASK 0x1u
5664 #define LPI2C_SDER_TDDE_SHIFT 0u
5665 #define LPI2C_SDER_TDDE_WIDTH 1u
5666 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_TDDE_SHIFT))&LPI2C_SDER_TDDE_MASK)
5667 #define LPI2C_SDER_RDDE_MASK 0x2u
5668 #define LPI2C_SDER_RDDE_SHIFT 1u
5669 #define LPI2C_SDER_RDDE_WIDTH 1u
5670 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_RDDE_SHIFT))&LPI2C_SDER_RDDE_MASK)
5671 #define LPI2C_SDER_AVDE_MASK 0x4u
5672 #define LPI2C_SDER_AVDE_SHIFT 2u
5673 #define LPI2C_SDER_AVDE_WIDTH 1u
5674 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_AVDE_SHIFT))&LPI2C_SDER_AVDE_MASK)
5675 /* SCFGR1 Bit Fields */
5676 #define LPI2C_SCFGR1_ADRSTALL_MASK 0x1u
5677 #define LPI2C_SCFGR1_ADRSTALL_SHIFT 0u
5678 #define LPI2C_SCFGR1_ADRSTALL_WIDTH 1u
5679 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADRSTALL_SHIFT))&LPI2C_SCFGR1_ADRSTALL_MASK)
5680 #define LPI2C_SCFGR1_RXSTALL_MASK 0x2u
5681 #define LPI2C_SCFGR1_RXSTALL_SHIFT 1u
5682 #define LPI2C_SCFGR1_RXSTALL_WIDTH 1u
5683 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXSTALL_SHIFT))&LPI2C_SCFGR1_RXSTALL_MASK)
5684 #define LPI2C_SCFGR1_TXDSTALL_MASK 0x4u
5685 #define LPI2C_SCFGR1_TXDSTALL_SHIFT 2u
5686 #define LPI2C_SCFGR1_TXDSTALL_WIDTH 1u
5687 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXDSTALL_SHIFT))&LPI2C_SCFGR1_TXDSTALL_MASK)
5688 #define LPI2C_SCFGR1_ACKSTALL_MASK 0x8u
5689 #define LPI2C_SCFGR1_ACKSTALL_SHIFT 3u
5690 #define LPI2C_SCFGR1_ACKSTALL_WIDTH 1u
5691 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ACKSTALL_SHIFT))&LPI2C_SCFGR1_ACKSTALL_MASK)
5692 #define LPI2C_SCFGR1_GCEN_MASK 0x100u
5693 #define LPI2C_SCFGR1_GCEN_SHIFT 8u
5694 #define LPI2C_SCFGR1_GCEN_WIDTH 1u
5695 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_GCEN_SHIFT))&LPI2C_SCFGR1_GCEN_MASK)
5696 #define LPI2C_SCFGR1_SAEN_MASK 0x200u
5697 #define LPI2C_SCFGR1_SAEN_SHIFT 9u
5698 #define LPI2C_SCFGR1_SAEN_WIDTH 1u
5699 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_SAEN_SHIFT))&LPI2C_SCFGR1_SAEN_MASK)
5700 #define LPI2C_SCFGR1_TXCFG_MASK 0x400u
5701 #define LPI2C_SCFGR1_TXCFG_SHIFT 10u
5702 #define LPI2C_SCFGR1_TXCFG_WIDTH 1u
5703 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXCFG_SHIFT))&LPI2C_SCFGR1_TXCFG_MASK)
5704 #define LPI2C_SCFGR1_RXCFG_MASK 0x800u
5705 #define LPI2C_SCFGR1_RXCFG_SHIFT 11u
5706 #define LPI2C_SCFGR1_RXCFG_WIDTH 1u
5707 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXCFG_SHIFT))&LPI2C_SCFGR1_RXCFG_MASK)
5708 #define LPI2C_SCFGR1_IGNACK_MASK 0x1000u
5709 #define LPI2C_SCFGR1_IGNACK_SHIFT 12u
5710 #define LPI2C_SCFGR1_IGNACK_WIDTH 1u
5711 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_IGNACK_SHIFT))&LPI2C_SCFGR1_IGNACK_MASK)
5712 #define LPI2C_SCFGR1_HSMEN_MASK 0x2000u
5713 #define LPI2C_SCFGR1_HSMEN_SHIFT 13u
5714 #define LPI2C_SCFGR1_HSMEN_WIDTH 1u
5715 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_HSMEN_SHIFT))&LPI2C_SCFGR1_HSMEN_MASK)
5716 #define LPI2C_SCFGR1_ADDRCFG_MASK 0x70000u
5717 #define LPI2C_SCFGR1_ADDRCFG_SHIFT 16u
5718 #define LPI2C_SCFGR1_ADDRCFG_WIDTH 3u
5719 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADDRCFG_SHIFT))&LPI2C_SCFGR1_ADDRCFG_MASK)
5720 /* SCFGR2 Bit Fields */
5721 #define LPI2C_SCFGR2_CLKHOLD_MASK 0xFu
5722 #define LPI2C_SCFGR2_CLKHOLD_SHIFT 0u
5723 #define LPI2C_SCFGR2_CLKHOLD_WIDTH 4u
5724 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_CLKHOLD_SHIFT))&LPI2C_SCFGR2_CLKHOLD_MASK)
5725 #define LPI2C_SCFGR2_DATAVD_MASK 0x3F00u
5726 #define LPI2C_SCFGR2_DATAVD_SHIFT 8u
5727 #define LPI2C_SCFGR2_DATAVD_WIDTH 6u
5728 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_DATAVD_SHIFT))&LPI2C_SCFGR2_DATAVD_MASK)
5729 #define LPI2C_SCFGR2_FILTSCL_MASK 0xF0000u
5730 #define LPI2C_SCFGR2_FILTSCL_SHIFT 16u
5731 #define LPI2C_SCFGR2_FILTSCL_WIDTH 4u
5732 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSCL_SHIFT))&LPI2C_SCFGR2_FILTSCL_MASK)
5733 #define LPI2C_SCFGR2_FILTSDA_MASK 0xF000000u
5734 #define LPI2C_SCFGR2_FILTSDA_SHIFT 24u
5735 #define LPI2C_SCFGR2_FILTSDA_WIDTH 4u
5736 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSDA_SHIFT))&LPI2C_SCFGR2_FILTSDA_MASK)
5737 /* SAMR Bit Fields */
5738 #define LPI2C_SAMR_ADDR0_MASK 0x7FEu
5739 #define LPI2C_SAMR_ADDR0_SHIFT 1u
5740 #define LPI2C_SAMR_ADDR0_WIDTH 10u
5741 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR0_SHIFT))&LPI2C_SAMR_ADDR0_MASK)
5742 #define LPI2C_SAMR_ADDR1_MASK 0x7FE0000u
5743 #define LPI2C_SAMR_ADDR1_SHIFT 17u
5744 #define LPI2C_SAMR_ADDR1_WIDTH 10u
5745 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR1_SHIFT))&LPI2C_SAMR_ADDR1_MASK)
5746 /* SASR Bit Fields */
5747 #define LPI2C_SASR_RADDR_MASK 0x7FFu
5748 #define LPI2C_SASR_RADDR_SHIFT 0u
5749 #define LPI2C_SASR_RADDR_WIDTH 11u
5750 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_RADDR_SHIFT))&LPI2C_SASR_RADDR_MASK)
5751 #define LPI2C_SASR_ANV_MASK 0x4000u
5752 #define LPI2C_SASR_ANV_SHIFT 14u
5753 #define LPI2C_SASR_ANV_WIDTH 1u
5754 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_ANV_SHIFT))&LPI2C_SASR_ANV_MASK)
5755 /* STAR Bit Fields */
5756 #define LPI2C_STAR_TXNACK_MASK 0x1u
5757 #define LPI2C_STAR_TXNACK_SHIFT 0u
5758 #define LPI2C_STAR_TXNACK_WIDTH 1u
5759 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STAR_TXNACK_SHIFT))&LPI2C_STAR_TXNACK_MASK)
5760 /* STDR Bit Fields */
5761 #define LPI2C_STDR_DATA_MASK 0xFFu
5762 #define LPI2C_STDR_DATA_SHIFT 0u
5763 #define LPI2C_STDR_DATA_WIDTH 8u
5764 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STDR_DATA_SHIFT))&LPI2C_STDR_DATA_MASK)
5765 /* SRDR Bit Fields */
5766 #define LPI2C_SRDR_DATA_MASK 0xFFu
5767 #define LPI2C_SRDR_DATA_SHIFT 0u
5768 #define LPI2C_SRDR_DATA_WIDTH 8u
5769 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_DATA_SHIFT))&LPI2C_SRDR_DATA_MASK)
5770 #define LPI2C_SRDR_RXEMPTY_MASK 0x4000u
5771 #define LPI2C_SRDR_RXEMPTY_SHIFT 14u
5772 #define LPI2C_SRDR_RXEMPTY_WIDTH 1u
5773 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_RXEMPTY_SHIFT))&LPI2C_SRDR_RXEMPTY_MASK)
5774 #define LPI2C_SRDR_SOF_MASK 0x8000u
5775 #define LPI2C_SRDR_SOF_SHIFT 15u
5776 #define LPI2C_SRDR_SOF_WIDTH 1u
5777 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_SOF_SHIFT))&LPI2C_SRDR_SOF_MASK)
5778  /* end of group LPI2C_Register_Masks */
5782 
5783  /* end of group LPI2C_Peripheral_Access_Layer */
5787 
5788 
5789 /* ----------------------------------------------------------------------------
5790  -- LPIT Peripheral Access Layer
5791  ---------------------------------------------------------------------------- */
5792 
5800 #define LPIT_TMR_COUNT 4u
5801 
5803 typedef struct {
5804  __I uint32_t VERID;
5805  __I uint32_t PARAM;
5806  __IO uint32_t MCR;
5807  __IO uint32_t MSR;
5808  __IO uint32_t MIER;
5809  __IO uint32_t SETTEN;
5810  __IO uint32_t CLRTEN;
5811  uint8_t RESERVED_0[4];
5812  struct { /* offset: 0x20, array step: 0x10 */
5813  __IO uint32_t TVAL;
5814  __I uint32_t CVAL;
5815  __IO uint32_t TCTRL;
5816  uint8_t RESERVED_0[4];
5817  } TMR[LPIT_TMR_COUNT];
5819 
5821 #define LPIT_INSTANCE_COUNT (1u)
5822 
5823 
5824 /* LPIT - Peripheral instance base addresses */
5826 #define LPIT0_BASE (0x40037000u)
5827 
5828 #define LPIT0 ((LPIT_Type *)LPIT0_BASE)
5829 
5830 #define LPIT_BASE_ADDRS { LPIT0_BASE }
5831 
5832 #define LPIT_BASE_PTRS { LPIT0 }
5833 
5834 #define LPIT_IRQS_ARR_COUNT (1u)
5835 
5836 #define LPIT_IRQS_CH_COUNT (1u)
5837 
5838 #define LPIT_IRQS { LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn, LPIT0_IRQn }
5839 
5840 /* ----------------------------------------------------------------------------
5841  -- LPIT Register Masks
5842  ---------------------------------------------------------------------------- */
5843 
5849 /* VERID Bit Fields */
5850 #define LPIT_VERID_FEATURE_MASK 0xFFFFu
5851 #define LPIT_VERID_FEATURE_SHIFT 0u
5852 #define LPIT_VERID_FEATURE_WIDTH 16u
5853 #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_FEATURE_SHIFT))&LPIT_VERID_FEATURE_MASK)
5854 #define LPIT_VERID_MINOR_MASK 0xFF0000u
5855 #define LPIT_VERID_MINOR_SHIFT 16u
5856 #define LPIT_VERID_MINOR_WIDTH 8u
5857 #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MINOR_SHIFT))&LPIT_VERID_MINOR_MASK)
5858 #define LPIT_VERID_MAJOR_MASK 0xFF000000u
5859 #define LPIT_VERID_MAJOR_SHIFT 24u
5860 #define LPIT_VERID_MAJOR_WIDTH 8u
5861 #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MAJOR_SHIFT))&LPIT_VERID_MAJOR_MASK)
5862 /* PARAM Bit Fields */
5863 #define LPIT_PARAM_CHANNEL_MASK 0xFFu
5864 #define LPIT_PARAM_CHANNEL_SHIFT 0u
5865 #define LPIT_PARAM_CHANNEL_WIDTH 8u
5866 #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_CHANNEL_SHIFT))&LPIT_PARAM_CHANNEL_MASK)
5867 #define LPIT_PARAM_EXT_TRIG_MASK 0xFF00u
5868 #define LPIT_PARAM_EXT_TRIG_SHIFT 8u
5869 #define LPIT_PARAM_EXT_TRIG_WIDTH 8u
5870 #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_EXT_TRIG_SHIFT))&LPIT_PARAM_EXT_TRIG_MASK)
5871 /* MCR Bit Fields */
5872 #define LPIT_MCR_M_CEN_MASK 0x1u
5873 #define LPIT_MCR_M_CEN_SHIFT 0u
5874 #define LPIT_MCR_M_CEN_WIDTH 1u
5875 #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_M_CEN_SHIFT))&LPIT_MCR_M_CEN_MASK)
5876 #define LPIT_MCR_SW_RST_MASK 0x2u
5877 #define LPIT_MCR_SW_RST_SHIFT 1u
5878 #define LPIT_MCR_SW_RST_WIDTH 1u
5879 #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_SW_RST_SHIFT))&LPIT_MCR_SW_RST_MASK)
5880 #define LPIT_MCR_DOZE_EN_MASK 0x4u
5881 #define LPIT_MCR_DOZE_EN_SHIFT 2u
5882 #define LPIT_MCR_DOZE_EN_WIDTH 1u
5883 #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DOZE_EN_SHIFT))&LPIT_MCR_DOZE_EN_MASK)
5884 #define LPIT_MCR_DBG_EN_MASK 0x8u
5885 #define LPIT_MCR_DBG_EN_SHIFT 3u
5886 #define LPIT_MCR_DBG_EN_WIDTH 1u
5887 #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DBG_EN_SHIFT))&LPIT_MCR_DBG_EN_MASK)
5888 /* MSR Bit Fields */
5889 #define LPIT_MSR_TIF0_MASK 0x1u
5890 #define LPIT_MSR_TIF0_SHIFT 0u
5891 #define LPIT_MSR_TIF0_WIDTH 1u
5892 #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF0_SHIFT))&LPIT_MSR_TIF0_MASK)
5893 #define LPIT_MSR_TIF1_MASK 0x2u
5894 #define LPIT_MSR_TIF1_SHIFT 1u
5895 #define LPIT_MSR_TIF1_WIDTH 1u
5896 #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF1_SHIFT))&LPIT_MSR_TIF1_MASK)
5897 #define LPIT_MSR_TIF2_MASK 0x4u
5898 #define LPIT_MSR_TIF2_SHIFT 2u
5899 #define LPIT_MSR_TIF2_WIDTH 1u
5900 #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF2_SHIFT))&LPIT_MSR_TIF2_MASK)
5901 #define LPIT_MSR_TIF3_MASK 0x8u
5902 #define LPIT_MSR_TIF3_SHIFT 3u
5903 #define LPIT_MSR_TIF3_WIDTH 1u
5904 #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF3_SHIFT))&LPIT_MSR_TIF3_MASK)
5905 /* MIER Bit Fields */
5906 #define LPIT_MIER_TIE0_MASK 0x1u
5907 #define LPIT_MIER_TIE0_SHIFT 0u
5908 #define LPIT_MIER_TIE0_WIDTH 1u
5909 #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE0_SHIFT))&LPIT_MIER_TIE0_MASK)
5910 #define LPIT_MIER_TIE1_MASK 0x2u
5911 #define LPIT_MIER_TIE1_SHIFT 1u
5912 #define LPIT_MIER_TIE1_WIDTH 1u
5913 #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE1_SHIFT))&LPIT_MIER_TIE1_MASK)
5914 #define LPIT_MIER_TIE2_MASK 0x4u
5915 #define LPIT_MIER_TIE2_SHIFT 2u
5916 #define LPIT_MIER_TIE2_WIDTH 1u
5917 #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE2_SHIFT))&LPIT_MIER_TIE2_MASK)
5918 #define LPIT_MIER_TIE3_MASK 0x8u
5919 #define LPIT_MIER_TIE3_SHIFT 3u
5920 #define LPIT_MIER_TIE3_WIDTH 1u
5921 #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE3_SHIFT))&LPIT_MIER_TIE3_MASK)
5922 /* SETTEN Bit Fields */
5923 #define LPIT_SETTEN_SET_T_EN_0_MASK 0x1u
5924 #define LPIT_SETTEN_SET_T_EN_0_SHIFT 0u
5925 #define LPIT_SETTEN_SET_T_EN_0_WIDTH 1u
5926 #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_0_SHIFT))&LPIT_SETTEN_SET_T_EN_0_MASK)
5927 #define LPIT_SETTEN_SET_T_EN_1_MASK 0x2u
5928 #define LPIT_SETTEN_SET_T_EN_1_SHIFT 1u
5929 #define LPIT_SETTEN_SET_T_EN_1_WIDTH 1u
5930 #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_1_SHIFT))&LPIT_SETTEN_SET_T_EN_1_MASK)
5931 #define LPIT_SETTEN_SET_T_EN_2_MASK 0x4u
5932 #define LPIT_SETTEN_SET_T_EN_2_SHIFT 2u
5933 #define LPIT_SETTEN_SET_T_EN_2_WIDTH 1u
5934 #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_2_SHIFT))&LPIT_SETTEN_SET_T_EN_2_MASK)
5935 #define LPIT_SETTEN_SET_T_EN_3_MASK 0x8u
5936 #define LPIT_SETTEN_SET_T_EN_3_SHIFT 3u
5937 #define LPIT_SETTEN_SET_T_EN_3_WIDTH 1u
5938 #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_3_SHIFT))&LPIT_SETTEN_SET_T_EN_3_MASK)
5939 /* CLRTEN Bit Fields */
5940 #define LPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
5941 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT 0u
5942 #define LPIT_CLRTEN_CLR_T_EN_0_WIDTH 1u
5943 #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_0_SHIFT))&LPIT_CLRTEN_CLR_T_EN_0_MASK)
5944 #define LPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
5945 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT 1u
5946 #define LPIT_CLRTEN_CLR_T_EN_1_WIDTH 1u
5947 #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_1_SHIFT))&LPIT_CLRTEN_CLR_T_EN_1_MASK)
5948 #define LPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
5949 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT 2u
5950 #define LPIT_CLRTEN_CLR_T_EN_2_WIDTH 1u
5951 #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_2_SHIFT))&LPIT_CLRTEN_CLR_T_EN_2_MASK)
5952 #define LPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
5953 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT 3u
5954 #define LPIT_CLRTEN_CLR_T_EN_3_WIDTH 1u
5955 #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_3_SHIFT))&LPIT_CLRTEN_CLR_T_EN_3_MASK)
5956 /* TMR_TVAL Bit Fields */
5957 #define LPIT_TMR_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
5958 #define LPIT_TMR_TVAL_TMR_VAL_SHIFT 0u
5959 #define LPIT_TMR_TVAL_TMR_VAL_WIDTH 32u
5960 #define LPIT_TMR_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TVAL_TMR_VAL_SHIFT))&LPIT_TMR_TVAL_TMR_VAL_MASK)
5961 /* TMR_CVAL Bit Fields */
5962 #define LPIT_TMR_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
5963 #define LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT 0u
5964 #define LPIT_TMR_CVAL_TMR_CUR_VAL_WIDTH 32u
5965 #define LPIT_TMR_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT))&LPIT_TMR_CVAL_TMR_CUR_VAL_MASK)
5966 /* TMR_TCTRL Bit Fields */
5967 #define LPIT_TMR_TCTRL_T_EN_MASK 0x1u
5968 #define LPIT_TMR_TCTRL_T_EN_SHIFT 0u
5969 #define LPIT_TMR_TCTRL_T_EN_WIDTH 1u
5970 #define LPIT_TMR_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_T_EN_SHIFT))&LPIT_TMR_TCTRL_T_EN_MASK)
5971 #define LPIT_TMR_TCTRL_CHAIN_MASK 0x2u
5972 #define LPIT_TMR_TCTRL_CHAIN_SHIFT 1u
5973 #define LPIT_TMR_TCTRL_CHAIN_WIDTH 1u
5974 #define LPIT_TMR_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_CHAIN_SHIFT))&LPIT_TMR_TCTRL_CHAIN_MASK)
5975 #define LPIT_TMR_TCTRL_MODE_MASK 0xCu
5976 #define LPIT_TMR_TCTRL_MODE_SHIFT 2u
5977 #define LPIT_TMR_TCTRL_MODE_WIDTH 2u
5978 #define LPIT_TMR_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_MODE_SHIFT))&LPIT_TMR_TCTRL_MODE_MASK)
5979 #define LPIT_TMR_TCTRL_TSOT_MASK 0x10000u
5980 #define LPIT_TMR_TCTRL_TSOT_SHIFT 16u
5981 #define LPIT_TMR_TCTRL_TSOT_WIDTH 1u
5982 #define LPIT_TMR_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOT_SHIFT))&LPIT_TMR_TCTRL_TSOT_MASK)
5983 #define LPIT_TMR_TCTRL_TSOI_MASK 0x20000u
5984 #define LPIT_TMR_TCTRL_TSOI_SHIFT 17u
5985 #define LPIT_TMR_TCTRL_TSOI_WIDTH 1u
5986 #define LPIT_TMR_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOI_SHIFT))&LPIT_TMR_TCTRL_TSOI_MASK)
5987 #define LPIT_TMR_TCTRL_TROT_MASK 0x40000u
5988 #define LPIT_TMR_TCTRL_TROT_SHIFT 18u
5989 #define LPIT_TMR_TCTRL_TROT_WIDTH 1u
5990 #define LPIT_TMR_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TROT_SHIFT))&LPIT_TMR_TCTRL_TROT_MASK)
5991 #define LPIT_TMR_TCTRL_TRG_SRC_MASK 0x800000u
5992 #define LPIT_TMR_TCTRL_TRG_SRC_SHIFT 23u
5993 #define LPIT_TMR_TCTRL_TRG_SRC_WIDTH 1u
5994 #define LPIT_TMR_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SRC_SHIFT))&LPIT_TMR_TCTRL_TRG_SRC_MASK)
5995 #define LPIT_TMR_TCTRL_TRG_SEL_MASK 0xF000000u
5996 #define LPIT_TMR_TCTRL_TRG_SEL_SHIFT 24u
5997 #define LPIT_TMR_TCTRL_TRG_SEL_WIDTH 4u
5998 #define LPIT_TMR_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SEL_SHIFT))&LPIT_TMR_TCTRL_TRG_SEL_MASK)
5999  /* end of group LPIT_Register_Masks */
6003 
6004  /* end of group LPIT_Peripheral_Access_Layer */
6008 
6009 
6010 /* ----------------------------------------------------------------------------
6011  -- LPSPI Peripheral Access Layer
6012  ---------------------------------------------------------------------------- */
6013 
6023 typedef struct {
6024  __I uint32_t VERID;
6025  __I uint32_t PARAM;
6026  uint8_t RESERVED_0[8];
6027  __IO uint32_t CR;
6028  __IO uint32_t SR;
6029  __IO uint32_t IER;
6030  __IO uint32_t DER;
6031  __IO uint32_t CFGR0;
6032  __IO uint32_t CFGR1;
6033  uint8_t RESERVED_1[8];
6034  __IO uint32_t DMR0;
6035  __IO uint32_t DMR1;
6036  uint8_t RESERVED_2[8];
6037  __IO uint32_t CCR;
6038  uint8_t RESERVED_3[20];
6039  __IO uint32_t FCR;
6040  __I uint32_t FSR;
6041  __IO uint32_t TCR;
6042  __O uint32_t TDR;
6043  uint8_t RESERVED_4[8];
6044  __I uint32_t RSR;
6045  __I uint32_t RDR;
6047 
6049 #define LPSPI_INSTANCE_COUNT (2u)
6050 
6051 
6052 /* LPSPI - Peripheral instance base addresses */
6054 #define LPSPI0_BASE (0x4002C000u)
6055 
6056 #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
6057 
6058 #define LPSPI1_BASE (0x4002D000u)
6059 
6060 #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
6061 
6062 #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE }
6063 
6064 #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 }
6065 
6066 #define LPSPI_IRQS_ARR_COUNT (1u)
6067 
6068 #define LPSPI_IRQS_CH_COUNT (1u)
6069 
6070 #define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn }
6071 
6072 /* ----------------------------------------------------------------------------
6073  -- LPSPI Register Masks
6074  ---------------------------------------------------------------------------- */
6075 
6081 /* VERID Bit Fields */
6082 #define LPSPI_VERID_FEATURE_MASK 0xFFFFu
6083 #define LPSPI_VERID_FEATURE_SHIFT 0u
6084 #define LPSPI_VERID_FEATURE_WIDTH 16u
6085 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_FEATURE_SHIFT))&LPSPI_VERID_FEATURE_MASK)
6086 #define LPSPI_VERID_MINOR_MASK 0xFF0000u
6087 #define LPSPI_VERID_MINOR_SHIFT 16u
6088 #define LPSPI_VERID_MINOR_WIDTH 8u
6089 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MINOR_SHIFT))&LPSPI_VERID_MINOR_MASK)
6090 #define LPSPI_VERID_MAJOR_MASK 0xFF000000u
6091 #define LPSPI_VERID_MAJOR_SHIFT 24u
6092 #define LPSPI_VERID_MAJOR_WIDTH 8u
6093 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MAJOR_SHIFT))&LPSPI_VERID_MAJOR_MASK)
6094 /* PARAM Bit Fields */
6095 #define LPSPI_PARAM_TXFIFO_MASK 0xFFu
6096 #define LPSPI_PARAM_TXFIFO_SHIFT 0u
6097 #define LPSPI_PARAM_TXFIFO_WIDTH 8u
6098 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_TXFIFO_SHIFT))&LPSPI_PARAM_TXFIFO_MASK)
6099 #define LPSPI_PARAM_RXFIFO_MASK 0xFF00u
6100 #define LPSPI_PARAM_RXFIFO_SHIFT 8u
6101 #define LPSPI_PARAM_RXFIFO_WIDTH 8u
6102 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_RXFIFO_SHIFT))&LPSPI_PARAM_RXFIFO_MASK)
6103 /* CR Bit Fields */
6104 #define LPSPI_CR_MEN_MASK 0x1u
6105 #define LPSPI_CR_MEN_SHIFT 0u
6106 #define LPSPI_CR_MEN_WIDTH 1u
6107 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_MEN_SHIFT))&LPSPI_CR_MEN_MASK)
6108 #define LPSPI_CR_RST_MASK 0x2u
6109 #define LPSPI_CR_RST_SHIFT 1u
6110 #define LPSPI_CR_RST_WIDTH 1u
6111 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RST_SHIFT))&LPSPI_CR_RST_MASK)
6112 #define LPSPI_CR_DOZEN_MASK 0x4u
6113 #define LPSPI_CR_DOZEN_SHIFT 2u
6114 #define LPSPI_CR_DOZEN_WIDTH 1u
6115 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DOZEN_SHIFT))&LPSPI_CR_DOZEN_MASK)
6116 #define LPSPI_CR_DBGEN_MASK 0x8u
6117 #define LPSPI_CR_DBGEN_SHIFT 3u
6118 #define LPSPI_CR_DBGEN_WIDTH 1u
6119 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DBGEN_SHIFT))&LPSPI_CR_DBGEN_MASK)
6120 #define LPSPI_CR_RTF_MASK 0x100u
6121 #define LPSPI_CR_RTF_SHIFT 8u
6122 #define LPSPI_CR_RTF_WIDTH 1u
6123 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RTF_SHIFT))&LPSPI_CR_RTF_MASK)
6124 #define LPSPI_CR_RRF_MASK 0x200u
6125 #define LPSPI_CR_RRF_SHIFT 9u
6126 #define LPSPI_CR_RRF_WIDTH 1u
6127 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RRF_SHIFT))&LPSPI_CR_RRF_MASK)
6128 /* SR Bit Fields */
6129 #define LPSPI_SR_TDF_MASK 0x1u
6130 #define LPSPI_SR_TDF_SHIFT 0u
6131 #define LPSPI_SR_TDF_WIDTH 1u
6132 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TDF_SHIFT))&LPSPI_SR_TDF_MASK)
6133 #define LPSPI_SR_RDF_MASK 0x2u
6134 #define LPSPI_SR_RDF_SHIFT 1u
6135 #define LPSPI_SR_RDF_WIDTH 1u
6136 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_RDF_SHIFT))&LPSPI_SR_RDF_MASK)
6137 #define LPSPI_SR_WCF_MASK 0x100u
6138 #define LPSPI_SR_WCF_SHIFT 8u
6139 #define LPSPI_SR_WCF_WIDTH 1u
6140 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_WCF_SHIFT))&LPSPI_SR_WCF_MASK)
6141 #define LPSPI_SR_FCF_MASK 0x200u
6142 #define LPSPI_SR_FCF_SHIFT 9u
6143 #define LPSPI_SR_FCF_WIDTH 1u
6144 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_FCF_SHIFT))&LPSPI_SR_FCF_MASK)
6145 #define LPSPI_SR_TCF_MASK 0x400u
6146 #define LPSPI_SR_TCF_SHIFT 10u
6147 #define LPSPI_SR_TCF_WIDTH 1u
6148 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TCF_SHIFT))&LPSPI_SR_TCF_MASK)
6149 #define LPSPI_SR_TEF_MASK 0x800u
6150 #define LPSPI_SR_TEF_SHIFT 11u
6151 #define LPSPI_SR_TEF_WIDTH 1u
6152 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TEF_SHIFT))&LPSPI_SR_TEF_MASK)
6153 #define LPSPI_SR_REF_MASK 0x1000u
6154 #define LPSPI_SR_REF_SHIFT 12u
6155 #define LPSPI_SR_REF_WIDTH 1u
6156 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_REF_SHIFT))&LPSPI_SR_REF_MASK)
6157 #define LPSPI_SR_DMF_MASK 0x2000u
6158 #define LPSPI_SR_DMF_SHIFT 13u
6159 #define LPSPI_SR_DMF_WIDTH 1u
6160 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_DMF_SHIFT))&LPSPI_SR_DMF_MASK)
6161 #define LPSPI_SR_MBF_MASK 0x1000000u
6162 #define LPSPI_SR_MBF_SHIFT 24u
6163 #define LPSPI_SR_MBF_WIDTH 1u
6164 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_MBF_SHIFT))&LPSPI_SR_MBF_MASK)
6165 /* IER Bit Fields */
6166 #define LPSPI_IER_TDIE_MASK 0x1u
6167 #define LPSPI_IER_TDIE_SHIFT 0u
6168 #define LPSPI_IER_TDIE_WIDTH 1u
6169 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TDIE_SHIFT))&LPSPI_IER_TDIE_MASK)
6170 #define LPSPI_IER_RDIE_MASK 0x2u
6171 #define LPSPI_IER_RDIE_SHIFT 1u
6172 #define LPSPI_IER_RDIE_WIDTH 1u
6173 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_RDIE_SHIFT))&LPSPI_IER_RDIE_MASK)
6174 #define LPSPI_IER_WCIE_MASK 0x100u
6175 #define LPSPI_IER_WCIE_SHIFT 8u
6176 #define LPSPI_IER_WCIE_WIDTH 1u
6177 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_WCIE_SHIFT))&LPSPI_IER_WCIE_MASK)
6178 #define LPSPI_IER_FCIE_MASK 0x200u
6179 #define LPSPI_IER_FCIE_SHIFT 9u
6180 #define LPSPI_IER_FCIE_WIDTH 1u
6181 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_FCIE_SHIFT))&LPSPI_IER_FCIE_MASK)
6182 #define LPSPI_IER_TCIE_MASK 0x400u
6183 #define LPSPI_IER_TCIE_SHIFT 10u
6184 #define LPSPI_IER_TCIE_WIDTH 1u
6185 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TCIE_SHIFT))&LPSPI_IER_TCIE_MASK)
6186 #define LPSPI_IER_TEIE_MASK 0x800u
6187 #define LPSPI_IER_TEIE_SHIFT 11u
6188 #define LPSPI_IER_TEIE_WIDTH 1u
6189 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TEIE_SHIFT))&LPSPI_IER_TEIE_MASK)
6190 #define LPSPI_IER_REIE_MASK 0x1000u
6191 #define LPSPI_IER_REIE_SHIFT 12u
6192 #define LPSPI_IER_REIE_WIDTH 1u
6193 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_REIE_SHIFT))&LPSPI_IER_REIE_MASK)
6194 #define LPSPI_IER_DMIE_MASK 0x2000u
6195 #define LPSPI_IER_DMIE_SHIFT 13u
6196 #define LPSPI_IER_DMIE_WIDTH 1u
6197 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_DMIE_SHIFT))&LPSPI_IER_DMIE_MASK)
6198 /* DER Bit Fields */
6199 #define LPSPI_DER_TDDE_MASK 0x1u
6200 #define LPSPI_DER_TDDE_SHIFT 0u
6201 #define LPSPI_DER_TDDE_WIDTH 1u
6202 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_TDDE_SHIFT))&LPSPI_DER_TDDE_MASK)
6203 #define LPSPI_DER_RDDE_MASK 0x2u
6204 #define LPSPI_DER_RDDE_SHIFT 1u
6205 #define LPSPI_DER_RDDE_WIDTH 1u
6206 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_RDDE_SHIFT))&LPSPI_DER_RDDE_MASK)
6207 /* CFGR0 Bit Fields */
6208 #define LPSPI_CFGR0_HREN_MASK 0x1u
6209 #define LPSPI_CFGR0_HREN_SHIFT 0u
6210 #define LPSPI_CFGR0_HREN_WIDTH 1u
6211 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HREN_SHIFT))&LPSPI_CFGR0_HREN_MASK)
6212 #define LPSPI_CFGR0_HRPOL_MASK 0x2u
6213 #define LPSPI_CFGR0_HRPOL_SHIFT 1u
6214 #define LPSPI_CFGR0_HRPOL_WIDTH 1u
6215 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRPOL_SHIFT))&LPSPI_CFGR0_HRPOL_MASK)
6216 #define LPSPI_CFGR0_HRSEL_MASK 0x4u
6217 #define LPSPI_CFGR0_HRSEL_SHIFT 2u
6218 #define LPSPI_CFGR0_HRSEL_WIDTH 1u
6219 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRSEL_SHIFT))&LPSPI_CFGR0_HRSEL_MASK)
6220 #define LPSPI_CFGR0_CIRFIFO_MASK 0x100u
6221 #define LPSPI_CFGR0_CIRFIFO_SHIFT 8u
6222 #define LPSPI_CFGR0_CIRFIFO_WIDTH 1u
6223 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_CIRFIFO_SHIFT))&LPSPI_CFGR0_CIRFIFO_MASK)
6224 #define LPSPI_CFGR0_RDMO_MASK 0x200u
6225 #define LPSPI_CFGR0_RDMO_SHIFT 9u
6226 #define LPSPI_CFGR0_RDMO_WIDTH 1u
6227 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_RDMO_SHIFT))&LPSPI_CFGR0_RDMO_MASK)
6228 /* CFGR1 Bit Fields */
6229 #define LPSPI_CFGR1_MASTER_MASK 0x1u
6230 #define LPSPI_CFGR1_MASTER_SHIFT 0u
6231 #define LPSPI_CFGR1_MASTER_WIDTH 1u
6232 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MASTER_SHIFT))&LPSPI_CFGR1_MASTER_MASK)
6233 #define LPSPI_CFGR1_SAMPLE_MASK 0x2u
6234 #define LPSPI_CFGR1_SAMPLE_SHIFT 1u
6235 #define LPSPI_CFGR1_SAMPLE_WIDTH 1u
6236 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_SAMPLE_SHIFT))&LPSPI_CFGR1_SAMPLE_MASK)
6237 #define LPSPI_CFGR1_AUTOPCS_MASK 0x4u
6238 #define LPSPI_CFGR1_AUTOPCS_SHIFT 2u
6239 #define LPSPI_CFGR1_AUTOPCS_WIDTH 1u
6240 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_AUTOPCS_SHIFT))&LPSPI_CFGR1_AUTOPCS_MASK)
6241 #define LPSPI_CFGR1_NOSTALL_MASK 0x8u
6242 #define LPSPI_CFGR1_NOSTALL_SHIFT 3u
6243 #define LPSPI_CFGR1_NOSTALL_WIDTH 1u
6244 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_NOSTALL_SHIFT))&LPSPI_CFGR1_NOSTALL_MASK)
6245 #define LPSPI_CFGR1_PCSPOL_MASK 0xF00u
6246 #define LPSPI_CFGR1_PCSPOL_SHIFT 8u
6247 #define LPSPI_CFGR1_PCSPOL_WIDTH 4u
6248 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSPOL_SHIFT))&LPSPI_CFGR1_PCSPOL_MASK)
6249 #define LPSPI_CFGR1_MATCFG_MASK 0x70000u
6250 #define LPSPI_CFGR1_MATCFG_SHIFT 16u
6251 #define LPSPI_CFGR1_MATCFG_WIDTH 3u
6252 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MATCFG_SHIFT))&LPSPI_CFGR1_MATCFG_MASK)
6253 #define LPSPI_CFGR1_PINCFG_MASK 0x3000000u
6254 #define LPSPI_CFGR1_PINCFG_SHIFT 24u
6255 #define LPSPI_CFGR1_PINCFG_WIDTH 2u
6256 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PINCFG_SHIFT))&LPSPI_CFGR1_PINCFG_MASK)
6257 #define LPSPI_CFGR1_OUTCFG_MASK 0x4000000u
6258 #define LPSPI_CFGR1_OUTCFG_SHIFT 26u
6259 #define LPSPI_CFGR1_OUTCFG_WIDTH 1u
6260 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_OUTCFG_SHIFT))&LPSPI_CFGR1_OUTCFG_MASK)
6261 #define LPSPI_CFGR1_PCSCFG_MASK 0x8000000u
6262 #define LPSPI_CFGR1_PCSCFG_SHIFT 27u
6263 #define LPSPI_CFGR1_PCSCFG_WIDTH 1u
6264 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSCFG_SHIFT))&LPSPI_CFGR1_PCSCFG_MASK)
6265 /* DMR0 Bit Fields */
6266 #define LPSPI_DMR0_MATCH0_MASK 0xFFFFFFFFu
6267 #define LPSPI_DMR0_MATCH0_SHIFT 0u
6268 #define LPSPI_DMR0_MATCH0_WIDTH 32u
6269 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR0_MATCH0_SHIFT))&LPSPI_DMR0_MATCH0_MASK)
6270 /* DMR1 Bit Fields */
6271 #define LPSPI_DMR1_MATCH1_MASK 0xFFFFFFFFu
6272 #define LPSPI_DMR1_MATCH1_SHIFT 0u
6273 #define LPSPI_DMR1_MATCH1_WIDTH 32u
6274 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR1_MATCH1_SHIFT))&LPSPI_DMR1_MATCH1_MASK)
6275 /* CCR Bit Fields */
6276 #define LPSPI_CCR_SCKDIV_MASK 0xFFu
6277 #define LPSPI_CCR_SCKDIV_SHIFT 0u
6278 #define LPSPI_CCR_SCKDIV_WIDTH 8u
6279 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKDIV_SHIFT))&LPSPI_CCR_SCKDIV_MASK)
6280 #define LPSPI_CCR_DBT_MASK 0xFF00u
6281 #define LPSPI_CCR_DBT_SHIFT 8u
6282 #define LPSPI_CCR_DBT_WIDTH 8u
6283 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_DBT_SHIFT))&LPSPI_CCR_DBT_MASK)
6284 #define LPSPI_CCR_PCSSCK_MASK 0xFF0000u
6285 #define LPSPI_CCR_PCSSCK_SHIFT 16u
6286 #define LPSPI_CCR_PCSSCK_WIDTH 8u
6287 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_PCSSCK_SHIFT))&LPSPI_CCR_PCSSCK_MASK)
6288 #define LPSPI_CCR_SCKPCS_MASK 0xFF000000u
6289 #define LPSPI_CCR_SCKPCS_SHIFT 24u
6290 #define LPSPI_CCR_SCKPCS_WIDTH 8u
6291 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKPCS_SHIFT))&LPSPI_CCR_SCKPCS_MASK)
6292 /* FCR Bit Fields */
6293 #define LPSPI_FCR_TXWATER_MASK 0x3u
6294 #define LPSPI_FCR_TXWATER_SHIFT 0u
6295 #define LPSPI_FCR_TXWATER_WIDTH 2u
6296 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_TXWATER_SHIFT))&LPSPI_FCR_TXWATER_MASK)
6297 #define LPSPI_FCR_RXWATER_MASK 0x30000u
6298 #define LPSPI_FCR_RXWATER_SHIFT 16u
6299 #define LPSPI_FCR_RXWATER_WIDTH 2u
6300 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_RXWATER_SHIFT))&LPSPI_FCR_RXWATER_MASK)
6301 /* FSR Bit Fields */
6302 #define LPSPI_FSR_TXCOUNT_MASK 0x7u
6303 #define LPSPI_FSR_TXCOUNT_SHIFT 0u
6304 #define LPSPI_FSR_TXCOUNT_WIDTH 3u
6305 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_TXCOUNT_SHIFT))&LPSPI_FSR_TXCOUNT_MASK)
6306 #define LPSPI_FSR_RXCOUNT_MASK 0x70000u
6307 #define LPSPI_FSR_RXCOUNT_SHIFT 16u
6308 #define LPSPI_FSR_RXCOUNT_WIDTH 3u
6309 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_RXCOUNT_SHIFT))&LPSPI_FSR_RXCOUNT_MASK)
6310 /* TCR Bit Fields */
6311 #define LPSPI_TCR_FRAMESZ_MASK 0xFFFu
6312 #define LPSPI_TCR_FRAMESZ_SHIFT 0u
6313 #define LPSPI_TCR_FRAMESZ_WIDTH 12u
6314 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_FRAMESZ_SHIFT))&LPSPI_TCR_FRAMESZ_MASK)
6315 #define LPSPI_TCR_WIDTH_MASK 0x30000u
6316 #define LPSPI_TCR_WIDTH_SHIFT 16u
6317 #define LPSPI_TCR_WIDTH_WIDTH 2u
6318 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_WIDTH_SHIFT))&LPSPI_TCR_WIDTH_MASK)
6319 #define LPSPI_TCR_TXMSK_MASK 0x40000u
6320 #define LPSPI_TCR_TXMSK_SHIFT 18u
6321 #define LPSPI_TCR_TXMSK_WIDTH 1u
6322 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_TXMSK_SHIFT))&LPSPI_TCR_TXMSK_MASK)
6323 #define LPSPI_TCR_RXMSK_MASK 0x80000u
6324 #define LPSPI_TCR_RXMSK_SHIFT 19u
6325 #define LPSPI_TCR_RXMSK_WIDTH 1u
6326 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_RXMSK_SHIFT))&LPSPI_TCR_RXMSK_MASK)
6327 #define LPSPI_TCR_CONTC_MASK 0x100000u
6328 #define LPSPI_TCR_CONTC_SHIFT 20u
6329 #define LPSPI_TCR_CONTC_WIDTH 1u
6330 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONTC_SHIFT))&LPSPI_TCR_CONTC_MASK)
6331 #define LPSPI_TCR_CONT_MASK 0x200000u
6332 #define LPSPI_TCR_CONT_SHIFT 21u
6333 #define LPSPI_TCR_CONT_WIDTH 1u
6334 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONT_SHIFT))&LPSPI_TCR_CONT_MASK)
6335 #define LPSPI_TCR_BYSW_MASK 0x400000u
6336 #define LPSPI_TCR_BYSW_SHIFT 22u
6337 #define LPSPI_TCR_BYSW_WIDTH 1u
6338 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_BYSW_SHIFT))&LPSPI_TCR_BYSW_MASK)
6339 #define LPSPI_TCR_LSBF_MASK 0x800000u
6340 #define LPSPI_TCR_LSBF_SHIFT 23u
6341 #define LPSPI_TCR_LSBF_WIDTH 1u
6342 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_LSBF_SHIFT))&LPSPI_TCR_LSBF_MASK)
6343 #define LPSPI_TCR_PCS_MASK 0x3000000u
6344 #define LPSPI_TCR_PCS_SHIFT 24u
6345 #define LPSPI_TCR_PCS_WIDTH 2u
6346 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PCS_SHIFT))&LPSPI_TCR_PCS_MASK)
6347 #define LPSPI_TCR_PRESCALE_MASK 0x38000000u
6348 #define LPSPI_TCR_PRESCALE_SHIFT 27u
6349 #define LPSPI_TCR_PRESCALE_WIDTH 3u
6350 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PRESCALE_SHIFT))&LPSPI_TCR_PRESCALE_MASK)
6351 #define LPSPI_TCR_CPHA_MASK 0x40000000u
6352 #define LPSPI_TCR_CPHA_SHIFT 30u
6353 #define LPSPI_TCR_CPHA_WIDTH 1u
6354 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPHA_SHIFT))&LPSPI_TCR_CPHA_MASK)
6355 #define LPSPI_TCR_CPOL_MASK 0x80000000u
6356 #define LPSPI_TCR_CPOL_SHIFT 31u
6357 #define LPSPI_TCR_CPOL_WIDTH 1u
6358 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPOL_SHIFT))&LPSPI_TCR_CPOL_MASK)
6359 /* TDR Bit Fields */
6360 #define LPSPI_TDR_DATA_MASK 0xFFFFFFFFu
6361 #define LPSPI_TDR_DATA_SHIFT 0u
6362 #define LPSPI_TDR_DATA_WIDTH 32u
6363 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TDR_DATA_SHIFT))&LPSPI_TDR_DATA_MASK)
6364 /* RSR Bit Fields */
6365 #define LPSPI_RSR_SOF_MASK 0x1u
6366 #define LPSPI_RSR_SOF_SHIFT 0u
6367 #define LPSPI_RSR_SOF_WIDTH 1u
6368 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_SOF_SHIFT))&LPSPI_RSR_SOF_MASK)
6369 #define LPSPI_RSR_RXEMPTY_MASK 0x2u
6370 #define LPSPI_RSR_RXEMPTY_SHIFT 1u
6371 #define LPSPI_RSR_RXEMPTY_WIDTH 1u
6372 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_RXEMPTY_SHIFT))&LPSPI_RSR_RXEMPTY_MASK)
6373 /* RDR Bit Fields */
6374 #define LPSPI_RDR_DATA_MASK 0xFFFFFFFFu
6375 #define LPSPI_RDR_DATA_SHIFT 0u
6376 #define LPSPI_RDR_DATA_WIDTH 32u
6377 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RDR_DATA_SHIFT))&LPSPI_RDR_DATA_MASK)
6378  /* end of group LPSPI_Register_Masks */
6382 
6383  /* end of group LPSPI_Peripheral_Access_Layer */
6387 
6388 
6389 /* ----------------------------------------------------------------------------
6390  -- LPTMR Peripheral Access Layer
6391  ---------------------------------------------------------------------------- */
6392 
6402 typedef struct {
6403  __IO uint32_t CSR;
6404  __IO uint32_t PSR;
6405  __IO uint32_t CMR;
6406  __IO uint32_t CNR;
6408 
6410 #define LPTMR_INSTANCE_COUNT (1u)
6411 
6412 
6413 /* LPTMR - Peripheral instance base addresses */
6415 #define LPTMR0_BASE (0x40040000u)
6416 
6417 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
6418 
6419 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
6420 
6421 #define LPTMR_BASE_PTRS { LPTMR0 }
6422 
6423 #define LPTMR_IRQS_ARR_COUNT (1u)
6424 
6425 #define LPTMR_IRQS_CH_COUNT (1u)
6426 
6427 #define LPTMR_IRQS { LPTMR0_IRQn }
6428 
6429 /* ----------------------------------------------------------------------------
6430  -- LPTMR Register Masks
6431  ---------------------------------------------------------------------------- */
6432 
6438 /* CSR Bit Fields */
6439 #define LPTMR_CSR_TEN_MASK 0x1u
6440 #define LPTMR_CSR_TEN_SHIFT 0u
6441 #define LPTMR_CSR_TEN_WIDTH 1u
6442 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
6443 #define LPTMR_CSR_TMS_MASK 0x2u
6444 #define LPTMR_CSR_TMS_SHIFT 1u
6445 #define LPTMR_CSR_TMS_WIDTH 1u
6446 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
6447 #define LPTMR_CSR_TFC_MASK 0x4u
6448 #define LPTMR_CSR_TFC_SHIFT 2u
6449 #define LPTMR_CSR_TFC_WIDTH 1u
6450 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
6451 #define LPTMR_CSR_TPP_MASK 0x8u
6452 #define LPTMR_CSR_TPP_SHIFT 3u
6453 #define LPTMR_CSR_TPP_WIDTH 1u
6454 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
6455 #define LPTMR_CSR_TPS_MASK 0x30u
6456 #define LPTMR_CSR_TPS_SHIFT 4u
6457 #define LPTMR_CSR_TPS_WIDTH 2u
6458 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
6459 #define LPTMR_CSR_TIE_MASK 0x40u
6460 #define LPTMR_CSR_TIE_SHIFT 6u
6461 #define LPTMR_CSR_TIE_WIDTH 1u
6462 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
6463 #define LPTMR_CSR_TCF_MASK 0x80u
6464 #define LPTMR_CSR_TCF_SHIFT 7u
6465 #define LPTMR_CSR_TCF_WIDTH 1u
6466 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
6467 #define LPTMR_CSR_TDRE_MASK 0x100u
6468 #define LPTMR_CSR_TDRE_SHIFT 8u
6469 #define LPTMR_CSR_TDRE_WIDTH 1u
6470 #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TDRE_SHIFT))&LPTMR_CSR_TDRE_MASK)
6471 /* PSR Bit Fields */
6472 #define LPTMR_PSR_PCS_MASK 0x3u
6473 #define LPTMR_PSR_PCS_SHIFT 0u
6474 #define LPTMR_PSR_PCS_WIDTH 2u
6475 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
6476 #define LPTMR_PSR_PBYP_MASK 0x4u
6477 #define LPTMR_PSR_PBYP_SHIFT 2u
6478 #define LPTMR_PSR_PBYP_WIDTH 1u
6479 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
6480 #define LPTMR_PSR_PRESCALE_MASK 0x78u
6481 #define LPTMR_PSR_PRESCALE_SHIFT 3u
6482 #define LPTMR_PSR_PRESCALE_WIDTH 4u
6483 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
6484 /* CMR Bit Fields */
6485 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
6486 #define LPTMR_CMR_COMPARE_SHIFT 0u
6487 #define LPTMR_CMR_COMPARE_WIDTH 16u
6488 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
6489 /* CNR Bit Fields */
6490 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
6491 #define LPTMR_CNR_COUNTER_SHIFT 0u
6492 #define LPTMR_CNR_COUNTER_WIDTH 16u
6493 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
6494  /* end of group LPTMR_Register_Masks */
6498 
6499  /* end of group LPTMR_Peripheral_Access_Layer */
6503 
6504 
6505 /* ----------------------------------------------------------------------------
6506  -- LPUART Peripheral Access Layer
6507  ---------------------------------------------------------------------------- */
6508 
6518 typedef struct {
6519  __I uint32_t VERID;
6520  __I uint32_t PARAM;
6521  __IO uint32_t GLOBAL;
6522  __IO uint32_t PINCFG;
6523  __IO uint32_t BAUD;
6524  __IO uint32_t STAT;
6525  __IO uint32_t CTRL;
6526  __IO uint32_t DATA;
6527  __IO uint32_t MATCH;
6528  __IO uint32_t MODIR;
6529  __IO uint32_t FIFO;
6530  __IO uint32_t WATER;
6532 
6534 #define LPUART_INSTANCE_COUNT (2u)
6535 
6536 
6537 /* LPUART - Peripheral instance base addresses */
6539 #define LPUART0_BASE (0x4006A000u)
6540 
6541 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
6542 
6543 #define LPUART1_BASE (0x4006B000u)
6544 
6545 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
6546 
6547 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
6548 
6549 #define LPUART_BASE_PTRS { LPUART0, LPUART1 }
6550 
6551 #define LPUART_IRQS_ARR_COUNT (1u)
6552 
6553 #define LPUART_RX_TX_IRQS_CH_COUNT (1u)
6554 
6555 #define LPUART_RX_TX_IRQS { LPUART0_RxTx_IRQn, LPUART1_RxTx_IRQn }
6556 
6557 /* ----------------------------------------------------------------------------
6558  -- LPUART Register Masks
6559  ---------------------------------------------------------------------------- */
6560 
6566 /* VERID Bit Fields */
6567 #define LPUART_VERID_FEATURE_MASK 0xFFFFu
6568 #define LPUART_VERID_FEATURE_SHIFT 0u
6569 #define LPUART_VERID_FEATURE_WIDTH 16u
6570 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_FEATURE_SHIFT))&LPUART_VERID_FEATURE_MASK)
6571 #define LPUART_VERID_MINOR_MASK 0xFF0000u
6572 #define LPUART_VERID_MINOR_SHIFT 16u
6573 #define LPUART_VERID_MINOR_WIDTH 8u
6574 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MINOR_SHIFT))&LPUART_VERID_MINOR_MASK)
6575 #define LPUART_VERID_MAJOR_MASK 0xFF000000u
6576 #define LPUART_VERID_MAJOR_SHIFT 24u
6577 #define LPUART_VERID_MAJOR_WIDTH 8u
6578 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MAJOR_SHIFT))&LPUART_VERID_MAJOR_MASK)
6579 /* PARAM Bit Fields */
6580 #define LPUART_PARAM_TXFIFO_MASK 0xFFu
6581 #define LPUART_PARAM_TXFIFO_SHIFT 0u
6582 #define LPUART_PARAM_TXFIFO_WIDTH 8u
6583 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_TXFIFO_SHIFT))&LPUART_PARAM_TXFIFO_MASK)
6584 #define LPUART_PARAM_RXFIFO_MASK 0xFF00u
6585 #define LPUART_PARAM_RXFIFO_SHIFT 8u
6586 #define LPUART_PARAM_RXFIFO_WIDTH 8u
6587 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_RXFIFO_SHIFT))&LPUART_PARAM_RXFIFO_MASK)
6588 /* GLOBAL Bit Fields */
6589 #define LPUART_GLOBAL_RST_MASK 0x2u
6590 #define LPUART_GLOBAL_RST_SHIFT 1u
6591 #define LPUART_GLOBAL_RST_WIDTH 1u
6592 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x))<<LPUART_GLOBAL_RST_SHIFT))&LPUART_GLOBAL_RST_MASK)
6593 /* PINCFG Bit Fields */
6594 #define LPUART_PINCFG_TRGSEL_MASK 0x3u
6595 #define LPUART_PINCFG_TRGSEL_SHIFT 0u
6596 #define LPUART_PINCFG_TRGSEL_WIDTH 2u
6597 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PINCFG_TRGSEL_SHIFT))&LPUART_PINCFG_TRGSEL_MASK)
6598 /* BAUD Bit Fields */
6599 #define LPUART_BAUD_SBR_MASK 0x1FFFu
6600 #define LPUART_BAUD_SBR_SHIFT 0u
6601 #define LPUART_BAUD_SBR_WIDTH 13u
6602 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
6603 #define LPUART_BAUD_SBNS_MASK 0x2000u
6604 #define LPUART_BAUD_SBNS_SHIFT 13u
6605 #define LPUART_BAUD_SBNS_WIDTH 1u
6606 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
6607 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
6608 #define LPUART_BAUD_RXEDGIE_SHIFT 14u
6609 #define LPUART_BAUD_RXEDGIE_WIDTH 1u
6610 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
6611 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
6612 #define LPUART_BAUD_LBKDIE_SHIFT 15u
6613 #define LPUART_BAUD_LBKDIE_WIDTH 1u
6614 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
6615 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
6616 #define LPUART_BAUD_RESYNCDIS_SHIFT 16u
6617 #define LPUART_BAUD_RESYNCDIS_WIDTH 1u
6618 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
6619 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
6620 #define LPUART_BAUD_BOTHEDGE_SHIFT 17u
6621 #define LPUART_BAUD_BOTHEDGE_WIDTH 1u
6622 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
6623 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
6624 #define LPUART_BAUD_MATCFG_SHIFT 18u
6625 #define LPUART_BAUD_MATCFG_WIDTH 2u
6626 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
6627 #define LPUART_BAUD_RIDMAE_MASK 0x100000u
6628 #define LPUART_BAUD_RIDMAE_SHIFT 20u
6629 #define LPUART_BAUD_RIDMAE_WIDTH 1u
6630 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RIDMAE_SHIFT))&LPUART_BAUD_RIDMAE_MASK)
6631 #define LPUART_BAUD_RDMAE_MASK 0x200000u
6632 #define LPUART_BAUD_RDMAE_SHIFT 21u
6633 #define LPUART_BAUD_RDMAE_WIDTH 1u
6634 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
6635 #define LPUART_BAUD_TDMAE_MASK 0x800000u
6636 #define LPUART_BAUD_TDMAE_SHIFT 23u
6637 #define LPUART_BAUD_TDMAE_WIDTH 1u
6638 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
6639 #define LPUART_BAUD_OSR_MASK 0x1F000000u
6640 #define LPUART_BAUD_OSR_SHIFT 24u
6641 #define LPUART_BAUD_OSR_WIDTH 5u
6642 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
6643 #define LPUART_BAUD_M10_MASK 0x20000000u
6644 #define LPUART_BAUD_M10_SHIFT 29u
6645 #define LPUART_BAUD_M10_WIDTH 1u
6646 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
6647 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
6648 #define LPUART_BAUD_MAEN2_SHIFT 30u
6649 #define LPUART_BAUD_MAEN2_WIDTH 1u
6650 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
6651 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
6652 #define LPUART_BAUD_MAEN1_SHIFT 31u
6653 #define LPUART_BAUD_MAEN1_WIDTH 1u
6654 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
6655 /* STAT Bit Fields */
6656 #define LPUART_STAT_MA2F_MASK 0x4000u
6657 #define LPUART_STAT_MA2F_SHIFT 14u
6658 #define LPUART_STAT_MA2F_WIDTH 1u
6659 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
6660 #define LPUART_STAT_MA1F_MASK 0x8000u
6661 #define LPUART_STAT_MA1F_SHIFT 15u
6662 #define LPUART_STAT_MA1F_WIDTH 1u
6663 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
6664 #define LPUART_STAT_PF_MASK 0x10000u
6665 #define LPUART_STAT_PF_SHIFT 16u
6666 #define LPUART_STAT_PF_WIDTH 1u
6667 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
6668 #define LPUART_STAT_FE_MASK 0x20000u
6669 #define LPUART_STAT_FE_SHIFT 17u
6670 #define LPUART_STAT_FE_WIDTH 1u
6671 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
6672 #define LPUART_STAT_NF_MASK 0x40000u
6673 #define LPUART_STAT_NF_SHIFT 18u
6674 #define LPUART_STAT_NF_WIDTH 1u
6675 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
6676 #define LPUART_STAT_OR_MASK 0x80000u
6677 #define LPUART_STAT_OR_SHIFT 19u
6678 #define LPUART_STAT_OR_WIDTH 1u
6679 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
6680 #define LPUART_STAT_IDLE_MASK 0x100000u
6681 #define LPUART_STAT_IDLE_SHIFT 20u
6682 #define LPUART_STAT_IDLE_WIDTH 1u
6683 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
6684 #define LPUART_STAT_RDRF_MASK 0x200000u
6685 #define LPUART_STAT_RDRF_SHIFT 21u
6686 #define LPUART_STAT_RDRF_WIDTH 1u
6687 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
6688 #define LPUART_STAT_TC_MASK 0x400000u
6689 #define LPUART_STAT_TC_SHIFT 22u
6690 #define LPUART_STAT_TC_WIDTH 1u
6691 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
6692 #define LPUART_STAT_TDRE_MASK 0x800000u
6693 #define LPUART_STAT_TDRE_SHIFT 23u
6694 #define LPUART_STAT_TDRE_WIDTH 1u
6695 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
6696 #define LPUART_STAT_RAF_MASK 0x1000000u
6697 #define LPUART_STAT_RAF_SHIFT 24u
6698 #define LPUART_STAT_RAF_WIDTH 1u
6699 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
6700 #define LPUART_STAT_LBKDE_MASK 0x2000000u
6701 #define LPUART_STAT_LBKDE_SHIFT 25u
6702 #define LPUART_STAT_LBKDE_WIDTH 1u
6703 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
6704 #define LPUART_STAT_BRK13_MASK 0x4000000u
6705 #define LPUART_STAT_BRK13_SHIFT 26u
6706 #define LPUART_STAT_BRK13_WIDTH 1u
6707 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
6708 #define LPUART_STAT_RWUID_MASK 0x8000000u
6709 #define LPUART_STAT_RWUID_SHIFT 27u
6710 #define LPUART_STAT_RWUID_WIDTH 1u
6711 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
6712 #define LPUART_STAT_RXINV_MASK 0x10000000u
6713 #define LPUART_STAT_RXINV_SHIFT 28u
6714 #define LPUART_STAT_RXINV_WIDTH 1u
6715 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
6716 #define LPUART_STAT_MSBF_MASK 0x20000000u
6717 #define LPUART_STAT_MSBF_SHIFT 29u
6718 #define LPUART_STAT_MSBF_WIDTH 1u
6719 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
6720 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
6721 #define LPUART_STAT_RXEDGIF_SHIFT 30u
6722 #define LPUART_STAT_RXEDGIF_WIDTH 1u
6723 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
6724 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
6725 #define LPUART_STAT_LBKDIF_SHIFT 31u
6726 #define LPUART_STAT_LBKDIF_WIDTH 1u
6727 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
6728 /* CTRL Bit Fields */
6729 #define LPUART_CTRL_PT_MASK 0x1u
6730 #define LPUART_CTRL_PT_SHIFT 0u
6731 #define LPUART_CTRL_PT_WIDTH 1u
6732 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
6733 #define LPUART_CTRL_PE_MASK 0x2u
6734 #define LPUART_CTRL_PE_SHIFT 1u
6735 #define LPUART_CTRL_PE_WIDTH 1u
6736 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
6737 #define LPUART_CTRL_ILT_MASK 0x4u
6738 #define LPUART_CTRL_ILT_SHIFT 2u
6739 #define LPUART_CTRL_ILT_WIDTH 1u
6740 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
6741 #define LPUART_CTRL_WAKE_MASK 0x8u
6742 #define LPUART_CTRL_WAKE_SHIFT 3u
6743 #define LPUART_CTRL_WAKE_WIDTH 1u
6744 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
6745 #define LPUART_CTRL_M_MASK 0x10u
6746 #define LPUART_CTRL_M_SHIFT 4u
6747 #define LPUART_CTRL_M_WIDTH 1u
6748 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
6749 #define LPUART_CTRL_RSRC_MASK 0x20u
6750 #define LPUART_CTRL_RSRC_SHIFT 5u
6751 #define LPUART_CTRL_RSRC_WIDTH 1u
6752 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
6753 #define LPUART_CTRL_DOZEEN_MASK 0x40u
6754 #define LPUART_CTRL_DOZEEN_SHIFT 6u
6755 #define LPUART_CTRL_DOZEEN_WIDTH 1u
6756 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
6757 #define LPUART_CTRL_LOOPS_MASK 0x80u
6758 #define LPUART_CTRL_LOOPS_SHIFT 7u
6759 #define LPUART_CTRL_LOOPS_WIDTH 1u
6760 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
6761 #define LPUART_CTRL_IDLECFG_MASK 0x700u
6762 #define LPUART_CTRL_IDLECFG_SHIFT 8u
6763 #define LPUART_CTRL_IDLECFG_WIDTH 3u
6764 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
6765 #define LPUART_CTRL_M7_MASK 0x800u
6766 #define LPUART_CTRL_M7_SHIFT 11u
6767 #define LPUART_CTRL_M7_WIDTH 1u
6768 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M7_SHIFT))&LPUART_CTRL_M7_MASK)
6769 #define LPUART_CTRL_MA2IE_MASK 0x4000u
6770 #define LPUART_CTRL_MA2IE_SHIFT 14u
6771 #define LPUART_CTRL_MA2IE_WIDTH 1u
6772 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
6773 #define LPUART_CTRL_MA1IE_MASK 0x8000u
6774 #define LPUART_CTRL_MA1IE_SHIFT 15u
6775 #define LPUART_CTRL_MA1IE_WIDTH 1u
6776 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
6777 #define LPUART_CTRL_SBK_MASK 0x10000u
6778 #define LPUART_CTRL_SBK_SHIFT 16u
6779 #define LPUART_CTRL_SBK_WIDTH 1u
6780 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
6781 #define LPUART_CTRL_RWU_MASK 0x20000u
6782 #define LPUART_CTRL_RWU_SHIFT 17u
6783 #define LPUART_CTRL_RWU_WIDTH 1u
6784 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
6785 #define LPUART_CTRL_RE_MASK 0x40000u
6786 #define LPUART_CTRL_RE_SHIFT 18u
6787 #define LPUART_CTRL_RE_WIDTH 1u
6788 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
6789 #define LPUART_CTRL_TE_MASK 0x80000u
6790 #define LPUART_CTRL_TE_SHIFT 19u
6791 #define LPUART_CTRL_TE_WIDTH 1u
6792 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
6793 #define LPUART_CTRL_ILIE_MASK 0x100000u
6794 #define LPUART_CTRL_ILIE_SHIFT 20u
6795 #define LPUART_CTRL_ILIE_WIDTH 1u
6796 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
6797 #define LPUART_CTRL_RIE_MASK 0x200000u
6798 #define LPUART_CTRL_RIE_SHIFT 21u
6799 #define LPUART_CTRL_RIE_WIDTH 1u
6800 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
6801 #define LPUART_CTRL_TCIE_MASK 0x400000u
6802 #define LPUART_CTRL_TCIE_SHIFT 22u
6803 #define LPUART_CTRL_TCIE_WIDTH 1u
6804 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
6805 #define LPUART_CTRL_TIE_MASK 0x800000u
6806 #define LPUART_CTRL_TIE_SHIFT 23u
6807 #define LPUART_CTRL_TIE_WIDTH 1u
6808 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
6809 #define LPUART_CTRL_PEIE_MASK 0x1000000u
6810 #define LPUART_CTRL_PEIE_SHIFT 24u
6811 #define LPUART_CTRL_PEIE_WIDTH 1u
6812 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
6813 #define LPUART_CTRL_FEIE_MASK 0x2000000u
6814 #define LPUART_CTRL_FEIE_SHIFT 25u
6815 #define LPUART_CTRL_FEIE_WIDTH 1u
6816 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
6817 #define LPUART_CTRL_NEIE_MASK 0x4000000u
6818 #define LPUART_CTRL_NEIE_SHIFT 26u
6819 #define LPUART_CTRL_NEIE_WIDTH 1u
6820 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
6821 #define LPUART_CTRL_ORIE_MASK 0x8000000u
6822 #define LPUART_CTRL_ORIE_SHIFT 27u
6823 #define LPUART_CTRL_ORIE_WIDTH 1u
6824 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
6825 #define LPUART_CTRL_TXINV_MASK 0x10000000u
6826 #define LPUART_CTRL_TXINV_SHIFT 28u
6827 #define LPUART_CTRL_TXINV_WIDTH 1u
6828 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
6829 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
6830 #define LPUART_CTRL_TXDIR_SHIFT 29u
6831 #define LPUART_CTRL_TXDIR_WIDTH 1u
6832 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
6833 #define LPUART_CTRL_R9T8_MASK 0x40000000u
6834 #define LPUART_CTRL_R9T8_SHIFT 30u
6835 #define LPUART_CTRL_R9T8_WIDTH 1u
6836 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
6837 #define LPUART_CTRL_R8T9_MASK 0x80000000u
6838 #define LPUART_CTRL_R8T9_SHIFT 31u
6839 #define LPUART_CTRL_R8T9_WIDTH 1u
6840 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
6841 /* DATA Bit Fields */
6842 #define LPUART_DATA_R0T0_MASK 0x1u
6843 #define LPUART_DATA_R0T0_SHIFT 0u
6844 #define LPUART_DATA_R0T0_WIDTH 1u
6845 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
6846 #define LPUART_DATA_R1T1_MASK 0x2u
6847 #define LPUART_DATA_R1T1_SHIFT 1u
6848 #define LPUART_DATA_R1T1_WIDTH 1u
6849 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
6850 #define LPUART_DATA_R2T2_MASK 0x4u
6851 #define LPUART_DATA_R2T2_SHIFT 2u
6852 #define LPUART_DATA_R2T2_WIDTH 1u
6853 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
6854 #define LPUART_DATA_R3T3_MASK 0x8u
6855 #define LPUART_DATA_R3T3_SHIFT 3u
6856 #define LPUART_DATA_R3T3_WIDTH 1u
6857 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
6858 #define LPUART_DATA_R4T4_MASK 0x10u
6859 #define LPUART_DATA_R4T4_SHIFT 4u
6860 #define LPUART_DATA_R4T4_WIDTH 1u
6861 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
6862 #define LPUART_DATA_R5T5_MASK 0x20u
6863 #define LPUART_DATA_R5T5_SHIFT 5u
6864 #define LPUART_DATA_R5T5_WIDTH 1u
6865 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
6866 #define LPUART_DATA_R6T6_MASK 0x40u
6867 #define LPUART_DATA_R6T6_SHIFT 6u
6868 #define LPUART_DATA_R6T6_WIDTH 1u
6869 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
6870 #define LPUART_DATA_R7T7_MASK 0x80u
6871 #define LPUART_DATA_R7T7_SHIFT 7u
6872 #define LPUART_DATA_R7T7_WIDTH 1u
6873 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
6874 #define LPUART_DATA_R8T8_MASK 0x100u
6875 #define LPUART_DATA_R8T8_SHIFT 8u
6876 #define LPUART_DATA_R8T8_WIDTH 1u
6877 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
6878 #define LPUART_DATA_R9T9_MASK 0x200u
6879 #define LPUART_DATA_R9T9_SHIFT 9u
6880 #define LPUART_DATA_R9T9_WIDTH 1u
6881 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
6882 #define LPUART_DATA_IDLINE_MASK 0x800u
6883 #define LPUART_DATA_IDLINE_SHIFT 11u
6884 #define LPUART_DATA_IDLINE_WIDTH 1u
6885 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
6886 #define LPUART_DATA_RXEMPT_MASK 0x1000u
6887 #define LPUART_DATA_RXEMPT_SHIFT 12u
6888 #define LPUART_DATA_RXEMPT_WIDTH 1u
6889 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
6890 #define LPUART_DATA_FRETSC_MASK 0x2000u
6891 #define LPUART_DATA_FRETSC_SHIFT 13u
6892 #define LPUART_DATA_FRETSC_WIDTH 1u
6893 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
6894 #define LPUART_DATA_PARITYE_MASK 0x4000u
6895 #define LPUART_DATA_PARITYE_SHIFT 14u
6896 #define LPUART_DATA_PARITYE_WIDTH 1u
6897 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
6898 #define LPUART_DATA_NOISY_MASK 0x8000u
6899 #define LPUART_DATA_NOISY_SHIFT 15u
6900 #define LPUART_DATA_NOISY_WIDTH 1u
6901 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
6902 /* MATCH Bit Fields */
6903 #define LPUART_MATCH_MA1_MASK 0x3FFu
6904 #define LPUART_MATCH_MA1_SHIFT 0u
6905 #define LPUART_MATCH_MA1_WIDTH 10u
6906 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
6907 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
6908 #define LPUART_MATCH_MA2_SHIFT 16u
6909 #define LPUART_MATCH_MA2_WIDTH 10u
6910 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
6911 /* MODIR Bit Fields */
6912 #define LPUART_MODIR_TXCTSE_MASK 0x1u
6913 #define LPUART_MODIR_TXCTSE_SHIFT 0u
6914 #define LPUART_MODIR_TXCTSE_WIDTH 1u
6915 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
6916 #define LPUART_MODIR_TXRTSE_MASK 0x2u
6917 #define LPUART_MODIR_TXRTSE_SHIFT 1u
6918 #define LPUART_MODIR_TXRTSE_WIDTH 1u
6919 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
6920 #define LPUART_MODIR_TXRTSPOL_MASK 0x4u
6921 #define LPUART_MODIR_TXRTSPOL_SHIFT 2u
6922 #define LPUART_MODIR_TXRTSPOL_WIDTH 1u
6923 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
6924 #define LPUART_MODIR_RXRTSE_MASK 0x8u
6925 #define LPUART_MODIR_RXRTSE_SHIFT 3u
6926 #define LPUART_MODIR_RXRTSE_WIDTH 1u
6927 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
6928 #define LPUART_MODIR_TXCTSC_MASK 0x10u
6929 #define LPUART_MODIR_TXCTSC_SHIFT 4u
6930 #define LPUART_MODIR_TXCTSC_WIDTH 1u
6931 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
6932 #define LPUART_MODIR_TXCTSSRC_MASK 0x20u
6933 #define LPUART_MODIR_TXCTSSRC_SHIFT 5u
6934 #define LPUART_MODIR_TXCTSSRC_WIDTH 1u
6935 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
6936 #define LPUART_MODIR_RTSWATER_MASK 0x300u
6937 #define LPUART_MODIR_RTSWATER_SHIFT 8u
6938 #define LPUART_MODIR_RTSWATER_WIDTH 2u
6939 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RTSWATER_SHIFT))&LPUART_MODIR_RTSWATER_MASK)
6940 #define LPUART_MODIR_TNP_MASK 0x30000u
6941 #define LPUART_MODIR_TNP_SHIFT 16u
6942 #define LPUART_MODIR_TNP_WIDTH 2u
6943 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
6944 #define LPUART_MODIR_IREN_MASK 0x40000u
6945 #define LPUART_MODIR_IREN_SHIFT 18u
6946 #define LPUART_MODIR_IREN_WIDTH 1u
6947 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
6948 /* FIFO Bit Fields */
6949 #define LPUART_FIFO_RXFIFOSIZE_MASK 0x7u
6950 #define LPUART_FIFO_RXFIFOSIZE_SHIFT 0u
6951 #define LPUART_FIFO_RXFIFOSIZE_WIDTH 3u
6952 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFIFOSIZE_SHIFT))&LPUART_FIFO_RXFIFOSIZE_MASK)
6953 #define LPUART_FIFO_RXFE_MASK 0x8u
6954 #define LPUART_FIFO_RXFE_SHIFT 3u
6955 #define LPUART_FIFO_RXFE_WIDTH 1u
6956 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFE_SHIFT))&LPUART_FIFO_RXFE_MASK)
6957 #define LPUART_FIFO_TXFIFOSIZE_MASK 0x70u
6958 #define LPUART_FIFO_TXFIFOSIZE_SHIFT 4u
6959 #define LPUART_FIFO_TXFIFOSIZE_WIDTH 3u
6960 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFIFOSIZE_SHIFT))&LPUART_FIFO_TXFIFOSIZE_MASK)
6961 #define LPUART_FIFO_TXFE_MASK 0x80u
6962 #define LPUART_FIFO_TXFE_SHIFT 7u
6963 #define LPUART_FIFO_TXFE_WIDTH 1u
6964 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFE_SHIFT))&LPUART_FIFO_TXFE_MASK)
6965 #define LPUART_FIFO_RXUFE_MASK 0x100u
6966 #define LPUART_FIFO_RXUFE_SHIFT 8u
6967 #define LPUART_FIFO_RXUFE_WIDTH 1u
6968 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUFE_SHIFT))&LPUART_FIFO_RXUFE_MASK)
6969 #define LPUART_FIFO_TXOFE_MASK 0x200u
6970 #define LPUART_FIFO_TXOFE_SHIFT 9u
6971 #define LPUART_FIFO_TXOFE_WIDTH 1u
6972 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOFE_SHIFT))&LPUART_FIFO_TXOFE_MASK)
6973 #define LPUART_FIFO_RXIDEN_MASK 0x1C00u
6974 #define LPUART_FIFO_RXIDEN_SHIFT 10u
6975 #define LPUART_FIFO_RXIDEN_WIDTH 3u
6976 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXIDEN_SHIFT))&LPUART_FIFO_RXIDEN_MASK)
6977 #define LPUART_FIFO_RXFLUSH_MASK 0x4000u
6978 #define LPUART_FIFO_RXFLUSH_SHIFT 14u
6979 #define LPUART_FIFO_RXFLUSH_WIDTH 1u
6980 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFLUSH_SHIFT))&LPUART_FIFO_RXFLUSH_MASK)
6981 #define LPUART_FIFO_TXFLUSH_MASK 0x8000u
6982 #define LPUART_FIFO_TXFLUSH_SHIFT 15u
6983 #define LPUART_FIFO_TXFLUSH_WIDTH 1u
6984 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFLUSH_SHIFT))&LPUART_FIFO_TXFLUSH_MASK)
6985 #define LPUART_FIFO_RXUF_MASK 0x10000u
6986 #define LPUART_FIFO_RXUF_SHIFT 16u
6987 #define LPUART_FIFO_RXUF_WIDTH 1u
6988 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUF_SHIFT))&LPUART_FIFO_RXUF_MASK)
6989 #define LPUART_FIFO_TXOF_MASK 0x20000u
6990 #define LPUART_FIFO_TXOF_SHIFT 17u
6991 #define LPUART_FIFO_TXOF_WIDTH 1u
6992 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOF_SHIFT))&LPUART_FIFO_TXOF_MASK)
6993 #define LPUART_FIFO_RXEMPT_MASK 0x400000u
6994 #define LPUART_FIFO_RXEMPT_SHIFT 22u
6995 #define LPUART_FIFO_RXEMPT_WIDTH 1u
6996 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXEMPT_SHIFT))&LPUART_FIFO_RXEMPT_MASK)
6997 #define LPUART_FIFO_TXEMPT_MASK 0x800000u
6998 #define LPUART_FIFO_TXEMPT_SHIFT 23u
6999 #define LPUART_FIFO_TXEMPT_WIDTH 1u
7000 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXEMPT_SHIFT))&LPUART_FIFO_TXEMPT_MASK)
7001 /* WATER Bit Fields */
7002 #define LPUART_WATER_TXWATER_MASK 0x3u
7003 #define LPUART_WATER_TXWATER_SHIFT 0u
7004 #define LPUART_WATER_TXWATER_WIDTH 2u
7005 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXWATER_SHIFT))&LPUART_WATER_TXWATER_MASK)
7006 #define LPUART_WATER_TXCOUNT_MASK 0x700u
7007 #define LPUART_WATER_TXCOUNT_SHIFT 8u
7008 #define LPUART_WATER_TXCOUNT_WIDTH 3u
7009 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXCOUNT_SHIFT))&LPUART_WATER_TXCOUNT_MASK)
7010 #define LPUART_WATER_RXWATER_MASK 0x30000u
7011 #define LPUART_WATER_RXWATER_SHIFT 16u
7012 #define LPUART_WATER_RXWATER_WIDTH 2u
7013 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXWATER_SHIFT))&LPUART_WATER_RXWATER_MASK)
7014 #define LPUART_WATER_RXCOUNT_MASK 0x7000000u
7015 #define LPUART_WATER_RXCOUNT_SHIFT 24u
7016 #define LPUART_WATER_RXCOUNT_WIDTH 3u
7017 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXCOUNT_SHIFT))&LPUART_WATER_RXCOUNT_MASK)
7018  /* end of group LPUART_Register_Masks */
7022 
7023  /* end of group LPUART_Peripheral_Access_Layer */
7027 
7028 
7029 /* ----------------------------------------------------------------------------
7030  -- MCM Peripheral Access Layer
7031  ---------------------------------------------------------------------------- */
7032 
7040 #define MCM_LMDR_COUNT 2u
7041 
7043 typedef struct {
7044  uint8_t RESERVED_0[8];
7045  __I uint16_t PLASC;
7046  __I uint16_t PLAMC;
7047  __IO uint32_t CPCR;
7048  uint8_t RESERVED_1[32];
7049  __IO uint32_t PID;
7050  uint8_t RESERVED_2[12];
7051  __IO uint32_t CPO;
7052  uint8_t RESERVED_3[956];
7053  __IO uint32_t LMDR[MCM_LMDR_COUNT];
7054  __IO uint32_t LMDR2;
7055  uint8_t RESERVED_4[116];
7056  __IO uint32_t LMPECR;
7057  uint8_t RESERVED_5[4];
7058  __IO uint32_t LMPEIR;
7059  uint8_t RESERVED_6[4];
7060  __I uint32_t LMFAR;
7061  __I uint32_t LMFATR;
7062  uint8_t RESERVED_7[8];
7063  __I uint32_t LMFDHR;
7064  __I uint32_t LMFDLR;
7066 
7068 #define MCM_INSTANCE_COUNT (1u)
7069 
7070 
7071 /* MCM - Peripheral instance base addresses */
7073 #define MCM_BASE (0xF0003000u)
7074 
7075 #define MCM ((MCM_Type *)MCM_BASE)
7076 
7077 #define MCM_BASE_ADDRS { MCM_BASE }
7078 
7079 #define MCM_BASE_PTRS { MCM }
7080 
7081 /* ----------------------------------------------------------------------------
7082  -- MCM Register Masks
7083  ---------------------------------------------------------------------------- */
7084 
7090 /* PLASC Bit Fields */
7091 #define MCM_PLASC_ASC_MASK 0xFFu
7092 #define MCM_PLASC_ASC_SHIFT 0u
7093 #define MCM_PLASC_ASC_WIDTH 8u
7094 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
7095 /* PLAMC Bit Fields */
7096 #define MCM_PLAMC_AMC_MASK 0xFFu
7097 #define MCM_PLAMC_AMC_SHIFT 0u
7098 #define MCM_PLAMC_AMC_WIDTH 8u
7099 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
7100 /* CPCR Bit Fields */
7101 #define MCM_CPCR_HLT_FSM_ST_MASK 0x3u
7102 #define MCM_CPCR_HLT_FSM_ST_SHIFT 0u
7103 #define MCM_CPCR_HLT_FSM_ST_WIDTH 2u
7104 #define MCM_CPCR_HLT_FSM_ST(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_HLT_FSM_ST_SHIFT))&MCM_CPCR_HLT_FSM_ST_MASK)
7105 #define MCM_CPCR_AXBS_HLT_REQ_MASK 0x4u
7106 #define MCM_CPCR_AXBS_HLT_REQ_SHIFT 2u
7107 #define MCM_CPCR_AXBS_HLT_REQ_WIDTH 1u
7108 #define MCM_CPCR_AXBS_HLT_REQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLT_REQ_SHIFT))&MCM_CPCR_AXBS_HLT_REQ_MASK)
7109 #define MCM_CPCR_AXBS_HLTD_MASK 0x8u
7110 #define MCM_CPCR_AXBS_HLTD_SHIFT 3u
7111 #define MCM_CPCR_AXBS_HLTD_WIDTH 1u
7112 #define MCM_CPCR_AXBS_HLTD(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLTD_SHIFT))&MCM_CPCR_AXBS_HLTD_MASK)
7113 #define MCM_CPCR_FMC_PF_IDLE_MASK 0x10u
7114 #define MCM_CPCR_FMC_PF_IDLE_SHIFT 4u
7115 #define MCM_CPCR_FMC_PF_IDLE_WIDTH 1u
7116 #define MCM_CPCR_FMC_PF_IDLE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_FMC_PF_IDLE_SHIFT))&MCM_CPCR_FMC_PF_IDLE_MASK)
7117 #define MCM_CPCR_PBRIDGE_IDLE_MASK 0x40u
7118 #define MCM_CPCR_PBRIDGE_IDLE_SHIFT 6u
7119 #define MCM_CPCR_PBRIDGE_IDLE_WIDTH 1u
7120 #define MCM_CPCR_PBRIDGE_IDLE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_PBRIDGE_IDLE_SHIFT))&MCM_CPCR_PBRIDGE_IDLE_MASK)
7121 #define MCM_CPCR_CBRR_MASK 0x200u
7122 #define MCM_CPCR_CBRR_SHIFT 9u
7123 #define MCM_CPCR_CBRR_WIDTH 1u
7124 #define MCM_CPCR_CBRR(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_CBRR_SHIFT))&MCM_CPCR_CBRR_MASK)
7125 /* PID Bit Fields */
7126 #define MCM_PID_PID_MASK 0xFFu
7127 #define MCM_PID_PID_SHIFT 0u
7128 #define MCM_PID_PID_WIDTH 8u
7129 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
7130 /* CPO Bit Fields */
7131 #define MCM_CPO_CPOREQ_MASK 0x1u
7132 #define MCM_CPO_CPOREQ_SHIFT 0u
7133 #define MCM_CPO_CPOREQ_WIDTH 1u
7134 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
7135 #define MCM_CPO_CPOACK_MASK 0x2u
7136 #define MCM_CPO_CPOACK_SHIFT 1u
7137 #define MCM_CPO_CPOACK_WIDTH 1u
7138 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
7139 #define MCM_CPO_CPOWOI_MASK 0x4u
7140 #define MCM_CPO_CPOWOI_SHIFT 2u
7141 #define MCM_CPO_CPOWOI_WIDTH 1u
7142 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
7143 /* LMDR Bit Fields */
7144 #define MCM_LMDR_CF0_MASK 0xFu
7145 #define MCM_LMDR_CF0_SHIFT 0u
7146 #define MCM_LMDR_CF0_WIDTH 4u
7147 #define MCM_LMDR_CF0(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF0_SHIFT))&MCM_LMDR_CF0_MASK)
7148 #define MCM_LMDR_MT_MASK 0xE000u
7149 #define MCM_LMDR_MT_SHIFT 13u
7150 #define MCM_LMDR_MT_WIDTH 3u
7151 #define MCM_LMDR_MT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_MT_SHIFT))&MCM_LMDR_MT_MASK)
7152 #define MCM_LMDR_DPW_MASK 0xE0000u
7153 #define MCM_LMDR_DPW_SHIFT 17u
7154 #define MCM_LMDR_DPW_WIDTH 3u
7155 #define MCM_LMDR_DPW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_DPW_SHIFT))&MCM_LMDR_DPW_MASK)
7156 #define MCM_LMDR_WY_MASK 0xF00000u
7157 #define MCM_LMDR_WY_SHIFT 20u
7158 #define MCM_LMDR_WY_WIDTH 4u
7159 #define MCM_LMDR_WY(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_WY_SHIFT))&MCM_LMDR_WY_MASK)
7160 #define MCM_LMDR_LMSZ_MASK 0xF000000u
7161 #define MCM_LMDR_LMSZ_SHIFT 24u
7162 #define MCM_LMDR_LMSZ_WIDTH 4u
7163 #define MCM_LMDR_LMSZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZ_SHIFT))&MCM_LMDR_LMSZ_MASK)
7164 #define MCM_LMDR_LMSZH_MASK 0x10000000u
7165 #define MCM_LMDR_LMSZH_SHIFT 28u
7166 #define MCM_LMDR_LMSZH_WIDTH 1u
7167 #define MCM_LMDR_LMSZH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZH_SHIFT))&MCM_LMDR_LMSZH_MASK)
7168 #define MCM_LMDR_V_MASK 0x80000000u
7169 #define MCM_LMDR_V_SHIFT 31u
7170 #define MCM_LMDR_V_WIDTH 1u
7171 #define MCM_LMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_V_SHIFT))&MCM_LMDR_V_MASK)
7172 /* LMDR2 Bit Fields */
7173 #define MCM_LMDR2_CF1_MASK 0xF0u
7174 #define MCM_LMDR2_CF1_SHIFT 4u
7175 #define MCM_LMDR2_CF1_WIDTH 4u
7176 #define MCM_LMDR2_CF1(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_CF1_SHIFT))&MCM_LMDR2_CF1_MASK)
7177 #define MCM_LMDR2_MT_MASK 0xE000u
7178 #define MCM_LMDR2_MT_SHIFT 13u
7179 #define MCM_LMDR2_MT_WIDTH 3u
7180 #define MCM_LMDR2_MT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_MT_SHIFT))&MCM_LMDR2_MT_MASK)
7181 #define MCM_LMDR2_DPW_MASK 0xE0000u
7182 #define MCM_LMDR2_DPW_SHIFT 17u
7183 #define MCM_LMDR2_DPW_WIDTH 3u
7184 #define MCM_LMDR2_DPW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_DPW_SHIFT))&MCM_LMDR2_DPW_MASK)
7185 #define MCM_LMDR2_WY_MASK 0xF00000u
7186 #define MCM_LMDR2_WY_SHIFT 20u
7187 #define MCM_LMDR2_WY_WIDTH 4u
7188 #define MCM_LMDR2_WY(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_WY_SHIFT))&MCM_LMDR2_WY_MASK)
7189 #define MCM_LMDR2_LMSZ_MASK 0xF000000u
7190 #define MCM_LMDR2_LMSZ_SHIFT 24u
7191 #define MCM_LMDR2_LMSZ_WIDTH 4u
7192 #define MCM_LMDR2_LMSZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZ_SHIFT))&MCM_LMDR2_LMSZ_MASK)
7193 #define MCM_LMDR2_LMSZH_MASK 0x10000000u
7194 #define MCM_LMDR2_LMSZH_SHIFT 28u
7195 #define MCM_LMDR2_LMSZH_WIDTH 1u
7196 #define MCM_LMDR2_LMSZH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZH_SHIFT))&MCM_LMDR2_LMSZH_MASK)
7197 #define MCM_LMDR2_V_MASK 0x80000000u
7198 #define MCM_LMDR2_V_SHIFT 31u
7199 #define MCM_LMDR2_V_WIDTH 1u
7200 #define MCM_LMDR2_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_V_SHIFT))&MCM_LMDR2_V_MASK)
7201 /* LMPECR Bit Fields */
7202 #define MCM_LMPECR_ERNCR_MASK 0x1u
7203 #define MCM_LMPECR_ERNCR_SHIFT 0u
7204 #define MCM_LMPECR_ERNCR_WIDTH 1u
7205 #define MCM_LMPECR_ERNCR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ERNCR_SHIFT))&MCM_LMPECR_ERNCR_MASK)
7206 #define MCM_LMPECR_ER1BR_MASK 0x100u
7207 #define MCM_LMPECR_ER1BR_SHIFT 8u
7208 #define MCM_LMPECR_ER1BR_WIDTH 1u
7209 #define MCM_LMPECR_ER1BR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ER1BR_SHIFT))&MCM_LMPECR_ER1BR_MASK)
7210 /* LMPEIR Bit Fields */
7211 #define MCM_LMPEIR_ENC_MASK 0xFFu
7212 #define MCM_LMPEIR_ENC_SHIFT 0u
7213 #define MCM_LMPEIR_ENC_WIDTH 8u
7214 #define MCM_LMPEIR_ENC(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_ENC_SHIFT))&MCM_LMPEIR_ENC_MASK)
7215 #define MCM_LMPEIR_E1B_MASK 0xFF00u
7216 #define MCM_LMPEIR_E1B_SHIFT 8u
7217 #define MCM_LMPEIR_E1B_WIDTH 8u
7218 #define MCM_LMPEIR_E1B(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_E1B_SHIFT))&MCM_LMPEIR_E1B_MASK)
7219 #define MCM_LMPEIR_PEELOC_MASK 0x1F000000u
7220 #define MCM_LMPEIR_PEELOC_SHIFT 24u
7221 #define MCM_LMPEIR_PEELOC_WIDTH 5u
7222 #define MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PEELOC_SHIFT))&MCM_LMPEIR_PEELOC_MASK)
7223 #define MCM_LMPEIR_V_MASK 0x80000000u
7224 #define MCM_LMPEIR_V_SHIFT 31u
7225 #define MCM_LMPEIR_V_WIDTH 1u
7226 #define MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_V_SHIFT))&MCM_LMPEIR_V_MASK)
7227 /* LMFAR Bit Fields */
7228 #define MCM_LMFAR_EFADD_MASK 0xFFFFFFFFu
7229 #define MCM_LMFAR_EFADD_SHIFT 0u
7230 #define MCM_LMFAR_EFADD_WIDTH 32u
7231 #define MCM_LMFAR_EFADD(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFAR_EFADD_SHIFT))&MCM_LMFAR_EFADD_MASK)
7232 /* LMFATR Bit Fields */
7233 #define MCM_LMFATR_PEFPRT_MASK 0xFu
7234 #define MCM_LMFATR_PEFPRT_SHIFT 0u
7235 #define MCM_LMFATR_PEFPRT_WIDTH 4u
7236 #define MCM_LMFATR_PEFPRT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFPRT_SHIFT))&MCM_LMFATR_PEFPRT_MASK)
7237 #define MCM_LMFATR_PEFSIZE_MASK 0x70u
7238 #define MCM_LMFATR_PEFSIZE_SHIFT 4u
7239 #define MCM_LMFATR_PEFSIZE_WIDTH 3u
7240 #define MCM_LMFATR_PEFSIZE(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFSIZE_SHIFT))&MCM_LMFATR_PEFSIZE_MASK)
7241 #define MCM_LMFATR_PEFW_MASK 0x80u
7242 #define MCM_LMFATR_PEFW_SHIFT 7u
7243 #define MCM_LMFATR_PEFW_WIDTH 1u
7244 #define MCM_LMFATR_PEFW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFW_SHIFT))&MCM_LMFATR_PEFW_MASK)
7245 #define MCM_LMFATR_PEFMST_MASK 0xFF00u
7246 #define MCM_LMFATR_PEFMST_SHIFT 8u
7247 #define MCM_LMFATR_PEFMST_WIDTH 8u
7248 #define MCM_LMFATR_PEFMST(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFMST_SHIFT))&MCM_LMFATR_PEFMST_MASK)
7249 #define MCM_LMFATR_OVR_MASK 0x80000000u
7250 #define MCM_LMFATR_OVR_SHIFT 31u
7251 #define MCM_LMFATR_OVR_WIDTH 1u
7252 #define MCM_LMFATR_OVR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_OVR_SHIFT))&MCM_LMFATR_OVR_MASK)
7253 /* LMFDHR Bit Fields */
7254 #define MCM_LMFDHR_PEFDH_MASK 0xFFFFFFFFu
7255 #define MCM_LMFDHR_PEFDH_SHIFT 0u
7256 #define MCM_LMFDHR_PEFDH_WIDTH 32u
7257 #define MCM_LMFDHR_PEFDH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFDHR_PEFDH_SHIFT))&MCM_LMFDHR_PEFDH_MASK)
7258 /* LMFDLR Bit Fields */
7259 #define MCM_LMFDLR_PEFDL_MASK 0xFFFFFFFFu
7260 #define MCM_LMFDLR_PEFDL_SHIFT 0u
7261 #define MCM_LMFDLR_PEFDL_WIDTH 32u
7262 #define MCM_LMFDLR_PEFDL(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFDLR_PEFDL_SHIFT))&MCM_LMFDLR_PEFDL_MASK)
7263  /* end of group MCM_Register_Masks */
7267 
7268  /* end of group MCM_Peripheral_Access_Layer */
7272 
7273 
7274 /* ----------------------------------------------------------------------------
7275  -- MPU Peripheral Access Layer
7276  ---------------------------------------------------------------------------- */
7277 
7285 #define MPU_EAR_EDR_COUNT 2u
7286 #define MPU_RGD_COUNT 8u
7287 #define MPU_RGDAAC_COUNT 8u
7288 
7290 typedef struct {
7291  __IO uint32_t CESR;
7292  uint8_t RESERVED_0[12];
7293  struct { /* offset: 0x10, array step: 0x8 */
7294  __I uint32_t EAR;
7297  __I uint32_t EDR;
7300  } EAR_EDR[MPU_EAR_EDR_COUNT];
7301  uint8_t RESERVED_1[992];
7302  struct { /* offset: 0x400, array step: 0x10 */
7303  __IO uint32_t WORD0;
7304  __IO uint32_t WORD1;
7305  __IO uint32_t WORD2;
7306  __IO uint32_t WORD3;
7307  } RGD[MPU_RGD_COUNT];
7308  uint8_t RESERVED_2[896];
7309  __IO uint32_t RGDAAC[MPU_RGDAAC_COUNT];
7313 
7315 #define MPU_INSTANCE_COUNT (1u)
7316 
7317 
7318 /* MPU - Peripheral instance base addresses */
7320 #define MPU_BASE (0x4000D000u)
7321 
7322 #define MPU ((MPU_Type *)MPU_BASE)
7323 
7324 #define MPU_BASE_ADDRS { MPU_BASE }
7325 
7326 #define MPU_BASE_PTRS { MPU }
7327 
7328 /* ----------------------------------------------------------------------------
7329  -- MPU Register Masks
7330  ---------------------------------------------------------------------------- */
7331 
7337 /* CESR Bit Fields */
7338 #define MPU_CESR_VLD_MASK 0x1u
7339 #define MPU_CESR_VLD_SHIFT 0u
7340 #define MPU_CESR_VLD_WIDTH 1u
7341 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
7342 #define MPU_CESR_NRGD_MASK 0xF00u
7343 #define MPU_CESR_NRGD_SHIFT 8u
7344 #define MPU_CESR_NRGD_WIDTH 4u
7345 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
7346 #define MPU_CESR_NSP_MASK 0xF000u
7347 #define MPU_CESR_NSP_SHIFT 12u
7348 #define MPU_CESR_NSP_WIDTH 4u
7349 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
7350 #define MPU_CESR_HRL_MASK 0xF0000u
7351 #define MPU_CESR_HRL_SHIFT 16u
7352 #define MPU_CESR_HRL_WIDTH 4u
7353 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
7354 #define MPU_CESR_SPERR1_MASK 0x40000000u
7355 #define MPU_CESR_SPERR1_SHIFT 30u
7356 #define MPU_CESR_SPERR1_WIDTH 1u
7357 #define MPU_CESR_SPERR1(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR1_SHIFT))&MPU_CESR_SPERR1_MASK)
7358 #define MPU_CESR_SPERR0_MASK 0x80000000u
7359 #define MPU_CESR_SPERR0_SHIFT 31u
7360 #define MPU_CESR_SPERR0_WIDTH 1u
7361 #define MPU_CESR_SPERR0(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR0_SHIFT))&MPU_CESR_SPERR0_MASK)
7362 /* EAR Bit Fields */
7363 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
7364 #define MPU_EAR_EADDR_SHIFT 0u
7365 #define MPU_EAR_EADDR_WIDTH 32u
7366 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
7367 /* EDR Bit Fields */
7368 #define MPU_EDR_ERW_MASK 0x1u
7369 #define MPU_EDR_ERW_SHIFT 0u
7370 #define MPU_EDR_ERW_WIDTH 1u
7371 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
7372 #define MPU_EDR_EATTR_MASK 0xEu
7373 #define MPU_EDR_EATTR_SHIFT 1u
7374 #define MPU_EDR_EATTR_WIDTH 3u
7375 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
7376 #define MPU_EDR_EMN_MASK 0xF0u
7377 #define MPU_EDR_EMN_SHIFT 4u
7378 #define MPU_EDR_EMN_WIDTH 4u
7379 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
7380 #define MPU_EDR_EPID_MASK 0xFF00u
7381 #define MPU_EDR_EPID_SHIFT 8u
7382 #define MPU_EDR_EPID_WIDTH 8u
7383 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
7384 #define MPU_EDR_EACD_MASK 0xFFFF0000u
7385 #define MPU_EDR_EACD_SHIFT 16u
7386 #define MPU_EDR_EACD_WIDTH 16u
7387 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
7388 /* RGD_WORD0 Bit Fields */
7389 #define MPU_RGD_WORD0_SRTADDR_MASK 0xFFFFFFE0u
7390 #define MPU_RGD_WORD0_SRTADDR_SHIFT 5u
7391 #define MPU_RGD_WORD0_SRTADDR_WIDTH 27u
7392 #define MPU_RGD_WORD0_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD0_SRTADDR_SHIFT))&MPU_RGD_WORD0_SRTADDR_MASK)
7393 /* RGD_WORD1 Bit Fields */
7394 #define MPU_RGD_WORD1_ENDADDR_MASK 0xFFFFFFE0u
7395 #define MPU_RGD_WORD1_ENDADDR_SHIFT 5u
7396 #define MPU_RGD_WORD1_ENDADDR_WIDTH 27u
7397 #define MPU_RGD_WORD1_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD1_ENDADDR_SHIFT))&MPU_RGD_WORD1_ENDADDR_MASK)
7398 /* RGD_WORD2 Bit Fields */
7399 #define MPU_RGD_WORD2_M0UM_MASK 0x7u
7400 #define MPU_RGD_WORD2_M0UM_SHIFT 0u
7401 #define MPU_RGD_WORD2_M0UM_WIDTH 3u
7402 #define MPU_RGD_WORD2_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0UM_SHIFT))&MPU_RGD_WORD2_M0UM_MASK)
7403 #define MPU_RGD_WORD2_M0SM_MASK 0x18u
7404 #define MPU_RGD_WORD2_M0SM_SHIFT 3u
7405 #define MPU_RGD_WORD2_M0SM_WIDTH 2u
7406 #define MPU_RGD_WORD2_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0SM_SHIFT))&MPU_RGD_WORD2_M0SM_MASK)
7407 #define MPU_RGD_WORD2_M0PE_MASK 0x20u
7408 #define MPU_RGD_WORD2_M0PE_SHIFT 5u
7409 #define MPU_RGD_WORD2_M0PE_WIDTH 1u
7410 #define MPU_RGD_WORD2_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0PE_SHIFT))&MPU_RGD_WORD2_M0PE_MASK)
7411 #define MPU_RGD_WORD2_M1UM_MASK 0x1C0u
7412 #define MPU_RGD_WORD2_M1UM_SHIFT 6u
7413 #define MPU_RGD_WORD2_M1UM_WIDTH 3u
7414 #define MPU_RGD_WORD2_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1UM_SHIFT))&MPU_RGD_WORD2_M1UM_MASK)
7415 #define MPU_RGD_WORD2_M1SM_MASK 0x600u
7416 #define MPU_RGD_WORD2_M1SM_SHIFT 9u
7417 #define MPU_RGD_WORD2_M1SM_WIDTH 2u
7418 #define MPU_RGD_WORD2_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1SM_SHIFT))&MPU_RGD_WORD2_M1SM_MASK)
7419 #define MPU_RGD_WORD2_M2UM_MASK 0x7000u
7420 #define MPU_RGD_WORD2_M2UM_SHIFT 12u
7421 #define MPU_RGD_WORD2_M2UM_WIDTH 3u
7422 #define MPU_RGD_WORD2_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2UM_SHIFT))&MPU_RGD_WORD2_M2UM_MASK)
7423 #define MPU_RGD_WORD2_M2SM_MASK 0x18000u
7424 #define MPU_RGD_WORD2_M2SM_SHIFT 15u
7425 #define MPU_RGD_WORD2_M2SM_WIDTH 2u
7426 #define MPU_RGD_WORD2_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2SM_SHIFT))&MPU_RGD_WORD2_M2SM_MASK)
7427 #define MPU_RGD_WORD2_M3UM_MASK 0x1C0000u
7428 #define MPU_RGD_WORD2_M3UM_SHIFT 18u
7429 #define MPU_RGD_WORD2_M3UM_WIDTH 3u
7430 #define MPU_RGD_WORD2_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3UM_SHIFT))&MPU_RGD_WORD2_M3UM_MASK)
7431 #define MPU_RGD_WORD2_M3SM_MASK 0x600000u
7432 #define MPU_RGD_WORD2_M3SM_SHIFT 21u
7433 #define MPU_RGD_WORD2_M3SM_WIDTH 2u
7434 #define MPU_RGD_WORD2_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3SM_SHIFT))&MPU_RGD_WORD2_M3SM_MASK)
7435 #define MPU_RGD_WORD2_M4WE_MASK 0x1000000u
7436 #define MPU_RGD_WORD2_M4WE_SHIFT 24u
7437 #define MPU_RGD_WORD2_M4WE_WIDTH 1u
7438 #define MPU_RGD_WORD2_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4WE_SHIFT))&MPU_RGD_WORD2_M4WE_MASK)
7439 #define MPU_RGD_WORD2_M4RE_MASK 0x2000000u
7440 #define MPU_RGD_WORD2_M4RE_SHIFT 25u
7441 #define MPU_RGD_WORD2_M4RE_WIDTH 1u
7442 #define MPU_RGD_WORD2_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4RE_SHIFT))&MPU_RGD_WORD2_M4RE_MASK)
7443 #define MPU_RGD_WORD2_M5WE_MASK 0x4000000u
7444 #define MPU_RGD_WORD2_M5WE_SHIFT 26u
7445 #define MPU_RGD_WORD2_M5WE_WIDTH 1u
7446 #define MPU_RGD_WORD2_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5WE_SHIFT))&MPU_RGD_WORD2_M5WE_MASK)
7447 #define MPU_RGD_WORD2_M5RE_MASK 0x8000000u
7448 #define MPU_RGD_WORD2_M5RE_SHIFT 27u
7449 #define MPU_RGD_WORD2_M5RE_WIDTH 1u
7450 #define MPU_RGD_WORD2_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5RE_SHIFT))&MPU_RGD_WORD2_M5RE_MASK)
7451 #define MPU_RGD_WORD2_M6WE_MASK 0x10000000u
7452 #define MPU_RGD_WORD2_M6WE_SHIFT 28u
7453 #define MPU_RGD_WORD2_M6WE_WIDTH 1u
7454 #define MPU_RGD_WORD2_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6WE_SHIFT))&MPU_RGD_WORD2_M6WE_MASK)
7455 #define MPU_RGD_WORD2_M6RE_MASK 0x20000000u
7456 #define MPU_RGD_WORD2_M6RE_SHIFT 29u
7457 #define MPU_RGD_WORD2_M6RE_WIDTH 1u
7458 #define MPU_RGD_WORD2_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6RE_SHIFT))&MPU_RGD_WORD2_M6RE_MASK)
7459 #define MPU_RGD_WORD2_M7WE_MASK 0x40000000u
7460 #define MPU_RGD_WORD2_M7WE_SHIFT 30u
7461 #define MPU_RGD_WORD2_M7WE_WIDTH 1u
7462 #define MPU_RGD_WORD2_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7WE_SHIFT))&MPU_RGD_WORD2_M7WE_MASK)
7463 #define MPU_RGD_WORD2_M7RE_MASK 0x80000000u
7464 #define MPU_RGD_WORD2_M7RE_SHIFT 31u
7465 #define MPU_RGD_WORD2_M7RE_WIDTH 1u
7466 #define MPU_RGD_WORD2_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7RE_SHIFT))&MPU_RGD_WORD2_M7RE_MASK)
7467 /* RGD_WORD3 Bit Fields */
7468 #define MPU_RGD_WORD3_VLD_MASK 0x1u
7469 #define MPU_RGD_WORD3_VLD_SHIFT 0u
7470 #define MPU_RGD_WORD3_VLD_WIDTH 1u
7471 #define MPU_RGD_WORD3_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_VLD_SHIFT))&MPU_RGD_WORD3_VLD_MASK)
7472 #define MPU_RGD_WORD3_PIDMASK_MASK 0xFF0000u
7473 #define MPU_RGD_WORD3_PIDMASK_SHIFT 16u
7474 #define MPU_RGD_WORD3_PIDMASK_WIDTH 8u
7475 #define MPU_RGD_WORD3_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PIDMASK_SHIFT))&MPU_RGD_WORD3_PIDMASK_MASK)
7476 #define MPU_RGD_WORD3_PID_MASK 0xFF000000u
7477 #define MPU_RGD_WORD3_PID_SHIFT 24u
7478 #define MPU_RGD_WORD3_PID_WIDTH 8u
7479 #define MPU_RGD_WORD3_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PID_SHIFT))&MPU_RGD_WORD3_PID_MASK)
7480 /* RGDAAC Bit Fields */
7481 #define MPU_RGDAAC_M0UM_MASK 0x7u
7482 #define MPU_RGDAAC_M0UM_SHIFT 0u
7483 #define MPU_RGDAAC_M0UM_WIDTH 3u
7484 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
7485 #define MPU_RGDAAC_M0SM_MASK 0x18u
7486 #define MPU_RGDAAC_M0SM_SHIFT 3u
7487 #define MPU_RGDAAC_M0SM_WIDTH 2u
7488 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
7489 #define MPU_RGDAAC_M0PE_MASK 0x20u
7490 #define MPU_RGDAAC_M0PE_SHIFT 5u
7491 #define MPU_RGDAAC_M0PE_WIDTH 1u
7492 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
7493 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
7494 #define MPU_RGDAAC_M1UM_SHIFT 6u
7495 #define MPU_RGDAAC_M1UM_WIDTH 3u
7496 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
7497 #define MPU_RGDAAC_M1SM_MASK 0x600u
7498 #define MPU_RGDAAC_M1SM_SHIFT 9u
7499 #define MPU_RGDAAC_M1SM_WIDTH 2u
7500 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
7501 #define MPU_RGDAAC_M2UM_MASK 0x7000u
7502 #define MPU_RGDAAC_M2UM_SHIFT 12u
7503 #define MPU_RGDAAC_M2UM_WIDTH 3u
7504 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
7505 #define MPU_RGDAAC_M2SM_MASK 0x18000u
7506 #define MPU_RGDAAC_M2SM_SHIFT 15u
7507 #define MPU_RGDAAC_M2SM_WIDTH 2u
7508 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
7509 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
7510 #define MPU_RGDAAC_M3UM_SHIFT 18u
7511 #define MPU_RGDAAC_M3UM_WIDTH 3u
7512 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
7513 #define MPU_RGDAAC_M3SM_MASK 0x600000u
7514 #define MPU_RGDAAC_M3SM_SHIFT 21u
7515 #define MPU_RGDAAC_M3SM_WIDTH 2u
7516 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
7517 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
7518 #define MPU_RGDAAC_M4WE_SHIFT 24u
7519 #define MPU_RGDAAC_M4WE_WIDTH 1u
7520 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
7521 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
7522 #define MPU_RGDAAC_M4RE_SHIFT 25u
7523 #define MPU_RGDAAC_M4RE_WIDTH 1u
7524 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
7525 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
7526 #define MPU_RGDAAC_M5WE_SHIFT 26u
7527 #define MPU_RGDAAC_M5WE_WIDTH 1u
7528 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
7529 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
7530 #define MPU_RGDAAC_M5RE_SHIFT 27u
7531 #define MPU_RGDAAC_M5RE_WIDTH 1u
7532 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
7533 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
7534 #define MPU_RGDAAC_M6WE_SHIFT 28u
7535 #define MPU_RGDAAC_M6WE_WIDTH 1u
7536 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
7537 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
7538 #define MPU_RGDAAC_M6RE_SHIFT 29u
7539 #define MPU_RGDAAC_M6RE_WIDTH 1u
7540 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
7541 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
7542 #define MPU_RGDAAC_M7WE_SHIFT 30u
7543 #define MPU_RGDAAC_M7WE_WIDTH 1u
7544 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
7545 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
7546 #define MPU_RGDAAC_M7RE_SHIFT 31u
7547 #define MPU_RGDAAC_M7RE_WIDTH 1u
7548 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
7549  /* end of group MPU_Register_Masks */
7553 
7554  /* end of group MPU_Peripheral_Access_Layer */
7558 
7559 
7560 /* ----------------------------------------------------------------------------
7561  -- MSCM Peripheral Access Layer
7562  ---------------------------------------------------------------------------- */
7563 
7571 #define MSCM_OCMDR_COUNT 3u
7572 
7574 typedef struct {
7575  __I uint32_t CPxTYPE;
7576  __I uint32_t CPxNUM;
7577  __I uint32_t CPxMASTER;
7578  __I uint32_t CPxCOUNT;
7579  __I uint32_t CPxCFG0;
7580  __I uint32_t CPxCFG1;
7581  __I uint32_t CPxCFG2;
7582  __I uint32_t CPxCFG3;
7583  __I uint32_t CP0TYPE;
7584  __I uint32_t CP0NUM;
7585  __I uint32_t CP0MASTER;
7586  __I uint32_t CP0COUNT;
7587  __I uint32_t CP0CFG0;
7588  __I uint32_t CP0CFG1;
7589  __I uint32_t CP0CFG2;
7590  __I uint32_t CP0CFG3;
7591  uint8_t RESERVED_0[960];
7592  __IO uint32_t OCMDR[MSCM_OCMDR_COUNT];
7594 
7596 #define MSCM_INSTANCE_COUNT (1u)
7597 
7598 
7599 /* MSCM - Peripheral instance base addresses */
7601 #define MSCM_BASE (0x40001000u)
7602 
7603 #define MSCM ((MSCM_Type *)MSCM_BASE)
7604 
7605 #define MSCM_BASE_ADDRS { MSCM_BASE }
7606 
7607 #define MSCM_BASE_PTRS { MSCM }
7608 
7609 /* ----------------------------------------------------------------------------
7610  -- MSCM Register Masks
7611  ---------------------------------------------------------------------------- */
7612 
7618 /* CPxTYPE Bit Fields */
7619 #define MSCM_CPxTYPE_RYPZ_MASK 0xFFu
7620 #define MSCM_CPxTYPE_RYPZ_SHIFT 0u
7621 #define MSCM_CPxTYPE_RYPZ_WIDTH 8u
7622 #define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_RYPZ_SHIFT))&MSCM_CPxTYPE_RYPZ_MASK)
7623 #define MSCM_CPxTYPE_PERSONALITY_MASK 0xFFFFFF00u
7624 #define MSCM_CPxTYPE_PERSONALITY_SHIFT 8u
7625 #define MSCM_CPxTYPE_PERSONALITY_WIDTH 24u
7626 #define MSCM_CPxTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_PERSONALITY_SHIFT))&MSCM_CPxTYPE_PERSONALITY_MASK)
7627 /* CPxNUM Bit Fields */
7628 #define MSCM_CPxNUM_CPN_MASK 0x1u
7629 #define MSCM_CPxNUM_CPN_SHIFT 0u
7630 #define MSCM_CPxNUM_CPN_WIDTH 1u
7631 #define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxNUM_CPN_SHIFT))&MSCM_CPxNUM_CPN_MASK)
7632 /* CPxMASTER Bit Fields */
7633 #define MSCM_CPxMASTER_PPMN_MASK 0x3Fu
7634 #define MSCM_CPxMASTER_PPMN_SHIFT 0u
7635 #define MSCM_CPxMASTER_PPMN_WIDTH 6u
7636 #define MSCM_CPxMASTER_PPMN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxMASTER_PPMN_SHIFT))&MSCM_CPxMASTER_PPMN_MASK)
7637 /* CPxCOUNT Bit Fields */
7638 #define MSCM_CPxCOUNT_PCNT_MASK 0x3u
7639 #define MSCM_CPxCOUNT_PCNT_SHIFT 0u
7640 #define MSCM_CPxCOUNT_PCNT_WIDTH 2u
7641 #define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCOUNT_PCNT_SHIFT))&MSCM_CPxCOUNT_PCNT_MASK)
7642 /* CPxCFG0 Bit Fields */
7643 #define MSCM_CPxCFG0_DCWY_MASK 0xFFu
7644 #define MSCM_CPxCFG0_DCWY_SHIFT 0u
7645 #define MSCM_CPxCFG0_DCWY_WIDTH 8u
7646 #define MSCM_CPxCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_DCWY_SHIFT))&MSCM_CPxCFG0_DCWY_MASK)
7647 #define MSCM_CPxCFG0_DCSZ_MASK 0xFF00u
7648 #define MSCM_CPxCFG0_DCSZ_SHIFT 8u
7649 #define MSCM_CPxCFG0_DCSZ_WIDTH 8u
7650 #define MSCM_CPxCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_DCSZ_SHIFT))&MSCM_CPxCFG0_DCSZ_MASK)
7651 #define MSCM_CPxCFG0_ICWY_MASK 0xFF0000u
7652 #define MSCM_CPxCFG0_ICWY_SHIFT 16u
7653 #define MSCM_CPxCFG0_ICWY_WIDTH 8u
7654 #define MSCM_CPxCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_ICWY_SHIFT))&MSCM_CPxCFG0_ICWY_MASK)
7655 #define MSCM_CPxCFG0_ICSZ_MASK 0xFF000000u
7656 #define MSCM_CPxCFG0_ICSZ_SHIFT 24u
7657 #define MSCM_CPxCFG0_ICSZ_WIDTH 8u
7658 #define MSCM_CPxCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_ICSZ_SHIFT))&MSCM_CPxCFG0_ICSZ_MASK)
7659 /* CPxCFG1 Bit Fields */
7660 #define MSCM_CPxCFG1_L2WY_MASK 0xFF0000u
7661 #define MSCM_CPxCFG1_L2WY_SHIFT 16u
7662 #define MSCM_CPxCFG1_L2WY_WIDTH 8u
7663 #define MSCM_CPxCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG1_L2WY_SHIFT))&MSCM_CPxCFG1_L2WY_MASK)
7664 #define MSCM_CPxCFG1_L2SZ_MASK 0xFF000000u
7665 #define MSCM_CPxCFG1_L2SZ_SHIFT 24u
7666 #define MSCM_CPxCFG1_L2SZ_WIDTH 8u
7667 #define MSCM_CPxCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG1_L2SZ_SHIFT))&MSCM_CPxCFG1_L2SZ_MASK)
7668 /* CPxCFG2 Bit Fields */
7669 #define MSCM_CPxCFG2_TMUSZ_MASK 0xFF00u
7670 #define MSCM_CPxCFG2_TMUSZ_SHIFT 8u
7671 #define MSCM_CPxCFG2_TMUSZ_WIDTH 8u
7672 #define MSCM_CPxCFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG2_TMUSZ_SHIFT))&MSCM_CPxCFG2_TMUSZ_MASK)
7673 #define MSCM_CPxCFG2_TMLSZ_MASK 0xFF000000u
7674 #define MSCM_CPxCFG2_TMLSZ_SHIFT 24u
7675 #define MSCM_CPxCFG2_TMLSZ_WIDTH 8u
7676 #define MSCM_CPxCFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG2_TMLSZ_SHIFT))&MSCM_CPxCFG2_TMLSZ_MASK)
7677 /* CPxCFG3 Bit Fields */
7678 #define MSCM_CPxCFG3_FPU_MASK 0x1u
7679 #define MSCM_CPxCFG3_FPU_SHIFT 0u
7680 #define MSCM_CPxCFG3_FPU_WIDTH 1u
7681 #define MSCM_CPxCFG3_FPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_FPU_SHIFT))&MSCM_CPxCFG3_FPU_MASK)
7682 #define MSCM_CPxCFG3_SIMD_MASK 0x2u
7683 #define MSCM_CPxCFG3_SIMD_SHIFT 1u
7684 #define MSCM_CPxCFG3_SIMD_WIDTH 1u
7685 #define MSCM_CPxCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_SIMD_SHIFT))&MSCM_CPxCFG3_SIMD_MASK)
7686 #define MSCM_CPxCFG3_JAZ_MASK 0x4u
7687 #define MSCM_CPxCFG3_JAZ_SHIFT 2u
7688 #define MSCM_CPxCFG3_JAZ_WIDTH 1u
7689 #define MSCM_CPxCFG3_JAZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_JAZ_SHIFT))&MSCM_CPxCFG3_JAZ_MASK)
7690 #define MSCM_CPxCFG3_MMU_MASK 0x8u
7691 #define MSCM_CPxCFG3_MMU_SHIFT 3u
7692 #define MSCM_CPxCFG3_MMU_WIDTH 1u
7693 #define MSCM_CPxCFG3_MMU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_MMU_SHIFT))&MSCM_CPxCFG3_MMU_MASK)
7694 #define MSCM_CPxCFG3_TZ_MASK 0x10u
7695 #define MSCM_CPxCFG3_TZ_SHIFT 4u
7696 #define MSCM_CPxCFG3_TZ_WIDTH 1u
7697 #define MSCM_CPxCFG3_TZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_TZ_SHIFT))&MSCM_CPxCFG3_TZ_MASK)
7698 #define MSCM_CPxCFG3_CMP_MASK 0x20u
7699 #define MSCM_CPxCFG3_CMP_SHIFT 5u
7700 #define MSCM_CPxCFG3_CMP_WIDTH 1u
7701 #define MSCM_CPxCFG3_CMP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_CMP_SHIFT))&MSCM_CPxCFG3_CMP_MASK)
7702 #define MSCM_CPxCFG3_BB_MASK 0x40u
7703 #define MSCM_CPxCFG3_BB_SHIFT 6u
7704 #define MSCM_CPxCFG3_BB_WIDTH 1u
7705 #define MSCM_CPxCFG3_BB(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_BB_SHIFT))&MSCM_CPxCFG3_BB_MASK)
7706 #define MSCM_CPxCFG3_SBP_MASK 0x300u
7707 #define MSCM_CPxCFG3_SBP_SHIFT 8u
7708 #define MSCM_CPxCFG3_SBP_WIDTH 2u
7709 #define MSCM_CPxCFG3_SBP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_SBP_SHIFT))&MSCM_CPxCFG3_SBP_MASK)
7710 /* CP0TYPE Bit Fields */
7711 #define MSCM_CP0TYPE_RYPZ_MASK 0xFFu
7712 #define MSCM_CP0TYPE_RYPZ_SHIFT 0u
7713 #define MSCM_CP0TYPE_RYPZ_WIDTH 8u
7714 #define MSCM_CP0TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_RYPZ_SHIFT))&MSCM_CP0TYPE_RYPZ_MASK)
7715 #define MSCM_CP0TYPE_PERSONALITY_MASK 0xFFFFFF00u
7716 #define MSCM_CP0TYPE_PERSONALITY_SHIFT 8u
7717 #define MSCM_CP0TYPE_PERSONALITY_WIDTH 24u
7718 #define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_PERSONALITY_SHIFT))&MSCM_CP0TYPE_PERSONALITY_MASK)
7719 /* CP0NUM Bit Fields */
7720 #define MSCM_CP0NUM_CPN_MASK 0x1u
7721 #define MSCM_CP0NUM_CPN_SHIFT 0u
7722 #define MSCM_CP0NUM_CPN_WIDTH 1u
7723 #define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0NUM_CPN_SHIFT))&MSCM_CP0NUM_CPN_MASK)
7724 /* CP0MASTER Bit Fields */
7725 #define MSCM_CP0MASTER_PPMN_MASK 0x3Fu
7726 #define MSCM_CP0MASTER_PPMN_SHIFT 0u
7727 #define MSCM_CP0MASTER_PPMN_WIDTH 6u
7728 #define MSCM_CP0MASTER_PPMN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0MASTER_PPMN_SHIFT))&MSCM_CP0MASTER_PPMN_MASK)
7729 /* CP0COUNT Bit Fields */
7730 #define MSCM_CP0COUNT_PCNT_MASK 0x3u
7731 #define MSCM_CP0COUNT_PCNT_SHIFT 0u
7732 #define MSCM_CP0COUNT_PCNT_WIDTH 2u
7733 #define MSCM_CP0COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0COUNT_PCNT_SHIFT))&MSCM_CP0COUNT_PCNT_MASK)
7734 /* CP0CFG0 Bit Fields */
7735 #define MSCM_CP0CFG0_DCWY_MASK 0xFFu
7736 #define MSCM_CP0CFG0_DCWY_SHIFT 0u
7737 #define MSCM_CP0CFG0_DCWY_WIDTH 8u
7738 #define MSCM_CP0CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_DCWY_SHIFT))&MSCM_CP0CFG0_DCWY_MASK)
7739 #define MSCM_CP0CFG0_DCSZ_MASK 0xFF00u
7740 #define MSCM_CP0CFG0_DCSZ_SHIFT 8u
7741 #define MSCM_CP0CFG0_DCSZ_WIDTH 8u
7742 #define MSCM_CP0CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_DCSZ_SHIFT))&MSCM_CP0CFG0_DCSZ_MASK)
7743 #define MSCM_CP0CFG0_ICWY_MASK 0xFF0000u
7744 #define MSCM_CP0CFG0_ICWY_SHIFT 16u
7745 #define MSCM_CP0CFG0_ICWY_WIDTH 8u
7746 #define MSCM_CP0CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_ICWY_SHIFT))&MSCM_CP0CFG0_ICWY_MASK)
7747 #define MSCM_CP0CFG0_ICSZ_MASK 0xFF000000u
7748 #define MSCM_CP0CFG0_ICSZ_SHIFT 24u
7749 #define MSCM_CP0CFG0_ICSZ_WIDTH 8u
7750 #define MSCM_CP0CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_ICSZ_SHIFT))&MSCM_CP0CFG0_ICSZ_MASK)
7751 /* CP0CFG1 Bit Fields */
7752 #define MSCM_CP0CFG1_L2WY_MASK 0xFF0000u
7753 #define MSCM_CP0CFG1_L2WY_SHIFT 16u
7754 #define MSCM_CP0CFG1_L2WY_WIDTH 8u
7755 #define MSCM_CP0CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG1_L2WY_SHIFT))&MSCM_CP0CFG1_L2WY_MASK)
7756 #define MSCM_CP0CFG1_L2SZ_MASK 0xFF000000u
7757 #define MSCM_CP0CFG1_L2SZ_SHIFT 24u
7758 #define MSCM_CP0CFG1_L2SZ_WIDTH 8u
7759 #define MSCM_CP0CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG1_L2SZ_SHIFT))&MSCM_CP0CFG1_L2SZ_MASK)
7760 /* CP0CFG2 Bit Fields */
7761 #define MSCM_CP0CFG2_TMUSZ_MASK 0xFF00u
7762 #define MSCM_CP0CFG2_TMUSZ_SHIFT 8u
7763 #define MSCM_CP0CFG2_TMUSZ_WIDTH 8u
7764 #define MSCM_CP0CFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG2_TMUSZ_SHIFT))&MSCM_CP0CFG2_TMUSZ_MASK)
7765 #define MSCM_CP0CFG2_TMLSZ_MASK 0xFF000000u
7766 #define MSCM_CP0CFG2_TMLSZ_SHIFT 24u
7767 #define MSCM_CP0CFG2_TMLSZ_WIDTH 8u
7768 #define MSCM_CP0CFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG2_TMLSZ_SHIFT))&MSCM_CP0CFG2_TMLSZ_MASK)
7769 /* CP0CFG3 Bit Fields */
7770 #define MSCM_CP0CFG3_FPU_MASK 0x1u
7771 #define MSCM_CP0CFG3_FPU_SHIFT 0u
7772 #define MSCM_CP0CFG3_FPU_WIDTH 1u
7773 #define MSCM_CP0CFG3_FPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_FPU_SHIFT))&MSCM_CP0CFG3_FPU_MASK)
7774 #define MSCM_CP0CFG3_SIMD_MASK 0x2u
7775 #define MSCM_CP0CFG3_SIMD_SHIFT 1u
7776 #define MSCM_CP0CFG3_SIMD_WIDTH 1u
7777 #define MSCM_CP0CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_SIMD_SHIFT))&MSCM_CP0CFG3_SIMD_MASK)
7778 #define MSCM_CP0CFG3_JAZ_MASK 0x4u
7779 #define MSCM_CP0CFG3_JAZ_SHIFT 2u
7780 #define MSCM_CP0CFG3_JAZ_WIDTH 1u
7781 #define MSCM_CP0CFG3_JAZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_JAZ_SHIFT))&MSCM_CP0CFG3_JAZ_MASK)
7782 #define MSCM_CP0CFG3_MMU_MASK 0x8u
7783 #define MSCM_CP0CFG3_MMU_SHIFT 3u
7784 #define MSCM_CP0CFG3_MMU_WIDTH 1u
7785 #define MSCM_CP0CFG3_MMU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_MMU_SHIFT))&MSCM_CP0CFG3_MMU_MASK)
7786 #define MSCM_CP0CFG3_TZ_MASK 0x10u
7787 #define MSCM_CP0CFG3_TZ_SHIFT 4u
7788 #define MSCM_CP0CFG3_TZ_WIDTH 1u
7789 #define MSCM_CP0CFG3_TZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_TZ_SHIFT))&MSCM_CP0CFG3_TZ_MASK)
7790 #define MSCM_CP0CFG3_CMP_MASK 0x20u
7791 #define MSCM_CP0CFG3_CMP_SHIFT 5u
7792 #define MSCM_CP0CFG3_CMP_WIDTH 1u
7793 #define MSCM_CP0CFG3_CMP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_CMP_SHIFT))&MSCM_CP0CFG3_CMP_MASK)
7794 #define MSCM_CP0CFG3_BB_MASK 0x40u
7795 #define MSCM_CP0CFG3_BB_SHIFT 6u
7796 #define MSCM_CP0CFG3_BB_WIDTH 1u
7797 #define MSCM_CP0CFG3_BB(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_BB_SHIFT))&MSCM_CP0CFG3_BB_MASK)
7798 #define MSCM_CP0CFG3_SBP_MASK 0x300u
7799 #define MSCM_CP0CFG3_SBP_SHIFT 8u
7800 #define MSCM_CP0CFG3_SBP_WIDTH 2u
7801 #define MSCM_CP0CFG3_SBP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_SBP_SHIFT))&MSCM_CP0CFG3_SBP_MASK)
7802 /* OCMDR Bit Fields */
7803 #define MSCM_OCMDR_OCM1_MASK 0x30u
7804 #define MSCM_OCMDR_OCM1_SHIFT 4u
7805 #define MSCM_OCMDR_OCM1_WIDTH 2u
7806 #define MSCM_OCMDR_OCM1(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM1_SHIFT))&MSCM_OCMDR_OCM1_MASK)
7807 #define MSCM_OCMDR_OCMPU_MASK 0x1000u
7808 #define MSCM_OCMDR_OCMPU_SHIFT 12u
7809 #define MSCM_OCMDR_OCMPU_WIDTH 1u
7810 #define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMPU_SHIFT))&MSCM_OCMDR_OCMPU_MASK)
7811 #define MSCM_OCMDR_OCMT_MASK 0xE000u
7812 #define MSCM_OCMDR_OCMT_SHIFT 13u
7813 #define MSCM_OCMDR_OCMT_WIDTH 3u
7814 #define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMT_SHIFT))&MSCM_OCMDR_OCMT_MASK)
7815 #define MSCM_OCMDR_RO_MASK 0x10000u
7816 #define MSCM_OCMDR_RO_SHIFT 16u
7817 #define MSCM_OCMDR_RO_WIDTH 1u
7818 #define MSCM_OCMDR_RO(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_RO_SHIFT))&MSCM_OCMDR_RO_MASK)
7819 #define MSCM_OCMDR_OCMW_MASK 0xE0000u
7820 #define MSCM_OCMDR_OCMW_SHIFT 17u
7821 #define MSCM_OCMDR_OCMW_WIDTH 3u
7822 #define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMW_SHIFT))&MSCM_OCMDR_OCMW_MASK)
7823 #define MSCM_OCMDR_OCMSZ_MASK 0xF000000u
7824 #define MSCM_OCMDR_OCMSZ_SHIFT 24u
7825 #define MSCM_OCMDR_OCMSZ_WIDTH 4u
7826 #define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZ_SHIFT))&MSCM_OCMDR_OCMSZ_MASK)
7827 #define MSCM_OCMDR_OCMSZH_MASK 0x10000000u
7828 #define MSCM_OCMDR_OCMSZH_SHIFT 28u
7829 #define MSCM_OCMDR_OCMSZH_WIDTH 1u
7830 #define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZH_SHIFT))&MSCM_OCMDR_OCMSZH_MASK)
7831 #define MSCM_OCMDR_V_MASK 0x80000000u
7832 #define MSCM_OCMDR_V_SHIFT 31u
7833 #define MSCM_OCMDR_V_WIDTH 1u
7834 #define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_V_SHIFT))&MSCM_OCMDR_V_MASK)
7835  /* end of group MSCM_Register_Masks */
7839 
7840  /* end of group MSCM_Peripheral_Access_Layer */
7844 
7845 
7846 /* ----------------------------------------------------------------------------
7847  -- PCC Peripheral Access Layer
7848  ---------------------------------------------------------------------------- */
7849 
7857 #define PCC_PCCn_COUNT 116u
7858 
7860 typedef struct {
7861  __IO uint32_t PCCn[PCC_PCCn_COUNT];
7863 
7865 #define PCC_INSTANCE_COUNT (1u)
7866 
7867 
7868 /* PCC - Peripheral instance base addresses */
7870 #define PCC_BASE (0x40065000u)
7871 
7872 #define PCC ((PCC_Type *)PCC_BASE)
7873 
7874 #define PCC_BASE_ADDRS { PCC_BASE }
7875 
7876 #define PCC_BASE_PTRS { PCC }
7877 
7878 /* PCC index offsets */
7879 #define PCC_FTFC_INDEX 32
7880 #define PCC_DMAMUX_INDEX 33
7881 #define PCC_FlexCAN0_INDEX 36
7882 #define PCC_LPSPI0_INDEX 44
7883 #define PCC_LPSPI1_INDEX 45
7884 #define PCC_CRC_INDEX 50
7885 #define PCC_PDB0_INDEX 54
7886 #define PCC_LPIT_INDEX 55
7887 #define PCC_FTM0_INDEX 56
7888 #define PCC_FTM1_INDEX 57
7889 #define PCC_ADC0_INDEX 59
7890 #define PCC_RTC_INDEX 61
7891 #define PCC_CMU0_INDEX 62
7892 #define PCC_CMU1_INDEX 63
7893 #define PCC_LPTMR0_INDEX 64
7894 #define PCC_PORTA_INDEX 73
7895 #define PCC_PORTB_INDEX 74
7896 #define PCC_PORTC_INDEX 75
7897 #define PCC_PORTD_INDEX 76
7898 #define PCC_PORTE_INDEX 77
7899 #define PCC_FlexIO_INDEX 90
7900 #define PCC_LPI2C0_INDEX 102
7901 #define PCC_LPUART0_INDEX 106
7902 #define PCC_LPUART1_INDEX 107
7903 #define PCC_CMP0_INDEX 115
7904 
7905 /* ----------------------------------------------------------------------------
7906  -- PCC Register Masks
7907  ---------------------------------------------------------------------------- */
7908 
7914 /* PCCn Bit Fields */
7915 #define PCC_PCCn_PCD_MASK 0xFu
7916 #define PCC_PCCn_PCD_SHIFT 0u
7917 #define PCC_PCCn_PCD_WIDTH 4u
7918 #define PCC_PCCn_PCD(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PCD_SHIFT))&PCC_PCCn_PCD_MASK)
7919 #define PCC_PCCn_FRAC_MASK 0x10u
7920 #define PCC_PCCn_FRAC_SHIFT 4u
7921 #define PCC_PCCn_FRAC_WIDTH 1u
7922 #define PCC_PCCn_FRAC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_FRAC_SHIFT))&PCC_PCCn_FRAC_MASK)
7923 #define PCC_PCCn_PCS_MASK 0x7000000u
7924 #define PCC_PCCn_PCS_SHIFT 24u
7925 #define PCC_PCCn_PCS_WIDTH 3u
7926 #define PCC_PCCn_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PCS_SHIFT))&PCC_PCCn_PCS_MASK)
7927 #define PCC_PCCn_CGC_MASK 0x40000000u
7928 #define PCC_PCCn_CGC_SHIFT 30u
7929 #define PCC_PCCn_CGC_WIDTH 1u
7930 #define PCC_PCCn_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_CGC_SHIFT))&PCC_PCCn_CGC_MASK)
7931 #define PCC_PCCn_PR_MASK 0x80000000u
7932 #define PCC_PCCn_PR_SHIFT 31u
7933 #define PCC_PCCn_PR_WIDTH 1u
7934 #define PCC_PCCn_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PR_SHIFT))&PCC_PCCn_PR_MASK)
7935  /* end of group PCC_Register_Masks */
7939 
7940  /* end of group PCC_Peripheral_Access_Layer */
7944 
7945 
7946 /* ----------------------------------------------------------------------------
7947  -- PDB Peripheral Access Layer
7948  ---------------------------------------------------------------------------- */
7949 
7957 #define PDB_CH_COUNT 2u
7958 #define PDB_DLY_COUNT 8u
7959 #define PDB_POnDLY_COUNT 1u
7960 
7962 typedef struct {
7963  __IO uint32_t SC;
7964  __IO uint32_t MOD;
7965  __I uint32_t CNT;
7966  __IO uint32_t IDLY;
7967  struct { /* offset: 0x10, array step: 0x28 */
7968  __IO uint32_t C1;
7969  __IO uint32_t S;
7970  __IO uint32_t DLY[PDB_DLY_COUNT];
7971  } CH[PDB_CH_COUNT];
7972  uint8_t RESERVED_0[304];
7973  __IO uint32_t POEN;
7974  union { /* offset: 0x194, array step: 0x4 */
7975  __IO uint32_t PODLY;
7976  struct { /* offset: 0x194, array step: 0x4 */
7977  __IO uint16_t DLY2;
7978  __IO uint16_t DLY1;
7979  } ACCESS16BIT;
7980  } POnDLY[PDB_POnDLY_COUNT];
7982 
7984 #define PDB_INSTANCE_COUNT (1u)
7985 
7986 
7987 /* PDB - Peripheral instance base addresses */
7989 #define PDB0_BASE (0x40036000u)
7990 
7991 #define PDB0 ((PDB_Type *)PDB0_BASE)
7992 
7993 #define PDB_BASE_ADDRS { PDB0_BASE }
7994 
7995 #define PDB_BASE_PTRS { PDB0 }
7996 
7997 #define PDB_IRQS_ARR_COUNT (1u)
7998 
7999 #define PDB_IRQS_CH_COUNT (1u)
8000 
8001 #define PDB_IRQS { PDB0_IRQn }
8002 
8003 /* ----------------------------------------------------------------------------
8004  -- PDB Register Masks
8005  ---------------------------------------------------------------------------- */
8006 
8012 /* SC Bit Fields */
8013 #define PDB_SC_LDOK_MASK 0x1u
8014 #define PDB_SC_LDOK_SHIFT 0u
8015 #define PDB_SC_LDOK_WIDTH 1u
8016 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
8017 #define PDB_SC_CONT_MASK 0x2u
8018 #define PDB_SC_CONT_SHIFT 1u
8019 #define PDB_SC_CONT_WIDTH 1u
8020 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
8021 #define PDB_SC_MULT_MASK 0xCu
8022 #define PDB_SC_MULT_SHIFT 2u
8023 #define PDB_SC_MULT_WIDTH 2u
8024 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
8025 #define PDB_SC_PDBIE_MASK 0x20u
8026 #define PDB_SC_PDBIE_SHIFT 5u
8027 #define PDB_SC_PDBIE_WIDTH 1u
8028 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
8029 #define PDB_SC_PDBIF_MASK 0x40u
8030 #define PDB_SC_PDBIF_SHIFT 6u
8031 #define PDB_SC_PDBIF_WIDTH 1u
8032 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
8033 #define PDB_SC_PDBEN_MASK 0x80u
8034 #define PDB_SC_PDBEN_SHIFT 7u
8035 #define PDB_SC_PDBEN_WIDTH 1u
8036 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
8037 #define PDB_SC_TRGSEL_MASK 0xF00u
8038 #define PDB_SC_TRGSEL_SHIFT 8u
8039 #define PDB_SC_TRGSEL_WIDTH 4u
8040 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
8041 #define PDB_SC_PRESCALER_MASK 0x7000u
8042 #define PDB_SC_PRESCALER_SHIFT 12u
8043 #define PDB_SC_PRESCALER_WIDTH 3u
8044 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
8045 #define PDB_SC_DMAEN_MASK 0x8000u
8046 #define PDB_SC_DMAEN_SHIFT 15u
8047 #define PDB_SC_DMAEN_WIDTH 1u
8048 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
8049 #define PDB_SC_SWTRIG_MASK 0x10000u
8050 #define PDB_SC_SWTRIG_SHIFT 16u
8051 #define PDB_SC_SWTRIG_WIDTH 1u
8052 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
8053 #define PDB_SC_PDBEIE_MASK 0x20000u
8054 #define PDB_SC_PDBEIE_SHIFT 17u
8055 #define PDB_SC_PDBEIE_WIDTH 1u
8056 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
8057 #define PDB_SC_LDMOD_MASK 0xC0000u
8058 #define PDB_SC_LDMOD_SHIFT 18u
8059 #define PDB_SC_LDMOD_WIDTH 2u
8060 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
8061 /* MOD Bit Fields */
8062 #define PDB_MOD_MOD_MASK 0xFFFFu
8063 #define PDB_MOD_MOD_SHIFT 0u
8064 #define PDB_MOD_MOD_WIDTH 16u
8065 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
8066 /* CNT Bit Fields */
8067 #define PDB_CNT_CNT_MASK 0xFFFFu
8068 #define PDB_CNT_CNT_SHIFT 0u
8069 #define PDB_CNT_CNT_WIDTH 16u
8070 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
8071 /* IDLY Bit Fields */
8072 #define PDB_IDLY_IDLY_MASK 0xFFFFu
8073 #define PDB_IDLY_IDLY_SHIFT 0u
8074 #define PDB_IDLY_IDLY_WIDTH 16u
8075 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
8076 /* C1 Bit Fields */
8077 #define PDB_C1_EN_MASK 0xFFu
8078 #define PDB_C1_EN_SHIFT 0u
8079 #define PDB_C1_EN_WIDTH 8u
8080 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
8081 #define PDB_C1_TOS_MASK 0xFF00u
8082 #define PDB_C1_TOS_SHIFT 8u
8083 #define PDB_C1_TOS_WIDTH 8u
8084 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
8085 #define PDB_C1_BB_MASK 0xFF0000u
8086 #define PDB_C1_BB_SHIFT 16u
8087 #define PDB_C1_BB_WIDTH 8u
8088 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
8089 /* S Bit Fields */
8090 #define PDB_S_ERR_MASK 0xFFu
8091 #define PDB_S_ERR_SHIFT 0u
8092 #define PDB_S_ERR_WIDTH 8u
8093 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
8094 #define PDB_S_CF_MASK 0xFF0000u
8095 #define PDB_S_CF_SHIFT 16u
8096 #define PDB_S_CF_WIDTH 8u
8097 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
8098 /* DLY Bit Fields */
8099 #define PDB_DLY_DLY_MASK 0xFFFFu
8100 #define PDB_DLY_DLY_SHIFT 0u
8101 #define PDB_DLY_DLY_WIDTH 16u
8102 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
8103 /* POEN Bit Fields */
8104 #define PDB_POEN_POEN_MASK 0xFFu
8105 #define PDB_POEN_POEN_SHIFT 0u
8106 #define PDB_POEN_POEN_WIDTH 8u
8107 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
8108 /* POnDLY_PODLY Bit Fields */
8109 #define PDB_POnDLY_PODLY_DLY2_MASK 0xFFFFu
8110 #define PDB_POnDLY_PODLY_DLY2_SHIFT 0u
8111 #define PDB_POnDLY_PODLY_DLY2_WIDTH 16u
8112 #define PDB_POnDLY_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_POnDLY_PODLY_DLY2_SHIFT))&PDB_POnDLY_PODLY_DLY2_MASK)
8113 #define PDB_POnDLY_PODLY_DLY1_MASK 0xFFFF0000u
8114 #define PDB_POnDLY_PODLY_DLY1_SHIFT 16u
8115 #define PDB_POnDLY_PODLY_DLY1_WIDTH 16u
8116 #define PDB_POnDLY_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_POnDLY_PODLY_DLY1_SHIFT))&PDB_POnDLY_PODLY_DLY1_MASK)
8117 /* POnDLY_ACCESS16BIT_DLY2 Bit Fields */
8118 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK 0xFFFFu
8119 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT 0u
8120 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_WIDTH 16u
8121 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2(x) (((uint16_t)(((uint16_t)(x))<<PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT))&PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK)
8122 /* POnDLY_ACCESS16BIT_DLY1 Bit Fields */
8123 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK 0xFFFFu
8124 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT 0u
8125 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_WIDTH 16u
8126 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1(x) (((uint16_t)(((uint16_t)(x))<<PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT))&PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK)
8127  /* end of group PDB_Register_Masks */
8131 
8132  /* end of group PDB_Peripheral_Access_Layer */
8136 
8137 
8138 /* ----------------------------------------------------------------------------
8139  -- PMC Peripheral Access Layer
8140  ---------------------------------------------------------------------------- */
8141 
8151 typedef struct {
8152  __IO uint8_t LVDSC1;
8153  __IO uint8_t LVDSC2;
8154  __IO uint8_t REGSC;
8155  uint8_t RESERVED_0[1];
8156  __IO uint8_t LPOTRIM;
8158 
8160 #define PMC_INSTANCE_COUNT (1u)
8161 
8162 
8163 /* PMC - Peripheral instance base addresses */
8165 #define PMC_BASE (0x4007D000u)
8166 
8167 #define PMC ((PMC_Type *)PMC_BASE)
8168 
8169 #define PMC_BASE_ADDRS { PMC_BASE }
8170 
8171 #define PMC_BASE_PTRS { PMC }
8172 
8173 #define PMC_IRQS_ARR_COUNT (1u)
8174 
8175 #define PMC_IRQS_CH_COUNT (1u)
8176 
8177 #define PMC_IRQS { SCG_CMU_LVD_LVWSCG_IRQn }
8178 
8179 /* ----------------------------------------------------------------------------
8180  -- PMC Register Masks
8181  ---------------------------------------------------------------------------- */
8182 
8188 /* LVDSC1 Bit Fields */
8189 #define PMC_LVDSC1_LVDRE_MASK 0x10u
8190 #define PMC_LVDSC1_LVDRE_SHIFT 4u
8191 #define PMC_LVDSC1_LVDRE_WIDTH 1u
8192 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
8193 #define PMC_LVDSC1_LVDIE_MASK 0x20u
8194 #define PMC_LVDSC1_LVDIE_SHIFT 5u
8195 #define PMC_LVDSC1_LVDIE_WIDTH 1u
8196 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
8197 #define PMC_LVDSC1_LVDACK_MASK 0x40u
8198 #define PMC_LVDSC1_LVDACK_SHIFT 6u
8199 #define PMC_LVDSC1_LVDACK_WIDTH 1u
8200 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
8201 #define PMC_LVDSC1_LVDF_MASK 0x80u
8202 #define PMC_LVDSC1_LVDF_SHIFT 7u
8203 #define PMC_LVDSC1_LVDF_WIDTH 1u
8204 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
8205 /* LVDSC2 Bit Fields */
8206 #define PMC_LVDSC2_LVWIE_MASK 0x20u
8207 #define PMC_LVDSC2_LVWIE_SHIFT 5u
8208 #define PMC_LVDSC2_LVWIE_WIDTH 1u
8209 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
8210 #define PMC_LVDSC2_LVWACK_MASK 0x40u
8211 #define PMC_LVDSC2_LVWACK_SHIFT 6u
8212 #define PMC_LVDSC2_LVWACK_WIDTH 1u
8213 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
8214 #define PMC_LVDSC2_LVWF_MASK 0x80u
8215 #define PMC_LVDSC2_LVWF_SHIFT 7u
8216 #define PMC_LVDSC2_LVWF_WIDTH 1u
8217 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
8218 /* REGSC Bit Fields */
8219 #define PMC_REGSC_BIASEN_MASK 0x1u
8220 #define PMC_REGSC_BIASEN_SHIFT 0u
8221 #define PMC_REGSC_BIASEN_WIDTH 1u
8222 #define PMC_REGSC_BIASEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BIASEN_SHIFT))&PMC_REGSC_BIASEN_MASK)
8223 #define PMC_REGSC_CLKBIASDIS_MASK 0x2u
8224 #define PMC_REGSC_CLKBIASDIS_SHIFT 1u
8225 #define PMC_REGSC_CLKBIASDIS_WIDTH 1u
8226 #define PMC_REGSC_CLKBIASDIS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_CLKBIASDIS_SHIFT))&PMC_REGSC_CLKBIASDIS_MASK)
8227 #define PMC_REGSC_REGFPM_MASK 0x4u
8228 #define PMC_REGSC_REGFPM_SHIFT 2u
8229 #define PMC_REGSC_REGFPM_WIDTH 1u
8230 #define PMC_REGSC_REGFPM(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGFPM_SHIFT))&PMC_REGSC_REGFPM_MASK)
8231 #define PMC_REGSC_LPOSTAT_MASK 0x40u
8232 #define PMC_REGSC_LPOSTAT_SHIFT 6u
8233 #define PMC_REGSC_LPOSTAT_WIDTH 1u
8234 #define PMC_REGSC_LPOSTAT(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_LPOSTAT_SHIFT))&PMC_REGSC_LPOSTAT_MASK)
8235 #define PMC_REGSC_LPODIS_MASK 0x80u
8236 #define PMC_REGSC_LPODIS_SHIFT 7u
8237 #define PMC_REGSC_LPODIS_WIDTH 1u
8238 #define PMC_REGSC_LPODIS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_LPODIS_SHIFT))&PMC_REGSC_LPODIS_MASK)
8239 /* LPOTRIM Bit Fields */
8240 #define PMC_LPOTRIM_LPOTRIM_MASK 0x1Fu
8241 #define PMC_LPOTRIM_LPOTRIM_SHIFT 0u
8242 #define PMC_LPOTRIM_LPOTRIM_WIDTH 5u
8243 #define PMC_LPOTRIM_LPOTRIM(x) (((uint8_t)(((uint8_t)(x))<<PMC_LPOTRIM_LPOTRIM_SHIFT))&PMC_LPOTRIM_LPOTRIM_MASK)
8244  /* end of group PMC_Register_Masks */
8248 
8249  /* end of group PMC_Peripheral_Access_Layer */
8253 
8254 
8255 /* ----------------------------------------------------------------------------
8256  -- PORT Peripheral Access Layer
8257  ---------------------------------------------------------------------------- */
8258 
8266 #define PORT_PCR_COUNT 32u
8267 
8269 typedef struct {
8270  __IO uint32_t PCR[PORT_PCR_COUNT];
8271  __O uint32_t GPCLR;
8272  __O uint32_t GPCHR;
8273  __O uint32_t GICLR;
8274  __O uint32_t GICHR;
8275  uint8_t RESERVED_0[16];
8276  __IO uint32_t ISFR;
8277  uint8_t RESERVED_1[28];
8278  __IO uint32_t DFER;
8279  __IO uint32_t DFCR;
8280  __IO uint32_t DFWR;
8282 
8284 #define PORT_INSTANCE_COUNT (5u)
8285 
8286 
8287 /* PORT - Peripheral instance base addresses */
8289 #define PORTA_BASE (0x40049000u)
8290 
8291 #define PORTA ((PORT_Type *)PORTA_BASE)
8292 
8293 #define PORTB_BASE (0x4004A000u)
8294 
8295 #define PORTB ((PORT_Type *)PORTB_BASE)
8296 
8297 #define PORTC_BASE (0x4004B000u)
8298 
8299 #define PORTC ((PORT_Type *)PORTC_BASE)
8300 
8301 #define PORTD_BASE (0x4004C000u)
8302 
8303 #define PORTD ((PORT_Type *)PORTD_BASE)
8304 
8305 #define PORTE_BASE (0x4004D000u)
8306 
8307 #define PORTE ((PORT_Type *)PORTE_BASE)
8308 
8309 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
8310 
8311 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
8312 
8313 #define PORT_IRQS_ARR_COUNT (1u)
8314 
8315 #define PORT_IRQS_CH_COUNT (1u)
8316 
8317 #define PORT_IRQS { PORT_IRQn, PORT_IRQn, PORT_IRQn, PORT_IRQn, PORT_IRQn }
8318 
8319 /* ----------------------------------------------------------------------------
8320  -- PORT Register Masks
8321  ---------------------------------------------------------------------------- */
8322 
8328 /* PCR Bit Fields */
8329 #define PORT_PCR_PS_MASK 0x1u
8330 #define PORT_PCR_PS_SHIFT 0u
8331 #define PORT_PCR_PS_WIDTH 1u
8332 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
8333 #define PORT_PCR_PE_MASK 0x2u
8334 #define PORT_PCR_PE_SHIFT 1u
8335 #define PORT_PCR_PE_WIDTH 1u
8336 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
8337 #define PORT_PCR_PFE_MASK 0x10u
8338 #define PORT_PCR_PFE_SHIFT 4u
8339 #define PORT_PCR_PFE_WIDTH 1u
8340 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
8341 #define PORT_PCR_DSE_MASK 0x40u
8342 #define PORT_PCR_DSE_SHIFT 6u
8343 #define PORT_PCR_DSE_WIDTH 1u
8344 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
8345 #define PORT_PCR_MUX_MASK 0x700u
8346 #define PORT_PCR_MUX_SHIFT 8u
8347 #define PORT_PCR_MUX_WIDTH 3u
8348 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
8349 #define PORT_PCR_LK_MASK 0x8000u
8350 #define PORT_PCR_LK_SHIFT 15u
8351 #define PORT_PCR_LK_WIDTH 1u
8352 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
8353 #define PORT_PCR_IRQC_MASK 0xF0000u
8354 #define PORT_PCR_IRQC_SHIFT 16u
8355 #define PORT_PCR_IRQC_WIDTH 4u
8356 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
8357 #define PORT_PCR_ISF_MASK 0x1000000u
8358 #define PORT_PCR_ISF_SHIFT 24u
8359 #define PORT_PCR_ISF_WIDTH 1u
8360 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
8361 /* GPCLR Bit Fields */
8362 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
8363 #define PORT_GPCLR_GPWD_SHIFT 0u
8364 #define PORT_GPCLR_GPWD_WIDTH 16u
8365 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
8366 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
8367 #define PORT_GPCLR_GPWE_SHIFT 16u
8368 #define PORT_GPCLR_GPWE_WIDTH 16u
8369 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
8370 /* GPCHR Bit Fields */
8371 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
8372 #define PORT_GPCHR_GPWD_SHIFT 0u
8373 #define PORT_GPCHR_GPWD_WIDTH 16u
8374 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
8375 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
8376 #define PORT_GPCHR_GPWE_SHIFT 16u
8377 #define PORT_GPCHR_GPWE_WIDTH 16u
8378 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
8379 /* GICLR Bit Fields */
8380 #define PORT_GICLR_GIWE_MASK 0xFFFFu
8381 #define PORT_GICLR_GIWE_SHIFT 0u
8382 #define PORT_GICLR_GIWE_WIDTH 16u
8383 #define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWE_SHIFT))&PORT_GICLR_GIWE_MASK)
8384 #define PORT_GICLR_GIWD_MASK 0xFFFF0000u
8385 #define PORT_GICLR_GIWD_SHIFT 16u
8386 #define PORT_GICLR_GIWD_WIDTH 16u
8387 #define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICLR_GIWD_SHIFT))&PORT_GICLR_GIWD_MASK)
8388 /* GICHR Bit Fields */
8389 #define PORT_GICHR_GIWE_MASK 0xFFFFu
8390 #define PORT_GICHR_GIWE_SHIFT 0u
8391 #define PORT_GICHR_GIWE_WIDTH 16u
8392 #define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWE_SHIFT))&PORT_GICHR_GIWE_MASK)
8393 #define PORT_GICHR_GIWD_MASK 0xFFFF0000u
8394 #define PORT_GICHR_GIWD_SHIFT 16u
8395 #define PORT_GICHR_GIWD_WIDTH 16u
8396 #define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GICHR_GIWD_SHIFT))&PORT_GICHR_GIWD_MASK)
8397 /* ISFR Bit Fields */
8398 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
8399 #define PORT_ISFR_ISF_SHIFT 0u
8400 #define PORT_ISFR_ISF_WIDTH 32u
8401 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
8402 /* DFER Bit Fields */
8403 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
8404 #define PORT_DFER_DFE_SHIFT 0u
8405 #define PORT_DFER_DFE_WIDTH 32u
8406 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
8407 /* DFCR Bit Fields */
8408 #define PORT_DFCR_CS_MASK 0x1u
8409 #define PORT_DFCR_CS_SHIFT 0u
8410 #define PORT_DFCR_CS_WIDTH 1u
8411 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
8412 /* DFWR Bit Fields */
8413 #define PORT_DFWR_FILT_MASK 0x1Fu
8414 #define PORT_DFWR_FILT_SHIFT 0u
8415 #define PORT_DFWR_FILT_WIDTH 5u
8416 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
8417  /* end of group PORT_Register_Masks */
8421 
8422  /* end of group PORT_Peripheral_Access_Layer */
8426 
8427 
8428 /* ----------------------------------------------------------------------------
8429  -- RCM Peripheral Access Layer
8430  ---------------------------------------------------------------------------- */
8431 
8441 typedef struct {
8442  __I uint32_t VERID;
8443  __I uint32_t PARAM;
8444  __I uint32_t SRS;
8445  __IO uint32_t RPC;
8446  uint8_t RESERVED_0[8];
8447  __IO uint32_t SSRS;
8448  __IO uint32_t SRIE;
8450 
8452 #define RCM_INSTANCE_COUNT (1u)
8453 
8454 
8455 /* RCM - Peripheral instance base addresses */
8457 #define RCM_BASE (0x4007F000u)
8458 
8459 #define RCM ((RCM_Type *)RCM_BASE)
8460 
8461 #define RCM_BASE_ADDRS { RCM_BASE }
8462 
8463 #define RCM_BASE_PTRS { RCM }
8464 
8465 #define RCM_IRQS_ARR_COUNT (1u)
8466 
8467 #define RCM_IRQS_CH_COUNT (1u)
8468 
8469 #define RCM_IRQS { RCM_IRQn }
8470 
8471 /* ----------------------------------------------------------------------------
8472  -- RCM Register Masks
8473  ---------------------------------------------------------------------------- */
8474 
8480 /* VERID Bit Fields */
8481 #define RCM_VERID_FEATURE_MASK 0xFFFFu
8482 #define RCM_VERID_FEATURE_SHIFT 0u
8483 #define RCM_VERID_FEATURE_WIDTH 16u
8484 #define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_FEATURE_SHIFT))&RCM_VERID_FEATURE_MASK)
8485 #define RCM_VERID_MINOR_MASK 0xFF0000u
8486 #define RCM_VERID_MINOR_SHIFT 16u
8487 #define RCM_VERID_MINOR_WIDTH 8u
8488 #define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MINOR_SHIFT))&RCM_VERID_MINOR_MASK)
8489 #define RCM_VERID_MAJOR_MASK 0xFF000000u
8490 #define RCM_VERID_MAJOR_SHIFT 24u
8491 #define RCM_VERID_MAJOR_WIDTH 8u
8492 #define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MAJOR_SHIFT))&RCM_VERID_MAJOR_MASK)
8493 /* PARAM Bit Fields */
8494 #define RCM_PARAM_EWAKEUP_MASK 0x1u
8495 #define RCM_PARAM_EWAKEUP_SHIFT 0u
8496 #define RCM_PARAM_EWAKEUP_WIDTH 1u
8497 #define RCM_PARAM_EWAKEUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EWAKEUP_SHIFT))&RCM_PARAM_EWAKEUP_MASK)
8498 #define RCM_PARAM_ELVD_MASK 0x2u
8499 #define RCM_PARAM_ELVD_SHIFT 1u
8500 #define RCM_PARAM_ELVD_WIDTH 1u
8501 #define RCM_PARAM_ELVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELVD_SHIFT))&RCM_PARAM_ELVD_MASK)
8502 #define RCM_PARAM_ELOC_MASK 0x4u
8503 #define RCM_PARAM_ELOC_SHIFT 2u
8504 #define RCM_PARAM_ELOC_WIDTH 1u
8505 #define RCM_PARAM_ELOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOC_SHIFT))&RCM_PARAM_ELOC_MASK)
8506 #define RCM_PARAM_ELOL_MASK 0x8u
8507 #define RCM_PARAM_ELOL_SHIFT 3u
8508 #define RCM_PARAM_ELOL_WIDTH 1u
8509 #define RCM_PARAM_ELOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOL_SHIFT))&RCM_PARAM_ELOL_MASK)
8510 #define RCM_PARAM_ECMU_LOC_MASK 0x10u
8511 #define RCM_PARAM_ECMU_LOC_SHIFT 4u
8512 #define RCM_PARAM_ECMU_LOC_WIDTH 1u
8513 #define RCM_PARAM_ECMU_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ECMU_LOC_SHIFT))&RCM_PARAM_ECMU_LOC_MASK)
8514 #define RCM_PARAM_EWDOG_MASK 0x20u
8515 #define RCM_PARAM_EWDOG_SHIFT 5u
8516 #define RCM_PARAM_EWDOG_WIDTH 1u
8517 #define RCM_PARAM_EWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EWDOG_SHIFT))&RCM_PARAM_EWDOG_MASK)
8518 #define RCM_PARAM_EPIN_MASK 0x40u
8519 #define RCM_PARAM_EPIN_SHIFT 6u
8520 #define RCM_PARAM_EPIN_WIDTH 1u
8521 #define RCM_PARAM_EPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EPIN_SHIFT))&RCM_PARAM_EPIN_MASK)
8522 #define RCM_PARAM_EPOR_MASK 0x80u
8523 #define RCM_PARAM_EPOR_SHIFT 7u
8524 #define RCM_PARAM_EPOR_WIDTH 1u
8525 #define RCM_PARAM_EPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EPOR_SHIFT))&RCM_PARAM_EPOR_MASK)
8526 #define RCM_PARAM_EJTAG_MASK 0x100u
8527 #define RCM_PARAM_EJTAG_SHIFT 8u
8528 #define RCM_PARAM_EJTAG_WIDTH 1u
8529 #define RCM_PARAM_EJTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EJTAG_SHIFT))&RCM_PARAM_EJTAG_MASK)
8530 #define RCM_PARAM_ELOCKUP_MASK 0x200u
8531 #define RCM_PARAM_ELOCKUP_SHIFT 9u
8532 #define RCM_PARAM_ELOCKUP_WIDTH 1u
8533 #define RCM_PARAM_ELOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOCKUP_SHIFT))&RCM_PARAM_ELOCKUP_MASK)
8534 #define RCM_PARAM_ESW_MASK 0x400u
8535 #define RCM_PARAM_ESW_SHIFT 10u
8536 #define RCM_PARAM_ESW_WIDTH 1u
8537 #define RCM_PARAM_ESW(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ESW_SHIFT))&RCM_PARAM_ESW_MASK)
8538 #define RCM_PARAM_EMDM_AP_MASK 0x800u
8539 #define RCM_PARAM_EMDM_AP_SHIFT 11u
8540 #define RCM_PARAM_EMDM_AP_WIDTH 1u
8541 #define RCM_PARAM_EMDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EMDM_AP_SHIFT))&RCM_PARAM_EMDM_AP_MASK)
8542 #define RCM_PARAM_ESACKERR_MASK 0x2000u
8543 #define RCM_PARAM_ESACKERR_SHIFT 13u
8544 #define RCM_PARAM_ESACKERR_WIDTH 1u
8545 #define RCM_PARAM_ESACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ESACKERR_SHIFT))&RCM_PARAM_ESACKERR_MASK)
8546 #define RCM_PARAM_ETAMPER_MASK 0x8000u
8547 #define RCM_PARAM_ETAMPER_SHIFT 15u
8548 #define RCM_PARAM_ETAMPER_WIDTH 1u
8549 #define RCM_PARAM_ETAMPER(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ETAMPER_SHIFT))&RCM_PARAM_ETAMPER_MASK)
8550 #define RCM_PARAM_ECORE1_MASK 0x10000u
8551 #define RCM_PARAM_ECORE1_SHIFT 16u
8552 #define RCM_PARAM_ECORE1_WIDTH 1u
8553 #define RCM_PARAM_ECORE1(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ECORE1_SHIFT))&RCM_PARAM_ECORE1_MASK)
8554 /* SRS Bit Fields */
8555 #define RCM_SRS_LVD_MASK 0x2u
8556 #define RCM_SRS_LVD_SHIFT 1u
8557 #define RCM_SRS_LVD_WIDTH 1u
8558 #define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LVD_SHIFT))&RCM_SRS_LVD_MASK)
8559 #define RCM_SRS_LOC_MASK 0x4u
8560 #define RCM_SRS_LOC_SHIFT 2u
8561 #define RCM_SRS_LOC_WIDTH 1u
8562 #define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOC_SHIFT))&RCM_SRS_LOC_MASK)
8563 #define RCM_SRS_LOL_MASK 0x8u
8564 #define RCM_SRS_LOL_SHIFT 3u
8565 #define RCM_SRS_LOL_WIDTH 1u
8566 #define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOL_SHIFT))&RCM_SRS_LOL_MASK)
8567 #define RCM_SRS_CMU_LOC_MASK 0x10u
8568 #define RCM_SRS_CMU_LOC_SHIFT 4u
8569 #define RCM_SRS_CMU_LOC_WIDTH 1u
8570 #define RCM_SRS_CMU_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_CMU_LOC_SHIFT))&RCM_SRS_CMU_LOC_MASK)
8571 #define RCM_SRS_WDOG_MASK 0x20u
8572 #define RCM_SRS_WDOG_SHIFT 5u
8573 #define RCM_SRS_WDOG_WIDTH 1u
8574 #define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_WDOG_SHIFT))&RCM_SRS_WDOG_MASK)
8575 #define RCM_SRS_PIN_MASK 0x40u
8576 #define RCM_SRS_PIN_SHIFT 6u
8577 #define RCM_SRS_PIN_WIDTH 1u
8578 #define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_PIN_SHIFT))&RCM_SRS_PIN_MASK)
8579 #define RCM_SRS_POR_MASK 0x80u
8580 #define RCM_SRS_POR_SHIFT 7u
8581 #define RCM_SRS_POR_WIDTH 1u
8582 #define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_POR_SHIFT))&RCM_SRS_POR_MASK)
8583 #define RCM_SRS_JTAG_MASK 0x100u
8584 #define RCM_SRS_JTAG_SHIFT 8u
8585 #define RCM_SRS_JTAG_WIDTH 1u
8586 #define RCM_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_JTAG_SHIFT))&RCM_SRS_JTAG_MASK)
8587 #define RCM_SRS_LOCKUP_MASK 0x200u
8588 #define RCM_SRS_LOCKUP_SHIFT 9u
8589 #define RCM_SRS_LOCKUP_WIDTH 1u
8590 #define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOCKUP_SHIFT))&RCM_SRS_LOCKUP_MASK)
8591 #define RCM_SRS_SW_MASK 0x400u
8592 #define RCM_SRS_SW_SHIFT 10u
8593 #define RCM_SRS_SW_WIDTH 1u
8594 #define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SW_SHIFT))&RCM_SRS_SW_MASK)
8595 #define RCM_SRS_MDM_AP_MASK 0x800u
8596 #define RCM_SRS_MDM_AP_SHIFT 11u
8597 #define RCM_SRS_MDM_AP_WIDTH 1u
8598 #define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_MDM_AP_SHIFT))&RCM_SRS_MDM_AP_MASK)
8599 #define RCM_SRS_SACKERR_MASK 0x2000u
8600 #define RCM_SRS_SACKERR_SHIFT 13u
8601 #define RCM_SRS_SACKERR_WIDTH 1u
8602 #define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SACKERR_SHIFT))&RCM_SRS_SACKERR_MASK)
8603 /* RPC Bit Fields */
8604 #define RCM_RPC_RSTFLTSRW_MASK 0x3u
8605 #define RCM_RPC_RSTFLTSRW_SHIFT 0u
8606 #define RCM_RPC_RSTFLTSRW_WIDTH 2u
8607 #define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSRW_SHIFT))&RCM_RPC_RSTFLTSRW_MASK)
8608 #define RCM_RPC_RSTFLTSS_MASK 0x4u
8609 #define RCM_RPC_RSTFLTSS_SHIFT 2u
8610 #define RCM_RPC_RSTFLTSS_WIDTH 1u
8611 #define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSS_SHIFT))&RCM_RPC_RSTFLTSS_MASK)
8612 #define RCM_RPC_RSTFLTSEL_MASK 0x1F00u
8613 #define RCM_RPC_RSTFLTSEL_SHIFT 8u
8614 #define RCM_RPC_RSTFLTSEL_WIDTH 5u
8615 #define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSEL_SHIFT))&RCM_RPC_RSTFLTSEL_MASK)
8616 /* SSRS Bit Fields */
8617 #define RCM_SSRS_SLVD_MASK 0x2u
8618 #define RCM_SSRS_SLVD_SHIFT 1u
8619 #define RCM_SSRS_SLVD_WIDTH 1u
8620 #define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLVD_SHIFT))&RCM_SSRS_SLVD_MASK)
8621 #define RCM_SSRS_SLOC_MASK 0x4u
8622 #define RCM_SSRS_SLOC_SHIFT 2u
8623 #define RCM_SSRS_SLOC_WIDTH 1u
8624 #define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOC_SHIFT))&RCM_SSRS_SLOC_MASK)
8625 #define RCM_SSRS_SLOL_MASK 0x8u
8626 #define RCM_SSRS_SLOL_SHIFT 3u
8627 #define RCM_SSRS_SLOL_WIDTH 1u
8628 #define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOL_SHIFT))&RCM_SSRS_SLOL_MASK)
8629 #define RCM_SSRS_SCMU_LOC_MASK 0x10u
8630 #define RCM_SSRS_SCMU_LOC_SHIFT 4u
8631 #define RCM_SSRS_SCMU_LOC_WIDTH 1u
8632 #define RCM_SSRS_SCMU_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SCMU_LOC_SHIFT))&RCM_SSRS_SCMU_LOC_MASK)
8633 #define RCM_SSRS_SWDOG_MASK 0x20u
8634 #define RCM_SSRS_SWDOG_SHIFT 5u
8635 #define RCM_SSRS_SWDOG_WIDTH 1u
8636 #define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SWDOG_SHIFT))&RCM_SSRS_SWDOG_MASK)
8637 #define RCM_SSRS_SPIN_MASK 0x40u
8638 #define RCM_SSRS_SPIN_SHIFT 6u
8639 #define RCM_SSRS_SPIN_WIDTH 1u
8640 #define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPIN_SHIFT))&RCM_SSRS_SPIN_MASK)
8641 #define RCM_SSRS_SPOR_MASK 0x80u
8642 #define RCM_SSRS_SPOR_SHIFT 7u
8643 #define RCM_SSRS_SPOR_WIDTH 1u
8644 #define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPOR_SHIFT))&RCM_SSRS_SPOR_MASK)
8645 #define RCM_SSRS_SJTAG_MASK 0x100u
8646 #define RCM_SSRS_SJTAG_SHIFT 8u
8647 #define RCM_SSRS_SJTAG_WIDTH 1u
8648 #define RCM_SSRS_SJTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SJTAG_SHIFT))&RCM_SSRS_SJTAG_MASK)
8649 #define RCM_SSRS_SLOCKUP_MASK 0x200u
8650 #define RCM_SSRS_SLOCKUP_SHIFT 9u
8651 #define RCM_SSRS_SLOCKUP_WIDTH 1u
8652 #define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOCKUP_SHIFT))&RCM_SSRS_SLOCKUP_MASK)
8653 #define RCM_SSRS_SSW_MASK 0x400u
8654 #define RCM_SSRS_SSW_SHIFT 10u
8655 #define RCM_SSRS_SSW_WIDTH 1u
8656 #define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSW_SHIFT))&RCM_SSRS_SSW_MASK)
8657 #define RCM_SSRS_SMDM_AP_MASK 0x800u
8658 #define RCM_SSRS_SMDM_AP_SHIFT 11u
8659 #define RCM_SSRS_SMDM_AP_WIDTH 1u
8660 #define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SMDM_AP_SHIFT))&RCM_SSRS_SMDM_AP_MASK)
8661 #define RCM_SSRS_SSACKERR_MASK 0x2000u
8662 #define RCM_SSRS_SSACKERR_SHIFT 13u
8663 #define RCM_SSRS_SSACKERR_WIDTH 1u
8664 #define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSACKERR_SHIFT))&RCM_SSRS_SSACKERR_MASK)
8665 /* SRIE Bit Fields */
8666 #define RCM_SRIE_DELAY_MASK 0x3u
8667 #define RCM_SRIE_DELAY_SHIFT 0u
8668 #define RCM_SRIE_DELAY_WIDTH 2u
8669 #define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_DELAY_SHIFT))&RCM_SRIE_DELAY_MASK)
8670 #define RCM_SRIE_LOC_MASK 0x4u
8671 #define RCM_SRIE_LOC_SHIFT 2u
8672 #define RCM_SRIE_LOC_WIDTH 1u
8673 #define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOC_SHIFT))&RCM_SRIE_LOC_MASK)
8674 #define RCM_SRIE_LOL_MASK 0x8u
8675 #define RCM_SRIE_LOL_SHIFT 3u
8676 #define RCM_SRIE_LOL_WIDTH 1u
8677 #define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOL_SHIFT))&RCM_SRIE_LOL_MASK)
8678 #define RCM_SRIE_CMU_LOC_MASK 0x10u
8679 #define RCM_SRIE_CMU_LOC_SHIFT 4u
8680 #define RCM_SRIE_CMU_LOC_WIDTH 1u
8681 #define RCM_SRIE_CMU_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_CMU_LOC_SHIFT))&RCM_SRIE_CMU_LOC_MASK)
8682 #define RCM_SRIE_WDOG_MASK 0x20u
8683 #define RCM_SRIE_WDOG_SHIFT 5u
8684 #define RCM_SRIE_WDOG_WIDTH 1u
8685 #define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_WDOG_SHIFT))&RCM_SRIE_WDOG_MASK)
8686 #define RCM_SRIE_PIN_MASK 0x40u
8687 #define RCM_SRIE_PIN_SHIFT 6u
8688 #define RCM_SRIE_PIN_WIDTH 1u
8689 #define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_PIN_SHIFT))&RCM_SRIE_PIN_MASK)
8690 #define RCM_SRIE_GIE_MASK 0x80u
8691 #define RCM_SRIE_GIE_SHIFT 7u
8692 #define RCM_SRIE_GIE_WIDTH 1u
8693 #define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_GIE_SHIFT))&RCM_SRIE_GIE_MASK)
8694 #define RCM_SRIE_JTAG_MASK 0x100u
8695 #define RCM_SRIE_JTAG_SHIFT 8u
8696 #define RCM_SRIE_JTAG_WIDTH 1u
8697 #define RCM_SRIE_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_JTAG_SHIFT))&RCM_SRIE_JTAG_MASK)
8698 #define RCM_SRIE_LOCKUP_MASK 0x200u
8699 #define RCM_SRIE_LOCKUP_SHIFT 9u
8700 #define RCM_SRIE_LOCKUP_WIDTH 1u
8701 #define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOCKUP_SHIFT))&RCM_SRIE_LOCKUP_MASK)
8702 #define RCM_SRIE_SW_MASK 0x400u
8703 #define RCM_SRIE_SW_SHIFT 10u
8704 #define RCM_SRIE_SW_WIDTH 1u
8705 #define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SW_SHIFT))&RCM_SRIE_SW_MASK)
8706 #define RCM_SRIE_MDM_AP_MASK 0x800u
8707 #define RCM_SRIE_MDM_AP_SHIFT 11u
8708 #define RCM_SRIE_MDM_AP_WIDTH 1u
8709 #define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_MDM_AP_SHIFT))&RCM_SRIE_MDM_AP_MASK)
8710 #define RCM_SRIE_SACKERR_MASK 0x2000u
8711 #define RCM_SRIE_SACKERR_SHIFT 13u
8712 #define RCM_SRIE_SACKERR_WIDTH 1u
8713 #define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SACKERR_SHIFT))&RCM_SRIE_SACKERR_MASK)
8714  /* end of group RCM_Register_Masks */
8718 
8719  /* end of group RCM_Peripheral_Access_Layer */
8723 
8724 
8725 /* ----------------------------------------------------------------------------
8726  -- RTC Peripheral Access Layer
8727  ---------------------------------------------------------------------------- */
8728 
8738 typedef struct {
8739  __IO uint32_t TSR;
8740  __IO uint32_t TPR;
8741  __IO uint32_t TAR;
8742  __IO uint32_t TCR;
8743  __IO uint32_t CR;
8744  __IO uint32_t SR;
8745  __IO uint32_t LR;
8746  __IO uint32_t IER;
8748 
8750 #define RTC_INSTANCE_COUNT (1u)
8751 
8752 
8753 /* RTC - Peripheral instance base addresses */
8755 #define RTC_BASE (0x4003D000u)
8756 
8757 #define RTC ((RTC_Type *)RTC_BASE)
8758 
8759 #define RTC_BASE_ADDRS { RTC_BASE }
8760 
8761 #define RTC_BASE_PTRS { RTC }
8762 
8763 #define RTC_IRQS_ARR_COUNT (2u)
8764 
8765 #define RTC_IRQS_CH_COUNT (1u)
8766 
8767 #define RTC_SECONDS_IRQS_CH_COUNT (1u)
8768 
8769 #define RTC_IRQS { RTC_IRQn }
8770 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
8771 
8772 /* ----------------------------------------------------------------------------
8773  -- RTC Register Masks
8774  ---------------------------------------------------------------------------- */
8775 
8781 /* TSR Bit Fields */
8782 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
8783 #define RTC_TSR_TSR_SHIFT 0u
8784 #define RTC_TSR_TSR_WIDTH 32u
8785 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
8786 /* TPR Bit Fields */
8787 #define RTC_TPR_TPR_MASK 0xFFFFu
8788 #define RTC_TPR_TPR_SHIFT 0u
8789 #define RTC_TPR_TPR_WIDTH 16u
8790 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
8791 /* TAR Bit Fields */
8792 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
8793 #define RTC_TAR_TAR_SHIFT 0u
8794 #define RTC_TAR_TAR_WIDTH 32u
8795 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
8796 /* TCR Bit Fields */
8797 #define RTC_TCR_TCR_MASK 0xFFu
8798 #define RTC_TCR_TCR_SHIFT 0u
8799 #define RTC_TCR_TCR_WIDTH 8u
8800 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
8801 #define RTC_TCR_CIR_MASK 0xFF00u
8802 #define RTC_TCR_CIR_SHIFT 8u
8803 #define RTC_TCR_CIR_WIDTH 8u
8804 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
8805 #define RTC_TCR_TCV_MASK 0xFF0000u
8806 #define RTC_TCR_TCV_SHIFT 16u
8807 #define RTC_TCR_TCV_WIDTH 8u
8808 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
8809 #define RTC_TCR_CIC_MASK 0xFF000000u
8810 #define RTC_TCR_CIC_SHIFT 24u
8811 #define RTC_TCR_CIC_WIDTH 8u
8812 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
8813 /* CR Bit Fields */
8814 #define RTC_CR_SWR_MASK 0x1u
8815 #define RTC_CR_SWR_SHIFT 0u
8816 #define RTC_CR_SWR_WIDTH 1u
8817 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
8818 #define RTC_CR_SUP_MASK 0x4u
8819 #define RTC_CR_SUP_SHIFT 2u
8820 #define RTC_CR_SUP_WIDTH 1u
8821 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
8822 #define RTC_CR_UM_MASK 0x8u
8823 #define RTC_CR_UM_SHIFT 3u
8824 #define RTC_CR_UM_WIDTH 1u
8825 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
8826 #define RTC_CR_CPS_MASK 0x20u
8827 #define RTC_CR_CPS_SHIFT 5u
8828 #define RTC_CR_CPS_WIDTH 1u
8829 #define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPS_SHIFT))&RTC_CR_CPS_MASK)
8830 #define RTC_CR_LPOS_MASK 0x80u
8831 #define RTC_CR_LPOS_SHIFT 7u
8832 #define RTC_CR_LPOS_WIDTH 1u
8833 #define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_LPOS_SHIFT))&RTC_CR_LPOS_MASK)
8834 #define RTC_CR_CLKO_MASK 0x200u
8835 #define RTC_CR_CLKO_SHIFT 9u
8836 #define RTC_CR_CLKO_WIDTH 1u
8837 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CLKO_SHIFT))&RTC_CR_CLKO_MASK)
8838 #define RTC_CR_CPE_MASK 0x1000000u
8839 #define RTC_CR_CPE_SHIFT 24u
8840 #define RTC_CR_CPE_WIDTH 1u
8841 #define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPE_SHIFT))&RTC_CR_CPE_MASK)
8842 /* SR Bit Fields */
8843 #define RTC_SR_TIF_MASK 0x1u
8844 #define RTC_SR_TIF_SHIFT 0u
8845 #define RTC_SR_TIF_WIDTH 1u
8846 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
8847 #define RTC_SR_TOF_MASK 0x2u
8848 #define RTC_SR_TOF_SHIFT 1u
8849 #define RTC_SR_TOF_WIDTH 1u
8850 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
8851 #define RTC_SR_TAF_MASK 0x4u
8852 #define RTC_SR_TAF_SHIFT 2u
8853 #define RTC_SR_TAF_WIDTH 1u
8854 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
8855 #define RTC_SR_TCE_MASK 0x10u
8856 #define RTC_SR_TCE_SHIFT 4u
8857 #define RTC_SR_TCE_WIDTH 1u
8858 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
8859 /* LR Bit Fields */
8860 #define RTC_LR_TCL_MASK 0x8u
8861 #define RTC_LR_TCL_SHIFT 3u
8862 #define RTC_LR_TCL_WIDTH 1u
8863 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
8864 #define RTC_LR_CRL_MASK 0x10u
8865 #define RTC_LR_CRL_SHIFT 4u
8866 #define RTC_LR_CRL_WIDTH 1u
8867 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
8868 #define RTC_LR_SRL_MASK 0x20u
8869 #define RTC_LR_SRL_SHIFT 5u
8870 #define RTC_LR_SRL_WIDTH 1u
8871 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
8872 #define RTC_LR_LRL_MASK 0x40u
8873 #define RTC_LR_LRL_SHIFT 6u
8874 #define RTC_LR_LRL_WIDTH 1u
8875 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
8876 /* IER Bit Fields */
8877 #define RTC_IER_TIIE_MASK 0x1u
8878 #define RTC_IER_TIIE_SHIFT 0u
8879 #define RTC_IER_TIIE_WIDTH 1u
8880 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
8881 #define RTC_IER_TOIE_MASK 0x2u
8882 #define RTC_IER_TOIE_SHIFT 1u
8883 #define RTC_IER_TOIE_WIDTH 1u
8884 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
8885 #define RTC_IER_TAIE_MASK 0x4u
8886 #define RTC_IER_TAIE_SHIFT 2u
8887 #define RTC_IER_TAIE_WIDTH 1u
8888 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
8889 #define RTC_IER_TSIE_MASK 0x10u
8890 #define RTC_IER_TSIE_SHIFT 4u
8891 #define RTC_IER_TSIE_WIDTH 1u
8892 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
8893 #define RTC_IER_TSIC_MASK 0x70000u
8894 #define RTC_IER_TSIC_SHIFT 16u
8895 #define RTC_IER_TSIC_WIDTH 3u
8896 #define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIC_SHIFT))&RTC_IER_TSIC_MASK)
8897  /* end of group RTC_Register_Masks */
8901 
8902  /* end of group RTC_Peripheral_Access_Layer */
8906 
8907 
8908 /* ----------------------------------------------------------------------------
8909  -- S32_NVIC Peripheral Access Layer
8910  ---------------------------------------------------------------------------- */
8911 
8919 #define S32_NVIC_ISER_COUNT 1u
8920 #define S32_NVIC_ICER_COUNT 1u
8921 #define S32_NVIC_ISPR_COUNT 1u
8922 #define S32_NVIC_ICPR_COUNT 1u
8923 #define S32_NVIC_IPR_COUNT 8u
8924 
8926 typedef struct {
8927  __IO uint32_t ISER[S32_NVIC_ISER_COUNT];
8928  uint8_t RESERVED_0[124];
8929  __IO uint32_t ICER[S32_NVIC_ICER_COUNT];
8930  uint8_t RESERVED_1[124];
8931  __IO uint32_t ISPR[S32_NVIC_ISPR_COUNT];
8932  uint8_t RESERVED_2[124];
8933  __IO uint32_t ICPR[S32_NVIC_ICPR_COUNT];
8934  uint8_t RESERVED_3[380];
8935  __IO uint32_t IPR[S32_NVIC_IPR_COUNT];
8937 
8939 #define S32_NVIC_INSTANCE_COUNT (1u)
8940 
8941 
8942 /* S32_NVIC - Peripheral instance base addresses */
8944 #define S32_NVIC_BASE (0xE000E100u)
8945 
8946 #define S32_NVIC ((S32_NVIC_Type *)S32_NVIC_BASE)
8947 
8948 #define S32_NVIC_BASE_ADDRS { S32_NVIC_BASE }
8949 
8950 #define S32_NVIC_BASE_PTRS { S32_NVIC }
8951 
8952 /* ----------------------------------------------------------------------------
8953  -- S32_NVIC Register Masks
8954  ---------------------------------------------------------------------------- */
8955 
8961 /* ISER Bit Fields */
8962 #define S32_NVIC_ISER_SETENA_MASK 0xFFFFFFFFu
8963 #define S32_NVIC_ISER_SETENA_SHIFT 0u
8964 #define S32_NVIC_ISER_SETENA_WIDTH 32u
8965 #define S32_NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISER_SETENA_SHIFT))&S32_NVIC_ISER_SETENA_MASK)
8966 /* ICER Bit Fields */
8967 #define S32_NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu
8968 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
8969 #define S32_NVIC_ICER_CLRENA_WIDTH 32u
8970 #define S32_NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICER_CLRENA_SHIFT))&S32_NVIC_ICER_CLRENA_MASK)
8971 /* ISPR Bit Fields */
8972 #define S32_NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu
8973 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
8974 #define S32_NVIC_ISPR_SETPEND_WIDTH 32u
8975 #define S32_NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISPR_SETPEND_SHIFT))&S32_NVIC_ISPR_SETPEND_MASK)
8976 /* ICPR Bit Fields */
8977 #define S32_NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu
8978 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
8979 #define S32_NVIC_ICPR_CLRPEND_WIDTH 32u
8980 #define S32_NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICPR_CLRPEND_SHIFT))&S32_NVIC_ICPR_CLRPEND_MASK)
8981 /* IPR Bit Fields */
8982 #define S32_NVIC_IPR_PRI_0_MASK 0xFFu
8983 #define S32_NVIC_IPR_PRI_0_SHIFT 0u
8984 #define S32_NVIC_IPR_PRI_0_WIDTH 8u
8985 #define S32_NVIC_IPR_PRI_0(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_0_SHIFT))&S32_NVIC_IPR_PRI_0_MASK)
8986 #define S32_NVIC_IPR_PRI_1_MASK 0xFF00u
8987 #define S32_NVIC_IPR_PRI_1_SHIFT 8u
8988 #define S32_NVIC_IPR_PRI_1_WIDTH 8u
8989 #define S32_NVIC_IPR_PRI_1(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_1_SHIFT))&S32_NVIC_IPR_PRI_1_MASK)
8990 #define S32_NVIC_IPR_PRI_2_MASK 0xFF0000u
8991 #define S32_NVIC_IPR_PRI_2_SHIFT 16u
8992 #define S32_NVIC_IPR_PRI_2_WIDTH 8u
8993 #define S32_NVIC_IPR_PRI_2(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_2_SHIFT))&S32_NVIC_IPR_PRI_2_MASK)
8994 #define S32_NVIC_IPR_PRI_3_MASK 0xFF000000u
8995 #define S32_NVIC_IPR_PRI_3_SHIFT 24u
8996 #define S32_NVIC_IPR_PRI_3_WIDTH 8u
8997 #define S32_NVIC_IPR_PRI_3(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_3_SHIFT))&S32_NVIC_IPR_PRI_3_MASK)
8998  /* end of group S32_NVIC_Register_Masks */
9002 
9003  /* end of group S32_NVIC_Peripheral_Access_Layer */
9007 
9008 
9009 /* ----------------------------------------------------------------------------
9010  -- S32_SCB Peripheral Access Layer
9011  ---------------------------------------------------------------------------- */
9012 
9022 typedef struct {
9023  uint8_t RESERVED_0[8];
9024  __I uint32_t ACTLR;
9025  uint8_t RESERVED_1[3316];
9026  __I uint32_t CPUID;
9027  __IO uint32_t ICSR;
9028  __IO uint32_t VTOR;
9029  __IO uint32_t AIRCR;
9030  __IO uint32_t SCR;
9031  __I uint32_t CCR;
9032  uint8_t RESERVED_2[4];
9033  __IO uint32_t SHPR2;
9034  __IO uint32_t SHPR3;
9035  __IO uint32_t SHCSR;
9036  uint8_t RESERVED_3[8];
9037  __IO uint32_t DFSR;
9039 
9041 #define S32_SCB_INSTANCE_COUNT (1u)
9042 
9043 
9044 /* S32_SCB - Peripheral instance base addresses */
9046 #define S32_SCB_BASE (0xE000E000u)
9047 
9048 #define S32_SCB ((S32_SCB_Type *)S32_SCB_BASE)
9049 
9050 #define S32_SCB_BASE_ADDRS { S32_SCB_BASE }
9051 
9052 #define S32_SCB_BASE_PTRS { S32_SCB }
9053 
9054 /* ----------------------------------------------------------------------------
9055  -- S32_SCB Register Masks
9056  ---------------------------------------------------------------------------- */
9057 
9063 /* CPUID Bit Fields */
9064 #define S32_SCB_CPUID_REVISION_MASK 0xFu
9065 #define S32_SCB_CPUID_REVISION_SHIFT 0u
9066 #define S32_SCB_CPUID_REVISION_WIDTH 4u
9067 #define S32_SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_REVISION_SHIFT))&S32_SCB_CPUID_REVISION_MASK)
9068 #define S32_SCB_CPUID_PARTNO_MASK 0xFFF0u
9069 #define S32_SCB_CPUID_PARTNO_SHIFT 4u
9070 #define S32_SCB_CPUID_PARTNO_WIDTH 12u
9071 #define S32_SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_PARTNO_SHIFT))&S32_SCB_CPUID_PARTNO_MASK)
9072 #define S32_SCB_CPUID_VARIANT_MASK 0xF00000u
9073 #define S32_SCB_CPUID_VARIANT_SHIFT 20u
9074 #define S32_SCB_CPUID_VARIANT_WIDTH 4u
9075 #define S32_SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_VARIANT_SHIFT))&S32_SCB_CPUID_VARIANT_MASK)
9076 #define S32_SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u
9077 #define S32_SCB_CPUID_IMPLEMENTER_SHIFT 24u
9078 #define S32_SCB_CPUID_IMPLEMENTER_WIDTH 8u
9079 #define S32_SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_IMPLEMENTER_SHIFT))&S32_SCB_CPUID_IMPLEMENTER_MASK)
9080 /* ICSR Bit Fields */
9081 #define S32_SCB_ICSR_VECTACTIVE_MASK 0x3Fu
9082 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u
9083 #define S32_SCB_ICSR_VECTACTIVE_WIDTH 6u
9084 #define S32_SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTACTIVE_SHIFT))&S32_SCB_ICSR_VECTACTIVE_MASK)
9085 #define S32_SCB_ICSR_VECTPENDING_MASK 0x3F000u
9086 #define S32_SCB_ICSR_VECTPENDING_SHIFT 12u
9087 #define S32_SCB_ICSR_VECTPENDING_WIDTH 6u
9088 #define S32_SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTPENDING_SHIFT))&S32_SCB_ICSR_VECTPENDING_MASK)
9089 #define S32_SCB_ICSR_ISRPENDING_MASK 0x400000u
9090 #define S32_SCB_ICSR_ISRPENDING_SHIFT 22u
9091 #define S32_SCB_ICSR_ISRPENDING_WIDTH 1u
9092 #define S32_SCB_ICSR_ISRPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPENDING_SHIFT))&S32_SCB_ICSR_ISRPENDING_MASK)
9093 #define S32_SCB_ICSR_PENDSTCLR_MASK 0x2000000u
9094 #define S32_SCB_ICSR_PENDSTCLR_SHIFT 25u
9095 #define S32_SCB_ICSR_PENDSTCLR_WIDTH 1u
9096 #define S32_SCB_ICSR_PENDSTCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTCLR_SHIFT))&S32_SCB_ICSR_PENDSTCLR_MASK)
9097 #define S32_SCB_ICSR_PENDSTSET_MASK 0x4000000u
9098 #define S32_SCB_ICSR_PENDSTSET_SHIFT 26u
9099 #define S32_SCB_ICSR_PENDSTSET_WIDTH 1u
9100 #define S32_SCB_ICSR_PENDSTSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTSET_SHIFT))&S32_SCB_ICSR_PENDSTSET_MASK)
9101 #define S32_SCB_ICSR_PENDSVCLR_MASK 0x8000000u
9102 #define S32_SCB_ICSR_PENDSVCLR_SHIFT 27u
9103 #define S32_SCB_ICSR_PENDSVCLR_WIDTH 1u
9104 #define S32_SCB_ICSR_PENDSVCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVCLR_SHIFT))&S32_SCB_ICSR_PENDSVCLR_MASK)
9105 #define S32_SCB_ICSR_PENDSVSET_MASK 0x10000000u
9106 #define S32_SCB_ICSR_PENDSVSET_SHIFT 28u
9107 #define S32_SCB_ICSR_PENDSVSET_WIDTH 1u
9108 #define S32_SCB_ICSR_PENDSVSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVSET_SHIFT))&S32_SCB_ICSR_PENDSVSET_MASK)
9109 #define S32_SCB_ICSR_NMIPENDSET_MASK 0x80000000u
9110 #define S32_SCB_ICSR_NMIPENDSET_SHIFT 31u
9111 #define S32_SCB_ICSR_NMIPENDSET_WIDTH 1u
9112 #define S32_SCB_ICSR_NMIPENDSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_NMIPENDSET_SHIFT))&S32_SCB_ICSR_NMIPENDSET_MASK)
9113 /* VTOR Bit Fields */
9114 #define S32_SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u
9115 #define S32_SCB_VTOR_TBLOFF_SHIFT 7u
9116 #define S32_SCB_VTOR_TBLOFF_WIDTH 25u
9117 #define S32_SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_VTOR_TBLOFF_SHIFT))&S32_SCB_VTOR_TBLOFF_MASK)
9118 /* AIRCR Bit Fields */
9119 #define S32_SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u
9120 #define S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT 1u
9121 #define S32_SCB_AIRCR_VECTCLRACTIVE_WIDTH 1u
9122 #define S32_SCB_AIRCR_VECTCLRACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT))&S32_SCB_AIRCR_VECTCLRACTIVE_MASK)
9123 #define S32_SCB_AIRCR_SYSRESETREQ_MASK 0x4u
9124 #define S32_SCB_AIRCR_SYSRESETREQ_SHIFT 2u
9125 #define S32_SCB_AIRCR_SYSRESETREQ_WIDTH 1u
9126 #define S32_SCB_AIRCR_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_SYSRESETREQ_SHIFT))&S32_SCB_AIRCR_SYSRESETREQ_MASK)
9127 #define S32_SCB_AIRCR_ENDIANNESS_MASK 0x8000u
9128 #define S32_SCB_AIRCR_ENDIANNESS_SHIFT 15u
9129 #define S32_SCB_AIRCR_ENDIANNESS_WIDTH 1u
9130 #define S32_SCB_AIRCR_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_ENDIANNESS_SHIFT))&S32_SCB_AIRCR_ENDIANNESS_MASK)
9131 #define S32_SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u
9132 #define S32_SCB_AIRCR_VECTKEY_SHIFT 16u
9133 #define S32_SCB_AIRCR_VECTKEY_WIDTH 16u
9134 #define S32_SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTKEY_SHIFT))&S32_SCB_AIRCR_VECTKEY_MASK)
9135 /* SCR Bit Fields */
9136 #define S32_SCB_SCR_SLEEPONEXIT_MASK 0x2u
9137 #define S32_SCB_SCR_SLEEPONEXIT_SHIFT 1u
9138 #define S32_SCB_SCR_SLEEPONEXIT_WIDTH 1u
9139 #define S32_SCB_SCR_SLEEPONEXIT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPONEXIT_SHIFT))&S32_SCB_SCR_SLEEPONEXIT_MASK)
9140 #define S32_SCB_SCR_SLEEPDEEP_MASK 0x4u
9141 #define S32_SCB_SCR_SLEEPDEEP_SHIFT 2u
9142 #define S32_SCB_SCR_SLEEPDEEP_WIDTH 1u
9143 #define S32_SCB_SCR_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPDEEP_SHIFT))&S32_SCB_SCR_SLEEPDEEP_MASK)
9144 #define S32_SCB_SCR_SEVONPEND_MASK 0x10u
9145 #define S32_SCB_SCR_SEVONPEND_SHIFT 4u
9146 #define S32_SCB_SCR_SEVONPEND_WIDTH 1u
9147 #define S32_SCB_SCR_SEVONPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SEVONPEND_SHIFT))&S32_SCB_SCR_SEVONPEND_MASK)
9148 /* CCR Bit Fields */
9149 #define S32_SCB_CCR_UNALIGN_TRP_MASK 0x8u
9150 #define S32_SCB_CCR_UNALIGN_TRP_SHIFT 3u
9151 #define S32_SCB_CCR_UNALIGN_TRP_WIDTH 1u
9152 #define S32_SCB_CCR_UNALIGN_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_UNALIGN_TRP_SHIFT))&S32_SCB_CCR_UNALIGN_TRP_MASK)
9153 #define S32_SCB_CCR_STKALIGN_MASK 0x200u
9154 #define S32_SCB_CCR_STKALIGN_SHIFT 9u
9155 #define S32_SCB_CCR_STKALIGN_WIDTH 1u
9156 #define S32_SCB_CCR_STKALIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_STKALIGN_SHIFT))&S32_SCB_CCR_STKALIGN_MASK)
9157 /* SHPR2 Bit Fields */
9158 #define S32_SCB_SHPR2_PRI_11_MASK 0xFF000000u
9159 #define S32_SCB_SHPR2_PRI_11_SHIFT 24u
9160 #define S32_SCB_SHPR2_PRI_11_WIDTH 8u
9161 #define S32_SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR2_PRI_11_SHIFT))&S32_SCB_SHPR2_PRI_11_MASK)
9162 /* SHPR3 Bit Fields */
9163 #define S32_SCB_SHPR3_PRI_14_MASK 0xFF0000u
9164 #define S32_SCB_SHPR3_PRI_14_SHIFT 16u
9165 #define S32_SCB_SHPR3_PRI_14_WIDTH 8u
9166 #define S32_SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_14_SHIFT))&S32_SCB_SHPR3_PRI_14_MASK)
9167 #define S32_SCB_SHPR3_PRI_15_MASK 0xFF000000u
9168 #define S32_SCB_SHPR3_PRI_15_SHIFT 24u
9169 #define S32_SCB_SHPR3_PRI_15_WIDTH 8u
9170 #define S32_SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_15_SHIFT))&S32_SCB_SHPR3_PRI_15_MASK)
9171 /* SHCSR Bit Fields */
9172 #define S32_SCB_SHCSR_SVCALLPENDED_MASK 0x8000u
9173 #define S32_SCB_SHCSR_SVCALLPENDED_SHIFT 15u
9174 #define S32_SCB_SHCSR_SVCALLPENDED_WIDTH 1u
9175 #define S32_SCB_SHCSR_SVCALLPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLPENDED_SHIFT))&S32_SCB_SHCSR_SVCALLPENDED_MASK)
9176 /* DFSR Bit Fields */
9177 #define S32_SCB_DFSR_HALTED_MASK 0x1u
9178 #define S32_SCB_DFSR_HALTED_SHIFT 0u
9179 #define S32_SCB_DFSR_HALTED_WIDTH 1u
9180 #define S32_SCB_DFSR_HALTED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_HALTED_SHIFT))&S32_SCB_DFSR_HALTED_MASK)
9181 #define S32_SCB_DFSR_BKPT_MASK 0x2u
9182 #define S32_SCB_DFSR_BKPT_SHIFT 1u
9183 #define S32_SCB_DFSR_BKPT_WIDTH 1u
9184 #define S32_SCB_DFSR_BKPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_BKPT_SHIFT))&S32_SCB_DFSR_BKPT_MASK)
9185 #define S32_SCB_DFSR_DWTTRAP_MASK 0x4u
9186 #define S32_SCB_DFSR_DWTTRAP_SHIFT 2u
9187 #define S32_SCB_DFSR_DWTTRAP_WIDTH 1u
9188 #define S32_SCB_DFSR_DWTTRAP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_DWTTRAP_SHIFT))&S32_SCB_DFSR_DWTTRAP_MASK)
9189 #define S32_SCB_DFSR_VCATCH_MASK 0x8u
9190 #define S32_SCB_DFSR_VCATCH_SHIFT 3u
9191 #define S32_SCB_DFSR_VCATCH_WIDTH 1u
9192 #define S32_SCB_DFSR_VCATCH(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_VCATCH_SHIFT))&S32_SCB_DFSR_VCATCH_MASK)
9193 #define S32_SCB_DFSR_EXTERNAL_MASK 0x10u
9194 #define S32_SCB_DFSR_EXTERNAL_SHIFT 4u
9195 #define S32_SCB_DFSR_EXTERNAL_WIDTH 1u
9196 #define S32_SCB_DFSR_EXTERNAL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_EXTERNAL_SHIFT))&S32_SCB_DFSR_EXTERNAL_MASK)
9197  /* end of group S32_SCB_Register_Masks */
9201 
9202  /* end of group S32_SCB_Peripheral_Access_Layer */
9206 
9207 
9208 /* ----------------------------------------------------------------------------
9209  -- S32_SysTick Peripheral Access Layer
9210  ---------------------------------------------------------------------------- */
9211 
9221 typedef struct {
9222  __IO uint32_t CSR;
9223  __IO uint32_t RVR;
9224  __IO uint32_t CVR;
9225  __I uint32_t CALIB;
9227 
9229 #define S32_SysTick_INSTANCE_COUNT (1u)
9230 
9231 
9232 /* S32_SysTick - Peripheral instance base addresses */
9234 #define S32_SysTick_BASE (0xE000E010u)
9235 
9236 #define S32_SysTick ((S32_SysTick_Type *)S32_SysTick_BASE)
9237 
9238 #define S32_SysTick_BASE_ADDRS { S32_SysTick_BASE }
9239 
9240 #define S32_SysTick_BASE_PTRS { S32_SysTick }
9241 
9242 #define S32_SysTick_IRQS_ARR_COUNT (1u)
9243 
9244 #define S32_SysTick_IRQS_CH_COUNT (1u)
9245 
9246 #define S32_SysTick_IRQS { SysTick_IRQn }
9247 
9248 /* ----------------------------------------------------------------------------
9249  -- S32_SysTick Register Masks
9250  ---------------------------------------------------------------------------- */
9251 
9257 /* CSR Bit Fields */
9258 #define S32_SysTick_CSR_ENABLE_MASK 0x1u
9259 #define S32_SysTick_CSR_ENABLE_SHIFT 0u
9260 #define S32_SysTick_CSR_ENABLE_WIDTH 1u
9261 #define S32_SysTick_CSR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_ENABLE_SHIFT))&S32_SysTick_CSR_ENABLE_MASK)
9262 #define S32_SysTick_CSR_TICKINT_MASK 0x2u
9263 #define S32_SysTick_CSR_TICKINT_SHIFT 1u
9264 #define S32_SysTick_CSR_TICKINT_WIDTH 1u
9265 #define S32_SysTick_CSR_TICKINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_TICKINT_SHIFT))&S32_SysTick_CSR_TICKINT_MASK)
9266 #define S32_SysTick_CSR_CLKSOURCE_MASK 0x4u
9267 #define S32_SysTick_CSR_CLKSOURCE_SHIFT 2u
9268 #define S32_SysTick_CSR_CLKSOURCE_WIDTH 1u
9269 #define S32_SysTick_CSR_CLKSOURCE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_CLKSOURCE_SHIFT))&S32_SysTick_CSR_CLKSOURCE_MASK)
9270 #define S32_SysTick_CSR_COUNTFLAG_MASK 0x10000u
9271 #define S32_SysTick_CSR_COUNTFLAG_SHIFT 16u
9272 #define S32_SysTick_CSR_COUNTFLAG_WIDTH 1u
9273 #define S32_SysTick_CSR_COUNTFLAG(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_COUNTFLAG_SHIFT))&S32_SysTick_CSR_COUNTFLAG_MASK)
9274 /* RVR Bit Fields */
9275 #define S32_SysTick_RVR_RELOAD_MASK 0xFFFFFFu
9276 #define S32_SysTick_RVR_RELOAD_SHIFT 0u
9277 #define S32_SysTick_RVR_RELOAD_WIDTH 24u
9278 #define S32_SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_RVR_RELOAD_SHIFT))&S32_SysTick_RVR_RELOAD_MASK)
9279 /* CVR Bit Fields */
9280 #define S32_SysTick_CVR_CURRENT_MASK 0xFFFFFFu
9281 #define S32_SysTick_CVR_CURRENT_SHIFT 0u
9282 #define S32_SysTick_CVR_CURRENT_WIDTH 24u
9283 #define S32_SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CVR_CURRENT_SHIFT))&S32_SysTick_CVR_CURRENT_MASK)
9284 /* CALIB Bit Fields */
9285 #define S32_SysTick_CALIB_TENMS_MASK 0xFFFFFFu
9286 #define S32_SysTick_CALIB_TENMS_SHIFT 0u
9287 #define S32_SysTick_CALIB_TENMS_WIDTH 24u
9288 #define S32_SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_TENMS_SHIFT))&S32_SysTick_CALIB_TENMS_MASK)
9289 #define S32_SysTick_CALIB_SKEW_MASK 0x40000000u
9290 #define S32_SysTick_CALIB_SKEW_SHIFT 30u
9291 #define S32_SysTick_CALIB_SKEW_WIDTH 1u
9292 #define S32_SysTick_CALIB_SKEW(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_SKEW_SHIFT))&S32_SysTick_CALIB_SKEW_MASK)
9293 #define S32_SysTick_CALIB_NOREF_MASK 0x80000000u
9294 #define S32_SysTick_CALIB_NOREF_SHIFT 31u
9295 #define S32_SysTick_CALIB_NOREF_WIDTH 1u
9296 #define S32_SysTick_CALIB_NOREF(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_NOREF_SHIFT))&S32_SysTick_CALIB_NOREF_MASK)
9297  /* end of group S32_SysTick_Register_Masks */
9301 
9302  /* end of group S32_SysTick_Peripheral_Access_Layer */
9306 
9307 
9308 /* ----------------------------------------------------------------------------
9309  -- SCG Peripheral Access Layer
9310  ---------------------------------------------------------------------------- */
9311 
9321 typedef struct {
9322  __I uint32_t VERID;
9323  __I uint32_t PARAM;
9324  uint8_t RESERVED_0[8];
9325  __I uint32_t CSR;
9326  __IO uint32_t RCCR;
9327  __IO uint32_t VCCR;
9328  uint8_t RESERVED_1[4];
9329  __IO uint32_t CLKOUTCNFG;
9330  uint8_t RESERVED_2[220];
9331  __IO uint32_t SOSCCSR;
9332  __IO uint32_t SOSCDIV;
9333  __IO uint32_t SOSCCFG;
9334  uint8_t RESERVED_3[244];
9335  __IO uint32_t SIRCCSR;
9336  __IO uint32_t SIRCDIV;
9337  __IO uint32_t SIRCCFG;
9338  uint8_t RESERVED_4[244];
9339  __IO uint32_t FIRCCSR;
9340  __IO uint32_t FIRCDIV;
9341  __IO uint32_t FIRCCFG;
9343 
9345 #define SCG_INSTANCE_COUNT (1u)
9346 
9347 
9348 /* SCG - Peripheral instance base addresses */
9350 #define SCG_BASE (0x40064000u)
9351 
9352 #define SCG ((SCG_Type *)SCG_BASE)
9353 
9354 #define SCG_BASE_ADDRS { SCG_BASE }
9355 
9356 #define SCG_BASE_PTRS { SCG }
9357 
9358 #define SCG_IRQS_ARR_COUNT (1u)
9359 
9360 #define SCG_IRQS_CH_COUNT (1u)
9361 
9362 #define SCG_IRQS { SCG_CMU_LVD_LVWSCG_IRQn }
9363 
9364 /* ----------------------------------------------------------------------------
9365  -- SCG Register Masks
9366  ---------------------------------------------------------------------------- */
9367 
9373 /* VERID Bit Fields */
9374 #define SCG_VERID_VERSION_MASK 0xFFFFFFFFu
9375 #define SCG_VERID_VERSION_SHIFT 0u
9376 #define SCG_VERID_VERSION_WIDTH 32u
9377 #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x))<<SCG_VERID_VERSION_SHIFT))&SCG_VERID_VERSION_MASK)
9378 /* PARAM Bit Fields */
9379 #define SCG_PARAM_CLKPRES_MASK 0xFFu
9380 #define SCG_PARAM_CLKPRES_SHIFT 0u
9381 #define SCG_PARAM_CLKPRES_WIDTH 8u
9382 #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_CLKPRES_SHIFT))&SCG_PARAM_CLKPRES_MASK)
9383 #define SCG_PARAM_DIVPRES_MASK 0xF8000000u
9384 #define SCG_PARAM_DIVPRES_SHIFT 27u
9385 #define SCG_PARAM_DIVPRES_WIDTH 5u
9386 #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_DIVPRES_SHIFT))&SCG_PARAM_DIVPRES_MASK)
9387 /* CSR Bit Fields */
9388 #define SCG_CSR_DIVSLOW_MASK 0xFu
9389 #define SCG_CSR_DIVSLOW_SHIFT 0u
9390 #define SCG_CSR_DIVSLOW_WIDTH 4u
9391 #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVSLOW_SHIFT))&SCG_CSR_DIVSLOW_MASK)
9392 #define SCG_CSR_DIVBUS_MASK 0xF0u
9393 #define SCG_CSR_DIVBUS_SHIFT 4u
9394 #define SCG_CSR_DIVBUS_WIDTH 4u
9395 #define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVBUS_SHIFT))&SCG_CSR_DIVBUS_MASK)
9396 #define SCG_CSR_DIVCORE_MASK 0xF0000u
9397 #define SCG_CSR_DIVCORE_SHIFT 16u
9398 #define SCG_CSR_DIVCORE_WIDTH 4u
9399 #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVCORE_SHIFT))&SCG_CSR_DIVCORE_MASK)
9400 #define SCG_CSR_SCS_MASK 0xF000000u
9401 #define SCG_CSR_SCS_SHIFT 24u
9402 #define SCG_CSR_SCS_WIDTH 4u
9403 #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_SCS_SHIFT))&SCG_CSR_SCS_MASK)
9404 /* RCCR Bit Fields */
9405 #define SCG_RCCR_DIVSLOW_MASK 0xFu
9406 #define SCG_RCCR_DIVSLOW_SHIFT 0u
9407 #define SCG_RCCR_DIVSLOW_WIDTH 4u
9408 #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVSLOW_SHIFT))&SCG_RCCR_DIVSLOW_MASK)
9409 #define SCG_RCCR_DIVBUS_MASK 0xF0u
9410 #define SCG_RCCR_DIVBUS_SHIFT 4u
9411 #define SCG_RCCR_DIVBUS_WIDTH 4u
9412 #define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVBUS_SHIFT))&SCG_RCCR_DIVBUS_MASK)
9413 #define SCG_RCCR_DIVCORE_MASK 0xF0000u
9414 #define SCG_RCCR_DIVCORE_SHIFT 16u
9415 #define SCG_RCCR_DIVCORE_WIDTH 4u
9416 #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVCORE_SHIFT))&SCG_RCCR_DIVCORE_MASK)
9417 #define SCG_RCCR_SCS_MASK 0xF000000u
9418 #define SCG_RCCR_SCS_SHIFT 24u
9419 #define SCG_RCCR_SCS_WIDTH 4u
9420 #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_SCS_SHIFT))&SCG_RCCR_SCS_MASK)
9421 /* VCCR Bit Fields */
9422 #define SCG_VCCR_DIVSLOW_MASK 0xFu
9423 #define SCG_VCCR_DIVSLOW_SHIFT 0u
9424 #define SCG_VCCR_DIVSLOW_WIDTH 4u
9425 #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVSLOW_SHIFT))&SCG_VCCR_DIVSLOW_MASK)
9426 #define SCG_VCCR_DIVBUS_MASK 0xF0u
9427 #define SCG_VCCR_DIVBUS_SHIFT 4u
9428 #define SCG_VCCR_DIVBUS_WIDTH 4u
9429 #define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVBUS_SHIFT))&SCG_VCCR_DIVBUS_MASK)
9430 #define SCG_VCCR_DIVCORE_MASK 0xF0000u
9431 #define SCG_VCCR_DIVCORE_SHIFT 16u
9432 #define SCG_VCCR_DIVCORE_WIDTH 4u
9433 #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVCORE_SHIFT))&SCG_VCCR_DIVCORE_MASK)
9434 #define SCG_VCCR_SCS_MASK 0xF000000u
9435 #define SCG_VCCR_SCS_SHIFT 24u
9436 #define SCG_VCCR_SCS_WIDTH 4u
9437 #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_SCS_SHIFT))&SCG_VCCR_SCS_MASK)
9438 /* CLKOUTCNFG Bit Fields */
9439 #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK 0xF000000u
9440 #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT 24u
9441 #define SCG_CLKOUTCNFG_CLKOUTSEL_WIDTH 4u
9442 #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT))&SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
9443 /* SOSCCSR Bit Fields */
9444 #define SCG_SOSCCSR_SOSCEN_MASK 0x1u
9445 #define SCG_SOSCCSR_SOSCEN_SHIFT 0u
9446 #define SCG_SOSCCSR_SOSCEN_WIDTH 1u
9447 #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCEN_SHIFT))&SCG_SOSCCSR_SOSCEN_MASK)
9448 #define SCG_SOSCCSR_SOSCCM_MASK 0x10000u
9449 #define SCG_SOSCCSR_SOSCCM_SHIFT 16u
9450 #define SCG_SOSCCSR_SOSCCM_WIDTH 1u
9451 #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCM_SHIFT))&SCG_SOSCCSR_SOSCCM_MASK)
9452 #define SCG_SOSCCSR_SOSCCMRE_MASK 0x20000u
9453 #define SCG_SOSCCSR_SOSCCMRE_SHIFT 17u
9454 #define SCG_SOSCCSR_SOSCCMRE_WIDTH 1u
9455 #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCMRE_SHIFT))&SCG_SOSCCSR_SOSCCMRE_MASK)
9456 #define SCG_SOSCCSR_LK_MASK 0x800000u
9457 #define SCG_SOSCCSR_LK_SHIFT 23u
9458 #define SCG_SOSCCSR_LK_WIDTH 1u
9459 #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_LK_SHIFT))&SCG_SOSCCSR_LK_MASK)
9460 #define SCG_SOSCCSR_SOSCVLD_MASK 0x1000000u
9461 #define SCG_SOSCCSR_SOSCVLD_SHIFT 24u
9462 #define SCG_SOSCCSR_SOSCVLD_WIDTH 1u
9463 #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCVLD_SHIFT))&SCG_SOSCCSR_SOSCVLD_MASK)
9464 #define SCG_SOSCCSR_SOSCSEL_MASK 0x2000000u
9465 #define SCG_SOSCCSR_SOSCSEL_SHIFT 25u
9466 #define SCG_SOSCCSR_SOSCSEL_WIDTH 1u
9467 #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCSEL_SHIFT))&SCG_SOSCCSR_SOSCSEL_MASK)
9468 #define SCG_SOSCCSR_SOSCERR_MASK 0x4000000u
9469 #define SCG_SOSCCSR_SOSCERR_SHIFT 26u
9470 #define SCG_SOSCCSR_SOSCERR_WIDTH 1u
9471 #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCERR_SHIFT))&SCG_SOSCCSR_SOSCERR_MASK)
9472 /* SOSCDIV Bit Fields */
9473 #define SCG_SOSCDIV_SOSCDIV1_MASK 0x7u
9474 #define SCG_SOSCDIV_SOSCDIV1_SHIFT 0u
9475 #define SCG_SOSCDIV_SOSCDIV1_WIDTH 3u
9476 #define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV1_SHIFT))&SCG_SOSCDIV_SOSCDIV1_MASK)
9477 #define SCG_SOSCDIV_SOSCDIV2_MASK 0x700u
9478 #define SCG_SOSCDIV_SOSCDIV2_SHIFT 8u
9479 #define SCG_SOSCDIV_SOSCDIV2_WIDTH 3u
9480 #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV2_SHIFT))&SCG_SOSCDIV_SOSCDIV2_MASK)
9481 /* SOSCCFG Bit Fields */
9482 #define SCG_SOSCCFG_EREFS_MASK 0x4u
9483 #define SCG_SOSCCFG_EREFS_SHIFT 2u
9484 #define SCG_SOSCCFG_EREFS_WIDTH 1u
9485 #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_EREFS_SHIFT))&SCG_SOSCCFG_EREFS_MASK)
9486 #define SCG_SOSCCFG_HGO_MASK 0x8u
9487 #define SCG_SOSCCFG_HGO_SHIFT 3u
9488 #define SCG_SOSCCFG_HGO_WIDTH 1u
9489 #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_HGO_SHIFT))&SCG_SOSCCFG_HGO_MASK)
9490 #define SCG_SOSCCFG_RANGE_MASK 0x30u
9491 #define SCG_SOSCCFG_RANGE_SHIFT 4u
9492 #define SCG_SOSCCFG_RANGE_WIDTH 2u
9493 #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_RANGE_SHIFT))&SCG_SOSCCFG_RANGE_MASK)
9494 /* SIRCCSR Bit Fields */
9495 #define SCG_SIRCCSR_SIRCEN_MASK 0x1u
9496 #define SCG_SIRCCSR_SIRCEN_SHIFT 0u
9497 #define SCG_SIRCCSR_SIRCEN_WIDTH 1u
9498 #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCEN_SHIFT))&SCG_SIRCCSR_SIRCEN_MASK)
9499 #define SCG_SIRCCSR_SIRCSTEN_MASK 0x2u
9500 #define SCG_SIRCCSR_SIRCSTEN_SHIFT 1u
9501 #define SCG_SIRCCSR_SIRCSTEN_WIDTH 1u
9502 #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSTEN_SHIFT))&SCG_SIRCCSR_SIRCSTEN_MASK)
9503 #define SCG_SIRCCSR_SIRCLPEN_MASK 0x4u
9504 #define SCG_SIRCCSR_SIRCLPEN_SHIFT 2u
9505 #define SCG_SIRCCSR_SIRCLPEN_WIDTH 1u
9506 #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCLPEN_SHIFT))&SCG_SIRCCSR_SIRCLPEN_MASK)
9507 #define SCG_SIRCCSR_LK_MASK 0x800000u
9508 #define SCG_SIRCCSR_LK_SHIFT 23u
9509 #define SCG_SIRCCSR_LK_WIDTH 1u
9510 #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_LK_SHIFT))&SCG_SIRCCSR_LK_MASK)
9511 #define SCG_SIRCCSR_SIRCVLD_MASK 0x1000000u
9512 #define SCG_SIRCCSR_SIRCVLD_SHIFT 24u
9513 #define SCG_SIRCCSR_SIRCVLD_WIDTH 1u
9514 #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCVLD_SHIFT))&SCG_SIRCCSR_SIRCVLD_MASK)
9515 #define SCG_SIRCCSR_SIRCSEL_MASK 0x2000000u
9516 #define SCG_SIRCCSR_SIRCSEL_SHIFT 25u
9517 #define SCG_SIRCCSR_SIRCSEL_WIDTH 1u
9518 #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSEL_SHIFT))&SCG_SIRCCSR_SIRCSEL_MASK)
9519 /* SIRCDIV Bit Fields */
9520 #define SCG_SIRCDIV_SIRCDIV1_MASK 0x7u
9521 #define SCG_SIRCDIV_SIRCDIV1_SHIFT 0u
9522 #define SCG_SIRCDIV_SIRCDIV1_WIDTH 3u
9523 #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV1_SHIFT))&SCG_SIRCDIV_SIRCDIV1_MASK)
9524 #define SCG_SIRCDIV_SIRCDIV2_MASK 0x700u
9525 #define SCG_SIRCDIV_SIRCDIV2_SHIFT 8u
9526 #define SCG_SIRCDIV_SIRCDIV2_WIDTH 3u
9527 #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV2_SHIFT))&SCG_SIRCDIV_SIRCDIV2_MASK)
9528 /* SIRCCFG Bit Fields */
9529 #define SCG_SIRCCFG_RANGE_MASK 0x1u
9530 #define SCG_SIRCCFG_RANGE_SHIFT 0u
9531 #define SCG_SIRCCFG_RANGE_WIDTH 1u
9532 #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCFG_RANGE_SHIFT))&SCG_SIRCCFG_RANGE_MASK)
9533 /* FIRCCSR Bit Fields */
9534 #define SCG_FIRCCSR_FIRCEN_MASK 0x1u
9535 #define SCG_FIRCCSR_FIRCEN_SHIFT 0u
9536 #define SCG_FIRCCSR_FIRCEN_WIDTH 1u
9537 #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCEN_SHIFT))&SCG_FIRCCSR_FIRCEN_MASK)
9538 #define SCG_FIRCCSR_FIRCREGOFF_MASK 0x8u
9539 #define SCG_FIRCCSR_FIRCREGOFF_SHIFT 3u
9540 #define SCG_FIRCCSR_FIRCREGOFF_WIDTH 1u
9541 #define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCREGOFF_SHIFT))&SCG_FIRCCSR_FIRCREGOFF_MASK)
9542 #define SCG_FIRCCSR_LK_MASK 0x800000u
9543 #define SCG_FIRCCSR_LK_SHIFT 23u
9544 #define SCG_FIRCCSR_LK_WIDTH 1u
9545 #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_LK_SHIFT))&SCG_FIRCCSR_LK_MASK)
9546 #define SCG_FIRCCSR_FIRCVLD_MASK 0x1000000u
9547 #define SCG_FIRCCSR_FIRCVLD_SHIFT 24u
9548 #define SCG_FIRCCSR_FIRCVLD_WIDTH 1u
9549 #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCVLD_SHIFT))&SCG_FIRCCSR_FIRCVLD_MASK)
9550 #define SCG_FIRCCSR_FIRCSEL_MASK 0x2000000u
9551 #define SCG_FIRCCSR_FIRCSEL_SHIFT 25u
9552 #define SCG_FIRCCSR_FIRCSEL_WIDTH 1u
9553 #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCSEL_SHIFT))&SCG_FIRCCSR_FIRCSEL_MASK)
9554 #define SCG_FIRCCSR_FIRCERR_MASK 0x4000000u
9555 #define SCG_FIRCCSR_FIRCERR_SHIFT 26u
9556 #define SCG_FIRCCSR_FIRCERR_WIDTH 1u
9557 #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCERR_SHIFT))&SCG_FIRCCSR_FIRCERR_MASK)
9558 /* FIRCDIV Bit Fields */
9559 #define SCG_FIRCDIV_FIRCDIV1_MASK 0x7u
9560 #define SCG_FIRCDIV_FIRCDIV1_SHIFT 0u
9561 #define SCG_FIRCDIV_FIRCDIV1_WIDTH 3u
9562 #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV1_SHIFT))&SCG_FIRCDIV_FIRCDIV1_MASK)
9563 #define SCG_FIRCDIV_FIRCDIV2_MASK 0x700u
9564 #define SCG_FIRCDIV_FIRCDIV2_SHIFT 8u
9565 #define SCG_FIRCDIV_FIRCDIV2_WIDTH 3u
9566 #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV2_SHIFT))&SCG_FIRCDIV_FIRCDIV2_MASK)
9567 /* FIRCCFG Bit Fields */
9568 #define SCG_FIRCCFG_RANGE_MASK 0x3u
9569 #define SCG_FIRCCFG_RANGE_SHIFT 0u
9570 #define SCG_FIRCCFG_RANGE_WIDTH 2u
9571 #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCFG_RANGE_SHIFT))&SCG_FIRCCFG_RANGE_MASK)
9572  /* end of group SCG_Register_Masks */
9576 
9577  /* end of group SCG_Peripheral_Access_Layer */
9581 
9582 
9583 /* ----------------------------------------------------------------------------
9584  -- SIM Peripheral Access Layer
9585  ---------------------------------------------------------------------------- */
9586 
9596 typedef struct {
9597  uint8_t RESERVED_0[4];
9598  __IO uint32_t CHIPCTL;
9599  uint8_t RESERVED_1[4];
9600  __IO uint32_t FTMOPT0;
9601  __IO uint32_t LPOCLKS;
9602  uint8_t RESERVED_2[4];
9603  __IO uint32_t ADCOPT;
9604  __IO uint32_t FTMOPT1;
9605  __IO uint32_t MISCTRL0;
9606  __I uint32_t SDID;
9607  uint8_t RESERVED_3[24];
9608  __IO uint32_t PLATCGC;
9609  uint8_t RESERVED_4[8];
9610  __IO uint32_t FCFG1;
9611  uint8_t RESERVED_5[4];
9612  __I uint32_t UIDH;
9613  __I uint32_t UIDMH;
9614  __I uint32_t UIDML;
9615  __I uint32_t UIDL;
9616  uint8_t RESERVED_6[4];
9617  __IO uint32_t CLKDIV4;
9618  __IO uint32_t MISCTRL1;
9620 
9622 #define SIM_INSTANCE_COUNT (1u)
9623 
9624 
9625 /* SIM - Peripheral instance base addresses */
9627 #define SIM_BASE (0x40048000u)
9628 
9629 #define SIM ((SIM_Type *)SIM_BASE)
9630 
9631 #define SIM_BASE_ADDRS { SIM_BASE }
9632 
9633 #define SIM_BASE_PTRS { SIM }
9634 
9635 /* ----------------------------------------------------------------------------
9636  -- SIM Register Masks
9637  ---------------------------------------------------------------------------- */
9638 
9644 /* CHIPCTL Bit Fields */
9645 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK 0xFu
9646 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT 0u
9647 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_WIDTH 4u
9648 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT))&SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK)
9649 #define SIM_CHIPCTL_CLKOUTSEL_MASK 0xF0u
9650 #define SIM_CHIPCTL_CLKOUTSEL_SHIFT 4u
9651 #define SIM_CHIPCTL_CLKOUTSEL_WIDTH 4u
9652 #define SIM_CHIPCTL_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTSEL_SHIFT))&SIM_CHIPCTL_CLKOUTSEL_MASK)
9653 #define SIM_CHIPCTL_CLKOUTDIV_MASK 0x700u
9654 #define SIM_CHIPCTL_CLKOUTDIV_SHIFT 8u
9655 #define SIM_CHIPCTL_CLKOUTDIV_WIDTH 3u
9656 #define SIM_CHIPCTL_CLKOUTDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTDIV_SHIFT))&SIM_CHIPCTL_CLKOUTDIV_MASK)
9657 #define SIM_CHIPCTL_CLKOUTEN_MASK 0x800u
9658 #define SIM_CHIPCTL_CLKOUTEN_SHIFT 11u
9659 #define SIM_CHIPCTL_CLKOUTEN_WIDTH 1u
9660 #define SIM_CHIPCTL_CLKOUTEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTEN_SHIFT))&SIM_CHIPCTL_CLKOUTEN_MASK)
9661 #define SIM_CHIPCTL_TRACECLK_SEL_MASK 0x1000u
9662 #define SIM_CHIPCTL_TRACECLK_SEL_SHIFT 12u
9663 #define SIM_CHIPCTL_TRACECLK_SEL_WIDTH 1u
9664 #define SIM_CHIPCTL_TRACECLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_TRACECLK_SEL_SHIFT))&SIM_CHIPCTL_TRACECLK_SEL_MASK)
9665 #define SIM_CHIPCTL_PDB_BB_SEL_MASK 0x2000u
9666 #define SIM_CHIPCTL_PDB_BB_SEL_SHIFT 13u
9667 #define SIM_CHIPCTL_PDB_BB_SEL_WIDTH 1u
9668 #define SIM_CHIPCTL_PDB_BB_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_PDB_BB_SEL_SHIFT))&SIM_CHIPCTL_PDB_BB_SEL_MASK)
9669 #define SIM_CHIPCTL_ADC_SUPPLY_MASK 0x70000u
9670 #define SIM_CHIPCTL_ADC_SUPPLY_SHIFT 16u
9671 #define SIM_CHIPCTL_ADC_SUPPLY_WIDTH 3u
9672 #define SIM_CHIPCTL_ADC_SUPPLY(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLY_SHIFT))&SIM_CHIPCTL_ADC_SUPPLY_MASK)
9673 #define SIM_CHIPCTL_ADC_SUPPLYEN_MASK 0x80000u
9674 #define SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT 19u
9675 #define SIM_CHIPCTL_ADC_SUPPLYEN_WIDTH 1u
9676 #define SIM_CHIPCTL_ADC_SUPPLYEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT))&SIM_CHIPCTL_ADC_SUPPLYEN_MASK)
9677 #define SIM_CHIPCTL_SRAMU_RETEN_MASK 0x100000u
9678 #define SIM_CHIPCTL_SRAMU_RETEN_SHIFT 20u
9679 #define SIM_CHIPCTL_SRAMU_RETEN_WIDTH 1u
9680 #define SIM_CHIPCTL_SRAMU_RETEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAMU_RETEN_SHIFT))&SIM_CHIPCTL_SRAMU_RETEN_MASK)
9681 #define SIM_CHIPCTL_SRAML_RETEN_MASK 0x200000u
9682 #define SIM_CHIPCTL_SRAML_RETEN_SHIFT 21u
9683 #define SIM_CHIPCTL_SRAML_RETEN_WIDTH 1u
9684 #define SIM_CHIPCTL_SRAML_RETEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAML_RETEN_SHIFT))&SIM_CHIPCTL_SRAML_RETEN_MASK)
9685 /* FTMOPT0 Bit Fields */
9686 #define SIM_FTMOPT0_FTM0FLTxSEL_MASK 0x7u
9687 #define SIM_FTMOPT0_FTM0FLTxSEL_SHIFT 0u
9688 #define SIM_FTMOPT0_FTM0FLTxSEL_WIDTH 3u
9689 #define SIM_FTMOPT0_FTM0FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM0FLTxSEL_MASK)
9690 #define SIM_FTMOPT0_FTM1FLTxSEL_MASK 0x70u
9691 #define SIM_FTMOPT0_FTM1FLTxSEL_SHIFT 4u
9692 #define SIM_FTMOPT0_FTM1FLTxSEL_WIDTH 3u
9693 #define SIM_FTMOPT0_FTM1FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM1FLTxSEL_MASK)
9694 #define SIM_FTMOPT0_FTM2FLTxSEL_MASK 0x700u
9695 #define SIM_FTMOPT0_FTM2FLTxSEL_SHIFT 8u
9696 #define SIM_FTMOPT0_FTM2FLTxSEL_WIDTH 3u
9697 #define SIM_FTMOPT0_FTM2FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM2FLTxSEL_MASK)
9698 #define SIM_FTMOPT0_FTM3FLTxSEL_MASK 0x7000u
9699 #define SIM_FTMOPT0_FTM3FLTxSEL_SHIFT 12u
9700 #define SIM_FTMOPT0_FTM3FLTxSEL_WIDTH 3u
9701 #define SIM_FTMOPT0_FTM3FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM3FLTxSEL_MASK)
9702 #define SIM_FTMOPT0_FTM0CLKSEL_MASK 0x3000000u
9703 #define SIM_FTMOPT0_FTM0CLKSEL_SHIFT 24u
9704 #define SIM_FTMOPT0_FTM0CLKSEL_WIDTH 2u
9705 #define SIM_FTMOPT0_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0CLKSEL_SHIFT))&SIM_FTMOPT0_FTM0CLKSEL_MASK)
9706 #define SIM_FTMOPT0_FTM1CLKSEL_MASK 0xC000000u
9707 #define SIM_FTMOPT0_FTM1CLKSEL_SHIFT 26u
9708 #define SIM_FTMOPT0_FTM1CLKSEL_WIDTH 2u
9709 #define SIM_FTMOPT0_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1CLKSEL_SHIFT))&SIM_FTMOPT0_FTM1CLKSEL_MASK)
9710 #define SIM_FTMOPT0_FTM2CLKSEL_MASK 0x30000000u
9711 #define SIM_FTMOPT0_FTM2CLKSEL_SHIFT 28u
9712 #define SIM_FTMOPT0_FTM2CLKSEL_WIDTH 2u
9713 #define SIM_FTMOPT0_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2CLKSEL_SHIFT))&SIM_FTMOPT0_FTM2CLKSEL_MASK)
9714 #define SIM_FTMOPT0_FTM3CLKSEL_MASK 0xC0000000u
9715 #define SIM_FTMOPT0_FTM3CLKSEL_SHIFT 30u
9716 #define SIM_FTMOPT0_FTM3CLKSEL_WIDTH 2u
9717 #define SIM_FTMOPT0_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3CLKSEL_SHIFT))&SIM_FTMOPT0_FTM3CLKSEL_MASK)
9718 /* LPOCLKS Bit Fields */
9719 #define SIM_LPOCLKS_LPO1KCLKEN_MASK 0x1u
9720 #define SIM_LPOCLKS_LPO1KCLKEN_SHIFT 0u
9721 #define SIM_LPOCLKS_LPO1KCLKEN_WIDTH 1u
9722 #define SIM_LPOCLKS_LPO1KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO1KCLKEN_SHIFT))&SIM_LPOCLKS_LPO1KCLKEN_MASK)
9723 #define SIM_LPOCLKS_LPO32KCLKEN_MASK 0x2u
9724 #define SIM_LPOCLKS_LPO32KCLKEN_SHIFT 1u
9725 #define SIM_LPOCLKS_LPO32KCLKEN_WIDTH 1u
9726 #define SIM_LPOCLKS_LPO32KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO32KCLKEN_SHIFT))&SIM_LPOCLKS_LPO32KCLKEN_MASK)
9727 #define SIM_LPOCLKS_LPOCLKSEL_MASK 0xCu
9728 #define SIM_LPOCLKS_LPOCLKSEL_SHIFT 2u
9729 #define SIM_LPOCLKS_LPOCLKSEL_WIDTH 2u
9730 #define SIM_LPOCLKS_LPOCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPOCLKSEL_SHIFT))&SIM_LPOCLKS_LPOCLKSEL_MASK)
9731 #define SIM_LPOCLKS_RTCCLKSEL_MASK 0x30u
9732 #define SIM_LPOCLKS_RTCCLKSEL_SHIFT 4u
9733 #define SIM_LPOCLKS_RTCCLKSEL_WIDTH 2u
9734 #define SIM_LPOCLKS_RTCCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_RTCCLKSEL_SHIFT))&SIM_LPOCLKS_RTCCLKSEL_MASK)
9735 /* ADCOPT Bit Fields */
9736 #define SIM_ADCOPT_ADC0TRGSEL_MASK 0x1u
9737 #define SIM_ADCOPT_ADC0TRGSEL_SHIFT 0u
9738 #define SIM_ADCOPT_ADC0TRGSEL_WIDTH 1u
9739 #define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0TRGSEL_SHIFT))&SIM_ADCOPT_ADC0TRGSEL_MASK)
9740 #define SIM_ADCOPT_ADC0SWPRETRG_MASK 0xEu
9741 #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT 1u
9742 #define SIM_ADCOPT_ADC0SWPRETRG_WIDTH 3u
9743 #define SIM_ADCOPT_ADC0SWPRETRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0SWPRETRG_SHIFT))&SIM_ADCOPT_ADC0SWPRETRG_MASK)
9744 #define SIM_ADCOPT_ADC0PRETRGSEL_MASK 0x30u
9745 #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT 4u
9746 #define SIM_ADCOPT_ADC0PRETRGSEL_WIDTH 2u
9747 #define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC0PRETRGSEL_MASK)
9748 #define SIM_ADCOPT_ADC1TRGSEL_MASK 0x100u
9749 #define SIM_ADCOPT_ADC1TRGSEL_SHIFT 8u
9750 #define SIM_ADCOPT_ADC1TRGSEL_WIDTH 1u
9751 #define SIM_ADCOPT_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1TRGSEL_SHIFT))&SIM_ADCOPT_ADC1TRGSEL_MASK)
9752 #define SIM_ADCOPT_ADC1SWPRETRG_MASK 0xE00u
9753 #define SIM_ADCOPT_ADC1SWPRETRG_SHIFT 9u
9754 #define SIM_ADCOPT_ADC1SWPRETRG_WIDTH 3u
9755 #define SIM_ADCOPT_ADC1SWPRETRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1SWPRETRG_SHIFT))&SIM_ADCOPT_ADC1SWPRETRG_MASK)
9756 #define SIM_ADCOPT_ADC1PRETRGSEL_MASK 0x3000u
9757 #define SIM_ADCOPT_ADC1PRETRGSEL_SHIFT 12u
9758 #define SIM_ADCOPT_ADC1PRETRGSEL_WIDTH 2u
9759 #define SIM_ADCOPT_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC1PRETRGSEL_MASK)
9760 /* FTMOPT1 Bit Fields */
9761 #define SIM_FTMOPT1_FTM0SYNCBIT_MASK 0x1u
9762 #define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT 0u
9763 #define SIM_FTMOPT1_FTM0SYNCBIT_WIDTH 1u
9764 #define SIM_FTMOPT1_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM0SYNCBIT_MASK)
9765 #define SIM_FTMOPT1_FTM1SYNCBIT_MASK 0x2u
9766 #define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT 1u
9767 #define SIM_FTMOPT1_FTM1SYNCBIT_WIDTH 1u
9768 #define SIM_FTMOPT1_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM1SYNCBIT_MASK)
9769 #define SIM_FTMOPT1_FTM2SYNCBIT_MASK 0x4u
9770 #define SIM_FTMOPT1_FTM2SYNCBIT_SHIFT 2u
9771 #define SIM_FTMOPT1_FTM2SYNCBIT_WIDTH 1u
9772 #define SIM_FTMOPT1_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM2SYNCBIT_MASK)
9773 #define SIM_FTMOPT1_FTM3SYNCBIT_MASK 0x8u
9774 #define SIM_FTMOPT1_FTM3SYNCBIT_SHIFT 3u
9775 #define SIM_FTMOPT1_FTM3SYNCBIT_WIDTH 1u
9776 #define SIM_FTMOPT1_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM3SYNCBIT_MASK)
9777 #define SIM_FTMOPT1_FTM1CH0SEL_MASK 0x30u
9778 #define SIM_FTMOPT1_FTM1CH0SEL_SHIFT 4u
9779 #define SIM_FTMOPT1_FTM1CH0SEL_WIDTH 2u
9780 #define SIM_FTMOPT1_FTM1CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1CH0SEL_SHIFT))&SIM_FTMOPT1_FTM1CH0SEL_MASK)
9781 #define SIM_FTMOPT1_FTM2CH0SEL_MASK 0xC0u
9782 #define SIM_FTMOPT1_FTM2CH0SEL_SHIFT 6u
9783 #define SIM_FTMOPT1_FTM2CH0SEL_WIDTH 2u
9784 #define SIM_FTMOPT1_FTM2CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH0SEL_SHIFT))&SIM_FTMOPT1_FTM2CH0SEL_MASK)
9785 #define SIM_FTMOPT1_FTM2CH1SEL_MASK 0x100u
9786 #define SIM_FTMOPT1_FTM2CH1SEL_SHIFT 8u
9787 #define SIM_FTMOPT1_FTM2CH1SEL_WIDTH 1u
9788 #define SIM_FTMOPT1_FTM2CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH1SEL_SHIFT))&SIM_FTMOPT1_FTM2CH1SEL_MASK)
9789 #define SIM_FTMOPT1_FTMGLDOK_MASK 0x8000u
9790 #define SIM_FTMOPT1_FTMGLDOK_SHIFT 15u
9791 #define SIM_FTMOPT1_FTMGLDOK_WIDTH 1u
9792 #define SIM_FTMOPT1_FTMGLDOK(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTMGLDOK_SHIFT))&SIM_FTMOPT1_FTMGLDOK_MASK)
9793 #define SIM_FTMOPT1_FTM0_OUTSEL_MASK 0xFF0000u
9794 #define SIM_FTMOPT1_FTM0_OUTSEL_SHIFT 16u
9795 #define SIM_FTMOPT1_FTM0_OUTSEL_WIDTH 8u
9796 #define SIM_FTMOPT1_FTM0_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM0_OUTSEL_MASK)
9797 #define SIM_FTMOPT1_FTM3_OUTSEL_MASK 0xFF000000u
9798 #define SIM_FTMOPT1_FTM3_OUTSEL_SHIFT 24u
9799 #define SIM_FTMOPT1_FTM3_OUTSEL_WIDTH 8u
9800 #define SIM_FTMOPT1_FTM3_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM3_OUTSEL_MASK)
9801 /* MISCTRL0 Bit Fields */
9802 #define SIM_MISCTRL0_FTM0_OBE_CTRL_MASK 0x10000u
9803 #define SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT 16u
9804 #define SIM_MISCTRL0_FTM0_OBE_CTRL_WIDTH 1u
9805 #define SIM_MISCTRL0_FTM0_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM0_OBE_CTRL_MASK)
9806 #define SIM_MISCTRL0_FTM1_OBE_CTRL_MASK 0x20000u
9807 #define SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT 17u
9808 #define SIM_MISCTRL0_FTM1_OBE_CTRL_WIDTH 1u
9809 #define SIM_MISCTRL0_FTM1_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM1_OBE_CTRL_MASK)
9810 #define SIM_MISCTRL0_FTM2_OBE_CTRL_MASK 0x40000u
9811 #define SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT 18u
9812 #define SIM_MISCTRL0_FTM2_OBE_CTRL_WIDTH 1u
9813 #define SIM_MISCTRL0_FTM2_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM2_OBE_CTRL_MASK)
9814 #define SIM_MISCTRL0_FTM3_OBE_CTRL_MASK 0x80000u
9815 #define SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT 19u
9816 #define SIM_MISCTRL0_FTM3_OBE_CTRL_WIDTH 1u
9817 #define SIM_MISCTRL0_FTM3_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM3_OBE_CTRL_MASK)
9818 /* SDID Bit Fields */
9819 #define SIM_SDID_FEATURES_MASK 0xFFu
9820 #define SIM_SDID_FEATURES_SHIFT 0u
9821 #define SIM_SDID_FEATURES_WIDTH 8u
9822 #define SIM_SDID_FEATURES(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FEATURES_SHIFT))&SIM_SDID_FEATURES_MASK)
9823 #define SIM_SDID_PACKAGE_MASK 0xF00u
9824 #define SIM_SDID_PACKAGE_SHIFT 8u
9825 #define SIM_SDID_PACKAGE_WIDTH 4u
9826 #define SIM_SDID_PACKAGE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PACKAGE_SHIFT))&SIM_SDID_PACKAGE_MASK)
9827 #define SIM_SDID_REVID_MASK 0xF000u
9828 #define SIM_SDID_REVID_SHIFT 12u
9829 #define SIM_SDID_REVID_WIDTH 4u
9830 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
9831 #define SIM_SDID_RAMSIZE_MASK 0xF0000u
9832 #define SIM_SDID_RAMSIZE_SHIFT 16u
9833 #define SIM_SDID_RAMSIZE_WIDTH 4u
9834 #define SIM_SDID_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_RAMSIZE_SHIFT))&SIM_SDID_RAMSIZE_MASK)
9835 #define SIM_SDID_DERIVATE_MASK 0xF00000u
9836 #define SIM_SDID_DERIVATE_SHIFT 20u
9837 #define SIM_SDID_DERIVATE_WIDTH 4u
9838 #define SIM_SDID_DERIVATE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DERIVATE_SHIFT))&SIM_SDID_DERIVATE_MASK)
9839 #define SIM_SDID_SUBSERIES_MASK 0xF000000u
9840 #define SIM_SDID_SUBSERIES_SHIFT 24u
9841 #define SIM_SDID_SUBSERIES_WIDTH 4u
9842 #define SIM_SDID_SUBSERIES(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBSERIES_SHIFT))&SIM_SDID_SUBSERIES_MASK)
9843 #define SIM_SDID_GENERATION_MASK 0xF0000000u
9844 #define SIM_SDID_GENERATION_SHIFT 28u
9845 #define SIM_SDID_GENERATION_WIDTH 4u
9846 #define SIM_SDID_GENERATION(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_GENERATION_SHIFT))&SIM_SDID_GENERATION_MASK)
9847 /* PLATCGC Bit Fields */
9848 #define SIM_PLATCGC_CGCMSCM_MASK 0x1u
9849 #define SIM_PLATCGC_CGCMSCM_SHIFT 0u
9850 #define SIM_PLATCGC_CGCMSCM_WIDTH 1u
9851 #define SIM_PLATCGC_CGCMSCM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMSCM_SHIFT))&SIM_PLATCGC_CGCMSCM_MASK)
9852 #define SIM_PLATCGC_CGCMPU_MASK 0x2u
9853 #define SIM_PLATCGC_CGCMPU_SHIFT 1u
9854 #define SIM_PLATCGC_CGCMPU_WIDTH 1u
9855 #define SIM_PLATCGC_CGCMPU(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMPU_SHIFT))&SIM_PLATCGC_CGCMPU_MASK)
9856 #define SIM_PLATCGC_CGCDMA_MASK 0x4u
9857 #define SIM_PLATCGC_CGCDMA_SHIFT 2u
9858 #define SIM_PLATCGC_CGCDMA_WIDTH 1u
9859 #define SIM_PLATCGC_CGCDMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCDMA_SHIFT))&SIM_PLATCGC_CGCDMA_MASK)
9860 #define SIM_PLATCGC_CGCERM_MASK 0x8u
9861 #define SIM_PLATCGC_CGCERM_SHIFT 3u
9862 #define SIM_PLATCGC_CGCERM_WIDTH 1u
9863 #define SIM_PLATCGC_CGCERM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCERM_SHIFT))&SIM_PLATCGC_CGCERM_MASK)
9864 #define SIM_PLATCGC_CGCEIM_MASK 0x10u
9865 #define SIM_PLATCGC_CGCEIM_SHIFT 4u
9866 #define SIM_PLATCGC_CGCEIM_WIDTH 1u
9867 #define SIM_PLATCGC_CGCEIM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCEIM_SHIFT))&SIM_PLATCGC_CGCEIM_MASK)
9868 /* FCFG1 Bit Fields */
9869 #define SIM_FCFG1_DEPART_MASK 0xF000u
9870 #define SIM_FCFG1_DEPART_SHIFT 12u
9871 #define SIM_FCFG1_DEPART_WIDTH 4u
9872 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
9873 #define SIM_FCFG1_EEERAMSIZE_MASK 0xF0000u
9874 #define SIM_FCFG1_EEERAMSIZE_SHIFT 16u
9875 #define SIM_FCFG1_EEERAMSIZE_WIDTH 4u
9876 #define SIM_FCFG1_EEERAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EEERAMSIZE_SHIFT))&SIM_FCFG1_EEERAMSIZE_MASK)
9877 /* UIDH Bit Fields */
9878 #define SIM_UIDH_UID127_96_MASK 0xFFFFFFFFu
9879 #define SIM_UIDH_UID127_96_SHIFT 0u
9880 #define SIM_UIDH_UID127_96_WIDTH 32u
9881 #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID127_96_SHIFT))&SIM_UIDH_UID127_96_MASK)
9882 /* UIDMH Bit Fields */
9883 #define SIM_UIDMH_UID95_64_MASK 0xFFFFFFFFu
9884 #define SIM_UIDMH_UID95_64_SHIFT 0u
9885 #define SIM_UIDMH_UID95_64_WIDTH 32u
9886 #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID95_64_SHIFT))&SIM_UIDMH_UID95_64_MASK)
9887 /* UIDML Bit Fields */
9888 #define SIM_UIDML_UID63_32_MASK 0xFFFFFFFFu
9889 #define SIM_UIDML_UID63_32_SHIFT 0u
9890 #define SIM_UIDML_UID63_32_WIDTH 32u
9891 #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID63_32_SHIFT))&SIM_UIDML_UID63_32_MASK)
9892 /* UIDL Bit Fields */
9893 #define SIM_UIDL_UID31_0_MASK 0xFFFFFFFFu
9894 #define SIM_UIDL_UID31_0_SHIFT 0u
9895 #define SIM_UIDL_UID31_0_WIDTH 32u
9896 #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID31_0_SHIFT))&SIM_UIDL_UID31_0_MASK)
9897 /* CLKDIV4 Bit Fields */
9898 #define SIM_CLKDIV4_TRACEFRAC_MASK 0x1u
9899 #define SIM_CLKDIV4_TRACEFRAC_SHIFT 0u
9900 #define SIM_CLKDIV4_TRACEFRAC_WIDTH 1u
9901 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEFRAC_SHIFT))&SIM_CLKDIV4_TRACEFRAC_MASK)
9902 #define SIM_CLKDIV4_TRACEDIV_MASK 0xEu
9903 #define SIM_CLKDIV4_TRACEDIV_SHIFT 1u
9904 #define SIM_CLKDIV4_TRACEDIV_WIDTH 3u
9905 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIV_SHIFT))&SIM_CLKDIV4_TRACEDIV_MASK)
9906 #define SIM_CLKDIV4_TRACEDIVEN_MASK 0x10000000u
9907 #define SIM_CLKDIV4_TRACEDIVEN_SHIFT 28u
9908 #define SIM_CLKDIV4_TRACEDIVEN_WIDTH 1u
9909 #define SIM_CLKDIV4_TRACEDIVEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIVEN_SHIFT))&SIM_CLKDIV4_TRACEDIVEN_MASK)
9910 /* MISCTRL1 Bit Fields */
9911 #define SIM_MISCTRL1_SW_TRG_MASK 0x1u
9912 #define SIM_MISCTRL1_SW_TRG_SHIFT 0u
9913 #define SIM_MISCTRL1_SW_TRG_WIDTH 1u
9914 #define SIM_MISCTRL1_SW_TRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL1_SW_TRG_SHIFT))&SIM_MISCTRL1_SW_TRG_MASK)
9915  /* end of group SIM_Register_Masks */
9919 
9920  /* end of group SIM_Peripheral_Access_Layer */
9924 
9925 
9926 /* ----------------------------------------------------------------------------
9927  -- SMC Peripheral Access Layer
9928  ---------------------------------------------------------------------------- */
9929 
9939 typedef struct {
9940  __I uint32_t VERID;
9941  __I uint32_t PARAM;
9942  __IO uint32_t PMPROT;
9943  __IO uint32_t PMCTRL;
9944  __IO uint32_t STOPCTRL;
9945  __I uint32_t PMSTAT;
9947 
9949 #define SMC_INSTANCE_COUNT (1u)
9950 
9951 
9952 /* SMC - Peripheral instance base addresses */
9954 #define SMC_BASE (0x4007E000u)
9955 
9956 #define SMC ((SMC_Type *)SMC_BASE)
9957 
9958 #define SMC_BASE_ADDRS { SMC_BASE }
9959 
9960 #define SMC_BASE_PTRS { SMC }
9961 
9962 /* ----------------------------------------------------------------------------
9963  -- SMC Register Masks
9964  ---------------------------------------------------------------------------- */
9965 
9971 /* VERID Bit Fields */
9972 #define SMC_VERID_FEATURE_MASK 0xFFFFu
9973 #define SMC_VERID_FEATURE_SHIFT 0u
9974 #define SMC_VERID_FEATURE_WIDTH 16u
9975 #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_FEATURE_SHIFT))&SMC_VERID_FEATURE_MASK)
9976 #define SMC_VERID_MINOR_MASK 0xFF0000u
9977 #define SMC_VERID_MINOR_SHIFT 16u
9978 #define SMC_VERID_MINOR_WIDTH 8u
9979 #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MINOR_SHIFT))&SMC_VERID_MINOR_MASK)
9980 #define SMC_VERID_MAJOR_MASK 0xFF000000u
9981 #define SMC_VERID_MAJOR_SHIFT 24u
9982 #define SMC_VERID_MAJOR_WIDTH 8u
9983 #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MAJOR_SHIFT))&SMC_VERID_MAJOR_MASK)
9984 /* PARAM Bit Fields */
9985 #define SMC_PARAM_EHSRUN_MASK 0x1u
9986 #define SMC_PARAM_EHSRUN_SHIFT 0u
9987 #define SMC_PARAM_EHSRUN_WIDTH 1u
9988 #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EHSRUN_SHIFT))&SMC_PARAM_EHSRUN_MASK)
9989 #define SMC_PARAM_ELLS_MASK 0x8u
9990 #define SMC_PARAM_ELLS_SHIFT 3u
9991 #define SMC_PARAM_ELLS_WIDTH 1u
9992 #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS_SHIFT))&SMC_PARAM_ELLS_MASK)
9993 #define SMC_PARAM_ELLS2_MASK 0x20u
9994 #define SMC_PARAM_ELLS2_SHIFT 5u
9995 #define SMC_PARAM_ELLS2_WIDTH 1u
9996 #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS2_SHIFT))&SMC_PARAM_ELLS2_MASK)
9997 #define SMC_PARAM_EVLLS0_MASK 0x40u
9998 #define SMC_PARAM_EVLLS0_SHIFT 6u
9999 #define SMC_PARAM_EVLLS0_WIDTH 1u
10000 #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EVLLS0_SHIFT))&SMC_PARAM_EVLLS0_MASK)
10001 /* PMPROT Bit Fields */
10002 #define SMC_PMPROT_AVLP_MASK 0x20u
10003 #define SMC_PMPROT_AVLP_SHIFT 5u
10004 #define SMC_PMPROT_AVLP_WIDTH 1u
10005 #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
10006 /* PMCTRL Bit Fields */
10007 #define SMC_PMCTRL_STOPM_MASK 0x7u
10008 #define SMC_PMCTRL_STOPM_SHIFT 0u
10009 #define SMC_PMCTRL_STOPM_WIDTH 3u
10010 #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
10011 #define SMC_PMCTRL_VLPSA_MASK 0x8u
10012 #define SMC_PMCTRL_VLPSA_SHIFT 3u
10013 #define SMC_PMCTRL_VLPSA_WIDTH 1u
10014 #define SMC_PMCTRL_VLPSA(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_VLPSA_SHIFT))&SMC_PMCTRL_VLPSA_MASK)
10015 #define SMC_PMCTRL_RUNM_MASK 0x60u
10016 #define SMC_PMCTRL_RUNM_SHIFT 5u
10017 #define SMC_PMCTRL_RUNM_WIDTH 2u
10018 #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
10019 /* STOPCTRL Bit Fields */
10020 #define SMC_STOPCTRL_STOPO_MASK 0xC0u
10021 #define SMC_STOPCTRL_STOPO_SHIFT 6u
10022 #define SMC_STOPCTRL_STOPO_WIDTH 2u
10023 #define SMC_STOPCTRL_STOPO(x) (((uint32_t)(((uint32_t)(x))<<SMC_STOPCTRL_STOPO_SHIFT))&SMC_STOPCTRL_STOPO_MASK)
10024 /* PMSTAT Bit Fields */
10025 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
10026 #define SMC_PMSTAT_PMSTAT_SHIFT 0u
10027 #define SMC_PMSTAT_PMSTAT_WIDTH 8u
10028 #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
10029  /* end of group SMC_Register_Masks */
10033 
10034  /* end of group SMC_Peripheral_Access_Layer */
10038 
10039 
10040 /* ----------------------------------------------------------------------------
10041  -- TRGMUX Peripheral Access Layer
10042  ---------------------------------------------------------------------------- */
10043 
10051 #define TRGMUX_TRGMUXn_COUNT 26u
10052 
10054 typedef struct {
10055  __IO uint32_t TRGMUXn[TRGMUX_TRGMUXn_COUNT];
10057 
10059 #define TRGMUX_INSTANCE_COUNT (1u)
10060 
10061 
10062 /* TRGMUX - Peripheral instance base addresses */
10064 #define TRGMUX_BASE (0x40063000u)
10065 
10066 #define TRGMUX ((TRGMUX_Type *)TRGMUX_BASE)
10067 
10068 #define TRGMUX_BASE_ADDRS { TRGMUX_BASE }
10069 
10070 #define TRGMUX_BASE_PTRS { TRGMUX }
10071 
10072 /* TRGMUX index offsets */
10073 #define TRGMUX_DMAMUX0_INDEX 0
10074 #define TRGMUX_EXTOUT0_INDEX 1
10075 #define TRGMUX_EXTOUT1_INDEX 2
10076 #define TRGMUX_ADC0_INDEX 3
10077 #define TRGMUX_CMP0_INDEX 7
10078 #define TRGMUX_FTM0_INDEX 10
10079 #define TRGMUX_FTM1_INDEX 11
10080 #define TRGMUX_PDB0_INDEX 14
10081 #define TRGMUX_FLEXIO_INDEX 17
10082 #define TRGMUX_LPIT0_INDEX 18
10083 #define TRGMUX_LPUART0_INDEX 19
10084 #define TRGMUX_LPUART1_INDEX 20
10085 #define TRGMUX_LPI2C0_INDEX 21
10086 #define TRGMUX_LPSPI0_INDEX 23
10087 #define TRGMUX_LPSPI1_INDEX 24
10088 #define TRGMUX_LPTMR0_INDEX 25
10089 
10090 /* ----------------------------------------------------------------------------
10091  -- TRGMUX Register Masks
10092  ---------------------------------------------------------------------------- */
10093 
10099 /* TRGMUXn Bit Fields */
10100 #define TRGMUX_TRGMUXn_SEL0_MASK 0x3Fu
10101 #define TRGMUX_TRGMUXn_SEL0_SHIFT 0u
10102 #define TRGMUX_TRGMUXn_SEL0_WIDTH 6u
10103 #define TRGMUX_TRGMUXn_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL0_SHIFT))&TRGMUX_TRGMUXn_SEL0_MASK)
10104 #define TRGMUX_TRGMUXn_SEL1_MASK 0x3F00u
10105 #define TRGMUX_TRGMUXn_SEL1_SHIFT 8u
10106 #define TRGMUX_TRGMUXn_SEL1_WIDTH 6u
10107 #define TRGMUX_TRGMUXn_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL1_SHIFT))&TRGMUX_TRGMUXn_SEL1_MASK)
10108 #define TRGMUX_TRGMUXn_SEL2_MASK 0x3F0000u
10109 #define TRGMUX_TRGMUXn_SEL2_SHIFT 16u
10110 #define TRGMUX_TRGMUXn_SEL2_WIDTH 6u
10111 #define TRGMUX_TRGMUXn_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL2_SHIFT))&TRGMUX_TRGMUXn_SEL2_MASK)
10112 #define TRGMUX_TRGMUXn_SEL3_MASK 0x3F000000u
10113 #define TRGMUX_TRGMUXn_SEL3_SHIFT 24u
10114 #define TRGMUX_TRGMUXn_SEL3_WIDTH 6u
10115 #define TRGMUX_TRGMUXn_SEL3(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL3_SHIFT))&TRGMUX_TRGMUXn_SEL3_MASK)
10116 #define TRGMUX_TRGMUXn_LK_MASK 0x80000000u
10117 #define TRGMUX_TRGMUXn_LK_SHIFT 31u
10118 #define TRGMUX_TRGMUXn_LK_WIDTH 1u
10119 #define TRGMUX_TRGMUXn_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_LK_SHIFT))&TRGMUX_TRGMUXn_LK_MASK)
10120  /* end of group TRGMUX_Register_Masks */
10124 
10125  /* end of group TRGMUX_Peripheral_Access_Layer */
10129 
10130 
10131 /* ----------------------------------------------------------------------------
10132  -- WDOG Peripheral Access Layer
10133  ---------------------------------------------------------------------------- */
10134 
10144 typedef struct {
10145  __IO uint32_t CS;
10146  __IO uint32_t CNT;
10147  __IO uint32_t TOVAL;
10148  __IO uint32_t WIN;
10150 
10152 #define WDOG_INSTANCE_COUNT (1u)
10153 
10154 
10155 /* WDOG - Peripheral instance base addresses */
10157 #define WDOG_BASE (0x40052000u)
10158 
10159 #define WDOG ((WDOG_Type *)WDOG_BASE)
10160 
10161 #define WDOG_BASE_ADDRS { WDOG_BASE }
10162 
10163 #define WDOG_BASE_PTRS { WDOG }
10164 
10165 #define WDOG_IRQS_ARR_COUNT (1u)
10166 
10167 #define WDOG_IRQS_CH_COUNT (1u)
10168 
10169 #define WDOG_IRQS { WDOG_IRQn }
10170 
10171 /* ----------------------------------------------------------------------------
10172  -- WDOG Register Masks
10173  ---------------------------------------------------------------------------- */
10174 
10180 /* CS Bit Fields */
10181 #define WDOG_CS_STOP_MASK 0x1u
10182 #define WDOG_CS_STOP_SHIFT 0u
10183 #define WDOG_CS_STOP_WIDTH 1u
10184 #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_STOP_SHIFT))&WDOG_CS_STOP_MASK)
10185 #define WDOG_CS_WAIT_MASK 0x2u
10186 #define WDOG_CS_WAIT_SHIFT 1u
10187 #define WDOG_CS_WAIT_WIDTH 1u
10188 #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WAIT_SHIFT))&WDOG_CS_WAIT_MASK)
10189 #define WDOG_CS_DBG_MASK 0x4u
10190 #define WDOG_CS_DBG_SHIFT 2u
10191 #define WDOG_CS_DBG_WIDTH 1u
10192 #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_DBG_SHIFT))&WDOG_CS_DBG_MASK)
10193 #define WDOG_CS_TST_MASK 0x18u
10194 #define WDOG_CS_TST_SHIFT 3u
10195 #define WDOG_CS_TST_WIDTH 2u
10196 #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_TST_SHIFT))&WDOG_CS_TST_MASK)
10197 #define WDOG_CS_UPDATE_MASK 0x20u
10198 #define WDOG_CS_UPDATE_SHIFT 5u
10199 #define WDOG_CS_UPDATE_WIDTH 1u
10200 #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_UPDATE_SHIFT))&WDOG_CS_UPDATE_MASK)
10201 #define WDOG_CS_INT_MASK 0x40u
10202 #define WDOG_CS_INT_SHIFT 6u
10203 #define WDOG_CS_INT_WIDTH 1u
10204 #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_INT_SHIFT))&WDOG_CS_INT_MASK)
10205 #define WDOG_CS_EN_MASK 0x80u
10206 #define WDOG_CS_EN_SHIFT 7u
10207 #define WDOG_CS_EN_WIDTH 1u
10208 #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_EN_SHIFT))&WDOG_CS_EN_MASK)
10209 #define WDOG_CS_CLK_MASK 0x300u
10210 #define WDOG_CS_CLK_SHIFT 8u
10211 #define WDOG_CS_CLK_WIDTH 2u
10212 #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CLK_SHIFT))&WDOG_CS_CLK_MASK)
10213 #define WDOG_CS_RCS_MASK 0x400u
10214 #define WDOG_CS_RCS_SHIFT 10u
10215 #define WDOG_CS_RCS_WIDTH 1u
10216 #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_RCS_SHIFT))&WDOG_CS_RCS_MASK)
10217 #define WDOG_CS_ULK_MASK 0x800u
10218 #define WDOG_CS_ULK_SHIFT 11u
10219 #define WDOG_CS_ULK_WIDTH 1u
10220 #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_ULK_SHIFT))&WDOG_CS_ULK_MASK)
10221 #define WDOG_CS_PRES_MASK 0x1000u
10222 #define WDOG_CS_PRES_SHIFT 12u
10223 #define WDOG_CS_PRES_WIDTH 1u
10224 #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_PRES_SHIFT))&WDOG_CS_PRES_MASK)
10225 #define WDOG_CS_CMD32EN_MASK 0x2000u
10226 #define WDOG_CS_CMD32EN_SHIFT 13u
10227 #define WDOG_CS_CMD32EN_WIDTH 1u
10228 #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CMD32EN_SHIFT))&WDOG_CS_CMD32EN_MASK)
10229 #define WDOG_CS_FLG_MASK 0x4000u
10230 #define WDOG_CS_FLG_SHIFT 14u
10231 #define WDOG_CS_FLG_WIDTH 1u
10232 #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_FLG_SHIFT))&WDOG_CS_FLG_MASK)
10233 #define WDOG_CS_WIN_MASK 0x8000u
10234 #define WDOG_CS_WIN_SHIFT 15u
10235 #define WDOG_CS_WIN_WIDTH 1u
10236 #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WIN_SHIFT))&WDOG_CS_WIN_MASK)
10237 /* CNT Bit Fields */
10238 #define WDOG_CNT_CNTLOW_MASK 0xFFu
10239 #define WDOG_CNT_CNTLOW_SHIFT 0u
10240 #define WDOG_CNT_CNTLOW_WIDTH 8u
10241 #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTLOW_SHIFT))&WDOG_CNT_CNTLOW_MASK)
10242 #define WDOG_CNT_CNTHIGH_MASK 0xFF00u
10243 #define WDOG_CNT_CNTHIGH_SHIFT 8u
10244 #define WDOG_CNT_CNTHIGH_WIDTH 8u
10245 #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTHIGH_SHIFT))&WDOG_CNT_CNTHIGH_MASK)
10246 /* TOVAL Bit Fields */
10247 #define WDOG_TOVAL_TOVALLOW_MASK 0xFFu
10248 #define WDOG_TOVAL_TOVALLOW_SHIFT 0u
10249 #define WDOG_TOVAL_TOVALLOW_WIDTH 8u
10250 #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALLOW_SHIFT))&WDOG_TOVAL_TOVALLOW_MASK)
10251 #define WDOG_TOVAL_TOVALHIGH_MASK 0xFF00u
10252 #define WDOG_TOVAL_TOVALHIGH_SHIFT 8u
10253 #define WDOG_TOVAL_TOVALHIGH_WIDTH 8u
10254 #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALHIGH_SHIFT))&WDOG_TOVAL_TOVALHIGH_MASK)
10255 /* WIN Bit Fields */
10256 #define WDOG_WIN_WINLOW_MASK 0xFFu
10257 #define WDOG_WIN_WINLOW_SHIFT 0u
10258 #define WDOG_WIN_WINLOW_WIDTH 8u
10259 #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINLOW_SHIFT))&WDOG_WIN_WINLOW_MASK)
10260 #define WDOG_WIN_WINHIGH_MASK 0xFF00u
10261 #define WDOG_WIN_WINHIGH_SHIFT 8u
10262 #define WDOG_WIN_WINHIGH_WIDTH 8u
10263 #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINHIGH_SHIFT))&WDOG_WIN_WINHIGH_MASK)
10264  /* end of group WDOG_Register_Masks */
10268 
10269  /* end of group WDOG_Peripheral_Access_Layer */
10273 
10274  /* end of group Peripheral_access_layer_S32K118 */
10278 
10279 
10280 /* ----------------------------------------------------------------------------
10281  -- Backward Compatibility for S32K118
10282  ---------------------------------------------------------------------------- */
10283 
10289 /* No backward compatibility issues. */
10290  /* end of group Backward_Compatibility_Symbols_S32K118 */
10294 
10295 
10296 #else /* #if !defined(S32K118_H_) */
10297  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
10298  #if (MCU_MEM_MAP_VERSION != 0x0100u)
10299  #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
10300  #warning There are included two not compatible versions of memory maps. Please check possible differences.
10301  #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
10302  #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
10303 #endif /* #if !defined(S32K118_H_) */
10304 
10305 /* S32K118.h, eof. */
volatile uint32_t TVAL
Definition: S32K118.h:5813
#define FTM_CV_MIRROR_COUNT
Definition: S32K118.h:3823
volatile const uint32_t VERID
Definition: S32K118.h:5184
volatile uint32_t MIER
Definition: S32K118.h:5189
volatile uint32_t SETTEN
Definition: S32K118.h:5809
volatile const uint32_t WMBn_ID
Definition: S32K118.h:829
volatile uint32_t CnSC
Definition: S32K118.h:3831
volatile uint32_t WATER
Definition: S32K118.h:6530
volatile uint32_t INT
Definition: S32K118.h:2228
volatile const uint32_t MRDR
Definition: S32K118.h:5206
volatile uint32_t PLATCGC
Definition: S32K118.h:9608
struct RTC_Type * RTC_MemMapPtr
volatile uint32_t CLP0_OFS
Definition: S32K118.h:293
volatile const uint32_t CPxTYPE
Definition: S32K118.h:7575
struct PORT_Type * PORT_MemMapPtr
volatile uint32_t CLP1_OFS
Definition: S32K118.h:292
struct DMAMUX_Type * DMAMUX_MemMapPtr
volatile uint16_t DOFF
Definition: S32K118.h:2249
volatile uint32_t FLTCTRL
Definition: S32K118.h:3846
#define FTM_CONTROLS_COUNT
Definition: S32K118.h:3822
volatile uint32_t TIMIEN
Definition: S32K118.h:3326
volatile const uint32_t VERID
Definition: S32K118.h:9322
volatile uint32_t SAMR
Definition: S32K118.h:5216
volatile const uint8_t FOPT
Definition: S32K118.h:3620
volatile const uint32_t SDID
Definition: S32K118.h:9606
volatile uint32_t SC
Definition: S32K118.h:3827
#define FLEXIO_TIMCFG_COUNT
Definition: S32K118.h:3311
volatile uint32_t GPOLY
Definition: S32K118.h:1985
volatile const uint32_t UIDML
Definition: S32K118.h:9614
volatile uint32_t CFGR0
Definition: S32K118.h:6031
struct LPUART_Type * LPUART_MemMapPtr
volatile uint32_t FCR
Definition: S32K118.h:6039
volatile const uint32_t EDR
Definition: S32K118.h:7297
volatile uint32_t MCCR0
Definition: S32K118.h:5198
volatile uint32_t CTRL2
Definition: S32K118.h:804
volatile uint32_t DEADTIME
Definition: S32K118.h:3841
volatile uint32_t CONF
Definition: S32K118.h:3848
volatile uint32_t LMDR2
Definition: S32K118.h:7054
volatile uint32_t SIER
Definition: S32K118.h:5210
volatile const uint32_t ES
Definition: S32K118.h:2214
volatile uint32_t IER
Definition: S32K118.h:8746
volatile uint32_t MSR
Definition: S32K118.h:5807
#define EIM_EICHDn_COUNT
Definition: S32K118.h:3138
volatile uint32_t PDDR
Definition: S32K118.h:4872
volatile const uint32_t RDR
Definition: S32K118.h:6045
volatile uint32_t PCOR
Definition: S32K118.h:4869
volatile uint32_t SHIFTSDEN
Definition: S32K118.h:3328
volatile uint8_t SERQ
Definition: S32K118.h:2222
#define S32_NVIC_ICER_COUNT
Definition: S32K118.h:8920
#define FLEXIO_SHIFTCFG_COUNT
Definition: S32K118.h:3305
volatile const uint32_t HRS
Definition: S32K118.h:2232
volatile uint32_t CLP2_OFS
Definition: S32K118.h:291
#define PORT_PCR_COUNT
Definition: S32K118.h:8266
volatile uint8_t DATA_8HU
Definition: S32K118.h:2121
volatile uint32_t FIRCDIV
Definition: S32K118.h:9340
volatile uint8_t CERR
Definition: S32K118.h:2225
volatile const uint32_t PARAM
Definition: S32K118.h:5185
volatile uint32_t STDR
Definition: S32K118.h:5221
volatile uint32_t CLPX_OFS
Definition: S32K118.h:294
volatile uint32_t FTMOPT1
Definition: S32K118.h:9604
struct TRGMUX_Type * TRGMUX_MemMapPtr
volatile uint32_t SR
Definition: S32K118.h:8744
volatile uint32_t EXTTRIG
Definition: S32K118.h:3842
volatile uint32_t OUTINIT
Definition: S32K118.h:3838
volatile uint32_t CFG2
Definition: S32K118.h:270
volatile uint32_t SCR
Definition: S32K118.h:5208
volatile uint32_t DATA
Definition: S32K118.h:1973
volatile uint8_t CDNE
Definition: S32K118.h:2223
volatile uint8_t LVDSC1
Definition: S32K118.h:8152
volatile uint32_t STOPCTRL
Definition: S32K118.h:9944
volatile uint32_t DFSR
Definition: S32K118.h:9037
volatile const uint32_t CPxNUM
Definition: S32K118.h:7576
volatile uint32_t S
Definition: S32K118.h:7969
volatile uint32_t LMPEIR
Definition: S32K118.h:7058
volatile uint32_t MCFGR1
Definition: S32K118.h:5192
volatile uint32_t PMCTRL
Definition: S32K118.h:9943
#define S32_NVIC_ISER_COUNT
Definition: S32K118.h:8919
volatile uint32_t OFS
Definition: S32K118.h:276
volatile uint32_t MCFGR3
Definition: S32K118.h:5194
volatile uint32_t WORD1
Definition: S32K118.h:7304
volatile uint32_t UG
Definition: S32K118.h:281
struct CAN_Type * CAN_MemMapPtr
struct DMA_Type * DMA_MemMapPtr
volatile uint32_t CNT
Definition: S32K118.h:10146
volatile uint32_t CR0
Definition: S32K118.h:3220
volatile uint32_t BAUD
Definition: S32K118.h:6523
volatile uint32_t CLKDIV4
Definition: S32K118.h:9617
volatile uint32_t CHIPCTL
Definition: S32K118.h:9598
volatile uint32_t ERR
Definition: S32K118.h:2230
volatile uint32_t PWMLOAD
Definition: S32K118.h:3853
volatile uint32_t CNR
Definition: S32K118.h:6406
volatile const uint32_t LMFDHR
Definition: S32K118.h:7063
volatile const uint32_t CP0NUM
Definition: S32K118.h:7584
volatile uint32_t LTCR
Definition: S32K118.h:1855
volatile uint32_t CNTIN
Definition: S32K118.h:3834
volatile uint32_t EIMCR
Definition: S32K118.h:3142
volatile uint32_t GICHR
Definition: S32K118.h:8274
struct LPTMR_Type * LPTMR_MemMapPtr
struct ADC_Type * ADC_MemMapPtr
volatile uint32_t MDER
Definition: S32K118.h:5190
volatile uint8_t CERQ
Definition: S32K118.h:2221
volatile uint32_t OUTMASK
Definition: S32K118.h:3839
volatile uint32_t FDCTRL
Definition: S32K118.h:834
volatile uint32_t LPOCLKS
Definition: S32K118.h:9601
volatile uint32_t MLOFFYES
Definition: S32K118.h:2245
#define FTFC_FPROT_COUNT
Definition: S32K118.h:3613
volatile const uint32_t CSR
Definition: S32K118.h:9325
struct LMEM_Type * LMEM_MemMapPtr
volatile uint32_t C2
Definition: S32K118.h:1604
volatile uint8_t SSRT
Definition: S32K118.h:2224
volatile uint32_t CPO
Definition: S32K118.h:7051
#define __IO
Definition: S32K118.h:128
volatile uint32_t GLOBAL
Definition: S32K118.h:6521
struct FTM_Type * FTM_MemMapPtr
volatile uint16_t DLY2
Definition: S32K118.h:7977
volatile uint32_t PTOR
Definition: S32K118.h:4870
struct LPSPI_Type * LPSPI_MemMapPtr
volatile uint32_t SLAST
Definition: S32K118.h:2247
#define PDB_POnDLY_COUNT
Definition: S32K118.h:7959
volatile uint32_t SC
Definition: S32K118.h:7963
volatile uint32_t PSR
Definition: S32K118.h:6404
volatile uint32_t RCCR
Definition: S32K118.h:1853
volatile uint32_t MSR
Definition: S32K118.h:5188
volatile uint32_t LMPECR
Definition: S32K118.h:7056
volatile uint32_t MODIR
Definition: S32K118.h:6528
volatile const uint32_t PARAM
Definition: S32K118.h:3317
#define FLEXIO_SHIFTBUFBYS_COUNT
Definition: S32K118.h:3308
volatile const uint32_t CP0CFG2
Definition: S32K118.h:7589
volatile uint32_t MISCTRL1
Definition: S32K118.h:9618
volatile uint32_t YOFS
Definition: S32K118.h:279
volatile uint32_t WORD2
Definition: S32K118.h:7305
struct SIM_Type * SIM_MemMapPtr
volatile uint32_t CLP2
Definition: S32K118.h:284
volatile uint32_t SHIFTEIEN
Definition: S32K118.h:3325
volatile uint32_t RXMGMASK
Definition: S32K118.h:795
volatile uint32_t EICHEN
Definition: S32K118.h:3143
volatile uint32_t C1
Definition: S32K118.h:1603
volatile uint8_t FERCNFG
Definition: S32K118.h:3630
#define FLEXIO_SHIFTBUFBIS_COUNT
Definition: S32K118.h:3307
volatile uint32_t PDOR
Definition: S32K118.h:4867
struct EIM_Type * EIM_MemMapPtr
struct PMC_Type * PMC_MemMapPtr
volatile uint32_t DLASTSGA
Definition: S32K118.h:2254
volatile uint32_t SHIFTSIEN
Definition: S32K118.h:3324
volatile uint32_t FMS
Definition: S32K118.h:3844
volatile uint8_t LU
Definition: S32K118.h:1980
volatile const uint32_t ESR2
Definition: S32K118.h:805
volatile uint32_t SOSCCFG
Definition: S32K118.h:9333
volatile uint32_t ISFR
Definition: S32K118.h:8276
volatile uint32_t SR
Definition: S32K118.h:1856
#define ADC_R_COUNT
Definition: S32K118.h:263
volatile uint32_t RX14MASK
Definition: S32K118.h:796
volatile uint32_t DMR1
Definition: S32K118.h:6035
volatile uint32_t DER
Definition: S32K118.h:6030
volatile uint32_t HTCR
Definition: S32K118.h:1854
volatile uint32_t SRIE
Definition: S32K118.h:8448
volatile uint32_t MFCR
Definition: S32K118.h:5202
volatile uint32_t FLT_ID1
Definition: S32K118.h:819
#define ERM_EARn_COUNT
Definition: S32K118.h:3216
volatile uint32_t MATCH
Definition: S32K118.h:6527
volatile const uint16_t PLASC
Definition: S32K118.h:7045
volatile const uint32_t PARAM
Definition: S32K118.h:6520
#define MSCM_OCMDR_COUNT
Definition: S32K118.h:7571
volatile uint32_t SIRCCFG
Definition: S32K118.h:9337
volatile uint32_t FLT_ID2_IDMASK
Definition: S32K118.h:823
struct WDOG_Type * WDOG_MemMapPtr
volatile uint32_t PIDR
Definition: S32K118.h:4873
volatile uint32_t PL1_LO
Definition: S32K118.h:821
volatile uint32_t MPRA
Definition: S32K118.h:562
volatile uint32_t POEN
Definition: S32K118.h:7973
struct MPU_Type * MPU_MemMapPtr
volatile const uint32_t UIDL
Definition: S32K118.h:9615
volatile uint32_t CFG1
Definition: S32K118.h:269
volatile uint32_t SYNCONF
Definition: S32K118.h:3850
#define LPIT_TMR_COUNT
Definition: S32K118.h:5800
volatile uint32_t FLT_DLC
Definition: S32K118.h:820
volatile uint32_t CTRL
Definition: S32K118.h:6525
volatile uint16_t SOFF
Definition: S32K118.h:2240
volatile uint32_t DATA_32
Definition: S32K118.h:2116
volatile uint32_t SR0
Definition: S32K118.h:3222
volatile uint8_t FERSTAT
Definition: S32K118.h:3629
volatile const uint32_t CPxCOUNT
Definition: S32K118.h:7578
#define DMA_TCD_COUNT
Definition: S32K118.h:2209
volatile uint32_t CLPS_OFS
Definition: S32K118.h:289
volatile const uint32_t CRCR
Definition: S32K118.h:807
volatile const uint8_t FCSESTAT
Definition: S32K118.h:3627
volatile uint32_t QDCTRL
Definition: S32K118.h:3847
volatile uint32_t FTMOPT0
Definition: S32K118.h:9600
volatile uint32_t SDER
Definition: S32K118.h:5211
volatile uint32_t GPCHR
Definition: S32K118.h:8272
volatile uint32_t MODE
Definition: S32K118.h:3836
volatile uint32_t MLNO
Definition: S32K118.h:2243
volatile uint32_t CLPS
Definition: S32K118.h:282
volatile uint32_t TPR
Definition: S32K118.h:8740
volatile uint32_t IFLAG1
Definition: S32K118.h:803
volatile const uint32_t CPUID
Definition: S32K118.h:9026
volatile uint32_t PSOR
Definition: S32K118.h:4868
struct MSCM_Type * MSCM_MemMapPtr
volatile uint32_t SCFGR1
Definition: S32K118.h:5213
#define S32_NVIC_ISPR_COUNT
Definition: S32K118.h:8921
volatile uint32_t SHPR2
Definition: S32K118.h:9033
volatile const uint16_t PLAMC
Definition: S32K118.h:7046
volatile uint32_t STATUS
Definition: S32K118.h:3835
volatile uint32_t PAIR1DEADTIME
Definition: S32K118.h:3857
volatile uint32_t SYNC
Definition: S32K118.h:3837
volatile uint8_t FEPROT
Definition: S32K118.h:3624
volatile uint32_t SR
Definition: S32K118.h:6028
volatile uint8_t REGSC
Definition: S32K118.h:8154
volatile uint32_t CLP0
Definition: S32K118.h:286
struct PDB_Type * PDB_MemMapPtr
#define TRGMUX_TRGMUXn_COUNT
Definition: S32K118.h:10051
volatile const uint32_t LMFAR
Definition: S32K118.h:7060
volatile uint32_t PL1_HI
Definition: S32K118.h:822
#define CAN_WMB_COUNT
Definition: S32K118.h:787
volatile uint32_t SCFGR2
Definition: S32K118.h:5214
volatile uint32_t CLP3
Definition: S32K118.h:283
volatile uint32_t PL2_PLMASK_LO
Definition: S32K118.h:824
volatile const uint32_t VERID
Definition: S32K118.h:8442
volatile uint32_t PCCCR
Definition: S32K118.h:4975
volatile uint32_t EARS
Definition: S32K118.h:2234
volatile const uint32_t PARAM
Definition: S32K118.h:5805
volatile uint32_t TOVAL
Definition: S32K118.h:10147
volatile uint32_t MCR
Definition: S32K118.h:5806
volatile uint32_t MCFGR0
Definition: S32K118.h:5191
#define __O
Definition: S32K118.h:127
volatile uint32_t DFCR
Definition: S32K118.h:8279
volatile uint8_t DATA_8LL
Definition: S32K118.h:2118
volatile uint32_t MCR
Definition: S32K118.h:791
volatile uint32_t ECR
Definition: S32K118.h:798
volatile uint16_t H
Definition: S32K118.h:1976
volatile uint32_t CCR
Definition: S32K118.h:6037
volatile uint32_t SSR
Definition: S32K118.h:5209
#define CAN_RAMn_COUNT
Definition: S32K118.h:785
volatile uint32_t GICLR
Definition: S32K118.h:8273
volatile uint32_t CLKOUTCNFG
Definition: S32K118.h:9329
volatile const uint32_t PMSTAT
Definition: S32K118.h:9945
#define FTFC_FCCOB_COUNT
Definition: S32K118.h:3612
volatile uint32_t CLP1
Definition: S32K118.h:285
struct CRC_Type * CRC_MemMapPtr
#define AIPS_PACR_COUNT
Definition: S32K118.h:557
volatile uint32_t WORD1
Definition: S32K118.h:3147
volatile uint32_t SIRCCSR
Definition: S32K118.h:9335
volatile const uint32_t ACTLR
Definition: S32K118.h:9024
volatile uint32_t SC3
Definition: S32K118.h:274
volatile uint32_t MOD_MIRROR
Definition: S32K118.h:3863
volatile uint32_t TCR
Definition: S32K118.h:6041
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K118.h:188
volatile uint32_t RPC
Definition: S32K118.h:8445
volatile uint32_t LR
Definition: S32K118.h:8745
volatile uint32_t CLP3_OFS
Definition: S32K118.h:290
volatile const uint32_t PARAM
Definition: S32K118.h:6025
volatile const uint32_t CP0CFG0
Definition: S32K118.h:7587
#define MPU_RGDAAC_COUNT
Definition: S32K118.h:7287
volatile const uint32_t LMFATR
Definition: S32K118.h:7061
struct GPIO_Type * GPIO_MemMapPtr
volatile uint32_t SHPR3
Definition: S32K118.h:9034
volatile uint32_t USR_OFS
Definition: S32K118.h:277
volatile const uint8_t FSEC
Definition: S32K118.h:3619
struct CMU_FC_Type * CMU_FC_MemMapPtr
volatile uint32_t SSRS
Definition: S32K118.h:8447
struct S32_NVIC_Type * S32_NVIC_MemMapPtr
#define PCC_PCCn_COUNT
Definition: S32K118.h:7857
volatile uint32_t VCCR
Definition: S32K118.h:9327
struct SCG_Type * SCG_MemMapPtr
volatile const uint32_t VERID
Definition: S32K118.h:3316
volatile uint32_t RX15MASK
Definition: S32K118.h:797
volatile uint8_t LPOTRIM
Definition: S32K118.h:8156
volatile uint32_t FIRCCSR
Definition: S32K118.h:9339
volatile uint32_t CR
Definition: S32K118.h:8743
volatile uint32_t MLOFFNO
Definition: S32K118.h:2244
struct ERM_Type * ERM_MemMapPtr
volatile const uint32_t EAR
Definition: S32K118.h:7294
struct CMP_Type * CMP_MemMapPtr
volatile const uint32_t SRS
Definition: S32K118.h:8444
volatile uint32_t PAIR3DEADTIME
Definition: S32K118.h:3861
volatile const uint32_t CP0COUNT
Definition: S32K118.h:7586
volatile uint32_t PL2_PLMASK_HI
Definition: S32K118.h:825
#define MPU_RGD_COUNT
Definition: S32K118.h:7286
volatile uint32_t GCR
Definition: S32K118.h:1852
volatile uint32_t SADDR
Definition: S32K118.h:2239
volatile uint32_t FCFG1
Definition: S32K118.h:9610
#define S32_NVIC_ICPR_COUNT
Definition: S32K118.h:8922
volatile const uint32_t SRDR
Definition: S32K118.h:5223
volatile uint32_t SHCSR
Definition: S32K118.h:9035
volatile uint8_t DATA_8HL
Definition: S32K118.h:2120
volatile uint32_t IER
Definition: S32K118.h:6029
volatile const uint32_t CPxCFG1
Definition: S32K118.h:7580
#define DMAMUX_CHCFG_COUNT
Definition: S32K118.h:3073
#define FLEXIO_SHIFTBUF_COUNT
Definition: S32K118.h:3306
volatile uint32_t PODLY
Definition: S32K118.h:7975
volatile uint32_t MISCTRL0
Definition: S32K118.h:9605
volatile uint32_t SWOCTRL
Definition: S32K118.h:3852
#define S32_NVIC_IPR_COUNT
Definition: S32K118.h:8923
volatile uint32_t TAR
Definition: S32K118.h:8741
volatile const uint32_t WMBn_D03
Definition: S32K118.h:830
volatile const uint32_t WMBn_CS
Definition: S32K118.h:828
volatile uint32_t BASE_OFS
Definition: S32K118.h:275
volatile uint32_t CnV
Definition: S32K118.h:3832
volatile uint32_t C0
Definition: S32K118.h:1602
volatile const uint32_t UIDMH
Definition: S32K118.h:9613
volatile uint32_t CTRL2_PN
Definition: S32K118.h:817
struct LPIT_Type * LPIT_MemMapPtr
volatile uint32_t CTRL
Definition: S32K118.h:1986
volatile uint8_t CEEI
Definition: S32K118.h:2219
volatile const uint32_t PARAM
Definition: S32K118.h:9323
volatile uint32_t IMASK1
Definition: S32K118.h:801
volatile uint32_t FILTER
Definition: S32K118.h:3845
struct MCM_Type * MCM_MemMapPtr
volatile uint8_t LL
Definition: S32K118.h:1979
volatile uint32_t SC2
Definition: S32K118.h:273
volatile uint32_t PINCFG
Definition: S32K118.h:6522
volatile uint32_t WORD3
Definition: S32K118.h:7306
volatile uint32_t PCCSAR
Definition: S32K118.h:4977
volatile uint32_t MOD
Definition: S32K118.h:7964
volatile uint32_t XOFS
Definition: S32K118.h:278
volatile uint8_t HL
Definition: S32K118.h:1981
volatile uint32_t MTDR
Definition: S32K118.h:5204
volatile uint32_t PCCRMR
Definition: S32K118.h:4980
volatile uint32_t SHIFTERR
Definition: S32K118.h:3321
volatile uint32_t MCCR1
Definition: S32K118.h:5200
volatile uint32_t CSR
Definition: S32K118.h:9222
volatile uint32_t PAIR2DEADTIME
Definition: S32K118.h:3859
volatile const uint32_t MFSR
Definition: S32K118.h:5203
volatile uint16_t DLY1
Definition: S32K118.h:7978
volatile uint32_t MIER
Definition: S32K118.h:5808
volatile uint32_t CTRL
Definition: S32K118.h:3318
#define FLEXIO_SHIFTBUFBBS_COUNT
Definition: S32K118.h:3309
volatile const uint32_t CPxCFG2
Definition: S32K118.h:7581
volatile uint32_t TIMER
Definition: S32K118.h:793
volatile uint32_t TSR
Definition: S32K118.h:8739
volatile uint32_t COMBINE
Definition: S32K118.h:3840
volatile const uint32_t CPxCFG3
Definition: S32K118.h:7582
volatile uint32_t CR
Definition: S32K118.h:6027
volatile uint32_t FIRCCFG
Definition: S32K118.h:9341
volatile uint32_t DFWR
Definition: S32K118.h:8280
#define FLEXIO_TIMCTL_COUNT
Definition: S32K118.h:3310
volatile const uint32_t RSR
Definition: S32K118.h:6044
volatile uint32_t CLPX
Definition: S32K118.h:287
struct SMC_Type * SMC_MemMapPtr
volatile uint16_t ELINKNO
Definition: S32K118.h:2251
volatile const uint32_t CP0CFG3
Definition: S32K118.h:7590
volatile uint32_t HCR
Definition: S32K118.h:3854
volatile uint32_t CS
Definition: S32K118.h:10145
#define FLEXIO_SHIFTCTL_COUNT
Definition: S32K118.h:3304
volatile uint16_t CSR
Definition: S32K118.h:2255
volatile uint8_t FCNFG
Definition: S32K118.h:3618
volatile uint32_t DMR0
Definition: S32K118.h:6034
struct LPI2C_Type * LPI2C_MemMapPtr
volatile uint32_t CR
Definition: S32K118.h:2213
volatile const uint32_t CCR
Definition: S32K118.h:9031
volatile uint32_t DFER
Definition: S32K118.h:8278
volatile const uint32_t SASR
Definition: S32K118.h:5218
volatile uint32_t CPCR
Definition: S32K118.h:7047
volatile uint32_t PAIR0DEADTIME
Definition: S32K118.h:3855
volatile const uint32_t FSR
Definition: S32K118.h:6040
volatile const uint32_t UIDH
Definition: S32K118.h:9612
volatile uint32_t RCCR
Definition: S32K118.h:9326
#define CAN_RXIMR_COUNT
Definition: S32K118.h:786
volatile uint32_t SOSCDIV
Definition: S32K118.h:9332
volatile uint32_t INVCTRL
Definition: S32K118.h:3851
volatile const uint32_t PIN
Definition: S32K118.h:3319
#define MPU_EAR_EDR_COUNT
Definition: S32K118.h:7285
volatile const uint32_t PDIR
Definition: S32K118.h:4871
volatile uint32_t ADCOPT
Definition: S32K118.h:9603
struct AIPS_Type * AIPS_MemMapPtr
volatile uint8_t SEEI
Definition: S32K118.h:2220
volatile uint32_t WU_MTC
Definition: S32K118.h:818
volatile const uint32_t VERID
Definition: S32K118.h:5804
#define AIPS_OPACR_COUNT
Definition: S32K118.h:558
volatile uint32_t G
Definition: S32K118.h:280
volatile uint32_t DADDR
Definition: S32K118.h:2248
volatile uint32_t WORD0
Definition: S32K118.h:7303
volatile uint32_t VTOR
Definition: S32K118.h:9028
volatile uint32_t CTRL1_PN
Definition: S32K118.h:816
volatile const uint32_t RXFIR
Definition: S32K118.h:809
volatile uint16_t ELINKYES
Definition: S32K118.h:2252
volatile uint32_t CTRL1
Definition: S32K118.h:792
volatile uint32_t DATA
Definition: S32K118.h:6526
#define MCM_LMDR_COUNT
Definition: S32K118.h:7040
volatile uint32_t PCCLCR
Definition: S32K118.h:4976
volatile uint8_t DATA_8LU
Definition: S32K118.h:2119
struct RCM_Type * RCM_MemMapPtr
volatile uint32_t SIRCDIV
Definition: S32K118.h:9336
volatile uint32_t CLP9
Definition: S32K118.h:288
volatile uint32_t ERQ
Definition: S32K118.h:2216
volatile uint16_t ATTR
Definition: S32K118.h:2241
struct S32_SCB_Type * S32_SCB_MemMapPtr
volatile uint32_t CLRTEN
Definition: S32K118.h:5810
volatile uint32_t PID
Definition: S32K118.h:7049
volatile uint32_t WIN
Definition: S32K118.h:10148
struct FLEXIO_Type * FLEXIO_MemMapPtr
volatile uint32_t SHIFTSTAT
Definition: S32K118.h:3320
volatile uint32_t CFGR1
Definition: S32K118.h:6032
volatile const uint32_t CPxCFG0
Definition: S32K118.h:7579
volatile const uint32_t FDCRC
Definition: S32K118.h:836
volatile uint32_t STAT
Definition: S32K118.h:6524
volatile uint32_t ICSR
Definition: S32K118.h:9027
volatile uint32_t PCCCVR
Definition: S32K118.h:4978
volatile const uint32_t CVAL
Definition: S32K118.h:5814
struct CSE_PRAM_Type * CSE_PRAM_MemMapPtr
volatile const uint32_t CPxMASTER
Definition: S32K118.h:7577
#define DMA_DCHPRI_COUNT
Definition: S32K118.h:2208
volatile uint32_t AIRCR
Definition: S32K118.h:9029
#define ADC_CV_COUNT
Definition: S32K118.h:264
volatile uint32_t FIFO
Definition: S32K118.h:6529
volatile uint32_t CNT
Definition: S32K118.h:3828
volatile const uint32_t CNT
Definition: S32K118.h:7965
volatile uint32_t FLTPOL
Definition: S32K118.h:3849
volatile uint32_t CMR
Definition: S32K118.h:6405
volatile uint32_t CVR
Definition: S32K118.h:9224
volatile uint32_t CLP9_OFS
Definition: S32K118.h:295
volatile uint32_t C1
Definition: S32K118.h:7968
volatile uint32_t TDR
Definition: S32K118.h:6042
volatile uint16_t L
Definition: S32K118.h:1975
volatile const uint32_t VERID
Definition: S32K118.h:6519
volatile const uint32_t PARAM
Definition: S32K118.h:8443
volatile uint32_t TIMSTAT
Definition: S32K118.h:3322
volatile const uint32_t CP0CFG1
Definition: S32K118.h:7588
volatile uint32_t POL
Definition: S32K118.h:3843
volatile const uint32_t WMBn_D47
Definition: S32K118.h:831
volatile uint8_t HU
Definition: S32K118.h:1982
volatile uint32_t MCFGR2
Definition: S32K118.h:5193
volatile uint32_t IER
Definition: S32K118.h:1857
volatile uint32_t MOD
Definition: S32K118.h:3829
struct FTFC_Type * FTFC_MemMapPtr
volatile uint32_t TCR
Definition: S32K118.h:8742
volatile uint8_t FDPROT
Definition: S32K118.h:3625
volatile uint32_t ESR1
Definition: S32K118.h:799
volatile const uint32_t CP0MASTER
Definition: S32K118.h:7585
#define ADC_SC1_COUNT
Definition: S32K118.h:262
volatile uint32_t WORD0
Definition: S32K118.h:3146
volatile uint32_t GPCLR
Definition: S32K118.h:8271
struct S32_SysTick_Type * S32_SysTick_MemMapPtr
#define PDB_DLY_COUNT
Definition: S32K118.h:7958
volatile uint32_t CSR
Definition: S32K118.h:6403
struct PCC_Type * PCC_MemMapPtr
#define CSE_PRAM_RAMn_COUNT
Definition: S32K118.h:2111
volatile uint32_t SOSCCSR
Definition: S32K118.h:9331
volatile uint32_t MDMR
Definition: S32K118.h:5196
#define FLEXIO_TIMCMP_COUNT
Definition: S32K118.h:3312
volatile const uint32_t PARAM
Definition: S32K118.h:9941
volatile const uint32_t VERID
Definition: S32K118.h:6024
volatile uint32_t CBT
Definition: S32K118.h:810
volatile const uint32_t CP0TYPE
Definition: S32K118.h:7583
#define __I
Definition: S32K118.h:125
volatile uint32_t MCR
Definition: S32K118.h:5187
volatile uint32_t FDCBT
Definition: S32K118.h:835
volatile const uint32_t CALIB
Definition: S32K118.h:9225
volatile uint8_t FSTAT
Definition: S32K118.h:3617
volatile uint32_t RVR
Definition: S32K118.h:9223
volatile uint32_t RXFGMASK
Definition: S32K118.h:808
volatile uint32_t SCR
Definition: S32K118.h:9030
volatile uint32_t CESR
Definition: S32K118.h:7291
volatile uint32_t EEI
Definition: S32K118.h:2218
volatile uint32_t STAR
Definition: S32K118.h:5219
volatile uint32_t IDLY
Definition: S32K118.h:7966
#define PDB_CH_COUNT
Definition: S32K118.h:7957
volatile const uint32_t VERID
Definition: S32K118.h:9940
volatile uint8_t CINT
Definition: S32K118.h:2226
volatile uint8_t LVDSC2
Definition: S32K118.h:8153
volatile uint32_t PMPROT
Definition: S32K118.h:9942
volatile uint32_t TCTRL
Definition: S32K118.h:5815
volatile const uint32_t LMFDLR
Definition: S32K118.h:7064