adc_irq.c
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
35 #include "adc_pal_cfg.h"
36 #include "adc_irq.h"
37 
38 /*******************************************************************************
39  * Code
40  ******************************************************************************/
41 
42 /* Define default interrupt handlers for ADC instances.
43  * Default interrupt handlers already declared in startup files. */
44 
45 #if defined(ADC_PAL_S32K1xx)
46 
47 #if (ADC_INSTANCE_COUNT >= 1u)
48 void ADC0_IRQHandler(void)
49 {
50  ADC_S32K1xx_IrqHandler(0u);
51 }
52 #endif /* (ADC_INSTANCE_COUNT >= 1u) */
53 
54 #if (ADC_INSTANCE_COUNT >= 2u)
55 void ADC1_IRQHandler(void)
56 {
57  ADC_S32K1xx_IrqHandler(1u);
58 }
59 #endif /* (ADC_INSTANCE_COUNT >= 2u) */
60 
61 #endif /* defined(ADC_PAL_S32K1xx) */
62 
63 
64 #if defined(ADC_PAL_MPC574xC_G_R)
65 
66 /* For HW triggered groups with a single conversion */
67 void BCTU_ConvUpdate_IRQHandler(void)
68 {
69  uint8_t adcIdx = 0u;
70  const uint32_t bctuIdx = 0u; /* For ADC_PAL_MPC574xC_G_R, ADC PAL instances are mapped 1:1 with BCTU instances. */
71 
72  for(adcIdx = 0u; adcIdx < FEATURE_BCTU_NUM_ADC; adcIdx++)
73  {
74  /* ADC PAL doesn't trigger conversions in parallel on multiple ADCs,
75  * so only one ADC should have new data available. */
76  if(BCTU_DRV_GetStatusFlag(bctuIdx, adcIdx, BCTU_FLAG_NEW_DATA_AVAILABLE))
77  {
78  ADC_MPC574xC_G_R_HwTrigIrqHandler(bctuIdx, adcIdx);
79 
80  break;
81  }
82  }
83 }
84 
85 /* For HW triggered groups with multiple conversions */
86 void BCTU_ListLast_IRQHandler(void)
87 {
88  uint8_t adcIdx = 0u;
89  const uint32_t bctuIdx = 0u; /* For ADC_PAL_MPC574xC_G_R, ADC PAL instances are mapped 1:1 with BCTU instances. */
90 
91  for(adcIdx = 0u; adcIdx < FEATURE_BCTU_NUM_ADC; adcIdx++)
92  {
93  /* ADC PAL doesn't trigger conversions in parallel on multiple ADCs,
94  * so only one ADC should have new data available. */
95  if(BCTU_DRV_GetStatusFlag(bctuIdx, adcIdx, BCTU_FLAG_LIST_LAST_CONV))
96  {
97  ADC_MPC574xC_G_R_HwTrigIrqHandler(bctuIdx, adcIdx);
98 
99  break;
100  }
101  }
102 }
103 
104 void ADC0_EOC_IRQHandler(void)
105 {
106  /* For ADC_PAL_MPC574xC_G_R, ADC PAL instances are mapped 1:1 with BCTU instances.
107  * ADC0 is connected to BCTU 0. */
108  const uint32_t palIdx = 0u;
109  ADC_MPC574x_SwTrigIrqHandler(palIdx, 0u);
110 }
111 
112 void ADC1_EOC_IRQHandler(void)
113 {
114  /* For ADC_PAL_MPC574xC_G_R, ADC PAL instances are mapped 1:1 with BCTU instances.
115  * ADC1 is connected to BCTU 0. */
116  const uint32_t palIdx = 0u;
117  ADC_MPC574x_SwTrigIrqHandler(palIdx, 1u);
118 }
119 
120 #endif /* defined(ADC_PAL_MPC574xC_G_R) */
121 
122 
123 #if defined(ADC_PAL_MPC574xP)
124 
125 void CTU0_FIFO0_IRQHandler(void)
126 {
127  const uint32_t palIdx = 0u;
128  ADC_MPC574xP_HwTrigIrqHandler(palIdx, 0u);
129 }
130 
131 void CTU0_FIFO1_IRQHandler(void)
132 {
133  const uint32_t palIdx = 0u;
134  ADC_MPC574xP_HwTrigIrqHandler(palIdx, 1u);
135 }
136 
137 void CTU0_FIFO2_IRQHandler(void)
138 {
139  const uint32_t palIdx = 0u;
140  ADC_MPC574xP_HwTrigIrqHandler(palIdx, 2u);
141 }
142 
143 void CTU0_FIFO3_IRQHandler(void)
144 {
145  const uint32_t palIdx = 0u;
146  ADC_MPC574xP_HwTrigIrqHandler(palIdx, 3u);
147 }
148 
149 void CTU1_FIFO0_IRQHandler(void)
150 {
151  const uint32_t palIdx = 1u;
152  ADC_MPC574xP_HwTrigIrqHandler(palIdx, 0u);
153 }
154 
155 void CTU1_FIFO1_IRQHandler(void)
156 {
157  const uint32_t palIdx = 1u;
158  ADC_MPC574xP_HwTrigIrqHandler(palIdx, 1u);
159 }
160 
161 void CTU1_FIFO2_IRQHandler(void)
162 {
163  const uint32_t palIdx = 1u;
164  ADC_MPC574xP_HwTrigIrqHandler(palIdx, 2u);
165 }
166 
167 void CTU1_FIFO3_IRQHandler(void)
168 {
169  const uint32_t palIdx = 1u;
170  ADC_MPC574xP_HwTrigIrqHandler(palIdx, 3u);
171 }
172 
173 void ADC0_EOC_IRQHandler(void)
174 {
175  /* For ADC_PAL_MPC574xP, ADC PAL instances are mapped 1:1 with CTU instances.
176  * ADC0 is connected to CTU 0. */
177  const uint32_t palIdx = 0u;
178  ADC_MPC574x_SwTrigIrqHandler(palIdx, 0u);
179 }
180 
181 void ADC1_EOC_IRQHandler(void)
182 {
183  /* For ADC_PAL_MPC574xP, ADC PAL instances are mapped 1:1 with CTU instances.
184  * ADC1 is connected to CTU 0. */
185  const uint32_t palIdx = 0u;
186  ADC_MPC574x_SwTrigIrqHandler(palIdx, 1u);
187 }
188 
189 void ADC2_EOC_IRQHandler(void)
190 {
191  /* For ADC_PAL_MPC574xP, ADC PAL instances are mapped 1:1 with CTU instances.
192  * ADC2 is connected to CTU 1. */
193  const uint32_t palIdx = 1u;
194  ADC_MPC574x_SwTrigIrqHandler(palIdx, 2u);
195 }
196 
197 void ADC3_EOC_IRQHandler(void)
198 {
199  /* For ADC_PAL_MPC574xP, ADC PAL instances are mapped 1:1 with CTU instances.
200  * ADC3 is connected to CTU 1. */
201  const uint32_t palIdx = 1u;
202  ADC_MPC574x_SwTrigIrqHandler(palIdx, 3u);
203 }
204 
205 #endif /* defined(ADC_PAL_MPC574xP) */
206 
207 /*******************************************************************************
208  * EOF
209  ******************************************************************************/