i2s_pal.c
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1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
49 #include "i2s_pal.h"
50 
51 /* Include PD files */
52 #if (defined(I2S_OVER_SAI))
53  #include "sai_driver.h"
54 #endif
55 #if (defined(I2S_OVER_FLEXIO))
56  #include "flexio.h"
57  #include "flexio_i2s_driver.h"
58 #endif
59 
60 /* Define state structures for SAI */
61 #if (defined(I2S_OVER_SAI))
62  #define LAST_IS_TX 1U
63  #define LAST_IS_RX 2U
64  #define LAST_IS_NONE 0U
65  /* sai state structures */
66  static sai_state_t saiTxState[NO_OF_SAI_INSTS_FOR_I2S];
67  static sai_state_t saiRxState[NO_OF_SAI_INSTS_FOR_I2S];
68  /* sai state-instance matching */
69  static uint32_t saiStateInstanceMapping[NO_OF_SAI_INSTS_FOR_I2S];
70  /* sai available resources table */
71  static bool saiStateIsAllocated[NO_OF_SAI_INSTS_FOR_I2S];
72  /* record last transfer is tx or rx to call SelectMaster for sai */
73  static uint8_t lastXfer[NO_OF_SAI_INSTS_FOR_I2S];
74 #endif
75 
76 /* Define state structures for i2s over FLEXIO */
77 #if (defined(I2S_OVER_FLEXIO))
78  #define NO_OF_FLEXIO_INSTS_FOR_I2S (NO_OF_FLEXIO_MASTER_INSTS_FOR_I2S+NO_OF_FLEXIO_SLAVE_INSTS_FOR_I2S)
79  /* FLEXIO state structures */
80 #if (NO_OF_FLEXIO_MASTER_INSTS_FOR_I2S > 0U)
81  static flexio_i2s_master_state_t flexioMasterState[NO_OF_FLEXIO_MASTER_INSTS_FOR_I2S];
82  static bool flexioMasterStateIsAllocated[NO_OF_FLEXIO_MASTER_INSTS_FOR_I2S];
83 #endif
84 #if (NO_OF_FLEXIO_SLAVE_INSTS_FOR_I2S > 0U)
85  static flexio_i2s_slave_state_t flexioSlaveState[NO_OF_FLEXIO_SLAVE_INSTS_FOR_I2S];
86  static bool flexioSlaveStateIsAllocated[NO_OF_FLEXIO_SLAVE_INSTS_FOR_I2S];
87 #endif
88  /* flexio device state */
89  static flexio_device_state_t flexioDeviceState;
90  /* state-instance matching table */
91  static uint32_t flexioStateInstanceMapping[NO_OF_FLEXIO_INSTS_FOR_I2S];
92  /* state is master or slave */
93  static bool flexioIsMaster[NO_OF_FLEXIO_INSTS_FOR_I2S];
94  /* pointer to master/slave state */
95  static void* flexioState[NO_OF_FLEXIO_INSTS_FOR_I2S];
96  /* available resources table */
97  static bool flexioStateIsAllocated[NO_OF_FLEXIO_INSTS_FOR_I2S];
98  static uint8_t flexioWordSize[NO_OF_FLEXIO_INSTS_FOR_I2S];
99 #endif
100 
101 #ifdef I2S_OVER_FLEXIO
102 /*FUNCTION**********************************************************************
103  *
104  * Function Name : flexioAllocateState
105  * Description : Allocates one of the available state structures.
106  *
107  *END**************************************************************************/
108 static uint8_t flexioAllocateState(uint32_t instId,
109  bool isMaster)
110 {
111  uint8_t i;
112  uint8_t j;
113  /* Allocate one of the i2s state structures for this instance */
114  for (i = 0; i < NO_OF_FLEXIO_INSTS_FOR_I2S; i++)
115  {
116  if (!flexioStateIsAllocated[i])
117  {
118  flexioStateInstanceMapping[i] = instId;
119  flexioStateIsAllocated[i] = true;
120  flexioIsMaster[i] = isMaster;
121  if (isMaster)
122  {
123 #if (NO_OF_FLEXIO_MASTER_INSTS_FOR_I2S > 0U)
124  for (j = 0; j < NO_OF_FLEXIO_MASTER_INSTS_FOR_I2S; j++)
125  {
126  if (!flexioMasterStateIsAllocated[j])
127  {
128  flexioMasterStateIsAllocated[j] = true;
129  flexioState[i] = &flexioMasterState[j];
130  break;
131  }
132  }
133 #endif
134  }
135  else
136  {
137 #if (NO_OF_FLEXIO_SLAVE_INSTS_FOR_I2S > 0U)
138  for (j = 0; j < NO_OF_FLEXIO_SLAVE_INSTS_FOR_I2S; j++)
139  {
140  if (!flexioSlaveStateIsAllocated[j])
141  {
142  flexioSlaveStateIsAllocated[j] = true;
143  flexioState[i] = &flexioSlaveState[j];
144  break;
145  }
146  }
147 #endif
148  }
149  break;
150  }
151  }
152  return i;
153 }
154 #endif /* I2S_OVER_FLEXIO */
155 
156 #ifdef I2S_OVER_SAI
157 /*FUNCTION**********************************************************************
158  *
159  * Function Name : saiAllocateState
160  * Description : Allocates one of the available state structures.
161  *
162  *END**************************************************************************/
163 static uint8_t saiAllocateState(uint32_t instId)
164 {
165  uint8_t i;
166  for (i = 0; i < NO_OF_SAI_INSTS_FOR_I2S; i++)
167  {
168  if (!saiStateIsAllocated[i])
169  {
170  saiStateIsAllocated[i] = true;
171  saiStateInstanceMapping[i] = instId;
172  break;
173  }
174  }
175  return i;
176 }
177 #endif /* I2S_OVER_SAI */
178 
179 /*FUNCTION**********************************************************************
180  *
181  * Function Name : freeState
182  * Description : free allocated state
183  *
184  *END**************************************************************************/
185 static void freeState(const i2s_instance_t* instance)
186 {
187  uint8_t i;
188 #ifdef I2S_OVER_SAI
189  if (instance->instType == I2S_INST_TYPE_SAI)
190  {
191  for (i = 0; i < NO_OF_SAI_INSTS_FOR_I2S; i++)
192  {
193  if ((saiStateInstanceMapping[i] == instance->instIdx) && saiStateIsAllocated[i])
194  {
195  saiStateIsAllocated[i] = false;
196  break;
197  }
198  }
199  }
200 #endif /* I2S_OVER_SAI */
201 #ifdef I2S_OVER_FLEXIO
202  uint8_t j;
203  if (instance->instType == I2S_INST_TYPE_FLEXIO)
204  {
205  for (i = 0; i < NO_OF_FLEXIO_INSTS_FOR_I2S; i++)
206  {
207  if ((flexioStateInstanceMapping[i] == instance->instIdx) && flexioStateIsAllocated[i])
208  {
209  flexioStateIsAllocated[i] = false;
210  if (flexioIsMaster[i])
211  {
212 #if (NO_OF_FLEXIO_MASTER_INSTS_FOR_I2S > 0U)
213  for (j = 0; j < NO_OF_FLEXIO_MASTER_INSTS_FOR_I2S; j++)
214  {
215  if ((&flexioMasterState[j] == flexioState[i]) && flexioMasterStateIsAllocated[j])
216  {
217  flexioMasterStateIsAllocated[j] = false;
218  }
219  }
220 #endif
221  }
222  else
223  {
224 #if (NO_OF_FLEXIO_SLAVE_INSTS_FOR_I2S > 0U)
225  for (j = 0; j < NO_OF_FLEXIO_SLAVE_INSTS_FOR_I2S; j++)
226  {
227  if ((&flexioSlaveState[j] == flexioState[i]) && flexioSlaveStateIsAllocated[j])
228  {
229  flexioSlaveStateIsAllocated[j] = false;
230  }
231  }
232 #endif
233  }
234  break;
235  }
236  }
237  }
238 #endif /* I2S_OVER_FLEXIO */
239 }
240 
241 /*FUNCTION**********************************************************************
242  *
243  * Function Name : findState
244  * Description : find state index from instance
245  *
246  *END**************************************************************************/
247 static uint8_t findState(uint32_t instance, const uint32_t* instMap, const bool* isAlloc, uint32_t noOfInst)
248 {
249  uint8_t i;
250  for (i = 0; i < noOfInst; i++)
251  {
252  if ((instMap[i] == instance) && isAlloc[i])
253  {
254  break;
255  }
256  }
257  /* cannot find state */
258  DEV_ASSERT(i < noOfInst);
259  return i;
260 }
261 
262 /*FUNCTION**********************************************************************
263  *
264  * Function Name : I2S_Init
265  * Description : initialize driver
266  *
267  * Implements : I2S_Init_Activity
268  *END**************************************************************************/
269 status_t I2S_Init(const i2s_instance_t* instance, const i2s_user_config_t * config)
270 {
271  uint8_t stateIndex;
273 #ifdef I2S_OVER_SAI
274  sai_user_config_t saiUserConfig;
275  if (instance->instType == I2S_INST_TYPE_SAI)
276  {
277  stateIndex = saiAllocateState(instance->instIdx);
278  DEV_ASSERT(stateIndex < NO_OF_SAI_INSTS_FOR_I2S);
279  lastXfer[stateIndex] = LAST_IS_NONE;
280  saiUserConfig.BitClkNegPolar = true;
281  saiUserConfig.ChannelCount = 1U;
282  if (config->wordWidth <= 8U)
283  {
284  saiUserConfig.ElementSize = 1U;
285  }
286  else if (config->wordWidth <= 16U)
287  {
288  saiUserConfig.ElementSize = 2U;
289  }
290  else
291  {
292  saiUserConfig.ElementSize = 4U;
293  }
294  saiUserConfig.FirstBitIndex = (uint8_t)(config->wordWidth - 1U);
295  saiUserConfig.FrameSize = 2U;
296 #ifdef FEATURE_SAI_HAS_CHMOD
297  saiUserConfig.MaskMode = SAI_MASK_TRISTATE;
298 #endif /* FEATURE_SAI_HAS_CHMOD */
299 
300 #ifdef FEATURE_SAI_MSEL_FCD
301  saiUserConfig.MasterClkSrc = SAI_FCD_CLK;
302 #endif /* FEATURE_SAI_MSEL_FCD */
303 #ifdef FEATURE_SAI_MSEL_BUS_CLK
304  saiUserConfig.MasterClkSrc = SAI_BUS_CLK;
305 #endif /* FEATURE_SAI_MSEL_BUS_CLK */
306  saiUserConfig.MsbFirst = true;
307  saiUserConfig.MuxMode = SAI_MUX_DISABLED;
308  saiUserConfig.SyncEarly = true;
309  saiUserConfig.SyncNegPolar = true;
310  saiUserConfig.SyncWidth = config->wordWidth;
311  saiUserConfig.Word0Width = config->wordWidth;
312  saiUserConfig.WordNWidth = config->wordWidth;
313  saiUserConfig.FrameStartReport = false;
314  saiUserConfig.SyncErrorReport = false;
315  saiUserConfig.RunErrorReport = false;
316  if (config->transferType == I2S_USING_DMA)
317  {
318  saiUserConfig.TransferType = SAI_DMA;
319  }
320  else
321  {
322  saiUserConfig.TransferType = SAI_INTERRUPT;
323  }
324  saiUserConfig.callback = (sai_transfer_callback_t) config->callback;
325  saiUserConfig.callbackParam = config->callbackParam;
326  saiUserConfig.BitClkFreq = config->baudRate;
327  saiUserConfig.SyncMode = SAI_ASYNC;
328  /* saiUserConfig.BitClkDiv */
329  saiUserConfig.DmaChannel[0] = config->txDMAChannel;
330  saiUserConfig.ChannelEnable = 1U;
331  if (config->mode == I2S_MASTER)
332  {
333 #ifdef FEATURE_SAI_MSEL_FCD
334  SAI_DRV_FCDInit(instance->instIdx, SAI_FCD_PLL, config->baudRate*2UL, false);
335 #endif /* FEATURE_SAI_MSEL_FCD */
336  saiUserConfig.BitClkInternal = true;
337  saiUserConfig.SyncInternal = true;
338  }
339  else
340  {
341  saiUserConfig.BitClkInternal = false;
342  saiUserConfig.SyncInternal = false;
343  }
344  SAI_DRV_TxInit(instance->instIdx, &saiUserConfig, &saiTxState[stateIndex]);
345  saiUserConfig.DmaChannel[0] = config->rxDMAChannel;
346  if (instance->instIdx == 0UL)
347  {
348  saiUserConfig.ChannelEnable = 2U;
349  }
350  SAI_DRV_RxInit(instance->instIdx, &saiUserConfig, &saiRxState[stateIndex]);
351  ret = STATUS_SUCCESS;
352  }
353 #endif /* I2S_OVER_SAI */
354 #ifdef I2S_OVER_FLEXIO
355  flexio_i2s_master_user_config_t flexioMasterConfig;
356  flexio_i2s_slave_user_config_t flexioSlaveConfig;
357  if (instance->instType == I2S_INST_TYPE_FLEXIO)
358  {
359  stateIndex = flexioAllocateState(instance->instIdx, ((config->mode == I2S_MASTER) ? true : false));
360  DEV_ASSERT(stateIndex < NO_OF_FLEXIO_INSTS_FOR_I2S);
361  ret = FLEXIO_DRV_InitDevice(0UL, &flexioDeviceState);
362  if (ret == STATUS_SUCCESS)
363  {
364  if (config->wordWidth <= 8U)
365  {
366  flexioWordSize[stateIndex] = 1U;
367  }
368  else if (config->wordWidth <= 16U)
369  {
370  flexioWordSize[stateIndex] = 2U;
371  }
372  else
373  {
374  flexioWordSize[stateIndex] = 4U;
375  }
376  if (config->mode == I2S_MASTER)
377  {
378  flexioMasterConfig.baudRate = config->baudRate;
379  flexioMasterConfig.bitsWidth = config->wordWidth;
380  flexioMasterConfig.callback = config->callback;
381  flexioMasterConfig.callbackParam = config->callbackParam;
382  if (config->transferType == I2S_USING_DMA)
383  {
384  flexioMasterConfig.driverType = FLEXIO_DRIVER_TYPE_DMA;
385  }
386  if (config->transferType == I2S_USING_INTERRUPT)
387  {
388  flexioMasterConfig.driverType = FLEXIO_DRIVER_TYPE_INTERRUPTS;
389  }
390  flexioMasterConfig.rxDMAChannel = config->rxDMAChannel;
391  flexioMasterConfig.txDMAChannel = config->txDMAChannel;
392  flexioMasterConfig.rxPin = ((extension_flexio_for_i2s_t*)config->extension)->rxPin;
393  flexioMasterConfig.sckPin = ((extension_flexio_for_i2s_t*)config->extension)->sckPin;
394  flexioMasterConfig.txPin = ((extension_flexio_for_i2s_t*)config->extension)->txPin;
395  flexioMasterConfig.wsPin = ((extension_flexio_for_i2s_t*)config->extension)->wsPin;
396  ret = FLEXIO_I2S_DRV_MasterInit(0, &flexioMasterConfig, flexioState[stateIndex]);
397  }
398  else
399  {
400  flexioSlaveConfig.bitsWidth = config->wordWidth;
401  flexioSlaveConfig.callback = config->callback;
402  flexioSlaveConfig.callbackParam = config->callbackParam;
403  if (config->transferType == I2S_USING_DMA)
404  {
405  flexioSlaveConfig.driverType = FLEXIO_DRIVER_TYPE_DMA;
406  }
407  if (config->transferType == I2S_USING_INTERRUPT)
408  {
409  flexioSlaveConfig.driverType = FLEXIO_DRIVER_TYPE_INTERRUPTS;
410  }
411  flexioSlaveConfig.rxDMAChannel = config->rxDMAChannel;
412  flexioSlaveConfig.txDMAChannel = config->txDMAChannel;
413  flexioSlaveConfig.rxPin = ((extension_flexio_for_i2s_t*)config->extension)->rxPin;
414  flexioSlaveConfig.sckPin = ((extension_flexio_for_i2s_t*)config->extension)->sckPin;
415  flexioSlaveConfig.txPin = ((extension_flexio_for_i2s_t*)config->extension)->txPin;
416  flexioSlaveConfig.wsPin = ((extension_flexio_for_i2s_t*)config->extension)->wsPin;
417  ret = FLEXIO_I2S_DRV_SlaveInit(0, &flexioSlaveConfig, flexioState[stateIndex]);
418  }
419  }
420  }
421 #endif /* I2S_OVER_FLEXIO */
422  return ret;
423 }
424 
425 /*FUNCTION**********************************************************************
426  *
427  * Function Name : I2S_Deinit
428  * Description : deinit driver
429  *
430  * Implements : I2S_Deinit_Activity
431  *END**************************************************************************/
433 {
435 #ifdef I2S_OVER_FLEXIO
436  uint8_t stateIndex;
437  if (instance->instType == I2S_INST_TYPE_FLEXIO)
438  {
439  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
440  if (flexioIsMaster[stateIndex])
441  {
442  ret = FLEXIO_I2S_DRV_MasterDeinit(flexioState[stateIndex]);
443  }
444  else
445  {
446  ret = FLEXIO_I2S_DRV_SlaveDeinit(flexioState[stateIndex]);
447  }
448  if (ret == STATUS_SUCCESS)
449  {
450  freeState(instance);
451  }
452  }
453 #endif /* I2S_OVER_FLEXIO */
454 #ifdef I2S_OVER_SAI
455  if (instance->instType == I2S_INST_TYPE_SAI)
456  {
457  SAI_DRV_TxDeinit(instance->instIdx);
458  SAI_DRV_RxDeinit(instance->instIdx);
459  freeState(instance);
460  ret = STATUS_SUCCESS;
461  }
462 #endif /* I2S_OVER_SAI */
463  return ret;
464 }
465 
466 /*FUNCTION**********************************************************************
467  *
468  * Function Name : I2S_GetBaudRate
469  * Description : return true baud rate
470  *
471  * Implements : I2S_GetBaudRate_Activity
472  *END**************************************************************************/
474  uint32_t * configuredBaudRate)
475 {
477 #ifdef I2S_OVER_FLEXIO
478  uint8_t stateIndex;
479  if (instance->instType == I2S_INST_TYPE_FLEXIO)
480  {
481  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
482  if (flexioIsMaster[stateIndex])
483  {
484  ret = FLEXIO_I2S_DRV_MasterGetBaudRate(flexioState[stateIndex], configuredBaudRate);
485  }
486  }
487 #endif /* I2S_OVER_FLEXIO */
488 #ifdef I2S_OVER_SAI
489  if (instance->instType == I2S_INST_TYPE_SAI)
490  {
491  *configuredBaudRate = SAI_DRV_TxGetBitClockFreq(instance->instIdx);
492  ret = STATUS_SUCCESS;
493  }
494 #endif /* I2S_OVER_SAI */
495  return ret;
496 }
497 
498 /*FUNCTION**********************************************************************
499  *
500  * Function Name : I2S_SendDataBlocking
501  * Description : Send blocking
502  *
503  * Implements : I2S_SendDataBlocking_Activity
504  *END**************************************************************************/
506  const i2s_instance_t* instance,
507  const uint8_t * txBuff,
508  uint32_t txSize,
509  uint32_t timeout)
510 {
512  uint8_t stateIndex;
513 #ifdef I2S_OVER_FLEXIO
514  if (instance->instType == I2S_INST_TYPE_FLEXIO)
515  {
516  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
517  if (flexioIsMaster[stateIndex])
518  {
519  ret = FLEXIO_I2S_DRV_MasterSendDataBlocking(flexioState[stateIndex], txBuff, flexioWordSize[stateIndex] * txSize, timeout);
520  }
521  else
522  {
523  ret = FLEXIO_I2S_DRV_SlaveSendDataBlocking(flexioState[stateIndex], txBuff, flexioWordSize[stateIndex] * txSize, timeout);
524  }
525  }
526 #endif /* I2S_OVER_FLEXIO */
527 #ifdef I2S_OVER_SAI
528  const uint8_t* addr;
529  if (instance->instType == I2S_INST_TYPE_SAI)
530  {
531  stateIndex = findState(instance->instIdx, saiStateInstanceMapping, saiStateIsAllocated, NO_OF_SAI_INSTS_FOR_I2S);
532  if ((lastXfer[stateIndex] == LAST_IS_NONE) || (lastXfer[stateIndex] == LAST_IS_RX))
533  {
534  lastXfer[stateIndex] = LAST_IS_TX;
535  SAI_DRV_SetMaster(instance->instIdx, true);
536  }
537  addr = txBuff;
538  ret = SAI_DRV_SendBlocking(instance->instIdx, &addr, txSize, timeout);
539  }
540 #endif /* I2S_OVER_SAI */
541  return ret;
542 }
543 
544 /*FUNCTION**********************************************************************
545  *
546  * Function Name : I2S_SetRxBuffer
547  * Description : Keep receiving data
548  *
549  * Implements : I2S_SetRxBuffer_Activity
550  *END**************************************************************************/
552  uint8_t * rxBuff,
553  uint32_t rxSize)
554 {
556 #ifdef I2S_OVER_FLEXIO
557  uint8_t stateIndex;
558  if (instance->instType == I2S_INST_TYPE_FLEXIO)
559  {
560  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
561  if (flexioIsMaster[stateIndex])
562  {
563  ret = FLEXIO_I2S_DRV_MasterSetRxBuffer(flexioState[stateIndex], rxBuff, flexioWordSize[stateIndex] * rxSize);
564  }
565  else
566  {
567  ret = FLEXIO_I2S_DRV_SlaveSetRxBuffer(flexioState[stateIndex], rxBuff, flexioWordSize[stateIndex] * rxSize);
568  }
569  }
570 #endif /* I2S_OVER_FLEXIO */
571 #ifdef I2S_OVER_SAI
572  uint8_t* addr;
573  if (instance->instType == I2S_INST_TYPE_SAI)
574  {
575  addr = rxBuff;
576  SAI_DRV_Receive(instance->instIdx, &addr, rxSize);
577  ret = STATUS_SUCCESS;
578  }
579 #endif /* I2S_OVER_SAI */
580  return ret;
581 }
582 
583 /*FUNCTION**********************************************************************
584  *
585  * Function Name : I2S_SetTxBuffer
586  * Description : Keep sending data
587  *
588  * Implements : I2S_SetTxBuffer_Activity
589  *END**************************************************************************/
591  const uint8_t * txBuff,
592  uint32_t txSize)
593 {
595 #ifdef I2S_OVER_FLEXIO
596  uint8_t stateIndex;
597  if (instance->instType == I2S_INST_TYPE_FLEXIO)
598  {
599  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
600  if (flexioIsMaster[stateIndex])
601  {
602  ret = FLEXIO_I2S_DRV_MasterSetTxBuffer(flexioState[stateIndex], txBuff, flexioWordSize[stateIndex] * txSize);
603  }
604  else
605  {
606  ret = FLEXIO_I2S_DRV_SlaveSetTxBuffer(flexioState[stateIndex], txBuff, flexioWordSize[stateIndex] * txSize);
607  }
608  }
609 #endif /* I2S_OVER_FLEXIO */
610 #ifdef I2S_OVER_SAI
611  const uint8_t* addr;
612  if (instance->instType == I2S_INST_TYPE_SAI)
613  {
614  addr = txBuff;
615  SAI_DRV_Send(instance->instIdx, &addr, txSize);
616  ret = STATUS_SUCCESS;
617  }
618 #endif /* I2S_OVER_SAI */
619  return ret;
620 }
621 /*FUNCTION**********************************************************************
622  *
623  * Function Name : I2S_SendData
624  * Description : Send non-blocking
625  *
626  * Implements : I2S_SendData_Activity
627  *END**************************************************************************/
629  const uint8_t * txBuff,
630  uint32_t txSize)
631 {
633  uint8_t stateIndex;
634 #ifdef I2S_OVER_FLEXIO
635  if (instance->instType == I2S_INST_TYPE_FLEXIO)
636  {
637  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
638  if (flexioIsMaster[stateIndex])
639  {
640  ret = FLEXIO_I2S_DRV_MasterSendData(flexioState[stateIndex], txBuff, flexioWordSize[stateIndex] * txSize);
641  }
642  else
643  {
644  ret = FLEXIO_I2S_DRV_SlaveSendData(flexioState[stateIndex], txBuff, flexioWordSize[stateIndex] * txSize);
645  }
646  }
647 #endif /* I2S_OVER_FLEXIO */
648 #ifdef I2S_OVER_SAI
649  const uint8_t* addr;
650  if (instance->instType == I2S_INST_TYPE_SAI)
651  {
652  stateIndex = findState(instance->instIdx, saiStateInstanceMapping, saiStateIsAllocated, NO_OF_SAI_INSTS_FOR_I2S);
653  if ((lastXfer[stateIndex] == LAST_IS_NONE) || (lastXfer[stateIndex] == LAST_IS_RX))
654  {
655  lastXfer[stateIndex] = LAST_IS_TX;
656  SAI_DRV_SetMaster(instance->instIdx, true);
657  }
658  addr = txBuff;
659  SAI_DRV_Send(instance->instIdx, &addr, txSize);
660  ret = STATUS_SUCCESS;
661  }
662 #endif /* I2S_OVER_SAI */
663  return ret;
664 }
665 
666 /*FUNCTION**********************************************************************
667  *
668  * Function Name : I2S_I2S_AbortTransfer
669  * Description : Abort ongoing transfer
670  *
671  * Implements : I2S_AbortTransfer_Activity
672  *END**************************************************************************/
674 {
676  uint8_t stateIndex;
677 #ifdef I2S_OVER_FLEXIO
678  if (instance->instType == I2S_INST_TYPE_FLEXIO)
679  {
680  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
681  if (flexioIsMaster[stateIndex])
682  {
683  ret = FLEXIO_I2S_DRV_MasterTransferAbort((flexio_i2s_master_state_t*)flexioState[stateIndex]);
684  }
685  else
686  {
687  ret = FLEXIO_I2S_DRV_SlaveTransferAbort((flexio_i2s_slave_state_t*)flexioState[stateIndex]);
688  }
689  }
690  else
691  {
692  /* avoid misra */
693  }
694 #endif /* I2S_OVER_FLEXIO */
695 #ifdef I2S_OVER_SAI
696  if (instance->instType == I2S_INST_TYPE_SAI)
697  {
698  stateIndex = findState(instance->instIdx, saiStateInstanceMapping, saiStateIsAllocated, NO_OF_SAI_INSTS_FOR_I2S);
699  if (lastXfer[stateIndex] == LAST_IS_TX)
700  {
701  SAI_DRV_AbortSending(instance->instIdx);
702  }
703  else if (lastXfer[stateIndex] == LAST_IS_RX)
704  {
705  SAI_DRV_AbortReceiving(instance->instIdx);
706  }
707  else
708  {
709  /* avoid misra */
710  }
711  ret = STATUS_SUCCESS;
712  }
713  else
714  {
715  /* avoid misra */
716  }
717 #endif /* I2S_OVER_SAI */
718  return ret;
719 }
720 
721 /*FUNCTION**********************************************************************
722  *
723  * Function Name : I2S_GetStatus
724  * Description : get status of driver
725  *
726  * Implements : I2S_GetStatus_Activity
727  *END**************************************************************************/
729  uint32_t * countRemaining)
730 {
732  uint8_t stateIndex;
733 #ifdef I2S_OVER_FLEXIO
734  if (instance->instType == I2S_INST_TYPE_FLEXIO)
735  {
736  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
737  if (flexioIsMaster[stateIndex])
738  {
739  ret = FLEXIO_I2S_DRV_MasterGetStatus(flexioState[stateIndex], countRemaining);
740  if (countRemaining != NULL)
741  {
742  *countRemaining /= flexioWordSize[stateIndex];
743  }
744  }
745  else
746  {
747  ret = FLEXIO_I2S_DRV_SlaveGetStatus(flexioState[stateIndex], countRemaining);
748  if (countRemaining != NULL)
749  {
750  *countRemaining /= flexioWordSize[stateIndex];
751  }
752  }
753  }
754 #endif /* I2S_OVER_FLEXIO */
755 #ifdef I2S_OVER_SAI
756  if (instance->instType == I2S_INST_TYPE_SAI)
757  {
758  stateIndex = findState(instance->instIdx, saiStateInstanceMapping, saiStateIsAllocated, NO_OF_SAI_INSTS_FOR_I2S);
759  if (lastXfer[stateIndex] == LAST_IS_TX)
760  {
761  ret = SAI_DRV_GetSendingStatus(instance->instIdx, countRemaining);
762  }
763  else if (lastXfer[stateIndex] == LAST_IS_RX)
764  {
765  ret = SAI_DRV_GetReceivingStatus(instance->instIdx, countRemaining);
766  }
767  else
768  {
769  /* avoid misra */
770  }
771  }
772  else
773  {
774  /* avoid misra */
775  }
776 #endif /* I2S_OVER_SAI */
777  return ret;
778 }
779 
780 /*FUNCTION**********************************************************************
781  *
782  * Function Name : I2S_ReceiveDataBlocking
783  * Description : receive blocking
784  *
785  * Implements : I2S_ReceiveDataBlocking_Activity
786  *END**************************************************************************/
788  const i2s_instance_t* instance,
789  uint8_t * rxBuff,
790  uint32_t rxSize,
791  uint32_t timeout)
792 {
794  uint8_t stateIndex;
795 #ifdef I2S_OVER_FLEXIO
796  if (instance->instType == I2S_INST_TYPE_FLEXIO)
797  {
798  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
799  if (flexioIsMaster[stateIndex])
800  {
801  ret = FLEXIO_I2S_DRV_MasterReceiveDataBlocking(flexioState[stateIndex], rxBuff, flexioWordSize[stateIndex] * rxSize, timeout);
802  }
803  else
804  {
805  ret = FLEXIO_I2S_DRV_SlaveReceiveDataBlocking(flexioState[stateIndex], rxBuff, flexioWordSize[stateIndex] * rxSize, timeout);
806  }
807  }
808 #endif /* I2S_OVER_FLEXIO */
809 #ifdef I2S_OVER_SAI
810  uint8_t* addr;
811  if (instance->instType == I2S_INST_TYPE_SAI)
812  {
813  stateIndex = findState(instance->instIdx, saiStateInstanceMapping, saiStateIsAllocated, NO_OF_SAI_INSTS_FOR_I2S);
814  if ((lastXfer[stateIndex] == LAST_IS_NONE) || (lastXfer[stateIndex] == LAST_IS_TX))
815  {
816  lastXfer[stateIndex] = LAST_IS_RX;
817  SAI_DRV_SetMaster(instance->instIdx, false);
818  }
819  addr = rxBuff;
820  ret = SAI_DRV_ReceiveBlocking(instance->instIdx, &addr, rxSize, timeout);
821  }
822  else
823  {
824  /* avoid misra */
825  }
826 #endif /* I2S_OVER_SAI */
827  return ret;
828 }
829 
830 /*FUNCTION**********************************************************************
831  *
832  * Function Name : I2S_ReceiveData
833  * Description : receive non blocking
834  *
835  * Implements : I2S_ReceiveData_Activity
836  *END**************************************************************************/
838  uint8_t * rxBuff,
839  uint32_t rxSize)
840 {
842  uint8_t stateIndex;
843 #ifdef I2S_OVER_FLEXIO
844  if (instance->instType == I2S_INST_TYPE_FLEXIO)
845  {
846  stateIndex = findState(instance->instIdx, flexioStateInstanceMapping, flexioStateIsAllocated, NO_OF_FLEXIO_INSTS_FOR_I2S);
847  if (flexioIsMaster[stateIndex])
848  {
849  ret = FLEXIO_I2S_DRV_MasterReceiveData(flexioState[stateIndex], rxBuff, flexioWordSize[stateIndex] * rxSize);
850  }
851  else
852  {
853  ret = FLEXIO_I2S_DRV_SlaveReceiveData(flexioState[stateIndex], rxBuff, flexioWordSize[stateIndex] * rxSize);
854  }
855  }
856 #endif /* I2S_OVER_FLEXIO */
857 #ifdef I2S_OVER_SAI
858  uint8_t* addr;
859  if (instance->instType == I2S_INST_TYPE_SAI)
860  {
861  stateIndex = findState(instance->instIdx, saiStateInstanceMapping, saiStateIsAllocated, NO_OF_SAI_INSTS_FOR_I2S);
862  if ((lastXfer[stateIndex] == LAST_IS_NONE) || (lastXfer[stateIndex] == LAST_IS_TX))
863  {
864  lastXfer[stateIndex] = LAST_IS_RX;
865  SAI_DRV_SetMaster(instance->instIdx, false);
866  }
867  addr = rxBuff;
868  SAI_DRV_Receive(instance->instIdx, &addr, rxSize);
869  ret = STATUS_SUCCESS;
870  }
871  else
872  {
873  /* avoid misra */
874  }
875 #endif /* I2S_OVER_SAI */
876  return ret;
877 }
878 
879 /*******************************************************************************
880  * EOF
881  ******************************************************************************/
i2s_transfer_type_t transferType
Definition: i2s_pal.h:64
status_t I2S_GetBaudRate(const i2s_instance_t *instance, uint32_t *configuredBaudRate)
Returns the i2s baud rate.
Definition: i2s_pal.c:473
status_t FLEXIO_I2S_DRV_MasterReceiveDataBlocking(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking receive transaction on the I2S bus.
status_t FLEXIO_I2S_DRV_MasterReceiveData(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking receive transaction on the I2S bus.
status_t I2S_ReceiveDataBlocking(const i2s_instance_t *instance, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking I2S reception.
Definition: i2s_pal.c:787
static status_t FLEXIO_I2S_DRV_SlaveTransferAbort(flexio_i2s_slave_state_t *slave)
Aborts a non-blocking I2S slave transaction.
status_t I2S_SendDataBlocking(const i2s_instance_t *instance, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking I2S transmission.
Definition: i2s_pal.c:505
static void freeState(const i2s_instance_t *instance)
Definition: i2s_pal.c:185
status_t FLEXIO_I2S_DRV_MasterSetTxBuffer(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
status_t FLEXIO_I2S_DRV_MasterSendData(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking send transaction on the I2S bus.
I2S user configuration structure.
Definition: i2s_pal.h:62
Master internal context structure.
i2s_callback_t callback
Definition: i2s_pal.h:70
Slave configuration structure.
status_t I2S_Deinit(const i2s_instance_t *instance)
De-initializes the I2S module.
Definition: i2s_pal.c:432
uint32_t baudRate
Definition: i2s_pal.h:66
uint8_t rxDMAChannel
Definition: i2s_pal.h:72
static status_t FLEXIO_I2S_DRV_SlaveSetTxBuffer(flexio_i2s_slave_state_t *slave, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
status_t FLEXIO_I2S_DRV_MasterDeinit(flexio_i2s_master_state_t *master)
De-initialize the FLEXIO_I2S master mode driver.
status_t FLEXIO_I2S_DRV_SlaveInit(uint32_t instance, const flexio_i2s_slave_user_config_t *userConfigPtr, flexio_i2s_slave_state_t *slave)
Initialize the FLEXIO_I2S slave mode driver.
#define DEV_ASSERT(x)
Definition: devassert.h:77
static status_t FLEXIO_I2S_DRV_SlaveSendData(flexio_i2s_slave_state_t *slave, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking send transaction on the I2S bus.
status_t FLEXIO_I2S_DRV_MasterSendDataBlocking(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking send transaction on the I2S bus.
status_t FLEXIO_I2S_DRV_MasterGetStatus(flexio_i2s_master_state_t *master, uint32_t *bytesRemaining)
Get the status of the current non-blocking I2S master transaction.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
status_t I2S_ReceiveData(const i2s_instance_t *instance, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking I2S reception.
Definition: i2s_pal.c:837
Structure storing PAL instance information.
status_t I2S_SetRxBuffer(const i2s_instance_t *instance, uint8_t *rxBuff, uint32_t rxSize)
Keep receiving.
Definition: i2s_pal.c:551
flexio_driver_type_t driverType
status_t I2S_Init(const i2s_instance_t *instance, const i2s_user_config_t *config)
Initializes the I2S module.
Definition: i2s_pal.c:269
status_t I2S_Abort(const i2s_instance_t *instance)
Terminates a non-blocking transfer early.
Definition: i2s_pal.c:673
static status_t FLEXIO_I2S_DRV_SlaveSetRxBuffer(flexio_i2s_slave_state_t *slave, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
void * extension
Definition: i2s_pal.h:74
status_t FLEXIO_I2S_DRV_MasterInit(uint32_t instance, const flexio_i2s_master_user_config_t *userConfigPtr, flexio_i2s_master_state_t *master)
Initialize the FLEXIO_I2S master mode driver.
static status_t FLEXIO_I2S_DRV_SlaveGetStatus(flexio_i2s_slave_state_t *slave, uint32_t *bytesRemaining)
Get the status of the current non-blocking I2S slave transaction.
status_t I2S_SendData(const i2s_instance_t *instance, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking I2S transmission.
Definition: i2s_pal.c:628
void * callbackParam
Definition: i2s_pal.h:71
status_t I2S_GetStatus(const i2s_instance_t *instance, uint32_t *countRemaining)
Get the status of the current I2S transfer.
Definition: i2s_pal.c:728
status_t I2S_SetTxBuffer(const i2s_instance_t *instance, const uint8_t *txBuff, uint32_t txSize)
Keep sending.
Definition: i2s_pal.c:590
status_t FLEXIO_I2S_DRV_MasterSetRxBuffer(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
Master configuration structure.
status_t FLEXIO_I2S_DRV_MasterGetBaudRate(flexio_i2s_master_state_t *master, uint32_t *baudRate)
Get the currently configured baud rate.
status_t FLEXIO_I2S_DRV_MasterTransferAbort(flexio_i2s_master_state_t *master)
Aborts a non-blocking I2S master transaction.
i2s_mode_t mode
Definition: i2s_pal.h:65
uint8_t txDMAChannel
Definition: i2s_pal.h:73
static status_t FLEXIO_I2S_DRV_SlaveReceiveData(flexio_i2s_slave_state_t *slave, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking receive transaction on the I2S bus.
static status_t FLEXIO_I2S_DRV_SlaveDeinit(flexio_i2s_slave_state_t *slave)
De-initialize the FLEXIO_I2S slave mode driver.
status_t FLEXIO_DRV_InitDevice(uint32_t instance, flexio_device_state_t *deviceState)
Initializes the FlexIO device.
Definition: flexio_common.c:89
uint8_t wordWidth
Definition: i2s_pal.h:67
static status_t FLEXIO_I2S_DRV_SlaveReceiveDataBlocking(flexio_i2s_slave_state_t *slave, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking receive transaction on the I2S bus.
static status_t FLEXIO_I2S_DRV_SlaveSendDataBlocking(flexio_i2s_slave_state_t *slave, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking send transaction on the I2S bus.
i2s_inst_type_t instType
static uint8_t findState(uint32_t instance, const uint32_t *instMap, const bool *isAlloc, uint32_t noOfInst)
Definition: i2s_pal.c:247