20 #include "flexio_hw_access.h"
105 #define DIVIDER_MIN_VALUE 1U
106 #define DIVIDER_MAX_VALUE 0xFFU
110 #define TX_SHIFTER(x) (x)
111 #define RX_SHIFTER(x) (uint8_t)((x) + 1U)
112 #define SCL_TIMER(x) (x)
113 #define CONTROL_TIMER(x) (uint8_t)((x) + 1U)
126 static void FLEXIO_I2C_DRV_MasterComputeBaudRateDivider(uint32_t baudRate,
134 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 2U;
136 if (tmpDiv < DIVIDER_MIN_VALUE)
138 tmpDiv = DIVIDER_MIN_VALUE;
140 if (tmpDiv > DIVIDER_MAX_VALUE)
142 tmpDiv = DIVIDER_MAX_VALUE;
145 *divider = (uint16_t)tmpDiv;
155 static void FLEXIO_I2C_DRV_MasterConfigure(
const flexio_i2c_master_state_t *master, uint32_t inputClock, uint32_t baudRate)
159 uint8_t resourceIndex;
162 resourceIndex = master->flexioCommon.resourceIndex;
165 FLEXIO_I2C_DRV_MasterComputeBaudRateDivider(baudRate, ÷r, inputClock);
168 FLEXIO_SetShifterConfig(baseAddr,
169 TX_SHIFTER(resourceIndex),
170 FLEXIO_SHIFTER_START_BIT_0,
171 FLEXIO_SHIFTER_STOP_BIT_1,
172 FLEXIO_SHIFTER_SOURCE_PIN);
175 FLEXIO_SetShifterControl(baseAddr,
176 TX_SHIFTER(resourceIndex),
177 FLEXIO_SHIFTER_MODE_DISABLED,
179 FLEXIO_PIN_POLARITY_LOW,
180 FLEXIO_PIN_CONFIG_DISABLED,
181 CONTROL_TIMER(resourceIndex),
182 FLEXIO_TIMER_POLARITY_POSEDGE);
185 FLEXIO_SetShifterConfig(baseAddr,
186 RX_SHIFTER(resourceIndex),
187 FLEXIO_SHIFTER_START_BIT_DISABLED,
188 FLEXIO_SHIFTER_STOP_BIT_0,
189 FLEXIO_SHIFTER_SOURCE_PIN);
190 FLEXIO_SetShifterControl(baseAddr,
191 RX_SHIFTER(resourceIndex),
192 FLEXIO_SHIFTER_MODE_DISABLED,
194 FLEXIO_PIN_POLARITY_HIGH,
195 FLEXIO_PIN_CONFIG_DISABLED,
196 CONTROL_TIMER(resourceIndex),
197 FLEXIO_TIMER_POLARITY_NEGEDGE);
200 FLEXIO_SetTimerCompare(baseAddr, SCL_TIMER(resourceIndex), divider);
201 FLEXIO_SetTimerConfig(baseAddr,
202 SCL_TIMER(resourceIndex),
203 FLEXIO_TIMER_START_BIT_ENABLED,
204 FLEXIO_TIMER_STOP_BIT_TIM_DIS,
205 FLEXIO_TIMER_ENABLE_TRG_HIGH,
206 FLEXIO_TIMER_DISABLE_TIM_CMP,
207 FLEXIO_TIMER_RESET_PIN_OUT,
208 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
209 FLEXIO_TIMER_INITOUT_ZERO);
210 FLEXIO_SetTimerControl(baseAddr,
211 SCL_TIMER(resourceIndex),
212 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
213 FLEXIO_TRIGGER_POLARITY_LOW,
214 FLEXIO_TRIGGER_SOURCE_INTERNAL,
216 FLEXIO_PIN_POLARITY_HIGH,
217 FLEXIO_PIN_CONFIG_OPEN_DRAIN,
218 FLEXIO_TIMER_MODE_DISABLED);
221 FLEXIO_SetTimerCompare(baseAddr, CONTROL_TIMER(resourceIndex), 0x000FU);
222 FLEXIO_SetTimerConfig(baseAddr,
223 CONTROL_TIMER(resourceIndex),
224 FLEXIO_TIMER_START_BIT_ENABLED,
225 FLEXIO_TIMER_STOP_BIT_TIM_CMP,
226 FLEXIO_TIMER_ENABLE_TIM_ENABLE,
227 FLEXIO_TIMER_DISABLE_TIM_DISABLE,
228 FLEXIO_TIMER_RESET_NEVER,
229 FLEXIO_TIMER_DECREMENT_PIN_SHIFT_PIN,
230 FLEXIO_TIMER_INITOUT_ONE);
231 FLEXIO_SetTimerControl(baseAddr,
232 CONTROL_TIMER(resourceIndex),
233 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
234 FLEXIO_TRIGGER_POLARITY_LOW,
235 FLEXIO_TRIGGER_SOURCE_INTERNAL,
237 FLEXIO_PIN_POLARITY_LOW,
238 FLEXIO_PIN_CONFIG_DISABLED,
239 FLEXIO_TIMER_MODE_DISABLED);
253 uint8_t resourceIndex;
255 resourceIndex = master->flexioCommon.resourceIndex;
257 bytesNo = master->txRemainingBytes;
258 bytesNo = (bytesNo * 18U) + 1U;
260 timerCmp = FLEXIO_GetTimerCompare(baseAddr, SCL_TIMER(resourceIndex));
261 timerCmp = (uint16_t)((timerCmp & 0x00FFU) | (uint16_t)((bytesNo & 0xFFU) << 8U));
262 FLEXIO_SetTimerCompare(baseAddr, SCL_TIMER(resourceIndex), timerCmp);
275 uint8_t resourceIndex;
277 resourceIndex = master->flexioCommon.resourceIndex;
279 addrByte = (uint8_t)((uint8_t)(master->slaveAddress << 1U) + (uint8_t)(master->receive ? 1U : 0U));
280 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), (uint32_t)addrByte << 24U, FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
294 uint8_t resourceIndex;
297 resourceIndex = master->flexioCommon.resourceIndex;
300 data = (uint8_t)FLEXIO_ReadShifterBuffer(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
302 if (master->rxRemainingBytes == 0U)
307 if (master->addrReceived ==
false)
310 master->addrReceived =
true;
311 if (master->receive ==
true)
314 FLEXIO_SetShifterStopBit(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_STOP_BIT_0);
319 master->rxRemainingBytes--;
320 if (master->receive ==
true)
323 *(master->data) = data;
327 if ((master->receive ==
true) && (master->rxRemainingBytes == 1U))
330 FLEXIO_SetShifterStopBit(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_STOP_BIT_1);
332 FLEXIO_SetShifterStopBit(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_STOP_BIT_1);
347 uint8_t resourceIndex;
350 resourceIndex = master->flexioCommon.resourceIndex;
353 if (master->txRemainingBytes == 0U)
358 master->txRemainingBytes--;
360 if (master->txRemainingBytes == 0U)
363 if (master->sendStop ==
true)
374 else if (master->receive ==
true)
382 data = *(master->data);
388 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), data, FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
401 uint8_t resourceIndex;
404 resourceIndex = master->flexioCommon.resourceIndex;
407 FLEXIO_SetShifterStopBit(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_STOP_BIT_0);
409 FLEXIO_SetShifterStopBit(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_STOP_BIT_1);
411 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
414 switch (master->driverType)
418 FLEXIO_SetShifterInterrupt(baseAddr,
419 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
421 FLEXIO_SetShifterErrorInterrupt(baseAddr,
422 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
425 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << SCL_TIMER(resourceIndex)),
false);
432 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
false);
434 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << SCL_TIMER(resourceIndex)),
false);
439 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
false);
446 master->driverIdle =
true;
449 if (master->blocking ==
true)
465 uint8_t resourceIndex;
467 resourceIndex = master->flexioCommon.resourceIndex;
471 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_TRANSMIT);
472 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_RECEIVE);
473 FLEXIO_SetTimerMode(baseAddr, SCL_TIMER(resourceIndex), FLEXIO_TIMER_MODE_8BIT_BAUD);
474 FLEXIO_SetTimerMode(baseAddr, CONTROL_TIMER(resourceIndex), FLEXIO_TIMER_MODE_16BIT);
476 FLEXIO_SetShifterPinConfig(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_PIN_CONFIG_OPEN_DRAIN);
489 uint8_t resourceIndex;
491 resourceIndex = master->flexioCommon.resourceIndex;
495 FLEXIO_SetShifterPinConfig(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_PIN_CONFIG_DISABLED);
497 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
498 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
499 FLEXIO_SetTimerMode(baseAddr, SCL_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
500 FLEXIO_SetTimerMode(baseAddr, CONTROL_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
503 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
504 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
506 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
509 FLEXIO_I2C_DRV_MasterEndTransfer(master);
523 switch (master->driverType)
527 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
537 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
545 master->blocking =
false;
550 FLEXIO_I2C_DRV_MasterStopTransfer(master);
553 return master->status;
572 uint8_t resourceIndex;
574 resourceIndex = master->flexioCommon.resourceIndex;
575 return !(FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)));
588 uint8_t pinMask = (uint8_t)((1U << master->sdaPin) | (1U << master->sclPin));
589 if ((FLEXIO_GetPinData(baseAddr) & pinMask) == pinMask)
610 static void FLEXIO_I2C_DRV_MasterCheckStatus(
void *stateStruct)
613 uint8_t resourceIndex;
620 resourceIndex = master->flexioCommon.resourceIndex;
623 if (FLEXIO_GetShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex)))
626 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
629 if (FLEXIO_GetShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex)))
632 if (FLEXIO_I2C_DRV_MasterCheckNack(baseAddr, master))
636 FLEXIO_I2C_DRV_MasterStopTransfer(master);
638 if (master->callback != NULL)
647 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
652 if (FLEXIO_GetShifterStatus(baseAddr, RX_SHIFTER(resourceIndex)))
654 FLEXIO_I2C_DRV_ReadData(master);
657 if (FLEXIO_GetTimerStatus(baseAddr, SCL_TIMER(resourceIndex)))
660 FLEXIO_ClearTimerStatus(baseAddr, SCL_TIMER(resourceIndex));
668 FLEXIO_I2C_DRV_MasterStopTransfer(master);
670 if (master->callback != NULL)
678 if (FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)))
680 FLEXIO_I2C_DRV_WriteData(master);
681 if (master->txRemainingBytes == 0U)
684 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
703 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
704 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter])) + (
sizeof(uint32_t) - 1U);
722 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
723 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter]));
734 static inline void FLEXIO_I2C_DRV_MasterDmaBlockImmediate(
edma_software_tcd_t *stcdBase, uint8_t blockNo)
747 static inline void FLEXIO_I2C_DRV_MasterDmaBlockTerminate(
edma_software_tcd_t *stcdBase, uint8_t blockNo)
769 if (master->receive ==
false)
771 addr = (uint32_t)(master->data);
776 master->dummyDmaIdle = 0xFFU;
777 addr = (uint32_t)(&(master->dummyDmaIdle));
780 srcList[0U].
length = master->rxRemainingBytes;
782 destList[0U].
address = FLEXIO_I2C_DRV_MasterComputeTxRegAddr(master);
783 destList[0U].
length = master->rxRemainingBytes;
787 if (master->sendStop)
789 master->dummyDmaStop = 0U;
793 master->dummyDmaStop = 0xFFU;
795 srcList[1U].
address = (uint32_t)(&(master->dummyDmaStop));
798 destList[1U].
address = FLEXIO_I2C_DRV_MasterComputeTxRegAddr(master);
804 1U, srcList, destList, 2U);
806 if (master->receive ==
true)
812 FLEXIO_I2C_DRV_MasterDmaBlockTerminate(stcdBase, 0U);
828 uint8_t blockCnt = 0U;
834 dmaChn = master->rxDMAChannel;
837 if (master->receive ==
false)
842 FLEXIO_I2C_DRV_MasterComputeRxRegAddr(master),
843 (uint32_t)(&(master->dummyDmaReceive)),
845 1U, master->rxRemainingBytes + 1U,
true);
852 srcList[blockCnt].
address = FLEXIO_I2C_DRV_MasterComputeRxRegAddr(master);
853 srcList[blockCnt].
length = 1U;
855 destList[blockCnt].
address = (uint32_t)(&(master->dummyDmaReceive));
856 destList[blockCnt].
length = 1U;
860 if (master->rxRemainingBytes > 1U)
863 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
867 master->dmaReceiveTxStop0 = (uint8_t)(tmp & 0xFFU);
868 srcList[blockCnt].
address = (uint32_t)(&(master->dmaReceiveTxStop0));
869 srcList[blockCnt].
length = 1U;
871 destList[blockCnt].
address = (uint32_t)(&(baseAddr->
SHIFTCFG[shifter]));
872 destList[blockCnt].
length = 1U;
876 srcList[blockCnt].
address = FLEXIO_I2C_DRV_MasterComputeRxRegAddr(master);
877 srcList[blockCnt].
length = master->rxRemainingBytes - 1U;
879 destList[blockCnt].
address = (uint32_t)(master->data);
880 destList[blockCnt].
length = master->rxRemainingBytes - 1U;
887 master->dmaReceiveTxStop1 = (uint8_t)(tmp & 0xFFU);
888 srcList[blockCnt].
address = (uint32_t)(&(master->dmaReceiveTxStop1));
889 srcList[blockCnt].
length = 1U;
891 destList[blockCnt].
address = (uint32_t)(&(baseAddr->
SHIFTCFG[shifter]));
892 destList[blockCnt].
length = 1U;
897 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
901 master->dmaReceiveRxStop1 = (uint8_t)(tmp & 0xFFU);
902 srcList[blockCnt].
address = (uint32_t)(&(master->dmaReceiveRxStop1));
903 srcList[blockCnt].
length = 1U;
905 destList[blockCnt].
address = (uint32_t)(&(baseAddr->
SHIFTCFG[shifter]));
906 destList[blockCnt].
length = 1U;
910 srcList[blockCnt].
address = FLEXIO_I2C_DRV_MasterComputeRxRegAddr(master);
911 srcList[blockCnt].
length = 1U;
913 destList[blockCnt].
address = (uint32_t)(&(master->data[master->rxRemainingBytes - 1U]));
914 destList[blockCnt].
length = 1U;
924 FLEXIO_I2C_DRV_MasterDmaBlockImmediate(stcdBase, 0U);
925 if (master->rxRemainingBytes > 1U)
927 FLEXIO_I2C_DRV_MasterDmaBlockImmediate(stcdBase, 2U);
928 FLEXIO_I2C_DRV_MasterDmaBlockImmediate(stcdBase, 3U);
931 FLEXIO_I2C_DRV_MasterDmaBlockTerminate(stcdBase, (uint8_t)(blockCnt - 2U));
944 uint32_t alignedStcd;
952 FLEXIO_I2C_DRV_MasterDmaConfigTx(master, stcdBase);
953 FLEXIO_I2C_DRV_MasterDmaConfigRx(master, &stcdBase[FLEXIO_I2C_DMA_TX_CHAIN_LENGTH]);
968 static void FLEXIO_I2C_DRV_MasterEndDmaTransfer(
void *stateStruct)
971 uint8_t resourceIndex;
978 resourceIndex = master->flexioCommon.resourceIndex;
981 if (FLEXIO_GetShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex)))
983 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
986 FLEXIO_I2C_DRV_MasterStopTransfer(master);
988 if (master->callback != NULL)
995 if (FLEXIO_GetTimerStatus(baseAddr, SCL_TIMER(resourceIndex)))
998 FLEXIO_ClearTimerStatus(baseAddr, SCL_TIMER(resourceIndex));
1005 FLEXIO_I2C_DRV_MasterStopTransfer(master);
1007 if (master->callback != NULL)
1028 uint8_t resourceIndex;
1032 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1033 resourceIndex = master->flexioCommon.resourceIndex;
1041 if (FLEXIO_I2C_DRV_MasterBusBusy(baseAddr, master))
1047 master->data = (uint8_t *)buff;
1049 master->txRemainingBytes = size + 1U;
1050 master->rxRemainingBytes = size;
1052 master->driverIdle =
false;
1053 master->sendStop = sendStop;
1054 master->receive = receive;
1055 master->addrReceived =
false;
1058 FLEXIO_I2C_DRV_MasterSetBytesNo(baseAddr, master);
1060 FLEXIO_I2C_DRV_MasterEnableTransfer(master);
1062 switch (master->driverType)
1066 FLEXIO_I2C_DRV_MasterSendAddress(baseAddr, master);
1068 FLEXIO_SetShifterInterrupt(baseAddr,
1069 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
1071 FLEXIO_SetShifterErrorInterrupt(baseAddr,
1072 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
1075 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << SCL_TIMER(resourceIndex)),
true);
1079 FLEXIO_I2C_DRV_MasterSendAddress(baseAddr, master);
1083 FLEXIO_I2C_DRV_MasterStartDmaTransfer(master);
1085 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
1087 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << SCL_TIMER(resourceIndex)),
true);
1089 FLEXIO_I2C_DRV_MasterSendAddress(baseAddr, master);
1091 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
true);
1118 uint32_t inputClock;
1137 master->flexioCommon.resourceCount = 2U;
1153 master->driverType = userConfigPtr->
driverType;
1155 master->sdaPin = userConfigPtr->
sdaPin;
1156 master->sclPin = userConfigPtr->
sclPin;
1157 master->callback = userConfigPtr->
callback;
1159 master->blocking =
false;
1160 master->driverIdle =
true;
1164 FLEXIO_I2C_DRV_MasterConfigure(master, inputClock, userConfigPtr->
baudRate);
1167 switch (master->driverType)
1170 master->flexioCommon.isr = FLEXIO_I2C_DRV_MasterCheckStatus;
1180 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(master->flexioCommon.resourceIndex)];
1181 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(master->flexioCommon.resourceIndex)];
1185 master->flexioCommon.isr = FLEXIO_I2C_DRV_MasterEndDmaTransfer;
1233 uint32_t inputClock;
1235 uint8_t resourceIndex;
1239 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1240 resourceIndex = master->flexioCommon.resourceIndex;
1250 FLEXIO_I2C_DRV_MasterComputeBaudRateDivider(baudRate, ÷r, inputClock);
1253 timerCmp = FLEXIO_GetTimerCompare(baseAddr, SCL_TIMER(resourceIndex));
1254 timerCmp = (uint16_t)((timerCmp & 0xFF00U) | divider);
1255 FLEXIO_SetTimerCompare(baseAddr, SCL_TIMER(resourceIndex), timerCmp);
1272 uint32_t inputClock;
1276 uint8_t resourceIndex;
1281 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1282 resourceIndex = master->flexioCommon.resourceIndex;
1290 timerCmp = FLEXIO_GetTimerCompare(baseAddr, SCL_TIMER(resourceIndex));
1291 divider = (uint16_t)(timerCmp & 0x00FFU);
1294 *baudRate = (inputClock + divider + 2U) / (2U * ((uint32_t)divider + 2U));
1315 master->slaveAddress = address;
1328 const uint8_t * txBuff,
1336 return FLEXIO_I2C_DRV_MasterStartTransfer(master, (uint8_t *)txBuff, txSize, sendStop,
false);
1348 const uint8_t * txBuff,
1362 master->blocking =
true;
1365 status = FLEXIO_I2C_DRV_MasterStartTransfer(master, (uint8_t *)txBuff, txSize, sendStop,
false);
1369 master->blocking =
false;
1374 return FLEXIO_I2C_DRV_MasterWaitTransferEnd(master, timeout);
1394 return FLEXIO_I2C_DRV_MasterStartTransfer(master, rxBuff, rxSize, sendStop,
true);
1420 master->blocking =
true;
1423 status = FLEXIO_I2C_DRV_MasterStartTransfer(master, rxBuff, rxSize, sendStop,
true);
1427 master->blocking =
false;
1432 return FLEXIO_I2C_DRV_MasterWaitTransferEnd(master, timeout);
1456 if (master->driverIdle)
1462 FLEXIO_I2C_DRV_MasterStopTransfer(master);
1477 uint32_t remainingBytes;
1483 remainingBytes = master->rxRemainingBytes;
1485 if (!master->driverIdle)
1487 switch(master->driverType)
1491 FLEXIO_I2C_DRV_MasterCheckStatus(master);
1507 if (bytesRemaining != NULL)
1509 *bytesRemaining = remainingBytes;
1512 if (!master->driverIdle)
1518 return master->status;
eDMA TCD Implements : edma_software_tcd_t_Class
uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t virtualChannel)
Returns the remaining major loop iteration count.
i2c_master_callback_t callback
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
#define FLEXIO_I2C_MAX_SIZE
Maximum size of a transfer. The restriction is that the total number of SCL edges must not exceed 8 b...
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t virtualChannel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
#define FLEXIO_INSTANCE_COUNT
status_t FLEXIO_I2C_DRV_MasterInit(uint32_t instance, const flexio_i2c_master_user_config_t *userConfigPtr, flexio_i2c_master_state_t *master)
Initialize the FLEXIO_I2C master mode driver.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
void EDMA_DRV_SetDestOffset(uint8_t virtualChannel, int16_t offset)
Configures the destination address signed offset for the eDMA channel.
status_t FLEXIO_I2C_DRV_MasterGetBaudRate(flexio_i2c_master_state_t *master, uint32_t *baudRate)
Get the currently configured baud rate.
volatile uint32_t SHIFTCFG[4u]
status_t EDMA_DRV_StopChannel(uint8_t virtualChannel)
Stops the eDMA channel.
flexio_driver_type_t driverType
#define STCD_ADDR(address)
volatile uint32_t SHIFTBUFBIS[4u]
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
const clock_names_t g_flexioClock[(1u)]
status_t FLEXIO_I2C_DRV_MasterSetSlaveAddr(flexio_i2c_master_state_t *master, uint16_t address)
Set the slave address for any subsequent I2C communication.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
FLEXIO_Type *const g_flexioBase[(1u)]
void EDMA_DRV_SetSrcOffset(uint8_t virtualChannel, int16_t offset)
Configures the source address signed offset for the eDMA channel.
Data structure for configuring a discrete memory transfer. Implements : edma_scatter_gather_list_t_Cl...
status_t FLEXIO_I2C_DRV_MasterDeinit(flexio_i2c_master_state_t *master)
De-initialize the FLEXIO_I2C master mode driver.
const uint8_t g_flexioDMASrc[(1u)][(4U)]
#define FLEXIO_SHIFTCFG_SSTOP(x)
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
edma_transfer_type_t type
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_ConfigScatterGatherTransfer(uint8_t virtualChannel, edma_software_tcd_t *stcd, edma_transfer_size_t transferSize, uint32_t bytesOnEachRequest, const edma_scatter_gather_list_t *srcList, const edma_scatter_gather_list_t *destList, uint8_t tcdCount)
Configures the DMA transfer in a scatter-gather mode.
flexio_device_state_t * g_flexioDeviceStatePtr[(1u)]
#define DMA_TCD_CSR_START(x)
status_t FLEXIO_I2C_DRV_MasterSetBaudRate(flexio_i2c_master_state_t *master, uint32_t baudRate)
Set the baud rate for any subsequent I2C communication.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
status_t EDMA_DRV_StartChannel(uint8_t virtualChannel)
Starts an eDMA channel.
Master internal context structure.
#define FLEXIO_SHIFTCFG_SSTOP_MASK
status_t EDMA_DRV_SetChannelRequest(uint8_t virtualChannel, uint8_t req)
Configures the DMA request for the eDMA channel.
Master configuration structure.
status_t FLEXIO_I2C_DRV_MasterSendDataBlocking(flexio_i2c_master_state_t *master, const uint8_t *txBuff, uint32_t txSize, bool sendStop, uint32_t timeout)
Perform a blocking send transaction on the I2C bus.
status_t FLEXIO_I2C_DRV_MasterReceiveDataBlocking(flexio_i2c_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize, bool sendStop, uint32_t timeout)
Perform a blocking receive transaction on the I2C bus.
status_t FLEXIO_I2C_DRV_MasterTransferAbort(flexio_i2c_master_state_t *master)
Aborts a non-blocking I2C master transaction.
status_t FLEXIO_I2C_DRV_MasterReceiveData(flexio_i2c_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize, bool sendStop)
Perform a non-blocking receive transaction on the I2C bus.
status_t FLEXIO_I2C_DRV_MasterGetStatus(flexio_i2c_master_state_t *master, uint32_t *bytesRemaining)
Get the status of the current non-blocking I2C master transaction.
status_t FLEXIO_I2C_DRV_MasterSendData(flexio_i2c_master_state_t *master, const uint8_t *txBuff, uint32_t txSize, bool sendStop)
Perform a non-blocking send transaction on the I2C bus.
#define DMA_TCD_CSR_DREQ(x)