#define S32_NVIC_ICER_CLRENA | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICER_CLRENA_SHIFT))&S32_NVIC_ICER_CLRENA_MASK) |
#define S32_NVIC_ICPR_CLRPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICPR_CLRPEND_SHIFT))&S32_NVIC_ICPR_CLRPEND_MASK) |
#define S32_NVIC_IPR_PRI_0 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_0_SHIFT))&S32_NVIC_IPR_PRI_0_MASK) |
#define S32_NVIC_IPR_PRI_1 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_1_SHIFT))&S32_NVIC_IPR_PRI_1_MASK) |
#define S32_NVIC_IPR_PRI_2 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_2_SHIFT))&S32_NVIC_IPR_PRI_2_MASK) |
#define S32_NVIC_IPR_PRI_3 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IPR_PRI_3_SHIFT))&S32_NVIC_IPR_PRI_3_MASK) |
#define S32_NVIC_ISER_SETENA | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISER_SETENA_SHIFT))&S32_NVIC_ISER_SETENA_MASK) |
#define S32_NVIC_ISPR_SETPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISPR_SETPEND_SHIFT))&S32_NVIC_ISPR_SETPEND_MASK) |