adc_pal.c
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1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
66 #include <stddef.h>
67 #include "adc_pal.h"
68 #include "adc_irq.h"
69 #include "device_registers.h"
70 #include "interrupt_manager.h"
71 #include "osif.h"
72 
73 
74 /*******************************************************************************
75  * Definitions
76  ******************************************************************************/
77 
78 
82 typedef struct
83 {
84  uint16_t bufferLength;
85  uint16_t currentBufferOffset;
86  bool notificationEn;
87  bool active;
88 #if defined(ADC_PAL_MPC574xP)
89  uint32_t groupIdx;
90 #endif
91 } adc_group_state_t;
92 
98 typedef struct
99 {
100  const adc_group_config_t * groupArray;
101  uint16_t numGroups;
102  adc_group_state_t hwTrigGroupState[ADC_PAL_MAX_NUM_HW_GROUPS_EN];
103  adc_group_state_t swTrigGroupState;
104  uint32_t latestGroupIdx;
105 #if (defined(ADC_PAL_S32K1xx))
106  pdb_clk_prescaler_div_t pdbPrescaler;
107 #endif
108 #if (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
109  uint32_t stateIdxMapping[ADC_PAL_TOTAL_NUM_GROUPS];
110 #endif
111 } adc_pal_state_t;
112 
113 
114 #if defined(ADC_PAL_S32K1xx)
115 
116 #if (ADC_PAL_MAX_NUM_HW_GROUPS_EN != 1u)
117 #error "The current device supports maximum 1 HW triggered group enabled"
118 #endif /* (ADC_PAL_MAX_NUM_HW_GROUPS_EN != 1) */
119 
120 /* For S32K1xx, ADC PAL instances are mapped 1:1 with ADC instances (and PDB instances). */
121 #define NUMBER_OF_ADC_PAL_INSTANCES ADC_INSTANCE_COUNT
122 
123 #define ADC_PAL_PDB_CHAN (0u)
124 #define ADC_PAL_TRGMUX_IDX (0u)
125 #define ADC_PAL_MAX_CONVS_IN_GROUP (PDB_DLY_COUNT)
127 /* For S32K1xx, the ADC PAL assumes that ADC and PDB instances are mapped 1:1, thus PDB_INSTANCE_COUNT == ADC_INSTANCE_COUNT */
128 static const trgmux_target_module_t adcPalTrgmuxTarget[ADC_INSTANCE_COUNT] = {
129 #if (ADC_INSTANCE_COUNT >= 1u)
131 #endif
132 #if (ADC_INSTANCE_COUNT >= 2u)
133  TRGMUX_TARGET_MODULE_PDB1_TRG_IN
134 #endif
135 };
136 
137 static status_t ADC_Init_S32K1xx(const uint32_t instance, const adc_config_t * const config);
138 
139 static inline void ADC_ConfigPdbAndPretriggers(const uint32_t instIdx, const pdb_trigger_src_t trgSrc, const adc_group_config_t * currentGroupCfg);
140 static void ADC_ConfigGroup(const uint32_t instance, const uint32_t groupIdx, const bool hwTriggerFlag);
141 static status_t ADC_StopGroupBlocking(const uint32_t instance, const uint32_t timeout);
142 
143 #elif defined(ADC_PAL_MPC574xC_G_R)
144 
145 /* For MPC574xC_G_R, ADC PAL instances are mapped 1:1 with BCTU instances.
146  * Each BCTU instance may have multiple ADCs connected. */
147 #define NUMBER_OF_ADC_PAL_INSTANCES BCTU_INSTANCE_COUNT
148 
149 #define ADC_PAL_MAX_CONVS_IN_GROUP_HW_TRIG (BCTU_LISTCHR__COUNT * 2u)
151 static status_t ADC_Init_MPC574xC_G_R(const uint32_t instIdx, const adc_config_t * const config);
152 static status_t ADC_ConfigHwTriggeredGroup(const uint32_t instIdx, const adc_group_config_t * const groupConfig, const uint8_t bctuStartListIdx);
153 static uint32_t ADC_GetGroupIdx(const uint32_t instIdx, const adc_trigger_source_t hwTrigSource);
154 
155 #elif defined(ADC_PAL_MPC574xP)
156 
157 /* For MPC574xP, ADC PAL instances are mapped 1:1 with CTU instances.
158  * Each CTU instance may have multiple ADCs connected. */
159 #define NUMBER_OF_ADC_PAL_INSTANCES CTU_INSTANCE_COUNT
160 
161 /* Table of base addresses for CTU and ADC instances. */
162 static CTU_Type * const ctuBase[CTU_INSTANCE_COUNT] = CTU_BASE_PTRS;
163 static ADC_Type * const adcBase[ADC_INSTANCE_COUNT] = ADC_BASE_PTRS;
164 
165 static status_t ADC_Init_MPC574xP(const uint32_t instIdx, const adc_config_t * const config);
166 
167 #endif /* defined(ADC_PAL_MPC574xP) */
168 
169 
170 #if (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
171 
172 static const IRQn_Type adcEocIrqNums[ADC_INSTANCE_COUNT] = {
173  ADC0_EOC_IRQn,
174 #if ADC_INSTANCE_COUNT > 1u
175  ADC1_EOC_IRQn,
176 #endif
177 #if ADC_INSTANCE_COUNT > 2u
178  ADC2_EOC_IRQn,
179 #endif
180 #if ADC_INSTANCE_COUNT > 3u
181  ADC3_EOC_IRQn
182 #endif
183 };
184 
185 static inline uint8_t ADC_GetChanIdx(const adc_input_chan_t adcPalInputChan);
186 static inline uint8_t ADC_GetAdcAbsoluteIdx(const adc_input_chan_t adcPalInputChan);
187 static uint16_t ADC_GetUsedAdcInstances(const uint32_t instance);
188 static void ADC_ConfigAdcMPC574x(const uint32_t instIdx, const adc_config_t * const config);
189 static void ADC_ResetAdcMPC574x(const uint32_t instIdx);
190 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
191 static void ADC_CheckChanDuplicate(const adc_config_t * const config);
192 #endif /* defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT) */
193 
194 #endif /* (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
195 
196 
197 #if (defined(ADC_PAL_S32K1xx) || defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
198 
199 static inline adc_group_state_t * ADC_GetHwGroupStatePtr(const uint32_t instIdx, const uint32_t groupIdx);
200 static bool ADC_AnyHwTrigGroupActive(const uint32_t instIdx);
201 static void ADC_PalStateUpdateStart(const uint32_t instIdx, const uint32_t groupIdx);
202 static void ADC_CallNotificationCb(const adc_pal_state_t * const palState, const uint32_t groupIdx, const adc_group_state_t * const groupState);
203 
204 #endif /* (defined(ADC_PAL_S32K1xx) || defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
205 
206 
209 /*******************************************************************************
210  * Variables
211  ******************************************************************************/
212 /* Static variable to store the PAL state information */
213 static adc_pal_state_t adcPalState[NUMBER_OF_ADC_PAL_INSTANCES];
214 
215 /*******************************************************************************
216  * Public Functions
217  ******************************************************************************/
218 
219 
220 /*FUNCTION**********************************************************************
221  *
222  * Function Name : ADC_Init
223  * Description : This function initializes the ADC PAL instance, including the
224  * other platform specific HW units used together with ADC.
225  *
226  * Implements : ADC_Init_Activity
227  *END**************************************************************************/
228 status_t ADC_Init(const adc_instance_t * const instance, const adc_config_t * const config)
229 {
230  DEV_ASSERT(instance != NULL);
231  DEV_ASSERT(config != NULL);
232  DEV_ASSERT(config->extension != NULL);
233  DEV_ASSERT(config->groupConfigArray != NULL);
234 
235  uint32_t instIdx = instance->instIdx;
236  DEV_ASSERT(instIdx < NUMBER_OF_ADC_PAL_INSTANCES);
237 
238  adc_pal_state_t * const palState = &(adcPalState[instIdx]);
239  status_t status = STATUS_SUCCESS;
240  uint8_t idx = 0u;
241 
242  /* Initialize PAL state structure members common for all platforms */
243  palState->groupArray = config->groupConfigArray;
244  palState->numGroups = config->numGroups;
245  for(idx = 0; idx < ADC_PAL_MAX_NUM_HW_GROUPS_EN; idx++)
246  {
247  palState->hwTrigGroupState[idx].active = false;
248  palState->hwTrigGroupState[idx].bufferLength = 0u;
249  palState->hwTrigGroupState[idx].currentBufferOffset = 0u;
250  palState->hwTrigGroupState[idx].notificationEn = false;
251  }
252  palState->swTrigGroupState.active = false;
253  palState->swTrigGroupState.bufferLength = 0u;
254  palState->swTrigGroupState.currentBufferOffset = 0u;
255  palState->swTrigGroupState.notificationEn = false;
256  palState->latestGroupIdx = 0u;
257 
258 #if defined(ADC_PAL_S32K1xx)
259 
260  /* Initialize state members specific for this platform */
261  const extension_adc_s32k1xx_t * const extension = (extension_adc_s32k1xx_t *)(config->extension);
262  palState->pdbPrescaler = extension->pdbPrescaler;
263 
264  status = ADC_Init_S32K1xx(instIdx, config);
265 
266 #elif (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
267 
268  /* Initialize state members specific for this platform */
269  uint8_t hwTrigGroupIdx = 0;
270  for(idx = 0; idx < palState->numGroups; idx++)
271  {
272  if(palState->groupArray[idx].hwTriggerSupport == true)
273  {
274  /* For hwTrigGroups, stateIdxMapping holds the index in hwTrigGroupState array */
275  palState->stateIdxMapping[idx] = hwTrigGroupIdx;
276  hwTrigGroupIdx++;
277  }
278  else
279  {
280  /* A single SW triggered group active is supported,
281  * so for swTrigGroups, stateIdxMapping holds a value which is not used. */
282  palState->stateIdxMapping[idx] = 0u;
283  }
284  }
285 
286 #if defined(ADC_PAL_MPC574xC_G_R)
287 
288  status = ADC_Init_MPC574xC_G_R(instIdx, config);
289 
290 #else
291 
292  status = ADC_Init_MPC574xP(instIdx, config);
293 
294 #endif /* defined(ADC_PAL_MPC574xC_G_R) */
295 
296 #endif /* (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
297 
298  return status;
299 }
300 
301 
302 /*FUNCTION**********************************************************************
303  *
304  * Function Name : ADC_Deinit
305  * Description : This function resets the ADC PAL instance, including
306  * the other platform specific HW units used together with ADC.
307  *
308  * Implements : ADC_Deinit_Activity
309  *END**************************************************************************/
310 status_t ADC_Deinit(const adc_instance_t * const instance)
311 {
312  DEV_ASSERT(instance != NULL);
313 
314  uint32_t instIdx = instance->instIdx;
315  DEV_ASSERT(instIdx < NUMBER_OF_ADC_PAL_INSTANCES);
316 
317  adc_pal_state_t * const palState = &(adcPalState[instIdx]);
318  bool hwTrigGroupActive = false;
319  status_t status;
320  uint16_t idx;
321 
322  hwTrigGroupActive = ADC_AnyHwTrigGroupActive(instIdx);
323 
324  if((palState->swTrigGroupState.active == true) || (hwTrigGroupActive == true))
325  {
326  status = STATUS_BUSY;
327  }
328  else
329  {
330 #if defined(ADC_PAL_S32K1xx)
331 
332  /* No state members specific for this platform to reset */
333 
334  PDB_DRV_Deinit(instIdx);
335 
336  status = TRGMUX_DRV_SetTrigSourceForTargetModule(ADC_PAL_TRGMUX_IDX, TRGMUX_TRIG_SOURCE_DISABLED, adcPalTrgmuxTarget[instIdx]);
337  DEV_ASSERT(status == STATUS_SUCCESS);
338 
339  ADC_DRV_Reset(instIdx);
340 
341  /* Disable interrupt from INT manager */
342  IRQn_Type adcIrqId;
343  adcIrqId = ADC_DRV_GetInterruptNumber(instIdx);
344  INT_SYS_DisableIRQ(adcIrqId);
345 
346  status = STATUS_SUCCESS;
347 
348 #elif defined(ADC_PAL_MPC574xC_G_R)
349 
350  /* Reset state members specific for this platform */
351  for(idx = 0; idx < palState->numGroups; idx++)
352  {
353  palState->stateIdxMapping[idx] = 0u;
354  }
355 
356  /* Deinit BCTU and ADCs */
357  status_t bctuStatus;
358  bctuStatus = BCTU_DRV_Reset(instIdx, /* default timeout value 2ms*/ 2u);
359  if(bctuStatus == STATUS_TIMEOUT)
360  {
361  status = STATUS_BUSY;
362  }
363  else
364  {
365  ADC_ResetAdcMPC574x(instIdx);
366 
367  status = STATUS_SUCCESS;
368  }
369 
370 #elif defined(ADC_PAL_MPC574xP)
371 
372  /* Reset state members specific for this platform */
373  for(idx = 0; idx < palState->numGroups; idx++)
374  {
375  palState->stateIdxMapping[idx] = 0u;
376  }
377 
378  CTU_DRV_Reset(instIdx);
379 
380  ADC_ResetAdcMPC574x(instIdx);
381 
382  status = STATUS_SUCCESS;
383 
384 #endif /* defined(ADC_PAL_MPC574xP) */
385 
386  /* Reset PAL state structure members common for all platforms */
387  palState->groupArray = NULL;
388  palState->numGroups = 0u;
389  for(idx = 0; idx < ADC_PAL_MAX_NUM_HW_GROUPS_EN; idx++)
390  {
391  palState->hwTrigGroupState[idx].active = false;
392  }
393  palState->swTrigGroupState.active = false;
394  palState->latestGroupIdx = 0u;
395  }
396 
397  return status;
398 }
399 
400 /*FUNCTION**********************************************************************
401  *
402  * Function Name : ADC_EnableHardwareTrigger
403  * Description : Enables the selected HW trigger for a conversion group,
404  * if the conversion group has support for HW trigger.
405  *
406  * Implements : ADC_EnableHardwareTrigger_Activity
407  *END**************************************************************************/
408 status_t ADC_EnableHardwareTrigger(const adc_instance_t * const instance, const uint32_t groupIdx)
409 {
410  DEV_ASSERT(instance != NULL);
411 
412  uint32_t instIdx = instance->instIdx;
413  DEV_ASSERT(instIdx < NUMBER_OF_ADC_PAL_INSTANCES);
414  DEV_ASSERT(groupIdx < adcPalState[instIdx].numGroups);
415  DEV_ASSERT(adcPalState[instIdx].groupArray != NULL);
416 
417  const adc_pal_state_t * const palState = &(adcPalState[instIdx]);
418  const adc_group_config_t * const currentGroupCfg = &(palState->groupArray[groupIdx]);
419  const adc_group_state_t * const currentGroupState = ADC_GetHwGroupStatePtr(instIdx, groupIdx);
420  status_t status = STATUS_SUCCESS;
421  status_t statusTrgmux = STATUS_SUCCESS;
422  (void) statusTrgmux;
423 
424  DEV_ASSERT(currentGroupCfg->hwTriggerSupport == true);
425  (void) currentGroupCfg;
426 
427  if((palState->swTrigGroupState.active == true) || (currentGroupState->active == true))
428  {
429  /* A conversion group is already active */
430  status = STATUS_BUSY;
431  }
432  else
433  {
434  /* Update ADC PAL and group state structures */
435  ADC_PalStateUpdateStart(instIdx, groupIdx);
436 
437 #if defined(ADC_PAL_S32K1xx)
438 
439  /* Enable the ADC interrupt from Interrupt Manager */
440  IRQn_Type adcIrqId;
441  adcIrqId = ADC_DRV_GetInterruptNumber(instIdx);
442  INT_SYS_EnableIRQ(adcIrqId);
443 
444  /* The group shall be configured each time it is enabled. */
445  ADC_ConfigGroup(instIdx, groupIdx, true);
446 
447  /* Enable in TRGMUX the selected HW trigger source for PDB.
448  * Must be called after all PDB pre-triggers have been configured, to make sure no triggers occur during configuration. */
449  statusTrgmux = TRGMUX_DRV_SetTrigSourceForTargetModule(ADC_PAL_TRGMUX_IDX, currentGroupCfg->triggerSource, adcPalTrgmuxTarget[instIdx]);
450  DEV_ASSERT(statusTrgmux == STATUS_SUCCESS);
451 
452 #elif defined(ADC_PAL_MPC574xC_G_R)
453  const uint8_t numChans = (palState->groupArray[groupIdx]).numChannels;
454 
455  if(numChans == 1u)
456  {
457  INT_SYS_EnableIRQ(BCTU_ConvUpdate_IRQn);
458  }
459  else
460  {
461  INT_SYS_EnableIRQ(BCTU_ListLast_IRQn);
462  }
463 
464  /* De-activate low-power mode. Any pending triggers will become active, immediately triggering a conversion. */
465  BCTU_DRV_SetLowPowerMode(instIdx, false);
466 
467  /* All groups get configured at ADC PAL initialization,
468  * so here they only need to be enabled. */
469  BCTU_DRV_EnableHwTrigger(instIdx, currentGroupCfg->triggerSource);
470 
471 #elif defined(ADC_PAL_MPC574xP)
472  /* internalTrigIdx is mapped 1:1 with stateIdx */
473  const uint32_t internalTrigIdx = palState->stateIdxMapping[groupIdx];
474  const uint32_t shift = internalTrigIdx * CTU_THCR1_T1_ADCE_SHIFT;
475  CTU_Type * const ctuInstBase = ctuBase[instIdx];
476 
477  /* Enable internal trigger corresponding to current groupIdx */
478  ctuInstBase->THCR1 |= (uint32_t)CTU_OUTPUT_TRIG_EN << shift; /* Assumes: internalTrigIdx < 4 */
479 
480  /* THCR is double-buffered, so mark that MRS can reload the value */
481  CTU_DRV_EnableGeneralReload(instIdx);
482 
483 #endif /* defined(ADC_PAL_MPC574xP) */
484 
485  status = STATUS_SUCCESS;
486  }
487 
488  return status;
489 }
490 
491 
492 /*FUNCTION**********************************************************************
493  *
494  * Function Name : ADC_DisableHardwareTrigger
495  * Description : Disables the selected HW trigger for a conversion group,
496  * if the conversion group has support for HW trigger.
497  *
498  * Implements : ADC_DisableHardwareTrigger_Activity
499  *END**************************************************************************/
500 status_t ADC_DisableHardwareTrigger(const adc_instance_t * const instance, const uint32_t groupIdx, const uint32_t timeout)
501 {
502  DEV_ASSERT(instance != NULL);
503 
504  uint32_t instIdx = instance->instIdx;
505  adc_group_state_t * const currentGroupState = ADC_GetHwGroupStatePtr(instIdx, groupIdx);
506 
507  DEV_ASSERT(instIdx < NUMBER_OF_ADC_PAL_INSTANCES);
508  DEV_ASSERT(groupIdx < adcPalState[instIdx].numGroups);
509  DEV_ASSERT(adcPalState[instIdx].groupArray != NULL);
510  DEV_ASSERT(adcPalState[instIdx].groupArray[groupIdx].hwTriggerSupport == true);
511 
512  status_t status = STATUS_SUCCESS;
513 
514  /* Make sure no more notifications are received from current groupIdx */
515  status = ADC_DisableNotification(instance, groupIdx);
516 
517  if((currentGroupState->active == true) && (status == STATUS_SUCCESS))
518  {
519 #if defined(ADC_PAL_S32K1xx)
520  /* Disable from TRGMUX the trigger source for PDB */
521  status = TRGMUX_DRV_SetTrigSourceForTargetModule(ADC_PAL_TRGMUX_IDX, TRGMUX_TRIG_SOURCE_DISABLED, adcPalTrgmuxTarget[instIdx]);
522  DEV_ASSERT(status == STATUS_SUCCESS);
523 
524  status = ADC_StopGroupBlocking(instIdx, timeout);
525 
526 #elif defined(ADC_PAL_MPC574xC_G_R)
527  const adc_pal_state_t * const palState = &(adcPalState[instIdx]);
528  const adc_trigger_source_t triggerSource = palState->groupArray[groupIdx].triggerSource;
529  const uint8_t numChans = palState->groupArray[groupIdx].numChannels;
530  uint32_t startTime, deltaTime;
531 
532  if(numChans == 1u)
533  {
534  INT_SYS_DisableIRQ(BCTU_ConvUpdate_IRQn);
535  }
536  else
537  {
538  INT_SYS_DisableIRQ(BCTU_ListLast_IRQn);
539  }
540 
541  OSIF_TimeDelay(0u); /* Make sure OSIF timer is initialized. */
542 
543  startTime = OSIF_GetMilliseconds();
544  deltaTime = 0u;
545 
546  /* Prevent new conversions from starting */
547  BCTU_DRV_DisableHwTrigger(instIdx, triggerSource);
548 
549  /* Check if conversion is still running until execution finished or timeout occurred */
550  while((BCTU_DRV_IsConvRunning(instIdx, triggerSource) == true) && (deltaTime < timeout))
551  {
552  deltaTime = OSIF_GetMilliseconds() - startTime;
553  }
554 
555  if(deltaTime >= timeout)
556  {
557  status = STATUS_TIMEOUT;
558  }
559  else
560  {
561  status = STATUS_SUCCESS;
562 
563  /* Activate low-power mode */
564  BCTU_DRV_SetLowPowerMode(instIdx, true);
565  }
566 
567 #elif defined(ADC_PAL_MPC574xP)
568  const adc_pal_state_t * const palState = &(adcPalState[instIdx]);
569  /* internalTrigIdx is mapped 1:1 with stateIdx */
570  const uint32_t internalTrigIdx = palState->stateIdxMapping[groupIdx];
571  const uint32_t shift = internalTrigIdx * CTU_THCR1_T1_ADCE_SHIFT;
572  CTU_Type * const ctuInstBase = ctuBase[instIdx];
573 
574  (void) timeout;
575 
576  /* Disable internal trigger corresponding to current groupIdx */
577  /* Register is double-buffered so the new value will not have effect in the current control cycle
578  * - only after a new MRS occurs */
579  ctuInstBase->THCR1 &= ~((uint32_t)CTU_OUTPUT_TRIG_EN << shift); /* Assumes: fifoIdx < 4 */
580 
581  /* THCR is double-buffered, so mark that MRS can reload the value. */
582  CTU_DRV_EnableGeneralReload(instIdx);
583 
584  currentGroupState->active = false;
585 
586 #endif /* defined(ADC_PAL_MPC574xP) */
587 
588 #ifndef ADC_PAL_MPC574xP
589  if(status == STATUS_SUCCESS)
590  {
591  currentGroupState->active = false;
592  }
593 #endif /* ADC_PAL_MPC574xP */
594  }
595 
596 
597  return status;
598 }
599 
600 /*FUNCTION**********************************************************************
601  *
602  * Function Name : ADC_StartGroupConversion
603  * Description : Starts the execution of a selected ADC conversion group.
604  *
605  * Implements : ADC_StartGroupConversion_Activity
606  *END**************************************************************************/
607 status_t ADC_StartGroupConversion(const adc_instance_t * const instance, const uint32_t groupIdx)
608 {
609  DEV_ASSERT(instance != NULL);
610 
611  uint32_t instIdx = instance->instIdx;
612  DEV_ASSERT(instIdx < NUMBER_OF_ADC_PAL_INSTANCES);
613 
614  const adc_pal_state_t * const palState = &(adcPalState[instIdx]);
615  DEV_ASSERT(groupIdx < palState->numGroups);
616  DEV_ASSERT(palState->groupArray != NULL);
617  DEV_ASSERT(palState->groupArray[groupIdx].hwTriggerSupport == false);
618 
619  status_t status;
620 
621  if((ADC_AnyHwTrigGroupActive(instIdx) == true) || (palState->swTrigGroupState.active == true))
622  {
623  /* Any other conversion group is already active */
624  status = STATUS_BUSY;
625  }
626  else
627  {
628  /* Update ADC PAL and group state structures */
629  ADC_PalStateUpdateStart(instIdx, groupIdx);
630 
631 #if defined(ADC_PAL_S32K1xx)
632  DEV_ASSERT(palState->groupArray[groupIdx].numChannels <= ADC_PAL_MAX_CONVS_IN_GROUP);
633 
634  bool hwTriggerEnabled = false;
635 
636  /* Enable the ADC interrupt from Interrupt Manager */
637  IRQn_Type adcIrqId;
638  adcIrqId = ADC_DRV_GetInterruptNumber(instIdx);
639  INT_SYS_EnableIRQ(adcIrqId);
640 
641  ADC_ConfigGroup(instIdx, groupIdx, hwTriggerEnabled);
642 
643  /* Sw trigger PDB */
644  PDB_DRV_SoftTriggerCmd(instIdx);
645 
646 #elif (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
647 
648  const adc_group_config_t * currentGroupCfg = &(palState->groupArray[groupIdx]);
649  uint8_t idx, adcIdx;
650  uint32_t currentChan;
651 
652  /* Assumes that all channels in the group target the same ADC instance */
653  adcIdx = ADC_GetAdcAbsoluteIdx(currentGroupCfg->inputChannelArray[0u]);
654 
655 #if defined(ADC_PAL_MPC574xP)
656  adcBase[adcIdx]->MCR &= ~(ADC_MCR_CTUEN(1u)); /* set ADC to CTU MODE DISABLED, to allow SW triggering */
657 #endif /* defined(ADC_PAL_MPC574xP) */
658 
659  INT_SYS_EnableIRQ(adcEocIrqNums[adcIdx]);
660 
661  for(idx = 0u; idx < currentGroupCfg->numChannels; idx++)
662  {
663  DEV_ASSERT(adcIdx == ADC_GetAdcAbsoluteIdx(currentGroupCfg->inputChannelArray[idx])); /* channels in the group must target the same ADC instance */
664  currentChan = ADC_GetChanIdx(currentGroupCfg->inputChannelArray[idx]);
665 
666  ADC_DRV_EnableChannel(adcIdx, ADC_CONV_CHAIN_NORMAL, currentChan);
667  }
668 
669  ADC_DRV_StartConversion(adcIdx, ADC_CONV_CHAIN_NORMAL);
670 
671 #endif /* (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
672 
673  status = STATUS_SUCCESS;
674  }
675 
676  return status;
677 }
678 
679 /*FUNCTION**********************************************************************
680  *
681  * Function Name : ADC_StopGroupConversion
682  * Description : Stops the execution of the ADC group currently executing.
683  *
684  * Implements : ADC_StopGroupConversion_Activity
685  *END**************************************************************************/
686 status_t ADC_StopGroupConversion(const adc_instance_t * const instance, const uint32_t groupIdx, const uint32_t timeout)
687 {
688  DEV_ASSERT(instance != NULL);
689 
690  uint32_t instIdx = instance->instIdx;
691  DEV_ASSERT(instIdx < NUMBER_OF_ADC_PAL_INSTANCES);
692  DEV_ASSERT(groupIdx < adcPalState[instIdx].numGroups);
693  DEV_ASSERT(adcPalState[instIdx].groupArray != NULL);
694  DEV_ASSERT(adcPalState[instIdx].groupArray[groupIdx].hwTriggerSupport == false);
695 
696  status_t status = STATUS_SUCCESS;
697 
698  if(adcPalState[instIdx].swTrigGroupState.active == true)
699  {
700 #if defined(ADC_PAL_S32K1xx)
701  (void) groupIdx;
702 
703  /* Disable the ADC interrupt from Interrupt Manager */
704  IRQn_Type adcIrqId;
705  adcIrqId = ADC_DRV_GetInterruptNumber(instIdx);
706  INT_SYS_DisableIRQ(adcIrqId);
707 
708  status = ADC_StopGroupBlocking(instIdx, timeout);
709 
710 #elif (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
711 
712  const adc_group_config_t * currentGroupCfg = &(adcPalState[instIdx].groupArray[groupIdx]);
713  uint8_t idx, adcIdx;
714  uint32_t currentChan;
715  uint32_t startTime, deltaTime;
716 
717  OSIF_TimeDelay(0u); /* Make sure OSIF timer is initialized. */
718 
719  startTime = OSIF_GetMilliseconds();
720  deltaTime = 0u;
721 
722  /* Assumes that all channels in the group target the same ADC */
723  adcIdx = ADC_GetAdcAbsoluteIdx(currentGroupCfg->inputChannelArray[0u]);
724 
725  INT_SYS_EnableIRQ(adcEocIrqNums[adcIdx]);
726 
727  /* Disable channels from current conversion group */
728  for(idx = 0u; idx < currentGroupCfg->numChannels; idx++)
729  {
730  currentChan = ADC_GetChanIdx(currentGroupCfg->inputChannelArray[idx]);
731 
732  ADC_DRV_DisableChannel(adcIdx, ADC_CONV_CHAIN_NORMAL, currentChan);
733  }
734 
735  /* Check if conversion is still running, until execution finished or timeout occurred */
736  while(((ADC_DRV_GetStatusFlags(adcIdx) & ADC_FLAG_NORMAL_STARTED) != 0u) && (deltaTime < timeout))
737  {
738  deltaTime = OSIF_GetMilliseconds() - startTime;
739  }
740 
741  /* Clear status & pending flags corresponding to a conversion group
742  * which may have finished after interrupts have been disabled */
743  ADC_DRV_ClearStatusFlags(adcIdx, ADC_FLAG_NORMAL_ENDCHAIN);
745  ADC_Type * const base = s_adcBase[instIdx];
746  for(idx = 0u; idx < ADC_CEOCFR_COUNT; idx++)
747  {
748  base->CEOCFR[idx] |= 0xFFFFFFFFu;
749  }
750 
751  if(deltaTime >= timeout)
752  {
753  status = STATUS_TIMEOUT;
754  }
755  else
756  {
757 #if defined(ADC_PAL_MPC574xP)
758  adcBase[adcIdx]->MCR |= ADC_MCR_CTUEN(1u); /* set ADC to CTU CONTROL MODE, to allow HW triggering */
759 #endif /* defined(ADC_PAL_MPC574xP) */
760 
761  status = STATUS_SUCCESS;
762  }
763 #endif /* (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
764 
765  if(status == STATUS_SUCCESS)
766  {
767  adcPalState[instIdx].swTrigGroupState.active = false;
768  }
769  }
770  else
771  {
772  status = STATUS_ERROR;
773  }
774 
775  return status;
776 }
777 
778 
779 /*FUNCTION**********************************************************************
780  *
781  * Function Name : ADC_EnableNotification
782  * Description : Enables the notification callback for a configured group.
783  *
784  * Implements : ADC_EnableNotification_Activity
785  *END**************************************************************************/
786 status_t ADC_EnableNotification(const adc_instance_t * const instance, const uint32_t groupIdx)
787 {
788  DEV_ASSERT(instance != NULL);
789 
790  uint32_t instIdx = instance->instIdx;
791  DEV_ASSERT(instIdx < NUMBER_OF_ADC_PAL_INSTANCES);
792 
793  adc_pal_state_t * const palState = &(adcPalState[instIdx]);
794  const adc_group_config_t * currentGroupCfg = &(adcPalState[instIdx].groupArray[groupIdx]);
795  adc_group_state_t * groupState;
796 
797  DEV_ASSERT(groupIdx < palState->numGroups);
798 
799  status_t status = STATUS_SUCCESS;
800 
801  if(currentGroupCfg->hwTriggerSupport == true)
802  {
803  groupState = ADC_GetHwGroupStatePtr(instIdx, groupIdx);
804  }
805  else
806  {
807  groupState = &(palState->swTrigGroupState);
808  }
809 
810  if(groupState->active == false)
811  {
812  status = STATUS_ERROR;
813  }
814  else
815  {
816 #if (defined(ADC_PAL_S32K1xx) || defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
817 
818  DEV_ASSERT(palState->groupArray[groupIdx].callback != NULL);
819 
820  groupState->notificationEn = true;
821 
822 #endif /* (defined(ADC_PAL_S32K1xx) || defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
823  }
824 
825  return status;
826 }
827 
828 /*FUNCTION**********************************************************************
829  *
830  * Function Name : ADC_DisableNotification
831  * Description : Disables the notification callback for a configured group.
832  *
833  * Implements : ADC_DisableNotification_Activity
834  *END**************************************************************************/
835 status_t ADC_DisableNotification(const adc_instance_t * const instance, const uint32_t groupIdx)
836 {
837  DEV_ASSERT(instance != NULL);
838 
839  uint32_t instIdx = instance->instIdx;
840  DEV_ASSERT(instIdx < NUMBER_OF_ADC_PAL_INSTANCES);
841 
842  adc_pal_state_t * const palState = &(adcPalState[instIdx]);
843  const adc_group_config_t * currentGroupCfg = &(adcPalState[instIdx].groupArray[groupIdx]);
844  adc_group_state_t * groupState;
845 
846  DEV_ASSERT(groupIdx < palState->numGroups);
847 
848  status_t status = STATUS_SUCCESS;
849 
850  if(currentGroupCfg->hwTriggerSupport == true)
851  {
852  groupState = ADC_GetHwGroupStatePtr(instIdx, groupIdx);
853  }
854  else
855  {
856  groupState = &(palState->swTrigGroupState);
857  }
858 
859  if(groupState->active == false)
860  {
861  status = STATUS_ERROR;
862  }
863  else
864  {
865 #if (defined(ADC_PAL_S32K1xx) || defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
866 
867  groupState->notificationEn = false;
868 
869 #endif /* (defined(ADC_PAL_S32K1xx) || defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
870  }
871 
872  return status;
873 }
874 
875 
876 /*******************************************************************************
877  * Private Functions
878  ******************************************************************************/
879 
880 #if defined(ADC_PAL_S32K1xx)
881 
882 
883 static status_t ADC_Init_S32K1xx(const uint32_t instance, const adc_config_t * const config)
884 {
885  const extension_adc_s32k1xx_t * const extension = (extension_adc_s32k1xx_t *)(config->extension);
886  adc_converter_config_t adcCfg;
887  status_t status;
888 
889  DEV_ASSERT(extension->inputClock <= NUMBER_OF_ALT_CLOCKS);
890 
891 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
892  {
893  uint16_t idx;
894  uint16_t idx0, idx1;
895  const adc_group_config_t * currentGroupCfg;
896 
897  /* Iterate over all conversion groups */
898  for(idx = 0u; idx < adcPalState[instance].numGroups; idx++)
899  {
900  currentGroupCfg = &(adcPalState[instance].groupArray[idx]);
901  /* Error if number of conversions is larger than max supported */
902  DEV_ASSERT(currentGroupCfg->numChannels <= ADC_PAL_MAX_CONVS_IN_GROUP);
903 
904  if(currentGroupCfg->delayType == ADC_DELAY_TYPE_INDIVIDUAL_DELAY)
905  {
906  /* Delay values are measured relative to the trigger event.
907  * The pretriggers must not occur while another conversion in the group is running, otherwise the ADC freezes.
908  * This code only checks that the values are not identical, but it is the users' responsibility
909  * to make sure they do not overlap, i.e. delayN_plus_1 > (delayN + conversion_duration) */
910  for(idx0 = 0u; idx0 < currentGroupCfg->numChannels; idx0++)
911  {
912  for(idx1 = idx0 + 1u; idx1 < currentGroupCfg->numChannels; idx1++)
913  {
914  DEV_ASSERT(currentGroupCfg->delayArray[idx0] != currentGroupCfg->delayArray[idx1]);
915  }
916  }
917  }
918  }
919  }
920 #endif /* defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT) */
921 
922  /* ADC configuration */
923  ADC_DRV_Reset(instance);
924 
926  adcCfg.trigger = ADC_TRIGGER_HARDWARE; /* ADC in hw trigger mode - sw triggering shall be done via PDB */
927  adcCfg.sampleTime = config->sampleTicks;
928  adcCfg.clockDivide = extension->clockDivide;
929  adcCfg.resolution = extension->resolution;
930  adcCfg.inputClock = extension->inputClock;
931  adcCfg.voltageRef = extension->voltageRef;
932  adcCfg.supplyMonitoringEnable = extension->supplyMonitoringEnable;
933  adcCfg.pretriggerSel = ADC_PRETRIGGER_SEL_PDB; /* configure pretriggers 0->3 to be routed from PDB */
934 
935  ADC_DRV_ConfigConverter(instance, &adcCfg);
936 
937  ADC_DRV_AutoCalibration(instance);
938 
939  /* PDB init shall only be called from StartConversion() & EnableHardwareTrigger()
940  * because PDB input source and continuous conversion enable need to be configured for each call. */
941 
942  /* Only reset the trgmux target register corresponding to PDB instance.
943  * Calling TRGMUX init would reset all TRGMUX target registers - affecting other modules. */
944  status = TRGMUX_DRV_SetTrigSourceForTargetModule(ADC_PAL_TRGMUX_IDX, TRGMUX_TRIG_SOURCE_DISABLED, adcPalTrgmuxTarget[instance]);
945  if(status != STATUS_SUCCESS)
946  {
947  status = STATUS_ERROR;
948  }
949 
950  return status;
951 }
952 
953 
954 /*FUNCTION**********************************************************************
955  *
956  * Function Name : ADC_S32K1xx_IrqHandler
957  * Description : Implements interrupt handler functionality to be called from
958  * interrupt handlers for each ADC.
959  *
960  *END**************************************************************************/
961 void ADC_S32K1xx_IrqHandler(const uint32_t instIdx)
962 {
963  adc_pal_state_t * const palState = &(adcPalState[instIdx]);
964  const uint32_t currentGroupIdx = palState->latestGroupIdx;
965  uint8_t controlChanIdx = 0u;
966  const adc_group_config_t * activeGroupCfg;
967  adc_group_state_t * groupState;
968 
969  activeGroupCfg = &(palState->groupArray[currentGroupIdx]);
970 
971  if(activeGroupCfg->hwTriggerSupport == false)
972  {
973  groupState = &(palState->swTrigGroupState);
974  }
975  else
976  {
977  groupState = &(palState->hwTrigGroupState[0u]); /* A single HW trigger enabled is supported by this platform */
978  }
979 
980  uint16_t * result = &(activeGroupCfg->resultBuffer[groupState->currentBufferOffset]);
981 
982  /* Read all conversion results */
983  for(controlChanIdx = 0u; controlChanIdx < activeGroupCfg->numChannels; controlChanIdx++)
984  {
985  ADC_DRV_GetChanResult(instIdx, controlChanIdx, result); /* interrupt flag is cleared when reading the result */
986  result++;
987  }
988  /* Increment offset in result buffer */
989  groupState->currentBufferOffset = (uint16_t)((groupState->currentBufferOffset + activeGroupCfg->numChannels) % groupState->bufferLength);
990 
991 
992  if(activeGroupCfg->hwTriggerSupport == false) /* Continuous mode currently supported only for SW triggered groups */
993  {
994  if(activeGroupCfg->continuousConvEn == true)
995  {
996  /* Sw trigger PDB */
997  PDB_DRV_SoftTriggerCmd(instIdx);
998  }
999  else
1000  {
1001  groupState->active = false;
1002  }
1003  }
1004 
1005  /* Call notification callback, if it is enabled */
1006  ADC_CallNotificationCb(palState, currentGroupIdx, groupState);
1007 }
1008 
1009 
1010 /*FUNCTION**********************************************************************
1011  *
1012  * Function Name : ADC_ConfigPdbAndPretriggers
1013  * Description : Configures PDB global parameters, PDB pretriggers and delays (if used)
1014  *
1015  *END**************************************************************************/
1016 static inline void ADC_ConfigPdbAndPretriggers(const uint32_t instIdx, const pdb_trigger_src_t trgSrc, const adc_group_config_t * currentGroupCfg)
1017 {
1018  pdb_timer_config_t pdbCfg;
1019  pdb_adc_pretrigger_config_t pdbPretrigCfg;
1020  uint8_t idx;
1021 
1022  /* PDB driver instance configuration */
1024  pdbCfg.seqErrIntEnable = false;
1025  pdbCfg.clkPreDiv = adcPalState[instIdx].pdbPrescaler;
1027  pdbCfg.dmaEnable = false;
1028  pdbCfg.intEnable = false;
1029  pdbCfg.continuousModeEnable = false; /* Continuous mode refers to Counter being reset at zero - not used in ADC PAL */
1030 
1031  pdbCfg.triggerInput = trgSrc;
1032  PDB_DRV_Init(instIdx, &pdbCfg);
1033 
1034  if(currentGroupCfg->delayType == ADC_DELAY_TYPE_NO_DELAY)
1035  {
1036  /* PDB pre-triggers configuration */
1037  pdbPretrigCfg.preTriggerEnable = true;
1038  pdbPretrigCfg.preTriggerOutputEnable = false; /* pretrigger asserts one clock cycle after input trigger is asserted (hw or sw) */
1039  pdbPretrigCfg.preTriggerBackToBackEnable = false; /* the first pretrigger in the group must have BB disabled */
1040  pdbPretrigCfg.adcPreTriggerIdx = 0u;
1041  PDB_DRV_ConfigAdcPreTrigger(instIdx, ADC_PAL_PDB_CHAN, &pdbPretrigCfg);
1042 
1043  pdbPretrigCfg.preTriggerBackToBackEnable = true; /* the rest of pretriggers in the group must have BB enabled */
1044  for(idx = 1u; idx < currentGroupCfg->numChannels; idx++)
1045  {
1046  pdbPretrigCfg.adcPreTriggerIdx = idx;
1047  PDB_DRV_ConfigAdcPreTrigger(instIdx, ADC_PAL_PDB_CHAN, &pdbPretrigCfg);
1048  }
1049  }
1050  else if(currentGroupCfg->delayType == ADC_DELAY_TYPE_GROUP_DELAY)
1051  {
1052  DEV_ASSERT(currentGroupCfg->delayArray != NULL);
1053 
1054  /* PDB pre-triggers configuration */
1055  pdbPretrigCfg.preTriggerEnable = true;
1056  pdbPretrigCfg.preTriggerOutputEnable = true; /* the first pretrigger asserts when counter reaches delay value plus one */
1057  pdbPretrigCfg.preTriggerBackToBackEnable = false; /* the first pretrigger in the group must have BB disabled */
1058  pdbPretrigCfg.adcPreTriggerIdx = 0u;
1059  PDB_DRV_ConfigAdcPreTrigger(instIdx, ADC_PAL_PDB_CHAN, &pdbPretrigCfg);
1060 
1061  PDB_DRV_SetAdcPreTriggerDelayValue(instIdx, ADC_PAL_PDB_CHAN, pdbPretrigCfg.adcPreTriggerIdx, *(currentGroupCfg->delayArray));
1062 
1063  pdbPretrigCfg.preTriggerOutputEnable = false; /* the rest of pretriggers in the group must ignore the delay value */
1064  pdbPretrigCfg.preTriggerBackToBackEnable = true; /* the rest of pretriggers in the group must have BB enabled */
1065  for(idx = 1u; idx < currentGroupCfg->numChannels; idx++)
1066  {
1067  pdbPretrigCfg.adcPreTriggerIdx = idx;
1068  PDB_DRV_ConfigAdcPreTrigger(instIdx, ADC_PAL_PDB_CHAN, &pdbPretrigCfg);
1069  }
1070  }
1071  else /* corresponds to currentGroupCfg->delayType == ADC_DELAY_TYPE_INDIVIDUAL_DELAY */
1072  {
1073  DEV_ASSERT(currentGroupCfg->delayArray != NULL);
1074 
1075  /* PDB pre-triggers configuration */
1076  pdbPretrigCfg.preTriggerEnable = true;
1077  pdbPretrigCfg.preTriggerOutputEnable = true; /* each pretrigger asserts when counter reaches corresponding delay value plus one */
1078  pdbPretrigCfg.preTriggerBackToBackEnable = false; /* all pretriggers in the group must have BB disabled */
1079  for(idx = 0u; idx < currentGroupCfg->numChannels; idx++)
1080  {
1081  pdbPretrigCfg.adcPreTriggerIdx = idx;
1082  PDB_DRV_ConfigAdcPreTrigger(instIdx, ADC_PAL_PDB_CHAN, &pdbPretrigCfg);
1083 
1084  PDB_DRV_SetAdcPreTriggerDelayValue(instIdx, ADC_PAL_PDB_CHAN, pdbPretrigCfg.adcPreTriggerIdx, currentGroupCfg->delayArray[idx]);
1085  }
1086  }
1087 
1088  PDB_DRV_Enable(instIdx);
1089  PDB_DRV_LoadValuesCmd(instIdx);
1090 }
1091 
1092 
1093 /*FUNCTION**********************************************************************
1094  *
1095  * Function Name : ADC_ConfigGroup
1096  * Description : Configures ADC input channels and PDB for a conversion group
1097  *
1098  *END**************************************************************************/
1099 static void ADC_ConfigGroup(const uint32_t instance, const uint32_t groupIdx, const bool hwTriggerFlag)
1100 {
1101  const adc_group_config_t * const currentGroupCfg = &(adcPalState[instance].groupArray[groupIdx]);
1102 
1103  pdb_trigger_src_t pdbTrigSrc;
1104  if(hwTriggerFlag == true)
1105  {
1106  pdbTrigSrc = PDB_TRIGGER_IN0;
1107  }
1108  else
1109  {
1110  pdbTrigSrc = PDB_SOFTWARE_TRIGGER;
1111  /* SW triggered groups do not support delays */
1112  DEV_ASSERT(currentGroupCfg->delayType == ADC_DELAY_TYPE_NO_DELAY);
1113  }
1114 
1115  /* Configure PDB instance and pre-triggers */
1116  ADC_ConfigPdbAndPretriggers(instance, pdbTrigSrc, currentGroupCfg);
1117 
1118  /* Configure ADC channels */
1119  adc_chan_config_t adcChanCfg;
1120  uint8_t idx;
1121 
1122  adcChanCfg.interruptEnable = false; /* interrupt is disabled for all conversion, except the last one in the group */
1123  for(idx = 0u; idx < (currentGroupCfg->numChannels - 1u); idx++)
1124  {
1125  adcChanCfg.channel = currentGroupCfg->inputChannelArray[idx]; /* set the ADC input channel */
1126 
1127  ADC_DRV_ConfigChan(instance, idx, &adcChanCfg); /* conversion complete flag is cleared implicitly when writing a new configuration */
1128  }
1129  adcChanCfg.interruptEnable = true; /* enable interrupt for last conversion in the group */
1130  adcChanCfg.channel = currentGroupCfg->inputChannelArray[idx]; /* set the ADC input channel */
1131  ADC_DRV_ConfigChan(instance, idx, &adcChanCfg); /* configure the last conversion in the group */
1132 }
1133 
1134 /*FUNCTION**********************************************************************
1135  *
1136  * Function Name : ADC_StopGroupBlocking
1137  * Description : Stops a group of conversions within a given timeout interval
1138  *
1139  *END**************************************************************************/
1140 static status_t ADC_StopGroupBlocking(const uint32_t instance, const uint32_t timeout)
1141 {
1142  const adc_pal_state_t * const palState = &(adcPalState[instance]);
1143  uint32_t startTime, deltaTime;
1144  status_t status;
1145  pdb_adc_pretrigger_config_t pdbPretrigCfg;
1146  uint8_t idx;
1147 
1148  /* Make sure OSIF timer is initialized. */
1149  OSIF_TimeDelay(0u);
1150 
1151  startTime = OSIF_GetMilliseconds();
1152  deltaTime = 0u;
1153 
1154  /* Reset PDB pre-trigger configurations to stop PDB from triggering other conversions in the group */
1155  pdbPretrigCfg.preTriggerEnable = false;
1156  pdbPretrigCfg.preTriggerOutputEnable = false;
1157  pdbPretrigCfg.preTriggerBackToBackEnable = false;
1158  for(idx = 0u; idx < palState->groupArray[palState->latestGroupIdx].numChannels; idx++)
1159  {
1160  pdbPretrigCfg.adcPreTriggerIdx = idx;
1161  PDB_DRV_ConfigAdcPreTrigger(instance, ADC_PAL_PDB_CHAN, &pdbPretrigCfg);
1162  }
1163  /* Completely stop PDB */
1164  PDB_DRV_Deinit((uint32_t)instance);
1165 
1166  /* Wait for current ADC active conversion to finish execution */
1167  ADC_Type * const adcBase[ADC_INSTANCE_COUNT] = ADC_BASE_PTRS;
1168  const ADC_Type * const base = adcBase[instance];
1169  while((ADC_GetConvActiveFlag(base) == true) && (deltaTime < timeout))
1170  {
1171  deltaTime = OSIF_GetMilliseconds() - startTime;
1172  }
1173 
1174  if(deltaTime >= timeout)
1175  {
1176  status = STATUS_TIMEOUT;
1177  }
1178  else
1179  {
1180  status = STATUS_SUCCESS;
1181  }
1182 
1183  return status;
1184 }
1185 
1186 #elif defined(ADC_PAL_MPC574xC_G_R)
1187 
1188 
1189 
1190 static status_t ADC_Init_MPC574xC_G_R(const uint32_t instIdx, const adc_config_t * const config)
1191 {
1192  const adc_group_config_t * currentGroup;
1193  bctu_config_t bctuCfg;
1194  status_t status;
1195  uint8_t idx;
1196 
1197  ADC_ConfigAdcMPC574x(instIdx, config);
1198 
1199  /* Configure BCTU */
1200  status = BCTU_DRV_Reset(instIdx, /* default timeout value 2ms*/ 2u);
1201  if(status == STATUS_TIMEOUT)
1202  {
1203  status = STATUS_BUSY;
1204  }
1205  else
1206  {
1207  BCTU_DRV_GetDefaultConfig(&bctuCfg);
1208  bctuCfg.lowPowerModeEn = true; /* Low power mode is enabled by default until a HW triggered group is enabled (only HW triggered groups use BCTU) */
1209  /* Used for HW triggered groups with a single conversion. By default enable new data interrupt for both ADCs */
1210  bctuCfg.newDataIntEnMask = (((uint8_t)1u << FEATURE_BCTU_NUM_ADC) - 1u);
1211  bctuCfg.listIntEn = true; /* Used for HW triggered groups with multiple conversions */
1212 
1213  BCTU_DRV_Config(instIdx, &bctuCfg);
1214 
1215  uint8_t bctuNumChansList = 0u; /* total number of channels programmed in BCTU list */
1216 
1217  /* Configure all HW triggered groups in BCTU.
1218  * SW triggered groups will be configured directly in ADC, each time ADC_StartGroupConversion() is called. */
1219  for(idx = 0u; idx < config->numGroups; idx++)
1220  {
1221  currentGroup = &(config->groupConfigArray[idx]);
1222  DEV_ASSERT(currentGroup->inputChannelArray != NULL);
1223 
1224  if(currentGroup->hwTriggerSupport == true)
1225  {
1226  status = ADC_ConfigHwTriggeredGroup(instIdx, currentGroup, bctuNumChansList);
1227 
1228  if(currentGroup->numChannels > 1u)
1229  {
1230  bctuNumChansList += currentGroup->numChannels; /* Increment total number of channels programmed into BCTU LIST */
1231  }
1232  }
1233  }
1234 
1235 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
1236  {
1237  ADC_CheckChanDuplicate(config);
1238  }
1239 #endif /* defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT) */
1240 
1241  /* Move BCTU out of configuration mode */
1242  BCTU_DRV_WriteGlobalTriggerEn(instIdx, true);
1243  }
1244 
1245  return status;
1246 }
1247 
1248 
1249 /*FUNCTION**********************************************************************
1250  *
1251  * Function Name : ADC_MPC574xC_G_R_HwTrigIrqHandler
1252  * Description : Implements interrupt handler functionality for HW triggered
1253  * conversion groups - to be called from BCTU interrupt handler.
1254  *
1255  *END**************************************************************************/
1256 void ADC_MPC574xC_G_R_HwTrigIrqHandler(const uint32_t instIdx, const uint8_t adcIdx)
1257 {
1258  const adc_pal_state_t * const palState = &(adcPalState[instIdx]);
1259  const adc_group_config_t * activeGroupCfg;
1260  adc_group_state_t * groupState;
1261  uint32_t currentGroupIdx;
1262  bctu_conv_result_t bctuResult;
1263  uint16_t * result;
1264 
1265  /* Get trigger idx for which the conv has finished */
1266  BCTU_DRV_GetConvResult(instIdx, adcIdx, &bctuResult);
1267  /* Get group idx assigned to the trigger idx */
1268  currentGroupIdx = ADC_GetGroupIdx(instIdx, bctuResult.triggerIdx);
1269 
1270  groupState = ADC_GetHwGroupStatePtr(instIdx, currentGroupIdx);
1271 
1272  activeGroupCfg = &(palState->groupArray[currentGroupIdx]);
1273 
1274  result = &(activeGroupCfg->resultBuffer[groupState->currentBufferOffset]);
1275 
1276  if(activeGroupCfg->numChannels == 1u)
1277  {
1278  *result = bctuResult.adcData;
1279 
1280  /* Increment offset in result buffer */
1281  groupState->currentBufferOffset = (groupState->currentBufferOffset + 1u) % groupState->bufferLength;
1282 
1283  BCTU_DRV_ClearStatusFlag(instIdx, adcIdx, BCTU_FLAG_NEW_DATA_AVAILABLE);
1284  DEV_ASSERT(BCTU_DRV_GetStatusFlag(instIdx, adcIdx, BCTU_FLAG_DATA_OVERRUN) == false);
1285  }
1286  else
1287  {
1288  /* Read all conversion results for the current conversion group */
1289  uint32_t numResRead = 0u;
1290  (void) numResRead;
1291  numResRead = ADC_DRV_GetConvResultsToArray(adcIdx, ADC_CONV_CHAIN_CTU, result, activeGroupCfg->numChannels);
1292  DEV_ASSERT(numResRead == activeGroupCfg->numChannels);
1293 
1294  /* Increment offset in result buffer */
1295  groupState->currentBufferOffset = (groupState->currentBufferOffset + activeGroupCfg->numChannels) % groupState->bufferLength;
1296 
1297  BCTU_DRV_ClearStatusFlag(instIdx, adcIdx, BCTU_FLAG_LIST_LAST_CONV);
1298  /* Clear because conversion results are not read from BCTU result register */
1299  BCTU_DRV_ClearStatusFlag(instIdx, adcIdx, BCTU_FLAG_NEW_DATA_AVAILABLE);
1300  /* Clear because BCTU result register is overwritten */
1301  BCTU_DRV_ClearStatusFlag(instIdx, adcIdx, BCTU_FLAG_DATA_OVERRUN);
1302  }
1303 
1304  /* Call notification callback, if it is enabled */
1305  ADC_CallNotificationCb(palState, currentGroupIdx, groupState);
1306 }
1307 
1308 
1309 /*FUNCTION**********************************************************************
1310  *
1311  * Function Name : ADC_ConfigHwTriggeredGroup
1312  * Description : Configure BCTU for a ADC PAL HW triggered group
1313  *
1314  *END**************************************************************************/
1315 static status_t ADC_ConfigHwTriggeredGroup(const uint32_t instIdx, const adc_group_config_t * const groupConfig, const uint8_t bctuStartListIdx)
1316 {
1317  const adc_input_chan_t * const inputChans = groupConfig->inputChannelArray;
1318  bctu_trig_config_t bctuTrigConfig;
1319  status_t bctuStatus;
1320  status_t status = STATUS_SUCCESS;
1321  const uint8_t numChans = groupConfig->numChannels;
1322 
1323  DEV_ASSERT(numChans > 0u);
1324  DEV_ASSERT(groupConfig->delayArray == NULL); /* Delays are not supported */
1325  DEV_ASSERT(groupConfig->delayType == ADC_DELAY_TYPE_NO_DELAY); /* Delays are not supported */
1326 
1327  bctuTrigConfig.adcTargetMask = (uint8_t)1u << (ADC_GetAdcAbsoluteIdx(inputChans[0]) % FEATURE_BCTU_NUM_ADC);
1328  bctuTrigConfig.hwTriggersEn = groupConfig->hwTriggerSupport;
1329  bctuTrigConfig.loopEn = groupConfig->continuousConvEn;
1330 
1331 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
1332  {
1333  /* Check that a trigger source is only used by a single HW triggered group. */
1334  static const BCTU_Type * const bctuBase[BCTU_INSTANCE_COUNT] = BCTU_BASE_PTRS;
1335  const BCTU_Type * bctu;
1336  bctu = bctuBase[instIdx];
1337  if(bctu->TRGCFG_[groupConfig->triggerSource] != 0u) /* Check if the BCTU trigger register has been already written */
1338  {
1339  /* A trigger source cannot be assigned to multiple HW triggered groups. */
1340  DEV_ASSERT(false);
1341  }
1342  }
1343 #endif /* defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT) */
1344 
1345  if(numChans == 1u) /* Configure groups containing a single conversion. */
1346  {
1347  bctuStatus = BCTU_DRV_ConfigTriggerSingle(instIdx, groupConfig->triggerSource, &bctuTrigConfig, ADC_GetChanIdx(inputChans[0]));
1348  DEV_ASSERT(bctuStatus == STATUS_SUCCESS);
1349  (void) bctuStatus;
1350  }
1351  else /* Configure groups containing more than a single conversion. */
1352  {
1353  /* Prepare array with adc channel indexes expressed in normal format, accepted by the BCTU driver */
1354  uint8_t adcChanIdx[ADC_PAL_MAX_CONVS_IN_GROUP_HW_TRIG];
1355  uint8_t idx;
1356  for(idx = 0u; idx < numChans; idx++)
1357  {
1358  adcChanIdx[idx] = ADC_GetChanIdx(inputChans[idx]);
1359 
1360 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
1361  const uint8_t firstChanIdx = ADC_GetAdcAbsoluteIdx(inputChans[0u]);
1362  /* Channels in the group must target the same ADC instance */
1363  DEV_ASSERT(ADC_GetAdcAbsoluteIdx(inputChans[idx]) == firstChanIdx);
1364 #endif /* defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT) */
1365  }
1366 
1367  /* For groups which include a minimum of 2 conversions, the total number of conversions within all these groups shall be less than
1368  * or equal with the number of BCTU LIST HW registers. Otherwise the first groups will be overwritten. */
1369  if((bctuStartListIdx + numChans) >= (uint8_t)ADC_PAL_MAX_CONVS_IN_GROUP_HW_TRIG)
1370  {
1371  status = STATUS_ERROR;
1372  }
1373  else
1374  {
1375  bctuStatus = BCTU_DRV_ConfigTriggerList(instIdx, groupConfig->triggerSource, &bctuTrigConfig, bctuStartListIdx);
1376  DEV_ASSERT(bctuStatus == STATUS_SUCCESS);
1377 
1378  BCTU_DRV_SetConvListArray(instIdx, bctuStartListIdx, adcChanIdx, numChans);
1379  }
1380  }
1381 
1382  return status;
1383 }
1384 
1385 /*FUNCTION**********************************************************************
1386  *
1387  * Function Name : ADC_GetGroupIdx
1388  * Description : Returns the ADC conversion group index, for which the HW trigger
1389  * source has been configured.
1390  *
1391  *END**************************************************************************/
1392 static uint32_t ADC_GetGroupIdx(const uint32_t instIdx, const adc_trigger_source_t hwTrigSource)
1393 {
1394  uint32_t groupIdx = 0u;
1395  bool found = false;
1396  const adc_pal_state_t * const palState = &(adcPalState[instIdx]);
1397 
1398  while((found == false) && (groupIdx < palState->numGroups))
1399  {
1400  if((palState->groupArray[groupIdx].triggerSource == hwTrigSource) \
1401  && (palState->groupArray[groupIdx].hwTriggerSupport == true))
1402  {
1403  found = true;
1404  }
1405  groupIdx++;
1406  }
1407  groupIdx--; /* compensate for additional groupIdx increment */
1408  DEV_ASSERT(found == true);
1409 
1410  return groupIdx;
1411 }
1412 
1413 
1414 #elif defined(ADC_PAL_MPC574xP)
1415 
1416 
1417 static status_t ADC_Init_MPC574xP(const uint32_t instIdx, const adc_config_t * const config)
1418 {
1419  const extension_adc_mpc574xp_t * const extension = (extension_adc_mpc574xp_t *)(config->extension);
1420  const adc_group_config_t * currentGroup;
1421  ctu_config_t ctuCfg;
1422  status_t status = STATUS_SUCCESS;
1423  uint8_t idx;
1424 
1425  static const IRQn_Type ctuFirstFifoIrqNums[CTU_INSTANCE_COUNT] = {
1426  CTU_0_FIFO0_IRQn,
1427  #if CTU_INSTANCE_COUNT > 1u
1428  CTU_1_FIFO0_IRQn
1429  #endif
1430  };
1431 
1432  ADC_ConfigAdcMPC574x(instIdx, config);
1433 
1434  /* Configure CTU */
1435  CTU_DRV_Reset(instIdx);
1436 
1437  uint8_t ctuNumChansList = 0u; /* total number of channels programmed in CTU list */
1438  uint8_t internalTrigIdx = 0u; /* each HW triggered group has associated a single internal trigger and a single result FIFO */
1439  uint8_t fifoIdx = 0u;
1440  uint16_t delay = 0u;
1441  ctu_trig_config_t trigConfig;
1442  ctu_res_fifo_config_t resFifoConfig;
1443  uint32_t inputTriggerSelectMask = 0u;
1444 
1445  /* Configure all HW triggered groups in CTU.
1446  * SW triggered groups will be configured directly in ADC, each time ADC_StartGroupConversion() is called. */
1447  for(idx = 0u; idx < config->numGroups; idx++)
1448  {
1449  currentGroup = &(config->groupConfigArray[idx]);
1450  DEV_ASSERT(currentGroup->inputChannelArray != NULL);
1451 
1452  if(currentGroup->hwTriggerSupport == true)
1453  {
1454  if(internalTrigIdx >= CTU_FR_COUNT) /* Maximum supported number of HW triggers is number of result FIFOs */
1455  {
1456  status = STATUS_ERROR;
1457  return status;
1458  }
1459 
1460  /* The total number of conversions in all HW triggered groups must be <= CTU_CHANNEL_COUNT */
1461  DEV_ASSERT((ctuNumChansList + currentGroup->numChannels) <= CTU_CHANNEL_COUNT);
1462 
1463 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
1464  {
1465  /* Length of result FIFOs are mentioned in the ReferenceManual. */
1466  static const uint8_t resultFifoLengths[CTU_FR_COUNT] = { 16u, 16u, 4u, 4u };
1467 
1468  /* The number of conversions in the current HW triggered group must be <= than
1469  * the length of the assigned result FIFO. */
1470  DEV_ASSERT(currentGroup->numChannels <= resultFifoLengths[internalTrigIdx]);
1471  }
1472 #endif /* defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT) */
1473 
1474  switch(currentGroup->delayType)
1475  {
1477  delay = 0u;
1478  break;
1480  DEV_ASSERT(currentGroup->delayArray != NULL);
1481  delay = currentGroup->delayArray[0u]; /* single delay value per group */
1482  break;
1483  default:
1484  DEV_ASSERT(false); /* Other type not supported */
1485  break;
1486  }
1487 
1488  trigConfig.cmdListStartAdr = ctuNumChansList;
1489  trigConfig.compareVal = delay;
1490  trigConfig.intEn = false;
1491  trigConfig.outputTrigEnMask = CTU_OUTPUT_TRIG_ADC_CMD_EN;
1492  CTU_DRV_ConfigInternalTrigger(instIdx, internalTrigIdx, &trigConfig);
1493 
1494  /* Input trigger select register is common for all internal triggers (i.e. HW triggered groups) */
1495  inputTriggerSelectMask |= currentGroup->triggerSource;
1496 
1497  fifoIdx = internalTrigIdx; /* Each HW triggered group has associated a single internal trigger and a single result FIFO.*/
1498  resFifoConfig.dmaEn = false;
1499  resFifoConfig.fifoIntEnMask = CTU_FIFO_OVERFLOW;
1500  resFifoConfig.fifoThreshold = (currentGroup->numChannels - 1u); /* -1 because OVERFLOW interrupt gets triggered when the number of available results is above this value */
1501  CTU_DRV_ConfigResultFifo(instIdx, fifoIdx, &resFifoConfig);
1502 
1503  IRQn_Type fifoIrqNum;
1504  const uint16_t fifoIrqNumU = ((uint16_t)ctuFirstFifoIrqNums[instIdx] + fifoIdx); /* MISRA workaround */
1505  fifoIrqNum = (IRQn_Type)fifoIrqNumU;
1506  INT_SYS_EnableIRQ(fifoIrqNum);
1507 
1508  /* Config ADC command for each conversion in the group */
1509  uint8_t idx1 = 0u;
1510  uint8_t pos, adcPort;
1511  ctu_adc_cmd_t adcCmd;
1512  adcCmd.convMode = CTU_CONV_MODE_SINGLE;
1513  adcCmd.fifoIdx = fifoIdx;
1514  adcCmd.intEn = false;
1515  adcCmd.selfTestEn = false;
1516 
1517  adcCmd.adcChanA = ADC_GetChanIdx(currentGroup->inputChannelArray[idx1]);
1518  adcPort = ADC_GetAdcAbsoluteIdx(currentGroup->inputChannelArray[idx1]) % FEATURE_CTU_NUM_ADC;
1519  switch(adcPort)
1520  {
1521  case 0u: adcCmd.adcPort = CTU_ADC_PORT_A; break;
1522  case 1u: adcCmd.adcPort = CTU_ADC_PORT_B; break;
1523  default: DEV_ASSERT(false); break;
1524  }
1525 
1526  pos = trigConfig.cmdListStartAdr;
1527  CTU_DRV_ConfigAdcCmdList(instIdx, pos, &adcCmd, 1u); /* Write one command at a time */
1528  for(idx1 = 1u; idx1 < currentGroup->numChannels; idx1++)
1529  {
1530  CTU_Type * const ctuInstBase = ctuBase[instIdx];
1531 
1532  adcCmd.adcChanA = ADC_GetChanIdx(currentGroup->inputChannelArray[idx1]);
1533 
1534  /* For uniformity with SW triggered groups, even if CTU supports the feature,
1535  * do not allow multiple ADC instances in the same conversion group. */
1536  DEV_ASSERT(ADC_GetAdcAbsoluteIdx(currentGroup->inputChannelArray[idx1]) == adcPort);
1537 
1538  pos = (trigConfig.cmdListStartAdr + idx1) % CTU_CHANNEL_COUNT;
1539  CTU_DRV_ConfigAdcCmdList(instIdx, pos, &adcCmd, 1u);
1540 
1541  /* Workaround: clear LC bit starting from second iteration,
1542  * because each CTU_DRV_ConfigAdcCmdList call marks the end of the list. */
1543  ctuInstBase->CHANNEL[pos].CLR_A &= (~CTU_CLR_A_LC_MASK);
1544  }
1545  internalTrigIdx++; /* Move to next trigger index */
1546  ctuNumChansList += currentGroup->numChannels; /* Increment total number of channels programmed into CTU LIST */
1547  }
1548  }
1549 
1550  CTU_DRV_GetDefaultConfig(&ctuCfg);
1551  ctuCfg.prescaler = extension->ctuPrescaler;
1552  ctuCfg.tgsMode = CTU_TGS_MODE_TRIGGERED;
1553  ctuCfg.inputTrigSelectMask = inputTriggerSelectMask;
1554  ctuCfg.tgsCounterCompareVal = CTU_TGSCCR_TGSCCV_MASK; /* set to max */
1555  ctuCfg.tgsCounterReloadVal = 0u; /* set to minimum */
1556 
1557  CTU_DRV_Config(instIdx, &ctuCfg);
1558 
1559  /* Mark that writes to double-buffered configuration registers have ended. */
1560  CTU_DRV_EnableGeneralReload(instIdx);
1561 
1562  /* Sw trigger MRS to load all double-buffered registers and start a new CTU control cycle */
1563  CTU_DRV_SwMasterReloadSignal(instIdx);
1564 
1565 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
1566  {
1567  ADC_CheckChanDuplicate(config);
1568  }
1569 #endif /* defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT) */
1570 
1571  return status;
1572 }
1573 
1574 /*FUNCTION**********************************************************************
1575  *
1576  * Function Name : ADC_MPC574xP_HwTrigIrqHandler
1577  * Description : Implements interrupt handler functionality for HW triggered
1578  * conversion groups - to be called from CTU FIFO interrupt handler.
1579  *
1580  *END**************************************************************************/
1581 void ADC_MPC574xP_HwTrigIrqHandler(const uint32_t instIdx, const uint8_t fifoIdx)
1582 {
1583  adc_pal_state_t * const palState = &(adcPalState[instIdx]);
1584  const adc_group_config_t * activeGroupCfg;
1585  adc_group_state_t * groupState;
1586  uint32_t currentGroupIdx;
1587  ctu_conv_result_t ctuResult;
1588  uint16_t * result;
1589 
1590  DEV_ASSERT(CTU_DRV_GetFifoStatusFlags(instIdx, fifoIdx) != CTU_FIFO_OVERRUN);
1591 
1592  CTU_DRV_GetConvResult(instIdx, fifoIdx, CTU_RESULT_ALIGN_RIGHT_UNSIGNED, &ctuResult);
1593 
1594  groupState = &(palState->hwTrigGroupState[fifoIdx]);
1595 
1596  currentGroupIdx = groupState->groupIdx;
1597 
1598  activeGroupCfg = &(palState->groupArray[currentGroupIdx]);
1599 
1600  result = &(activeGroupCfg->resultBuffer[groupState->currentBufferOffset]);
1601 
1602  *result = ctuResult.convData;
1603 
1604  uint8_t idx;
1605  for(idx = 0u; idx < (activeGroupCfg->numChannels - 1u); idx++)
1606  {
1607  result++;
1608  *result = CTU_DRV_GetConvData(instIdx, fifoIdx, CTU_RESULT_ALIGN_RIGHT_UNSIGNED);
1609  }
1610 
1611  /* Increment offset in result buffer */
1612  groupState->currentBufferOffset = (groupState->currentBufferOffset + activeGroupCfg->numChannels) % groupState->bufferLength;
1613 
1614  /* Call notification callback, if it is enabled */
1615  ADC_CallNotificationCb(palState, currentGroupIdx, groupState);
1616 }
1617 
1618 
1619 #endif /* defined(ADC_PAL_MPC574xP) */
1620 
1621 
1622 
1623 #if (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
1624 
1625 /*FUNCTION**********************************************************************
1626  *
1627  * Function Name : ADC_GetChanIdx
1628  * Description : Returns ADC channel index, demapped from an ADC PAL input channel
1629  *
1630  *END**************************************************************************/
1631 static inline uint8_t ADC_GetChanIdx(const adc_input_chan_t adcPalInputChan)
1632 {
1633  return (uint8_t)(adcPalInputChan & ADC_CHAN_CHAN_IDX_MASK);
1634 }
1635 
1636 
1637 /*FUNCTION**********************************************************************
1638  *
1639  * Function Name : ADC_GetAdcIdx
1640  * Description : Returns ADC absolute index, demapped from an ADC PAL input channel.
1641  * E.g. each BCTU/CTU instance is linked to 2 ADCs => for ADC_3, idx = 3.
1642  *
1643  *END**************************************************************************/
1644 static inline uint8_t ADC_GetAdcAbsoluteIdx(const adc_input_chan_t adcPalInputChan)
1645 {
1646  return (uint8_t)((adcPalInputChan & ADC_CHAN_ADC_IDX_MASK) >> ADC_CHAN_ADC_IDX_OFFSET);
1647 }
1648 
1649 
1650 /*FUNCTION**********************************************************************
1651  *
1652  * Function Name : ADC_GetUsedAdcMask
1653  * Description : Returns a bitmask with each bit (starting from LSB) corresponding to
1654  * an ADC instance. If the corresponding bit is set to "1" the ADC instance is targeted
1655  * by at least one conversion within a group.
1656  *
1657  *END**************************************************************************/
1658 static uint16_t ADC_GetUsedAdcInstances(const uint32_t instance)
1659 {
1660  const adc_pal_state_t * const palState = &(adcPalState[instance]);
1661  const adc_group_config_t * currentGroup;
1662  uint16_t usedAdcMask = 0u;
1663  uint8_t idx;
1664 
1665  for(idx = 0u; idx < palState->numGroups; idx++)
1666  {
1667  currentGroup = &(palState->groupArray[idx]);
1668  /* Assumes that a group contains channels targeting the same ADC index.
1669  * This assumption is checked with DEV_ASSERT in other part of the code. */
1670  usedAdcMask |= ((uint16_t)1u << ADC_GetAdcAbsoluteIdx(currentGroup->inputChannelArray[0u]));
1671  }
1672 
1673  return usedAdcMask;
1674 }
1675 
1676 
1677 /*FUNCTION**********************************************************************
1678  *
1679  * Function Name : ADC_MPC574x_SwTrigIrqHandler
1680  * Description : Implements interrupt handler functionality for SW triggered
1681  * conversion groups - to be called from ADC End of Chain (ECH) interrupt handler.
1682  *
1683  *END**************************************************************************/
1684 void ADC_MPC574x_SwTrigIrqHandler(const uint32_t instIdx, const uint8_t adcIdx)
1685 {
1686  adc_pal_state_t * const palState = &(adcPalState[instIdx]);
1687  adc_group_state_t * const groupState = &(palState->swTrigGroupState);
1688  const uint32_t currentGroupIdx = palState->latestGroupIdx;
1689  const adc_group_config_t * const activeGroupCfg = &(palState->groupArray[currentGroupIdx]);
1690 
1691  uint16_t * result = &(activeGroupCfg->resultBuffer[groupState->currentBufferOffset]);
1692 
1693  DEV_ASSERT(activeGroupCfg->hwTriggerSupport == false); /* This is only used for SW triggered conversion groups */
1694 
1695  /* Read all conversion results for the current conversion group */
1696  uint32_t numResRead = 0u;
1697  (void) numResRead;
1698  numResRead = ADC_DRV_GetConvResultsToArray(adcIdx, ADC_CONV_CHAIN_NORMAL, result, activeGroupCfg->numChannels);
1699  DEV_ASSERT(numResRead == activeGroupCfg->numChannels);
1700 
1701  /* Increment offset in result buffer */
1702  groupState->currentBufferOffset = (uint16_t)((groupState->currentBufferOffset + activeGroupCfg->numChannels) % groupState->bufferLength);
1703 
1704  ADC_DRV_ClearStatusFlags(adcIdx, ADC_FLAG_NORMAL_ENDCHAIN);
1705 
1706  /* Call notification callback, if it is enabled */
1707  ADC_CallNotificationCb(palState, currentGroupIdx, groupState);
1708 
1709  if(activeGroupCfg->continuousConvEn == true) /* Continuous mode currently supported only for SW triggered groups */
1710  {
1711  ADC_DRV_StartConversion(adcIdx, ADC_CONV_CHAIN_NORMAL);
1712  }
1713  else
1714  {
1715 #if defined(ADC_PAL_MPC574xP)
1716  adcBase[adcIdx]->MCR |= ADC_MCR_CTUEN(1u); /* set ADC to CTU CONTROL MODE, to allow HW triggering */
1717 #endif /* defined(ADC_PAL_MPC574xP) */
1718 
1719  groupState->active = false;
1720  }
1721 }
1722 
1723 
1724 /*FUNCTION**********************************************************************
1725  *
1726  * Function Name : ADC_ConfigAdcMPC574x
1727  * Description : Configure ADC instances used by the ADC_PAL for MPC574xC_G_R and MPC574xP
1728  *
1729  *END**************************************************************************/
1730 static void ADC_ConfigAdcMPC574x(const uint32_t instIdx, const adc_config_t * const config)
1731 {
1732 #if defined(ADC_PAL_MPC574xC_G_R)
1733  const extension_adc_mpc574xc_g_r_t * const extension = (extension_adc_mpc574xc_g_r_t *)(config->extension);
1734 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
1735  const uint8_t numAdcPerTrigUnit = FEATURE_BCTU_NUM_ADC;
1736 #endif
1737 #elif defined(ADC_PAL_MPC574xP)
1738  const extension_adc_mpc574xp_t * const extension = (extension_adc_mpc574xp_t *)(config->extension);
1739 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
1740  const uint8_t numAdcPerTrigUnit = FEATURE_CTU_NUM_ADC;
1741 #endif
1742 #endif /* defined(ADC_PAL_MPC574xP) */
1743  adc_conv_config_t adcCfg;
1744  uint16_t idx;
1745 
1746  ADC_DRV_GetDefaultConfigConverter(&adcCfg);
1747  adcCfg.sampleTimeExternal = config->sampleTicks;
1748  adcCfg.sampleTimeInternal = config->sampleTicks;
1749  adcCfg.sampleTimePrecision = config->sampleTicks;
1750  adcCfg.clkSelect = extension->clkSelect;
1751  adcCfg.refSelect = extension->refSelect;
1752  adcCfg.autoClockOff = extension->autoClockOff;
1753  adcCfg.convMode = ADC_CONV_MODE_ONESHOT;
1754 #if defined(ADC_PAL_MPC574xC_G_R)
1755  /* ADC may be triggered from BCTU and also from SW. */
1756  adcCfg.ctuMode = ADC_CTU_MODE_TRIGGER;
1757 #elif defined(ADC_PAL_MPC574xP)
1758  /* ADC may be triggered only from CTU. To allow SW triggered groups, will toggle to CTU control disabled/enabled when starting/stopping a SW triggered conversion. */
1759  adcCfg.ctuMode = ADC_CTU_MODE_CONTROL;
1760 #endif
1761  adcCfg.overwriteEnable = true;
1762 
1763  /* Configure only the ADC instances which are used,
1764  * i.e. which have at least one channel assigned to at least one group. */
1765  uint16_t activeAdcMask = ADC_GetUsedAdcInstances(instIdx);
1766  for(idx = 0u; idx < ADC_INSTANCE_COUNT; idx++)
1767  {
1768  status_t status = STATUS_ERROR;
1769  (void) status;
1770  if((activeAdcMask & ((uint16_t)1u << idx)) != 0u)
1771  {
1772  /* Check that the selected ADC is connected to the selected triggering unit.
1773  * Triggering unit index is mapped 1:1 with adc_pal instance index */
1774  DEV_ASSERT(idx >= (instIdx * numAdcPerTrigUnit));
1775  DEV_ASSERT(idx < ((instIdx + 1u) * numAdcPerTrigUnit));
1776 
1777  ADC_DRV_Reset(idx);
1778  status = ADC_DRV_DoCalibration(idx);
1779  DEV_ASSERT(status == STATUS_SUCCESS);
1780 
1781  ADC_DRV_ConfigConverter(idx, &adcCfg);
1782 
1783  /* Used for SW triggered groups */
1784  ADC_DRV_EnableInterrupts(idx, ADC_FLAG_NORMAL_ENDCHAIN);
1785  }
1786  }
1787 }
1788 
1789 
1790 /*FUNCTION**********************************************************************
1791  *
1792  * Function Name : ADC_ResetAdcInstances
1793  * Description : Reset active ADC instances used by the ADC_PAL for MPC574xC_G_R and MPC574xP
1794  *
1795  *END**************************************************************************/
1796 static void ADC_ResetAdcMPC574x(const uint32_t instIdx)
1797 {
1798 #if defined(ADC_PAL_MPC574xC_G_R)
1799  const uint8_t numAdcPerTrigUnit = FEATURE_BCTU_NUM_ADC;
1800 #elif defined(ADC_PAL_MPC574xP)
1801  const uint8_t numAdcPerTrigUnit = FEATURE_CTU_NUM_ADC;
1802 #endif
1803 
1804  uint16_t idx;
1805 
1806  /* Deinit only the ADC instances which correspond to the current ADC PAL instance,
1807  * and are active, i.e. have at least one channel assigned to at least one group. */
1808  uint16_t activeAdcMask = ADC_GetUsedAdcInstances(instIdx);
1809  const uint16_t startIdx = instIdx * numAdcPerTrigUnit;
1810  const uint16_t endIdx = (instIdx + 1u) * numAdcPerTrigUnit;
1811  for(idx = startIdx; idx < endIdx; idx++)
1812  {
1813  if((activeAdcMask & ((uint16_t)1u << idx)) != 0u)
1814  {
1815  ADC_DRV_Reset(idx);
1816  }
1817  }
1818 }
1819 
1820 
1821 #if defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT)
1822 /*FUNCTION**********************************************************************
1823  *
1824  * Function Name : ADC_CheckChanDuplicate
1825  * Description : Check that a channel doesn't appear multiple times within a group
1826  * for MPC574xC_G_R: check for SW and HW triggered groups
1827  * for MPC574xP: check only for SW triggered groups. HW triggered groups may contain
1828  * the same channel multiple times, because results are stored in CTU result FIFOs.
1829  *
1830  *END**************************************************************************/
1831 static void ADC_CheckChanDuplicate(const adc_config_t * const config)
1832 {
1833  uint8_t numOccurrences[ADC_CDR_COUNT] = {0}; /* total number of ADC channels is given by ADC_CDR_COUNT */
1834  uint8_t idx1, idx;
1835  uint8_t chanIdx;
1836  const adc_group_config_t * currentGroup;
1837 
1838  for(idx = 0u; idx < config->numGroups; idx++)
1839  {
1840  currentGroup = &(config->groupConfigArray[idx]);
1841 
1842 #if defined(ADC_PAL_MPC574xP)
1843  if(currentGroup->hwTriggerSupport == true)
1844  {
1845  continue;
1846  }
1847 #endif /* defined(ADC_PAL_MPC574xP) */
1848 
1849  /* First reset the number of occurrences of each channel */
1850  for(idx1 = 0u; idx1 < currentGroup->numChannels; idx1++)
1851  {
1852  chanIdx = ADC_GetChanIdx(currentGroup->inputChannelArray[idx1]);
1853  numOccurrences[chanIdx] = 0u;
1854  }
1855  /* Count the number of occurrences for each channel */
1856  for(idx1 = 0u; idx1 < currentGroup->numChannels; idx1++)
1857  {
1858  chanIdx = ADC_GetChanIdx(currentGroup->inputChannelArray[idx1]);
1859  numOccurrences[chanIdx]++;
1860  }
1861  for(idx1 = 0u; idx1 < currentGroup->numChannels; idx1++)
1862  {
1863  chanIdx = ADC_GetChanIdx(currentGroup->inputChannelArray[idx1]);
1864  if(numOccurrences[chanIdx] > 1u)
1865  {
1866  DEV_ASSERT(false); /* A channel must not appear multiple times inside a SW triggered group */
1867  }
1868  }
1869  }
1870 }
1871 #endif /* defined (CUSTOM_DEVASSERT) || defined (DEV_ERROR_DETECT) */
1872 
1873 #endif /* (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
1874 
1875 
1876 
1877 #if (defined(ADC_PAL_S32K1xx) || defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
1878 
1879 
1880 
1881 /*FUNCTION**********************************************************************
1882  *
1883  * Function Name : ADC_GetHwGroupStatePtr
1884  * Description : Returns pointer to the HW triggered state structure.
1885  * Mapping of groupIndex to index of the HW triggered state is platform specific.
1886  *
1887  *END**************************************************************************/
1888 static inline adc_group_state_t * ADC_GetHwGroupStatePtr(const uint32_t instIdx, const uint32_t groupIdx)
1889 {
1890 #if defined(ADC_PAL_S32K1xx)
1891 
1892  (void) groupIdx;
1893  return &(adcPalState[instIdx].hwTrigGroupState[0u]); /* S32K1xx supports only a single active group at a time, so any active groupIdx will be mapped to state idx 0 */
1894 
1895 #elif (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
1896 
1897  adc_pal_state_t * const palState = &(adcPalState[instIdx]);
1898  const uint32_t stateIdx = palState->stateIdxMapping[groupIdx];
1899  return &(palState->hwTrigGroupState[stateIdx]);
1900 
1901 #endif /* (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
1902 }
1903 
1904 
1905 
1906 /*FUNCTION**********************************************************************
1907  *
1908  * Function Name : ADC_AnyHwTrigGroupActive
1909  * Description : Returns true if at least one hwTriggered group is enabled.
1910  * Otherwise returns false.
1911  *
1912  *END**************************************************************************/
1913 static bool ADC_AnyHwTrigGroupActive(const uint32_t instIdx)
1914 {
1915 #if defined(ADC_PAL_S32K1xx)
1916 
1917  return adcPalState[instIdx].hwTrigGroupState[0u].active; /* S32K1xx supports only a single active group at a time, so any active groupIdx will be mapped to state idx 0 */
1918 
1919 #elif (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP))
1920 
1921  bool active = false;
1922  uint8_t idx = 0u;
1923 
1924  while((active == false) && (idx < ADC_PAL_MAX_NUM_HW_GROUPS_EN))
1925  {
1926  if(adcPalState[instIdx].hwTrigGroupState[idx].active == true)
1927  {
1928  active = true;
1929  }
1930  idx++;
1931  }
1932  return active;
1933 
1934 #endif /* (defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
1935 }
1936 
1937 /*FUNCTION**********************************************************************
1938  *
1939  * Function Name : ADC_PalStateUpdateStart
1940  * Description : Update PAL state structure with changes for StartGroupConversion and
1941  * EnableHardwareTigger.
1942  *
1943  *END**************************************************************************/
1944 static void ADC_PalStateUpdateStart(const uint32_t instIdx, const uint32_t groupIdx)
1945 {
1946  adc_pal_state_t * palState = &(adcPalState[instIdx]);
1947  const adc_group_config_t * const currentGroupCfg = &(palState->groupArray[groupIdx]);
1948  adc_group_state_t * groupState;
1949 
1950  if(currentGroupCfg->hwTriggerSupport == true)
1951  {
1952  groupState = ADC_GetHwGroupStatePtr(instIdx, groupIdx);
1953  }
1954  else
1955  {
1956  groupState = &(palState->swTrigGroupState);
1957  }
1958 
1959  palState->latestGroupIdx = groupIdx;
1960  groupState->active = true;
1961  groupState->currentBufferOffset = 0u;
1962 #if defined(ADC_PAL_MPC574xP)
1963  groupState->groupIdx = groupIdx;
1964 #endif
1965  groupState->bufferLength = (uint16_t)currentGroupCfg->numChannels * currentGroupCfg->numSetsResultBuffer;
1966  if(currentGroupCfg->callback != NULL)
1967  {
1968  groupState->notificationEn = true; /* enable notification by default if callback is available */
1969  }
1970  else
1971  {
1972  groupState->notificationEn = false; /* disable notification if callback is not available */
1973  }
1974 }
1975 
1976 
1977 /*FUNCTION**********************************************************************
1978  *
1979  * Function Name : ADC_CallNotificationCb
1980  * Description : Calls the notification callback for the current active group,
1981  * if it is enabled.
1982  *
1983  *END**************************************************************************/
1984 static void ADC_CallNotificationCb(const adc_pal_state_t * const palState, const uint32_t groupIdx, const adc_group_state_t * const groupState)
1985 {
1986  const adc_group_config_t * const activeGroupCfg = &(palState->groupArray[groupIdx]);
1987 
1988  /* Call notification callback, if it is enabled */
1989  if(groupState->notificationEn)
1990  {
1991  adc_callback_info_t cbInfo;
1992  cbInfo.groupIndex = groupIdx;
1993 
1994  if(groupState->currentBufferOffset == 0u)
1995  {
1996  cbInfo.resultBufferTail = (uint16_t)(groupState->bufferLength - 1u); /* set tail to the last position in buffer */
1997  }
1998  else
1999  {
2000  cbInfo.resultBufferTail = (uint16_t)(groupState->currentBufferOffset - 1u); /* set tail to last written position */
2001  }
2002 
2003  (*(activeGroupCfg->callback))(&cbInfo, activeGroupCfg->callbackUserData);
2004  }
2005 }
2006 
2007 #endif /* (defined(ADC_PAL_S32K1xx) || defined(ADC_PAL_MPC574xC_G_R) || defined(ADC_PAL_MPC574xP)) */
2008 
2009 /*******************************************************************************
2010  * EOF
2011  ******************************************************************************/
void PDB_DRV_SetAdcPreTriggerDelayValue(const uint32_t instance, const uint32_t chn, const uint32_t preChn, const uint32_t value)
Sets the ADC pre_trigger delay value in the PDB module.
Definition: pdb_driver.c:389
static ADC_Type *const s_adcBase[ADC_INSTANCE_COUNT]
Definition: adc_driver.c:53
void * extension
Definition: adc_pal.h:161
status_t ADC_StopGroupConversion(const adc_instance_t *const instance, const uint32_t groupIdx, const uint32_t timeout)
Stops the selected SW triggered ADC conversion group execution.
Definition: adc_pal.c:686
const adc_group_config_t * groupConfigArray
Definition: adc_pal.h:157
void ADC_DRV_AutoCalibration(const uint32_t instance)
Executes an Auto-Calibration.
Definition: adc_driver.c:548
status_t TRGMUX_DRV_SetTrigSourceForTargetModule(const uint32_t instance, const trgmux_trigger_source_t triggerSource, const trgmux_target_module_t targetModule)
Configure a source trigger for a selected target module.
pdb_trigger_src_t
Defines the type of trigger source mode for the PDB.
Definition: pdb_driver.h:80
void OSIF_TimeDelay(const uint32_t delay)
Delays execution for a number of milliseconds.
adc_voltage_reference_t voltageRef
Definition: adc_driver.h:262
status_t ADC_DisableNotification(const adc_instance_t *const instance, const uint32_t groupIdx)
Disables the notification callback for a configured group.
Definition: adc_pal.c:835
void PDB_DRV_ConfigAdcPreTrigger(const uint32_t instance, const uint32_t chn, const pdb_adc_pretrigger_config_t *configPtr)
Configures the ADC pre_trigger in the PDB module.
Definition: pdb_driver.c:296
void ADC_DRV_ConfigConverter(const uint32_t instance, const adc_converter_config_t *const config)
Configures the converter with the given configuration structure.
Definition: adc_driver.c:91
adc_callback_t callback
Definition: adc_pal.h:145
adc_input_clock_t inputClock
Definition: adc_driver.h:257
void ADC_DRV_Reset(const uint32_t instance)
Resets the converter (sets all configurations to reset values)
Definition: adc_driver.c:175
uint32_t OSIF_GetMilliseconds(void)
Returns the number of miliseconds elapsed since starting the internal timer or starting the scheduler...
adc_clk_divide_t clockDivide
Definition: adc_driver.h:254
void ADC_DRV_GetChanResult(const uint32_t instance, const uint8_t chanIndex, uint16_t *const result)
Gets the last result for the selected control channel.
Definition: adc_driver.c:510
Defines the configuration structure for ADC PAL.
Definition: adc_pal.h:155
const adc_input_chan_t * inputChannelArray
Definition: adc_pal.h:131
Defines the type of structure for basic timer in PDB.
Definition: pdb_driver.h:106
adc_trigger_t trigger
Definition: adc_driver.h:258
void ADC_DRV_ConfigChan(const uint32_t instance, const uint8_t chanIndex, const adc_chan_config_t *const config)
Configures the selected control channel with the given configuration structure.
Definition: adc_driver.c:378
adc_trigger_source_t triggerSource
Definition: adc_pal.h:138
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
bool continuousConvEn
Definition: adc_pal.h:143
#define DEV_ASSERT(x)
Definition: devassert.h:77
Defines the configuration structure for an ADC PAL conversion group.
Definition: adc_pal.h:129
adc_delay_type_t delayType
Definition: adc_pal.h:140
status_t ADC_StartGroupConversion(const adc_instance_t *const instance, const uint32_t groupIdx)
Starts the execution of a selected SW triggered ADC conversion group.
Definition: adc_pal.c:607
bool hwTriggerSupport
Definition: adc_pal.h:137
status_t ADC_EnableHardwareTrigger(const adc_instance_t *const instance, const uint32_t groupIdx)
Enables the selected HW trigger for a conversion group, if the conversion group has support for HW tr...
Definition: adc_pal.c:408
status_t ADC_Deinit(const adc_instance_t *const instance)
Deinitializes the ADC PAL instance.
Definition: adc_pal.c:310
void ADC_DRV_InitConverterStruct(adc_converter_config_t *const config)
Initializes the converter configuration structure.
Definition: adc_driver.c:66
static adc_pal_state_t adcPalState[NUMBER_OF_ADC_PAL_INSTANCES]
Definition: adc_pal.c:213
pdb_clk_prescaler_mult_factor_t clkPreMultFactor
Definition: pdb_driver.h:111
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K118.h:188
pdb_load_value_mode_t loadValueMode
Definition: pdb_driver.h:108
void PDB_DRV_SoftTriggerCmd(const uint32_t instance)
Triggers the PDB with a software trigger.
Definition: pdb_driver.c:188
void PDB_DRV_LoadValuesCmd(const uint32_t instance)
Executes the command of loading values.
Definition: pdb_driver.c:249
IRQn_Type ADC_DRV_GetInterruptNumber(const uint32_t instance)
Returns the interrupt number for the ADC instance.
Definition: adc_driver.c:685
uint32_t groupIndex
Definition: callbacks.h:114
void PDB_DRV_Deinit(const uint32_t instance)
De-initializes the PDB module.
Definition: pdb_driver.c:111
uint16_t * resultBuffer
Definition: adc_pal.h:133
uint8_t sampleTicks
Definition: adc_pal.h:160
Defines the converter configuration.
Definition: adc_driver.h:252
void * callbackUserData
Definition: adc_pal.h:146
pdb_clk_prescaler_div_t clkPreDiv
Definition: pdb_driver.h:110
#define ADC_INSTANCE_COUNT
Definition: S32K118.h:299
uint16_t numGroups
Definition: adc_pal.h:158
pdb_trigger_src_t triggerInput
Definition: pdb_driver.h:112
uint16_t * delayArray
Definition: adc_pal.h:141
#define ADC_BASE_PTRS
Definition: S32K118.h:310
void PDB_DRV_Enable(const uint32_t instance)
Enables the PDB module.
Definition: pdb_driver.c:156
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
status_t ADC_Init(const adc_instance_t *const instance, const adc_config_t *const config)
Initializes the ADC PAL instance.
Definition: adc_pal.c:228
status_t ADC_EnableNotification(const adc_instance_t *const instance, const uint32_t groupIdx)
Enables the notification callback for a configured group.
Definition: adc_pal.c:786
uint8_t numSetsResultBuffer
Definition: adc_pal.h:135
void PDB_DRV_Init(const uint32_t instance, const pdb_timer_config_t *userConfigPtr)
Initializes the PDB counter and triggers input.
Definition: pdb_driver.c:63
pdb_clk_prescaler_div_t
Defines the type of prescaler divider for the PDB counter clock. Implements : pdb_clk_prescaler_div_t...
Definition: pdb_driver.h:61
Defines the type of structure for configuring ADC's pre_trigger.
Definition: pdb_driver.h:123
enum trgmux_target_module_e trgmux_target_module_t
Enumeration for target module of TRGMUX.
Definition: trgmux_driver.h:81
#define NUMBER_OF_ALT_CLOCKS
uint16_t resultBufferTail
Definition: callbacks.h:115
uint8_t numChannels
Definition: adc_pal.h:134
status_t ADC_DisableHardwareTrigger(const adc_instance_t *const instance, const uint32_t groupIdx, const uint32_t timeout)
Disables the selected HW trigger for a conversion group, if the conversion group is HW triggered...
Definition: adc_pal.c:500
Structure storing PAL instance information.
adc_resolution_t resolution
Definition: adc_driver.h:256
adc_pretrigger_sel_t pretriggerSel
Definition: adc_driver.h:259
adc_inputchannel_t channel
Definition: adc_driver.h:309
Defines the control channel configuration.
Definition: adc_driver.h:306