Interrupt vector numbers for S32K118

Detailed Description

This module covers interrupt number allocation.

Macros

#define NUMBER_OF_INT_VECTORS   48u
 

Enumerations

enum  IRQn_Type {
  NotAvail_IRQn = -128, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5,
  PendSV_IRQn = -2, SysTick_IRQn = -1, DMA0_IRQn = 0u, DMA1_IRQn = 1u,
  DMA2_IRQn = 2u, DMA3_IRQn = 3u, DMA_Error_IRQn = 4u, ERM_fault_IRQn = 5u,
  RTC_IRQn = 6u, RTC_Seconds_IRQn = 7u, LPTMR0_IRQn = 8u, PORT_IRQn = 9u,
  CAN0_ORed_Err_Wakeup_IRQn = 10u, CAN0_ORed_0_31_MB_IRQn = 11u, FTM0_Ch0_7_IRQn = 12u, FTM0_Fault_IRQn = 13u,
  FTM0_Ovf_Reload_IRQn = 14u, FTM1_Ch0_7_IRQn = 15u, FTM1_Fault_IRQn = 16u, FTM1_Ovf_Reload_IRQn = 17u,
  FTFC_IRQn = 18u, PDB0_IRQn = 19u, LPIT0_IRQn = 20u, SCG_CMU_LVD_LVWSCG_IRQn = 21u,
  WDOG_IRQn = 22u, RCM_IRQn = 23u, LPI2C0_Master_Slave_IRQn = 24u, FLEXIO_IRQn = 25u,
  LPSPI0_IRQn = 26u, LPSPI1_IRQn = 27u, ADC0_IRQn = 28u, CMP0_IRQn = 29u,
  LPUART1_RxTx_IRQn = 30u, LPUART0_RxTx_IRQn = 31u
}
 Defines the Interrupt Numbers definitions. More...
 

Macro Definition Documentation

#define NUMBER_OF_INT_VECTORS   48u

Interrupt Number Definitions Number of interrupts in the Vector table

Definition at line 179 of file S32K118.h.

Enumeration Type Documentation

enum IRQn_Type

Defines the Interrupt Numbers definitions.

This enumeration is used to configure the interrupts.

Implements : IRQn_Type_Class

Enumerator
NotAvail_IRQn 

Not available device specific interrupt

NonMaskableInt_IRQn 

Non Maskable Interrupt

HardFault_IRQn 

Cortex-M0 SV Hard Fault Interrupt

SVCall_IRQn 

Cortex-M0 SV Call Interrupt

PendSV_IRQn 

Cortex-M0 Pend SV Interrupt

SysTick_IRQn 

Cortex-M0 System Tick Interrupt

DMA0_IRQn 

DMA channel 0 transfer complete

DMA1_IRQn 

DMA channel 1 transfer complete

DMA2_IRQn 

DMA channel 2 transfer complete

DMA3_IRQn 

DMA channel 3 transfer complete

DMA_Error_IRQn 

DMA error interrupt channels 0-3

ERM_fault_IRQn 

ERM single and double bit error correction

RTC_IRQn 

RTC alarm interrupt

RTC_Seconds_IRQn 

RTC seconds interrupt

LPTMR0_IRQn 

LPTIMER interrupt request

PORT_IRQn 

Port A, B, C, D and E pin detect interrupt

CAN0_ORed_Err_Wakeup_IRQn 

OR’ed [Bus Off OR Bus Off Done OR Transmit Warning OR Receive Warning], Interrupt indicating that errors were detected on the CAN bus, Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode

CAN0_ORed_0_31_MB_IRQn 

OR'ed Message buffer (0-15, 16-31)

FTM0_Ch0_7_IRQn 

FTM0 Channel 0 to 7 interrupt

FTM0_Fault_IRQn 

FTM0 Fault interrupt

FTM0_Ovf_Reload_IRQn 

FTM0 Counter overflow and Reload interrupt

FTM1_Ch0_7_IRQn 

FTM1 Channel 0 to 7 interrupt

FTM1_Fault_IRQn 

FTM1 Fault interrupt

FTM1_Ovf_Reload_IRQn 

FTM1 Counter overflow and Reload interrupt

FTFC_IRQn 

FTFC Command complete, Read collision and Double bit fault detect

PDB0_IRQn 

PDB0 interrupt

LPIT0_IRQn 

LPIT interrupt

SCG_CMU_LVD_LVWSCG_IRQn 

PMC Low voltage detect interrupt, SCG bus interrupt request and CMU loss of range interrupt

WDOG_IRQn 

WDOG interrupt request out before wdg reset out

RCM_IRQn 

RCM Asynchronous Interrupt

LPI2C0_Master_Slave_IRQn 

LPI2C0 Master Interrupt and Slave Interrupt

FLEXIO_IRQn 

FlexIO Interrupt

LPSPI0_IRQn 

LPSPI0 Interrupt

LPSPI1_IRQn 

LPSPI1 Interrupt

ADC0_IRQn 

ADC0 interrupt request.

CMP0_IRQn 

CMP0 interrupt request

LPUART1_RxTx_IRQn 

LPUART1 Transmit / Receive Interrupt

LPUART0_RxTx_IRQn 

LPUART0 Transmit / Receive Interrupt

Definition at line 188 of file S32K118.h.