Watchdog Peripheral Abstraction Layer (WDG PAL)

Detailed Description

The S32 SDK provides a Peripheral Abstraction Layer for Watchdog (WDG PAL) modules of S32 SDK devices.

The Watchdog PAL driver allows to generate interrupt event to reset CPU or external circuit. It was designed to be portable across all platforms and IPs which support Watchdog Timer.

How to integrate WDG PAL in your application

Unlike the other drivers, WDG PAL modules need to include a configuration file named wdg_pal_cfg.h, which allows the user to specify which IPSs are used and how many resources are allocated for each of them (state structures). The following code example shows how to configure one instance for each available WDG IPs.

#ifndef WDG_PAL_CFG_H
#define WDG_PAL_CFG_H
/* Define which IP instance will be used in current project */
#define WDG_OVER_WDOG
#define WDG_OVER_EWM
#define WDG_OVER_SWT
/* Define the resources necessary for current project */
#define WDG_OVER_WDOG_INSTANCE_COUNT 1U
#define WDG_OVER_EWM_INSTANCE_COUNT 1U
#define WDG_OVER_SWT_INSTANCE_COUNT 1U
#endif /* WDG_PAL_CFG_H */

The following table contains the matching between platforms and available IPs

IP/MCU S32K11xS32K14xS32MTVMPC574x
WDOG YES YES YES NO
EWM NO YES YES NO
SWT NO NO NO YES

Functionality

Initialization

In order to use the WDG PAL driver it must be first initialized, using WDG_Init() function. Once initialized, it cannot be initialized again for the same WDG module instance until it is de-initialized, using WDG_Deinit(). Different WDG modules instances can function independently of each other.

Interrupt event

After initialization, WDG PAL counter will count to timeout value. In window mode, when WDG PAL counter is refreshed, it will reset count to default value and count again. If WDG PAL counter count to timeout value, CPU or the external circuit will be reseted or placed into safe mode.

The configuration structure includes a special field named extension. It will be used only for WDG PAL over EWM peripheral and should contain a pointer to extension_ewm_for_wdg_t structure. The purpose of this structure is to configure which EWM_OUT pins and clock prescaler are used by the applications.

WDG PAL internal counter

WDG PAL internal counter is

WDG PAL's counter over EWM and WDOG will start to count from 0 to timeout value. WDG PAL's counter over SWT will start to count from timeout value to 0.

Important Notes

Example code

const wdg_instance_t wdg_pal1_Instance =
{
.instIdx = 0U
};
const wdg_instance_t wdg_pal2_Instance =
{
.instType = WDG_INST_TYPE_EWM,
.instIdx = 0U
};
const wdg_instance_t wdg_pal3_Instance =
{
.instType = WDG_INST_TYPE_SWT,
.instIdx = 0U
};
/* Serial User Configurations */
const wdg_config_t wdg_pal1_Config0 =
{
.opMode =
{
.wait = false,
.stop = false,
.debug = false
},
.timeoutValue = 1024,
.percentWindow = 50,
.intEnable = true,
.winEnable = true,
.prescalerEnable = true
};
const wdg_config_t wdg_pal2_Config0 =
{
.opMode =
{
.wait = false,
.stop = false,
.debug = false
},
.timeoutValue = 254,
.percentWindow = 100,
.intEnable = true,
.winEnable = true,
.prescalerEnable = true,
.extension = &wdg_pal2_Extension0
};
extension_ewm_for_wdg_t wdg_pal2_Extension0 =
{
.assertLogic = WDG_IN_ASSERT_ON_LOGIC_ZERO,
.prescalerValue = 251
};
const wdg_config_t wdg_pal3_Config0 =
{
.opMode =
{
.wait = false,
.stop = false,
.debug = false
},
.timeoutValue = 2560,
.percentWindow = 50,
.intEnable = true,
.winEnable = true,
.prescalerEnable = false
};
int main()
{
/* Init clocks, pins, led and other modules */
...
/* Initialize WDG PAL */
WDG_Init(&wdg_pal1_Instance, &wdg_pal1_Config0);
/* Infinite loop*/
while(1)
{
/* Do something until the counter needs to be refreshed */
...
/* Reset WDG PAL counter */
WDG_Refresh(&wdg_pal1_Instance);
}
}

Modules

 WDG PAL
 Watchdog Peripheral Abstraction Layer.