clock_S32K1xx.c
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1 /*
2  * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2018 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
51 #include "device_registers.h"
52 #include "sim_hw_access.h"
53 #include "scg_hw_access.h"
54 #include "pcc_hw_access.h"
55 #include "pmc_hw_access.h"
56 #include "smc_hw_access.h"
57 #include "clock_manager.h"
58 #include <stddef.h> /* This header is included for bool type */
59 /*
60  * README:
61  * This file provides these APIs:
62  * 1. APIs to get the frequency of output clocks in Reference Manual ->
63  * Chapter Clock Distribution -> Figure Clocking diagram.
64  * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
65  * -> Module clocks.
66  */
67 
68 /*******************************************************************************
69  * Definitions
70  ******************************************************************************/
71 /* This frequency values should be set by different boards. */
72 /* SIM */
73 uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]; /* TCLKx clocks */
74 
75 /* RTC */
76 uint32_t g_RtcClkInFreq; /* RTC CLKIN clock */
77 
78 /* SCG */
79 uint32_t g_xtal0ClkFreq; /* EXTAL0 clock */
80 
81 
82 #if FEATURE_HAS_SPLL_CLK
83 /* @brief System PLL base multiplier value, it is the multiplier value when SCG_SPLLCFG[MULT]=0. */
84 #define SCG_SPLL_MULT_BASE 16U
85 
86 /*
87  * @brief System PLL base divider value, it is the PLL reference clock divider value when
88  * SCG_SPLLCFG[PREDIV]=0.
89  */
90 #define SCG_SPLL_PREDIV_BASE 1U
91 
92 /*
93  * @brief System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the range of
94  * SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX.
95  */
96 #define SCG_SPLL_REF_MIN 8000000U
97 
98 /*
99  * @brief System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the range of
100  * SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX.
101  */
102 #define SCG_SPLL_REF_MAX 32000000U
103 #endif
104 
105 /*
106  * @brief LPO 128K fixed clock frequency.
107  */
108 #define LPO_128K_FREQUENCY 128000UL
109 
110 /*
111  * @brief LPO 32K fixed clock frequency.
112  */
113 #define LPO_32K_FREQUENCY 32000UL
114 
115 /*
116  * @brief LPO 1K fixed clock frequency.
117  */
118 #define LPO_1K_FREQUENCY 1000UL
119 
120 /*
121  * @brief Running modes.
122  */
123 #define HIGH_SPEED_RUNNING_MODE (1UL << 7U)
124 #define RUN_SPEED_RUNNING_MODE (1UL << 0U)
125 #define VLPR_SPEED_RUNNING_MODE (1UL << 2U)
126 
127 
128 #define MODES_MAX_NO 7U
129 #define CLOCK_MAX_FREQUENCIES_VLPR_MODE \
130 {/* SYS_CLK BUS_CLK SLOW_CLK */ \
131 { 0UL, 0UL, 0UL}, \
132 { 4000000UL, 4000000UL, 1000000UL}, \
133 { 4000000UL, 4000000UL, 1000000UL}, \
134 { 4000000UL, 4000000UL, 1000000UL}, \
135 { 0UL, 0UL, 0UL}, \
136 { 0UL, 0UL, 0UL}, \
137 { 4000000UL, 4000000UL, 1000000UL}, \
138 }
139 #define CLOCK_MAX_FREQUENCIES_RUN_MODE \
140 {/* SYS_CLK BUS_CLK SLOW_CLK */ \
141 { 0UL, 0UL, 0UL}, \
142 {80000000UL, 48000000UL, 26670000UL}, \
143 {80000000UL, 48000000UL, 26670000UL}, \
144 {80000000UL, 48000000UL, 26670000UL}, \
145 { 0UL, 0UL, 0UL}, \
146 { 0UL, 0UL, 0UL}, \
147 {80000000UL, 40000000UL, 26670000UL}, \
148 }
149 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
150 #define CLOCK_MAX_FREQUENCIES_HSRUN_MODE \
151 {/* SYS_CLK BUS_CLK SLOW_CLK */ \
152 { 0UL, 0UL, 0UL}, \
153 {112000000UL, 56000000UL, 28000000UL}, \
154 {112000000UL, 56000000UL, 28000000UL}, \
155 {112000000UL, 56000000UL, 28000000UL}, \
156 { 0UL, 0UL, 0UL}, \
157 { 0UL, 0UL, 0UL}, \
158 {112000000UL, 56000000UL, 28000000UL}, \
159 }
160 #endif
161 
162 /*
163  * @brief Number of peripheral clocks.
164  */
165 #if defined(PCC_FTFC_INDEX)
166  #define TMP_FTFC 1U
167 #else
168  #define TMP_FTFC 0U
169 #endif
170 #if defined(PCC_DMAMUX_INDEX)
171  #define TMP_DMAMUX 1U
172 #else
173  #define TMP_DMAMUX 0U
174 #endif
175 #if defined(PCC_FlexCAN0_INDEX)
176  #define TMP_FlexCAN0 1U
177 #else
178  #define TMP_FlexCAN0 0U
179 #endif
180 #if defined(PCC_FlexCAN1_INDEX)
181  #define TMP_FlexCAN1 1U
182 #else
183  #define TMP_FlexCAN1 0U
184 #endif
185 #if defined(PCC_FTM3_INDEX)
186  #define TMP_FTM3 1U
187 #else
188  #define TMP_FTM3 0U
189 #endif
190 #if defined(PCC_ADC1_INDEX)
191  #define TMP_ADC1 1U
192 #else
193  #define TMP_ADC1 0U
194 #endif
195 #if defined(PCC_FlexCAN2_INDEX)
196  #define TMP_FlexCAN2 1U
197 #else
198  #define TMP_FlexCAN2 0U
199 #endif
200 #if defined(PCC_LPSPI0_INDEX)
201  #define TMP_LPSPI0 1U
202 #else
203  #define TMP_LPSPI0 0U
204 #endif
205 #if defined(PCC_LPSPI1_INDEX)
206  #define TMP_LPSPI1 1U
207 #else
208  #define TMP_LPSPI1 0U
209 #endif
210 #if defined(PCC_LPSPI2_INDEX)
211  #define TMP_LPSPI2 1U
212 #else
213  #define TMP_LPSPI2 0U
214 #endif
215 #if defined(PCC_PDB1_INDEX)
216  #define TMP_PDB1 1U
217 #else
218  #define TMP_PDB1 0U
219 #endif
220 #if defined(PCC_CRC_INDEX)
221  #define TMP_CRC 1U
222 #else
223  #define TMP_CRC 0U
224 #endif
225 #if defined(PCC_PDB0_INDEX)
226  #define TMP_PDB0 1U
227 #else
228  #define TMP_PDB0 0U
229 #endif
230 #if defined(PCC_LPIT_INDEX)
231  #define TMP_LPIT 1U
232 #else
233  #define TMP_LPIT 0U
234 #endif
235 #if defined(PCC_FTM0_INDEX)
236  #define TMP_FTM0 1U
237 #else
238  #define TMP_FTM0 0U
239 #endif
240 #if defined(PCC_FTM1_INDEX)
241  #define TMP_FTM1 1U
242 #else
243  #define TMP_FTM1 0U
244 #endif
245 #if defined(PCC_FTM2_INDEX)
246  #define TMP_FTM2 1U
247 #else
248  #define TMP_FTM2 0U
249 #endif
250 #if defined(PCC_ADC0_INDEX)
251  #define TMP_ADC0 1U
252 #else
253  #define TMP_ADC0 0U
254 #endif
255 #if defined(PCC_RTC_INDEX)
256  #define TMP_RTC 1U
257 #else
258  #define TMP_RTC 0U
259 #endif
260 #if defined(PCC_LPTMR0_INDEX)
261  #define TMP_LPTMR0 1U
262 #else
263  #define TMP_LPTMR0 0U
264 #endif
265 #if defined(PCC_PORTA_INDEX)
266  #define TMP_PORTA 1U
267 #else
268  #define TMP_PORTA 0U
269 #endif
270 #if defined(PCC_PORTB_INDEX)
271  #define TMP_PORTB 1U
272 #else
273  #define TMP_PORTB 0U
274 #endif
275 #if defined(PCC_PORTC_INDEX)
276  #define TMP_PORTC 1U
277 #else
278  #define TMP_PORTC 0U
279 #endif
280 #if defined(PCC_PORTD_INDEX)
281  #define TMP_PORTD 1U
282 #else
283  #define TMP_PORTD 0U
284 #endif
285 #if defined(PCC_PORTE_INDEX)
286  #define TMP_PORTE 1U
287 #else
288  #define TMP_PORTE 0U
289 #endif
290 #if defined(PCC_SAI0_INDEX)
291  #define TMP_SAI0 1U
292 #else
293  #define TMP_SAI0 0U
294 #endif
295 #if defined(PCC_SAI1_INDEX)
296  #define TMP_SAI1 1U
297 #else
298  #define TMP_SAI1 0U
299 #endif
300 #if defined(PCC_FlexIO_INDEX)
301  #define TMP_FlexIO 1U
302 #else
303  #define TMP_FlexIO 0U
304 #endif
305 #if defined(PCC_EWM_INDEX)
306  #define TMP_EWM 1U
307 #else
308  #define TMP_EWM 0U
309 #endif
310 #if defined(PCC_LPI2C0_INDEX)
311  #define TMP_LPI2C0 1U
312 #else
313  #define TMP_LPI2C0 0U
314 #endif
315 #if defined(PCC_LPI2C1_INDEX)
316  #define TMP_LPI2C1 1U
317 #else
318  #define TMP_LPI2C1 0U
319 #endif
320 #if defined(PCC_LPUART0_INDEX)
321  #define TMP_LPUART0 1U
322 #else
323  #define TMP_LPUART0 0U
324 #endif
325 #if defined(PCC_LPUART1_INDEX)
326  #define TMP_LPUART1 1U
327 #else
328  #define TMP_LPUART1 0U
329 #endif
330 #if defined(PCC_LPUART2_INDEX)
331  #define TMP_LPUART2 1U
332 #else
333  #define TMP_LPUART2 0U
334 #endif
335 #if defined(PCC_FTM4_INDEX)
336  #define TMP_FTM4 1U
337 #else
338  #define TMP_FTM4 0U
339 #endif
340 #if defined(PCC_FTM5_INDEX)
341  #define TMP_FTM5 1U
342 #else
343  #define TMP_FTM5 0U
344 #endif
345 #if defined(PCC_FTM6_INDEX)
346  #define TMP_FTM6 1U
347 #else
348  #define TMP_FTM6 0U
349 #endif
350 #if defined(PCC_FTM7_INDEX)
351  #define TMP_FTM7 1U
352 #else
353  #define TMP_FTM7 0U
354 #endif
355 #if defined(PCC_CMP0_INDEX)
356  #define TMP_CMP0 1U
357 #else
358  #define TMP_CMP0 0U
359 #endif
360 #if defined(PCC_QSPI_INDEX)
361  #define TMP_QSPI 1U
362 #else
363  #define TMP_QSPI 0U
364 #endif
365 #if defined(PCC_ENET_INDEX)
366  #define TMP_ENET 1U
367 #else
368  #define TMP_ENET 0U
369 #endif
370 
371 #define CLOCK_PERIPHERALS_COUNT (TMP_FTFC + TMP_DMAMUX + TMP_FlexCAN0 + TMP_FlexCAN1 + TMP_FTM3 + TMP_ADC1 + TMP_FlexCAN2 + TMP_LPSPI0 + TMP_LPSPI1 + TMP_LPSPI2 + TMP_PDB1 + TMP_CRC + TMP_PDB0 + TMP_LPIT + TMP_FTM0 + TMP_FTM1 + TMP_FTM2 + TMP_ADC0 + TMP_RTC + TMP_LPTMR0 + TMP_PORTA + TMP_PORTB + TMP_PORTC + TMP_PORTD + TMP_PORTE + TMP_SAI0 + TMP_SAI1 + TMP_FlexIO + TMP_EWM + TMP_LPI2C0 + TMP_LPI2C1 + TMP_LPUART0 + TMP_LPUART1 + TMP_LPUART2 + TMP_FTM4 + TMP_FTM5 + TMP_FTM6 + TMP_FTM7 + TMP_CMP0 + TMP_QSPI + TMP_ENET)
372 
373 
380 
385 
390 typedef enum
391 {
397 
402 typedef enum
403 {
408 
413 typedef enum
414 {
421 
422 
423 /*******************************************************************************
424  * INTERNAL FUNCTIONS
425  ******************************************************************************/
427 
429  uint32_t * frequency);
430 
431 #ifdef QuadSPI_INSTANCE_COUNT
432 static uint32_t CLOCK_SYS_GetQSPIInternalReferenceClock(void);
433 
434 static uint32_t CLOCK_SYS_GetQspiSfifClkHyp(void);
435 
436 static uint32_t CLOCK_SYS_GetQspiIpgClk(void);
437 
438 static uint32_t CLOCK_SYS_GetQspiIpgClkSfif(void);
439 
440 static uint32_t CLOCK_SYS_GetQspiIpgClk2Xsfif(void);
441 #endif
442 
444  uint32_t * frequency);
445 
447  uint32_t * frequency);
448 
449 static uint32_t CLOCK_SYS_GetPeripheralClock(clock_names_t clockName,
450  scg_async_clock_type_t divider);
451 
453 
455 
456 static uint32_t CLOCK_SYS_GetSimClkOutFreq(void);
457 
458 static uint32_t CLOCK_SYS_GetScgClkOutFreq(void);
459 
460 static uint32_t CLOCK_SYS_GetSimRtcClkFreq(void);
461 
463 
465 
466 static status_t CLOCK_SYS_ConfigureSIRC(bool enable, const scg_sirc_config_t * sircConfig);
467 
468 static status_t CLOCK_SYS_ConfigureFIRC(bool enable, const scg_firc_config_t * fircConfig);
469 
470 static status_t CLOCK_SYS_ConfigureSOSC(bool enable, const scg_sosc_config_t * soscConfig);
471 
472 #if FEATURE_HAS_SPLL_CLK
473 static status_t CLOCK_SYS_ConfigureSPLL(bool enable, const scg_spll_config_t * spllConfig);
474 #endif
475 
477 
479  scg_system_clock_config_t const * config);
480 
481 static uint32_t CLOCK_SYS_GetSysAsyncFreq(clock_names_t clockSource,
483 
484 static uint32_t CLOCK_SYS_GetSircFreq(void);
485 
486 static uint32_t CLOCK_SYS_GetFircFreq(void);
487 
488 static uint32_t CLOCK_SYS_GetSysOscFreq(void);
489 
490 #if FEATURE_HAS_SPLL_CLK
491 static uint32_t CLOCK_SYS_GetSysPllFreq(void);
492 #endif
493 
494 static uint32_t CLOCK_SYS_GetLpoFreq(void);
495 
497 
498 static void CLOCK_SYS_GetCurrentSysClkConfig(scg_system_clock_config_t * sysClockConfig);
499 
500 static status_t CLOCK_SYS_SetScgConfiguration(const scg_config_t * scgConfig);
501 
502 static void CLOCK_SYS_SetPccConfiguration(const pcc_config_t * peripheralClockConfig);
503 
504 static void CLOCK_SYS_SetSimConfiguration(const sim_clock_config_t * simClockConfig);
505 
506 static void CLOCK_SYS_SetPmcConfiguration(const pmc_config_t * pmcConfig);
507 
509 
510 /*******************************************************************************
511  * Code
512  ******************************************************************************/
513 
514 /*FUNCTION**********************************************************************
515  *
516  * Function Name : CLOCK_SYS_SetConfiguration
517  * Description : This function sets the system to target configuration, it
518  * only sets the clock modules registers for clock mode change, but not send
519  * notifications to drivers.
520  *
521  * Implements CLOCK_SYS_SetConfiguration_Activity
522  * END**************************************************************************/
524 {
525  status_t result;
526  clock_manager_user_config_t config_default;
527  clock_manager_user_config_t const * cfg = config;
528 
530 
531  if (config == NULL)
532  {
533  /* Get default configuration */
534  CLOCK_SYS_GetDefaultConfiguration(&config_default);
535  cfg = &config_default;
536  }
537 
538  /* Set SCG settings. */
540 
541  if (STATUS_SUCCESS == result)
542  {
543  /* Set PCC settings. */
545 
546  /* Set SIM settings. */
548 
549  /* Set PMC settings. */
551  }
552 
553  return result;
554 }
555 
556 /*FUNCTION**********************************************************************
557  *
558  * Function Name : CLOCK_SYS_SetScgConfiguration
559  * Description : This function configures the SCG blocks
560  *
561  * Implements CLOCK_SYS_SetScgConfiguration_Activity
562  * END**************************************************************************/
564 {
565  status_t status = STATUS_SUCCESS;
566  DEV_ASSERT(scgConfig != NULL);
567 
568  if (scgConfig != NULL)
569  {
570  /* Configure a temporary system clock source: FIRC */
572 
573  if (status == STATUS_SUCCESS)
574  {
575  /* Configure clock sources from SCG */
576  status = CLOCK_SYS_ConfigureModulesFromScg(scgConfig);
577  }
578 
579  if (status == STATUS_SUCCESS)
580  {
581  /* Configure RTC. */
582  if (scgConfig->rtcConfig.initialize)
583  {
584  /* RTC Clock settings. */
586  }
587 
588  /* Configure SCG ClockOut. */
589  if (scgConfig->clockOutConfig.initialize)
590  {
591  /* ClockOut settings. */
592  SCG_SetClockoutSourceSel(SCG, (uint32_t)scgConfig->clockOutConfig.source);
593  }
594 
595  /* Configure SCG clock modes. */
596  if (scgConfig->clockModeConfig.initialize)
597  {
598  /* Configure SCG clock modes */
600  if (status == STATUS_SUCCESS)
601  {
603  }
604 
605 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
606  if (status == STATUS_SUCCESS)
607  {
609  }
610 #endif
611  }
612  }
613  }
614 
615  return status;
616 }
617 
618 /*FUNCTION**********************************************************************
619  *
620  * Function Name : CLOCK_SYS_SetPccConfiguration
621  * Description : This function configures the PCC block
622  *
623  * Implements CLOCK_SYS_SetPccConfiguration_Activity
624  * END**************************************************************************/
625 static void CLOCK_SYS_SetPccConfiguration(const pcc_config_t * peripheralClockConfig)
626 {
627  DEV_ASSERT(peripheralClockConfig != NULL);
628 
629  uint32_t i;
630 
631  if ((peripheralClockConfig != NULL) && (peripheralClockConfig->peripheralClocks != NULL))
632  {
633  for (i = 0U; i < peripheralClockConfig->count; i++)
634  {
635  /* Disable the peripheral clock */
636  PCC_SetClockMode(PCC, peripheralClockConfig->peripheralClocks[i].clockName, false);
637 
638  /* Set peripheral clock control */
639  PCC_SetPeripheralClockControl(PCC,
640  peripheralClockConfig->peripheralClocks[i].clockName,
641  peripheralClockConfig->peripheralClocks[i].clkGate,
642  (uint32_t)peripheralClockConfig->peripheralClocks[i].clkSrc,
643  (uint32_t)peripheralClockConfig->peripheralClocks[i].divider,
644  (uint32_t)peripheralClockConfig->peripheralClocks[i].frac);
645  }
646  }
647 }
648 
649 /*FUNCTION**********************************************************************
650  *
651  * Function Name : CLOCK_SYS_SetSimConfiguration
652  * Description : This function configures the SIM block
653  *
654  * Implements CLOCK_SYS_SetSimConfiguration_Activity
655  * END**************************************************************************/
656 static void CLOCK_SYS_SetSimConfiguration(const sim_clock_config_t * simClockConfig)
657 {
658  DEV_ASSERT(simClockConfig != NULL);
659  uint8_t i;
660 
661  /* ClockOut settings. */
662  if (simClockConfig->clockOutConfig.initialize)
663  {
664  SIM_SetClockout(SIM, simClockConfig->clockOutConfig.enable, simClockConfig->clockOutConfig.source, simClockConfig->clockOutConfig.divider);
665  }
666 
667  /* Low Power Clock settings from SIM. */
668  if (simClockConfig->lpoClockConfig.initialize)
669  {
670  SIM_SetLpoClocks(SIM,
671  simClockConfig->lpoClockConfig.enableLpo1k,
672  simClockConfig->lpoClockConfig.enableLpo32k,
673  simClockConfig->lpoClockConfig.sourceLpoClk,
674  simClockConfig->lpoClockConfig.sourceRtcClk);
675  }
676 
677  /* Platform Gate Clock settings. */
678  if (simClockConfig->platGateConfig.initialize)
679  {
680  SIM_SetMscmClockGate(SIM, simClockConfig->platGateConfig.enableMscm);
681  SIM_SetMpuClockGate(SIM, simClockConfig->platGateConfig.enableMpu);
682  SIM_SetDmaClockGate(SIM, simClockConfig->platGateConfig.enableDma);
683  SIM_SetErmClockGate(SIM, simClockConfig->platGateConfig.enableErm);
684  SIM_SetEimClockGate(SIM, simClockConfig->platGateConfig.enableEim);
685 #if defined (QuadSPI_INSTANCE_COUNT)
686  SIM_SetQspiIntRefClockGate(SIM, simClockConfig->qspiRefClkGating.enableQspiRefClk);
687 #endif
688  }
689 
690  /* TCLK Clock settings. */
691  if (simClockConfig->tclkConfig.initialize)
692  {
693  for (i = 0; i < NUMBER_OF_TCLK_INPUTS; i++)
694  {
695  if (i < NUMBER_OF_TCLK_INPUTS)
696  {
697  g_TClkFreq[i] = simClockConfig->tclkConfig.tclkFreq[i];
698  }
699  }
700  }
701 
702  /* Debug trace Clock settings. */
703  if (simClockConfig->traceClockConfig.initialize)
704  {
705  SIM_ClearTraceClockConfig(SIM);
706  SIM_SetTraceClockSource(SIM, simClockConfig->traceClockConfig.source);
707 
708  SIM_SetTraceClockConfig(SIM, false, 0U, 0U);
709 
710  if (simClockConfig->traceClockConfig.divEnable)
711  {
712  SIM_SetTraceClockConfig(SIM,
713  simClockConfig->traceClockConfig.divEnable,
714  simClockConfig->traceClockConfig.divider,
715  simClockConfig->traceClockConfig.divFraction);
716  }
717  }
718 }
719 
720 /*FUNCTION**********************************************************************
721  *
722  * Function Name : CLOCK_SYS_SetPmcConfiguration
723  * Description : This function configures the PMC block
724  *
725  * Implements CLOCK_SYS_SetPmcConfiguration_Activity
726  * END**************************************************************************/
727 static void CLOCK_SYS_SetPmcConfiguration(const pmc_config_t * pmcConfig)
728 {
729  DEV_ASSERT(pmcConfig != NULL);
730 
731  /* Low Power Clock settings from PMC. */
732  if (pmcConfig->lpoClockConfig.initialize)
733  {
734  /* Enable/disable the low power oscillator. */
735  PMC_SetLpoMode(PMC, pmcConfig->lpoClockConfig.enable);
736 
737  /* Write trimming value. */
738  PMC_SetLpoTrimValue(PMC, pmcConfig->lpoClockConfig.trimValue);
739  }
740 }
741 
742 /*FUNCTION**********************************************************************
743  *
744  * Function Name : CLOCK_SYS_GetDefaultConfiguration
745  * Description : This function gets the system to a default configuration, it
746  * only gets the clock modules registers for clock mode change, but not send
747  * notifications to drivers.
748  *
749  * Implements CLOCK_SYS_GetConfiguration_Activity
750  * END**************************************************************************/
752 {
753  static peripheral_clock_config_t peripheralClockConfig[CLOCK_PERIPHERALS_COUNT] = {
754 #ifdef PCC_ADC0_INDEX
755  {
756  .clockName = ADC0_CLK,
757  .clkGate = true,
758  .clkSrc = CLK_SRC_SIRC_DIV1,
759  .frac = MULTIPLY_BY_ONE,
760  .divider = DIVIDE_BY_ONE,
761  },
762 #endif
763 #ifdef PCC_ADC1_INDEX
764  {
765  .clockName = ADC1_CLK,
766  .clkGate = true,
767  .clkSrc = CLK_SRC_SIRC_DIV1,
768  .frac = MULTIPLY_BY_ONE,
769  .divider = DIVIDE_BY_ONE,
770  },
771 #endif
772 #ifdef PCC_CMP0_INDEX
773  {
774  .clockName = CMP0_CLK,
775  .clkGate = true,
776  .clkSrc = CLK_SRC_OFF,
777  .frac = MULTIPLY_BY_ONE,
778  .divider = DIVIDE_BY_ONE,
779  },
780 #endif
781 #ifdef PCC_CRC_INDEX
782  {
783  .clockName = CRC0_CLK,
784  .clkGate = true,
785  .clkSrc = CLK_SRC_OFF,
786  .frac = MULTIPLY_BY_ONE,
787  .divider = DIVIDE_BY_ONE,
788  },
789 #endif
790 #ifdef PCC_DMAMUX_INDEX
791  {
792  .clockName = DMAMUX0_CLK,
793  .clkGate = true,
794  .clkSrc = CLK_SRC_OFF,
795  .frac = MULTIPLY_BY_ONE,
796  .divider = DIVIDE_BY_ONE,
797  },
798 #endif
799 #ifdef PCC_ENET_INDEX
800  {
801  .clockName = ENET0_CLK,
802  .clkGate = true,
803  .clkSrc = CLK_SRC_SIRC_DIV1,
804  .frac = MULTIPLY_BY_ONE,
805  .divider = DIVIDE_BY_ONE,
806  },
807 #endif
808 #ifdef PCC_EWM_INDEX
809  {
810  .clockName = EWM0_CLK,
811  .clkGate = true,
812  .clkSrc = CLK_SRC_OFF,
813  .frac = MULTIPLY_BY_ONE,
814  .divider = DIVIDE_BY_ONE,
815  },
816 #endif
817 #ifdef PCC_FlexCAN0_INDEX
818  {
819  .clockName = FlexCAN0_CLK,
820  .clkGate = true,
821  .clkSrc = CLK_SRC_OFF,
822  .frac = MULTIPLY_BY_ONE,
823  .divider = DIVIDE_BY_ONE,
824  },
825 #endif
826 #ifdef PCC_FlexCAN1_INDEX
827  {
828  .clockName = FlexCAN1_CLK,
829  .clkGate = true,
830  .clkSrc = CLK_SRC_OFF,
831  .frac = MULTIPLY_BY_ONE,
832  .divider = DIVIDE_BY_ONE,
833  },
834 #endif
835 #ifdef PCC_FlexCAN2_INDEX
836  {
837  .clockName = FlexCAN2_CLK,
838  .clkGate = true,
839  .clkSrc = CLK_SRC_OFF,
840  .frac = MULTIPLY_BY_ONE,
841  .divider = DIVIDE_BY_ONE,
842  },
843 #endif
844 #ifdef PCC_FlexIO_INDEX
845  {
846  .clockName = FLEXIO0_CLK,
847  .clkGate = true,
848  .clkSrc = CLK_SRC_SIRC_DIV1,
849  .frac = MULTIPLY_BY_ONE,
850  .divider = DIVIDE_BY_ONE,
851  },
852 #endif
853 #ifdef PCC_FTFC_INDEX
854  {
855  .clockName = FTFC0_CLK,
856  .clkGate = true,
857  .clkSrc = CLK_SRC_OFF,
858  .frac = MULTIPLY_BY_ONE,
859  .divider = DIVIDE_BY_ONE,
860  },
861 #endif
862 #ifdef PCC_FTM0_INDEX
863  {
864  .clockName = FTM0_CLK,
865  .clkGate = true,
866  .clkSrc = CLK_SRC_SIRC_DIV1,
867  .frac = MULTIPLY_BY_ONE,
868  .divider = DIVIDE_BY_ONE,
869  },
870 #endif
871 #ifdef PCC_FTM1_INDEX
872  {
873  .clockName = FTM1_CLK,
874  .clkGate = true,
875  .clkSrc = CLK_SRC_SIRC_DIV1,
876  .frac = MULTIPLY_BY_ONE,
877  .divider = DIVIDE_BY_ONE,
878  },
879 #endif
880 #ifdef PCC_FTM2_INDEX
881  {
882  .clockName = FTM2_CLK,
883  .clkGate = true,
884  .clkSrc = CLK_SRC_SIRC_DIV1,
885  .frac = MULTIPLY_BY_ONE,
886  .divider = DIVIDE_BY_ONE,
887  },
888 #endif
889 #ifdef PCC_FTM3_INDEX
890  {
891  .clockName = FTM3_CLK,
892  .clkGate = true,
893  .clkSrc = CLK_SRC_SIRC_DIV1,
894  .frac = MULTIPLY_BY_ONE,
895  .divider = DIVIDE_BY_ONE,
896  },
897 #endif
898 #ifdef PCC_FTM4_INDEX
899  {
900  .clockName = FTM4_CLK,
901  .clkGate = true,
902  .clkSrc = CLK_SRC_SIRC_DIV1,
903  .frac = MULTIPLY_BY_ONE,
904  .divider = DIVIDE_BY_ONE,
905  },
906 #endif
907 #ifdef PCC_FTM5_INDEX
908  {
909  .clockName = FTM5_CLK,
910  .clkGate = true,
911  .clkSrc = CLK_SRC_SIRC_DIV1,
912  .frac = MULTIPLY_BY_ONE,
913  .divider = DIVIDE_BY_ONE,
914  },
915 #endif
916 #ifdef PCC_FTM6_INDEX
917  {
918  .clockName = FTM6_CLK,
919  .clkGate = true,
920  .clkSrc = CLK_SRC_SIRC_DIV1,
921  .frac = MULTIPLY_BY_ONE,
922  .divider = DIVIDE_BY_ONE,
923  },
924 #endif
925 #ifdef PCC_FTM7_INDEX
926  {
927  .clockName = FTM7_CLK,
928  .clkGate = true,
929  .clkSrc = CLK_SRC_SIRC_DIV1,
930  .frac = MULTIPLY_BY_ONE,
931  .divider = DIVIDE_BY_ONE,
932  },
933 #endif
934 #ifdef PCC_LPI2C0_INDEX
935  {
936  .clockName = LPI2C0_CLK,
937  .clkGate = true,
938  .clkSrc = CLK_SRC_SIRC_DIV1,
939  .frac = MULTIPLY_BY_ONE,
940  .divider = DIVIDE_BY_ONE,
941  },
942 #endif
943 #ifdef PCC_LPI2C1_INDEX
944  {
945  .clockName = LPI2C1_CLK,
946  .clkGate = true,
947  .clkSrc = CLK_SRC_SIRC_DIV1,
948  .frac = MULTIPLY_BY_ONE,
949  .divider = DIVIDE_BY_ONE,
950  },
951 #endif
952 #ifdef PCC_LPIT_INDEX
953  {
954  .clockName = LPIT0_CLK,
955  .clkGate = true,
956  .clkSrc = CLK_SRC_SIRC_DIV1,
957  .frac = MULTIPLY_BY_ONE,
958  .divider = DIVIDE_BY_ONE,
959  },
960 #endif
961 #ifdef PCC_LPSPI0_INDEX
962  {
963  .clockName = LPSPI0_CLK,
964  .clkGate = true,
965  .clkSrc = CLK_SRC_SIRC_DIV1,
966  .frac = MULTIPLY_BY_ONE,
967  .divider = DIVIDE_BY_ONE,
968  },
969 #endif
970 #ifdef PCC_LPSPI1_INDEX
971  {
972  .clockName = LPSPI1_CLK,
973  .clkGate = true,
974  .clkSrc = CLK_SRC_SIRC_DIV1,
975  .frac = MULTIPLY_BY_ONE,
976  .divider = DIVIDE_BY_ONE,
977  },
978 #endif
979 #ifdef PCC_LPSPI2_INDEX
980  {
981  .clockName = LPSPI2_CLK,
982  .clkGate = true,
983  .clkSrc = CLK_SRC_SIRC_DIV1,
984  .frac = MULTIPLY_BY_ONE,
985  .divider = DIVIDE_BY_ONE,
986  },
987 #endif
988 #ifdef PCC_LPTMR0_INDEX
989  {
990  .clockName = LPTMR0_CLK,
991  .clkGate = true,
992  .clkSrc = CLK_SRC_SIRC_DIV1,
993  .frac = MULTIPLY_BY_ONE,
994  .divider = DIVIDE_BY_ONE,
995  },
996 #endif
997 #ifdef PCC_LPUART0_INDEX
998  {
999  .clockName = LPUART0_CLK,
1000  .clkGate = true,
1001  .clkSrc = CLK_SRC_SIRC_DIV1,
1002  .frac = MULTIPLY_BY_ONE,
1003  .divider = DIVIDE_BY_ONE,
1004  },
1005 #endif
1006 #ifdef PCC_LPUART1_INDEX
1007  {
1008  .clockName = LPUART1_CLK,
1009  .clkGate = true,
1010  .clkSrc = CLK_SRC_SIRC_DIV1,
1011  .frac = MULTIPLY_BY_ONE,
1012  .divider = DIVIDE_BY_ONE,
1013  },
1014 #endif
1015 #ifdef PCC_LPUART2_INDEX
1016  {
1017  .clockName = LPUART2_CLK,
1018  .clkGate = true,
1019  .clkSrc = CLK_SRC_SIRC_DIV1,
1020  .frac = MULTIPLY_BY_ONE,
1021  .divider = DIVIDE_BY_ONE,
1022  },
1023 #endif
1024 #ifdef PCC_PDB0_INDEX
1025  {
1026  .clockName = PDB0_CLK,
1027  .clkGate = true,
1028  .clkSrc = CLK_SRC_OFF,
1029  .frac = MULTIPLY_BY_ONE,
1030  .divider = DIVIDE_BY_ONE,
1031  },
1032 #endif
1033 #ifdef PCC_PDB1_INDEX
1034  {
1035  .clockName = PDB1_CLK,
1036  .clkGate = true,
1037  .clkSrc = CLK_SRC_OFF,
1038  .frac = MULTIPLY_BY_ONE,
1039  .divider = DIVIDE_BY_ONE,
1040  },
1041 #endif
1042 #ifdef PCC_PORTA_INDEX
1043  {
1044  .clockName = PORTA_CLK,
1045  .clkGate = true,
1046  .clkSrc = CLK_SRC_OFF,
1047  .frac = MULTIPLY_BY_ONE,
1048  .divider = DIVIDE_BY_ONE,
1049  },
1050 #endif
1051 #ifdef PCC_PORTB_INDEX
1052  {
1053  .clockName = PORTB_CLK,
1054  .clkGate = true,
1055  .clkSrc = CLK_SRC_OFF,
1056  .frac = MULTIPLY_BY_ONE,
1057  .divider = DIVIDE_BY_ONE,
1058  },
1059 #endif
1060 #ifdef PCC_PORTC_INDEX
1061  {
1062  .clockName = PORTC_CLK,
1063  .clkGate = true,
1064  .clkSrc = CLK_SRC_OFF,
1065  .frac = MULTIPLY_BY_ONE,
1066  .divider = DIVIDE_BY_ONE,
1067  },
1068 #endif
1069 #ifdef PCC_PORTD_INDEX
1070  {
1071  .clockName = PORTD_CLK,
1072  .clkGate = true,
1073  .clkSrc = CLK_SRC_OFF,
1074  .frac = MULTIPLY_BY_ONE,
1075  .divider = DIVIDE_BY_ONE,
1076  },
1077 #endif
1078 #ifdef PCC_PORTE_INDEX
1079  {
1080  .clockName = PORTE_CLK,
1081  .clkGate = true,
1082  .clkSrc = CLK_SRC_OFF,
1083  .frac = MULTIPLY_BY_ONE,
1084  .divider = DIVIDE_BY_ONE,
1085  },
1086 #endif
1087 #ifdef PCC_QSPI_INDEX
1088  {
1089  .clockName = QSPI0_CLK,
1090  .clkGate = true,
1091  .clkSrc = CLK_SRC_OFF,
1092  .frac = MULTIPLY_BY_ONE,
1093  .divider = DIVIDE_BY_ONE,
1094  },
1095 #endif
1096 #ifdef PCC_RTC_INDEX
1097  {
1098  .clockName = RTC0_CLK,
1099  .clkGate = true,
1100  .clkSrc = CLK_SRC_OFF,
1101  .frac = MULTIPLY_BY_ONE,
1102  .divider = DIVIDE_BY_ONE,
1103  },
1104 #endif
1105 #ifdef PCC_SAI0_INDEX
1106  {
1107  .clockName = SAI0_CLK,
1108  .clkGate = true,
1109  .clkSrc = CLK_SRC_OFF,
1110  .frac = MULTIPLY_BY_ONE,
1111  .divider = DIVIDE_BY_ONE,
1112  },
1113 #endif
1114 #ifdef PCC_SAI1_INDEX
1115  {
1116  .clockName = SAI1_CLK,
1117  .clkGate = true,
1118  .clkSrc = CLK_SRC_OFF,
1119  .frac = MULTIPLY_BY_ONE,
1120  .divider = DIVIDE_BY_ONE,
1121  },
1122 #endif
1123  };
1124 
1125  /* SCG */
1126  config->scgConfig.sircConfig.initialize = true;
1127  /* SIRCCSR */
1128  config->scgConfig.sircConfig.enableInStop = false;
1129  config->scgConfig.sircConfig.enableInLowPower = true;
1130  config->scgConfig.sircConfig.locked = false;
1131  /* SIRCCFG */
1133  /* SIRCDIV */
1137  config->scgConfig.fircConfig.initialize = true;
1138  /* FIRCCSR */
1139  config->scgConfig.fircConfig.regulator = true;
1140  config->scgConfig.fircConfig.locked = false;
1141  /* FIRCCFG */
1143  /* FIRCDIV */
1147  config->scgConfig.rtcConfig.initialize = true;
1148  config->scgConfig.rtcConfig.rtcClkInFreq = 0U;
1150  config->scgConfig.soscConfig.initialize = true;
1151  config->scgConfig.soscConfig.freq = 8000000U;
1152  /* SOSCCSR */
1154  config->scgConfig.soscConfig.locked = false;
1155  /* SOSCCFG */
1159  /* SOSCDIV */
1163  config->scgConfig.spllConfig.initialize = true;
1164  /* SPLLCSR */
1166  config->scgConfig.spllConfig.locked = false;
1167  /* SPLLCFG */
1170  config->scgConfig.spllConfig.src = 0U;
1171  /* SPLLDIV */
1175  config->scgConfig.clockOutConfig.initialize = true;
1178  config->scgConfig.clockModeConfig.initialize = true;
1190 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
1191 
1192  config->scgConfig.clockModeConfig.hccrConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
1196 #endif
1197 
1198  /* PCC */
1199  config->pccConfig.peripheralClocks = peripheralClockConfig;
1202  /* SIM */
1204  config->simConfig.clockOutConfig.initialize = true;
1205  config->simConfig.clockOutConfig.enable = false;
1209  config->simConfig.lpoClockConfig.initialize = true;
1210  config->simConfig.lpoClockConfig.enableLpo1k = true;
1211  config->simConfig.lpoClockConfig.enableLpo32k = true;
1215  config->simConfig.platGateConfig.initialize = true;
1216  config->simConfig.platGateConfig.enableMscm = true;
1217  config->simConfig.platGateConfig.enableMpu = true;
1218  config->simConfig.platGateConfig.enableDma = true;
1219  config->simConfig.platGateConfig.enableErm = true;
1220  config->simConfig.platGateConfig.enableEim = true;
1224  config->simConfig.tclkConfig.initialize = true;
1225  config->simConfig.tclkConfig.tclkFreq[0] = 0U;
1226  config->simConfig.tclkConfig.tclkFreq[1] = 0U;
1227  config->simConfig.tclkConfig.tclkFreq[2] = 0U;
1229  config->simConfig.traceClockConfig.initialize = true;
1230  config->simConfig.traceClockConfig.divEnable = true;
1232  config->simConfig.traceClockConfig.divider = 0U;
1233  config->simConfig.traceClockConfig.divFraction = false;
1235  /* PMC */
1237  config->pmcConfig.lpoClockConfig.initialize = true;
1238  config->pmcConfig.lpoClockConfig.enable = true;
1239  config->pmcConfig.lpoClockConfig.trimValue = 0;
1240 }
1241 
1242 /*FUNCTION**********************************************************************
1243  *
1244  * Function Name : CLOCK_SYS_GetScgClockFreq
1245  * Description : This function returns the frequency of a given clock from SCG
1246  *
1247  * END**************************************************************************/
1249  uint32_t * frequency)
1250 {
1251  status_t returnCode = STATUS_SUCCESS;
1252  uint32_t freq = 0U;
1253 
1254  switch (clockName)
1255  {
1256  /* Main clocks */
1257  case CORE_CLK:
1259  break;
1260  case BUS_CLK:
1262  break;
1263  case SLOW_CLK:
1265  break;
1266  case CLKOUT_CLK:
1267  freq = CLOCK_SYS_GetSimClkOutFreq();
1268  break;
1269 
1270  /* Other internal clocks used by peripherals. */
1271  case SIRC_CLK:
1272  freq = CLOCK_SYS_GetSircFreq();
1273  break;
1274  case FIRC_CLK:
1275  freq = CLOCK_SYS_GetFircFreq();
1276  break;
1277  case SOSC_CLK:
1278  freq = CLOCK_SYS_GetSysOscFreq();
1279  break;
1280 #if FEATURE_HAS_SPLL_CLK
1281  case SPLL_CLK:
1282  freq = CLOCK_SYS_GetSysPllFreq();
1283  break;
1284 #endif
1285  case RTC_CLKIN_CLK:
1286  freq = g_RtcClkInFreq;
1287  break;
1288  case SCG_CLKOUT_CLK:
1289  freq = CLOCK_SYS_GetScgClkOutFreq();
1290  break;
1291  case SIRCDIV1_CLK:
1293  break;
1294  case SIRCDIV2_CLK:
1296  break;
1297  case FIRCDIV1_CLK:
1299  break;
1300  case FIRCDIV2_CLK:
1302  break;
1303  case SOSCDIV1_CLK:
1305  break;
1306  case SOSCDIV2_CLK:
1308  break;
1309 #if FEATURE_HAS_SPLL_CLK
1310  case SPLLDIV1_CLK:
1312  break;
1313  case SPLLDIV2_CLK:
1315  break;
1316 #endif
1317  default:
1318  returnCode = STATUS_UNSUPPORTED;
1319  break;
1320  }
1321 
1322  if (frequency != NULL)
1323  {
1324  *frequency = freq;
1325  }
1326 
1327  return returnCode;
1328 }
1329 
1330 #ifdef QuadSPI_INSTANCE_COUNT
1331 static uint32_t CLOCK_SYS_GetQSPIInternalReferenceClock(void)
1332 {
1333  uint32_t freq = 0U;
1334  uint32_t divValue = 0U;
1335 
1336  if (SIM_GetClockingModeSelection(SIM))
1337  {
1338  if (QSPI_GetClockingModeSelection(QuadSPI))
1339  {
1341  }
1342  else
1343  {
1345  }
1346 
1347  divValue = QSPI_GetClockingProgrammableDividerValue(QuadSPI);
1348  freq /= (divValue + 1U);
1349  }
1350 
1351  return freq;
1352 }
1353 
1354 static uint32_t CLOCK_SYS_GetQspiSfifClkHyp(void)
1355 {
1356  uint32_t freq = 0U;
1357 
1358  freq = CLOCK_SYS_GetQSPIInternalReferenceClock();
1359  freq >>= 1U;
1360 
1361  return freq;
1362 }
1363 
1364 static uint32_t CLOCK_SYS_GetQspiIpgClk(void)
1365 {
1366  uint32_t freq = 0U;
1367 
1368  if (PCC_GetClockMode(PCC, QSPI0_CLK))
1369  {
1370  if (SIM_GetClockingModeSelection(SIM))
1371  {
1373  }
1374  else
1375  {
1377  }
1378  }
1379 
1380  return freq;
1381 }
1382 
1383 static uint32_t CLOCK_SYS_GetQspiIpgClkSfif(void)
1384 {
1385  uint32_t freq = 0U;
1386 
1387  freq = CLOCK_SYS_GetQSPIInternalReferenceClock();
1388 
1389  if (SIM_GetClockingModeSelection(SIM))
1390  {
1391  freq >>= 1U;
1392  }
1393 
1394  return freq;
1395 }
1396 
1397 static uint32_t CLOCK_SYS_GetQspiIpgClk2Xsfif(void)
1398 {
1399  uint32_t freq = 0U;
1400 
1401  if (SIM_GetClockingModeSelection(SIM))
1402  {
1403  freq = CLOCK_SYS_GetQSPIInternalReferenceClock();
1404  }
1405 
1406  return freq;
1407 }
1408 #endif
1409 
1410 /*FUNCTION**********************************************************************
1411  *
1412  * Function Name : CLOCK_SYS_GetSimClockFreq
1413  * Description : This function returns the frequency of a given clock from SIM
1414  *
1415  * END**************************************************************************/
1417  uint32_t * frequency)
1418 {
1419  status_t returnCode = STATUS_SUCCESS;
1420  uint32_t clockPinSelect;
1421  uint32_t freq = 0U;
1422 
1423  switch (clockName)
1424  {
1425  /* SIM clocks */
1426  case SIM_FTM0_CLOCKSEL:
1427  clockPinSelect = SIM_GetFtm0ExternalClkPinMode(SIM);
1428  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
1429  {
1430  freq = g_TClkFreq[clockPinSelect];
1431  }
1432 
1433  break;
1434  case SIM_FTM1_CLOCKSEL:
1435  clockPinSelect = SIM_GetFtm1ExternalClkPinMode(SIM);
1436  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
1437  {
1438  freq = g_TClkFreq[clockPinSelect];
1439  }
1440 
1441  break;
1442 #if FTM_INSTANCE_COUNT > 2U
1443  case SIM_FTM2_CLOCKSEL:
1444  clockPinSelect = SIM_GetFtm2ExternalClkPinMode(SIM);
1445  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
1446  {
1447  freq = g_TClkFreq[clockPinSelect];
1448  }
1449 
1450  break;
1451 #endif
1452 #if FTM_INSTANCE_COUNT > 3U
1453  case SIM_FTM3_CLOCKSEL:
1454  clockPinSelect = SIM_GetFtm3ExternalClkPinMode(SIM);
1455  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
1456  {
1457  freq = g_TClkFreq[clockPinSelect];
1458  }
1459 
1460  break;
1461 #endif
1462 #if FTM_INSTANCE_COUNT > 4U
1463  case SIM_FTM4_CLOCKSEL:
1464  clockPinSelect = SIM_GetFtm4ExternalClkPinMode(SIM);
1465  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
1466  {
1467  freq = g_TClkFreq[clockPinSelect];
1468  }
1469 
1470  break;
1471 #endif
1472 #if FTM_INSTANCE_COUNT > 5U
1473  case SIM_FTM5_CLOCKSEL:
1474  clockPinSelect = SIM_GetFtm5ExternalClkPinMode(SIM);
1475  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
1476  {
1477  freq = g_TClkFreq[clockPinSelect];
1478  }
1479 
1480  break;
1481 #endif
1482 #if FTM_INSTANCE_COUNT > 6U
1483  case SIM_FTM6_CLOCKSEL:
1484  clockPinSelect = SIM_GetFtm6ExternalClkPinMode(SIM);
1485  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
1486  {
1487  freq = g_TClkFreq[clockPinSelect];
1488  }
1489 
1490  break;
1491 #endif
1492 #if FTM_INSTANCE_COUNT > 7U
1493  case SIM_FTM7_CLOCKSEL:
1494  clockPinSelect = SIM_GetFtm7ExternalClkPinMode(SIM);
1495  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
1496  {
1497  freq = g_TClkFreq[clockPinSelect];
1498  }
1499 
1500  break;
1501 #endif
1502  case SIM_CLKOUTSELL:
1503  freq = CLOCK_SYS_GetSimClkOutFreq();
1504  break;
1505  case SIM_RTCCLK_CLK:
1506  freq = CLOCK_SYS_GetSimRtcClkFreq();
1507  break;
1508  case SIM_LPO_CLK:
1509  if (PMC_GetLpoMode(PMC))
1510  {
1511  freq = CLOCK_SYS_GetLpoFreq();
1512  }
1513 
1514  break;
1515  case SIM_LPO_1K_CLK:
1516  if (PMC_GetLpoMode(PMC))
1517  {
1518  freq = SIM_GetLpo1KStatus(SIM) ? LPO_1K_FREQUENCY : 0UL;
1519  }
1520 
1521  break;
1522  case SIM_LPO_32K_CLK:
1523  if (PMC_GetLpoMode(PMC))
1524  {
1525  freq = SIM_GetLpo32KStatus(SIM) ? LPO_32K_FREQUENCY : 0UL;
1526  }
1527 
1528  break;
1529  case SIM_LPO_128K_CLK:
1530  if (PMC_GetLpoMode(PMC))
1531  {
1532  freq = LPO_128K_FREQUENCY;
1533  }
1534 
1535  break;
1536  case SIM_EIM_CLK:
1537  if (!SIM_GetEimClockGate(SIM))
1538  {
1539  /* EIM is not clocked. */
1540  returnCode = STATUS_MCU_GATED_OFF;
1541  }
1542 
1543  break;
1544  case SIM_ERM_CLK:
1545  if (!SIM_GetErmClockGate(SIM))
1546  {
1547  /* ERM is not clocked. */
1548  returnCode = STATUS_MCU_GATED_OFF;
1549  }
1550 
1551  break;
1552  case SIM_DMA_CLK:
1553  if (!SIM_GetDmaClockGate(SIM))
1554  {
1555  /* DMA is not clocked. */
1556  returnCode = STATUS_MCU_GATED_OFF;
1557  }
1558 
1559  break;
1560  case SIM_MPU_CLK:
1561  if (!SIM_GetMpuClockGate(SIM))
1562  {
1563  /* MPU is not clocked. */
1564  returnCode = STATUS_MCU_GATED_OFF;
1565  }
1566 
1567  break;
1568  case SIM_MSCM_CLK:
1569  if (!SIM_GetMscmClockGate(SIM))
1570  {
1571  /* MSCM is not clocked. */
1572  returnCode = STATUS_MCU_GATED_OFF;
1573  }
1574 
1575  break;
1576 #ifdef QuadSPI_INSTANCE_COUNT
1577  case QSPI_MODULE_SFIF_CLK_HYP:
1578  freq = CLOCK_SYS_GetQspiSfifClkHyp();
1579  break;
1580 
1581  case QSPI_MODULE_CLK:
1582  freq = CLOCK_SYS_GetQspiIpgClk();
1583  break;
1584 
1585  case QSPI_MODULE_CLK_SFIF:
1586  freq = CLOCK_SYS_GetQspiIpgClkSfif();
1587  break;
1588 
1589  case QSPI_MODULE_CLK_2XSFIF:
1590  freq = CLOCK_SYS_GetQspiIpgClk2Xsfif();
1591  break;
1592 #endif
1593  default:
1594  returnCode = STATUS_UNSUPPORTED;
1595  break;
1596  }
1597 
1598  if (frequency != NULL)
1599  {
1600  *frequency = freq;
1601  }
1602 
1603  return returnCode;
1604 }
1605 
1606 /*FUNCTION**********************************************************************
1607  *
1608  * Function Name : CLOCK_SYS_GetPccClockFreq
1609  * Description : This function returns the clock frequency of peripheral functional clock.
1610  * END**************************************************************************/
1612  uint32_t * frequency)
1613 {
1614  status_t returnCode = STATUS_SUCCESS;
1615  uint32_t freq = 0U;
1616 
1617  /* Invalid PCC clock names. */
1618  if ((clockName <= SIM_END_OF_CLOCKS) ||
1619  (clockName == PCC_END_OF_BUS_CLOCKS) ||
1620  (clockName == PCC_END_OF_SYS_CLOCKS) ||
1621  (clockName == PCC_END_OF_SLOW_CLOCKS) ||
1622  (clockName == PCC_END_OF_ASYNCH_DIV1_CLOCKS) ||
1623  (clockName == PCC_END_OF_ASYNCH_DIV2_CLOCKS))
1624  {
1625  returnCode = STATUS_UNSUPPORTED;
1626  }
1627  else if (PCC_GetClockMode(PCC, clockName) == false)
1628  {
1629  /* Module is not clocked. */
1630  returnCode = STATUS_MCU_GATED_OFF;
1631  }
1632  else
1633  {
1634  if ((peripheralFeaturesList[clockName] & HAS_INT_CLOCK_FROM_BUS_CLOCK) != 0U)
1635  {
1636  /* Check whether BUS CLOCK is clocked. */
1638  }
1639  else if ((peripheralFeaturesList[clockName] & HAS_INT_CLOCK_FROM_SYS_CLOCK) != 0U)
1640  {
1641  /* Check whether SYS CLOCK is clocked. */
1643  }
1644  else if ((peripheralFeaturesList[clockName] & HAS_INT_CLOCK_FROM_SLOW_CLOCK) != 0U)
1645  {
1646  /* Check whether SLOW CLOCK is clocked. */
1648  }
1649  else
1650  { /* It's an issue in peripheral features list, each peripheral must have one interface clock. */
1651  DEV_ASSERT(false);
1652  }
1653 
1654  if (returnCode == STATUS_SUCCESS)
1655  {
1656  /* Check whether peripheral has protocol clock (functional clock) */
1658  {
1659  if ((peripheralFeaturesList[clockName] & HAS_PROTOCOL_CLOCK_FROM_ASYNC1) != 0U)
1660  {
1661  /* Check whether the functional clock is clocked */
1663  }
1664 
1665  if ((peripheralFeaturesList[clockName] & HAS_PROTOCOL_CLOCK_FROM_ASYNC2) != 0U)
1666  {
1667  /* Check whether the functional clock is clocked */
1669  }
1670 
1671  if (freq == 0U)
1672  {
1673  returnCode = STATUS_MCU_GATED_OFF;
1674  }
1675 
1676  }
1677  }
1678 
1679 
1680 
1681  }
1682 
1683  /* If frequency reference is provided, write this value */
1684  if (frequency != NULL)
1685  {
1686  *frequency = freq;
1687  }
1688 
1689  return returnCode;
1690 }
1691 
1692 /*FUNCTION**********************************************************************
1693  *
1694  * Function Name : CLOCK_SYS_GetFreq
1695  * Description : This function returns the frequency of a given clock
1696  *
1697  * Implements CLOCK_SYS_GetFreq_Activity
1698  * END**************************************************************************/
1700  uint32_t * frequency)
1701 {
1702  status_t returnCode;
1703 
1704  /* Frequency of the clock name from SCG */
1705  if (clockName < SCG_END_OF_CLOCKS)
1706  {
1707  returnCode = CLOCK_SYS_GetScgClockFreq(clockName, frequency);
1708  }
1709  /* Frequency of the clock name from SIM */
1710  else if (clockName < SIM_END_OF_CLOCKS)
1711  {
1712  returnCode = CLOCK_SYS_GetSimClockFreq(clockName, frequency);
1713  }
1714  /* Frequency of the clock name from PCC */
1715  else if (clockName < PCC_END_OF_CLOCKS)
1716  {
1717  returnCode = CLOCK_SYS_GetPccClockFreq(clockName, frequency);
1718  }
1719  /* Invalid clock name */
1720  else
1721  {
1722  returnCode = STATUS_UNSUPPORTED;
1723  }
1724 
1725  return returnCode;
1726 }
1727 
1728 /*FUNCTION**********************************************************************
1729  * Function Name : CLOCK_SYS_GetPeripheralClock
1730  * Description : Internal function used by CLOCK_SYS_GetFreq function
1731  * END**************************************************************************/
1732 
1734  scg_async_clock_type_t divider)
1735 {
1736  uint32_t frequency = 0;
1737  uint32_t fracValue = PCC_GetFracValueSel(PCC, clockName);
1738  uint32_t divValue = PCC_GetDividerSel(PCC, clockName);
1739 
1740  /* Check division factor */
1741  if (((uint32_t)fracValue) <= ((uint32_t)divValue))
1742  {
1743  /* Check clock gate */
1744  if (PCC_GetClockMode(PCC, clockName))
1745  {
1746  /* Check clock source */
1747  switch (PCC_GetClockSourceSel(PCC, clockName))
1748  {
1749  case (uint32_t)CLK_SRC_SOSC:
1750  frequency = CLOCK_SYS_GetSysAsyncFreq(SOSC_CLK, divider);
1751  break;
1752  case (uint32_t)CLK_SRC_SIRC:
1753  frequency = CLOCK_SYS_GetSysAsyncFreq(SIRC_CLK, divider);
1754  break;
1755  case (uint32_t)CLK_SRC_FIRC:
1756  frequency = CLOCK_SYS_GetSysAsyncFreq(FIRC_CLK, divider);
1757  break;
1758 #if FEATURE_HAS_SPLL_CLK
1759  case (uint32_t)CLK_SRC_SPLL:
1760  frequency = CLOCK_SYS_GetSysAsyncFreq(SPLL_CLK, divider);
1761  break;
1762 #endif
1763  default:
1764  frequency = 0;
1765  break;
1766  }
1767 
1768  frequency = frequency / (divValue + 1U);
1769  frequency = frequency * (fracValue + 1U);
1770  }
1771  }
1772 
1773  return frequency;
1774 }
1775 
1776 /*FUNCTION**********************************************************************
1777  * Function Name : CLOCK_SYS_GetCurrentRunMode
1778  * Description : Internal function used by CLOCK_SYS_SetScgConfiguration function
1779  * END**************************************************************************/
1781 {
1783 
1784  /* Get the current running mode */
1785  switch (SMC_GetCurrentRunningMode(SMC))
1786  {
1787  /* High speed run mode */
1790  break;
1791  /* Run mode */
1794  break;
1795  /* Very low power run mode */
1798  break;
1799  /* This should never happen - core has to be in some run mode to execute code */
1800  default:
1802  break;
1803  }
1804 
1805  return mode;
1806 }
1807 
1808 /*FUNCTION**********************************************************************
1809  * Function Name : CLOCK_SYS_TransitionSystemClock
1810  * Description : Internal function used by CLOCK_SYS_ConfigureTemporarySystemClock and
1811  * CLOCK_SYS_ConfigureModulesFromScg functions
1812  * END**************************************************************************/
1814 {
1815  scg_system_clock_mode_t run_mode;
1816  status_t retValue = STATUS_SUCCESS;
1817  uint32_t timeout;
1818 
1819  /* Check destination clock */
1820  DEV_ASSERT(to_clk != NULL);
1822 
1823  /* Get & Convert Run mode from SMC to SCG defines*/
1824  run_mode = CLOCK_SYS_GetCurrentRunMode();
1825 
1826  /* Check the current mode */
1828 
1829  /* Update run mode configuration */
1830  retValue = CLOCK_SYS_SetSystemClockConfig(run_mode, to_clk);
1831 
1832  if (retValue == STATUS_SUCCESS)
1833  {
1834  /* Wait for system clock to transition. */
1835 #ifdef ERRATA_E10777
1836  timeout = 10U;
1837 #else
1838  timeout = 1U;
1839 #endif
1840 
1841  do
1842  {
1843  timeout--;
1844  }
1845  while ((SCG_GetCurrentSystemClockSource(SCG) != ((uint32_t)to_clk->src)) && (timeout > 0U));
1846 
1847  if (timeout == 0U)
1848  {
1849  retValue = STATUS_TIMEOUT;
1850  }
1851  }
1852 
1853  return retValue;
1854 }
1855 
1856 /*FUNCTION**********************************************************************
1857  * Function Name : CLOCK_SYS_GetSimClkOutFreq
1858  * Description : Internal function used by CLOCK_SYS_GetFreq function
1859  * END**************************************************************************/
1860 static uint32_t CLOCK_SYS_GetSimClkOutFreq(void)
1861 {
1862  uint32_t frequency;
1863 
1864  if (SIM_GetClockoutStatus(SIM))
1865  {
1866  switch (SIM_GetClockoutSelectorValue(SIM))
1867  {
1868  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT):
1869  frequency = CLOCK_SYS_GetScgClkOutFreq();
1870  break;
1871  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SOSC_DIV2_CLK):
1873  break;
1874  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SIRC_DIV2_CLK):
1876  break;
1877  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_FIRC_DIV2_CLK):
1879  break;
1880  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_HCLK):
1882  break;
1883 #if FEATURE_HAS_SPLL_CLK
1884  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SPLL_DIV2_CLK):
1885  frequency = CLOCK_SYS_GetSysAsyncFreq(SPLL_CLK, SCG_ASYNC_CLOCK_DIV2);
1886  break;
1887 #endif
1888  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_BUS_CLK):
1890  break;
1891  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_LPO_128K_CLK):
1892  frequency = LPO_128K_FREQUENCY;
1893  break;
1894  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_LPO_CLK):
1895  frequency = CLOCK_SYS_GetLpoFreq();
1896  break;
1897  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_RTC_CLK):
1898  frequency = CLOCK_SYS_GetSimRtcClkFreq();
1899  break;
1900 #ifdef QuadSPI_INSTANCE_COUNT
1901  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SFIF_CLK_HYP):
1902  frequency = CLOCK_SYS_GetQspiSfifClkHyp();
1903  break;
1904  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_IPG_CLK):
1905  frequency = CLOCK_SYS_GetQspiIpgClk();
1906  break;
1907  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_IPG_CLK_SFIF):
1908  frequency = CLOCK_SYS_GetQspiIpgClkSfif();
1909  break;
1910  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_IPG_CLK_2XSFIF):
1911  frequency = CLOCK_SYS_GetQspiIpgClk2Xsfif();
1912  break;
1913 #endif
1914  default:
1915  /* Invalid SIM CLKOUT selection.*/
1916  frequency = 0U;
1917  break;
1918  }
1919 
1920  /* Apply Divide Ratio */
1921  frequency /= (SIM_GetClockoutDividerValue(SIM) + 1U);
1922  }
1923  else
1924  {
1925  /* Output disabled. */
1926  frequency = 0U;
1927  }
1928 
1929  return frequency;
1930 }
1931 
1932 /*FUNCTION**********************************************************************
1933  * Function Name : CLOCK_SYS_GetScgClkOutFreq
1934  * Description : Internal function used by CLOCK_SYS_GetFreq function
1935  * END**************************************************************************/
1936 static uint32_t CLOCK_SYS_GetScgClkOutFreq(void)
1937 {
1938  uint32_t frequency;
1939 
1940  switch (SCG_GetClockoutSourceSel(SCG))
1941  {
1942  case ((uint32_t)SCG_CLOCKOUT_SRC_SCG_SLOW):
1944  break;
1945  case ((uint32_t)SCG_CLOCKOUT_SRC_SOSC):
1946  frequency = CLOCK_SYS_GetSysOscFreq();
1947  break;
1948  case ((uint32_t)SCG_CLOCKOUT_SRC_SIRC):
1949  frequency = CLOCK_SYS_GetSircFreq();
1950  break;
1951  case ((uint32_t)SCG_CLOCKOUT_SRC_FIRC):
1952  frequency = CLOCK_SYS_GetFircFreq();
1953  break;
1954 #if FEATURE_HAS_SPLL_CLK
1955  case ((uint32_t)SCG_CLOCKOUT_SRC_SPLL):
1956  frequency = CLOCK_SYS_GetSysPllFreq();
1957  break;
1958 #endif
1959  default:
1960  /* Invalid SCG CLKOUT selection.*/
1961  frequency = 0U;
1962  break;
1963  }
1964 
1965  return frequency;
1966 }
1967 
1968 /*FUNCTION**********************************************************************
1969  * Function Name : CLOCK_SYS_GetSimRtcClkFreq
1970  * Description : Internal function used by CLOCK_SYS_GetFreq function
1971  * END**************************************************************************/
1973 {
1974  uint32_t frequency;
1975 
1976  /* Check RTCCLK Select */
1977  switch (SIM_GetRtcClkSrc(SIM))
1978  {
1979  case ((uint32_t)SIM_RTCCLK_SEL_SOSCDIV1_CLK):
1981  break;
1982  case ((uint32_t)SIM_RTCCLK_SEL_LPO_32K):
1983  frequency = SIM_GetLpo32KStatus(SIM) ? LPO_32K_FREQUENCY : 0UL;
1984  break;
1985  case ((uint32_t)SIM_RTCCLK_SEL_RTC_CLKIN):
1986  frequency = g_RtcClkInFreq;
1987  break;
1988  case ((uint32_t)SIM_RTCCLK_SEL_FIRCDIV1_CLK):
1990  break;
1991  default:
1992  /* Invalid RTCCLK selection.*/
1993  frequency = 0U;
1994  break;
1995  }
1996 
1997  return frequency;
1998 }
1999 
2000 /*FUNCTION**********************************************************************
2001  * Function Name : CLOCK_SYS_ConfigureSIRC
2002  * Description : Configures SIRC module based on provided configuration.
2003  * END**************************************************************************/
2004 static status_t CLOCK_SYS_ConfigureSIRC(bool enable, const scg_sirc_config_t * sircConfig)
2005 {
2006  status_t status = STATUS_SUCCESS;
2007  scg_sirc_config_t sircDefaultConfig;
2008  const scg_sirc_config_t * sircCfg;
2009  uint32_t timeout;
2010 
2011  if (sircConfig == NULL)
2012  {
2013  sircDefaultConfig.enableInStop = false;
2014  sircDefaultConfig.enableInLowPower = true;
2015  sircDefaultConfig.locked = false;
2016 
2017  sircDefaultConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
2018  sircDefaultConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
2019 
2020  sircDefaultConfig.range = SCG_SIRC_RANGE_HIGH;
2021 
2022  sircCfg = &sircDefaultConfig;
2023  }
2024  else
2025  {
2026  sircCfg = sircConfig;
2027  }
2028 
2029  /* If clock is used by system, return error. */
2030  if (SCG_GetSircSystemClockMode(SCG))
2031  {
2032  status = STATUS_BUSY;
2033  }
2034  /* Disable SIRC */
2035  else
2036  {
2037  /* Clear LK bit field */
2038  SCG_ClearSircLock(SCG);
2039 
2040  /* Disable monitor, disable clock and clear error. */
2041  SCG_ClearSircControl(SCG);
2042  }
2043 
2044  /* Configure SIRC. */
2045  if (enable && (status == STATUS_SUCCESS))
2046  {
2047  /* Now start to set up SIRC clock. */
2048  /* Step 1. Setup dividers. */
2049  SCG_SetSircAsyncConfig(SCG, sircCfg->div1, sircCfg->div2);
2050 
2051  /* Step 2. Set SIRC configuration: frequency range. */
2052  SCG_SetSircConfiguration(SCG, sircCfg->range);
2053 
2054  /* Step 3. Set SIRC control: enable clock, configure source in STOP and VLP modes, configure lock feature. */
2055  SCG_SetSircControl(SCG, sircCfg->enableInStop, sircCfg->enableInLowPower, sircCfg->locked);
2056 
2057  /* Wait for SIRC to initialize */
2058  timeout = SIRC_STABILIZATION_TIMEOUT;
2059  while ((CLOCK_SYS_GetSircFreq() == 0U) && (timeout > 0U))
2060  {
2061  timeout--;
2062  }
2063 
2064  if (timeout == 0U)
2065  {
2066  status = STATUS_TIMEOUT;
2067  }
2068  }
2069 
2070  return status;
2071 }
2072 
2073 /*FUNCTION**********************************************************************
2074  * Function Name : CLOCK_SYS_ConfigureFIRC
2075  * Description : Configures FIRC module based on provided configuration.
2076  * END**************************************************************************/
2077 static status_t CLOCK_SYS_ConfigureFIRC(bool enable, const scg_firc_config_t * fircConfig)
2078 {
2079  status_t status = STATUS_SUCCESS;
2080  scg_firc_config_t fircDefaultConfig;
2081  const scg_firc_config_t * fircCfg;
2082  uint32_t timeout;
2083 
2084  if (fircConfig == NULL)
2085  {
2086  fircDefaultConfig.regulator = true;
2087  fircDefaultConfig.locked = false;
2088 
2089  fircDefaultConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
2090  fircDefaultConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
2091 
2092  fircDefaultConfig.range = SCG_FIRC_RANGE_48M;
2093 
2094  fircCfg = &fircDefaultConfig;
2095  }
2096  else
2097  {
2098  fircCfg = fircConfig;
2099  }
2100 
2101  /* If clock is used by system, return error. */
2102  if (SCG_GetFircSystemClockMode(SCG))
2103  {
2104  status = STATUS_BUSY;
2105  }
2106  /* Disable FIRC */
2107  else
2108  {
2109  /* Clear LK bit field */
2110  SCG_ClearFircLock(SCG);
2111 
2112  /* Disable monitor, disable clock and clear error. */
2113  SCG_ClearFircControl(SCG);
2114  }
2115 
2116  /* Configure FIRC. */
2117  if (enable && (status == STATUS_SUCCESS))
2118  {
2119  /* Now start to set up FIRC clock. */
2120  /* Step 1. Setup dividers. */
2121  SCG_SetFircAsyncConfig(SCG, fircCfg->div1, fircCfg->div2);
2122 
2123  /* Step 2. Set FIRC configuration. */
2124  SCG_SetFircConfiguration(SCG, fircCfg->range);
2125 
2126  /* Step 3. Enable clock, config regulator and locking feature. */
2127  SCG_SetFircControl(SCG, fircCfg->regulator, fircCfg->locked);
2128 
2129  /* Wait for FIRC to initialize */
2130  timeout = FIRC_STABILIZATION_TIMEOUT;
2131  while ((CLOCK_SYS_GetFircFreq() == 0U) && (timeout > 0U))
2132  {
2133  timeout--;
2134  }
2135 
2136  if (timeout == 0U)
2137  {
2138  status = STATUS_TIMEOUT;
2139  }
2140  }
2141 
2142  return status;
2143 }
2144 
2145 /*FUNCTION**********************************************************************
2146  * Function Name : CLOCK_SYS_ConfigureSOSC
2147  * Description : Configures SOSC module based on provided configuration.
2148  * END**************************************************************************/
2149 static status_t CLOCK_SYS_ConfigureSOSC(bool enable, const scg_sosc_config_t * soscConfig)
2150 {
2151  status_t status = STATUS_SUCCESS;
2152  scg_sosc_config_t soscDefaultConfig;
2153  const scg_sosc_config_t * soscCfg;
2154  uint32_t timeout;
2155 
2156  if (soscConfig == NULL)
2157  {
2158  soscDefaultConfig.monitorMode = SCG_SOSC_MONITOR_DISABLE;
2159  soscDefaultConfig.locked = false;
2160 
2161  soscDefaultConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
2162  soscDefaultConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
2163 
2164  soscDefaultConfig.extRef = SCG_SOSC_REF_EXT;
2165  soscDefaultConfig.gain = SCG_SOSC_GAIN_LOW;
2166  soscDefaultConfig.range = SCG_SOSC_RANGE_MID;
2167 
2168  soscCfg = &soscDefaultConfig;
2169  }
2170  else
2171  {
2172  soscCfg = soscConfig;
2173  }
2174 
2175  /* If clock is used by system, return error. */
2176  if (SCG_GetSoscSystemClockMode(SCG))
2177  {
2178  status = STATUS_BUSY;
2179  }
2180  /* Disable SOSC */
2181  else
2182  {
2183  /* Clear LK bit field */
2184  SCG_ClearSoscLock(SCG);
2185 
2186  /* Disable monitor, disable clock and clear error. */
2187  SCG_ClearSoscControl(SCG);
2188 
2189  g_xtal0ClkFreq = 0U;
2190  }
2191 
2192  /* Configure SOSC. */
2193  if (enable && (status == STATUS_SUCCESS))
2194  {
2195  /* Now start to set up OSC clock. */
2196  /* Step 1. Setup dividers. */
2197  SCG_SetSoscAsyncConfig(SCG, soscCfg->div1, soscCfg->div2);
2198 
2199  /* Step 2. Set OSC configuration. */
2200  SCG_SetSoscConfiguration(SCG, soscCfg->range, soscCfg->gain, soscCfg->extRef);
2201 
2202  /* Step 3. Enable clock, configure monitor, lock register. */
2203  switch (soscCfg->monitorMode)
2204  {
2206  {
2207  SCG_SetSoscControl(SCG, false, false, soscCfg->locked);
2208  }
2209  break;
2210  case SCG_SOSC_MONITOR_INT:
2211  {
2212  SCG_SetSoscControl(SCG, true, false, soscCfg->locked);
2213  }
2214  break;
2216  {
2217  SCG_SetSoscControl(SCG, true, true, soscCfg->locked);
2218  }
2219  break;
2220  default:
2221  /* Invalid monitor mode */
2222  DEV_ASSERT(false);
2223  break;
2224  }
2225 
2226  g_xtal0ClkFreq = soscCfg->freq;
2227 
2228  /* Wait for System OSC to initialize */
2229  timeout = SOSC_STABILIZATION_TIMEOUT;
2230  while ((CLOCK_SYS_GetSysOscFreq() == 0U) && (timeout > 0U))
2231  {
2232  timeout--;
2233  }
2234 
2235  if (timeout == 0U)
2236  {
2237  status = STATUS_TIMEOUT;
2238  }
2239  }
2240 
2241  return status;
2242 }
2243 
2244 #if FEATURE_HAS_SPLL_CLK
2245 /*FUNCTION**********************************************************************
2246  * Function Name : CLOCK_SYS_ConfigureSPLL
2247  * Description : Configures SPLL module based on provided configuration.
2248  * END**************************************************************************/
2249 static status_t CLOCK_SYS_ConfigureSPLL(bool enable, const scg_spll_config_t * spllConfig)
2250 {
2251  status_t status = STATUS_SUCCESS;
2252  scg_spll_config_t spllDefaultConfig;
2253  const scg_spll_config_t * spllCfg;
2254  uint32_t srcFreq, timeout;
2255 
2256  if (spllConfig == NULL)
2257  {
2258  spllDefaultConfig.monitorMode = SCG_SPLL_MONITOR_DISABLE;
2259  spllDefaultConfig.locked = false;
2260 
2261  spllDefaultConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
2262  spllDefaultConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
2263 
2264  spllDefaultConfig.prediv = 0;
2265  spllDefaultConfig.mult = 0;
2266  spllDefaultConfig.src = 0;
2267 
2268  spllCfg = &spllDefaultConfig;
2269  }
2270  else
2271  {
2272  spllCfg = spllConfig;
2273  }
2274 
2275  /* If clock is used by system, return error. */
2276  if (SCG_GetSpllSystemClockMode(SCG))
2277  {
2278  status = STATUS_BUSY;
2279  }
2280  /* Disable the SPLL. */
2281  else
2282  {
2283  /* Clear LK bit field */
2284  SCG_ClearSpllLock(SCG);
2285 
2286  /* Disable monitor, disable clock and clear error. */
2287  SCG_ClearSpllControl(SCG);
2288  }
2289 
2290  /* Configure SPLL. */
2291  if (enable && (status == STATUS_SUCCESS))
2292  {
2293  /* Get clock source frequency. */
2294  srcFreq = CLOCK_SYS_GetSysOscFreq();
2295  DEV_ASSERT(srcFreq != 0U);
2296 
2297  /* Pre-divider checking. */
2298  srcFreq /= (((uint32_t)spllCfg->prediv) + SCG_SPLL_PREDIV_BASE);
2299  DEV_ASSERT((srcFreq >= SCG_SPLL_REF_MIN) && (srcFreq <= SCG_SPLL_REF_MAX));
2300 
2301  /* Now start to set up PLL clock. */
2302  SCG_SetSpllAsyncConfig(SCG, spllCfg->div1, spllCfg->div2);
2303 
2304  /* Step 2. Set PLL configuration. */
2305  SCG_SetSpllConfiguration(SCG, spllCfg->prediv, spllCfg->mult);
2306 
2307  /* Step 3. Enable clock, configure monitor, lock register. */
2308  switch (spllCfg->monitorMode)
2309  {
2311  {
2312  SCG_SetSpllControl(SCG, false, false, spllCfg->locked);
2313  }
2314  break;
2315  case SCG_SPLL_MONITOR_INT:
2316  {
2317  SCG_SetSpllControl(SCG, true, false, spllCfg->locked);
2318  }
2319  break;
2321  {
2322  SCG_SetSpllControl(SCG, true, true, spllCfg->locked);
2323  }
2324  break;
2325  default:
2326  /* Invalid monitor mode */
2327  DEV_ASSERT(false);
2328  break;
2329  }
2330 
2331  /* Wait for System PLL to initialize */
2332  timeout = SPLL_STABILIZATION_TIMEOUT;
2333  while ((CLOCK_SYS_GetSysPllFreq() == 0U) && (timeout > 0U))
2334  {
2335  timeout--;
2336  }
2337 
2338  if (timeout == 0U)
2339  {
2340  status = STATUS_TIMEOUT;
2341  }
2342  }
2343 
2344  return status;
2345 }
2346 #endif
2347 
2348 /*FUNCTION**********************************************************************
2349  * Function Name : CLOCK_SYS_ConfigureTemporarySystemClock
2350  * Description : Configures and transitions to a temporary system clock source: FIRC
2351  * END**************************************************************************/
2353 {
2354  status_t status = STATUS_SUCCESS;
2355  scg_system_clock_config_t sysClockConfig;
2357 
2358  /* If the current system clock source is not FIRC:
2359  * 1. Enable FIRC (if it's not enabled)
2360  * 2. Switch to FIRC.
2361  */
2362  if (SCG_GetCurrentSystemClockSource(SCG) != ((uint32_t)SCG_SYSTEM_CLOCK_SRC_FIRC))
2363  {
2364  /* If FIRC is not on, then FIRC is configured
2365  * with the default configuration */
2366  if (CLOCK_SYS_GetFircFreq() == 0UL)
2367  {
2368  status = CLOCK_SYS_ConfigureFIRC(true, NULL);
2369  }
2370 
2371  /* FIRC is enabled, transition the system clock source to FIRC. */
2372  if (status == STATUS_SUCCESS)
2373  {
2374  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_FIRC;
2375  sysClockConfig.divCore = tmpSysClk[TMP_FIRC_CLK][TMP_SYS_DIV];
2376  sysClockConfig.divBus = tmpSysClk[TMP_FIRC_CLK][TMP_BUS_DIV];
2377  sysClockConfig.divSlow = tmpSysClk[TMP_FIRC_CLK][TMP_SLOW_DIV];
2378  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2379  }
2380  }
2381 
2382  return status;
2383 }
2384 
2385 /*FUNCTION**********************************************************************
2386  * Function Name : CLOCK_SYS_ConfigureModulesFromScg
2387  * Description : Configures all modules from SCG (SIRC, FIRC, SOSC and SPLL)
2388  * END**************************************************************************/
2390 {
2391  status_t status = STATUS_SUCCESS;
2392  scg_system_clock_config_t sysClockConfig;
2393  const scg_system_clock_config_t * nextSysClockConfig;
2395 
2396  /* Configure all clock sources that are different from the
2397  * current system clock source FIRC (SIRC, SOSC, SPLL). */
2398  status = CLOCK_SYS_ConfigureSIRC(scgConfig->sircConfig.initialize, &scgConfig->sircConfig);
2399  if (status == STATUS_SUCCESS)
2400  {
2401  status = CLOCK_SYS_ConfigureSOSC(scgConfig->soscConfig.initialize, &scgConfig->soscConfig);
2402 #if FEATURE_HAS_SPLL_CLK
2403  if (status == STATUS_SUCCESS)
2404  {
2405  status = CLOCK_SYS_ConfigureSPLL(scgConfig->spllConfig.initialize,&scgConfig->spllConfig);
2406  }
2407 #endif
2408  }
2409 
2410  /* Get the next system clock source */
2411  switch (CLOCK_SYS_GetCurrentRunMode())
2412  {
2414  {
2415  nextSysClockConfig = &scgConfig->clockModeConfig.rccrConfig;
2416  }
2417  break;
2419  {
2420  nextSysClockConfig = &scgConfig->clockModeConfig.vccrConfig;
2421  }
2422  break;
2423 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
2425  {
2426  nextSysClockConfig = &scgConfig->clockModeConfig.hccrConfig;
2427  }
2428  break;
2429 #endif
2430  default:
2431  DEV_ASSERT(false);
2432  nextSysClockConfig = NULL;
2433  break;
2434  }
2435 
2436  if (status == STATUS_SUCCESS)
2437  {
2438  /* The current system clock source is FIRC.
2439  * Verify whether the next system clock source is FIRC. */
2440  if (nextSysClockConfig->src == SCG_SYSTEM_CLOCK_SRC_FIRC)
2441  {
2442  /* If they are the same, search for a temporary system clock source
2443  * (use one of the following sources: SPLL, SOSC, SIRC)
2444  * Assume that a temporary clock is not found status = ERROR. */
2445  status = STATUS_ERROR;
2446 
2447 #if FEATURE_HAS_SPLL_CLK
2448  /* SPLL is enabled */
2449  if (scgConfig->spllConfig.initialize && (status == STATUS_ERROR))
2450  {
2451  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
2452  sysClockConfig.divCore = tmpSysClk[TMP_SPLL_CLK][TMP_SYS_DIV];
2453  sysClockConfig.divBus = tmpSysClk[TMP_SPLL_CLK][TMP_BUS_DIV];
2454  sysClockConfig.divSlow = tmpSysClk[TMP_SPLL_CLK][TMP_SLOW_DIV];
2455  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2456  }
2457 #endif
2458 
2459  /* SOSC is enabled and SPLL configuration for system clock source is not valid */
2460  if (scgConfig->soscConfig.initialize && (status == STATUS_ERROR))
2461  {
2462  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_OSC;
2463  sysClockConfig.divCore = tmpSysClk[TMP_SOSC_CLK][TMP_SYS_DIV];
2464  sysClockConfig.divBus = tmpSysClk[TMP_SOSC_CLK][TMP_BUS_DIV];
2465  sysClockConfig.divSlow = tmpSysClk[TMP_SOSC_CLK][TMP_SLOW_DIV];
2466  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2467  }
2468 
2469 
2470  /* SIRC is enabled and SOSC configuration for system clock source is not valid */
2471  if (scgConfig->sircConfig.initialize && (status == STATUS_ERROR))
2472  {
2473  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SIRC;
2474  sysClockConfig.divCore = tmpSysClk[TMP_SIRC_CLK][TMP_SYS_DIV];
2475  sysClockConfig.divBus = tmpSysClk[TMP_SIRC_CLK][TMP_BUS_DIV];
2476  sysClockConfig.divSlow = tmpSysClk[TMP_SIRC_CLK][TMP_SLOW_DIV];
2477  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2478  }
2479 
2480  /* Transitioned to a temporary system clock source. */
2481  if (status == STATUS_SUCCESS)
2482  {
2483  /* Configure the remaining clock source (FIRC). */
2484  status = CLOCK_SYS_ConfigureFIRC(scgConfig->fircConfig.initialize, &scgConfig->fircConfig);
2485 
2486  if (status == STATUS_SUCCESS)
2487  {
2488  /* Transition to the next system clock source. */
2489  sysClockConfig.src = nextSysClockConfig->src;
2490  sysClockConfig.divCore = nextSysClockConfig->divCore;
2491  sysClockConfig.divBus = nextSysClockConfig->divBus;
2492  sysClockConfig.divSlow = nextSysClockConfig->divSlow;
2493  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2494  }
2495  }
2496  }
2497  else
2498  { /* Transition to the next system clock source. */
2499  sysClockConfig.src = nextSysClockConfig->src;
2500  sysClockConfig.divCore = nextSysClockConfig->divCore;
2501  sysClockConfig.divBus = nextSysClockConfig->divBus;
2502  sysClockConfig.divSlow = nextSysClockConfig->divSlow;
2503  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2504 
2505  if (status == STATUS_SUCCESS)
2506  {
2507  /* Configure the remaining clock source (FIRC) */
2508  status = CLOCK_SYS_ConfigureFIRC(scgConfig->fircConfig.initialize, &scgConfig->fircConfig);
2509  }
2510  }
2511  }
2512 
2513  return status;
2514 }
2515 
2516 /*FUNCTION**********************************************************************
2517  * Function Name : CLOCK_SYS_GetSystemClockFreq
2518  * Description : This function gets the SCG system clock frequency, these
2519  * clocks are used for core, platform, external and bus clock domains.
2520  * END**************************************************************************/
2522 {
2523  uint32_t freq;
2524 
2525 
2527 
2528  switch (SCG_GetCurrentSystemClockSource(SCG))
2529  {
2530  case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_OSC):
2531  freq = CLOCK_SYS_GetSysOscFreq();
2532  break;
2533  case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SIRC):
2534  freq = CLOCK_SYS_GetSircFreq();
2535  break;
2536  case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_FIRC):
2537  freq = CLOCK_SYS_GetFircFreq();
2538  break;
2539 #if FEATURE_HAS_SPLL_CLK
2540  case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_PLL):
2541  freq = CLOCK_SYS_GetSysPllFreq();
2542  break;
2543 #endif
2544  default:
2545  freq = 0U;
2546  break;
2547  }
2548 
2549  freq /= (SCG_GetCurrentCoreClockDividerRatio(SCG) + 1U);
2550 
2551  switch (type)
2552  {
2553  case SCG_SYSTEM_CLOCK_CORE:
2554  /* Intentionally left blank */
2555  break;
2556  case SCG_SYSTEM_CLOCK_BUS:
2557  freq /= (SCG_GetCurrentBusClockDividerRatio(SCG) + 1U);
2558  break;
2559  case SCG_SYSTEM_CLOCK_SLOW:
2560  freq /= (SCG_GetCurrentSlowClockDividerRatio(SCG) + 1U);
2561  break;
2562  default:
2563  freq = 0U;
2564  break;
2565  }
2566 
2567  return freq;
2568 }
2569 
2570 
2571 /*FUNCTION**********************************************************************
2572  * Function Name : CLOCK_SYS_SetSystemClockConfig
2573  * Description : This function sets the system configuration for the specified mode.
2574  * END**************************************************************************/
2576  scg_system_clock_config_t const * config)
2577 {
2578  status_t status = STATUS_SUCCESS;
2579  uint32_t srcFreq = 0U;
2580 
2581  /* The maximum clock frequencies of system clocks in all power modes */
2582  static const uint32_t maxSysClksInVLPR[MODES_MAX_NO][SYS_CLK_MAX_NO] = CLOCK_MAX_FREQUENCIES_VLPR_MODE;
2583  static const uint32_t maxSysClksInRUN[MODES_MAX_NO][SYS_CLK_MAX_NO] = CLOCK_MAX_FREQUENCIES_RUN_MODE;
2584 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
2585  static const uint32_t maxSysClksInHSRUN[MODES_MAX_NO][SYS_CLK_MAX_NO] = CLOCK_MAX_FREQUENCIES_HSRUN_MODE;
2586 #endif
2587  const uint32_t sysFreqMul = ((uint32_t)config->divCore) + 1UL;
2588  const uint32_t busFreqMul = (((uint32_t)config->divCore) + 1UL) * (((uint32_t)config->divBus) + 1UL);
2589  const uint32_t slowFreqMul = (((uint32_t)config->divCore) + 1UL) * (((uint32_t)config->divSlow) + 1UL);
2590 
2592 
2593  switch (config->src)
2594  {
2596  srcFreq = CLOCK_SYS_GetSysOscFreq();
2597  break;
2599  srcFreq = CLOCK_SYS_GetSircFreq();
2600  break;
2602  srcFreq = CLOCK_SYS_GetFircFreq();
2603  break;
2604 #if FEATURE_HAS_SPLL_CLK
2605  case SCG_SYSTEM_CLOCK_SRC_SYS_PLL:
2606  srcFreq = CLOCK_SYS_GetSysPllFreq();
2607  break;
2608 #endif
2609  default:
2610  srcFreq = 0U;
2611  break;
2612  }
2613 
2614  srcFreq >>= 4U;
2615 
2616  switch (mode)
2617  {
2619  /* Verify the frequencies of sys, bus and slow clocks. */
2620  if ((srcFreq > (sysFreqMul * (maxSysClksInRUN[(uint32_t)config->src][CORE_CLK_INDEX] >> 4U))) || /* Sys(core) clock */
2621  (srcFreq > (busFreqMul * (maxSysClksInRUN[(uint32_t)config->src][BUS_CLK_INDEX] >> 4U))) || /* Bus clock */
2622  (srcFreq > (slowFreqMul * (maxSysClksInRUN[(uint32_t)config->src][SLOW_CLK_INDEX] >> 4U)))) /* Slow clock */
2623  {
2624  /* Configuration for the next system clock source is not valid. */
2625  status = STATUS_ERROR;
2626  }
2627  else
2628  {
2629  SCG_SetRunClockControl(SCG, (uint32_t)config->src, (uint32_t)config->divCore, (uint32_t)config->divBus, (uint32_t)config->divSlow);
2630  }
2631  break;
2634  /* Verify the frequencies of sys, bus and slow clocks. */
2635  if ((srcFreq > (sysFreqMul * (maxSysClksInVLPR[(uint32_t)config->src][CORE_CLK_INDEX] >> 4U))) || /* Sys(core) clock */
2636  (srcFreq > (busFreqMul * (maxSysClksInVLPR[(uint32_t)config->src][BUS_CLK_INDEX] >> 4U))) || /* Bus clock */
2637  (srcFreq > (slowFreqMul * (maxSysClksInVLPR[(uint32_t)config->src][SLOW_CLK_INDEX] >> 4U)))) /* Slow clock */
2638  {
2639  /* Configuration for the next system clock source is not valid. */
2640  status = STATUS_ERROR;
2641  }
2642  else
2643  {
2644  SCG_SetVlprClockControl(SCG, (uint32_t)config->src, (uint32_t)config->divCore, (uint32_t)config->divBus, (uint32_t)config->divSlow);
2645  }
2646  break;
2647 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
2649  DEV_ASSERT((SCG_SYSTEM_CLOCK_SRC_FIRC == config->src) || ( SCG_SYSTEM_CLOCK_SRC_SYS_PLL == config->src));
2650  /* Verify the frequencies of sys, bus and slow clocks. */
2651  if ((srcFreq > (sysFreqMul * (maxSysClksInHSRUN[(uint32_t)config->src][CORE_CLK_INDEX] >> 4U))) || /* Sys(core) clock */
2652  (srcFreq > (busFreqMul * (maxSysClksInHSRUN[(uint32_t)config->src][BUS_CLK_INDEX] >> 4U))) || /* Bus clock */
2653  (srcFreq > (slowFreqMul * (maxSysClksInHSRUN[(uint32_t)config->src][SLOW_CLK_INDEX] >> 4U)))) /* Slow clock */
2654  {
2655  /* Configuration for the next system clock source is not valid. */
2656  status = STATUS_ERROR;
2657  }
2658  else
2659  {
2660  SCG_SetHsrunClockControl(SCG, (uint32_t)config->src, (uint32_t)config->divCore, (uint32_t)config->divBus, (uint32_t)config->divSlow);
2661  }
2662  break;
2663 #endif
2664  default:
2665  /* Invalid mode */
2666  DEV_ASSERT(false);
2667  break;
2668  }
2669  return status;
2670 }
2671 
2672 /*FUNCTION**********************************************************************
2673  * Function Name : CLOCK_SYS_GetSysAsyncFreq
2674  * Description : Gets SCG asynchronous clock frequency from a clock source.
2675  * END**************************************************************************/
2676 static uint32_t CLOCK_SYS_GetSysAsyncFreq(clock_names_t clockSource,
2678 {
2679  uint32_t freq, div = 0U;
2680 
2681  switch (type)
2682  {
2683  case SCG_ASYNC_CLOCK_DIV1:
2684  {
2685  switch (clockSource)
2686  {
2687  case FIRC_CLK:
2688  {
2689  freq = CLOCK_SYS_GetFircFreq();
2690  div = SCG_GetFircFirstAsyncDivider(SCG);
2691  }
2692  break;
2693  case SIRC_CLK:
2694  {
2695  freq = CLOCK_SYS_GetSircFreq();
2696  div = SCG_GetSircFirstAsyncDivider(SCG);
2697  }
2698  break;
2699  case SOSC_CLK:
2700  {
2701  freq = CLOCK_SYS_GetSysOscFreq();
2702  div = SCG_GetSoscFirstAsyncDivider(SCG);
2703  }
2704  break;
2705 #if FEATURE_HAS_SPLL_CLK
2706  case SPLL_CLK:
2707  {
2708  freq = CLOCK_SYS_GetSysPllFreq();
2709  div = SCG_GetSpllFirstAsyncDivider(SCG);
2710  }
2711  break;
2712 #endif
2713  default:
2714  {
2715  /* Invalid clock source type */
2716  freq = 0U;
2717  DEV_ASSERT(false);
2718  }
2719  break;
2720  }
2721  }
2722  break;
2723  case SCG_ASYNC_CLOCK_DIV2:
2724  {
2725  switch (clockSource)
2726  {
2727  case FIRC_CLK:
2728  {
2729  freq = CLOCK_SYS_GetFircFreq();
2730  div = SCG_GetFircSecondAsyncDivider(SCG);
2731  }
2732  break;
2733  case SIRC_CLK:
2734  {
2735  freq = CLOCK_SYS_GetSircFreq();
2736  div = SCG_GetSircSecondAsyncDivider(SCG);
2737  }
2738  break;
2739  case SOSC_CLK:
2740  {
2741  freq = CLOCK_SYS_GetSysOscFreq();
2742  div = SCG_GetSoscSecondAsyncDivider(SCG);
2743  }
2744  break;
2745 #if FEATURE_HAS_SPLL_CLK
2746  case SPLL_CLK:
2747  {
2748  freq = CLOCK_SYS_GetSysPllFreq();
2749  div = SCG_GetSpllSecondAsyncDivider(SCG);
2750  }
2751  break;
2752 #endif
2753  default:
2754  {
2755  /* Invalid clock source type */
2756  freq = 0U;
2757  DEV_ASSERT(false);
2758  }
2759  break;
2760  }
2761  }
2762  break;
2763  default:
2764  /* Invalid async clock source */
2765  freq = 0U;
2766  DEV_ASSERT(false);
2767  break;
2768  }
2769 
2770 
2771  if (div != 0U)
2772  {
2773  freq = (freq >> (div - 1U));
2774  }
2775  else /* Output disabled. */
2776  {
2777  freq = 0U;
2778  }
2779 
2780  return freq;
2781 }
2782 
2783 /*FUNCTION**********************************************************************
2784  * Function Name : CLOCK_SYS_GetSysOscFreq
2785  * Description : Gets SCG System OSC clock frequency (SYSOSC).
2786  * END**************************************************************************/
2787 static uint32_t CLOCK_SYS_GetSysOscFreq(void)
2788 {
2789  uint32_t retValue;
2790  if (SCG_GetSoscStatus(SCG)) /* System OSC clock is valid. */
2791  {
2792  retValue = g_xtal0ClkFreq;
2793  }
2794  else
2795  {
2796  retValue = 0U;
2797  }
2798 
2799  return retValue;
2800 }
2801 
2802 /*FUNCTION**********************************************************************
2803  * Function Name : CLOCK_SYS_GetSircFreq
2804  * Description : Gets SCG Slow IRC clock frequency (SIRC).
2805  * END**************************************************************************/
2806 static uint32_t CLOCK_SYS_GetSircFreq(void)
2807 {
2808  uint32_t retValue = 0U;
2809 
2810  if (SCG_GetSircStatus(SCG)) /* SIRC is valid. */
2811  {
2812  if (SCG_GetSircRange(SCG) != 0U)
2813  {
2815  }
2816  }
2817 
2818  return retValue;
2819 }
2820 
2821 /*FUNCTION**********************************************************************
2822  * Function Name : CLOCK_SYS_GetFircFreq
2823  * Description : Gets SCG Fast IRC clock frequency (FIRC).
2824  * END**************************************************************************/
2825 static uint32_t CLOCK_SYS_GetFircFreq(void)
2826 {
2827  uint32_t retValue;
2828 
2829  static const uint32_t fircFreq[] = {
2831  };
2832 
2833  if (SCG_GetFircStatus(SCG)) /* FIRC is valid. */
2834  {
2835  retValue = fircFreq[SCG_GetFircRange(SCG)];
2836  }
2837  else
2838  {
2839  retValue = 0U;
2840  }
2841 
2842  return retValue;
2843 }
2844 
2845 #if FEATURE_HAS_SPLL_CLK
2846 /*FUNCTION**********************************************************************
2847  * Function Name : CLOCK_SYS_GetSysPllFreq
2848  * Description : Gets SCG System PLL clock frequency (SYSPLL).
2849  * END**************************************************************************/
2850 static uint32_t CLOCK_SYS_GetSysPllFreq(void)
2851 {
2852  uint32_t freq, retValue;
2853 
2854  if (SCG_GetSpllStatus(SCG)) /* System PLL is valid. */
2855  {
2856  /* Get System OSC. frequency. */
2857  freq = CLOCK_SYS_GetSysOscFreq();
2858 
2859  if (freq != 0U) /* If source is valid. */
2860  {
2861  freq /= (SCG_GetSpllPredivider(SCG) + SCG_SPLL_PREDIV_BASE); /* Pre-divider. */
2862  freq *= (SCG_GetSpllMultiplier(SCG) + SCG_SPLL_MULT_BASE); /* Multiplier. */
2863  freq = freq >> 1U; /* Divide VCO by 2. */
2864  }
2865 
2866  retValue = freq;
2867  }
2868  else
2869  {
2870  retValue = 0U;
2871  }
2872 
2873  return retValue;
2874 }
2875 #endif
2876 
2877 /*FUNCTION**********************************************************************
2878  * Function Name : CLOCK_SYS_GetLpoFreq
2879  * Description : Gets SIM LPO clock frequency (LPO).
2880  * END**************************************************************************/
2881 static uint32_t CLOCK_SYS_GetLpoFreq(void)
2882 {
2883  uint32_t freq = 0U;
2884 
2885  switch (SIM_GetLpoClkSelectorValue(SIM))
2886  {
2887  case 0U: /* SIM_LPO_CLK_SEL_LPO_128K */
2888  freq = LPO_128K_FREQUENCY;
2889  break;
2890  case 1U: /* SIM_LPO_CLK_SEL_NO_CLOCK: */
2891  freq = 0U;
2892  break;
2893  case 2U: /* SIM_LPO_CLK_SEL_LPO_32K: */
2894  freq = SIM_GetLpo32KStatus(SIM) ? LPO_32K_FREQUENCY : 0UL;
2895  break;
2896  case 3U: /* SIM_LPO_CLK_SEL_LPO_1K: */
2897  freq = SIM_GetLpo32KStatus(SIM) ? LPO_32K_FREQUENCY : 0UL;
2898  break;
2899  default:
2900  /* Invalid LPOCLKSEL selection.*/
2901  DEV_ASSERT(false);
2902  break;
2903  }
2904 
2905  return freq;
2906 }
2907 
2908 /*FUNCTION**********************************************************************
2909  * Function Name : CLOCK_SYS_TransitionToTmpSysClk
2910  * Description : Transition to a temporary system clock
2911  * END**************************************************************************/
2913 {
2914  scg_system_clock_config_t sysClockConfig;
2915 
2917 
2918  status_t status = STATUS_ERROR;
2919 
2920 #if FEATURE_HAS_SPLL_CLK
2921  /* SPLL is functional, and is not the current system clock source */
2922  if ((CLOCK_SYS_GetSysPllFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_SYS_PLL) && (status == STATUS_ERROR))
2923  {
2924  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
2925  sysClockConfig.divCore = tmpSysClk[TMP_SPLL_CLK][TMP_SYS_DIV];
2926  sysClockConfig.divBus = tmpSysClk[TMP_SPLL_CLK][TMP_BUS_DIV];
2927  sysClockConfig.divSlow = tmpSysClk[TMP_SPLL_CLK][TMP_SLOW_DIV];
2928  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2929  }
2930 #endif
2931  /* FIRC is functional, it is not the current system clock source, no valid source has been found yet. */
2932  if ((CLOCK_SYS_GetFircFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_FIRC) && (status != STATUS_SUCCESS))
2933  {
2934  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_FIRC;
2935  sysClockConfig.divCore = tmpSysClk[TMP_FIRC_CLK][TMP_SYS_DIV];
2936  sysClockConfig.divBus = tmpSysClk[TMP_FIRC_CLK][TMP_BUS_DIV];
2937  sysClockConfig.divSlow = tmpSysClk[TMP_FIRC_CLK][TMP_SLOW_DIV];
2938  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2939  }
2940 
2941 
2942  /* SOSC is functional, it is not the current system clock source, no valid source has been found yet. */
2943  if ((CLOCK_SYS_GetSysOscFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_SYS_OSC) && (status != STATUS_SUCCESS))
2944  {
2945  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_OSC;
2946  sysClockConfig.divCore = tmpSysClk[TMP_SOSC_CLK][TMP_SYS_DIV];
2947  sysClockConfig.divBus = tmpSysClk[TMP_SOSC_CLK][TMP_BUS_DIV];
2948  sysClockConfig.divSlow = tmpSysClk[TMP_SOSC_CLK][TMP_SLOW_DIV];
2949  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2950  }
2951 
2952  /* SIRC is functional, it is not the current system clock source, no valid source has been found yet. */
2953  if ((CLOCK_SYS_GetSircFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_SIRC) && (status != STATUS_SUCCESS))
2954  {
2955  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SIRC;
2956  sysClockConfig.divCore = tmpSysClk[TMP_SIRC_CLK][TMP_SYS_DIV];
2957  sysClockConfig.divBus = tmpSysClk[TMP_SIRC_CLK][TMP_BUS_DIV];
2958  sysClockConfig.divSlow = tmpSysClk[TMP_SIRC_CLK][TMP_SLOW_DIV];
2959  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2960  }
2961 
2962  return status;
2963 }
2964 
2965 /*FUNCTION**********************************************************************
2966  * Function Name : CLOCK_SYS_TransitionToTmpSysClk
2967  * Description : Transition to a temporary system clock
2968  * END**************************************************************************/
2970 {
2971  static const scg_system_clock_div_t sysClkDivMappings[((uint32_t) SCG_SYSTEM_CLOCK_DIV_BY_16)+ 1U] = {
2980 
2981  /* Save the current system clock source configuration */
2982  switch(SCG_GetCurrentSystemClockSource(SCG))
2983  {
2984  case 1U:
2985  {
2986  sysClockConfig->src = SCG_SYSTEM_CLOCK_SRC_SYS_OSC;
2987  break;
2988  }
2989  case 2U:
2990  {
2991  sysClockConfig->src = SCG_SYSTEM_CLOCK_SRC_SIRC;
2992  break;
2993  }
2994  case 3U:
2995  {
2996  sysClockConfig->src = SCG_SYSTEM_CLOCK_SRC_FIRC;
2997  break;
2998  }
2999 #if FEATURE_HAS_SPLL_CLK
3000  case 6U:
3001  {
3002  sysClockConfig->src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
3003  break;
3004  }
3005 #endif
3006  default:
3007  {
3008  /* Invalid system clock value */
3009  DEV_ASSERT(false);
3010  break;
3011  }
3012  }
3013  sysClockConfig->divBus = sysClkDivMappings[SCG_GetCurrentBusClockDividerRatio(SCG)];
3014  sysClockConfig->divCore = sysClkDivMappings[SCG_GetCurrentCoreClockDividerRatio(SCG)];
3015  sysClockConfig->divSlow = sysClkDivMappings[SCG_GetCurrentSlowClockDividerRatio(SCG)];
3016 }
3017 
3018 /*FUNCTION**********************************************************************
3019  * Function Name : CLOCK_SYS_ConvertAsyncDividerValue
3020  * Description : Converts an integer value to asynchronous divider value type.
3021  * END**************************************************************************/
3023 {
3024  scg_async_clock_div_t retValue;
3025 
3026  switch(divider)
3027  {
3028  case (1U << 6U):
3029  retValue = SCG_ASYNC_CLOCK_DIV_BY_64;
3030  break;
3031  case (1U << 5U):
3032  retValue = SCG_ASYNC_CLOCK_DIV_BY_32;
3033  break;
3034  case (1U << 4U):
3035  retValue = SCG_ASYNC_CLOCK_DIV_BY_16;
3036  break;
3037  case (1U << 3U):
3038  retValue = SCG_ASYNC_CLOCK_DIV_BY_8;
3039  break;
3040  case (1U << 2U):
3041  retValue = SCG_ASYNC_CLOCK_DIV_BY_4;
3042  break;
3043  case (1U << 1U):
3044  retValue = SCG_ASYNC_CLOCK_DIV_BY_2;
3045  break;
3046  case (1U << 0U):
3047  retValue = SCG_ASYNC_CLOCK_DIV_BY_1;
3048  break;
3049  case 0U:
3050  /* Pass - through */
3051  default:
3052  retValue = SCG_ASYNC_CLOCK_DISABLE;
3053  break;
3054  }
3055  return retValue;
3056 }
3057 
3058 /*FUNCTION**********************************************************************
3059  *
3060  * Function Name : CLOCK_DRV_Init
3061  * Description : This function initializes clocking modules according to a provided
3062  * configuration.
3063  *
3064  * Implements CLOCK_DRV_Init_Activity
3065  * END**************************************************************************/
3067 {
3068  return CLOCK_SYS_SetConfiguration(config);
3069 }
3070 
3071 /*FUNCTION**********************************************************************
3072  *
3073  * Function Name : CLOCK_DRV_GetFreq
3074  * Description : This function returns the frequency according to a provided
3075  * clock.
3076  *
3077  * Implements CLOCK_DRV_GetFreq
3078  * END**************************************************************************/
3079 status_t CLOCK_DRV_GetFreq(clock_names_t clockName, uint32_t * frequency)
3080 {
3081  return CLOCK_SYS_GetFreq(clockName, frequency);
3082 }
3083 
3084 /*FUNCTION**********************************************************************
3085  *
3086  * Function Name : CLOCK_DRV_SetModuleClock
3087  * Description : This function enables a peripheral clock
3088  *
3089  * Implements CLOCK_DRV_SetModuleClock_Activity
3090  * END**************************************************************************/
3091 void CLOCK_DRV_SetModuleClock(clock_names_t clockName, const module_clk_config_t * moduleClkConfig)
3092 {
3093  uint32_t source = 0U, divider = 0U, multiplier = 0U;
3094  module_clk_config_t defaultModuleClkCfg;
3095  const module_clk_config_t * moduleClkCfg;
3096 
3097  /* Configuration is not provided, a default one will be used. */
3098  if (moduleClkConfig == NULL)
3099  {
3100  defaultModuleClkCfg.gating = true;
3101  defaultModuleClkCfg.source =
3102  (CLOCK_SYS_GetSircFreq() != 0U) ?
3103  SIRC_CLK :
3104  ((CLOCK_SYS_GetFircFreq() != 0U) ?
3105  FIRC_CLK :
3106  ((CLOCK_SYS_GetSysOscFreq() != 0U) ?
3107  SOSC_CLK :
3109  ((CLOCK_SYS_GetSysPllFreq() != 0U) ?
3110  SPLL_CLK : (CLOCK_NAME_COUNT))
3111 #else
3113 #endif
3114  ));
3115  defaultModuleClkCfg.mul = 1U;
3116  defaultModuleClkCfg.div = 1U;
3117  moduleClkCfg = &defaultModuleClkCfg;
3118  }
3119  else
3120  {
3121  moduleClkCfg = moduleClkConfig;
3122  }
3123 
3124  /* Check that clock gating is configurable from PCC */
3125  if ((peripheralFeaturesList[clockName] & HAS_CLOCK_GATING_IN_SIM) == 0U)
3126  {
3127  /* Check that protocol clock is supported by the peripheral corresponding to the clock name */
3129  {
3130  switch(moduleClkCfg->source)
3131  {
3132  case SIRC_CLK:
3133  source = CLK_SRC_SIRC;
3134  break;
3135  case FIRC_CLK:
3136  source = CLK_SRC_FIRC;
3137  break;
3138  case SOSC_CLK:
3139  source = CLK_SRC_SOSC;
3140  break;
3141 #if FEATURE_HAS_SPLL_CLK
3142  case SPLL_CLK:
3143  source = CLK_SRC_SPLL;
3144  break;
3145 #endif
3146  default:
3147  /* Invalid name of the clock source. */
3148  DEV_ASSERT(false);
3149  break;
3150  }
3151  }
3152 
3153  /* Check that divider is supported by the peripheral corresponding to the clock name */
3154  if ((peripheralFeaturesList[clockName] & HAS_DIVIDER) != 0U)
3155  {
3156  DEV_ASSERT((0U < ((uint32_t)moduleClkCfg->div)) && (((uint32_t)moduleClkCfg->div) <= (1UL << PCC_PCCn_PCD_WIDTH)));
3157  divider = ((uint32_t)moduleClkCfg->div) - 1U;
3158  }
3159 
3160  /* Check that multiplier is supported by the peripheral corresponding to the clock name */
3161  if ((peripheralFeaturesList[clockName] & HAS_MULTIPLIER) != 0U)
3162  {
3163  DEV_ASSERT((0U < ((uint32_t)moduleClkCfg->mul)) && (((uint32_t)moduleClkCfg->mul) <= (1UL << PCC_PCCn_FRAC_WIDTH)));
3164  multiplier = ((uint32_t)moduleClkCfg->mul) - 1U;
3165  }
3166 
3167  /* Disable the peripheral clock */
3168  PCC_SetClockMode(PCC, clockName, false);
3169 
3170  if (moduleClkCfg->gating)
3171  {
3172  /* Set peripheral clock control */
3173  PCC_SetPeripheralClockControl(PCC, clockName, true, source, divider, multiplier);
3174  }
3175  }
3176  else
3177  {
3178  switch (clockName)
3179  {
3180  case SIM_MSCM_CLK:
3181  SIM_SetMscmClockGate(SIM, moduleClkCfg->gating);
3182  break;
3183 
3184  case SIM_MPU_CLK:
3185  SIM_SetMpuClockGate(SIM, moduleClkCfg->gating);
3186  break;
3187 
3188  case SIM_DMA_CLK:
3189  SIM_SetDmaClockGate(SIM, moduleClkCfg->gating);
3190  break;
3191 
3192  case SIM_ERM_CLK:
3193  SIM_SetErmClockGate(SIM, moduleClkCfg->gating);
3194  break;
3195 
3196  case SIM_EIM_CLK:
3197  SIM_SetEimClockGate(SIM, moduleClkCfg->gating);
3198  break;
3199  default:
3200  /* Invalid clock name */
3201  DEV_ASSERT(false);
3202  break;
3203  }
3204  }
3205 }
3206 
3207 /*FUNCTION**********************************************************************
3208  *
3209  * Function Name : CLOCK_DRV_SetSystemClock
3210  * Description : This function configures the system clocks (core, bus and flash clocks).
3211  *
3212  * Implements CLOCK_DRV_SetSystemClock_Activity
3213  * END**************************************************************************/
3215  const sys_clk_config_t * sysClkConfig)
3216 {
3217  status_t retCode = STATUS_SUCCESS;
3218 
3219  scg_system_clock_mode_t sysClockMode, currentSysClockMode = CLOCK_SYS_GetCurrentRunMode();
3220  scg_system_clock_config_t sysClockConfig;
3221 
3224 
3225  /* The power mode is not provided, the current one will be used by default. */
3226  if (mode == NULL)
3227  {
3228  sysClockMode = currentSysClockMode;
3229  }
3230  else
3231  {
3232  switch (*mode)
3233  {
3234  /* High speed run mode */
3235  case HSRUN_MODE:
3236  sysClockMode = SCG_SYSTEM_CLOCK_MODE_HSRUN;
3237  break;
3238  /* Run mode */
3239  case RUN_MODE:
3240  sysClockMode = SCG_SYSTEM_CLOCK_MODE_RUN;
3241  break;
3242  /* Very low power run mode */
3243  case VLPR_MODE:
3244  sysClockMode = SCG_SYSTEM_CLOCK_MODE_VLPR;
3245  break;
3246  /* This should never happen - input power mode is invalid */
3247  default:
3248  sysClockMode = SCG_SYSTEM_CLOCK_MODE_NONE;
3249  DEV_ASSERT(false);
3250  break;
3251  }
3252  }
3253 
3254  /* System clock configuration is not provided, a default one will be used. */
3255  if (sysClkConfig == NULL)
3256  {
3257  /* Find a valid clock source. */
3258  if (CLOCK_SYS_GetFircFreq() != 0U)
3259  {
3260  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_FIRC;
3261  sysClockConfig.divCore = defSysClk[TMP_FIRC_CLK][TMP_SYS_DIV];
3262  sysClockConfig.divBus = defSysClk[TMP_FIRC_CLK][TMP_BUS_DIV];
3263  sysClockConfig.divSlow = defSysClk[TMP_FIRC_CLK][TMP_SLOW_DIV];
3264  }
3265 #if FEATURE_HAS_SPLL_CLK
3266  else if (CLOCK_SYS_GetSysPllFreq() != 0U)
3267  {
3268  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
3269  sysClockConfig.divCore = defSysClk[TMP_SPLL_CLK][TMP_SYS_DIV];
3270  sysClockConfig.divBus = defSysClk[TMP_SPLL_CLK][TMP_BUS_DIV];
3271  sysClockConfig.divSlow = defSysClk[TMP_SPLL_CLK][TMP_SLOW_DIV];
3272  }
3273 #endif
3274  else if (CLOCK_SYS_GetSysOscFreq() != 0U)
3275  {
3276  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_OSC;
3277  sysClockConfig.divCore = defSysClk[TMP_SOSC_CLK][TMP_SYS_DIV];
3278  sysClockConfig.divBus = defSysClk[TMP_SOSC_CLK][TMP_BUS_DIV];
3279  sysClockConfig.divSlow = defSysClk[TMP_SOSC_CLK][TMP_SLOW_DIV];
3280  }
3281  else if (CLOCK_SYS_GetSircFreq() != 0U)
3282  {
3283  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SIRC;
3284  sysClockConfig.divCore = defSysClk[TMP_SIRC_CLK][TMP_SYS_DIV];
3285  sysClockConfig.divBus = defSysClk[TMP_SIRC_CLK][TMP_BUS_DIV];
3286  sysClockConfig.divSlow = defSysClk[TMP_SIRC_CLK][TMP_SLOW_DIV];
3287  }
3288  else
3289  {
3290  /* Can't reach this point, at least one clock source is functional.
3291  * This code is written to avoid MISRA 15.7 (no 'else' at end of 'if ... else if' chain) */
3292  DEV_ASSERT(false);
3293  }
3294  }
3295  else
3296  {
3297  /* The system clock source from input configuration structure must be valid. */
3298  DEV_ASSERT((CLOCK_SYS_GetSircFreq() != 0U) || (sysClkConfig->src != SIRC_CLK));
3299  DEV_ASSERT((CLOCK_SYS_GetFircFreq() != 0U) || (sysClkConfig->src != FIRC_CLK));
3300  DEV_ASSERT((CLOCK_SYS_GetSysOscFreq() != 0U) || (sysClkConfig->src != SOSC_CLK));
3301 #if FEATURE_HAS_SPLL_CLK
3302  DEV_ASSERT((CLOCK_SYS_GetSysPllFreq() != 0U) || (sysClkConfig->src != SPLL_CLK));
3303 #endif
3304 
3305  switch(sysClkConfig->src)
3306  {
3307  case SIRC_CLK:
3308  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SIRC;
3309  break;
3310 
3311  case FIRC_CLK:
3312  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_FIRC;
3313  break;
3314 
3315  case SOSC_CLK:
3316  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_OSC;
3317  break;
3318 
3319 #if FEATURE_HAS_SPLL_CLK
3320  case SPLL_CLK:
3321  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
3322  break;
3323 #endif
3324 
3325  default:
3326  DEV_ASSERT(false);
3327  break;
3328  }
3329 
3330  DEV_ASSERT(sysClkConfig->dividers[0U] != 0U);
3331  DEV_ASSERT(sysClkConfig->dividers[1U] != 0U);
3332  DEV_ASSERT(sysClkConfig->dividers[2U] != 0U);
3333 
3334  sysClockConfig.divCore = sysClkDivMappings[sysClkConfig->dividers[0U]];
3335  sysClockConfig.divBus = sysClkDivMappings[sysClkConfig->dividers[1U]];
3336  sysClockConfig.divSlow = sysClkDivMappings[sysClkConfig->dividers[2U]];
3337  }
3338 
3339  /* System clock is configured in the current mode,
3340  * set configuration and wait until the system clock is changed. */
3341  if (sysClockMode == currentSysClockMode)
3342  {
3343  retCode = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
3344  }
3345  /* System clock is not configured in the current mode, just set configuration. */
3346  else
3347  {
3348  retCode = CLOCK_SYS_SetSystemClockConfig(sysClockMode,&sysClockConfig);
3349  }
3350  return retCode;
3351 }
3352 
3353 
3354 /*FUNCTION**********************************************************************
3355  *
3356  * Function Name : CLOCK_DRV_GetSystemClockSource
3357  * Description : This function gets the current system clock source
3358  *
3359  * Implements CLOCK_DRV_GetSystemClockSource_Activity
3360  * END**************************************************************************/
3362 {
3363  switch(SCG_GetCurrentSystemClockSource(SCG))
3364  {
3366  {
3367  sysClkConfig->src = SOSC_CLK;
3368  }
3369  break;
3371  {
3372  sysClkConfig->src = SIRC_CLK;
3373  }
3374  break;
3376  {
3377  sysClkConfig->src = FIRC_CLK;
3378  }
3379  break;
3380 #if FEATURE_HAS_SPLL_CLK
3381  case SCG_SYSTEM_CLOCK_SRC_SYS_PLL:
3382  {
3383  sysClkConfig->src = SPLL_CLK;
3384  }
3385  break;
3386 #endif
3387  default:
3388  {
3389  /* Invalid system clock source. */
3390  DEV_ASSERT(false);
3391  sysClkConfig->src = SIRC_CLK;
3392  }
3393  break;
3394  }
3395 
3396  DEV_ASSERT(SCG_GetCurrentCoreClockDividerRatio(SCG) < 16U);
3397  /* Core divider */
3398  sysClkConfig->dividers[0U] = (uint16_t) (SCG_GetCurrentCoreClockDividerRatio(SCG) + 1U);
3399 
3400  DEV_ASSERT(SCG_GetCurrentBusClockDividerRatio(SCG) < 16U);
3401  /* Bus divider */
3402  sysClkConfig->dividers[1U] = (uint16_t) (SCG_GetCurrentBusClockDividerRatio(SCG) + 1U);
3403 
3404  DEV_ASSERT(SCG_GetCurrentSlowClockDividerRatio(SCG) < 8U);
3405  /* Slow divider */
3406  sysClkConfig->dividers[2U] = (uint16_t) (SCG_GetCurrentSlowClockDividerRatio(SCG) + 1U);
3407 }
3408 
3409 /*FUNCTION**********************************************************************
3410  *
3411  * Function Name : CLOCK_DRV_SetClockSource
3412  * Description : This function configures a clock source
3413  *
3414  * Implements CLOCK_DRV_SetClockSource_Activity
3415  * END**************************************************************************/
3417 {
3418  status_t retCode = STATUS_SUCCESS;
3419  scg_sirc_config_t scgSircConfig;
3420  scg_firc_config_t scgFircConfig;
3421  scg_sosc_config_t scgSoscConfig;
3422 #if FEATURE_HAS_SPLL_CLK
3423  scg_spll_config_t scgSpllConfig;
3424 #endif
3425  bool clockSourceEnable = true;
3426  bool revertTmpSysClkTransition = false;
3427  scg_system_clock_config_t currentSysClockConfig;
3428 
3429  scg_async_clock_div_t divider1, divider2;
3430  divider1 = CLOCK_SYS_ConvertAsyncDividerValue(clkSrcConfig->outputDiv1);
3431  divider2 = CLOCK_SYS_ConvertAsyncDividerValue(clkSrcConfig->outputDiv2);
3432 
3433  /* Check whether the command enables and disables the clock source */
3434  if ((clkSrcConfig != NULL) && (clkSrcConfig->enable == false))
3435  {
3436  clockSourceEnable = false;
3437  }
3438 
3439  switch (clockName)
3440  {
3441  case SIRC_CLK:
3442 
3443  /* Check whether the current system clock source is SIRC */
3444  if (SCG_GetCurrentSystemClockSource(SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SIRC))
3445  {
3446  if (clockSourceEnable == false)
3447  {
3448  /* Can't disable SIRC, it's used as system clock source */
3449  retCode = STATUS_ERROR;
3450  }
3451  else
3452  {
3453  /* Save the current system clock source configuration */
3454  CLOCK_SYS_GetCurrentSysClkConfig(&currentSysClockConfig);
3455 
3456  /* Transition to a temporary system clock source */
3457  retCode = CLOCK_SYS_TransitionToTmpSysClk(SCG_SYSTEM_CLOCK_SRC_SIRC);
3458 
3459  revertTmpSysClkTransition = (retCode == STATUS_SUCCESS) ? true : false;
3460  }
3461  }
3462 
3463  if (retCode == STATUS_SUCCESS)
3464  {
3465  if (clkSrcConfig == NULL)
3466  {
3467  retCode = CLOCK_SYS_ConfigureSIRC(true, NULL);
3468  }
3469  else
3470  {
3471  /* Check VLP modes */
3472  scgSircConfig.enableInLowPower = true;
3473  scgSircConfig.enableInStop = true;
3474  scgSircConfig.locked = false;
3475 
3476  scgSircConfig.div1 = divider1;
3477  scgSircConfig.div2 = divider2;
3478 
3479  scgSircConfig.range = SCG_SIRC_RANGE_HIGH;
3480 
3481  retCode = CLOCK_SYS_ConfigureSIRC(clockSourceEnable, &scgSircConfig);
3482  }
3483 
3484  /* If system clock source was SIRC and SIRC has been set successfully,
3485  * then transition back to SIRC */
3486  if ((retCode == STATUS_SUCCESS) && (revertTmpSysClkTransition == true))
3487  {
3488  retCode = CLOCK_SYS_TransitionSystemClock(&currentSysClockConfig);
3489  }
3490  }
3491 
3492  break;
3493 
3494  case FIRC_CLK:
3495  /* Check whether the current system clock source is FIRC */
3496  if (SCG_GetCurrentSystemClockSource(SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_FIRC))
3497  {
3498  if (clockSourceEnable == false)
3499  {
3500  /* Can't disable FIRC, it's used as system clock source. */
3501  retCode = STATUS_ERROR;
3502  }
3503  else
3504  {
3505  /* Save the current system clock source configuration. */
3506  CLOCK_SYS_GetCurrentSysClkConfig(&currentSysClockConfig);
3507 
3508  /* Transition to a temporary system clock source. */
3509  retCode = CLOCK_SYS_TransitionToTmpSysClk(SCG_SYSTEM_CLOCK_SRC_FIRC);
3510 
3511  revertTmpSysClkTransition = (retCode == STATUS_SUCCESS) ? true : false;
3512  }
3513  }
3514 
3515  if (retCode == STATUS_SUCCESS)
3516  {
3517  if (clkSrcConfig == NULL)
3518  {
3519  retCode = CLOCK_SYS_ConfigureFIRC(clockSourceEnable, NULL);
3520  }
3521  else
3522  {
3523  scgFircConfig.locked = false;
3524 
3525  scgFircConfig.div1 = divider1;
3526  scgFircConfig.div2 = divider2;
3527 
3528  scgFircConfig.range = SCG_FIRC_RANGE_48M;
3529  scgFircConfig.regulator = 0U;
3530 
3531  retCode = CLOCK_SYS_ConfigureFIRC(clockSourceEnable, &scgFircConfig);
3532  }
3533 
3534  /* If system clock source was FIRC and FIRC has been set successfully,
3535  * then transition back to FIRC */
3536  if ((retCode == STATUS_SUCCESS) && (revertTmpSysClkTransition == true))
3537  {
3538  retCode = CLOCK_SYS_TransitionSystemClock(&currentSysClockConfig);
3539  }
3540  }
3541  break;
3542 
3543  case SOSC_CLK:
3544  /* Check whether the current system clock source is SOSC */
3545  if (SCG_GetCurrentSystemClockSource(SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_OSC))
3546  {
3547  if (clockSourceEnable == false)
3548  {
3549  /* Can't disable SOSC, it's used as system clock source. */
3550  retCode = STATUS_ERROR;
3551  }
3552  else
3553  {
3554  /* Save the current system clock source configuration. */
3555  CLOCK_SYS_GetCurrentSysClkConfig(&currentSysClockConfig);
3556 
3557  /* Transition to a temporary system clock source. */
3558  retCode = CLOCK_SYS_TransitionToTmpSysClk(SCG_SYSTEM_CLOCK_SRC_SYS_OSC);
3559 
3560  revertTmpSysClkTransition = (retCode == STATUS_SUCCESS) ? true : false;
3561  }
3562  }
3563 
3564  if (retCode == STATUS_SUCCESS)
3565  {
3566  if (clkSrcConfig == NULL)
3567  {
3568  retCode = CLOCK_SYS_ConfigureSOSC(clockSourceEnable, NULL);
3569  }
3570  else
3571  {
3572  scgSoscConfig.freq = clkSrcConfig->refFreq;
3573 
3574  scgSoscConfig.monitorMode = SCG_SOSC_MONITOR_DISABLE;
3575  scgSoscConfig.locked = false;
3576 
3577  scgSoscConfig.div1 = divider1;
3578  scgSoscConfig.div2 = divider2;
3579 
3580  switch (clkSrcConfig->refClk)
3581  {
3582  case XOSC_EXT_REF:
3583  scgSoscConfig.extRef = SCG_SOSC_REF_EXT;
3584  break;
3585 
3586  case XOSC_INT_OSC:
3587  scgSoscConfig.extRef = SCG_SOSC_REF_OSC;
3588  break;
3589 
3590  default:
3591  /* Invalid input reference value */
3592  DEV_ASSERT(false);
3593  break;
3594  }
3595 
3596  scgSoscConfig.gain = SCG_SOSC_GAIN_LOW;
3597 
3598  if((scgSoscConfig.freq >= 4000000U) && (scgSoscConfig.freq <= 8000000U))
3599  {
3600  scgSoscConfig.range = SCG_SOSC_RANGE_MID;
3601  }
3602  else if((scgSoscConfig.freq >= 8000000U) && (scgSoscConfig.freq <= 40000000U))
3603  {
3604  scgSoscConfig.range = SCG_SOSC_RANGE_HIGH;
3605  }
3606  else
3607  {
3608  /* Frequency of the input reference clock is invalid. */
3609  DEV_ASSERT(false);
3610  }
3611 
3612  retCode = CLOCK_SYS_ConfigureSOSC(clockSourceEnable, &scgSoscConfig);
3613  }
3614 
3615  /* If system clock source was SOSC and SOSC has been set successfully,
3616  * then transition back to SOSC */
3617  if ((retCode == STATUS_SUCCESS) && (revertTmpSysClkTransition == true))
3618  {
3619  retCode = CLOCK_SYS_TransitionSystemClock(&currentSysClockConfig);
3620  }
3621  }
3622  break;
3623 
3624 #if FEATURE_HAS_SPLL_CLK
3625  case SPLL_CLK:
3626  /* Check whether the current system clock source is PLL */
3627  if (SCG_GetCurrentSystemClockSource(SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_PLL))
3628  {
3629  if (clockSourceEnable == false)
3630  {
3631  /* Can't disable PLL, it's used as system clock source. */
3632  retCode = STATUS_ERROR;
3633  }
3634  else
3635  {
3636  /* Save the current system clock source configuration. */
3637  CLOCK_SYS_GetCurrentSysClkConfig(&currentSysClockConfig);
3638 
3639  /* Transition to a temporary system clock source. */
3640  retCode = CLOCK_SYS_TransitionToTmpSysClk(SCG_SYSTEM_CLOCK_SRC_SYS_PLL);
3641 
3642  revertTmpSysClkTransition = (retCode == STATUS_SUCCESS) ? true : false;
3643  }
3644  }
3645 
3646  if (retCode == STATUS_SUCCESS)
3647  {
3648  if (clkSrcConfig == NULL)
3649  {
3650  retCode = CLOCK_SYS_ConfigureSPLL(clockSourceEnable, NULL);
3651  }
3652  else
3653  {
3654  scgSpllConfig.monitorMode = SCG_SPLL_MONITOR_DISABLE;
3655  scgSpllConfig.locked = false;
3656 
3657  scgSpllConfig.div1 = divider1;
3658  scgSpllConfig.div2 = divider2;
3659 
3660  DEV_ASSERT((SCG_SPLL_PREDIV_BASE <= clkSrcConfig->div) && (clkSrcConfig->div < (SCG_SPLL_PREDIV_BASE + (1U << SCG_SPLLCFG_PREDIV_WIDTH)) ));
3661  scgSpllConfig.prediv = clkSrcConfig->div - SCG_SPLL_PREDIV_BASE;
3662 
3663  DEV_ASSERT((SCG_SPLL_MULT_BASE <= clkSrcConfig->mul) && (clkSrcConfig->mul < (SCG_SPLL_MULT_BASE + (1U << SCG_SPLLCFG_MULT_WIDTH)) ));
3664  scgSpllConfig.mult = clkSrcConfig->mul - SCG_SPLL_MULT_BASE;
3665 
3666  if (retCode == STATUS_SUCCESS)
3667  {
3668  retCode = CLOCK_SYS_ConfigureSPLL(clockSourceEnable, &scgSpllConfig);
3669  }
3670  }
3671 
3672  /* If system clock source was PLL and PLL has been set successfully,
3673  * then transition back to PLL */
3674  if ((retCode == STATUS_SUCCESS) && (revertTmpSysClkTransition == true))
3675  {
3676  retCode = CLOCK_SYS_TransitionSystemClock(&currentSysClockConfig);
3677  }
3678  }
3679  break;
3680 #endif
3681 
3682  case SIM_LPO_CLK:
3683 
3684  if (clockSourceEnable)
3685  {
3686  SIM_SetLpoClocks(SIM,true,true,SIM_LPO_CLK_SEL_LPO_128K,SIM_RTCCLK_SEL_SOSCDIV1_CLK);
3687  PMC_SetLpoMode(PMC, true);
3688  }
3689  else
3690  {
3691  PMC_SetLpoMode(PMC, false);
3692  }
3693  break;
3694 
3695  default:
3696  /* Invalid name of the clock source */
3697  DEV_ASSERT(false);
3698  break;
3699  }
3700 
3701  return retCode;
3702 }
3703 
3704 /*******************************************************************************
3705  * EOF
3706  ******************************************************************************/
PCC peripheral instance clock configuration. Implements peripheral_clock_config_t_Class.
static scg_system_clock_mode_t CLOCK_SYS_GetCurrentRunMode(void)
scg_async_clock_div_t
SCG asynchronous clock divider value.
scg_async_clock_div_t div1
#define SMC
Definition: S32K118.h:9956
scg_async_clock_div_t div2
scg_async_clock_div_t div1
sim_tclk_config_t tclkConfig
#define CLK_SRC_SOSC
static status_t CLOCK_SYS_TransitionToTmpSysClk(scg_system_clock_src_t currentSysClkSrc)
static status_t CLOCK_SYS_SetSystemClockConfig(scg_system_clock_mode_t mode, scg_system_clock_config_t const *config)
#define FIRC_STABILIZATION_TIMEOUT
#define VLPR_SPEED_RUNNING_MODE
scg_async_clock_div_t div2
scg_rtc_config_t rtcConfig
Clock source configuration. Implements clock_source_config_t_Class.
scg_async_clock_type_t
SCG asynchronous clock type. Implements scg_async_clock_type_t_Class.
#define TMP_SPLL_CLK
clock_names_t source
#define PCC_PCCn_PCD_WIDTH
Definition: S32K118.h:7917
static void CLOCK_SYS_SetPccConfiguration(const pcc_config_t *peripheralClockConfig)
status_t CLOCK_DRV_Init(clock_manager_user_config_t const *config)
Initialize clocking modules.
#define PCC_CLOCK_NAME_MAPPINGS
PCC clock name mappings Mappings between clock names and peripheral clock control indexes...
scg_system_clock_type_t
SCG system clock type. Implements scg_system_clock_type_t_Class.
SCG configure structure. Implements scg_config_t_Class.
#define SIRC_STABILIZATION_TIMEOUT
#define SIM
Definition: S32K118.h:9629
#define TMP_SOSC_CLK
scg_firc_range_t range
scg_system_clock_config_t vccrConfig
#define SPLL_STABILIZATION_TIMEOUT
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
#define TMP_SIRC_CLK
Temporary system clock source configurations. Each line represents the SYS(CORE), BUS and SLOW(FLASH)...
#define LPO_128K_FREQUENCY
#define TMP_SYS_DIV_NO
#define CLK_SRC_FIRC
#define HAS_CLOCK_GATING_IN_SIM
scg_sirc_range_t range
uint32_t rtcClkInFreq
static status_t CLOCK_SYS_SetScgConfiguration(const scg_config_t *scgConfig)
scg_spll_monitor_mode_t monitorMode
scg_async_clock_div_t div2
peripheral_clock_source_t clkSrc
SIM configure structure. Implements sim_clock_config_t_Class.
#define FEATURE_SCG_FIRC_FREQ0
#define TMP_SYSTEM_CLOCK_CONFIGS
static uint32_t CLOCK_SYS_GetPeripheralClock(clock_names_t clockName, scg_async_clock_type_t divider)
void CLOCK_DRV_SetModuleClock(clock_names_t clockName, const module_clk_config_t *moduleClkConfig)
Configures module clock.
#define HAS_INT_CLOCK_FROM_SYS_CLOCK
#define SYS_CLK_MAX_NO
The maximum number of system clock dividers and system clock divider indexes.
Definition: clock_S32K1xx.h:70
#define BUS_CLK_INDEX
Definition: clock_S32K1xx.h:72
scg_firc_config_t fircConfig
sim_clkout_div_t divider
scg_sosc_config_t soscConfig
#define PMC
Definition: S32K118.h:8167
scg_system_clock_mode_t
SCG system clock modes. Implements scg_system_clock_mode_t_Class.
#define LPO_32K_FREQUENCY
scg_sosc_ext_ref_t extRef
sim_trace_clock_config_t traceClockConfig
static uint32_t CLOCK_SYS_GetSimClkOutFreq(void)
#define HIGH_SPEED_RUNNING_MODE
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC2
#define TMP_BUS_DIV
uint32_t g_RtcClkInFreq
RTC_CLKIN clock frequency.
Definition: clock_S32K1xx.c:76
sim_rtc_clk_sel_src_t sourceRtcClk
static status_t CLOCK_SYS_ConfigureSOSC(bool enable, const scg_sosc_config_t *soscConfig)
peripheral_clock_config_t * peripheralClocks
#define DEV_ASSERT(x)
Definition: devassert.h:77
status_t CLOCK_DRV_SetSystemClock(const pwr_modes_t *mode, const sys_clk_config_t *sysClkConfig)
Configures the system clocks.
SCG system PLL configuration. Implements scg_spll_config_t_Class.
SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class.
#define CLOCK_MAX_FREQUENCIES_RUN_MODE
#define PERIPHERAL_FEATURES
Peripheral features. List of features for each clock name. If a clock name is not a peripheral...
#define FEATURE_HAS_SPLL_CLK
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
sim_plat_gate_config_t platGateConfig
static uint32_t CLOCK_SYS_GetSystemClockFreq(scg_system_clock_type_t type)
status_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const *config)
Set system clock configuration.
static status_t CLOCK_SYS_TransitionSystemClock(const scg_system_clock_config_t *to_clk)
scg_clockout_config_t clockOutConfig
#define PCC
Definition: S32K118.h:7872
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
sim_clkout_src_t source
scg_system_clock_div_t
SCG system clock divider value. Implements scg_system_clock_div_t_Class.
scg_spll_config_t spllConfig
scg_clockout_src_t source
uint32_t tclkFreq[3U]
void CLOCK_DRV_GetSystemClockSource(sys_clk_config_t *sysClkConfig)
Gets the system clock source.
scg_clock_mode_config_t clockModeConfig
#define CLK_SRC_OFF
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
scg_sirc_config_t sircConfig
scg_sosc_gain_t gain
pmc_lpo_clock_config_t lpoClockConfig
scg_async_clock_div_t div1
static status_t CLOCK_SYS_GetSimClockFreq(clock_names_t clockName, uint32_t *frequency)
#define TMP_SYS_CLK_NO
SCG system clock configuration. Implements scg_system_clock_config_t_Class.
#define SLOW_CLK_INDEX
Definition: clock_S32K1xx.h:73
#define CLOCK_PERIPHERALS_COUNT
#define HAS_INT_CLOCK_FROM_BUS_CLOCK
static scg_async_clock_div_t CLOCK_SYS_ConvertAsyncDividerValue(uint16_t divider)
#define HAS_MULTIPLIER
sim_clock_config_t simConfig
const uint16_t clockNameMappings[]
Clock name mappings Constant array storing the mappings between clock names and peripheral clock cont...
scg_system_clock_div_t divCore
module clock configuration. Implements module_clk_config_t_Class
scg_async_clock_div_t div2
#define HAS_DIVIDER
scg_system_clock_div_t divSlow
static void CLOCK_SYS_GetDefaultConfiguration(clock_manager_user_config_t *config)
uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]
Definition: clock_S32K1xx.c:73
sim_clock_out_config_t clockOutConfig
#define NUMBER_OF_TCLK_INPUTS
TClk clock frequency.
Definition: clock_S32K1xx.h:60
#define CLOCK_MAX_FREQUENCIES_VLPR_MODE
status_t CLOCK_DRV_SetClockSource(clock_names_t clockName, const clock_source_config_t *clkSrcConfig)
This function configures a clock source.
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC1
static uint32_t CLOCK_SYS_GetSircFreq(void)
#define CLK_SRC_SIRC
scg_async_clock_div_t div1
static status_t CLOCK_SYS_ConfigureFIRC(bool enable, const scg_firc_config_t *fircConfig)
static status_t CLOCK_SYS_GetPccClockFreq(clock_names_t clockName, uint32_t *frequency)
#define SCG
Definition: S32K118.h:9352
uint32_t count
scg_sosc_range_t range
sim_qspi_ref_clk_gating_t qspiRefClkGating
#define TMP_SYS_DIV
scg_sosc_monitor_mode_t monitorMode
pwr_modes_t
Power mode. Implements pwr_modes_t_Class.
peripheral_clock_divider_t divider
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
sim_lpo_clock_config_t lpoClockConfig
static status_t CLOCK_SYS_ConfigureTemporarySystemClock(void)
static void CLOCK_SYS_SetSimConfiguration(const sim_clock_config_t *simClockConfig)
static status_t CLOCK_SYS_ConfigureModulesFromScg(const scg_config_t *scgConfig)
#define TMP_SLOW_DIV
#define RUN_SPEED_RUNNING_MODE
static status_t CLOCK_SYS_GetScgClockFreq(clock_names_t clockName, uint32_t *frequency)
sim_lpoclk_sel_src_t sourceLpoClk
PMC configure structure.
uint32_t g_xtal0ClkFreq
EXTAL0 clock frequency.
Definition: clock_S32K1xx.c:79
static status_t CLOCK_SYS_ConfigureSIRC(bool enable, const scg_sirc_config_t *sircConfig)
scg_system_clock_src_t
SCG system clock source. Implements scg_system_clock_src_t_Class.
const uint8_t peripheralFeaturesList[]
Peripheral features list Constant array storing the mappings between clock names of the peripherals a...
clock_trace_src_t source
#define CLK_SRC_SIRC_DIV1
#define CLK_SRC_SPLL
#define CORE_CLK_INDEX
Definition: clock_S32K1xx.h:71
scg_system_clock_config_t rccrConfig
static uint32_t CLOCK_SYS_GetScgClkOutFreq(void)
clock_names_t src
clock_names_t
Clock names.
scg_system_clock_src_t src
status_t CLOCK_DRV_GetFreq(clock_names_t clockName, uint32_t *frequency)
Return frequency.
static uint32_t CLOCK_SYS_GetSysAsyncFreq(clock_names_t clockSource, scg_async_clock_type_t type)
Clock configuration structure. Implements clock_manager_user_config_t_Class.
static uint32_t CLOCK_SYS_GetSysOscFreq(void)
peripheral_clock_frac_t frac
#define SOSC_STABILIZATION_TIMEOUT
#define MODES_MAX_NO
static void CLOCK_SYS_SetPmcConfiguration(const pmc_config_t *pmcConfig)
static uint32_t CLOCK_SYS_GetLpoFreq(void)
#define PCC_PCCn_FRAC_WIDTH
Definition: S32K118.h:7921
static uint32_t CLOCK_SYS_GetFircFreq(void)
static uint32_t CLOCK_SYS_GetSimRtcClkFreq(void)
#define HAS_INT_CLOCK_FROM_SLOW_CLOCK
scg_system_clock_config_t hccrConfig
#define LPO_1K_FREQUENCY
uint16_t dividers[3U]
static void CLOCK_SYS_GetCurrentSysClkConfig(scg_system_clock_config_t *sysClockConfig)
scg_system_clock_div_t divBus
#define TMP_FIRC_CLK
System clock configuration. Implements sys_clk_config_t_Class.
PCC configuration. Implements pcc_config_t_Class.