edma_irq.c
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1 /*
2  * Copyright (c) 2013 - 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016 - 2018 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
45 #include "edma_irq.h"
46 
47 /*******************************************************************************
48  * Variables
49  ******************************************************************************/
50 
51 /*******************************************************************************
52  * Code
53  ******************************************************************************/
54 
55 #ifdef FEATURE_DMA_HWV3
56 
58 void DMA0_Ch0_Ch15_IRQHandler(void)
59 {
60  uint8_t index = 0U;
61  uint8_t virtualChannel = 0U;
62  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(0U);
63  /* Check all the flags and call the handler for the appropriate channel */
64  for(virtualChannel = 0U; virtualChannel <= 15U; virtualChannel++)
65  {
66  if ((edmaRegBase->TCD[index].CH_INT & DMA_TCD_CH_INT_INT_MASK) == DMA_TCD_CH_INT_INT_MASK)
67  {
68  EDMA_DRV_IRQHandler(virtualChannel);
69  }
70  index++;
71  }
72 }
73 
75 void DMA0_Ch16_Ch31_IRQHandler(void)
76 {
77  uint8_t index = 0U;
78  uint8_t virtualChannel = 16U;
79  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(0U);
80  /* Check all the flags and call the handler for the appropriate channel */
81  for(virtualChannel = 16U; virtualChannel <= 31U; virtualChannel++)
82  {
83  if ((edmaRegBase->TCD[index].CH_INT & DMA_TCD_CH_INT_INT_MASK) == DMA_TCD_CH_INT_INT_MASK)
84  {
85  EDMA_DRV_IRQHandler(virtualChannel);
86  }
87  index++;
88  }
89 }
90 
92 void DMA1_Ch0_Ch15_IRQHandler(void)
93 {
94  uint8_t index = 0U;
95  uint8_t virtualChannel = 32U;
96  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(1U);
97  /* Check all the flags and call the handler for the appropriate channel */
98  for(virtualChannel = 32U; virtualChannel <= 47U; virtualChannel++)
99  {
100  if ((edmaRegBase->TCD[index].CH_INT & DMA_TCD_CH_INT_INT_MASK) == DMA_TCD_CH_INT_INT_MASK)
101  {
102  EDMA_DRV_IRQHandler(virtualChannel);
103  }
104  index++;
105  }
106 }
107 
109 void DMA1_Ch16_Ch31_IRQHandler(void)
110 {
111  uint8_t index = 0U;
112  uint8_t virtualChannel = 48U;
113  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(1U);
114  /* Check all the flags and call the handler for the appropriate channel */
115  for(virtualChannel = 48U; virtualChannel <= 63U; virtualChannel++)
116  {
117  if ((edmaRegBase->TCD[index].CH_INT & DMA_TCD_CH_INT_INT_MASK) == DMA_TCD_CH_INT_INT_MASK)
118  {
119  EDMA_DRV_IRQHandler(virtualChannel);
120  }
121  index++;
122  }
123 }
124 
125 #ifdef FEATURE_DMA_HAS_ERROR_IRQ
126 
127 void DMA0_Error_IRQHandler(void)
128 {
129  uint8_t index = 0U;
130  uint8_t virtualChannel = 0U;
131  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(0U);
132  /* Check all the flags and call the handler for the appropriate channel */
133  for(virtualChannel = 0U; virtualChannel <= 31U; virtualChannel++)
134  {
135  if ((edmaRegBase->TCD[index].CH_ES & DMA_TCD_CH_ES_ERR_MASK) == DMA_TCD_CH_ES_ERR_MASK)
136  {
137  EDMA_DRV_ErrorIRQHandler(virtualChannel);
138  }
139  index++;
140  }
141 }
142 
144 void DMA1_Error_IRQHandler(void)
145 {
146  uint8_t index = 0U;
147  uint8_t virtualChannel = 32U;
148  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(1U);
149  /* Check all the flags and call the handler for the appropriate channel */
150  for(virtualChannel = 32U; virtualChannel <= 63U; virtualChannel++)
151  {
152  if ((edmaRegBase->TCD[index].CH_ES & DMA_TCD_CH_ES_ERR_MASK) == DMA_TCD_CH_ES_ERR_MASK)
153  {
154  EDMA_DRV_ErrorIRQHandler(virtualChannel);
155  }
156  index++;
157  }
158 }
159 #endif
160 
161 #else
162 
163 #ifdef FEATURE_DMA_ORED_IRQ_LINES_16_CHN
164 
165 void DMA0_15_IRQHandler(void)
166 {
167  /* Read the status flags register */
168  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(0U);
169  uint32_t mask = 0xFFFF;
170  uint32_t flags = edmaRegBase->INT;
171  uint8_t virtualChannel = 0U;
172  flags &= mask;
173  /* Check all the flags from 0 to 15 and call the handler for the appropriate channel */
174  while (flags > 0U)
175  {
176  if ((flags & 1U) > 0U)
177  {
178  EDMA_DRV_IRQHandler(virtualChannel);
179  }
180  virtualChannel++;
181  flags >>= 1U;
182  }
183 }
184 
186 void DMA16_31_IRQHandler(void)
187 {
188  /* Read the status flags register */
189  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(0U);
190  uint32_t flags = edmaRegBase->INT;
191  uint8_t virtualChannel = 16U;
192  flags >>= 16U;
193  /* Check all the flags from 16 to 31 and call the handler for the appropriate channel */
194  while (flags > 0U)
195  {
196  if ((flags & 1U) > 0U)
197  {
198  EDMA_DRV_IRQHandler(virtualChannel);
199  }
200  virtualChannel++;
201  flags >>= 1U;
202  }
203 }
204 #endif
205 
206 #ifdef FEATURE_DMA_SEPARATE_IRQ_LINES_PER_CHN
207 
208 void DMA0_IRQHandler(void)
209 {
211 }
212 
214 void DMA1_IRQHandler(void)
215 {
217 }
218 
220 void DMA2_IRQHandler(void)
221 {
223 }
224 
226 void DMA3_IRQHandler(void)
227 {
229 }
230 
232 void DMA4_IRQHandler(void)
233 {
235 }
236 
238 void DMA5_IRQHandler(void)
239 {
241 }
242 
244 void DMA6_IRQHandler(void)
245 {
247 }
248 
250 void DMA7_IRQHandler(void)
251 {
253 }
254 
256 void DMA8_IRQHandler(void)
257 {
259 }
260 
262 void DMA9_IRQHandler(void)
263 {
265 }
266 
268 void DMA10_IRQHandler(void)
269 {
270  EDMA_DRV_IRQHandler(10U);
271 }
272 
274 void DMA11_IRQHandler(void)
275 {
276  EDMA_DRV_IRQHandler(11U);
277 }
278 
280 void DMA12_IRQHandler(void)
281 {
282  EDMA_DRV_IRQHandler(12U);
283 }
284 
286 void DMA13_IRQHandler(void)
287 {
288  EDMA_DRV_IRQHandler(13U);
289 }
290 
292 void DMA14_IRQHandler(void)
293 {
294  EDMA_DRV_IRQHandler(14U);
295 }
296 
298 void DMA15_IRQHandler(void)
299 {
300  EDMA_DRV_IRQHandler(15U);
301 }
302 #if (FEATURE_DMA_CHANNELS > 16U)
303 void DMA16_IRQHandler(void)
304 {
305  EDMA_DRV_IRQHandler(16U);
306 }
307 
309 void DMA17_IRQHandler(void)
310 {
311  EDMA_DRV_IRQHandler(17U);
312 }
313 
315 void DMA18_IRQHandler(void)
316 {
317  EDMA_DRV_IRQHandler(18U);
318 }
319 
321 void DMA19_IRQHandler(void)
322 {
323  EDMA_DRV_IRQHandler(19U);
324 }
325 
327 void DMA20_IRQHandler(void)
328 {
329  EDMA_DRV_IRQHandler(20U);
330 }
331 
333 void DMA21_IRQHandler(void)
334 {
335  EDMA_DRV_IRQHandler(21U);
336 }
337 
339 void DMA22_IRQHandler(void)
340 {
341  EDMA_DRV_IRQHandler(22U);
342 }
343 
345 void DMA23_IRQHandler(void)
346 {
347  EDMA_DRV_IRQHandler(23U);
348 }
349 
351 void DMA24_IRQHandler(void)
352 {
353  EDMA_DRV_IRQHandler(24U);
354 }
355 
357 void DMA25_IRQHandler(void)
358 {
359  EDMA_DRV_IRQHandler(25U);
360 }
361 
363 void DMA26_IRQHandler(void)
364 {
365  EDMA_DRV_IRQHandler(26U);
366 }
367 
369 void DMA27_IRQHandler(void)
370 {
371  EDMA_DRV_IRQHandler(27U);
372 }
373 
375 void DMA28_IRQHandler(void)
376 {
377  EDMA_DRV_IRQHandler(28U);
378 }
379 
381 void DMA29_IRQHandler(void)
382 {
383  EDMA_DRV_IRQHandler(29U);
384 }
385 
387 void DMA30_IRQHandler(void)
388 {
389  EDMA_DRV_IRQHandler(30U);
390 }
391 
393 void DMA31_IRQHandler(void)
394 {
395  EDMA_DRV_IRQHandler(31U);
396 }
397 #endif
398 #endif
399 
400 #ifdef FEATURE_DMA_HAS_ERROR_IRQ
401 
402 void DMA_Error_IRQHandler(void)
403 {
404  const DMA_Type * edmaRegBase = EDMA_DRV_GetDmaRegBaseAddr(0U);
405  uint32_t error = EDMA_GetErrorIntStatusFlag(edmaRegBase);
406  uint8_t virtualChannel = 0U;
407 
408  for (virtualChannel = 0U;
409  virtualChannel < FEATURE_DMA_VIRTUAL_CHANNELS;
410  virtualChannel++)
411  {
412  if((error & EDMA_ERR_LSB_MASK) != 0UL)
413  {
414  EDMA_DRV_ErrorIRQHandler(virtualChannel);
415  }
416  error = error >> 1U;
417  }
418 }
419 #endif
420 
421 #endif
422 
423 /*******************************************************************************
424  * EOF
425  ******************************************************************************/
426 
volatile uint32_t INT
Definition: S32K118.h:2228
struct DMA_Type::@6 TCD[4u]
#define EDMA_ERR_LSB_MASK
Macro for accessing the least significant bit of the ERR register.
Definition: edma_driver.h:68
DMA_Type * EDMA_DRV_GetDmaRegBaseAddr(uint32_t instance)
Definition: edma_driver.c:1731
void EDMA_DRV_IRQHandler(uint8_t virtualChannel)
DMA channel interrupt handler, implemented in driver c file.
Definition: edma_driver.c:503
void EDMA_DRV_ErrorIRQHandler(uint8_t virtualChannel)
Definition: edma_driver.c:523
#define FEATURE_DMA_VIRTUAL_CHANNELS