ftm_common.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
48 #ifndef FTM_COMMON_H
49 #define FTM_COMMON_H
50 
51 
52 #include <stddef.h>
53 #include "status.h"
54 #include "device_registers.h"
55 #include "callbacks.h"
56 
62 /*******************************************************************************
63  * Variables
64  ******************************************************************************/
66 extern FTM_Type * const g_ftmBase[FTM_INSTANCE_COUNT];
67 
73 
74 #ifdef ERRATA_E10856
75 extern bool faultDetection;
76 #endif
77 
78 /*******************************************************************************
79  * Definitions
80  ******************************************************************************/
81 
85 #define FTM_RMW_SC(base, mask, value) (((base)->SC) = ((((base)->SC) & ~(mask)) | (value)))
86 
90 #define FTM_RMW_CNT(base, mask, value) (((base)->CNT) = ((((base)->CNT) & ~(mask)) | (value)))
91 
95 #define FTM_RMW_MOD(base, mask, value) (((base)->MOD) = ((((base)->MOD) & ~(mask)) | (value)))
96 
100 #define FTM_RMW_CNTIN(base, mask, value) (((base)->CNTIN) = ((((base)->CNTIN) & ~(mask)) | (value)))
101 
105 #define FTM_RMW_STATUS(base, mask, value) (((base)->STATUS) = ((((base)->STATUS) & ~(mask)) | (value)))
106 
110 #define FTM_RMW_MODE(base, mask, value) (((base)->MODE) = ((((base)->MODE) & ~(mask)) | (value)))
111 
115 #define FTM_RMW_CnSCV_REG(base, channel, mask, value) (((base)->CONTROLS[channel].CnSC) = ((((base)->CONTROLS[channel].CnSC) & ~(mask)) | (value)))
116 
120 #define FTM_RMW_DEADTIME(base, mask, value) (((base)->DEADTIME) = ((((base)->DEADTIME) & ~(mask)) | (value)))
121 
124 #define FTM_RMW_EXTTRIG_REG(base, mask, value) (((base)->EXTTRIG) = ((((base)->EXTTRIG) & ~(mask)) | (value)))
125 
129 #define FTM_RMW_FLTCTRL(base, mask, value) (((base)->FLTCTRL) = ((((base)->FLTCTRL) & ~(mask)) | (value)))
130 
134 #define FTM_RMW_FMS(base, mask, value) (((base)->FMS) = ((((base)->FMS) & ~(mask)) | (value)))
135 
139 #define FTM_RMW_CONF(base, mask, value) (((base)->CONF) = ((((base)->CONF) & ~(mask)) | (value)))
140 
144 #define FTM_RMW_POL(base, mask, value) (((base)->POL) = ((((base)->POL) & ~(mask)) | (value)))
145 
149 #define FTM_RMW_FILTER(base, mask, value) (((base)->FILTER) = ((((base)->FILTER) & ~(mask)) | (value)))
150 
154 #define FTM_RMW_SYNC(base, mask, value) (((base)->SYNC) = ((((base)->SYNC) & ~(mask)) | (value)))
155 
159 #define FTM_RMW_QDCTRL(base, mask, value) (((base)->QDCTRL) = ((((base)->QDCTRL) & ~(mask)) | (value)))
160 
164 #define FTM_RMW_PAIR0DEADTIME(base, mask, value) (((base)->PAIR0DEADTIME) = ((((base)->PAIR0DEADTIME) & ~(mask)) | (value)))
165 
169 #define FTM_RMW_PAIR1DEADTIME(base, mask, value) (((base)->PAIR1DEADTIME) = ((((base)->PAIR1DEADTIME) & ~(mask)) | (value)))
170 
174 #define FTM_RMW_PAIR2DEADTIME(base, mask, value) (((base)->PAIR2DEADTIME) = ((((base)->PAIR2DEADTIME) & ~(mask)) | (value)))
175 
179 #define FTM_RMW_PAIR3DEADTIME(base, mask, value) (((base)->PAIR3DEADTIME) = ((((base)->PAIR3DEADTIME) & ~(mask)) | (value)))
180 
181 #if FEATURE_FTM_HAS_SUPPORTED_DITHERING
182 
185 #define FTM_RMW_MOD_MIRROR(base, mask, value) (((base)->MOD_MIRROR) = ((((base)->MOD_MIRROR) & ~(mask)) | (value)))
186 
190 #define FTM_RMW_CnV_MIRROR(base, channel, mask, value) (((base)->CV_MIRROR[channel]) = ((((base)->CV_MIRROR[channel]) & ~(mask)) | (value)))
191 #endif
192 
194 #define CHAN0_IDX (0U)
195 
196 #define CHAN1_IDX (1U)
198 #define CHAN2_IDX (2U)
200 #define CHAN3_IDX (3U)
202 #define CHAN4_IDX (4U)
204 #define CHAN5_IDX (5U)
206 #define CHAN6_IDX (6U)
208 #define CHAN7_IDX (7U)
210 /*******************************************************************************
211  * Enumerations
212  ******************************************************************************/
218 typedef enum
219 {
220  FTM_MODE_NOT_INITIALIZED = 0x00U,
222  FTM_MODE_OUTPUT_COMPARE = 0x02U,
235 typedef enum
236 {
237  FTM_CLOCK_SOURCE_NONE = 0x00U,
239  FTM_CLOCK_SOURCE_FIXEDCLK = 0x02U,
249 typedef enum
250 {
251  FTM_CLOCK_DIVID_BY_1 = 0x00U,
253  FTM_CLOCK_DIVID_BY_4 = 0x02U,
266 typedef enum
267 {
268  FTM_CHANNEL0_INT_ENABLE = 0x00000001U,
269  FTM_CHANNEL1_INT_ENABLE = 0x00000002U,
270  FTM_CHANNEL2_INT_ENABLE = 0x00000004U,
271  FTM_CHANNEL3_INT_ENABLE = 0x00000008U,
272  FTM_CHANNEL4_INT_ENABLE = 0x00000010U,
273  FTM_CHANNEL5_INT_ENABLE = 0x00000020U,
274  FTM_CHANNEL6_INT_ENABLE = 0x00000040U,
275  FTM_CHANNEL7_INT_ENABLE = 0x00000080U,
276  FTM_FAULT_INT_ENABLE = 0x00000100U,
278  FTM_RELOAD_INT_ENABLE = 0x00000400U
286 typedef enum
287 {
288  FTM_CHANNEL0_FLAG = 0x00000001U,
289  FTM_CHANNEL1_FLAG = 0x00000002U,
290  FTM_CHANNEL2_FLAG = 0x00000004U,
291  FTM_CHANNEL3_FLAG = 0x00000008U,
292  FTM_CHANNEL4_FLAG = 0x00000010U,
293  FTM_CHANNEL5_FLAG = 0x00000020U,
294  FTM_CHANNEL6_FLAG = 0x00000040U,
295  FTM_CHANNEL7_FLAG = 0x00000080U,
296  FTM_FAULT_FLAG = 0x00000100U,
297  FTM_TIME_OVER_FLOW_FLAG = 0x00000200U,
298  FTM_RELOAD_FLAG = 0x00000400U,
307 typedef enum
308 {
309  FTM_SYSTEM_CLOCK = 0U,
311  FTM_PWM_SYNC = 1U
320 typedef enum
321 {
331 typedef enum
332 {
333  FTM_DEADTIME_DIVID_BY_1 = 0x01U,
335  FTM_DEADTIME_DIVID_BY_16 = 0x03U
343 typedef enum
344 {
345  FTM_QUAD_PHASE_ENCODE = 0x00U,
354 typedef enum
355 {
356  FTM_QUAD_PHASE_NORMAL = 0x00U,
358  FTM_QUAD_PHASE_INVERT = 0x01U
367 typedef enum
368 {
369  FTM_BDM_MODE_00 = 0x00U,
372  FTM_BDM_MODE_01 = 0x01U,
375  FTM_BDM_MODE_10 = 0x02U,
382 
388 typedef struct
389 {
390  ftm_clock_source_t ftmClockSource;
392  uint16_t ftmPeriod;
393  uint32_t ftmSourceClockFrequency;
394  uint16_t measurementResults[FEATURE_FTM_CHANNEL_COUNT];
395  void * channelsCallbacksParams[FEATURE_FTM_CHANNEL_COUNT];
397  bool enableNotification[FEATURE_FTM_CHANNEL_COUNT];
405 typedef struct
406 {
407  bool softwareSync;
409  bool hardwareSync0;
411  bool hardwareSync1;
413  bool hardwareSync2;
415  bool maxLoadingPoint;
417  bool minLoadingPoint;
419  ftm_reg_update_t inverterSync;
420  ftm_reg_update_t outRegSync;
421  ftm_reg_update_t maskRegSync;
422  ftm_reg_update_t initCounterSync;
423  bool autoClearTrigger;
433 typedef struct
434 {
435  ftm_pwm_sync_t syncMethod;
437  ftm_config_mode_t ftmMode;
438  ftm_clock_ps_t ftmPrescaler;
440  ftm_clock_source_t ftmClockSource;
441  ftm_bdm_mode_t BDMMode;
442  bool isTofIsrEnabled;
444  bool enableInitializationTrigger;
448 /*******************************************************************************
449  * Variables
450  ******************************************************************************/
453 
454 /*******************************************************************************
455  * API
456  ******************************************************************************/
457 
458 #if defined(__cplusplus)
459 extern "C" {
460 #endif
461 
470 static inline void FTM_DRV_SetClockFilterPs(FTM_Type * const ftmBase,
471  uint8_t filterPrescale)
472 {
473  FTM_RMW_SC(ftmBase, FTM_SC_FLTPS_MASK, FTM_SC_FLTPS(filterPrescale));
474 }
475 
485 static inline uint8_t FTM_DRV_GetClockFilterPs(const FTM_Type * ftmBase)
486 {
487  return (uint8_t)((((ftmBase)->SC) & FTM_SC_FLTPS_MASK) >> FTM_SC_FLTPS_SHIFT);
488 }
489 
499 static inline uint16_t FTM_DRV_GetCounter(const FTM_Type * ftmBase)
500 {
501  return (uint16_t)((((ftmBase)->CNT) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT);
502 }
503 
513 static inline uint16_t FTM_DRV_GetMod(const FTM_Type * ftmBase)
514 {
515  return (uint16_t)((((ftmBase)->MOD) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT);
516 }
517 
527 static inline uint16_t FTM_DRV_GetCounterInitVal(const FTM_Type * ftmBase)
528 {
529  return (uint16_t)((((ftmBase)->CNTIN) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT);
530 }
531 
540 static inline void FTM_DRV_ClearChSC(FTM_Type * const ftmBase,
541  uint8_t channel)
542 {
544 
545  ((ftmBase)->CONTROLS[channel].CnSC) = 0U;
546 #ifdef ERRATA_E9005
547  /* Read-after-write sequence to guarantee required serialization of memory operations */
548  ftmBase->CONTROLS[channel].CnSC;
549 #endif
550 }
551 
562 static inline uint8_t FTM_DRV_GetChnEdgeLevel(const FTM_Type * ftmBase,
563  uint8_t channel)
564 {
566  uint8_t retValue;
567 
568  retValue = (uint8_t)((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT);
569 
570  retValue |= (uint8_t)(((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT) << 1U);
571 
572  return retValue;
573 }
574 
586 static inline void FTM_DRV_SetChnIcrstCmd(FTM_Type * const ftmBase,
587  uint8_t channel,
588  bool enable)
589 {
591 
592  /* Write ICRST bit */
593  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_ICRST_MASK, FTM_CnSC_ICRST(enable));
594 }
595 
607 static inline bool FTM_DRV_IsChnIcrst(const FTM_Type * ftmBase,
608  uint8_t channel)
609 {
611 
612  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ICRST_MASK) != 0U;
613 }
614 
626 static inline void FTM_DRV_SetChnDmaCmd(FTM_Type * const ftmBase,
627  uint8_t channel,
628  bool enable)
629 {
631 
632  /* Write DMA bit */
633  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(enable));
634 }
635 
647 static inline bool FTM_DRV_IsChnDma(const FTM_Type * ftmBase,
648  uint8_t channel)
649 {
651 
652  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_DMA_MASK) != 0U;
653 }
654 
666 static inline void FTM_DRV_SetTrigModeControlCmd(FTM_Type * const ftmBase,
667  uint8_t channel,
668  bool enable)
669 {
671 
672  /* Write TRIGMODE bit */
673  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_TRIGMODE_MASK, FTM_CnSC_TRIGMODE((enable)));
674 }
675 
687 static inline bool FTM_DRV_GetTriggerControled(const FTM_Type * ftmBase,
688  uint8_t channel)
689 {
691 
692  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_TRIGMODE_MASK) != 0U;
693 }
694 
706 static inline bool FTM_DRV_GetChInputState(const FTM_Type * ftmBase,
707  uint8_t channel)
708 {
710 
711  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHIS_MASK) != 0U;
712 }
713 
725 static inline bool FTM_DRV_GetChOutputValue(const FTM_Type * ftmBase,
726  uint8_t channel)
727 {
729 
730  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHOV_MASK) != 0U;
731 }
732 
743 static inline uint16_t FTM_DRV_GetChnCountVal(const FTM_Type * ftmBase,
744  uint8_t channel)
745 {
747 
748  return (uint16_t)((ftmBase)->CONTROLS[channel].CnV);
749 }
750 
763 static inline bool FTM_DRV_GetChnEventStatus(const FTM_Type * ftmBase,
764  uint8_t channel)
765 {
767 
768  return (((ftmBase)->STATUS) & (1UL << channel)) != 0U;
769 }
770 
780 static inline uint32_t FTM_DRV_GetEventStatus(const FTM_Type * ftmBase)
781 {
782  return ((ftmBase)->STATUS) & (0xFFU);
783 }
784 
793 static inline void FTM_DRV_ClearChnEventStatus(FTM_Type * const ftmBase,
794  uint8_t channel)
795 {
797 
798  ((ftmBase)->STATUS) &= (~(1UL << channel));
799 #ifdef ERRATA_E9005
800  /* Read-after-write sequence to guarantee required serialization of memory operations */
801  ftmBase->STATUS;
802 #endif
803 }
804 
816 static inline void FTM_DRV_SetChnOutputMask(FTM_Type * const ftmBase,
817  uint8_t channel,
818  bool mask)
819 {
821 
822  if (mask)
823  {
824  ((ftmBase)->OUTMASK) |= (1UL << channel);
825  }
826  else
827  {
828  ((ftmBase)->OUTMASK) &= ~(1UL << channel);
829  }
830 }
831 
843 static inline void FTM_DRV_SetChnOutputInitStateCmd(FTM_Type * const ftmBase,
844  uint8_t channel,
845  bool state)
846 {
848 
849  if (state)
850  {
851  ((ftmBase)->OUTINIT) |= (1UL << channel);
852  }
853  else
854  {
855  ((ftmBase)->OUTINIT) &= ~(1UL << channel);
856  }
857 }
858 
866 static inline void FTM_DRV_DisableFaultInt(FTM_Type * const ftmBase)
867 {
869 }
870 
881 static inline void FTM_DRV_SetCaptureTestCmd(FTM_Type * const ftmBase,
882  bool enable)
883 {
885 }
886 
897 static inline bool FTM_DRV_IsFtmEnable(const FTM_Type * ftmBase)
898 {
899  return ((ftmBase->MODE & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT) != 0U;
900 }
901 
913 static inline void FTM_DRV_SetCountReinitSyncCmd(FTM_Type * const ftmBase,
914  bool enable)
915 {
917 }
918 
930 static inline bool FTM_DRV_IsWriteProtectionEnabled(const FTM_Type * ftmBase)
931 {
932  return (ftmBase->FMS & FTM_FMS_WPEN_MASK) != 0U;
933 }
934 
946 static inline bool FTM_DRV_IsFaultInputEnabled(const FTM_Type * ftmBase)
947 {
948  return (ftmBase->FMS & FTM_FMS_FAULTIN_MASK) != 0U;
949 }
950 
963 static inline bool FTM_DRV_IsFaultFlagDetected(const FTM_Type * ftmBase,
964  uint8_t channel)
965 {
966  DEV_ASSERT(channel < CHAN4_IDX);
967 
968  return (ftmBase->FMS & (FTM_FMS_FAULTF0_MASK << channel)) != 0U;
969 }
970 
979 static inline void FTM_DRV_ClearFaultFlagDetected(FTM_Type * const ftmBase,
980  uint8_t channel)
981 {
982  DEV_ASSERT(channel < CHAN4_IDX);
983 
984  ((ftmBase)->FMS) &= (~(1UL << channel));
985 #ifdef ERRATA_E9005
986  /* Read-after-write sequence to guarantee required serialization of memory operations */
987  ftmBase->FMS;
988 #endif
989 }
990 
1002 static inline void FTM_DRV_SetDualChnInvertCmd(FTM_Type * const ftmBase,
1003  uint8_t chnlPairNum,
1004  bool enable)
1006  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1007 
1008  if (enable)
1009  {
1010  ((ftmBase)->INVCTRL) |= (1UL << chnlPairNum);
1011  }
1012  else
1013  {
1014  ((ftmBase)->INVCTRL) &= ~(1UL << chnlPairNum);
1015  }
1016 }
1017 
1018 /*FTM software output control*/
1029 static inline void FTM_DRV_SetChnSoftwareCtrlCmd(FTM_Type * const ftmBase,
1030  uint8_t channel,
1031  bool enable)
1034 
1035  if (enable)
1036  {
1037  ((ftmBase)->SWOCTRL) |= (1UL << channel);
1038  }
1039  else
1040  {
1041  ((ftmBase)->SWOCTRL) &= ~(1UL << channel);
1042  }
1043 }
1044 
1056 static inline void FTM_DRV_SetChnSoftwareCtrlVal(FTM_Type * const ftmBase,
1057  uint8_t channel,
1058  bool enable)
1061 
1062  if (enable)
1063  {
1064  ((ftmBase)->SWOCTRL) |= (1UL << (channel + FTM_SWOCTRL_CH0OCV_SHIFT));
1065  }
1066  else
1067  {
1068  ((ftmBase)->SWOCTRL) &= ~(1UL << (channel + FTM_SWOCTRL_CH0OCV_SHIFT));
1069  }
1070 }
1071 
1072 /*FTM PWM load control*/
1082 static inline void FTM_DRV_SetGlobalLoadCmd(FTM_Type * const ftmBase)
1083 {
1084  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_GLDOK_SHIFT);
1086 
1097 static inline void FTM_DRV_SetLoadCmd(FTM_Type * const ftmBase,
1098  bool enable)
1099 {
1100  if (enable)
1101  {
1102  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_GLEN_SHIFT);
1103  }
1104  else
1105  {
1106  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_GLEN_SHIFT);
1107  }
1108 }
1109 
1120 static inline void FTM_DRV_SetHalfCycleCmd(FTM_Type * const ftmBase,
1121  bool enable)
1122 {
1123  if (enable)
1124  {
1125  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_HCSEL_SHIFT);
1126  }
1127  else
1128  {
1129  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_HCSEL_SHIFT);
1130  }
1131 }
1132 
1143 static inline void FTM_DRV_SetPwmLoadCmd(FTM_Type * const ftmBase,
1144  bool enable)
1145 {
1146  if (enable)
1147  {
1148  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_LDOK_SHIFT);
1149  }
1150  else
1151  {
1152  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_LDOK_SHIFT);
1153  }
1154 }
1155 
1167 static inline void FTM_DRV_SetPwmLoadChnSelCmd(FTM_Type * const ftmBase,
1168  uint8_t channel,
1169  bool enable)
1172 
1173  if (enable)
1174  {
1175  ((ftmBase)->PWMLOAD) |= (1UL << channel);
1176  }
1177  else
1178  {
1179  ((ftmBase)->PWMLOAD) &= ~(1UL << channel);
1180  }
1181 }
1182 
1183 /*FTM configuration*/
1194 static inline void FTM_DRV_SetInitTrigOnReloadCmd(FTM_Type * const ftmBase,
1195  bool enable)
1196 {
1197  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_ITRIGR_MASK) | FTM_CONF_ITRIGR(enable);
1198 }
1199 
1210 static inline void FTM_DRV_SetGlobalTimeBaseOutputCmd(FTM_Type * const ftmBase,
1211  bool enable)
1212 {
1213  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_GTBEOUT_MASK) | FTM_CONF_GTBEOUT(enable);
1214 }
1215 
1226 static inline void FTM_DRV_SetGlobalTimeBaseCmd(FTM_Type * const ftmBase,
1227  bool enable)
1228 {
1229  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_GTBEEN_MASK) | FTM_CONF_GTBEEN(enable);
1230 }
1231 
1240 static inline void FTM_DRV_SetLoadFreq(FTM_Type * const ftmBase,
1241  uint8_t val)
1242 {
1244 }
1245 
1255 static inline void FTM_DRV_SetExtPairDeadtimeValue(FTM_Type * const ftmBase,
1256  uint8_t channelPair,
1257  uint8_t value)
1259  DEV_ASSERT(value < 16U);
1260  DEV_ASSERT(channelPair < CHAN4_IDX);
1261 
1262  switch (channelPair)
1263  {
1264  case CHAN0_IDX:
1266  break;
1267  case CHAN1_IDX:
1269  break;
1270  case CHAN2_IDX:
1272  break;
1273  case CHAN3_IDX:
1275  break;
1276  default:
1277  /* Nothing to do */
1278  break;
1279  }
1280 }
1281 
1294 static inline void FTM_DRV_SetPairDeadtimePrescale(FTM_Type * const ftmBase,
1295  uint8_t channelPair,
1296  ftm_deadtime_ps_t divider)
1298  DEV_ASSERT(channelPair < CHAN4_IDX);
1299 
1300  switch (channelPair)
1301  {
1302  case CHAN0_IDX:
1304  break;
1305  case CHAN1_IDX:
1307  break;
1308  case CHAN2_IDX:
1310  break;
1311  case CHAN3_IDX:
1313  break;
1314  default:
1315  /* Nothing to do */
1316  break;
1317  }
1318 }
1319 
1333 static inline void FTM_DRV_SetPairDeadtimeCount(FTM_Type * const ftmBase,
1334  uint8_t channelPair,
1335  uint8_t count)
1337  DEV_ASSERT(channelPair < CHAN4_IDX);
1338  DEV_ASSERT(count < 64U);
1339 
1340  switch (channelPair)
1341  {
1342  case CHAN0_IDX:
1344  break;
1345  case CHAN1_IDX:
1347  break;
1348  case CHAN2_IDX:
1350  break;
1351  case CHAN3_IDX:
1353  break;
1354  default:
1355  /* Nothing to do */
1356  break;
1357  }
1358 }
1359 
1360 #if FEATURE_FTM_HAS_SUPPORTED_DITHERING
1361 
1369 static inline void FTM_DRV_SetMirrorMod(FTM_Type * const ftmBase,
1370  uint16_t value)
1371 {
1373 }
1374 
1384 static inline uint16_t FTM_DRV_GetMirrorMod(const FTM_Type * ftmBase)
1385 {
1386  return (uint16_t)((((ftmBase)->MOD_MIRROR) & FTM_MOD_MIRROR_MOD_MASK) >> FTM_MOD_MIRROR_MOD_SHIFT);
1388 
1398 static inline uint8_t FTM_DRV_GetModFracVal(const FTM_Type * ftmBase)
1399 {
1400  return (uint8_t)((((ftmBase)->MOD_MIRROR) & FTM_MOD_MIRROR_FRACMOD_MASK) >> FTM_MOD_MIRROR_FRACMOD_SHIFT);
1402 
1412 static inline void FTM_DRV_SetMirrorChnMatchVal(FTM_Type * const ftmBase,
1413  uint8_t channel,
1414  uint16_t value)
1416  FTM_RMW_CnV_MIRROR(ftmBase, channel, FTM_CV_MIRROR_VAL_MASK, FTM_CV_MIRROR_VAL(value));
1417 }
1418 
1429 static inline uint16_t FTM_DRV_GetMirrorChnMatchVal(const FTM_Type * ftmBase,
1430  uint8_t channel)
1431 {
1432  return (uint16_t)((((ftmBase)->CV_MIRROR[channel]) & FTM_CV_MIRROR_VAL_MASK) >> FTM_CV_MIRROR_VAL_SHIFT);
1433 }
1434 
1445 static inline uint8_t FTM_DRV_GetChnMatchFracVal(const FTM_Type * ftmBase,
1446  uint8_t channel)
1447 {
1448  return (uint8_t)((((ftmBase)->CV_MIRROR[channel]) & FTM_CV_MIRROR_FRACVAL_MASK) >> FTM_CV_MIRROR_FRACVAL_SHIFT);
1449 }
1450 #endif
1451 
1462 status_t FTM_DRV_Init(uint32_t instance,
1463  const ftm_user_config_t * info,
1464  ftm_state_t * state);
1465 
1474 status_t FTM_DRV_Deinit(uint32_t instance);
1475 
1487 status_t FTM_DRV_MaskOutputChannels(uint32_t instance,
1488  uint32_t channelsMask,
1489  bool softwareTrigger);
1490 
1503 status_t FTM_DRV_SetInitialCounterValue(uint32_t instance,
1504  uint16_t counterValue,
1505  bool softwareTrigger);
1506 
1517 status_t FTM_DRV_SetHalfCycleReloadPoint(uint32_t instance,
1518  uint16_t reloadPoint,
1519  bool softwareTrigger);
1520 
1534 status_t FTM_DRV_SetSoftOutChnValue(uint32_t instance,
1535  uint8_t channelsValues,
1536  bool softwareTrigger);
1537 
1549  uint8_t channelsMask,
1550  bool softwareTrigger);
1551 
1563  uint8_t channelMask,
1564  uint8_t channelValueMask);
1565 
1576 status_t FTM_DRV_SetInvertingControl(uint32_t instance,
1577  uint8_t channelsPairMask,
1578  bool softwareTrigger);
1579 
1590 status_t FTM_DRV_SetModuloCounterValue(uint32_t instance,
1591  uint16_t counterValue,
1592  bool softwareTrigger);
1593 
1604 status_t FTM_DRV_SetOutputlevel(uint32_t instance,
1605  uint8_t channel,
1606  uint8_t level);
1607 
1618 status_t FTM_DRV_SetSync(uint32_t instance,
1619  const ftm_pwm_sync_t * param);
1620 
1632 status_t FTM_DRV_EnableInterrupts(uint32_t instance,
1633  uint32_t interruptMask);
1634 
1642 void FTM_DRV_DisableInterrupts(uint32_t instance,
1643  uint32_t interruptMask);
1644 
1652 uint32_t FTM_DRV_GetEnabledInterrupts(uint32_t instance);
1653 
1661 uint32_t FTM_DRV_GetStatusFlags(uint32_t instance);
1662 
1670 void FTM_DRV_ClearStatusFlags(uint32_t instance,
1671  uint32_t flagMask);
1672 
1681 uint32_t FTM_DRV_GetFrequency(uint32_t instance);
1682 
1691 uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance,
1692  uint32_t freqencyHz);
1693 
1694 #if defined(__cplusplus)
1695 }
1696 #endif
1697  /* End of addtogroup ftm_common */
1701 
1702 #endif /* FTM_COMMON_H */
1703 /*******************************************************************************
1704  * EOF
1705  ******************************************************************************/
const IRQn_Type g_ftmReloadIrqId[(2u)]
Definition: ftm_common.c:77
const IRQn_Type g_ftmFaultIrqId[(2u)]
Definition: ftm_common.c:75
#define FTM_RMW_SC(base, mask, value)
FTM_SC - Read and modify and write to Status And Control (RW)
Definition: ftm_common.h:85
static uint16_t FTM_DRV_GetCounterInitVal(const FTM_Type *ftmBase)
Returns the FTM peripheral counter initial value.
Definition: ftm_common.h:530
static uint16_t FTM_DRV_GetMirrorMod(const FTM_Type *ftmBase)
Returns the mirror of the FTM peripheral counter modulo value.
Definition: ftm_common.h:1387
volatile uint32_t CnSC
Definition: S32K118.h:3831
static void FTM_DRV_SetCaptureTestCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer capture test mode.
Definition: ftm_common.h:884
static void FTM_DRV_SetChnIcrstCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Configure the feature of FTM counter reset by the selected input capture event.
Definition: ftm_common.h:589
#define FTM_FMS_FAULTF0_MASK
Definition: S32K118.h:4418
status_t FTM_DRV_SetSoftwareOutputChannelControl(uint32_t instance, uint8_t channelsMask, bool softwareTrigger)
This function will configure which output channel can be software controlled.
Definition: ftm_common.c:301
static void FTM_DRV_SetPwmLoadCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the loading of MOD, CNTIN and CV with values of their write buffer.
Definition: ftm_common.h:1146
static uint8_t FTM_DRV_GetChnMatchFracVal(const FTM_Type *ftmBase, uint8_t channel)
Returns the channel (n) match fractional value.
Definition: ftm_common.h:1448
static uint16_t FTM_DRV_GetChnCountVal(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel counter value.
Definition: ftm_common.h:746
#define FTM_CONF_GTBEOUT_MASK
Definition: S32K118.h:4550
FlexTimer state structure of the driver.
Definition: ftm_common.h:391
static bool FTM_DRV_GetChOutputValue(const FTM_Type *ftmBase, uint8_t channel)
Get the value of channel output.
Definition: ftm_common.h:728
static void FTM_DRV_SetChnSoftwareCtrlCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the channel software output control.
Definition: ftm_common.h:1032
static bool FTM_DRV_IsChnIcrst(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the FTM FTM counter is reset.
Definition: ftm_common.h:610
ftm_state_t * ftmStatePtr[(2u)]
Pointer to runtime state structure.
Definition: ftm_common.c:84
status_t FTM_DRV_SetSync(uint32_t instance, const ftm_pwm_sync_t *param)
This function configures sync mechanism for some FTM registers (MOD, CNINT, HCR, CnV, OUTMASK, INVCTRL, SWOCTRL).
Definition: ftm_common.c:409
#define FTM_PWMLOAD_GLEN_SHIFT
Definition: S32K118.h:4760
ftm_reg_update_t
FTM sync source.
Definition: ftm_common.h:310
static void FTM_DRV_SetPwmLoadChnSelCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Includes or excludes the channel in the matching process.
Definition: ftm_common.h:1170
volatile uint32_t CONF
Definition: S32K118.h:3848
#define FTM_CnSC_ELSB_SHIFT
Definition: S32K118.h:3999
#define FTM_PAIR3DEADTIME_DTVALEX_MASK
Definition: S32K118.h:4820
#define FTM_PWMLOAD_HCSEL_SHIFT
Definition: S32K118.h:4752
static bool FTM_DRV_IsWriteProtectionEnabled(const FTM_Type *ftmBase)
Checks whether the write protection is enabled.
Definition: ftm_common.h:933
#define FEATURE_FTM_CHANNEL_COUNT
Configuration structure that the user needs to set.
Definition: ftm_common.h:436
#define FTM_MOD_MOD_MASK
Definition: S32K118.h:3981
#define FTM_RMW_MOD_MIRROR(base, mask, value)
FTM_MOD_MIRROR - Read and modify and write mirror of modulo value for the FTM counter (RW) ...
Definition: ftm_common.h:185
#define FTM_MOD_MIRROR_MOD_SHIFT
Definition: S32K118.h:4830
ftm_bdm_mode_t
Options for the FlexTimer behavior in BDM Mode.
Definition: ftm_common.h:370
#define CHAN4_IDX
Channel number for CHAN5.
Definition: ftm_common.h:205
static void FTM_DRV_SetChnOutputInitStateCmd(FTM_Type *const ftmBase, uint8_t channel, bool state)
Sets the FTM peripheral timer channel output initial state 0 or 1.
Definition: ftm_common.h:846
static void FTM_DRV_SetMirrorMod(FTM_Type *const ftmBase, uint16_t value)
Sets the mirror of the modulo integer value.
Definition: ftm_common.h:1372
ftm_status_flag_t
List of FTM flags.
Definition: ftm_common.h:289
#define FTM_RMW_CONF(base, mask, value)
FTM_CONF - Read and modify and write Configuration (RW)
Definition: ftm_common.h:139
#define FTM_PAIR1DEADTIME_DTPS_MASK
Definition: S32K118.h:4790
#define FTM_RMW_PAIR0DEADTIME(base, mask, value)
FTM_PAIR0DEADTIME - Read and modify and write Dead-time Insertion Control for the pair 0 (RW) ...
Definition: ftm_common.h:164
static uint16_t FTM_DRV_GetMirrorChnMatchVal(const FTM_Type *ftmBase, uint8_t channel)
Returns the mirror of the channel (n) match integer value.
Definition: ftm_common.h:1432
static bool FTM_DRV_IsChnDma(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the FTM peripheral timer channel DMA is enabled.
Definition: ftm_common.h:650
#define FTM_SC_FLTPS_MASK
Definition: S32K118.h:3971
FlexTimer Registers sync parameters Please don't use software and hardware trigger simultaneously Imp...
Definition: ftm_common.h:408
#define FTM_SWOCTRL_CH0OCV_SHIFT
Definition: S32K118.h:4687
status_t FTM_DRV_SetInitialCounterValue(uint32_t instance, uint16_t counterValue, bool softwareTrigger)
This function configure the initial counter value. The counter will get this value after an overflow ...
Definition: ftm_common.c:237
#define FTM_PAIR3DEADTIME_DTVAL(x)
Definition: S32K118.h:4815
#define FTM_MOD_MIRROR_FRACMOD_SHIFT
Definition: S32K118.h:4826
status_t FTM_DRV_SetOutputlevel(uint32_t instance, uint8_t channel, uint8_t level)
This function will set the channel edge or level on the selection of the channel mode.
Definition: ftm_common.c:385
static uint8_t FTM_DRV_GetChnEdgeLevel(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel edge level.
Definition: ftm_common.h:565
#define FTM_MOD_MIRROR_FRACMOD_MASK
Definition: S32K118.h:4825
static void FTM_DRV_SetGlobalTimeBaseOutputCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM global time base signal generation to other FTM's.
Definition: ftm_common.h:1213
#define FTM_CONF_GTBEEN_MASK
Definition: S32K118.h:4546
const IRQn_Type g_ftmOverflowIrqId[(2u)]
Definition: ftm_common.c:76
volatile uint32_t FMS
Definition: S32K118.h:3844
#define FTM_PAIR3DEADTIME_DTPS_MASK
Definition: S32K118.h:4816
#define FTM_RMW_CnV_MIRROR(base, channel, mask, value)
FTM_CnV_MIRROR - Read and modify and write mirror of channel (n) match value (RW) ...
Definition: ftm_common.h:190
static uint8_t FTM_DRV_GetClockFilterPs(const FTM_Type *ftmBase)
Reads the FTM filter clock divider.
Definition: ftm_common.h:488
status_t FTM_DRV_SetHalfCycleReloadPoint(uint32_t instance, uint16_t reloadPoint, bool softwareTrigger)
This function configure the value of the counter which will generates an reload point.
Definition: ftm_common.c:258
#define FTM_CnSC_TRIGMODE(x)
Definition: S32K118.h:4021
ftm_interrupt_option_t
List of FTM interrupts.
Definition: ftm_common.h:269
static void FTM_DRV_SetCountReinitSyncCmd(FTM_Type *const ftmBase, bool enable)
Determines if the FTM counter is re-initialized when the selected trigger for synchronization is dete...
Definition: ftm_common.h:916
#define FTM_CONF_GTBEOUT(x)
Definition: S32K118.h:4553
#define FTM_CNTIN_INIT_MASK
Definition: S32K118.h:4036
#define FTM_PAIR2DEADTIME_DTVALEX_MASK
Definition: S32K118.h:4807
const IRQn_Type g_ftmIrqId[(2u)][(8U)]
Interrupt vectors for the FTM peripheral.
Definition: ftm_common.c:74
#define FTM_CNTIN_INIT_SHIFT
Definition: S32K118.h:4037
#define FTM_MODE_FAULTIE_MASK
Definition: S32K118.h:4098
static bool FTM_DRV_GetChnEventStatus(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel event status.
Definition: ftm_common.h:766
#define FTM_MOD_MIRROR_MOD(x)
Definition: S32K118.h:4832
#define DEV_ASSERT(x)
Definition: devassert.h:77
static uint8_t FTM_DRV_GetModFracVal(const FTM_Type *ftmBase)
Returns The modulo fractional value is used in the PWM period dithering.
Definition: ftm_common.h:1401
static void FTM_DRV_SetExtPairDeadtimeValue(FTM_Type *const ftmBase, uint8_t channelPair, uint8_t value)
Sets the FTM extended dead-time value for the channel pair.
Definition: ftm_common.h:1258
volatile uint32_t MODE
Definition: S32K118.h:3836
#define FTM_RMW_SYNC(base, mask, value)
SYNC - Read and modify and write Synchronization (RW)
Definition: ftm_common.h:154
#define FTM_MODE_FAULTIE(x)
Definition: S32K118.h:4101
uint32_t FTM_DRV_GetFrequency(uint32_t instance)
Retrieves the frequency of the clock source feeding the FTM counter.
Definition: ftm_common.c:733
#define FTM_PAIR1DEADTIME_DTVAL(x)
Definition: S32K118.h:4789
volatile uint32_t STATUS
Definition: S32K118.h:3835
#define FTM_PWMLOAD_GLDOK_SHIFT
Definition: S32K118.h:4764
uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance, uint32_t freqencyHz)
This function is used to covert the given frequency to period in ticks.
Definition: ftm_common.c:788
void FTM_DRV_ClearStatusFlags(uint32_t instance, uint32_t flagMask)
This function is used to clear the FTM status flags.
Definition: ftm_common.c:681
#define FTM_FMS_WPEN_MASK
Definition: S32K118.h:4438
#define FTM_PAIR1DEADTIME_DTPS(x)
Definition: S32K118.h:4793
#define FTM_PAIR1DEADTIME_DTVAL_MASK
Definition: S32K118.h:4786
#define FTM_PAIR2DEADTIME_DTPS(x)
Definition: S32K118.h:4806
#define FTM_CnSC_ELSA_MASK
Definition: S32K118.h:3994
static void FTM_DRV_SetLoadCmd(FTM_Type *const ftmBase, bool enable)
Enable the global load.
Definition: ftm_common.h:1100
#define FTM_PAIR0DEADTIME_DTVALEX_MASK
Definition: S32K118.h:4781
static void FTM_DRV_SetChnDmaCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the FTM peripheral timer channel DMA.
Definition: ftm_common.h:629
ftm_clock_ps_t
FlexTimer pre-scaler factor selection for the clock source. In quadrature decoder mode set FTM_CLOCK_...
Definition: ftm_common.h:252
static void FTM_DRV_SetClockFilterPs(FTM_Type *const ftmBase, uint8_t filterPrescale)
Sets the filter Pre-scaler divider.
Definition: ftm_common.h:473
static void FTM_DRV_SetGlobalLoadCmd(FTM_Type *const ftmBase)
Set the global load mechanism.
Definition: ftm_common.h:1085
#define FTM_CV_MIRROR_VAL(x)
Definition: S32K118.h:4841
static void FTM_DRV_SetInitTrigOnReloadCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM initialization trigger on Reload Point.
Definition: ftm_common.h:1197
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K118.h:188
static void FTM_DRV_ClearChSC(FTM_Type *const ftmBase, uint8_t channel)
Clears the content of Channel (n) Status And Control.
Definition: ftm_common.h:543
#define FTM_MOD_MOD_SHIFT
Definition: S32K118.h:3982
#define CHAN0_IDX
Channel number for CHAN1.
Definition: ftm_common.h:197
#define FTM_SC_FLTPS(x)
Definition: S32K118.h:3974
void(* ic_callback_t)(ic_event_t event, void *userData)
Definition: callbacks.h:185
ftm_clock_source_t
FlexTimer clock source selection.
Definition: ftm_common.h:238
static void FTM_DRV_SetChnSoftwareCtrlVal(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Sets the channel software output control value.
Definition: ftm_common.h:1059
#define FTM_CnSC_ELSB_MASK
Definition: S32K118.h:3998
ftm_quad_phase_polarity_t
FlexTimer quadrature phase polarities, normal or inverted polarity.
Definition: ftm_common.h:357
static void FTM_DRV_SetDualChnInvertCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the channel invert for a channel pair.
Definition: ftm_common.h:1005
#define FTM_MODE_CAPTEST_MASK
Definition: S32K118.h:4090
#define FTM_INSTANCE_COUNT
Definition: S32K118.h:3868
status_t FTM_DRV_SetInvertingControl(uint32_t instance, uint8_t channelsPairMask, bool softwareTrigger)
This function will configure if the second channel of a pair will be inverted or not.
Definition: ftm_common.c:344
#define FTM_CV_MIRROR_VAL_MASK
Definition: S32K118.h:4838
#define FTM_PAIR0DEADTIME_DTVAL_MASK
Definition: S32K118.h:4773
#define FTM_CONF_ITRIGR_MASK
Definition: S32K118.h:4554
static void FTM_DRV_SetTrigModeControlCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the trigger generation on FTM channel outputs.
Definition: ftm_common.h:669
#define FTM_PAIR3DEADTIME_DTVAL_MASK
Definition: S32K118.h:4812
ftm_quad_decode_mode_t
FlexTimer quadrature decode modes, phase encode or count and direction mode.
Definition: ftm_common.h:346
#define FTM_CnSC_ELSA_SHIFT
Definition: S32K118.h:3995
#define FTM_PAIR0DEADTIME_DTPS_MASK
Definition: S32K118.h:4777
#define FTM_PAIR3DEADTIME_DTPS(x)
Definition: S32K118.h:4819
#define CHAN2_IDX
Channel number for CHAN3.
Definition: ftm_common.h:201
#define FTM_PAIR1DEADTIME_DTVALEX(x)
Definition: S32K118.h:4797
static uint32_t FTM_DRV_GetEventStatus(const FTM_Type *ftmBase)
Gets the FTM peripheral timer status info for all channels.
Definition: ftm_common.h:783
#define FTM_CnSC_DMA(x)
Definition: S32K118.h:3989
#define FTM_MODE_CAPTEST(x)
Definition: S32K118.h:4093
#define FTM_CV_MIRROR_FRACVAL_MASK
Definition: S32K118.h:4834
#define FTM_PAIR3DEADTIME_DTVALEX(x)
Definition: S32K118.h:4823
#define FTM_CnSC_CHOV_MASK
Definition: S32K118.h:4026
static void FTM_DRV_SetLoadFreq(FTM_Type *const ftmBase, uint8_t val)
Sets the FTM timer TOF Frequency.
Definition: ftm_common.h:1243
static bool FTM_DRV_IsFtmEnable(const FTM_Type *ftmBase)
Get status of the FTMEN bit in the FTM_MODE register.
Definition: ftm_common.h:900
#define FTM_RMW_PAIR3DEADTIME(base, mask, value)
FTM_PAIR3DEADTIME - Read and modify and write Dead-time Insertion Control for the pair 3 (RW) ...
Definition: ftm_common.h:179
status_t FTM_DRV_EnableInterrupts(uint32_t instance, uint32_t interruptMask)
This function will enable the generation a list of interrupts. It includes the FTM overflow interrupt...
Definition: ftm_common.c:485
static void FTM_DRV_SetGlobalTimeBaseCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM timer global time base.
Definition: ftm_common.h:1229
static void FTM_DRV_SetHalfCycleCmd(FTM_Type *const ftmBase, bool enable)
Enable the half cycle reload.
Definition: ftm_common.h:1123
#define FTM_SYNC_REINIT_MASK
Definition: S32K118.h:4111
static bool FTM_DRV_GetChInputState(const FTM_Type *ftmBase, uint8_t channel)
Get the state of channel input.
Definition: ftm_common.h:709
#define FTM_RMW_PAIR2DEADTIME(base, mask, value)
FTM_PAIR2DEADTIME - Read and modify and write Dead-time Insertion Control for the pair 2 (RW) ...
Definition: ftm_common.h:174
ftm_deadtime_ps_t
FlexTimer pre-scaler factor for the dead-time insertion.
Definition: ftm_common.h:334
#define FTM_CnSC_CHIS_MASK
Definition: S32K118.h:4022
#define FTM_PAIR0DEADTIME_DTPS(x)
Definition: S32K118.h:4780
status_t FTM_DRV_SetModuloCounterValue(uint32_t instance, uint16_t counterValue, bool softwareTrigger)
This function configure the maximum counter value.
Definition: ftm_common.c:364
#define FTM_CONF_GTBEEN(x)
Definition: S32K118.h:4549
#define FTM_CnSC_TRIGMODE_MASK
Definition: S32K118.h:4018
#define FTM_CONF_ITRIGR(x)
Definition: S32K118.h:4557
#define CHAN1_IDX
Channel number for CHAN2.
Definition: ftm_common.h:199
static void FTM_DRV_SetChnOutputMask(FTM_Type *const ftmBase, uint8_t channel, bool mask)
Sets the FTM peripheral timer channel output mask.
Definition: ftm_common.h:819
#define FTM_CV_MIRROR_VAL_SHIFT
Definition: S32K118.h:4839
static void FTM_DRV_SetMirrorChnMatchVal(FTM_Type *const ftmBase, uint8_t channel, uint16_t value)
Sets the mirror of the channel (n) match integer value.
Definition: ftm_common.h:1415
#define FTM_RMW_CnSCV_REG(base, channel, mask, value)
FTM_CnSCV - Read and modify and write Channel (n) Status And Control (RW)
Definition: ftm_common.h:115
uint32_t FTM_DRV_GetEnabledInterrupts(uint32_t instance)
This function will get the enabled FTM interrupts.
Definition: ftm_common.c:585
#define FTM_CONF_LDFQ_MASK
Definition: S32K118.h:4538
status_t FTM_DRV_Deinit(uint32_t instance)
Shuts down the FTM driver.
Definition: ftm_common.c:196
#define FTM_FMS_FAULTIN_MASK
Definition: S32K118.h:4434
#define FTM_CnSC_ICRST(x)
Definition: S32K118.h:3993
status_t FTM_DRV_MaskOutputChannels(uint32_t instance, uint32_t channelsMask, bool softwareTrigger)
This function will mask the output of the channels and at match events will be ignored by the masked ...
Definition: ftm_common.c:216
#define FTM_MOD_MIRROR_MOD_MASK
Definition: S32K118.h:4829
#define FTM_PAIR2DEADTIME_DTVAL(x)
Definition: S32K118.h:4802
#define FTM_SYNC_REINIT(x)
Definition: S32K118.h:4114
static void FTM_DRV_ClearChnEventStatus(FTM_Type *const ftmBase, uint8_t channel)
Clears the FTM peripheral timer all channel event status.
Definition: ftm_common.h:796
#define FTM_CnSC_ICRST_MASK
Definition: S32K118.h:3990
#define FTM_PAIR1DEADTIME_DTVALEX_MASK
Definition: S32K118.h:4794
#define FTM_MODE_FTMEN_SHIFT
Definition: S32K118.h:4075
static uint16_t FTM_DRV_GetMod(const FTM_Type *ftmBase)
Returns the FTM peripheral counter modulo value.
Definition: ftm_common.h:516
#define FTM_CnSC_DMA_MASK
Definition: S32K118.h:3986
static bool FTM_DRV_IsFaultFlagDetected(const FTM_Type *ftmBase, uint8_t channel)
Checks whether a fault condition is detected at the fault input.
Definition: ftm_common.h:966
ftm_pwm_sync_mode_t
FTM update register.
Definition: ftm_common.h:323
status_t FTM_DRV_Init(uint32_t instance, const ftm_user_config_t *info, ftm_state_t *state)
Initializes the FTM driver.
Definition: ftm_common.c:117
status_t FTM_DRV_SetSoftOutChnValue(uint32_t instance, uint8_t channelsValues, bool softwareTrigger)
This function will force the output value of a channel to a specific value. Before using this functio...
Definition: ftm_common.c:281
static void FTM_DRV_SetPairDeadtimeCount(FTM_Type *const ftmBase, uint8_t channelPair, uint8_t count)
Sets the FTM dead-time value for the channel pair.
Definition: ftm_common.h:1336
#define FTM_PAIR2DEADTIME_DTVALEX(x)
Definition: S32K118.h:4810
#define FTM_RMW_MODE(base, mask, value)
FTM_MODE - Read and modify and write Counter Features Mode Selection (RW)
Definition: ftm_common.h:110
#define FTM_PAIR0DEADTIME_DTVAL(x)
Definition: S32K118.h:4776
struct FTM_Type::@11 CONTROLS[8u]
#define FTM_CNT_COUNT_SHIFT
Definition: S32K118.h:3977
#define FTM_CONF_LDFQ(x)
Definition: S32K118.h:4541
#define FTM_PWMLOAD_LDOK_SHIFT
Definition: S32K118.h:4756
#define FTM_MODE_FTMEN_MASK
Definition: S32K118.h:4074
static void FTM_DRV_DisableFaultInt(FTM_Type *const ftmBase)
Disables the FTM peripheral timer fault interrupt.
Definition: ftm_common.h:869
uint32_t FTM_DRV_GetStatusFlags(uint32_t instance)
This function will get the FTM status flags.
Definition: ftm_common.c:631
static bool FTM_DRV_IsFaultInputEnabled(const FTM_Type *ftmBase)
Checks whether the logic OR of the fault inputs is enabled.
Definition: ftm_common.h:949
#define FTM_PAIR2DEADTIME_DTPS_MASK
Definition: S32K118.h:4803
void FTM_DRV_DisableInterrupts(uint32_t instance, uint32_t interruptMask)
This function is used to disable some interrupts.
Definition: ftm_common.c:536
#define FTM_PAIR2DEADTIME_DTVAL_MASK
Definition: S32K118.h:4799
static void FTM_DRV_SetPairDeadtimePrescale(FTM_Type *const ftmBase, uint8_t channelPair, ftm_deadtime_ps_t divider)
Sets the FTM dead time divider for the channel pair.
Definition: ftm_common.h:1297
#define FTM_RMW_PAIR1DEADTIME(base, mask, value)
FTM_PAIR1DEADTIME - Read and modify and write Dead-time Insertion Control for the pair 1 (RW) ...
Definition: ftm_common.h:169
ftm_config_mode_t
FlexTimer operation mode.
Definition: ftm_common.h:221
#define FTM_CNT_COUNT_MASK
Definition: S32K118.h:3976
#define FTM_CV_MIRROR_FRACVAL_SHIFT
Definition: S32K118.h:4835
#define FTM_SC_FLTPS_SHIFT
Definition: S32K118.h:3972
status_t FTM_DRV_SetAllChnSoftwareOutputControl(uint32_t instance, uint8_t channelMask, uint8_t channelValueMask)
This function will control list of channels by software to force the output to specified value...
Definition: ftm_common.c:321
#define CHAN3_IDX
Channel number for CHAN4.
Definition: ftm_common.h:203
static uint16_t FTM_DRV_GetCounter(const FTM_Type *ftmBase)
Returns the FTM peripheral current counter value.
Definition: ftm_common.h:502
static bool FTM_DRV_GetTriggerControled(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the trigger mode is enabled.
Definition: ftm_common.h:690
FTM_Type *const g_ftmBase[(2u)]
Table of base addresses for FTM instances.
Definition: ftm_common.c:71
static void FTM_DRV_ClearFaultFlagDetected(FTM_Type *const ftmBase, uint8_t channel)
Clear a fault condition is detected at the fault input.
Definition: ftm_common.h:982
#define FTM_PAIR0DEADTIME_DTVALEX(x)
Definition: S32K118.h:4784