Modules | |
DMA Register Masks | |
Data Structures | |
struct | DMA_Type |
Macros | |
#define | DMA_DCHPRI_COUNT 4u |
#define | DMA_TCD_COUNT 4u |
#define | DMA_INSTANCE_COUNT (1u) |
#define | DMA_BASE (0x40008000u) |
#define | DMA ((DMA_Type *)DMA_BASE) |
#define | DMA_BASE_ADDRS { DMA_BASE } |
#define | DMA_BASE_PTRS { DMA } |
#define | DMA_IRQS_ARR_COUNT (2u) |
#define | DMA_CHN_IRQS_CH_COUNT (4u) |
#define | DMA_ERROR_IRQS_CH_COUNT (1u) |
#define | DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } |
#define | DMA_ERROR_IRQS { DMA_Error_IRQn } |
Typedefs | |
typedef struct DMA_Type * | DMA_MemMapPtr |
#define DMA_BASE (0x40008000u) |
#define DMA_BASE_ADDRS { DMA_BASE } |
#define DMA_BASE_PTRS { DMA } |
#define DMA_CHN_IRQS_CH_COUNT (4u) |
#define DMA_DCHPRI_COUNT 4u |
#define DMA_ERROR_IRQS { DMA_Error_IRQn } |
#define DMA_ERROR_IRQS_CH_COUNT (1u) |
#define DMA_INSTANCE_COUNT (1u) |
#define DMA_IRQS_ARR_COUNT (2u) |
typedef struct DMA_Type * DMA_MemMapPtr |