#define SCG_CLKOUTCNFG_CLKOUTSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT))&SCG_CLKOUTCNFG_CLKOUTSEL_MASK) |
#define SCG_CSR_DIVBUS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVBUS_SHIFT))&SCG_CSR_DIVBUS_MASK) |
#define SCG_CSR_DIVCORE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVCORE_SHIFT))&SCG_CSR_DIVCORE_MASK) |
#define SCG_CSR_DIVSLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVSLOW_SHIFT))&SCG_CSR_DIVSLOW_MASK) |
#define SCG_CSR_SCS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_CSR_SCS_SHIFT))&SCG_CSR_SCS_MASK) |
#define SCG_FIRCCFG_RANGE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCFG_RANGE_SHIFT))&SCG_FIRCCFG_RANGE_MASK) |
#define SCG_FIRCCSR_FIRCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCEN_SHIFT))&SCG_FIRCCSR_FIRCEN_MASK) |
#define SCG_FIRCCSR_FIRCERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCERR_SHIFT))&SCG_FIRCCSR_FIRCERR_MASK) |
#define SCG_FIRCCSR_FIRCREGOFF | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCREGOFF_SHIFT))&SCG_FIRCCSR_FIRCREGOFF_MASK) |
#define SCG_FIRCCSR_FIRCSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCSEL_SHIFT))&SCG_FIRCCSR_FIRCSEL_MASK) |
#define SCG_FIRCCSR_FIRCVLD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCVLD_SHIFT))&SCG_FIRCCSR_FIRCVLD_MASK) |
#define SCG_FIRCCSR_LK | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_LK_SHIFT))&SCG_FIRCCSR_LK_MASK) |
#define SCG_FIRCDIV_FIRCDIV1 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV1_SHIFT))&SCG_FIRCDIV_FIRCDIV1_MASK) |
#define SCG_FIRCDIV_FIRCDIV2 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV2_SHIFT))&SCG_FIRCDIV_FIRCDIV2_MASK) |
#define SCG_PARAM_CLKPRES | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_CLKPRES_SHIFT))&SCG_PARAM_CLKPRES_MASK) |
#define SCG_PARAM_DIVPRES | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_DIVPRES_SHIFT))&SCG_PARAM_DIVPRES_MASK) |
#define SCG_RCCR_DIVBUS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVBUS_SHIFT))&SCG_RCCR_DIVBUS_MASK) |
#define SCG_RCCR_DIVCORE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVCORE_SHIFT))&SCG_RCCR_DIVCORE_MASK) |
#define SCG_RCCR_DIVSLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVSLOW_SHIFT))&SCG_RCCR_DIVSLOW_MASK) |
#define SCG_RCCR_SCS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_SCS_SHIFT))&SCG_RCCR_SCS_MASK) |
#define SCG_SIRCCFG_RANGE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCFG_RANGE_SHIFT))&SCG_SIRCCFG_RANGE_MASK) |
#define SCG_SIRCCSR_LK | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_LK_SHIFT))&SCG_SIRCCSR_LK_MASK) |
#define SCG_SIRCCSR_SIRCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCEN_SHIFT))&SCG_SIRCCSR_SIRCEN_MASK) |
#define SCG_SIRCCSR_SIRCLPEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCLPEN_SHIFT))&SCG_SIRCCSR_SIRCLPEN_MASK) |
#define SCG_SIRCCSR_SIRCSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSEL_SHIFT))&SCG_SIRCCSR_SIRCSEL_MASK) |
#define SCG_SIRCCSR_SIRCSTEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSTEN_SHIFT))&SCG_SIRCCSR_SIRCSTEN_MASK) |
#define SCG_SIRCCSR_SIRCVLD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCVLD_SHIFT))&SCG_SIRCCSR_SIRCVLD_MASK) |
#define SCG_SIRCDIV_SIRCDIV1 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV1_SHIFT))&SCG_SIRCDIV_SIRCDIV1_MASK) |
#define SCG_SIRCDIV_SIRCDIV2 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV2_SHIFT))&SCG_SIRCDIV_SIRCDIV2_MASK) |
#define SCG_SOSCCFG_EREFS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_EREFS_SHIFT))&SCG_SOSCCFG_EREFS_MASK) |
#define SCG_SOSCCFG_HGO | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_HGO_SHIFT))&SCG_SOSCCFG_HGO_MASK) |
#define SCG_SOSCCFG_RANGE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_RANGE_SHIFT))&SCG_SOSCCFG_RANGE_MASK) |
#define SCG_SOSCCSR_LK | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_LK_SHIFT))&SCG_SOSCCSR_LK_MASK) |
#define SCG_SOSCCSR_SOSCCM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCM_SHIFT))&SCG_SOSCCSR_SOSCCM_MASK) |
#define SCG_SOSCCSR_SOSCCMRE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCMRE_SHIFT))&SCG_SOSCCSR_SOSCCMRE_MASK) |
#define SCG_SOSCCSR_SOSCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCEN_SHIFT))&SCG_SOSCCSR_SOSCEN_MASK) |
#define SCG_SOSCCSR_SOSCERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCERR_SHIFT))&SCG_SOSCCSR_SOSCERR_MASK) |
#define SCG_SOSCCSR_SOSCSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCSEL_SHIFT))&SCG_SOSCCSR_SOSCSEL_MASK) |
#define SCG_SOSCCSR_SOSCVLD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCVLD_SHIFT))&SCG_SOSCCSR_SOSCVLD_MASK) |
#define SCG_SOSCDIV_SOSCDIV1 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV1_SHIFT))&SCG_SOSCDIV_SOSCDIV1_MASK) |
#define SCG_SOSCDIV_SOSCDIV2 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV2_SHIFT))&SCG_SOSCDIV_SOSCDIV2_MASK) |
#define SCG_VCCR_DIVBUS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVBUS_SHIFT))&SCG_VCCR_DIVBUS_MASK) |
#define SCG_VCCR_DIVCORE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVCORE_SHIFT))&SCG_VCCR_DIVCORE_MASK) |
#define SCG_VCCR_DIVSLOW | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVSLOW_SHIFT))&SCG_VCCR_DIVSLOW_MASK) |
#define SCG_VCCR_SCS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_SCS_SHIFT))&SCG_VCCR_SCS_MASK) |
#define SCG_VERID_VERSION | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SCG_VERID_VERSION_SHIFT))&SCG_VERID_VERSION_MASK) |