pins_driver.h
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1 /*
2  * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #ifndef PINS_DRIVER_H
20 #define PINS_DRIVER_H
21 
22 #include <stddef.h>
23 #include "device_registers.h"
24 #include "status.h"
25 
33 /*******************************************************************************
34  * Definitions
35  ******************************************************************************/
36 #if defined(FEATURE_PINS_DRIVER_USING_PORT)
37 
41 typedef uint32_t pins_channel_type_t;
42 
43 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
44 
48 typedef uint16_t pins_channel_type_t;
49 
50 #endif /* if defined(FEATURE_PINS_DRIVER_USING_PORT) */
51 
56 typedef uint8_t pins_level_type_t;
57 
62 typedef enum
63 {
68 
69 #if FEATURE_PINS_HAS_PULL_SELECTION
70 
74 typedef enum
75 {
80 #endif /* FEATURE_PINS_HAS_PULL_SELECTION */
81 
82 #if FEATURE_PINS_HAS_OPEN_DRAIN
83 
87 typedef enum
88 {
89  PORT_OPEN_DRAIN_DISABLED = 0U,
90  PORT_OPEN_DRAIN_ENABLED = 1U
91 } port_open_drain_t;
92 #endif /* FEATURE_PINS_HAS_OPEN_DRAIN */
93 
94 #if FEATURE_PINS_HAS_DRIVE_STRENGTH
95 
99 typedef enum
100 {
101 #if FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL
102  PORT_STRENGTH_DISABLED = 0U,
104  PORT_STR1_DRIVE_STRENGTH = 1U,
105  PORT_STR2_DRIVE_STRENGTH = 2U,
106  PORT_STR3_DRIVE_STRENGTH = 3U,
107  PORT_STR4_DRIVE_STRENGTH = 4U,
108  PORT_STR5_DRIVE_STRENGTH = 5U,
109  PORT_STR6_DRIVE_STRENGTH = 6U,
110  PORT_STR7_DRIVE_STRENGTH = 7U,
112 #else /* if not FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL */
113  PORT_LOW_DRIVE_STRENGTH = 0U,
114  PORT_HIGH_DRIVE_STRENGTH = 1U
115 #endif /* if FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL */
117 #endif /* FEATURE_PINS_HAS_DRIVE_STRENGTH */
118 
119 #ifdef FEATURE_PINS_DRIVER_USING_PORT
120 
124 typedef enum
125 {
134 } port_mux_t;
135 
140 typedef enum
141 {
146 #if FEATURE_PORT_HAS_FLAG_SET_ONLY
147  PORT_FLAG_RISING_EDGE = 0x5U,
148  PORT_FLAG_FALLING_EDGE = 0x6U,
149  PORT_FLAG_EITHER_EDGE = 0x7U,
150 #endif /* FEATURE_PORT_HAS_FLAG_SET_ONLY */
156 #if FEATURE_PORT_HAS_TRIGGER_OUT
157  PORT_HIGH_TRIGGER_OUT = 0xDU,
158  PORT_LOW_TRIGGER_OUT = 0xEU
159 #endif /* FEATURE_PORT_HAS_TRIGGER_OUT */
161 
162 #if FEATURE_PINS_HAS_SLEW_RATE
163 
167 typedef enum
168 {
169  PORT_FAST_SLEW_RATE = 0U,
170  PORT_SLOW_SLEW_RATE = 1U
171 } port_slew_rate_t;
172 #endif /* FEATURE_PINS_HAS_SLEW_RATE */
173 
178 typedef enum
179 {
183 
188 typedef struct
189 {
191  uint8_t width;
193 
198 typedef enum
199 {
203 
204 #if FEATURE_PINS_HAS_OVER_CURRENT
205 
209 typedef enum
210 {
211  PORT_OVER_CURRENT_DISABLED = 0U,
212  PORT_OVER_CURRENT_INT_DISABLED = 1U,
213  PORT_OVER_CURRENT_INT_ENABLED = 2U
214 } port_over_current_config_t;
215 #endif /* FEATURE_PINS_HAS_OVER_CURRENT */
216 
217 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
218 #if FEATURE_SIUL2_HAS_DDR_PAD
219 
225 typedef enum
226 {
227  DDR_DDR3_MODE = 0x0U,
228  DDR_LPDDR2_MODE = 0x2U
229 } port_ddr_type_t;
230 
239 typedef enum
240 {
241  DDR_MIN_DELAY = 0x0U,
242  DDR_50PS_DELAY = 0x1U,
243  DDR_100PS_DELAY = 0x2U,
244  DDR_150PS_DELAY = 0x3U
245 } port_ddr_trim_delay_t;
246 
255 typedef enum
256 {
257  DDR_NO_CRPOINT = 0x0U,
258  DDR_MINUS_CRPOINT = 0x1U,
259  DDR_PLUS_CRPOINT = 0x2U,
260  DDR_DOUBLE_CRPOINT = 0x3U
261 } port_ddr_crpoint_t;
262 
271 typedef enum
272 {
273  DDR_NO_TRIM = 0x0U,
274  DDR_LEFT_TRIM = 0x1U,
275  DDR_RIGHT_TRIM = 0x2U
276 } port_ddr_trim_t;
277 
282 typedef enum
283 {
284  PORT_DDR_INPUT_CMOS = 0U,
285  PORT_DDR_INPUT_DIFFERENTIAL = 1U
286 } port_ddr_input_t;
287 
292 typedef enum
293 {
294  PORT_STR0_ON_DIE_TERMINATION = 0U,
295  PORT_STR1_ON_DIE_TERMINATION = 1U,
296  PORT_STR2_ON_DIE_TERMINATION = 2U,
297  PORT_STR3_ON_DIE_TERMINATION = 3U,
298  PORT_STR4_ON_DIE_TERMINATION = 4U,
299  PORT_STR5_ON_DIE_TERMINATION = 5U,
300  PORT_STR6_ON_DIE_TERMINATION = 6U,
301  PORT_STR7_ON_DIE_TERMINATION = 7U
302 } port_on_die_termination_t;
303 
310 typedef struct
311 {
312  port_ddr_type_t ddrSelection;
313  port_ddr_trim_delay_t trimmingDelay;
314  port_ddr_crpoint_t crosspointAdjustment;
315  port_ddr_trim_t trimmingAdjustment;
316 } pin_ddr_config_t;
317 
318 #endif /* FEATURE_SIUL2_HAS_DDR_PAD */
319 
324 typedef enum
325 {
326  PORT_MUX_AS_GPIO = 0U,
327  PORT_MUX_ALT1 = 1U,
328  PORT_MUX_ALT2 = 2U,
329  PORT_MUX_ALT3 = 3U,
330  PORT_MUX_ALT4 = 4U,
331  PORT_MUX_ALT5 = 5U,
332  PORT_MUX_ALT6 = 6U,
333  PORT_MUX_ALT7 = 7U,
334  PORT_MUX_ALT8 = 8U,
335  PORT_MUX_ALT9 = 9U,
336  PORT_MUX_ALT10 = 10U,
337  PORT_MUX_ALT11 = 11U,
338  PORT_MUX_ALT12 = 12U,
339  PORT_MUX_ALT13 = 13U,
340  PORT_MUX_ALT14 = 14U,
341  PORT_MUX_ALT15 = 15U
342 } port_mux_t;
343 
348 typedef enum
349 {
350  SIUL2_INT_DISABLE = 0x0U,
351  SIUL2_INT_RISING_EDGE = 0x1U,
352  SIUL2_INT_FALLING_EDGE = 0x2U,
353  SIUL2_INT_EITHER_EDGE = 0x3U
354 } siul2_interrupt_type_t;
355 
356 #if FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA
357 
361 typedef enum
362 {
363  SIUL2_INT_USING_INTERUPT = 0x0U,
364  SIUL2_INT_USING_DMA = 0x1U
365 } siul2_interrupt_dma_select_t;
366 #endif /* FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA */
367 
372 typedef struct
373 {
374  uint8_t eirqPinIdx;
375  siul2_interrupt_type_t intEdgeSel;
376  bool digitalFilter;
377  uint8_t maxCnt;
378 #if FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA
379  siul2_interrupt_dma_select_t intExeSel;
380 #endif
381 } siul2_interrupt_config_t;
382 
387 typedef enum
388 {
389  PORT_OUTPUT_BUFFER_DISABLED = 0U,
390  PORT_OUTPUT_BUFFER_ENABLED = 1U
391 } port_output_buffer_t;
392 
397 typedef enum
398 {
399  PORT_INPUT_BUFFER_DISABLED = 0U,
400  PORT_INPUT_BUFFER_ENABLED = 1U
401 } port_input_buffer_t;
402 
403 #if FEATURE_SIUL2_HAS_HYSTERESIS
404 
408 typedef enum
409 {
410  PORT_HYSTERESYS_CMOS = 0U,
411  PORT_HYSTERESYS_SCHMITT = 1U,
412  PORT_HYSTERESYS_DISABLED = 0U,
413  PORT_HYSTERESYS_ENABLED = 1U
414 } port_hysteresis_t;
415 #endif /* FEATURE_SIUL2_HAS_HYSTERESIS */
416 
417 #if FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT
418 
422 typedef enum
423 {
424  PORT_INVERT_OUTPUT_DISABLED = 0U,
425  PORT_INVERT_OUTPUT_ENABLED = 1U
426 } port_invert_output_t;
427 #endif /* FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT */
428 
429 #if FEATURE_SIUL2_HAS_INVERT_DATA_INPUT
430 
434 typedef enum
435 {
436  PORT_INVERT_INPUT_DISABLED = 0U,
437  PORT_INVERT_INPUT_ENABLED = 1U
438 } port_invert_input_t;
439 #endif /* FEATURE_SIUL2_HAS_INVERT_DATA_INPUT */
440 
441 #if FEATURE_SIUL2_HAS_PULL_KEEPER
442 
446 typedef enum
447 {
448  PORT_PULL_KEEP_DISABLED = 0U,
449  PORT_PULL_KEEP_ENABLED = 1U
450 } port_pull_keep_t;
451 
456 typedef enum
457 {
458  PORT_KEEPER_ENABLED = 0U,
459  PORT_PULL_ENABLED = 1U
460 } port_pull_keeper_select_t;
461 
466 typedef enum
467 {
468  PORT_PULL_DOWN_ENABLED = 0U,
469  PORT_PULL_UP_MEDIUM = 1U,
470  PORT_PULL_UP_HIGH = 2U,
471  PORT_PULL_UP_LOW = 3U
472 } port_pull_up_down_t;
473 
474 #endif /* FEATURE_SIUL2_HAS_PULL_KEEPER */
475 
476 #if FEATURE_SIUL2_HAS_ANALOG_PAD
477 
481 typedef enum
482 {
483  PORT_ANALOG_PAD_CONTROL_DISABLED = 0U,
484  PORT_ANALOG_PAD_CONTROL_ENABLED = 1U
485 } port_analog_pad_t;
486 #endif /* FEATURE_SIUL2_HAS_ANALOG_PAD */
487 
492 typedef enum
493 {
494  PORT_INPUT_MUX_ALT0 = 0U,
495  PORT_INPUT_MUX_ALT1 = 1U,
496  PORT_INPUT_MUX_ALT2 = 2U,
497  PORT_INPUT_MUX_ALT3 = 3U,
498  PORT_INPUT_MUX_ALT4 = 4U,
499  PORT_INPUT_MUX_ALT5 = 5U,
500  PORT_INPUT_MUX_ALT6 = 6U,
501  PORT_INPUT_MUX_ALT7 = 7U,
502 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 4U)
503  PORT_INPUT_MUX_ALT8 = 8U,
504  PORT_INPUT_MUX_ALT9 = 9U,
505  PORT_INPUT_MUX_ALT10 = 10U,
506  PORT_INPUT_MUX_ALT11 = 11U,
507  PORT_INPUT_MUX_ALT12 = 12U,
508  PORT_INPUT_MUX_ALT13 = 13U,
509  PORT_INPUT_MUX_ALT14 = 14U,
510  PORT_INPUT_MUX_ALT15 = 15U,
511 #endif
512  PORT_INPUT_MUX_NO_INIT
513 } port_input_mux_t;
514 
519 typedef enum
520 {
521  PORT_SAFE_MODE_DISABLED = 0U,
523  PORT_SAFE_MODE_ENABLED = 1U
524 } port_safe_mode_t;
525 
526 #if FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL
527 
531 typedef enum
532 {
533  HALF_STRENGTH_WITH_SLEWRATE_CONTROL = 0u,
534  FULL_STRENGTH_WITH_SLEWRATE_CONTROL = 1u,
535  HALF_STRENGTH_WITHOUT_SLEWRATE_CONTROL = 2u,
536  FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL = 3u
537 } port_slew_rate_control_t;
538 #endif /* FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL */
539 
540 #if FEATURE_PINS_HAS_SLEW_RATE
541 
545 typedef enum
546 {
547  PORT_LOW_SLEW_RATE = 0U,
548  PORT_MEDIUM_SLEW_RATE = 1U,
549  PORT_MEDIUM_SLEW_RATE2 = 2U,
550  PORT_HIGH_SLEW_RATE = 3U
551 } port_slew_rate_t;
552 #endif
553 
554 #endif /* FEATURE_PINS_DRIVER_USING_SIUL2 */
555 
562 typedef struct
563 {
564 #ifdef FEATURE_PINS_DRIVER_USING_PORT
566 #elif defined FEATURE_PINS_DRIVER_USING_SIUL2
567  SIUL2_Type * base;
568 #endif
569  uint32_t pinPortIdx;
570 #if FEATURE_PINS_HAS_PULL_SELECTION
572 #endif
573 #if FEATURE_PINS_HAS_SLEW_RATE
574  port_slew_rate_t rateSelect;
575 #endif
576 #if FEATURE_PORT_HAS_PASSIVE_FILTER
578 #endif
579 #if FEATURE_PINS_HAS_OPEN_DRAIN
580  port_open_drain_t openDrain;
581 #endif
582 #if FEATURE_PINS_HAS_DRIVE_STRENGTH
584 #endif
586 #if FEATURE_PORT_HAS_PIN_CONTROL_LOCK
587  bool pinLock;
588 #endif
589 #ifdef FEATURE_PINS_DRIVER_USING_PORT
593 #if FEATURE_PINS_HAS_OVER_CURRENT
594  bool clearOCurFlag;
595  port_over_current_config_t overCurConfig;
596 #endif
597 #endif
600 #ifdef FEATURE_PINS_DRIVER_USING_SIUL2
601  port_input_mux_t inputMux[FEATURE_SIUL2_INPUT_MUX_WIDTH];
602 #if FEATURE_SIUL2_HAS_INVERT_DATA_INPUT
603  port_invert_input_t inputInvert[FEATURE_SIUL2_INPUT_MUX_WIDTH];
604 #endif /* FEATURE_SIUL2_HAS_INVERT_DATA_INPUT */
605  uint32_t inputMuxReg[FEATURE_SIUL2_INPUT_MUX_WIDTH];
606  port_output_buffer_t outputBuffer;
607  port_input_buffer_t inputBuffer;
608  siul2_interrupt_config_t intConfig;
609 #if FEATURE_SIUL2_HAS_SAFE_MODE_CONTROL
610  port_safe_mode_t safeMode;
611 #endif /* FEATURE_SIUL2_HAS_SAFE_MODE_CONTROL */
612 #if FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL
613  port_slew_rate_control_t slewRateCtrlSel;
614 #endif /* FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL */
615 #if FEATURE_SIUL2_HAS_HYSTERESIS
616  port_hysteresis_t hysteresisSelect;
617 #endif /* FEATURE_SIUL2_HAS_HYSTERESIS */
618 #if FEATURE_SIUL2_HAS_DDR_PAD
619  pin_ddr_config_t ddrConfiguration;
620  port_ddr_input_t inputMode;
621  port_on_die_termination_t odtSelect;
622 #endif /* FEATURE_SIUL2_HAS_DDR_PAD */
623 #if FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT
624  port_invert_output_t invertOutput;
625 #endif /* FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT */
626 #if FEATURE_SIUL2_HAS_PULL_KEEPER
627  port_pull_keep_t pullKeepEnable;
628  port_pull_keeper_select_t pullKeepSelect;
629  port_pull_up_down_t pullSelect;
630 #endif /* FEATURE_SIUL2_HAS_PULL_KEEPER */
631 #if FEATURE_SIUL2_HAS_ANALOG_PAD
632  port_analog_pad_t analogPadCtrlSel;
633 #endif /* FEATURE_SIUL2_HAS_ANALOG_PAD */
634 #endif /* FEATURE_PINS_DRIVER_USING_SIUL2 */
637 
638 /*******************************************************************************
639  * API
640  ******************************************************************************/
646 #if defined(__cplusplus)
647 extern "C" {
648 #endif
649 
660 status_t PINS_DRV_Init(uint32_t pinCount,
661  const pin_settings_config_t config[]);
662 
663 #ifdef FEATURE_PINS_DRIVER_USING_PORT
664 #if FEATURE_PINS_HAS_PULL_SELECTION
665 
674 void PINS_DRV_SetPullSel(PORT_Type * const base,
675  uint32_t pin,
676  port_pull_config_t pullConfig);
677 
678 #endif /* FEATURE_PINS_HAS_PULL_SELECTION */
679 
689 void PINS_DRV_SetMuxModeSel(PORT_Type * const base,
690  uint32_t pin,
691  port_mux_t mux);
692 
702 void PINS_DRV_SetPinIntSel(PORT_Type * const base,
703  uint32_t pin,
705 
716  uint32_t pin);
717 
726 void PINS_DRV_ClearPinIntFlagCmd(PORT_Type * const base,
727  uint32_t pin);
728 
737 void PINS_DRV_EnableDigitalFilter(PORT_Type * const base,
738  uint32_t pin);
739 
748 void PINS_DRV_DisableDigitalFilter(PORT_Type * const base,
749  uint32_t pin);
750 
761 void PINS_DRV_ConfigDigitalFilter(PORT_Type * const base,
762  const port_digital_filter_config_t * const config);
763 
772 uint32_t PINS_DRV_GetPortIntFlag(const PORT_Type * const base);
773 
781 void PINS_DRV_ClearPortIntFlagCmd(PORT_Type * const base);
782 
800 void PINS_DRV_SetGlobalPinControl(PORT_Type * const base,
801  uint16_t pins,
802  uint16_t value,
803  port_global_control_pins_t halfPort);
804 
822 void PINS_DRV_SetGlobalIntControl(PORT_Type * const base,
823  uint16_t pins,
824  uint16_t value,
825  port_global_control_pins_t halfPort);
826 
827 #if FEATURE_PINS_HAS_OVER_CURRENT
828 
836 uint32_t PINS_DRV_GetOverCurPortIntFlag(const PORT_Type * const base);
837 
845 void PINS_DRV_ClearOverCurPortIntFlag(PORT_Type * const base);
846 #endif /* FEATURE_PINS_HAS_OVER_CURRENT */
847 
862 
880 void PINS_DRV_SetPinDirection(GPIO_Type * const base,
882  pins_level_type_t direction);
883 
902 void PINS_DRV_SetPinsDirection(GPIO_Type * const base,
903  pins_channel_type_t pins);
904 
905 #if FEATURE_PORT_HAS_INPUT_DISABLE
906 
920 void PINS_DRV_SetPortInputDisable(GPIO_Type * const base,
921  pins_channel_type_t pins);
922 
936 pins_channel_type_t PINS_DRV_GetPortInputDisable(const GPIO_Type * const base);
937 #endif /* FEATURE_PORT_HAS_INPUT_DISABLE */
938 
939 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
940 #if FEATURE_PINS_HAS_PULL_SELECTION
941 
950 void PINS_DRV_SetPullSel(PORT_Type * const base,
951  uint16_t pin,
952  port_pull_config_t pullConfig);
953 
954 #endif /* FEATURE_PINS_HAS_PULL_SELECTION */
955 
966 void PINS_DRV_SetOutputBuffer(PORT_Type * const base,
967  uint16_t pin,
968  bool enable,
969  port_mux_t mux);
970 
982 void PINS_DRV_SetInputBuffer(PORT_Type * const base,
983  uint16_t pin,
984  bool enable,
985  uint32_t inputMuxReg,
986  port_input_mux_t inputMux);
987 
995 void PINS_DRV_ConfigIntFilterClock(uint8_t prescaler);
996 
1004 void PINS_DRV_SetExInt(siul2_interrupt_config_t intConfig);
1005 
1013 void PINS_DRV_ClearPinExIntFlag(uint32_t eirqPinIdx);
1014 
1023 bool PINS_DRV_GetPinExIntFlag(uint32_t eirqPinIdx);
1024 
1030 void PINS_DRV_ClearExIntFlag(void);
1031 
1039 uint32_t PINS_DRV_GetExIntFlag(void);
1040 
1041 #endif /* FEATURE_PINS_DRIVER_USING_PORT */
1042 
1055 void PINS_DRV_WritePin(GPIO_Type * const base,
1056  pins_channel_type_t pin,
1057  pins_level_type_t value);
1058 
1070 void PINS_DRV_WritePins(GPIO_Type * const base,
1071  pins_channel_type_t pins);
1072 
1086 
1100 void PINS_DRV_SetPins(GPIO_Type * const base,
1101  pins_channel_type_t pins);
1102 
1116 void PINS_DRV_ClearPins(GPIO_Type * const base,
1117  pins_channel_type_t pins);
1118 
1131 void PINS_DRV_TogglePins(GPIO_Type * const base,
1132  pins_channel_type_t pins);
1133 
1146 pins_channel_type_t PINS_DRV_ReadPins(const GPIO_Type * const base);
1147 
1150 #if defined(__cplusplus)
1151 }
1152 #endif
1153 
1156 #endif /* PINS_DRIVER_H */
1157 /*******************************************************************************
1158  * EOF
1159  ******************************************************************************/
rtc_interrupt_config_t * intConfig
Definition: rtc_driver.c:78
status_t PINS_DRV_Init(uint32_t pinCount, const pin_settings_config_t config[])
Initializes the pins with the given configuration structure.
Definition: pins_driver.c:53
The digital filter configuration Implements : port_digital_filter_config_t_Class. ...
Definition: pins_driver.h:188
void PINS_DRV_SetGlobalIntControl(PORT_Type *const base, uint16_t pins, uint16_t value, port_global_control_pins_t halfPort)
Quickly configures multiple pins with the same interrupt configuration.
Definition: pins_driver.c:312
port_global_control_pins_t
The port global pin/interuppt control registers Implements : port_global_control_pins_t_Class.
Definition: pins_driver.h:198
uint32_t PINS_DRV_GetPortIntFlag(const PORT_Type *const base)
Reads the entire port interrupt status flag.
Definition: pins_driver.c:191
uint32_t pins_channel_type_t
Type of a GPIO channel representation Implements : pins_channel_type_t_Class.
Definition: pins_driver.h:41
port_pull_config_t pullConfig
Definition: pins_driver.h:571
port_interrupt_config_t intConfig
Definition: pins_driver.h:590
port_digital_filter_clock_t
Clock source for the digital input filters Implements : port_digital_filter_clock_t_Class.
Definition: pins_driver.h:178
void PINS_DRV_DisableDigitalFilter(PORT_Type *const base, uint32_t pin)
Disables digital filter for digital pin muxing.
Definition: pins_driver.c:164
void PINS_DRV_ClearPinIntFlagCmd(PORT_Type *const base, uint32_t pin)
Clears the individual pin-interrupt status flag.
Definition: pins_driver.c:137
port_drive_strength_t
Configures the drive strength. Implements : port_drive_strength_t_Class.
Definition: pins_driver.h:99
pins_channel_type_t PINS_DRV_GetPinsOutput(const GPIO_Type *const base)
Get the current output from a port.
Definition: pins_driver.c:506
port_interrupt_config_t
Configures the interrupt generation condition. Implements : port_interrupt_config_t_Class.
Definition: pins_driver.h:140
void PINS_DRV_SetPullSel(PORT_Type *const base, uint32_t pin, port_pull_config_t pullConfig)
Configures the internal resistor.
Definition: pins_driver.c:80
port_mux_t mux
Pin (C55: Out) mux selection.
Definition: pins_driver.h:585
void PINS_DRV_WritePin(GPIO_Type *const base, pins_channel_type_t pin, pins_level_type_t value)
Write a pin of a port with a given value.
Definition: pins_driver.c:477
void PINS_DRV_TogglePins(GPIO_Type *const base, pins_channel_type_t pins)
Toggle pins value.
Definition: pins_driver.c:549
GPIO_Type * gpioBase
Definition: pins_driver.h:598
void PINS_DRV_SetPinDirection(GPIO_Type *const base, pins_channel_type_t pin, pins_level_type_t direction)
Configure the direction for a certain pin from a port.
Definition: pins_driver.c:231
port_drive_strength_t driveSelect
Configures the drive strength.
Definition: pins_driver.h:583
void PINS_DRV_WritePins(GPIO_Type *const base, pins_channel_type_t pins)
Write all pins of a port.
Definition: pins_driver.c:492
void PINS_DRV_SetPinsDirection(GPIO_Type *const base, pins_channel_type_t pins)
Set the pins directions configuration for a port.
Definition: pins_driver.c:248
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
port_data_direction_t
Configures the port data direction Implements : port_data_direction_t_Class.
Definition: pins_driver.h:62
port_pull_config_t
Internal resistor pull feature selection Implements : port_pull_config_t_Class.
Definition: pins_driver.h:74
void PINS_DRV_EnableDigitalFilter(PORT_Type *const base, uint32_t pin)
Enables digital filter for digital pin muxing.
Definition: pins_driver.c:150
Defines the converter configuration.
Definition: pins_driver.h:562
void PINS_DRV_SetPins(GPIO_Type *const base, pins_channel_type_t pins)
Write pins with 'Set' value.
Definition: pins_driver.c:520
void PINS_DRV_ConfigDigitalFilter(PORT_Type *const base, const port_digital_filter_config_t *const config)
Configures digital filter for port with given configuration.
Definition: pins_driver.c:178
port_mux_t
Configures the Pin mux selection Implements : port_mux_t_Class.
Definition: pins_driver.h:124
void PINS_DRV_SetGlobalPinControl(PORT_Type *const base, uint16_t pins, uint16_t value, port_global_control_pins_t halfPort)
Quickly configures multiple pins with the same pin configuration.
Definition: pins_driver.c:295
pins_level_type_t initValue
Definition: pins_driver.h:635
pins_channel_type_t PINS_DRV_ReadPins(const GPIO_Type *const base)
Read input pins.
Definition: pins_driver.c:563
port_data_direction_t direction
Definition: pins_driver.h:599
pins_channel_type_t PINS_DRV_GetPinsDirection(const GPIO_Type *const base)
Get the pins directions configuration for a port.
Definition: pins_driver.c:217
uint8_t pins_level_type_t
Type of a port levels representation. Implements : pins_level_type_t_Class.
Definition: pins_driver.h:56
port_interrupt_config_t PINS_DRV_GetPinIntSel(const PORT_Type *const base, uint32_t pin)
Gets the current port pin interrupt/DMA request configuration.
Definition: pins_driver.c:124
void PINS_DRV_SetMuxModeSel(PORT_Type *const base, uint32_t pin, port_mux_t mux)
Configures the pin muxing.
Definition: pins_driver.c:96
void PINS_DRV_ClearPortIntFlagCmd(PORT_Type *const base)
Clears the entire port interrupt status flag.
Definition: pins_driver.c:203
port_digital_filter_clock_t clock
Definition: pins_driver.h:190
void PINS_DRV_SetPinIntSel(PORT_Type *const base, uint32_t pin, port_interrupt_config_t intConfig)
Configures the port pin interrupt/DMA request.
Definition: pins_driver.c:110
void PINS_DRV_ClearPins(GPIO_Type *const base, pins_channel_type_t pins)
Write pins to 'Clear' value.
Definition: pins_driver.c:535