47 #if (defined (TIMING_OVER_LPIT))
49 #if (FEATURE_LPIT_HAS_NUM_IRQS_CHANS == 1)
50 void LPIT0_IRQHandler(
void)
60 TIMING_Lpit_IrqHandler(0U, 0U);
65 TIMING_Lpit_IrqHandler(0U, 1U);
70 TIMING_Lpit_IrqHandler(0U, 2U);
75 TIMING_Lpit_IrqHandler(0U, 3U);
79 void LPIT0_Ch0_IRQHandler(
void)
81 TIMING_Lpit_IrqHandler(0U, 0U);
84 void LPIT0_Ch1_IRQHandler(
void)
86 TIMING_Lpit_IrqHandler(0U, 1U);
89 void LPIT0_Ch2_IRQHandler(
void)
91 TIMING_Lpit_IrqHandler(0U, 2U);
94 void LPIT0_Ch3_IRQHandler(
void)
96 TIMING_Lpit_IrqHandler(0U, 3U);
103 #if (defined (TIMING_OVER_LPTMR))
105 void LPTMR0_IRQHandler(
void)
107 TIMING_Lptmr_IrqHandler(0U, 0U);
113 #if (defined(TIMING_OVER_PIT))
115 void PIT_Ch0_IRQHandler(
void)
117 TIMING_Pit_IrqHandler(0U, 0U);
120 void PIT_Ch1_IRQHandler(
void)
122 TIMING_Pit_IrqHandler(0U, 1U);
125 void PIT_Ch2_IRQHandler(
void)
127 TIMING_Pit_IrqHandler(0U, 2U);
130 void PIT_Ch3_IRQHandler(
void)
132 TIMING_Pit_IrqHandler(0U, 3U);
134 #if (PIT_TIMER_COUNT > 4U)
135 void PIT_Ch4_IRQHandler(
void)
137 TIMING_Pit_IrqHandler(0U, 4U);
140 void PIT_Ch5_IRQHandler(
void)
142 TIMING_Pit_IrqHandler(0U, 5U);
145 void PIT_Ch6_IRQHandler(
void)
147 TIMING_Pit_IrqHandler(0U, 6U);
150 void PIT_Ch7_IRQHandler(
void)
152 TIMING_Pit_IrqHandler(0U, 7U);
155 void PIT_Ch8_IRQHandler(
void)
157 TIMING_Pit_IrqHandler(0U, 8U);
160 void PIT_Ch9_IRQHandler(
void)
162 TIMING_Pit_IrqHandler(0U, 9U);
165 void PIT_Ch10_IRQHandler(
void)
167 TIMING_Pit_IrqHandler(0U, 10U);
170 void PIT_Ch11_IRQHandler(
void)
172 TIMING_Pit_IrqHandler(0U, 11U);
175 void PIT_Ch12_IRQHandler(
void)
177 TIMING_Pit_IrqHandler(0U, 12U);
180 void PIT_Ch13_IRQHandler(
void)
182 TIMING_Pit_IrqHandler(0U, 13U);
185 void PIT_Ch14_IRQHandler(
void)
187 TIMING_Pit_IrqHandler(0U, 14U);
190 void PIT_Ch15_IRQHandler(
void)
192 TIMING_Pit_IrqHandler(0U, 15U);
199 #if (defined(TIMING_OVER_FTM))
201 #if (FTM_INSTANCE_COUNT > 0U)
202 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
203 void FTM0_Ch0_7_IrqHandler(
void)
205 const FTM_Type *
const base = ftmBase[0];
215 if (chan0IntFlag && g_ftmChannelRunning[0][0])
217 TIMING_Ftm_IrqHandler(0U, 0U);
220 if (chan1IntFlag && g_ftmChannelRunning[0][1])
222 TIMING_Ftm_IrqHandler(0U, 1U);
225 if (chan2IntFlag && g_ftmChannelRunning[0][2])
227 TIMING_Ftm_IrqHandler(0U, 2U);
230 if (chan3IntFlag && g_ftmChannelRunning[0][3])
232 TIMING_Ftm_IrqHandler(0U, 3U);
235 if (chan4IntFlag && g_ftmChannelRunning[0][4])
237 TIMING_Ftm_IrqHandler(0U, 4U);
240 if (chan5IntFlag && g_ftmChannelRunning[0][5])
242 TIMING_Ftm_IrqHandler(0U, 5U);
245 if (chan6IntFlag && g_ftmChannelRunning[0][6])
247 TIMING_Ftm_IrqHandler(0U, 6U);
250 if (chan7IntFlag && g_ftmChannelRunning[0][7])
252 TIMING_Ftm_IrqHandler(0U, 7U);
256 void FTM0_Ch0_Ch1_IrqHandler(
void)
258 const FTM_Type *
const base = ftmBase[0];
262 if (chan0IntFlag && g_ftmChannelRunning[0][0])
264 TIMING_Ftm_IrqHandler(0U, 0U);
267 if (chan1IntFlag && g_ftmChannelRunning[0][1])
269 TIMING_Ftm_IrqHandler(0U, 1U);
273 void FTM0_Ch2_Ch3_IrqHandler(
void)
275 const FTM_Type *
const base = ftmBase[0];
279 if (chan2IntFlag && g_ftmChannelRunning[0][2])
281 TIMING_Ftm_IrqHandler(0U, 2U);
284 if (chan3IntFlag && g_ftmChannelRunning[0][3])
286 TIMING_Ftm_IrqHandler(0U, 3U);
290 void FTM0_Ch4_Ch5_IrqHandler(
void)
292 const FTM_Type *
const base = ftmBase[0];
296 if (chan4IntFlag && g_ftmChannelRunning[0][4])
298 TIMING_Ftm_IrqHandler(0U, 4U);
301 if (chan5IntFlag && g_ftmChannelRunning[0][5])
303 TIMING_Ftm_IrqHandler(0U, 5U);
307 void FTM0_Ch6_Ch7_IrqHandler(
void)
309 const FTM_Type *
const base = ftmBase[0];
313 if (chan6IntFlag && g_ftmChannelRunning[0][6])
315 TIMING_Ftm_IrqHandler(0U, 6U);
318 if (chan7IntFlag && g_ftmChannelRunning[0][7])
320 TIMING_Ftm_IrqHandler(0U, 7U);
326 #if (FTM_INSTANCE_COUNT > 1U)
327 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
328 void FTM1_Ch0_7_IrqHandler(
void)
330 const FTM_Type *
const base = ftmBase[1];
340 if (chan0IntFlag && g_ftmChannelRunning[1][0])
342 TIMING_Ftm_IrqHandler(1U, 0U);
345 if (chan1IntFlag && g_ftmChannelRunning[1][1])
347 TIMING_Ftm_IrqHandler(1U, 1U);
350 if (chan2IntFlag && g_ftmChannelRunning[1][2])
352 TIMING_Ftm_IrqHandler(1U, 2U);
355 if (chan3IntFlag && g_ftmChannelRunning[1][3])
357 TIMING_Ftm_IrqHandler(1U, 3U);
360 if (chan4IntFlag && g_ftmChannelRunning[1][4])
362 TIMING_Ftm_IrqHandler(1U, 4U);
365 if (chan5IntFlag && g_ftmChannelRunning[1][5])
367 TIMING_Ftm_IrqHandler(1U, 5U);
370 if (chan6IntFlag && g_ftmChannelRunning[1][6])
372 TIMING_Ftm_IrqHandler(1U, 6U);
375 if (chan7IntFlag && g_ftmChannelRunning[1][7])
377 TIMING_Ftm_IrqHandler(1U, 7U);
381 void FTM1_Ch0_Ch1_IrqHandler(
void)
383 const FTM_Type *
const base = ftmBase[1];
387 if (chan0IntFlag && g_ftmChannelRunning[1][0])
389 TIMING_Ftm_IrqHandler(1U, 0U);
392 if (chan1IntFlag && g_ftmChannelRunning[1][1])
394 TIMING_Ftm_IrqHandler(1U, 1U);
398 void FTM1_Ch2_Ch3_IrqHandler(
void)
400 const FTM_Type *
const base = ftmBase[1];
404 if (chan2IntFlag && g_ftmChannelRunning[1][2])
406 TIMING_Ftm_IrqHandler(1U, 2U);
409 if (chan3IntFlag && g_ftmChannelRunning[1][3])
411 TIMING_Ftm_IrqHandler(1U, 3U);
415 void FTM1_Ch4_Ch5_IrqHandler(
void)
417 const FTM_Type *
const base = ftmBase[1];
421 if (chan4IntFlag && g_ftmChannelRunning[1][4])
423 TIMING_Ftm_IrqHandler(1U, 4U);
426 if (chan5IntFlag && g_ftmChannelRunning[1][5])
428 TIMING_Ftm_IrqHandler(1U, 5U);
432 void FTM1_Ch6_Ch7_IrqHandler(
void)
434 const FTM_Type *
const base = ftmBase[1];
438 if (chan6IntFlag && g_ftmChannelRunning[1][6])
440 TIMING_Ftm_IrqHandler(1U, 6U);
443 if (chan7IntFlag && g_ftmChannelRunning[1][7])
445 TIMING_Ftm_IrqHandler(1U, 7U);
451 #if (FTM_INSTANCE_COUNT > 2U)
452 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
453 void FTM2_Ch0_7_IrqHandler(
void)
455 const FTM_Type *
const base = ftmBase[2];
465 if (chan0IntFlag && g_ftmChannelRunning[2][0])
467 TIMING_Ftm_IrqHandler(2U, 0U);
470 if (chan1IntFlag && g_ftmChannelRunning[2][1])
472 TIMING_Ftm_IrqHandler(2U, 1U);
475 if (chan2IntFlag && g_ftmChannelRunning[2][2])
477 TIMING_Ftm_IrqHandler(2U, 2U);
480 if (chan3IntFlag && g_ftmChannelRunning[2][3])
482 TIMING_Ftm_IrqHandler(2U, 3U);
485 if (chan4IntFlag && g_ftmChannelRunning[2][4])
487 TIMING_Ftm_IrqHandler(2U, 4U);
490 if (chan5IntFlag && g_ftmChannelRunning[2][5])
492 TIMING_Ftm_IrqHandler(2U, 5U);
495 if (chan6IntFlag && g_ftmChannelRunning[2][6])
497 TIMING_Ftm_IrqHandler(2U, 6U);
500 if (chan7IntFlag && g_ftmChannelRunning[2][7])
502 TIMING_Ftm_IrqHandler(2U, 7U);
506 void FTM2_Ch0_Ch1_IrqHandler(
void)
508 const FTM_Type *
const base = ftmBase[2];
512 if (chan0IntFlag && g_ftmChannelRunning[2][0])
514 TIMING_Ftm_IrqHandler(2U, 0U);
517 if (chan1IntFlag && g_ftmChannelRunning[2][1])
519 TIMING_Ftm_IrqHandler(2U, 1U);
523 void FTM2_Ch2_Ch3_IrqHandler(
void)
525 const FTM_Type *
const base = ftmBase[2];
529 if (chan2IntFlag && g_ftmChannelRunning[2][2])
531 TIMING_Ftm_IrqHandler(2U, 2U);
534 if (chan3IntFlag && g_ftmChannelRunning[2][3])
536 TIMING_Ftm_IrqHandler(2U, 3U);
540 void FTM2_Ch4_Ch5_IrqHandler(
void)
542 const FTM_Type *
const base = ftmBase[2];
546 if (chan4IntFlag && g_ftmChannelRunning[2][4])
548 TIMING_Ftm_IrqHandler(2U, 4U);
551 if (chan5IntFlag && g_ftmChannelRunning[2][5])
553 TIMING_Ftm_IrqHandler(2U, 5U);
557 void FTM2_Ch6_Ch7_IrqHandler(
void)
559 const FTM_Type *
const base = ftmBase[2];
563 if (chan6IntFlag && g_ftmChannelRunning[2][6])
565 TIMING_Ftm_IrqHandler(2U, 6U);
568 if (chan7IntFlag && g_ftmChannelRunning[2][7])
570 TIMING_Ftm_IrqHandler(2U, 7U);
576 #if (FTM_INSTANCE_COUNT > 3U)
577 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
578 void FTM3_Ch0_7_IrqHandler(
void)
580 const FTM_Type *
const base = ftmBase[3];
590 if (chan0IntFlag && g_ftmChannelRunning[3][0])
592 TIMING_Ftm_IrqHandler(3U, 0U);
595 if (chan1IntFlag && g_ftmChannelRunning[3][1])
597 TIMING_Ftm_IrqHandler(3U, 1U);
600 if (chan2IntFlag && g_ftmChannelRunning[3][2])
602 TIMING_Ftm_IrqHandler(3U, 2U);
605 if (chan3IntFlag && g_ftmChannelRunning[3][3])
607 TIMING_Ftm_IrqHandler(3U, 3U);
610 if (chan4IntFlag && g_ftmChannelRunning[3][4])
612 TIMING_Ftm_IrqHandler(3U, 4U);
615 if (chan5IntFlag && g_ftmChannelRunning[3][5])
617 TIMING_Ftm_IrqHandler(3U, 5U);
620 if (chan6IntFlag && g_ftmChannelRunning[3][6])
622 TIMING_Ftm_IrqHandler(3U, 6U);
625 if (chan7IntFlag && g_ftmChannelRunning[3][7])
627 TIMING_Ftm_IrqHandler(3U, 7U);
631 void FTM3_Ch0_Ch1_IrqHandler(
void)
633 const FTM_Type *
const base = ftmBase[3];
637 if (chan0IntFlag && g_ftmChannelRunning[3][0])
639 TIMING_Ftm_IrqHandler(3U, 0U);
642 if (chan1IntFlag && g_ftmChannelRunning[3][1])
644 TIMING_Ftm_IrqHandler(3U, 1U);
648 void FTM3_Ch2_Ch3_IrqHandler(
void)
650 const FTM_Type *
const base = ftmBase[3];
654 if (chan2IntFlag && g_ftmChannelRunning[3][2])
656 TIMING_Ftm_IrqHandler(3U, 2U);
659 if (chan3IntFlag && g_ftmChannelRunning[3][3])
661 TIMING_Ftm_IrqHandler(3U, 3U);
665 void FTM3_Ch4_Ch5_IrqHandler(
void)
667 const FTM_Type *
const base = ftmBase[3];
671 if (chan4IntFlag && g_ftmChannelRunning[3][4])
673 TIMING_Ftm_IrqHandler(3U, 4U);
676 if (chan5IntFlag && g_ftmChannelRunning[3][5])
678 TIMING_Ftm_IrqHandler(3U, 5U);
682 void FTM3_Ch6_Ch7_IrqHandler(
void)
684 const FTM_Type *
const base = ftmBase[3];
688 if (chan6IntFlag && g_ftmChannelRunning[3][6])
690 TIMING_Ftm_IrqHandler(3U, 6U);
693 if (chan7IntFlag && g_ftmChannelRunning[3][7])
695 TIMING_Ftm_IrqHandler(3U, 7U);
701 #if (FTM_INSTANCE_COUNT > 4U)
702 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
703 void FTM4_Ch0_7_IrqHandler(
void)
705 const FTM_Type *
const base = ftmBase[4];
715 if (chan0IntFlag && g_ftmChannelRunning[4][0])
717 TIMING_Ftm_IrqHandler(4U, 0U);
720 if (chan1IntFlag && g_ftmChannelRunning[4][1])
722 TIMING_Ftm_IrqHandler(4U, 1U);
725 if (chan2IntFlag && g_ftmChannelRunning[4][2])
727 TIMING_Ftm_IrqHandler(4U, 2U);
730 if (chan3IntFlag && g_ftmChannelRunning[4][3])
732 TIMING_Ftm_IrqHandler(4U, 3U);
735 if (chan4IntFlag && g_ftmChannelRunning[4][4])
737 TIMING_Ftm_IrqHandler(4U, 4U);
740 if (chan5IntFlag && g_ftmChannelRunning[4][5])
742 TIMING_Ftm_IrqHandler(4U, 5U);
745 if (chan6IntFlag && g_ftmChannelRunning[4][6])
747 TIMING_Ftm_IrqHandler(4U, 6U);
750 if (chan7IntFlag && g_ftmChannelRunning[4][7])
752 TIMING_Ftm_IrqHandler(4U, 7U);
756 void FTM4_Ch0_Ch1_IrqHandler(
void)
758 const FTM_Type *
const base = ftmBase[4];
762 if (chan0IntFlag && g_ftmChannelRunning[4][0])
764 TIMING_Ftm_IrqHandler(4U, 0U);
767 if (chan1IntFlag && g_ftmChannelRunning[4][1])
769 TIMING_Ftm_IrqHandler(4U, 1U);
773 void FTM4_Ch2_Ch3_IrqHandler(
void)
775 const FTM_Type *
const base = ftmBase[4];
779 if (chan2IntFlag && g_ftmChannelRunning[4][2])
781 TIMING_Ftm_IrqHandler(4U, 2U);
784 if (chan3IntFlag && g_ftmChannelRunning[4][3])
786 TIMING_Ftm_IrqHandler(4U, 3U);
790 void FTM4_Ch4_Ch5_IrqHandler(
void)
792 const FTM_Type *
const base = ftmBase[4];
796 if (chan4IntFlag && g_ftmChannelRunning[4][4])
798 TIMING_Ftm_IrqHandler(4U, 4U);
801 if (chan5IntFlag && g_ftmChannelRunning[4][5])
803 TIMING_Ftm_IrqHandler(4U, 5U);
807 void FTM4_Ch6_Ch7_IrqHandler(
void)
809 const FTM_Type *
const base = ftmBase[4];
813 if (chan6IntFlag && g_ftmChannelRunning[4][6])
815 TIMING_Ftm_IrqHandler(4U, 6U);
818 if (chan7IntFlag && g_ftmChannelRunning[4][7])
820 TIMING_Ftm_IrqHandler(4U, 7U);
826 #if (FTM_INSTANCE_COUNT > 5U)
827 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
828 void FTM5_Ch0_7_IrqHandler(
void)
830 const FTM_Type *
const base = ftmBase[5];
840 if (chan0IntFlag && g_ftmChannelRunning[5][0])
842 TIMING_Ftm_IrqHandler(5U, 0U);
845 if (chan1IntFlag && g_ftmChannelRunning[5][1])
847 TIMING_Ftm_IrqHandler(5U, 1U);
850 if (chan2IntFlag && g_ftmChannelRunning[5][2])
852 TIMING_Ftm_IrqHandler(5U, 2U);
855 if (chan3IntFlag && g_ftmChannelRunning[5][3])
857 TIMING_Ftm_IrqHandler(5U, 3U);
860 if (chan4IntFlag && g_ftmChannelRunning[5][4])
862 TIMING_Ftm_IrqHandler(5U, 4U);
865 if (chan5IntFlag && g_ftmChannelRunning[5][5])
867 TIMING_Ftm_IrqHandler(5U, 5U);
870 if (chan6IntFlag && g_ftmChannelRunning[5][6])
872 TIMING_Ftm_IrqHandler(5U, 6U);
875 if (chan7IntFlag && g_ftmChannelRunning[5][7])
877 TIMING_Ftm_IrqHandler(5U, 7U);
881 void FTM5_Ch0_Ch1_IrqHandler(
void)
883 const FTM_Type *
const base = ftmBase[5];
887 if (chan0IntFlag && g_ftmChannelRunning[5][0])
889 TIMING_Ftm_IrqHandler(5U, 0U);
892 if (chan1IntFlag && g_ftmChannelRunning[5][1])
894 TIMING_Ftm_IrqHandler(5U, 1U);
898 void FTM5_Ch2_Ch3_IrqHandler(
void)
900 const FTM_Type *
const base = ftmBase[5];
904 if (chan2IntFlag && g_ftmChannelRunning[5][2])
906 TIMING_Ftm_IrqHandler(5U, 2U);
909 if (chan3IntFlag && g_ftmChannelRunning[5][3])
911 TIMING_Ftm_IrqHandler(5U, 3U);
915 void FTM5_Ch4_Ch5_IrqHandler(
void)
917 const FTM_Type *
const base = ftmBase[5];
921 if (chan4IntFlag && g_ftmChannelRunning[5][4])
923 TIMING_Ftm_IrqHandler(5U, 4U);
926 if (chan5IntFlag && g_ftmChannelRunning[5][5])
928 TIMING_Ftm_IrqHandler(5U, 5U);
932 void FTM5_Ch6_Ch7_IrqHandler(
void)
934 const FTM_Type *
const base = ftmBase[5];
938 if (chan6IntFlag && g_ftmChannelRunning[5][6])
940 TIMING_Ftm_IrqHandler(5U, 6U);
943 if (chan7IntFlag && g_ftmChannelRunning[5][7])
945 TIMING_Ftm_IrqHandler(5U, 7U);
951 #if (FTM_INSTANCE_COUNT > 6U)
952 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
953 void FTM6_Ch0_7_IrqHandler(
void)
955 const FTM_Type *
const base = ftmBase[6];
965 if (chan0IntFlag && g_ftmChannelRunning[6][0])
967 TIMING_Ftm_IrqHandler(6U, 0U);
970 if (chan1IntFlag && g_ftmChannelRunning[6][1])
972 TIMING_Ftm_IrqHandler(6U, 1U);
975 if (chan2IntFlag && g_ftmChannelRunning[6][2])
977 TIMING_Ftm_IrqHandler(6U, 2U);
980 if (chan3IntFlag && g_ftmChannelRunning[6][3])
982 TIMING_Ftm_IrqHandler(6U, 3U);
985 if (chan4IntFlag && g_ftmChannelRunning[6][4])
987 TIMING_Ftm_IrqHandler(6U, 4U);
990 if (chan5IntFlag && g_ftmChannelRunning[6][5])
992 TIMING_Ftm_IrqHandler(6U, 5U);
995 if (chan6IntFlag && g_ftmChannelRunning[6][6])
997 TIMING_Ftm_IrqHandler(6U, 6U);
1000 if (chan7IntFlag && g_ftmChannelRunning[6][7])
1002 TIMING_Ftm_IrqHandler(6U, 7U);
1006 void FTM6_Ch0_Ch1_IrqHandler(
void)
1008 const FTM_Type *
const base = ftmBase[6];
1012 if (chan0IntFlag && g_ftmChannelRunning[6][0])
1014 TIMING_Ftm_IrqHandler(6U, 0U);
1017 if (chan1IntFlag && g_ftmChannelRunning[6][1])
1019 TIMING_Ftm_IrqHandler(6U, 1U);
1023 void FTM6_Ch2_Ch3_IrqHandler(
void)
1025 const FTM_Type *
const base = ftmBase[6];
1029 if (chan2IntFlag && g_ftmChannelRunning[6][2])
1031 TIMING_Ftm_IrqHandler(6U, 2U);
1034 if (chan3IntFlag && g_ftmChannelRunning[6][3])
1036 TIMING_Ftm_IrqHandler(6U, 3U);
1040 void FTM6_Ch4_Ch5_IrqHandler(
void)
1042 const FTM_Type *
const base = ftmBase[6];
1046 if (chan4IntFlag && g_ftmChannelRunning[6][4])
1048 TIMING_Ftm_IrqHandler(6U, 4U);
1051 if (chan5IntFlag && g_ftmChannelRunning[6][5])
1053 TIMING_Ftm_IrqHandler(6U, 5U);
1057 void FTM6_Ch6_Ch7_IrqHandler(
void)
1059 const FTM_Type *
const base = ftmBase[6];
1063 if (chan6IntFlag && g_ftmChannelRunning[6][6])
1065 TIMING_Ftm_IrqHandler(6U, 6U);
1068 if (chan7IntFlag && g_ftmChannelRunning[6][7])
1070 TIMING_Ftm_IrqHandler(6U, 7U);
1076 #if (FTM_INSTANCE_COUNT > 7U)
1077 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1078 void FTM7_Ch0_7_IrqHandler(
void)
1080 const FTM_Type *
const base = ftmBase[7];
1090 if (chan0IntFlag && g_ftmChannelRunning[7][0])
1092 TIMING_Ftm_IrqHandler(7U, 0U);
1095 if (chan1IntFlag && g_ftmChannelRunning[7][1])
1097 TIMING_Ftm_IrqHandler(7U, 1U);
1100 if (chan2IntFlag && g_ftmChannelRunning[7][2])
1102 TIMING_Ftm_IrqHandler(7U, 2U);
1105 if (chan3IntFlag && g_ftmChannelRunning[7][3])
1107 TIMING_Ftm_IrqHandler(7U, 3U);
1110 if (chan4IntFlag && g_ftmChannelRunning[7][4])
1112 TIMING_Ftm_IrqHandler(7U, 4U);
1115 if (chan5IntFlag && g_ftmChannelRunning[7][5])
1117 TIMING_Ftm_IrqHandler(7U, 5U);
1120 if (chan6IntFlag && g_ftmChannelRunning[7][6])
1122 TIMING_Ftm_IrqHandler(7U, 6U);
1125 if (chan7IntFlag && g_ftmChannelRunning[7][7])
1127 TIMING_Ftm_IrqHandler(7U, 7U);
1131 void FTM7_Ch0_Ch1_IrqHandler(
void)
1133 const FTM_Type *
const base = ftmBase[7];
1137 if (chan0IntFlag && g_ftmChannelRunning[7][0])
1139 TIMING_Ftm_IrqHandler(7U, 0U);
1142 if (chan1IntFlag && g_ftmChannelRunning[7][1])
1144 TIMING_Ftm_IrqHandler(7U, 1U);
1148 void FTM7_Ch2_Ch3_IrqHandler(
void)
1150 const FTM_Type *
const base = ftmBase[7];
1154 if (chan2IntFlag && g_ftmChannelRunning[7][2])
1156 TIMING_Ftm_IrqHandler(7U, 2U);
1159 if (chan3IntFlag && g_ftmChannelRunning[7][3])
1161 TIMING_Ftm_IrqHandler(7U, 3U);
1165 void FTM7_Ch4_Ch5_IrqHandler(
void)
1167 const FTM_Type *
const base = ftmBase[7];
1171 if (chan4IntFlag && g_ftmChannelRunning[7][4])
1173 TIMING_Ftm_IrqHandler(7U, 4U);
1176 if (chan5IntFlag && g_ftmChannelRunning[7][5])
1178 TIMING_Ftm_IrqHandler(7U, 5U);
1182 void FTM7_Ch6_Ch7_IrqHandler(
void)
1184 const FTM_Type *
const base = ftmBase[7];
1188 if (chan6IntFlag && g_ftmChannelRunning[7][6])
1190 TIMING_Ftm_IrqHandler(7U, 6U);
1193 if (chan7IntFlag && g_ftmChannelRunning[7][7])
1195 TIMING_Ftm_IrqHandler(7U, 7U);
1204 #if (FTM_INSTANCE_COUNT > 0U)
1205 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1206 {FTM0_Ch0_7_IrqHandler,
1207 FTM0_Ch0_7_IrqHandler,
1208 FTM0_Ch0_7_IrqHandler,
1209 FTM0_Ch0_7_IrqHandler,
1210 FTM0_Ch0_7_IrqHandler,
1211 FTM0_Ch0_7_IrqHandler,
1212 FTM0_Ch0_7_IrqHandler,
1213 FTM0_Ch0_7_IrqHandler},
1215 {FTM0_Ch0_Ch1_IrqHandler,
1216 FTM0_Ch0_Ch1_IrqHandler,
1217 FTM0_Ch2_Ch3_IrqHandler,
1218 FTM0_Ch2_Ch3_IrqHandler,
1219 FTM0_Ch4_Ch5_IrqHandler,
1220 FTM0_Ch4_Ch5_IrqHandler,
1221 FTM0_Ch6_Ch7_IrqHandler,
1222 FTM0_Ch6_Ch7_IrqHandler},
1226 #if (FTM_INSTANCE_COUNT > 1U)
1227 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1228 {FTM1_Ch0_7_IrqHandler,
1229 FTM1_Ch0_7_IrqHandler,
1230 FTM1_Ch0_7_IrqHandler,
1231 FTM1_Ch0_7_IrqHandler,
1232 FTM1_Ch0_7_IrqHandler,
1233 FTM1_Ch0_7_IrqHandler,
1234 FTM1_Ch0_7_IrqHandler,
1235 FTM1_Ch0_7_IrqHandler},
1237 {FTM1_Ch0_Ch1_IrqHandler,
1238 FTM1_Ch0_Ch1_IrqHandler,
1239 FTM1_Ch2_Ch3_IrqHandler,
1240 FTM1_Ch2_Ch3_IrqHandler,
1241 FTM1_Ch4_Ch5_IrqHandler,
1242 FTM1_Ch4_Ch5_IrqHandler,
1243 FTM1_Ch6_Ch7_IrqHandler,
1244 FTM1_Ch6_Ch7_IrqHandler},
1248 #if (FTM_INSTANCE_COUNT > 2U)
1249 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1250 {FTM2_Ch0_7_IrqHandler,
1251 FTM2_Ch0_7_IrqHandler,
1252 FTM2_Ch0_7_IrqHandler,
1253 FTM2_Ch0_7_IrqHandler,
1254 FTM2_Ch0_7_IrqHandler,
1255 FTM2_Ch0_7_IrqHandler,
1256 FTM2_Ch0_7_IrqHandler,
1257 FTM2_Ch0_7_IrqHandler},
1259 {FTM2_Ch0_Ch1_IrqHandler,
1260 FTM2_Ch0_Ch1_IrqHandler,
1261 FTM2_Ch2_Ch3_IrqHandler,
1262 FTM2_Ch2_Ch3_IrqHandler,
1263 FTM2_Ch4_Ch5_IrqHandler,
1264 FTM2_Ch4_Ch5_IrqHandler,
1265 FTM2_Ch6_Ch7_IrqHandler,
1266 FTM2_Ch6_Ch7_IrqHandler},
1270 #if (FTM_INSTANCE_COUNT > 3U)
1271 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1272 {FTM3_Ch0_7_IrqHandler,
1273 FTM3_Ch0_7_IrqHandler,
1274 FTM3_Ch0_7_IrqHandler,
1275 FTM3_Ch0_7_IrqHandler,
1276 FTM3_Ch0_7_IrqHandler,
1277 FTM3_Ch0_7_IrqHandler,
1278 FTM3_Ch0_7_IrqHandler,
1279 FTM3_Ch0_7_IrqHandler},
1281 {FTM3_Ch0_Ch1_IrqHandler,
1282 FTM3_Ch0_Ch1_IrqHandler,
1283 FTM3_Ch2_Ch3_IrqHandler,
1284 FTM3_Ch2_Ch3_IrqHandler,
1285 FTM3_Ch4_Ch5_IrqHandler,
1286 FTM3_Ch4_Ch5_IrqHandler,
1287 FTM3_Ch6_Ch7_IrqHandler,
1288 FTM3_Ch6_Ch7_IrqHandler},
1292 #if (FTM_INSTANCE_COUNT > 4U)
1293 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1294 {FTM4_Ch0_7_IrqHandler,
1295 FTM4_Ch0_7_IrqHandler,
1296 FTM4_Ch0_7_IrqHandler,
1297 FTM4_Ch0_7_IrqHandler,
1298 FTM4_Ch0_7_IrqHandler,
1299 FTM4_Ch0_7_IrqHandler,
1300 FTM4_Ch0_7_IrqHandler,
1301 FTM4_Ch0_7_IrqHandler},
1303 {FTM4_Ch0_Ch1_IrqHandler,
1304 FTM4_Ch0_Ch1_IrqHandler,
1305 FTM4_Ch2_Ch3_IrqHandler,
1306 FTM4_Ch2_Ch3_IrqHandler,
1307 FTM4_Ch4_Ch5_IrqHandler,
1308 FTM4_Ch4_Ch5_IrqHandler,
1309 FTM4_Ch6_Ch7_IrqHandler,
1310 FTM4_Ch6_Ch7_IrqHandler},
1314 #if (FTM_INSTANCE_COUNT > 5U)
1315 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1316 {FTM5_Ch0_7_IrqHandler,
1317 FTM5_Ch0_7_IrqHandler,
1318 FTM5_Ch0_7_IrqHandler,
1319 FTM5_Ch0_7_IrqHandler,
1320 FTM5_Ch0_7_IrqHandler,
1321 FTM5_Ch0_7_IrqHandler,
1322 FTM5_Ch0_7_IrqHandler,
1323 FTM5_Ch0_7_IrqHandler},
1325 {FTM5_Ch0_Ch1_IrqHandler,
1326 FTM5_Ch0_Ch1_IrqHandler,
1327 FTM5_Ch2_Ch3_IrqHandler,
1328 FTM5_Ch2_Ch3_IrqHandler,
1329 FTM5_Ch4_Ch5_IrqHandler,
1330 FTM5_Ch4_Ch5_IrqHandler,
1331 FTM5_Ch6_Ch7_IrqHandler,
1332 FTM5_Ch6_Ch7_IrqHandler},
1336 #if (FTM_INSTANCE_COUNT > 6U)
1337 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1338 {FTM6_Ch0_7_IrqHandler,
1339 FTM6_Ch0_7_IrqHandler,
1340 FTM6_Ch0_7_IrqHandler,
1341 FTM6_Ch0_7_IrqHandler,
1342 FTM6_Ch0_7_IrqHandler,
1343 FTM6_Ch0_7_IrqHandler,
1344 FTM6_Ch0_7_IrqHandler,
1345 FTM6_Ch0_7_IrqHandler},
1347 {FTM6_Ch0_Ch1_IrqHandler,
1348 FTM6_Ch0_Ch1_IrqHandler,
1349 FTM6_Ch2_Ch3_IrqHandler,
1350 FTM6_Ch2_Ch3_IrqHandler,
1351 FTM6_Ch4_Ch5_IrqHandler,
1352 FTM6_Ch4_Ch5_IrqHandler,
1353 FTM6_Ch6_Ch7_IrqHandler,
1354 FTM6_Ch6_Ch7_IrqHandler},
1358 #if (FTM_INSTANCE_COUNT > 7U)
1359 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
1360 {FTM7_Ch0_7_IrqHandler,
1361 FTM7_Ch0_7_IrqHandler,
1362 FTM7_Ch0_7_IrqHandler,
1363 FTM7_Ch0_7_IrqHandler,
1364 FTM7_Ch0_7_IrqHandler,
1365 FTM7_Ch0_7_IrqHandler,
1366 FTM7_Ch0_7_IrqHandler,
1367 FTM7_Ch0_7_IrqHandler},
1369 {FTM7_Ch0_Ch1_IrqHandler,
1370 FTM7_Ch0_Ch1_IrqHandler,
1371 FTM7_Ch2_Ch3_IrqHandler,
1372 FTM7_Ch2_Ch3_IrqHandler,
1373 FTM7_Ch4_Ch5_IrqHandler,
1374 FTM7_Ch4_Ch5_IrqHandler,
1375 FTM7_Ch6_Ch7_IrqHandler,
1376 FTM7_Ch6_Ch7_IrqHandler},
1384 #if (defined (TIMING_OVER_STM))
1386 #if (STM_INSTANCE_COUNT > 0U)
1387 void STM0_Ch0_IRQHandler(
void)
1389 TIMING_Stm_IrqHandler(0U, 0U);
1392 void STM0_Ch1_IRQHandler(
void)
1394 TIMING_Stm_IrqHandler(0U, 1U);
1397 void STM0_Ch2_IRQHandler(
void)
1399 TIMING_Stm_IrqHandler(0U, 2U);
1402 void STM0_Ch3_IRQHandler(
void)
1404 TIMING_Stm_IrqHandler(0U, 3U);
1408 #if (STM_INSTANCE_COUNT > 1U)
1409 void STM1_Ch0_IRQHandler(
void)
1411 TIMING_Stm_IrqHandler(1U, 0U);
1414 void STM1_Ch1_IRQHandler(
void)
1416 TIMING_Stm_IrqHandler(1U, 1U);
1419 void STM1_Ch2_IRQHandler(
void)
1421 TIMING_Stm_IrqHandler(1U, 2U);
1424 void STM1_Ch3_IRQHandler(
void)
1426 TIMING_Stm_IrqHandler(1U, 3U);
1430 #if (STM_INSTANCE_COUNT > 2U)
1431 void STM2_Ch0_IRQHandler(
void)
1433 TIMING_Stm_IrqHandler(2U, 0U);
1436 void STM2_Ch1_IRQHandler(
void)
1438 TIMING_Stm_IrqHandler(2U, 1U);
1441 void STM2_Ch2_IRQHandler(
void)
1443 TIMING_Stm_IrqHandler(2U, 2U);
1446 void STM2_Ch3_IRQHandler(
void)
1448 TIMING_Stm_IrqHandler(2U, 3U);
#define FTM_CONTROLS_COUNT
#define LPIT_MSR_TIF1_MASK
#define LPIT_MSR_TIF3_MASK
static bool FTM_DRV_GetChnEventStatus(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel event status.
#define LPIT_MSR_TIF2_MASK
#define LPIT_MSR_TIF0_MASK
#define FTM_INSTANCE_COUNT
uint32_t LPIT_DRV_GetInterruptFlagTimerChannels(uint32_t instance, uint32_t mask)
Gets the current interrupt flag of timer channels.
void(* isr_t)(void)
Interrupt handler type.