52 #include "sim_hw_access.h"
53 #include "scg_hw_access.h"
54 #include "pcc_hw_access.h"
55 #include "pmc_hw_access.h"
56 #include "smc_hw_access.h"
82 #if FEATURE_HAS_SPLL_CLK
84 #define SCG_SPLL_MULT_BASE 16U
90 #define SCG_SPLL_PREDIV_BASE 1U
96 #define SCG_SPLL_REF_MIN 8000000U
102 #define SCG_SPLL_REF_MAX 32000000U
108 #define LPO_128K_FREQUENCY 128000UL
113 #define LPO_32K_FREQUENCY 32000UL
118 #define LPO_1K_FREQUENCY 1000UL
123 #define HIGH_SPEED_RUNNING_MODE (1UL << 7U)
124 #define RUN_SPEED_RUNNING_MODE (1UL << 0U)
125 #define VLPR_SPEED_RUNNING_MODE (1UL << 2U)
128 #define MODES_MAX_NO 7U
129 #define CLOCK_MAX_FREQUENCIES_VLPR_MODE \
132 { 4000000UL, 4000000UL, 1000000UL}, \
133 { 4000000UL, 4000000UL, 1000000UL}, \
134 { 4000000UL, 4000000UL, 1000000UL}, \
137 { 4000000UL, 4000000UL, 1000000UL}, \
139 #define CLOCK_MAX_FREQUENCIES_RUN_MODE \
142 {80000000UL, 48000000UL, 26670000UL}, \
143 {80000000UL, 48000000UL, 26670000UL}, \
144 {80000000UL, 48000000UL, 26670000UL}, \
147 {80000000UL, 40000000UL, 26670000UL}, \
149 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
150 #define CLOCK_MAX_FREQUENCIES_HSRUN_MODE \
153 {112000000UL, 56000000UL, 28000000UL}, \
154 {112000000UL, 56000000UL, 28000000UL}, \
155 {112000000UL, 56000000UL, 28000000UL}, \
158 {112000000UL, 56000000UL, 28000000UL}, \
165 #if defined(PCC_FTFC_INDEX)
170 #if defined(PCC_DMAMUX_INDEX)
171 #define TMP_DMAMUX 1U
173 #define TMP_DMAMUX 0U
175 #if defined(PCC_FlexCAN0_INDEX)
176 #define TMP_FlexCAN0 1U
178 #define TMP_FlexCAN0 0U
180 #if defined(PCC_FlexCAN1_INDEX)
181 #define TMP_FlexCAN1 1U
183 #define TMP_FlexCAN1 0U
185 #if defined(PCC_FTM3_INDEX)
190 #if defined(PCC_ADC1_INDEX)
195 #if defined(PCC_FlexCAN2_INDEX)
196 #define TMP_FlexCAN2 1U
198 #define TMP_FlexCAN2 0U
200 #if defined(PCC_LPSPI0_INDEX)
201 #define TMP_LPSPI0 1U
203 #define TMP_LPSPI0 0U
205 #if defined(PCC_LPSPI1_INDEX)
206 #define TMP_LPSPI1 1U
208 #define TMP_LPSPI1 0U
210 #if defined(PCC_LPSPI2_INDEX)
211 #define TMP_LPSPI2 1U
213 #define TMP_LPSPI2 0U
215 #if defined(PCC_PDB1_INDEX)
220 #if defined(PCC_CRC_INDEX)
225 #if defined(PCC_PDB0_INDEX)
230 #if defined(PCC_LPIT_INDEX)
235 #if defined(PCC_FTM0_INDEX)
240 #if defined(PCC_FTM1_INDEX)
245 #if defined(PCC_FTM2_INDEX)
250 #if defined(PCC_ADC0_INDEX)
255 #if defined(PCC_RTC_INDEX)
260 #if defined(PCC_LPTMR0_INDEX)
261 #define TMP_LPTMR0 1U
263 #define TMP_LPTMR0 0U
265 #if defined(PCC_PORTA_INDEX)
270 #if defined(PCC_PORTB_INDEX)
275 #if defined(PCC_PORTC_INDEX)
280 #if defined(PCC_PORTD_INDEX)
285 #if defined(PCC_PORTE_INDEX)
290 #if defined(PCC_SAI0_INDEX)
295 #if defined(PCC_SAI1_INDEX)
300 #if defined(PCC_FlexIO_INDEX)
301 #define TMP_FlexIO 1U
303 #define TMP_FlexIO 0U
305 #if defined(PCC_EWM_INDEX)
310 #if defined(PCC_LPI2C0_INDEX)
311 #define TMP_LPI2C0 1U
313 #define TMP_LPI2C0 0U
315 #if defined(PCC_LPI2C1_INDEX)
316 #define TMP_LPI2C1 1U
318 #define TMP_LPI2C1 0U
320 #if defined(PCC_LPUART0_INDEX)
321 #define TMP_LPUART0 1U
323 #define TMP_LPUART0 0U
325 #if defined(PCC_LPUART1_INDEX)
326 #define TMP_LPUART1 1U
328 #define TMP_LPUART1 0U
330 #if defined(PCC_LPUART2_INDEX)
331 #define TMP_LPUART2 1U
333 #define TMP_LPUART2 0U
335 #if defined(PCC_FTM4_INDEX)
340 #if defined(PCC_FTM5_INDEX)
345 #if defined(PCC_FTM6_INDEX)
350 #if defined(PCC_FTM7_INDEX)
355 #if defined(PCC_CMP0_INDEX)
360 #if defined(PCC_QSPI_INDEX)
365 #if defined(PCC_ENET_INDEX)
371 #define CLOCK_PERIPHERALS_COUNT (TMP_FTFC + TMP_DMAMUX + TMP_FlexCAN0 + TMP_FlexCAN1 + TMP_FTM3 + TMP_ADC1 + TMP_FlexCAN2 + TMP_LPSPI0 + TMP_LPSPI1 + TMP_LPSPI2 + TMP_PDB1 + TMP_CRC + TMP_PDB0 + TMP_LPIT + TMP_FTM0 + TMP_FTM1 + TMP_FTM2 + TMP_ADC0 + TMP_RTC + TMP_LPTMR0 + TMP_PORTA + TMP_PORTB + TMP_PORTC + TMP_PORTD + TMP_PORTE + TMP_SAI0 + TMP_SAI1 + TMP_FlexIO + TMP_EWM + TMP_LPI2C0 + TMP_LPI2C1 + TMP_LPUART0 + TMP_LPUART1 + TMP_LPUART2 + TMP_FTM4 + TMP_FTM5 + TMP_FTM6 + TMP_FTM7 + TMP_CMP0 + TMP_QSPI + TMP_ENET)
429 uint32_t * frequency);
431 #ifdef QuadSPI_INSTANCE_COUNT
432 static uint32_t CLOCK_SYS_GetQSPIInternalReferenceClock(
void);
434 static uint32_t CLOCK_SYS_GetQspiSfifClkHyp(
void);
436 static uint32_t CLOCK_SYS_GetQspiIpgClk(
void);
438 static uint32_t CLOCK_SYS_GetQspiIpgClkSfif(
void);
440 static uint32_t CLOCK_SYS_GetQspiIpgClk2Xsfif(
void);
444 uint32_t * frequency);
447 uint32_t * frequency);
472 #if FEATURE_HAS_SPLL_CLK
490 #if FEATURE_HAS_SPLL_CLK
491 static uint32_t CLOCK_SYS_GetSysPllFreq(
void);
535 cfg = &config_default;
568 if (scgConfig != NULL)
605 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
631 if ((peripheralClockConfig != NULL) && (peripheralClockConfig->
peripheralClocks != NULL))
633 for (i = 0U; i < peripheralClockConfig->
count; i++)
639 PCC_SetPeripheralClockControl(
PCC,
670 SIM_SetLpoClocks(
SIM,
685 #if defined (QuadSPI_INSTANCE_COUNT)
695 if (i < NUMBER_OF_TCLK_INPUTS)
705 SIM_ClearTraceClockConfig(
SIM);
708 SIM_SetTraceClockConfig(
SIM,
false, 0U, 0U);
712 SIM_SetTraceClockConfig(
SIM,
754 #ifdef PCC_ADC0_INDEX
763 #ifdef PCC_ADC1_INDEX
765 .clockName = ADC1_CLK,
772 #ifdef PCC_CMP0_INDEX
790 #ifdef PCC_DMAMUX_INDEX
799 #ifdef PCC_ENET_INDEX
801 .clockName = ENET0_CLK,
810 .clockName = EWM0_CLK,
817 #ifdef PCC_FlexCAN0_INDEX
826 #ifdef PCC_FlexCAN1_INDEX
828 .clockName = FlexCAN1_CLK,
835 #ifdef PCC_FlexCAN2_INDEX
837 .clockName = FlexCAN2_CLK,
844 #ifdef PCC_FlexIO_INDEX
853 #ifdef PCC_FTFC_INDEX
862 #ifdef PCC_FTM0_INDEX
871 #ifdef PCC_FTM1_INDEX
880 #ifdef PCC_FTM2_INDEX
882 .clockName = FTM2_CLK,
889 #ifdef PCC_FTM3_INDEX
891 .clockName = FTM3_CLK,
898 #ifdef PCC_FTM4_INDEX
900 .clockName = FTM4_CLK,
907 #ifdef PCC_FTM5_INDEX
909 .clockName = FTM5_CLK,
916 #ifdef PCC_FTM6_INDEX
918 .clockName = FTM6_CLK,
925 #ifdef PCC_FTM7_INDEX
927 .clockName = FTM7_CLK,
934 #ifdef PCC_LPI2C0_INDEX
943 #ifdef PCC_LPI2C1_INDEX
945 .clockName = LPI2C1_CLK,
952 #ifdef PCC_LPIT_INDEX
961 #ifdef PCC_LPSPI0_INDEX
970 #ifdef PCC_LPSPI1_INDEX
979 #ifdef PCC_LPSPI2_INDEX
981 .clockName = LPSPI2_CLK,
988 #ifdef PCC_LPTMR0_INDEX
997 #ifdef PCC_LPUART0_INDEX
1006 #ifdef PCC_LPUART1_INDEX
1015 #ifdef PCC_LPUART2_INDEX
1017 .clockName = LPUART2_CLK,
1024 #ifdef PCC_PDB0_INDEX
1033 #ifdef PCC_PDB1_INDEX
1035 .clockName = PDB1_CLK,
1042 #ifdef PCC_PORTA_INDEX
1051 #ifdef PCC_PORTB_INDEX
1060 #ifdef PCC_PORTC_INDEX
1069 #ifdef PCC_PORTD_INDEX
1078 #ifdef PCC_PORTE_INDEX
1087 #ifdef PCC_QSPI_INDEX
1089 .clockName = QSPI0_CLK,
1096 #ifdef PCC_RTC_INDEX
1105 #ifdef PCC_SAI0_INDEX
1107 .clockName = SAI0_CLK,
1114 #ifdef PCC_SAI1_INDEX
1116 .clockName = SAI1_CLK,
1190 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
1249 uint32_t * frequency)
1280 #if FEATURE_HAS_SPLL_CLK
1282 freq = CLOCK_SYS_GetSysPllFreq();
1309 #if FEATURE_HAS_SPLL_CLK
1322 if (frequency != NULL)
1330 #ifdef QuadSPI_INSTANCE_COUNT
1331 static uint32_t CLOCK_SYS_GetQSPIInternalReferenceClock(
void)
1334 uint32_t divValue = 0U;
1336 if (SIM_GetClockingModeSelection(
SIM))
1338 if (QSPI_GetClockingModeSelection(QuadSPI))
1347 divValue = QSPI_GetClockingProgrammableDividerValue(QuadSPI);
1348 freq /= (divValue + 1U);
1354 static uint32_t CLOCK_SYS_GetQspiSfifClkHyp(
void)
1358 freq = CLOCK_SYS_GetQSPIInternalReferenceClock();
1364 static uint32_t CLOCK_SYS_GetQspiIpgClk(
void)
1368 if (PCC_GetClockMode(
PCC, QSPI0_CLK))
1370 if (SIM_GetClockingModeSelection(
SIM))
1383 static uint32_t CLOCK_SYS_GetQspiIpgClkSfif(
void)
1387 freq = CLOCK_SYS_GetQSPIInternalReferenceClock();
1389 if (SIM_GetClockingModeSelection(
SIM))
1397 static uint32_t CLOCK_SYS_GetQspiIpgClk2Xsfif(
void)
1401 if (SIM_GetClockingModeSelection(
SIM))
1403 freq = CLOCK_SYS_GetQSPIInternalReferenceClock();
1417 uint32_t * frequency)
1420 uint32_t clockPinSelect;
1427 clockPinSelect = SIM_GetFtm0ExternalClkPinMode(
SIM);
1435 clockPinSelect = SIM_GetFtm1ExternalClkPinMode(
SIM);
1442 #if FTM_INSTANCE_COUNT > 2U
1443 case SIM_FTM2_CLOCKSEL:
1444 clockPinSelect = SIM_GetFtm2ExternalClkPinMode(
SIM);
1452 #if FTM_INSTANCE_COUNT > 3U
1453 case SIM_FTM3_CLOCKSEL:
1454 clockPinSelect = SIM_GetFtm3ExternalClkPinMode(
SIM);
1462 #if FTM_INSTANCE_COUNT > 4U
1463 case SIM_FTM4_CLOCKSEL:
1464 clockPinSelect = SIM_GetFtm4ExternalClkPinMode(
SIM);
1472 #if FTM_INSTANCE_COUNT > 5U
1473 case SIM_FTM5_CLOCKSEL:
1474 clockPinSelect = SIM_GetFtm5ExternalClkPinMode(
SIM);
1482 #if FTM_INSTANCE_COUNT > 6U
1483 case SIM_FTM6_CLOCKSEL:
1484 clockPinSelect = SIM_GetFtm6ExternalClkPinMode(
SIM);
1492 #if FTM_INSTANCE_COUNT > 7U
1493 case SIM_FTM7_CLOCKSEL:
1494 clockPinSelect = SIM_GetFtm7ExternalClkPinMode(
SIM);
1509 if (PMC_GetLpoMode(
PMC))
1516 if (PMC_GetLpoMode(
PMC))
1523 if (PMC_GetLpoMode(
PMC))
1530 if (PMC_GetLpoMode(
PMC))
1537 if (!SIM_GetEimClockGate(
SIM))
1545 if (!SIM_GetErmClockGate(
SIM))
1553 if (!SIM_GetDmaClockGate(
SIM))
1561 if (!SIM_GetMpuClockGate(
SIM))
1569 if (!SIM_GetMscmClockGate(
SIM))
1576 #ifdef QuadSPI_INSTANCE_COUNT
1577 case QSPI_MODULE_SFIF_CLK_HYP:
1578 freq = CLOCK_SYS_GetQspiSfifClkHyp();
1581 case QSPI_MODULE_CLK:
1582 freq = CLOCK_SYS_GetQspiIpgClk();
1585 case QSPI_MODULE_CLK_SFIF:
1586 freq = CLOCK_SYS_GetQspiIpgClkSfif();
1589 case QSPI_MODULE_CLK_2XSFIF:
1590 freq = CLOCK_SYS_GetQspiIpgClk2Xsfif();
1598 if (frequency != NULL)
1612 uint32_t * frequency)
1627 else if (PCC_GetClockMode(
PCC, clockName) ==
false)
1684 if (frequency != NULL)
1700 uint32_t * frequency)
1736 uint32_t frequency = 0;
1737 uint32_t fracValue = PCC_GetFracValueSel(
PCC, clockName);
1738 uint32_t divValue = PCC_GetDividerSel(
PCC, clockName);
1741 if (((uint32_t)fracValue) <= ((uint32_t)divValue))
1744 if (PCC_GetClockMode(
PCC, clockName))
1747 switch (PCC_GetClockSourceSel(
PCC, clockName))
1758 #if FEATURE_HAS_SPLL_CLK
1768 frequency = frequency / (divValue + 1U);
1769 frequency = frequency * (fracValue + 1U);
1785 switch (SMC_GetCurrentRunningMode(
SMC))
1835 #ifdef ERRATA_E10777
1845 while ((SCG_GetCurrentSystemClockSource(
SCG) != ((uint32_t)to_clk->
src)) && (timeout > 0U));
1864 if (SIM_GetClockoutStatus(
SIM))
1866 switch (SIM_GetClockoutSelectorValue(
SIM))
1883 #if FEATURE_HAS_SPLL_CLK
1900 #ifdef QuadSPI_INSTANCE_COUNT
1901 case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SFIF_CLK_HYP):
1902 frequency = CLOCK_SYS_GetQspiSfifClkHyp();
1904 case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_IPG_CLK):
1905 frequency = CLOCK_SYS_GetQspiIpgClk();
1907 case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_IPG_CLK_SFIF):
1908 frequency = CLOCK_SYS_GetQspiIpgClkSfif();
1910 case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_IPG_CLK_2XSFIF):
1911 frequency = CLOCK_SYS_GetQspiIpgClk2Xsfif();
1921 frequency /= (SIM_GetClockoutDividerValue(
SIM) + 1U);
1940 switch (SCG_GetClockoutSourceSel(
SCG))
1954 #if FEATURE_HAS_SPLL_CLK
1956 frequency = CLOCK_SYS_GetSysPllFreq();
1977 switch (SIM_GetRtcClkSrc(
SIM))
2011 if (sircConfig == NULL)
2015 sircDefaultConfig.
locked =
false;
2022 sircCfg = &sircDefaultConfig;
2026 sircCfg = sircConfig;
2030 if (SCG_GetSircSystemClockMode(
SCG))
2038 SCG_ClearSircLock(
SCG);
2041 SCG_ClearSircControl(
SCG);
2049 SCG_SetSircAsyncConfig(
SCG, sircCfg->
div1, sircCfg->
div2);
2052 SCG_SetSircConfiguration(
SCG, sircCfg->
range);
2084 if (fircConfig == NULL)
2087 fircDefaultConfig.
locked =
false;
2094 fircCfg = &fircDefaultConfig;
2098 fircCfg = fircConfig;
2102 if (SCG_GetFircSystemClockMode(
SCG))
2110 SCG_ClearFircLock(
SCG);
2113 SCG_ClearFircControl(
SCG);
2121 SCG_SetFircAsyncConfig(
SCG, fircCfg->
div1, fircCfg->
div2);
2124 SCG_SetFircConfiguration(
SCG, fircCfg->
range);
2156 if (soscConfig == NULL)
2159 soscDefaultConfig.
locked =
false;
2168 soscCfg = &soscDefaultConfig;
2172 soscCfg = soscConfig;
2176 if (SCG_GetSoscSystemClockMode(
SCG))
2184 SCG_ClearSoscLock(
SCG);
2187 SCG_ClearSoscControl(
SCG);
2197 SCG_SetSoscAsyncConfig(
SCG, soscCfg->
div1, soscCfg->
div2);
2207 SCG_SetSoscControl(
SCG,
false,
false, soscCfg->
locked);
2212 SCG_SetSoscControl(
SCG,
true,
false, soscCfg->
locked);
2217 SCG_SetSoscControl(
SCG,
true,
true, soscCfg->
locked);
2244 #if FEATURE_HAS_SPLL_CLK
2254 uint32_t srcFreq, timeout;
2256 if (spllConfig == NULL)
2259 spllDefaultConfig.
locked =
false;
2264 spllDefaultConfig.
prediv = 0;
2265 spllDefaultConfig.
mult = 0;
2266 spllDefaultConfig.
src = 0;
2268 spllCfg = &spllDefaultConfig;
2272 spllCfg = spllConfig;
2276 if (SCG_GetSpllSystemClockMode(
SCG))
2284 SCG_ClearSpllLock(
SCG);
2287 SCG_ClearSpllControl(
SCG);
2298 srcFreq /= (((uint32_t)spllCfg->
prediv) + SCG_SPLL_PREDIV_BASE);
2299 DEV_ASSERT((srcFreq >= SCG_SPLL_REF_MIN) && (srcFreq <= SCG_SPLL_REF_MAX));
2302 SCG_SetSpllAsyncConfig(
SCG, spllCfg->
div1, spllCfg->
div2);
2305 SCG_SetSpllConfiguration(
SCG, spllCfg->
prediv, spllCfg->
mult);
2312 SCG_SetSpllControl(
SCG,
false,
false, spllCfg->
locked);
2317 SCG_SetSpllControl(
SCG,
true,
false, spllCfg->
locked);
2322 SCG_SetSpllControl(
SCG,
true,
true, spllCfg->
locked);
2333 while ((CLOCK_SYS_GetSysPllFreq() == 0U) && (timeout > 0U))
2402 #if FEATURE_HAS_SPLL_CLK
2423 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
2432 nextSysClockConfig = NULL;
2447 #if FEATURE_HAS_SPLL_CLK
2451 sysClockConfig.
src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
2489 sysClockConfig.
src = nextSysClockConfig->
src;
2499 sysClockConfig.
src = nextSysClockConfig->
src;
2528 switch (SCG_GetCurrentSystemClockSource(
SCG))
2539 #if FEATURE_HAS_SPLL_CLK
2540 case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_PLL):
2541 freq = CLOCK_SYS_GetSysPllFreq();
2549 freq /= (SCG_GetCurrentCoreClockDividerRatio(
SCG) + 1U);
2557 freq /= (SCG_GetCurrentBusClockDividerRatio(
SCG) + 1U);
2560 freq /= (SCG_GetCurrentSlowClockDividerRatio(
SCG) + 1U);
2579 uint32_t srcFreq = 0U;
2584 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
2587 const uint32_t sysFreqMul = ((uint32_t)config->
divCore) + 1UL;
2588 const uint32_t busFreqMul = (((uint32_t)config->
divCore) + 1UL) * (((uint32_t)config->
divBus) + 1UL);
2589 const uint32_t slowFreqMul = (((uint32_t)config->
divCore) + 1UL) * (((uint32_t)config->
divSlow) + 1UL);
2593 switch (config->
src)
2604 #if FEATURE_HAS_SPLL_CLK
2605 case SCG_SYSTEM_CLOCK_SRC_SYS_PLL:
2606 srcFreq = CLOCK_SYS_GetSysPllFreq();
2620 if ((srcFreq > (sysFreqMul * (maxSysClksInRUN[(uint32_t)config->
src][
CORE_CLK_INDEX] >> 4U))) ||
2621 (srcFreq > (busFreqMul * (maxSysClksInRUN[(uint32_t)config->
src][
BUS_CLK_INDEX] >> 4U))) ||
2622 (srcFreq > (slowFreqMul * (maxSysClksInRUN[(uint32_t)config->
src][
SLOW_CLK_INDEX] >> 4U))))
2629 SCG_SetRunClockControl(
SCG, (uint32_t)config->
src, (uint32_t)config->
divCore, (uint32_t)config->
divBus, (uint32_t)config->
divSlow);
2635 if ((srcFreq > (sysFreqMul * (maxSysClksInVLPR[(uint32_t)config->
src][
CORE_CLK_INDEX] >> 4U))) ||
2636 (srcFreq > (busFreqMul * (maxSysClksInVLPR[(uint32_t)config->
src][
BUS_CLK_INDEX] >> 4U))) ||
2637 (srcFreq > (slowFreqMul * (maxSysClksInVLPR[(uint32_t)config->
src][
SLOW_CLK_INDEX] >> 4U))))
2644 SCG_SetVlprClockControl(
SCG, (uint32_t)config->
src, (uint32_t)config->
divCore, (uint32_t)config->
divBus, (uint32_t)config->
divSlow);
2647 #if FEATURE_HAS_HIGH_SPEED_RUN_MODE
2651 if ((srcFreq > (sysFreqMul * (maxSysClksInHSRUN[(uint32_t)config->
src][
CORE_CLK_INDEX] >> 4U))) ||
2652 (srcFreq > (busFreqMul * (maxSysClksInHSRUN[(uint32_t)config->
src][
BUS_CLK_INDEX] >> 4U))) ||
2653 (srcFreq > (slowFreqMul * (maxSysClksInHSRUN[(uint32_t)config->
src][
SLOW_CLK_INDEX] >> 4U))))
2660 SCG_SetHsrunClockControl(
SCG, (uint32_t)config->
src, (uint32_t)config->
divCore, (uint32_t)config->
divBus, (uint32_t)config->
divSlow);
2679 uint32_t freq, div = 0U;
2685 switch (clockSource)
2690 div = SCG_GetFircFirstAsyncDivider(
SCG);
2696 div = SCG_GetSircFirstAsyncDivider(
SCG);
2702 div = SCG_GetSoscFirstAsyncDivider(
SCG);
2705 #if FEATURE_HAS_SPLL_CLK
2708 freq = CLOCK_SYS_GetSysPllFreq();
2709 div = SCG_GetSpllFirstAsyncDivider(
SCG);
2725 switch (clockSource)
2730 div = SCG_GetFircSecondAsyncDivider(
SCG);
2736 div = SCG_GetSircSecondAsyncDivider(
SCG);
2742 div = SCG_GetSoscSecondAsyncDivider(
SCG);
2745 #if FEATURE_HAS_SPLL_CLK
2748 freq = CLOCK_SYS_GetSysPllFreq();
2749 div = SCG_GetSpllSecondAsyncDivider(
SCG);
2773 freq = (freq >> (div - 1U));
2790 if (SCG_GetSoscStatus(
SCG))
2808 uint32_t retValue = 0U;
2810 if (SCG_GetSircStatus(
SCG))
2812 if (SCG_GetSircRange(
SCG) != 0U)
2829 static const uint32_t fircFreq[] = {
2833 if (SCG_GetFircStatus(
SCG))
2835 retValue = fircFreq[SCG_GetFircRange(
SCG)];
2845 #if FEATURE_HAS_SPLL_CLK
2850 static uint32_t CLOCK_SYS_GetSysPllFreq(
void)
2852 uint32_t freq, retValue;
2854 if (SCG_GetSpllStatus(
SCG))
2861 freq /= (SCG_GetSpllPredivider(
SCG) + SCG_SPLL_PREDIV_BASE);
2862 freq *= (SCG_GetSpllMultiplier(
SCG) + SCG_SPLL_MULT_BASE);
2885 switch (SIM_GetLpoClkSelectorValue(
SIM))
2920 #if FEATURE_HAS_SPLL_CLK
2922 if ((CLOCK_SYS_GetSysPllFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_SYS_PLL) && (status ==
STATUS_ERROR))
2924 sysClockConfig.
src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
2982 switch(SCG_GetCurrentSystemClockSource(
SCG))
2999 #if FEATURE_HAS_SPLL_CLK
3002 sysClockConfig->
src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
3013 sysClockConfig->
divBus = sysClkDivMappings[SCG_GetCurrentBusClockDividerRatio(
SCG)];
3014 sysClockConfig->
divCore = sysClkDivMappings[SCG_GetCurrentCoreClockDividerRatio(
SCG)];
3015 sysClockConfig->
divSlow = sysClkDivMappings[SCG_GetCurrentSlowClockDividerRatio(
SCG)];
3093 uint32_t source = 0U, divider = 0U, multiplier = 0U;
3098 if (moduleClkConfig == NULL)
3100 defaultModuleClkCfg.
gating =
true;
3101 defaultModuleClkCfg.
source =
3109 ((CLOCK_SYS_GetSysPllFreq() != 0U) ?
3115 defaultModuleClkCfg.
mul = 1U;
3116 defaultModuleClkCfg.
div = 1U;
3117 moduleClkCfg = &defaultModuleClkCfg;
3121 moduleClkCfg = moduleClkConfig;
3130 switch(moduleClkCfg->
source)
3141 #if FEATURE_HAS_SPLL_CLK
3157 divider = ((uint32_t)moduleClkCfg->
div) - 1U;
3164 multiplier = ((uint32_t)moduleClkCfg->
mul) - 1U;
3168 PCC_SetClockMode(
PCC, clockName,
false);
3170 if (moduleClkCfg->
gating)
3173 PCC_SetPeripheralClockControl(
PCC, clockName,
true, source, divider, multiplier);
3181 SIM_SetMscmClockGate(
SIM, moduleClkCfg->
gating);
3185 SIM_SetMpuClockGate(
SIM, moduleClkCfg->
gating);
3189 SIM_SetDmaClockGate(
SIM, moduleClkCfg->
gating);
3193 SIM_SetErmClockGate(
SIM, moduleClkCfg->
gating);
3197 SIM_SetEimClockGate(
SIM, moduleClkCfg->
gating);
3222 static const scg_system_clock_div_t sysClkDivMappings[] = {
SCG_SYSTEM_CLOCK_DIV_BY_1,
SCG_SYSTEM_CLOCK_DIV_BY_1,
SCG_SYSTEM_CLOCK_DIV_BY_2,
SCG_SYSTEM_CLOCK_DIV_BY_3,
SCG_SYSTEM_CLOCK_DIV_BY_4,
SCG_SYSTEM_CLOCK_DIV_BY_5,
SCG_SYSTEM_CLOCK_DIV_BY_6,
SCG_SYSTEM_CLOCK_DIV_BY_7,
SCG_SYSTEM_CLOCK_DIV_BY_8,
SCG_SYSTEM_CLOCK_DIV_BY_9,
SCG_SYSTEM_CLOCK_DIV_BY_10,
SCG_SYSTEM_CLOCK_DIV_BY_11,
SCG_SYSTEM_CLOCK_DIV_BY_12,
SCG_SYSTEM_CLOCK_DIV_BY_13,
SCG_SYSTEM_CLOCK_DIV_BY_14,
SCG_SYSTEM_CLOCK_DIV_BY_15,
SCG_SYSTEM_CLOCK_DIV_BY_16};
3228 sysClockMode = currentSysClockMode;
3255 if (sysClkConfig == NULL)
3265 #if FEATURE_HAS_SPLL_CLK
3266 else if (CLOCK_SYS_GetSysPllFreq() != 0U)
3268 sysClockConfig.
src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
3301 #if FEATURE_HAS_SPLL_CLK
3302 DEV_ASSERT((CLOCK_SYS_GetSysPllFreq() != 0U) || (sysClkConfig->
src != SPLL_CLK));
3305 switch(sysClkConfig->
src)
3319 #if FEATURE_HAS_SPLL_CLK
3321 sysClockConfig.
src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
3334 sysClockConfig.
divCore = sysClkDivMappings[sysClkConfig->
dividers[0U]];
3335 sysClockConfig.
divBus = sysClkDivMappings[sysClkConfig->
dividers[1U]];
3336 sysClockConfig.
divSlow = sysClkDivMappings[sysClkConfig->
dividers[2U]];
3341 if (sysClockMode == currentSysClockMode)
3363 switch(SCG_GetCurrentSystemClockSource(
SCG))
3380 #if FEATURE_HAS_SPLL_CLK
3381 case SCG_SYSTEM_CLOCK_SRC_SYS_PLL:
3383 sysClkConfig->
src = SPLL_CLK;
3398 sysClkConfig->
dividers[0U] = (uint16_t) (SCG_GetCurrentCoreClockDividerRatio(
SCG) + 1U);
3402 sysClkConfig->
dividers[1U] = (uint16_t) (SCG_GetCurrentBusClockDividerRatio(
SCG) + 1U);
3406 sysClkConfig->
dividers[2U] = (uint16_t) (SCG_GetCurrentSlowClockDividerRatio(
SCG) + 1U);
3422 #if FEATURE_HAS_SPLL_CLK
3425 bool clockSourceEnable =
true;
3426 bool revertTmpSysClkTransition =
false;
3434 if ((clkSrcConfig != NULL) && (clkSrcConfig->
enable ==
false))
3436 clockSourceEnable =
false;
3446 if (clockSourceEnable ==
false)
3459 revertTmpSysClkTransition = (retCode ==
STATUS_SUCCESS) ?
true :
false;
3465 if (clkSrcConfig == NULL)
3474 scgSircConfig.
locked =
false;
3476 scgSircConfig.
div1 = divider1;
3477 scgSircConfig.
div2 = divider2;
3486 if ((retCode ==
STATUS_SUCCESS) && (revertTmpSysClkTransition ==
true))
3498 if (clockSourceEnable ==
false)
3511 revertTmpSysClkTransition = (retCode ==
STATUS_SUCCESS) ?
true :
false;
3517 if (clkSrcConfig == NULL)
3523 scgFircConfig.
locked =
false;
3525 scgFircConfig.
div1 = divider1;
3526 scgFircConfig.
div2 = divider2;
3536 if ((retCode ==
STATUS_SUCCESS) && (revertTmpSysClkTransition ==
true))
3547 if (clockSourceEnable ==
false)
3560 revertTmpSysClkTransition = (retCode ==
STATUS_SUCCESS) ?
true :
false;
3566 if (clkSrcConfig == NULL)
3575 scgSoscConfig.
locked =
false;
3577 scgSoscConfig.
div1 = divider1;
3578 scgSoscConfig.
div2 = divider2;
3580 switch (clkSrcConfig->
refClk)
3598 if((scgSoscConfig.
freq >= 4000000U) && (scgSoscConfig.
freq <= 8000000U))
3602 else if((scgSoscConfig.
freq >= 8000000U) && (scgSoscConfig.
freq <= 40000000U))
3617 if ((retCode ==
STATUS_SUCCESS) && (revertTmpSysClkTransition ==
true))
3624 #if FEATURE_HAS_SPLL_CLK
3627 if (SCG_GetCurrentSystemClockSource(
SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_PLL))
3629 if (clockSourceEnable ==
false)
3642 revertTmpSysClkTransition = (retCode ==
STATUS_SUCCESS) ?
true :
false;
3648 if (clkSrcConfig == NULL)
3650 retCode = CLOCK_SYS_ConfigureSPLL(clockSourceEnable, NULL);
3655 scgSpllConfig.
locked =
false;
3657 scgSpllConfig.
div1 = divider1;
3658 scgSpllConfig.
div2 = divider2;
3660 DEV_ASSERT((SCG_SPLL_PREDIV_BASE <= clkSrcConfig->div) && (clkSrcConfig->
div < (SCG_SPLL_PREDIV_BASE + (1U << SCG_SPLLCFG_PREDIV_WIDTH)) ));
3661 scgSpllConfig.
prediv = clkSrcConfig->
div - SCG_SPLL_PREDIV_BASE;
3663 DEV_ASSERT((SCG_SPLL_MULT_BASE <= clkSrcConfig->mul) && (clkSrcConfig->
mul < (SCG_SPLL_MULT_BASE + (1U << SCG_SPLLCFG_MULT_WIDTH)) ));
3664 scgSpllConfig.
mult = clkSrcConfig->
mul - SCG_SPLL_MULT_BASE;
3668 retCode = CLOCK_SYS_ConfigureSPLL(clockSourceEnable, &scgSpllConfig);
3674 if ((retCode ==
STATUS_SUCCESS) && (revertTmpSysClkTransition ==
true))
3684 if (clockSourceEnable)
3687 PMC_SetLpoMode(
PMC,
true);
3691 PMC_SetLpoMode(
PMC,
false);
PCC peripheral instance clock configuration. Implements peripheral_clock_config_t_Class.
static scg_system_clock_mode_t CLOCK_SYS_GetCurrentRunMode(void)
scg_async_clock_div_t
SCG asynchronous clock divider value.
scg_async_clock_div_t div1
scg_async_clock_div_t div2
scg_async_clock_div_t div1
sim_tclk_config_t tclkConfig
static status_t CLOCK_SYS_TransitionToTmpSysClk(scg_system_clock_src_t currentSysClkSrc)
static status_t CLOCK_SYS_SetSystemClockConfig(scg_system_clock_mode_t mode, scg_system_clock_config_t const *config)
#define FIRC_STABILIZATION_TIMEOUT
#define VLPR_SPEED_RUNNING_MODE
scg_async_clock_div_t div2
scg_rtc_config_t rtcConfig
Clock source configuration. Implements clock_source_config_t_Class.
scg_async_clock_type_t
SCG asynchronous clock type. Implements scg_async_clock_type_t_Class.
#define PCC_PCCn_PCD_WIDTH
static void CLOCK_SYS_SetPccConfiguration(const pcc_config_t *peripheralClockConfig)
status_t CLOCK_DRV_Init(clock_manager_user_config_t const *config)
Initialize clocking modules.
#define PCC_CLOCK_NAME_MAPPINGS
PCC clock name mappings Mappings between clock names and peripheral clock control indexes...
scg_system_clock_type_t
SCG system clock type. Implements scg_system_clock_type_t_Class.
SCG configure structure. Implements scg_config_t_Class.
#define SIRC_STABILIZATION_TIMEOUT
scg_system_clock_config_t vccrConfig
#define SPLL_STABILIZATION_TIMEOUT
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
#define TMP_SIRC_CLK
Temporary system clock source configurations. Each line represents the SYS(CORE), BUS and SLOW(FLASH)...
#define LPO_128K_FREQUENCY
#define HAS_CLOCK_GATING_IN_SIM
static status_t CLOCK_SYS_SetScgConfiguration(const scg_config_t *scgConfig)
scg_spll_monitor_mode_t monitorMode
scg_async_clock_div_t div2
peripheral_clock_source_t clkSrc
SIM configure structure. Implements sim_clock_config_t_Class.
#define FEATURE_SCG_FIRC_FREQ0
#define TMP_SYSTEM_CLOCK_CONFIGS
static uint32_t CLOCK_SYS_GetPeripheralClock(clock_names_t clockName, scg_async_clock_type_t divider)
void CLOCK_DRV_SetModuleClock(clock_names_t clockName, const module_clk_config_t *moduleClkConfig)
Configures module clock.
#define HAS_INT_CLOCK_FROM_SYS_CLOCK
#define SYS_CLK_MAX_NO
The maximum number of system clock dividers and system clock divider indexes.
scg_firc_config_t fircConfig
scg_sosc_config_t soscConfig
scg_system_clock_mode_t
SCG system clock modes. Implements scg_system_clock_mode_t_Class.
#define LPO_32K_FREQUENCY
scg_sosc_ext_ref_t extRef
sim_trace_clock_config_t traceClockConfig
static uint32_t CLOCK_SYS_GetSimClkOutFreq(void)
#define HIGH_SPEED_RUNNING_MODE
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC2
uint32_t g_RtcClkInFreq
RTC_CLKIN clock frequency.
sim_rtc_clk_sel_src_t sourceRtcClk
static status_t CLOCK_SYS_ConfigureSOSC(bool enable, const scg_sosc_config_t *soscConfig)
peripheral_clock_config_t * peripheralClocks
status_t CLOCK_DRV_SetSystemClock(const pwr_modes_t *mode, const sys_clk_config_t *sysClkConfig)
Configures the system clocks.
SCG system PLL configuration. Implements scg_spll_config_t_Class.
SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class.
#define CLOCK_MAX_FREQUENCIES_RUN_MODE
#define PERIPHERAL_FEATURES
Peripheral features. List of features for each clock name. If a clock name is not a peripheral...
#define FEATURE_HAS_SPLL_CLK
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
sim_plat_gate_config_t platGateConfig
static uint32_t CLOCK_SYS_GetSystemClockFreq(scg_system_clock_type_t type)
status_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const *config)
Set system clock configuration.
static status_t CLOCK_SYS_TransitionSystemClock(const scg_system_clock_config_t *to_clk)
scg_clockout_config_t clockOutConfig
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
scg_system_clock_div_t
SCG system clock divider value. Implements scg_system_clock_div_t_Class.
scg_spll_config_t spllConfig
scg_clockout_src_t source
void CLOCK_DRV_GetSystemClockSource(sys_clk_config_t *sysClkConfig)
Gets the system clock source.
scg_clock_mode_config_t clockModeConfig
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
scg_sirc_config_t sircConfig
pmc_lpo_clock_config_t lpoClockConfig
scg_async_clock_div_t div1
static status_t CLOCK_SYS_GetSimClockFreq(clock_names_t clockName, uint32_t *frequency)
SCG system clock configuration. Implements scg_system_clock_config_t_Class.
#define CLOCK_PERIPHERALS_COUNT
#define HAS_INT_CLOCK_FROM_BUS_CLOCK
static scg_async_clock_div_t CLOCK_SYS_ConvertAsyncDividerValue(uint16_t divider)
sim_clock_config_t simConfig
const uint16_t clockNameMappings[]
Clock name mappings Constant array storing the mappings between clock names and peripheral clock cont...
scg_system_clock_div_t divCore
module clock configuration. Implements module_clk_config_t_Class
scg_async_clock_div_t div2
scg_system_clock_div_t divSlow
static void CLOCK_SYS_GetDefaultConfiguration(clock_manager_user_config_t *config)
uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]
sim_clock_out_config_t clockOutConfig
#define NUMBER_OF_TCLK_INPUTS
TClk clock frequency.
#define CLOCK_MAX_FREQUENCIES_VLPR_MODE
status_t CLOCK_DRV_SetClockSource(clock_names_t clockName, const clock_source_config_t *clkSrcConfig)
This function configures a clock source.
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC1
static uint32_t CLOCK_SYS_GetSircFreq(void)
scg_async_clock_div_t div1
static status_t CLOCK_SYS_ConfigureFIRC(bool enable, const scg_firc_config_t *fircConfig)
static status_t CLOCK_SYS_GetPccClockFreq(clock_names_t clockName, uint32_t *frequency)
sim_qspi_ref_clk_gating_t qspiRefClkGating
scg_sosc_monitor_mode_t monitorMode
pwr_modes_t
Power mode. Implements pwr_modes_t_Class.
peripheral_clock_divider_t divider
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
sim_lpo_clock_config_t lpoClockConfig
static status_t CLOCK_SYS_ConfigureTemporarySystemClock(void)
static void CLOCK_SYS_SetSimConfiguration(const sim_clock_config_t *simClockConfig)
static status_t CLOCK_SYS_ConfigureModulesFromScg(const scg_config_t *scgConfig)
#define RUN_SPEED_RUNNING_MODE
static status_t CLOCK_SYS_GetScgClockFreq(clock_names_t clockName, uint32_t *frequency)
sim_lpoclk_sel_src_t sourceLpoClk
uint32_t g_xtal0ClkFreq
EXTAL0 clock frequency.
static status_t CLOCK_SYS_ConfigureSIRC(bool enable, const scg_sirc_config_t *sircConfig)
scg_system_clock_src_t
SCG system clock source. Implements scg_system_clock_src_t_Class.
const uint8_t peripheralFeaturesList[]
Peripheral features list Constant array storing the mappings between clock names of the peripherals a...
#define CLK_SRC_SIRC_DIV1
scg_system_clock_config_t rccrConfig
static uint32_t CLOCK_SYS_GetScgClkOutFreq(void)
clock_names_t
Clock names.
scg_system_clock_src_t src
status_t CLOCK_DRV_GetFreq(clock_names_t clockName, uint32_t *frequency)
Return frequency.
static uint32_t CLOCK_SYS_GetSysAsyncFreq(clock_names_t clockSource, scg_async_clock_type_t type)
Clock configuration structure. Implements clock_manager_user_config_t_Class.
static uint32_t CLOCK_SYS_GetSysOscFreq(void)
peripheral_clock_frac_t frac
#define SOSC_STABILIZATION_TIMEOUT
static void CLOCK_SYS_SetPmcConfiguration(const pmc_config_t *pmcConfig)
static uint32_t CLOCK_SYS_GetLpoFreq(void)
#define PCC_PCCn_FRAC_WIDTH
static uint32_t CLOCK_SYS_GetFircFreq(void)
static uint32_t CLOCK_SYS_GetSimRtcClkFreq(void)
#define HAS_INT_CLOCK_FROM_SLOW_CLOCK
scg_system_clock_config_t hccrConfig
static void CLOCK_SYS_GetCurrentSysClkConfig(scg_system_clock_config_t *sysClockConfig)
scg_system_clock_div_t divBus
System clock configuration. Implements sys_clk_config_t_Class.
PCC configuration. Implements pcc_config_t_Class.