29 #include "ftm_hw_access.h"
50 uint8_t hwChannel = 0U;
51 uint8_t fltChannel = 0U;
52 uint8_t chnlPairNum = 0U;
53 uint8_t channelId = 0U;
54 uint8_t faultChnNum = 0U;
55 uint32_t tempInst = instance;
64 FTM_DRV_ClearTimerOverflow(ftmBase);
66 FTM_DRV_SetWriteProtectionCmd(ftmBase,
false);
74 chnlPairNum = (uint8_t)(channelId >> 1U);
75 FTM_DRV_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum,
false);
79 FTM_DRV_SetChnMSnBAMode(ftmBase, channelId, 3U);
81 FTM_DRV_EnablePwmChannelOutputs(ftmBase, channelId);
84 FTM_DRV_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum,
true);
85 FTM_DRV_SetDualChnCombineCmd(ftmBase, chnlPairNum,
false);
86 FTM_DRV_SetDualChnMofCombineCmd(ftmBase, chnlPairNum,
false);
96 FTM_DRV_EnablePwmChannelOutputs(ftmBase, channelId);
100 FTM_DRV_SetChnMSnBAMode(ftmBase, channelId, 3U);
104 FTM_DRV_SetDualChnCompCmd(ftmBase, chnlPairNum,
true);
120 chnlPairNum = (uint8_t)(channelId >> 1U);
123 FTM_DRV_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum,
false);
127 FTM_DRV_SetChnMSnBAMode(ftmBase, channelId, 3U);
129 FTM_DRV_EnablePwmChannelOutputs(ftmBase, channelId);
133 FTM_DRV_EnablePwmChannelOutputs(ftmBase, (uint8_t)(channelId + 1U));
143 FTM_DRV_DisablePwmChannelOutputs(ftmBase, (uint8_t)(channelId + 1U));
149 FTM_DRV_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum,
true);
151 FTM_DRV_SetDualChnCombineCmd(ftmBase, chnlPairNum,
true);
163 FTM_DRV_SetInitChnOutputCmd(ftmBase,
true);
168 FTM_DRV_SetPwmFaultBehavior(ftmBase, ((param->
faultConfig)->pwmOutputStateOnFault) ?
true :
false);
170 FTM_DRV_SetFaultInputFilterVal(ftmBase, ((param->
faultConfig)->faultFilterValue));
181 for (fltChannel = 0U; fltChannel < faultChnNum; fltChannel++)
183 if (
true == (param->
faultConfig)->ftmFaultChannelParam[fltChannel].faultChannelEnabled)
186 FTM_DRV_SetFaultInputCmd(ftmBase, fltChannel,
true);
188 FTM_DRV_SetFaultInputFilterCmd(ftmBase,
190 ((param->
faultConfig)->ftmFaultChannelParam[fltChannel].faultFilterEnabled) ?
true :
false);
192 FTM_DRV_SetChnFaultInputPolarityCmd(ftmBase,
199 if (
true == ((param->
faultConfig)->pwmFaultInterrupt))
201 FTM_DRV_SetFaultInt(ftmBase,
true);
205 FTM_DRV_SetFaultControlMode(ftmBase, (uint32_t)(param->
faultConfig)->faultMode);
213 FTM_DRV_SetCounterInitVal(ftmBase, 0U);
219 FTM_DRV_SetMod(ftmBase, (uint16_t)(state->
ftmPeriod >> 1U));
223 FTM_DRV_SetMod(ftmBase, (uint16_t)(state->
ftmPeriod - 1U));
266 FTM_DRV_Enable(ftmBase,
true);
267 FTM_DRV_SetPwmSyncMode(ftmBase,
true);
304 chnlPairNum = (uint8_t)(channel >> 1U);
306 FTM_DRV_SetChnCountVal(ftmBase, channel, 0U);
307 FTM_DRV_SetChnEdgeLevel(ftmBase, channel, 0U);
308 FTM_DRV_SetChnMSnBAMode(ftmBase, channel, 0U);
309 FTM_DRV_SetCpwms(ftmBase,
false);
311 FTM_DRV_SetChnOutputPolarityCmd(ftmBase, channel,
false);
312 FTM_DRV_DisablePwmChannelOutputs(ftmBase, channel);
314 FTM_DRV_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum,
false);
316 FTM_DRV_SetDualChnMofCombineCmd(ftmBase, chnlPairNum,
false);
317 FTM_DRV_SetDualChnCombineCmd(ftmBase, chnlPairNum,
false);
318 FTM_DRV_SetDualChnDeadtimeCmd(ftmBase, chnlPairNum,
false);
319 FTM_DRV_SetDualChnFaultCmd(ftmBase, chnlPairNum,
false);
323 FTM_DRV_SetExtDeadtimeValue(ftmBase, 0U);
325 FTM_DRV_SetDeadtimeCount(ftmBase, 0U);
327 FTM_DRV_ClearFaultControl(ftmBase);
329 FTM_DRV_SetFaultInt(ftmBase,
false);
333 FTM_DRV_SetMod(ftmBase, 0U);
334 FTM_DRV_SetCounter(ftmBase, 0U);
361 bool softwareTrigger)
365 uint16_t hwFirstEdge = 0U;
366 uint16_t hwSecondEdge = 0U;
367 uint16_t ftmPeriod = 0U;
368 uint8_t chnlPairNum = (uint8_t)(channel >> 1U);
378 ftmPeriod = (uint16_t)(ftmPeriod << 1U);
382 ftmPeriod = (uint16_t)(ftmPeriod + 1U);
405 hwFirstEdge = (uint16_t)(hwFirstEdge + 1U);
415 if ((firstEdge <= ftmPeriod) && (secondEdge <= ftmPeriod))
417 hwFirstEdge = firstEdge;
418 hwSecondEdge = secondEdge;
428 if (
true == FTM_DRV_GetDualChnCombineCmd(ftmBase, chnlPairNum))
430 if (
true == FTM_DRV_GetDualChnMofCombineCmd(ftmBase, chnlPairNum))
433 if (FTM_DRV_GetClockSource(ftmBase) == 0U)
435 FTM_DRV_SetChnCountVal(ftmBase, (uint8_t)(chnlPairNum * 2U), hwFirstEdge);
440 FTM_DRV_SetChnCountVal(ftmBase, (uint8_t)(chnlPairNum * 2U), hwFirstEdge);
444 FTM_DRV_SetChnCountVal(ftmBase, (uint8_t)((chnlPairNum * 2U) + 1U), hwSecondEdge);
449 if (
true == FTM_DRV_GetCpwms(ftmBase))
451 FTM_DRV_SetChnCountVal(ftmBase, channel, (uint16_t)(hwFirstEdge >> 1U));
455 FTM_DRV_SetChnCountVal(ftmBase, channel, hwFirstEdge);
461 FTM_DRV_SetSoftwareTriggerCmd(ftmBase, softwareTrigger);
488 bool softwareTrigger)
492 uint32_t ftmPeriod = 0U;
500 ftmPeriod = newValue;
504 if (newValue <= state->ftmSourceClockFrequency)
522 ftmPeriod = (ftmPeriod >> 1U);
526 ftmPeriod = (ftmPeriod - 1U);
529 FTM_DRV_SetMod(ftmBase, (uint16_t)(ftmPeriod));
531 FTM_DRV_SetSoftwareTriggerCmd(ftmBase, softwareTrigger);
552 uint8_t numberOfChannels,
553 const uint8_t * channels,
554 const uint16_t * duty,
555 bool softwareTrigger)
562 for (i = 0U; i < numberOfChannels; i++)
564 ((ftmBase)->CONTROLS[channels[i]].CnV) = duty[i];
575 #if FEATURE_FTM_HAS_SUPPORTED_DITHERING
586 uint8_t newModFracVal,
587 bool softwareTrigger)
589 DEV_ASSERT((instance == 1U) || (instance == 2U));
593 FTM_DRV_SetModFracVal(ftmBase, newModFracVal);
595 FTM_DRV_SetSoftwareTriggerCmd(ftmBase, softwareTrigger);
613 uint8_t newMatchFracVal,
614 bool softwareTrigger)
616 DEV_ASSERT((instance == 1U) || (instance == 2U));
621 FTM_DRV_SetChnMatchFracVal(ftmBase, channel, newMatchFracVal);
623 FTM_DRV_SetSoftwareTriggerCmd(ftmBase, softwareTrigger);
642 void FTM_PWM_DRV_IrqHandler(uint32_t instance,
643 uint32_t chnOutCtrlVal)
648 if (FTM_DRV_GetDetectedFaultInput(ftmBase) ==
true)
650 faultDetection =
true;
652 FTM_DRV_SetOutmaskReg(ftmBase, chnOutCtrlVal);
654 FTM_DRV_ClearFaultsIsr(ftmBase);
656 FTM_DRV_ClearTimerOverflow(ftmBase);
659 else if (faultDetection ==
true)
662 FTM_DRV_SetAllChnSoftwareCtrlCmd(ftmBase, 0x00U);
663 FTM_DRV_SetAllChnSoftwareCtrlVal(ftmBase, 0x00U);
665 uint8_t u8chnOutCtrlVal = (uint8_t)(chnOutCtrlVal & 0xFFu);
666 FTM_DRV_SetAllChnSoftwareCtrlCmd(ftmBase, u8chnOutCtrlVal);
667 FTM_DRV_SetAllChnSoftwareCtrlVal(ftmBase, u8chnOutCtrlVal);
669 FTM_DRV_SetOutmaskReg(ftmBase, 0x00U);
671 faultDetection =
false;
673 FTM_DRV_ClearTimerOverflow(ftmBase);
status_t FTM_DRV_DeinitPwm(uint32_t instance)
Stops all PWM channels .
FlexTimer state structure of the driver.
ftm_state_t * ftmStatePtr[(2u)]
Pointer to runtime state structure.
ftm_safe_state_polarity_t levelSelect
#define FEATURE_FTM_CHANNEL_COUNT
bool enableSecondChannelOutput
#define FTM_DUTY_TO_TICKS_SHIFT
Shift value which converts duty to ticks.
status_t FTM_DRV_UpdatePwmPeriod(uint32_t instance, ftm_pwm_update_option_t typeOfUpdate, uint32_t newValue, bool softwareTrigger)
This function will update the new period in the frequency or in the counter value into mode register ...
status_t FTM_DRV_UpdatePwmEdgeChannelDither(uint32_t instance, uint8_t channel, uint8_t newMatchFracVal, bool softwareTrigger)
This function will use in the PWM edge dithering. This value is added to the channel (n) internal acc...
ftm_deadtime_ps_t deadTimePrescaler
uint8_t nNumCombinedPwmChannels
#define FTM_MAX_DUTY_CYCLE
Maximum value for PWM duty cycle.
ftm_safe_state_polarity_t levelSelectOnNextChn
uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance, uint32_t freqencyHz)
This function is used to covert the given frequency to period in ticks.
ftm_clock_source_t ftmClockSource
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
status_t FTM_DRV_FastUpdatePwmChannels(uint32_t instance, uint8_t numberOfChannels, const uint8_t *channels, const uint16_t *duty, bool softwareTrigger)
This function will update the duty cycle of PWM output for multiple channels.
ftm_safe_state_polarity_t levelSelect
status_t FTM_DRV_UpdatePwmPeriodDither(uint32_t instance, uint8_t newModFracVal, bool softwareTrigger)
This function will use in the PWM period dithering. This value is added to an internal accumulator at...
#define FTM_INSTANCE_COUNT
ftm_second_channel_polarity_t secondChannelPolarity
uint16_t uDutyCyclePercent
bool enableSecondChannelOutput
uint8_t nNumIndependentPwmChannels
FlexTimer driver PWM parameters.
bool enableExternalTrigger
ftm_polarity_t mainChannelPolarity
bool enableExternalTriggerOnNextChn
ftm_config_mode_t ftmMode
ftm_independent_ch_param_t * pwmIndependentChannelConfig
ftm_second_channel_polarity_t secondChannelPolarity
static uint16_t FTM_DRV_GetMod(const FTM_Type *ftmBase)
Returns the FTM peripheral counter modulo value.
status_t FTM_DRV_UpdatePwmChannel(uint32_t instance, uint8_t channel, ftm_pwm_update_option_t typeOfUpdate, uint16_t firstEdge, uint16_t secondEdge, bool softwareTrigger)
This function updates the waveform output in PWM mode (duty cycle and phase).
#define FTM_FEATURE_FAULT_CHANNELS
ftm_pwm_update_option_t
FlexTimer Configure type of PWM update in the duty cycle or in ticks.
bool enableExternalTrigger
status_t FTM_DRV_InitPwm(uint32_t instance, const ftm_pwm_param_t *param)
Configures the duty cycle and frequency and starts outputting the PWM on all channels configured in p...
ftm_pwm_fault_param_t * faultConfig
ftm_combined_ch_param_t * pwmCombinedChannelConfig
#define FTM_SYNC_SWSYNC_MASK
FTM_Type *const g_ftmBase[(2u)]
Table of base addresses for FTM instances.
bool enableModifiedCombine