SBC configuration control register structure. Two operating modes have a major impact on the operation of the watchdog: Forced Normal mode and Software Development mode (Software Development mode is provided for test and development purposes only and is not a dedicated SBC operating mode; the UJA1169 can be in any functional operating mode with Software Development mode enabled). These modes are enabled and disabled via bits FNMC and SDMC respectively in the SBC configuration control register. Note that this register is located in the non-volatile memory area. The watchdog is disabled in Forced Normal mode (FNM). In Software Development mode (SDM), the watchdog can be disabled or activated for test and software debugging purposes. More...

#include <middleware/sbc/sbc_uja1169/include/sbc_uja1169_driver.h>

Data Fields

sbc_sbc_v1rtsuc_t v1rtsuc
 
sbc_sbc_fnmc_t fnmc
 
sbc_sbc_sdmc_t sdmc
 
sbc_sbc_slpc_t slpc
 

Detailed Description

SBC configuration control register structure. Two operating modes have a major impact on the operation of the watchdog: Forced Normal mode and Software Development mode (Software Development mode is provided for test and development purposes only and is not a dedicated SBC operating mode; the UJA1169 can be in any functional operating mode with Software Development mode enabled). These modes are enabled and disabled via bits FNMC and SDMC respectively in the SBC configuration control register. Note that this register is located in the non-volatile memory area. The watchdog is disabled in Forced Normal mode (FNM). In Software Development mode (SDM), the watchdog can be disabled or activated for test and software debugging purposes.

Implements : sbc_sbc_t_Class

Definition at line 1108 of file sbc_uja1169_driver.h.

Field Documentation

Forced Normal mode control.

Definition at line 1111 of file sbc_uja1169_driver.h.

Software Development mode control.

Definition at line 1112 of file sbc_uja1169_driver.h.

Sleep control.

Definition at line 1114 of file sbc_uja1169_driver.h.

V1 undervoltage threshold (defined by bit V1RTC) at start-up (0x74).

Definition at line 1109 of file sbc_uja1169_driver.h.


The documentation for this struct was generated from the following file: