oc_irq.h
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1 /*
2  * Copyright 2017-2018 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
18 #ifndef OC_IRQ_H
19 #define OC_IRQ_H
20 
21 #include "oc_pal_mapping.h"
22 #include "interrupt_manager.h"
23 
24 
25 /*******************************************************************************
26  * Prototypes
27  ******************************************************************************/
28 void OC_IrqHandler(uint32_t instance, uint8_t channel);
29 
30 /*******************************************************************************
31  * Default interrupt handlers signatures
32  ******************************************************************************/
33 
34 /* Define OC PAL over FTM */
35 #if (defined(OC_PAL_OVER_FTM))
36 
37 #if (OC_PAL_INSTANCES_MAX > 0U)
38 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
39 void FTM0_Ch0_7_IrqHandler(void);
40 #else
41 void FTM0_Ch0_Ch1_IrqHandler(void);
42 
43 void FTM0_Ch2_Ch3_IrqHandler(void);
44 
45 void FTM0_Ch4_Ch5_IrqHandler(void);
46 
47 void FTM0_Ch6_Ch7_IrqHandler(void);
48 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
49 #endif /* OC_PAL_INSTANCES_MAX > 0U */
50 
51 #if (OC_PAL_INSTANCES_MAX > 1U)
52 #if (FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U)
53 void FTM1_Ch0_7_IrqHandler(void);
54 #else
55 void FTM1_Ch0_Ch1_IrqHandler(void);
56 
57 void FTM1_Ch2_Ch3_IrqHandler(void);
58 
59 void FTM1_Ch4_Ch5_IrqHandler(void);
60 
61 void FTM1_Ch6_Ch7_IrqHandler(void);
62 #endif /* FEATURE_FTM_HAS_NUM_IRQS_CHANS == 1U */
63 #endif /* OC_PAL_INSTANCES_MAX > 1U */
64 
65 #if (OC_PAL_INSTANCES_MAX > 2U)
66 void FTM2_Ch0_Ch1_IrqHandler(void);
67 
68 void FTM2_Ch2_Ch3_IrqHandler(void);
69 
70 void FTM2_Ch4_Ch5_IrqHandler(void);
71 
72 void FTM2_Ch6_Ch7_IrqHandler(void);
73 #endif /* OC_PAL_INSTANCES_MAX > 2U */
74 
75 #if (OC_PAL_INSTANCES_MAX > 3U)
76 void FTM3_Ch0_Ch1_IrqHandler(void);
77 
78 void FTM3_Ch2_Ch3_IrqHandler(void);
79 
80 void FTM3_Ch4_Ch5_IrqHandler(void);
81 
82 void FTM3_Ch6_Ch7_IrqHandler(void);
83 #endif /* OC_PAL_INSTANCES_MAX > 3U */
84 
85 #if (OC_PAL_INSTANCES_MAX > 4U)
86 void FTM4_Ch0_Ch1_IrqHandler(void);
87 
88 void FTM4_Ch2_Ch3_IrqHandler(void);
89 
90 void FTM4_Ch4_Ch5_IrqHandler(void);
91 
92 void FTM4_Ch6_Ch7_IrqHandler(void);
93 #endif /* OC_PAL_INSTANCES_MAX > 4U */
94 
95 #if (OC_PAL_INSTANCES_MAX > 5U)
96 void FTM5_Ch0_Ch1_IrqHandler(void);
97 
98 void FTM5_Ch2_Ch3_IrqHandler(void);
99 
100 void FTM5_Ch4_Ch5_IrqHandler(void);
101 
102 void FTM5_Ch6_Ch7_IrqHandler(void);
103 #endif /* OC_PAL_INSTANCES_MAX > 5U */
104 
105 #if (OC_PAL_INSTANCES_MAX > 6U)
106 void FTM6_Ch0_Ch1_IrqHandler(void);
107 
108 void FTM6_Ch2_Ch3_IrqHandler(void);
109 
110 void FTM6_Ch4_Ch5_IrqHandler(void);
111 
112 void FTM6_Ch6_Ch7_IrqHandler(void);
113 #endif /* OC_PAL_INSTANCES_MAX > 6U */
114 
115 #if (OC_PAL_INSTANCES_MAX > 7U)
116 void FTM7_Ch0_Ch1_IrqHandler(void);
117 
118 void FTM7_Ch2_Ch3_IrqHandler(void);
119 
120 void FTM7_Ch4_Ch5_IrqHandler(void);
121 
122 void FTM7_Ch6_Ch7_IrqHandler(void);
123 #endif /* OC_PAL_INSTANCES_MAX > 7U */
124 /* Array storing references to OC PAL over FTM irq handlers */
125 extern const isr_t s_ocOverFtmIsr[OC_PAL_INSTANCES_MAX][FTM_CONTROLS_COUNT];
126 
127 #endif /* OC_PAL_OVER_FTM */
128 
129 #if (defined(OC_PAL_OVER_EMIOS))
130 
131 #if (OC_PAL_INSTANCES_MAX > 0U)
132 void EMIOS0_00_01_IRQHandler(void);
133 void EMIOS0_02_03_IRQHandler(void);
134 void EMIOS0_04_05_IRQHandler(void);
135 void EMIOS0_06_07_IRQHandler(void);
136 void EMIOS0_08_09_IRQHandler(void);
137 void EMIOS0_10_11_IRQHandler(void);
138 void EMIOS0_12_13_IRQHandler(void);
139 void EMIOS0_14_15_IRQHandler(void);
140 void EMIOS0_16_17_IRQHandler(void);
141 void EMIOS0_18_19_IRQHandler(void);
142 void EMIOS0_20_21_IRQHandler(void);
143 void EMIOS0_22_23_IRQHandler(void);
144 void EMIOS0_24_25_IRQHandler(void);
145 void EMIOS0_26_27_IRQHandler(void);
146 void EMIOS0_28_29_IRQHandler(void);
147 void EMIOS0_30_31_IRQHandler(void);
148 #endif
149 
150 #if (OC_PAL_INSTANCES_MAX > 1U)
151 void EMIOS1_00_01_IRQHandler(void);
152 void EMIOS1_02_03_IRQHandler(void);
153 void EMIOS1_04_05_IRQHandler(void);
154 void EMIOS1_06_07_IRQHandler(void);
155 void EMIOS1_08_09_IRQHandler(void);
156 void EMIOS1_10_11_IRQHandler(void);
157 void EMIOS1_12_13_IRQHandler(void);
158 void EMIOS1_14_15_IRQHandler(void);
159 void EMIOS1_16_17_IRQHandler(void);
160 void EMIOS1_18_19_IRQHandler(void);
161 void EMIOS1_20_21_IRQHandler(void);
162 void EMIOS1_22_23_IRQHandler(void);
163 void EMIOS1_24_25_IRQHandler(void);
164 void EMIOS1_26_27_IRQHandler(void);
165 void EMIOS1_28_29_IRQHandler(void);
166 void EMIOS1_30_31_IRQHandler(void);
167 #endif
168 
169 #if (OC_PAL_INSTANCES_MAX > 2U)
170 void EMIOS2_00_01_IRQHandler(void);
171 void EMIOS2_02_03_IRQHandler(void);
172 void EMIOS2_04_05_IRQHandler(void);
173 void EMIOS2_06_07_IRQHandler(void);
174 void EMIOS2_08_09_IRQHandler(void);
175 void EMIOS2_10_11_IRQHandler(void);
176 void EMIOS2_12_13_IRQHandler(void);
177 void EMIOS2_14_15_IRQHandler(void);
178 void EMIOS2_16_17_IRQHandler(void);
179 void EMIOS2_18_19_IRQHandler(void);
180 void EMIOS2_20_21_IRQHandler(void);
181 void EMIOS2_22_23_IRQHandler(void);
182 void EMIOS2_24_25_IRQHandler(void);
183 void EMIOS2_26_27_IRQHandler(void);
184 void EMIOS2_28_29_IRQHandler(void);
185 void EMIOS2_30_31_IRQHandler(void);
186 #endif
187 
188 #endif /* defined(OC_PAL_OVER_EMIOS) */
189 
190 #if (defined(OC_PAL_OVER_ETIMER))
191 
192 #if (OC_PAL_INSTANCES_MAX > 0U)
193 void ETIMER0_TC0IR_IRQHandler(void);
194 void ETIMER0_TC1IR_IRQHandler(void);
195 void ETIMER0_TC2IR_IRQHandler(void);
196 void ETIMER0_TC3IR_IRQHandler(void);
197 void ETIMER0_TC4IR_IRQHandler(void);
198 void ETIMER0_TC5IR_IRQHandler(void);
199 #endif
200 
201 #if (OC_PAL_INSTANCES_MAX > 1U)
202 void ETIMER1_TC0IR_IRQHandler(void);
203 void ETIMER1_TC1IR_IRQHandler(void);
204 void ETIMER1_TC2IR_IRQHandler(void);
205 void ETIMER1_TC3IR_IRQHandler(void);
206 void ETIMER1_TC4IR_IRQHandler(void);
207 void ETIMER1_TC5IR_IRQHandler(void);
208 #endif
209 
210 #if (OC_PAL_INSTANCES_MAX > 2U)
211 void ETIMER2_TC0IR_IRQHandler(void);
212 void ETIMER2_TC1IR_IRQHandler(void);
213 void ETIMER2_TC2IR_IRQHandler(void);
214 void ETIMER2_TC3IR_IRQHandler(void);
215 void ETIMER2_TC4IR_IRQHandler(void);
216 void ETIMER2_TC5IR_IRQHandler(void);
217 #endif
218 
219 #endif /* defined(OC_PAL_OVER_ETIMER) */
220 
221 #endif /* OC_IRQ_H */
222 
223 /*******************************************************************************
224  * EOF
225  ******************************************************************************/
#define FTM_CONTROLS_COUNT
Definition: S32K118.h:3822
void OC_IrqHandler(uint32_t instance, uint8_t channel)
Definition: oc_pal.c:1194
void(* isr_t)(void)
Interrupt handler type.