clock_S32K1xx.h
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #if !defined (CLOCK_S32K1xx_H)
20 #define CLOCK_S32K1xx_H
21 
37 #include "device_registers.h"
38 #include "status.h"
39 #include <stdint.h>
40 #include <stdbool.h>
41 
42 
49 /*******************************************************************************
50  * Definitions
51  ******************************************************************************/
52 
56 extern const uint8_t peripheralFeaturesList[CLOCK_NAME_COUNT];
57 
58 
60 #define NUMBER_OF_TCLK_INPUTS 3U
61 extern uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS];
64 extern uint32_t g_xtal0ClkFreq;
65 
67 extern uint32_t g_RtcClkInFreq;
68 
70 #define SYS_CLK_MAX_NO 3U
71 #define CORE_CLK_INDEX 0U
72 #define BUS_CLK_INDEX 1U
73 #define SLOW_CLK_INDEX 2U
74 
79 typedef enum
80 {
86 
91 typedef enum
92 {
98 
102 typedef enum
103 {
115 #if defined (QuadSPI_INSTANCE_COUNT)
116  SIM_CLKOUT_SEL_SYSTEM_SFIF_CLK_HYP = 5U,
117  SIM_CLKOUT_SEL_SYSTEM_IPG_CLK = 11U,
118  SIM_CLKOUT_SEL_SYSTEM_IPG_CLK_SFIF = 13U,
119  SIM_CLKOUT_SEL_SYSTEM_IPG_CLK_2XSFIF = 15U
120 #endif
122 
126 typedef enum
127 {
137 
138 
143 typedef struct
144 {
145  bool initialize;
146  bool enable;
150 
151 
156 typedef struct
157 {
158  bool initialize;
162  bool enableLpo1k;
164 
169 typedef struct
170 {
171  bool initialize;
172  uint32_t tclkFreq[NUMBER_OF_TCLK_INPUTS];
174 
179 typedef struct
180 {
181  bool initialize;
182  bool enableMscm;
183  bool enableMpu;
184  bool enableDma;
185  bool enableErm;
186  bool enableEim;
188 
193 typedef struct
194 {
197 
198 
203 typedef enum
204 {
207 
208 
213 typedef struct
214 {
215  bool initialize;
216  bool divEnable;
218  uint8_t divider;
219  bool divFraction;
221 
226 typedef struct
227 {
235 
236 
241 typedef enum
242 {
246 #if FEATURE_HAS_SPLL_CLK
247  SCG_SYSTEM_CLOCK_SRC_SYS_PLL = 6U,
248 #endif
251 
256 typedef enum
257 {
275 
280 typedef struct
281 {
287 
297 typedef enum
298 {
311 typedef enum
312 {
322 
323 
328 typedef enum
329 {
334 
339 typedef enum
340 {
344 
349 typedef enum
350 {
354 
359 typedef enum
360 {
364 
369 typedef struct
370 {
371  uint32_t freq;
386  bool locked;
388  bool initialize;
390 
395 typedef enum
396 {
399 
404 typedef struct
405 {
411  bool initialize;
415  bool locked;
417 
422 typedef enum
423 {
426 
431 typedef struct
432 {
440  bool regulator;
441  bool locked;
443  bool initialize;
445 
450 typedef enum
451 {
456 
457 
461 typedef enum
462 {
471 
473 
477 typedef enum
478 {
512 
517 typedef struct
518 {
521  uint8_t prediv;
522  uint8_t mult;
523  uint8_t src;
530  bool locked;
531  bool initialize;
533 
538 typedef struct
539 {
540  uint32_t rtcClkInFreq;
541  bool initialize;
543 
548 typedef struct
549 {
554  bool initialize;
556 
561 typedef struct
562 {
564  bool initialize;
566 
571 typedef struct
572 {
580 } scg_config_t;
581 
586 
587 #define CLK_SRC_OFF 0x00U
588 #define CLK_SRC_SOSC 0x01U
589 #define CLK_SRC_SIRC 0x02U
590 #define CLK_SRC_FIRC 0x03U
591 #define CLK_SRC_SPLL 0x06U
592 #define CLK_SRC_SOSC_DIV1 0x01U
593 #define CLK_SRC_SIRC_DIV1 0x02U
594 #define CLK_SRC_FIRC_DIV1 0x03U
595 #define CLK_SRC_SPLL_DIV1 0x06U
596 #define CLK_SRC_SOSC_DIV2 0x01U
597 #define CLK_SRC_SIRC_DIV2 0x02U
598 #define CLK_SRC_FIRC_DIV2 0x03U
599 #define CLK_SRC_SPLL_DIV2 0x06U
604 typedef enum
605 {
606  MULTIPLY_BY_ONE = 0x00U,
609 
613 typedef enum
614 {
615  DIVIDE_BY_ONE = 0x00U,
616  DIVIDE_BY_TWO = 0x01U,
617  DIVIDE_BY_THREE = 0x02U,
618  DIVIDE_BY_FOUR = 0x03U,
619  DIVIDE_BY_FIVE = 0x04U,
620  DIVIDE_BY_SIX = 0x05U,
621  DIVIDE_BY_SEVEN = 0x06U,
624 
628 typedef struct
629 {
630  /* clockName is the name of the peripheral clock
631  * must be one of the following values (see the clock_names_t type from S32K1xx_clock_names.h)
632  * PCC_DMA0_CLOCK
633  * PCC_MPU0_CLOCK
634  * ...
635  * PCC_LPUART3_CLOCK
636  */
638  bool clkGate;
643 
647 typedef struct
648 {
649  uint32_t count;
651 } pcc_config_t;
652 
654 typedef struct
655 {
656  bool initialize;
657  bool enable;
658  int8_t trimValue;
660 
664 typedef struct
665 {
667 } pmc_config_t;
668 
673 typedef struct
674 {
680 
685 typedef enum {
686 
687  NO_MODE = 0U,
688  RUN_MODE = (1U<<0U),
689  VLPR_MODE = (1U<<1U),
690  HSRUN_MODE = (1U<<2U),
691  STOP_MODE = (1U<<3U),
692  VLPS_MODE = (1U<<4U),
693  ALL_MODES = 0x7FFFFFFF
694 
695 } pwr_modes_t;
696 
697 
702 typedef enum
703 {
706 } xosc_ref_t;
707 
711 typedef struct
712 {
713  bool gating;
715  uint16_t mul;
716  uint16_t div;
719 
724 typedef struct
725 {
727  uint16_t dividers[SYS_CLK_MAX_NO];
729 
734 typedef struct
735 {
736  bool enable;
738  uint32_t refFreq;
739  uint16_t mul;
740  uint16_t div;
742  uint16_t outputDiv1;
743  uint16_t outputDiv2;
746 
747 
748 /*******************************************************************************
749  * API
750  ******************************************************************************/
751 
752 #if defined (__cplusplus)
753 extern "C" {
754 #endif /* __cplusplus*/
755 
765 
775 status_t CLOCK_DRV_GetFreq(clock_names_t clockName, uint32_t * frequency);
776 
787 void CLOCK_DRV_SetModuleClock(clock_names_t clockName, const module_clk_config_t * moduleClkConfig);
788 
799  const sys_clk_config_t * sysClkConfig);
800 
809 
822 
823 #if defined (__cplusplus)
824 }
825 #endif /* __cplusplus*/
826 
829 #endif /* CLOCK_S32K1xx_H */
830 /*******************************************************************************
831  * EOF
832  ******************************************************************************/
clock_trace_src_t
Debug trace clock source select Implements clock_trace_src_t_Class.
PCC peripheral instance clock configuration. Implements peripheral_clock_config_t_Class.
scg_sosc_range_t
SCG OSC frequency range select Implements scg_sosc_range_t_Class.
scg_async_clock_div_t
SCG asynchronous clock divider value.
SIM LPO Clocks configuration. Implements sim_lpo_clock_config_t_Class.
scg_async_clock_div_t div1
scg_async_clock_div_t div2
scg_async_clock_div_t div1
sim_tclk_config_t tclkConfig
SCG ClockOut Configuration structure. Implements scg_clockout_config_t_Class.
scg_async_clock_div_t div2
scg_rtc_config_t rtcConfig
Clock source configuration. Implements clock_source_config_t_Class.
sim_rtc_clk_sel_src_t
SIM CLK32KSEL clock source select Implements sim_rtc_clk_sel_src_t_Class.
Definition: clock_S32K1xx.h:79
sim_clkout_div_t
SIM CLKOUT divider.
clock_names_t source
scg_sosc_ext_ref_t
SCG OSC external reference clock select. Implements scg_sosc_ext_ref_t_Class.
sim_clkout_src_t
SIM CLKOUT select.
scg_sosc_monitor_mode_t
SCG system OSC monitor mode. Implements scg_sosc_monitor_mode_t_Class.
status_t CLOCK_DRV_Init(clock_manager_user_config_t const *config)
Initialize clocking modules.
SCG configure structure. Implements scg_config_t_Class.
scg_spll_clock_multiply_t
SCG system PLL multiplier.
scg_firc_range_t range
sim_lpoclk_sel_src_t
SIM LPOCLKSEL clock source select Implements sim_lpoclk_sel_src_t_Class.
Definition: clock_S32K1xx.h:91
scg_system_clock_config_t vccrConfig
scg_sirc_range_t range
uint32_t rtcClkInFreq
uint8_t peripheral_clock_source_t
PCC clock source select Implements peripheral_clock_source_t_Class.
scg_spll_monitor_mode_t monitorMode
scg_async_clock_div_t div2
peripheral_clock_source_t clkSrc
SIM QSPI reference clock gating. Implements sim_qspi_ref_clk_gating_t_Class.
SIM configure structure. Implements sim_clock_config_t_Class.
void CLOCK_DRV_SetModuleClock(clock_names_t clockName, const module_clk_config_t *moduleClkConfig)
Configures module clock.
SCG Clock Mode Configuration structure. Implements scg_clock_mode_config_t_Class. ...
#define SYS_CLK_MAX_NO
The maximum number of system clock dividers and system clock divider indexes.
Definition: clock_S32K1xx.h:70
scg_firc_config_t fircConfig
sim_clkout_div_t divider
scg_sosc_config_t soscConfig
scg_sosc_ext_ref_t extRef
sim_trace_clock_config_t traceClockConfig
uint32_t g_RtcClkInFreq
RTC_CLKIN clock frequency.
Definition: clock_S32K1xx.c:76
sim_rtc_clk_sel_src_t sourceRtcClk
peripheral_clock_config_t * peripheralClocks
status_t CLOCK_DRV_SetSystemClock(const pwr_modes_t *mode, const sys_clk_config_t *sysClkConfig)
Configures the system clocks.
scg_sosc_gain_t
SCG OSC high gain oscillator select. Implements scg_sosc_gain_t_Class.
SCG system PLL configuration. Implements scg_spll_config_t_Class.
SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class.
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
sim_plat_gate_config_t platGateConfig
scg_clockout_config_t clockOutConfig
sim_clkout_src_t source
scg_system_clock_div_t
SCG system clock divider value. Implements scg_system_clock_div_t_Class.
scg_spll_config_t spllConfig
scg_clockout_src_t source
void CLOCK_DRV_GetSystemClockSource(sys_clk_config_t *sysClkConfig)
Gets the system clock source.
scg_clock_mode_config_t clockModeConfig
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
scg_sirc_range_t
SCG slow IRC clock frequency range. Implements scg_sirc_range_t_Class.
scg_sirc_config_t sircConfig
SCG RTC configuration. Implements scg_rtc_config_t_Class.
scg_sosc_gain_t gain
pmc_lpo_clock_config_t lpoClockConfig
scg_async_clock_div_t div1
SCG system clock configuration. Implements scg_system_clock_config_t_Class.
peripheral_clock_frac_t
PCC fractional value select Implements peripheral_clock_frac_t_Class.
sim_clock_config_t simConfig
scg_system_clock_div_t divCore
module clock configuration. Implements module_clk_config_t_Class
scg_async_clock_div_t div2
scg_system_clock_div_t divSlow
uint32_t g_TClkFreq[3U]
Definition: clock_S32K1xx.c:73
sim_clock_out_config_t clockOutConfig
scg_spll_monitor_mode_t
SCG system PLL monitor mode. Implements scg_spll_monitor_mode_t_Class.
#define NUMBER_OF_TCLK_INPUTS
TClk clock frequency.
Definition: clock_S32K1xx.h:60
xosc_ref_t
XOSC reference clock select (internal oscillator is bypassed or not) Implements xosc_ref_t_Class.
status_t CLOCK_DRV_SetClockSource(clock_names_t clockName, const clock_source_config_t *clkSrcConfig)
This function configures a clock source.
scg_async_clock_div_t div1
uint32_t count
scg_sosc_range_t range
SIM Platform Gate Clock configuration. Implements sim_plat_gate_config_t_Class.
sim_qspi_ref_clk_gating_t qspiRefClkGating
scg_sosc_monitor_mode_t monitorMode
pwr_modes_t
Power mode. Implements pwr_modes_t_Class.
SIM ClockOut configuration. Implements sim_clock_out_config_t_Class.
peripheral_clock_divider_t divider
scg_spll_clock_prediv_t
SCG system PLL predivider.
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
scg_firc_range_t
SCG fast IRC clock frequency range. Implements scg_firc_range_t_Class.
sim_lpo_clock_config_t lpoClockConfig
sim_lpoclk_sel_src_t sourceLpoClk
PMC configure structure.
uint32_t g_xtal0ClkFreq
EXTAL0 clock frequency.
Definition: clock_S32K1xx.c:79
scg_system_clock_src_t
SCG system clock source. Implements scg_system_clock_src_t_Class.
const uint8_t peripheralFeaturesList[CLOCK_NAME_COUNT]
Peripheral features list Constant array storing the mappings between clock names of the peripherals a...
clock_trace_src_t source
scg_clockout_src_t
SCG ClockOut type. Implements scg_clockout_src_t_Class.
peripheral_clock_divider_t
PCC divider value select Implements peripheral_clock_divider_t_Class.
scg_system_clock_config_t rccrConfig
clock_names_t src
clock_names_t
Clock names.
scg_system_clock_src_t src
scg_system_clock_src_t alternateClock
status_t CLOCK_DRV_GetFreq(clock_names_t clockName, uint32_t *frequency)
Return frequency.
Clock configuration structure. Implements clock_manager_user_config_t_Class.
SIM Platform Gate Clock configuration. Implements sim_tclk_config_t_Class.
peripheral_clock_frac_t frac
PMC LPO configuration.
scg_system_clock_config_t hccrConfig
scg_system_clock_div_t divBus
SIM Debug Trace clock configuration. Implements sim_trace_clock_config_t_Class.
System clock configuration. Implements sys_clk_config_t_Class.
PCC configuration. Implements pcc_config_t_Class.