Modules | |
FTM Register Masks | |
Data Structures | |
struct | FTM_Type |
Macros | |
#define | FTM_CONTROLS_COUNT 8u |
#define | FTM_CV_MIRROR_COUNT 8u |
#define | FTM_INSTANCE_COUNT (2u) |
#define | FTM0_BASE (0x40038000u) |
#define | FTM0 ((FTM_Type *)FTM0_BASE) |
#define | FTM1_BASE (0x40039000u) |
#define | FTM1 ((FTM_Type *)FTM1_BASE) |
#define | FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE } |
#define | FTM_BASE_PTRS { FTM0, FTM1 } |
#define | FTM_IRQS_ARR_COUNT (4u) |
#define | FTM_IRQS_CH_COUNT (8u) |
#define | FTM_Fault_IRQS_CH_COUNT (1u) |
#define | FTM_Overflow_IRQS_CH_COUNT (1u) |
#define | FTM_Reload_IRQS_CH_COUNT (1u) |
#define | FTM_IRQS |
#define | FTM_Fault_IRQS { FTM0_Fault_IRQn, FTM1_Fault_IRQn } |
#define | FTM_Overflow_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn } |
#define | FTM_Reload_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn } |
Typedefs | |
typedef struct FTM_Type * | FTM_MemMapPtr |
#define FTM0_BASE (0x40038000u) |
#define FTM1_BASE (0x40039000u) |
#define FTM_CONTROLS_COUNT 8u |
#define FTM_Fault_IRQS { FTM0_Fault_IRQn, FTM1_Fault_IRQn } |
#define FTM_Fault_IRQS_CH_COUNT (1u) |
#define FTM_INSTANCE_COUNT (2u) |
#define FTM_IRQS |
Interrupt vectors for the FTM peripheral type
#define FTM_IRQS_ARR_COUNT (4u) |
#define FTM_IRQS_CH_COUNT (8u) |
#define FTM_Overflow_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn } |
#define FTM_Overflow_IRQS_CH_COUNT (1u) |
#define FTM_Reload_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn } |
#define FTM_Reload_IRQS_CH_COUNT (1u) |
typedef struct FTM_Type * FTM_MemMapPtr |