Modules | |
CMU_FC Register Masks | |
Data Structures | |
struct | CMU_FC_Type |
Macros | |
#define | CMU_FC_INSTANCE_COUNT (2u) |
#define | CMU_FC_0_BASE (0x4003E000u) |
#define | CMU_FC_0 ((CMU_FC_Type *)CMU_FC_0_BASE) |
#define | CMU_FC_1_BASE (0x4003F000u) |
#define | CMU_FC_1 ((CMU_FC_Type *)CMU_FC_1_BASE) |
#define | CMU_FC_BASE_ADDRS { CMU_FC_0_BASE, CMU_FC_1_BASE } |
#define | CMU_FC_BASE_PTRS { CMU_FC_0, CMU_FC_1 } |
#define | CMU_FC_IRQS_ARR_COUNT (1u) |
#define | CMU_FC_IRQS_CH_COUNT (1u) |
#define | CMU_FC_IRQS { SCG_CMU_LVD_LVWSCG_IRQn, SCG_CMU_LVD_LVWSCG_IRQn } |
Typedefs | |
typedef struct CMU_FC_Type * | CMU_FC_MemMapPtr |
#define CMU_FC_0 ((CMU_FC_Type *)CMU_FC_0_BASE) |
#define CMU_FC_0_BASE (0x4003E000u) |
#define CMU_FC_1 ((CMU_FC_Type *)CMU_FC_1_BASE) |
#define CMU_FC_1_BASE (0x4003F000u) |
#define CMU_FC_BASE_ADDRS { CMU_FC_0_BASE, CMU_FC_1_BASE } |
#define CMU_FC_INSTANCE_COUNT (2u) |
#define CMU_FC_IRQS { SCG_CMU_LVD_LVWSCG_IRQn, SCG_CMU_LVD_LVWSCG_IRQn } |
#define CMU_FC_IRQS_ARR_COUNT (1u) |
#define CMU_FC_IRQS_CH_COUNT (1u) |
typedef struct CMU_FC_Type * CMU_FC_MemMapPtr |