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| void | arm_nn_depthwise_conv1d_k3_nhwc_f32 (const float32_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float32_t *__RESTRICT kernel, const float32_t *__RESTRICT b, float32_t *__RESTRICT out, int32_t out_w) |
| | Specialized NHWC depthwise 1D kernel for k=3, ch_mult=1 (float32).
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| void | arm_nn_depthwise_conv3x3_nhwc_f32 (const float32_t *__RESTRICT x_nhwc, int32_t batches, int32_t in_c, int32_t in_h, int32_t in_w, const float32_t *__RESTRICT kernel, const float32_t *__RESTRICT b, float32_t *__RESTRICT out, int32_t stride_x, int32_t stride_y, int32_t pad_x, int32_t pad_y, int32_t out_h, int32_t out_w, float32_t act_min, float32_t act_max) |
| | Specialized NHWC depthwise 3x3 kernel (float32, ch_mult=1).
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| arm_cmsis_nn_status | arm_nn_depthwise_conv_nt_t_f32 (const float32_t *__RESTRICT lhs, const float32_t *__RESTRICT rhs, const float32_t *__RESTRICT bias, float32_t *__RESTRICT out, int32_t lhs_rows, int32_t total_ch, int32_t row_x_col, int32_t out_row_stride, float32_t activation_min, float32_t activation_max) |
| | Generic depthwise helper with packed lhs tiles and transposed rhs layout (float32).
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| void | arm_nn_conv1d_k5_nhwc_f32 (const float32_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float32_t *__RESTRICT kernel, const float32_t *__RESTRICT b, float32_t *__RESTRICT out, int32_t out_c, int32_t out_w) |
| | Specialized NHWC 1D convolution kernel for k=5 (float32).
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| void | arm_nn_conv1d_k5_packed_f32 (const float32_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float32_t *__RESTRICT kernel_packed, const float32_t *__RESTRICT b, float32_t *__RESTRICT out, int32_t out_c, int32_t out_w) |
| | Specialized NHWC 1D convolution kernel for k=5 (float32, packed weights).
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| void | arm_nn_conv1d_k3_nhwc_f32 (const float32_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float32_t *__RESTRICT kernel, const float32_t *__RESTRICT b, float32_t *__RESTRICT out, int32_t out_c, int32_t out_w) |
| | Specialized NHWC 1D convolution kernel for k=3 (float32).
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| void | arm_nn_conv1d_k3_packed_f32 (const float32_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float32_t *__RESTRICT kernel_packed, const float32_t *__RESTRICT b, float32_t *__RESTRICT out, int32_t out_c, int32_t out_w) |
| | Specialized NHWC 1D convolution kernel for k=3 (float32, packed weights).
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| void | arm_nn_maxpool1d_k3s3_nhwc_f32 (const float32_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, float32_t *__RESTRICT out, int32_t out_w) |
| | Specialized NHWC max-pool 1D kernel for k=3, s=3 (float32).
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| void | arm_nn_maxpool1d_k2s2_nhwc_noclip_f32 (const float32_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, float32_t *__RESTRICT out, int32_t out_w) |
| | Specialized NHWC max-pool 1D kernel for k=2, s=2 without output clamp (float32).
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| void | arm_nn_maxpool1d_k2s2_nhwc_f32 (const float32_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, float32_t *__RESTRICT out, int32_t out_w, float32_t act_min, float32_t act_max) |
| | Specialized NHWC max-pool 1D kernel for k=2, s=2 with clamp (float32).
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| arm_cmsis_nn_status | arm_nn_mat_mult_nt_t_f32 (const float32_t *__RESTRICT lhs, const float32_t *__RESTRICT rhs, const float32_t *__RESTRICT bias, float32_t *__RESTRICT dst, int32_t lhs_rows, int32_t rhs_rows, int32_t rhs_cols, int32_t row_address_offset, float32_t activation_min, float32_t activation_max) |
| | Matrix multiply with non-transposed lhs and transposed rhs rows (float32).
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| arm_cmsis_nn_status | arm_nn_mat_mult_nt_n_packed_f32 (const float32_t *__RESTRICT lhs, const float32_t *__RESTRICT rhs_packed, const float32_t *__RESTRICT bias, float32_t *__RESTRICT dst, int32_t lhs_rows, int32_t rhs_rows, int32_t rhs_cols, int32_t row_address_offset, float32_t activation_min, float32_t activation_max) |
| | Matrix multiply with non-transposed lhs and packed non-transposed rhs (float32).
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| void | arm_nn_pack_conv_patch_f32 (const float32_t *__RESTRICT input, int32_t in_h, int32_t in_w, int32_t in_c, int32_t kernel_h, int32_t kernel_w, int32_t stride_h, int32_t stride_w, int32_t pad_h, int32_t pad_w, int32_t dilation_h, int32_t dilation_w, int32_t out_y, int32_t out_x, float32_t pad_value, float32_t *__RESTRICT patch_row) |
| | Pack a single convolution patch into one row of a contiguous float32 patch matrix.
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| void | arm_nn_softmax_1x2_f32 (const float32_t in[2], float32_t out[2]) |
| | Specialized softmax helper for a single float32 row of length 2.
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| void | arm_nn_depthwise_conv2x5_nhwc_f16 (const float16_t *__RESTRICT x_nhwc, int32_t batches, int32_t in_c, int32_t in_w, int32_t ch_mult, const float16_t *__RESTRICT kernel, const float16_t *__RESTRICT b, float16_t *__RESTRICT out, int32_t out_w, float16_t act_min, float16_t act_max) |
| | Specialized NHWC depthwise 2x5 kernel (float16).
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| void | arm_nn_depthwise_conv1d_k3_nhwc_f16 (const float16_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float16_t *__RESTRICT kernel, const float16_t *__RESTRICT b, float16_t *__RESTRICT out, int32_t out_w) |
| | Specialized NHWC depthwise 1D kernel for k=3, ch_mult=1 (float32).
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| void | arm_nn_depthwise_conv3x3_nhwc_f16 (const float16_t *__RESTRICT x_nhwc, int32_t batches, int32_t in_c, int32_t in_h, int32_t in_w, const float16_t *__RESTRICT kernel, const float16_t *__RESTRICT b, float16_t *__RESTRICT out, int32_t stride_x, int32_t stride_y, int32_t pad_x, int32_t pad_y, int32_t out_h, int32_t out_w, float16_t act_min, float16_t act_max) |
| | Specialized NHWC depthwise 3x3 kernel (float32, ch_mult=1).
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| arm_cmsis_nn_status | arm_nn_depthwise_conv_nt_t_f16 (const float16_t *__RESTRICT lhs, const float16_t *__RESTRICT rhs, const float16_t *__RESTRICT bias, float16_t *__RESTRICT out, int32_t lhs_rows, int32_t total_ch, int32_t row_x_col, int32_t out_row_stride, float16_t activation_min, float16_t activation_max) |
| | Generic depthwise helper with packed lhs tiles and transposed rhs layout (float32).
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| void | arm_nn_conv1d_k5_nhwc_f16 (const float16_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float16_t *__RESTRICT kernel, const float16_t *__RESTRICT b, float16_t *__RESTRICT out, int32_t out_c, int32_t out_w) |
| | Specialized NHWC 1D convolution kernel for k=5 (float32).
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| void | arm_nn_conv1d_k5_packed_f16 (const float16_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float16_t *__RESTRICT kernel_packed, const float16_t *__RESTRICT b, float16_t *__RESTRICT out, int32_t out_c, int32_t out_w) |
| | Specialized NHWC 1D convolution kernel for k=5 (float16, packed weights).
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| void | arm_nn_conv1d_k3_nhwc_f16 (const float16_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float16_t *__RESTRICT kernel, const float16_t *__RESTRICT b, float16_t *__RESTRICT out, int32_t out_c, int32_t out_w) |
| | Specialized NHWC 1D convolution kernel for k=3 (float32).
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| void | arm_nn_conv1d_k3_packed_f16 (const float16_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, const float16_t *__RESTRICT kernel_packed, const float16_t *__RESTRICT b, float16_t *__RESTRICT out, int32_t out_c, int32_t out_w) |
| | Specialized NHWC 1D convolution kernel for k=3 (float16, packed weights).
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| void | arm_nn_maxpool1d_k3s3_nhwc_f16 (const float16_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, float16_t *__RESTRICT out, int32_t out_w) |
| | Specialized NHWC max-pool 1D kernel for k=3, s=3 (float16).
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| void | arm_nn_maxpool1d_k2s2_nhwc_noclip_f16 (const float16_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, float16_t *__RESTRICT out, int32_t out_w) |
| | Specialized NHWC max-pool 1D kernel for k=2, s=2 without output clamp (float16).
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| void | arm_nn_maxpool1d_k2s2_nhwc_f16 (const float16_t *__RESTRICT x_nhwc, int32_t in_c, int32_t in_w, float16_t *__RESTRICT out, int32_t out_w, float16_t act_min, float16_t act_max) |
| | Specialized NHWC max-pool 1D kernel for k=2, s=2 with clamp (float16).
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| arm_cmsis_nn_status | arm_nn_mat_mult_nt_t_f16 (const float16_t *__RESTRICT lhs, const float16_t *__RESTRICT rhs, const float16_t *__RESTRICT bias, float16_t *__RESTRICT dst, int32_t lhs_rows, int32_t rhs_rows, int32_t rhs_cols, int32_t row_address_offset, float16_t activation_min, float16_t activation_max) |
| | Matrix multiply with non-transposed lhs and transposed rhs rows (float32).
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| arm_cmsis_nn_status | arm_nn_mat_mult_nt_n_packed_f16 (const float16_t *__RESTRICT lhs, const float16_t *__RESTRICT rhs_packed, const float16_t *__RESTRICT bias, float16_t *__RESTRICT dst, int32_t lhs_rows, int32_t rhs_rows, int32_t rhs_cols, int32_t row_address_offset, float16_t activation_min, float16_t activation_max) |
| | Matrix multiply with non-transposed lhs and packed non-transposed rhs (float16).
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| arm_cmsis_nn_status | arm_nn_lstm_step_f16 (const float16_t *data_in, const float16_t *hidden_in, float16_t *hidden_out, const cmsis_nn_lstm_params_f16 *params, cmsis_nn_lstm_context_f16 *buffers, const int32_t batch_offset) |
| | Update LSTM function for an iteration step using float16 input, output and state.
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| void | arm_nn_pack_conv_patch_f16 (const float16_t *__RESTRICT input, int32_t in_h, int32_t in_w, int32_t in_c, int32_t kernel_h, int32_t kernel_w, int32_t stride_h, int32_t stride_w, int32_t pad_h, int32_t pad_w, int32_t dilation_h, int32_t dilation_w, int32_t out_y, int32_t out_x, float16_t pad_value, float16_t *__RESTRICT patch_row) |
| | Pack a single convolution patch into one row of a contiguous float32 patch matrix.
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| void | arm_nn_softmax_1x2_f16 (const float16_t in[2], float16_t out[2]) |
| | Specialized softmax helper for a single float32 row of length 2.
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| arm_cmsis_nn_status | arm_nn_lstm_step_f32 (const float32_t *data_in, const float32_t *hidden_in, float32_t *hidden_out, const cmsis_nn_lstm_params_f32 *params, cmsis_nn_lstm_context_f32 *buffers, const int32_t batch_offset) |
| | Update LSTM function for an iteration step using float32 input, output and state.
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