Hi Guys, May be very basic question. I want to understand how JTAG debugger and Break point works.
Can any one help here...?
Abhijit Dhopate
Do you actually want to know how it works - or do you really want to know how to use it?
I want to know how it works. I have use it alot. So now I am curious to understand how it works. How exactly debugging take place or what happen internally when some break point hits.
I want to know how How Debugger/Breakpoint works ... till you specify WHICH debugger.
Thre is no 'standard' for breakpoint implementation.
Erik
Note that, strictly, "JTAG" just refers to the communication interface by which you connect to the target and communicate with the on-board debug hardware.
The on-board debug hardware has links to the data bus, address bus, and internal CPU features (registers, etc) to allow it to read and (in some cases) modify them. And a breakpoint signal that allows it to stop (or "freeze") the CPU.
The on-board debug hardware also has its own registers that can be programmed (via the JTAG interface) and, when a "match" is seen in the target hardware, the breakpoint occurs. Some debug hardware also has advanced features like Trace...
I just put "how does a jtag debugger work" into google and got this as the very first hit: instruct1.cit.cornell.edu/.../index.html
I suggest you do the same, and then get googling yourself.
en.wikipedia.org/.../Joint_Test_Action_Group also has a load of links...
Also look at the ARM technical documentation: infocenter.arm.com/.../index.jsp www.arm.com/.../index.php
Hi,
if you want to know this in detail you should read the ARM Documentation on http://www.arm.com
In general (examples are for the Command Line in Debug Mode):
Hardware Breakpoint, Address Breakpoint in Flash: A special Unit (2 on ARM7/9, 6 on Cortex-M3) has Address Comparators. If a BP is set and the Address is reached, the Core stops and tells the debugger (ULINK, JLink) the reason.
BS main
Soft BPs, Address BP in RAM: Additionally in RAM the Software BP can be used. This can be an Invalid Instruction (then one HW BP on the Fault Handler is needed) or a BP Instruction
bkpt (arg)
Access BP: If a memory location is read or written a BP can be defined for that. On ARM7/9 there are the 2 Units, the Cortex-M3 has 4 independant Units for this.
1. READ, WRITE or READWRITE access: - up to 4 BPs can be set
BS READ myvar BS WRITE myvar BS READWRITE myvar
2. READ, WRITE or READWRITE on specific data access: - up to 2 BPs can be set
BS READ myvar == 0x55 BS WRITE myvar == 0x55 BS READWRITE myvar == 0x55
Of course one with data and 2 without data can be set. The Watch Unit is also used to emit Data of memory locations to be traced in the Logic analyzer.
--- There are some BP possibillities I left out, they have to do with Address Ranges and are very complex. For them you'd have to read the manual.
--- Does this help? I think this is what you need for your debugging work.
. BR, /th.
if you want to know this in detail you should read the ARM Documentation
the OP issues a non-specific question and everybody must start guessing.
It is really amazing how often the OP get silent the moment a question is pointed at him/her.
JTAG, of course, is not specific to ARM - it's an industry-wide standard (from the IEEE).
And the basic principles of what debuggers do, and how breakpoints are done are quite general.
But, of course, for specific details the OP will need to go to the appropriate documentation...
And the basic principles of what debuggers do, and how breakpoints are done are quite general the OP specified: I want to know how it works.
third (my) assumption: how it is implemented, the answer to which, I know, at least, 5 different ones (not quite general).
It seems some one having quesitons "why OP is silent when Question point to him or her" Not neccessary that every one is having liberty of internet connectivity for every time. So here some one needs to grow up and mature.
@Thorsten Thanks a lot for your reply. That helps me to clear my doubts. Initially I went through Wikipadia and search results from google but was not able to understand correctly. With co-relation of your explanation now its clear. Now I will walk through Arm documentaion as you pointed.