NXP LPC1549JBD64

ARM Cortex-M3 CPU running up to 72MHz Memory:

• Up to 256 kB on-chip flash (ISP and IAP)
• Up to 36 kB SRAM
• 4 kB EEPROM Digital peripherals:
• Simple DMA engine with 18 chn
• up to 76 General-Purpose I/O (GPIO) pins
• GPIO interrupt generation capability
• 2 GPIO grouped port interrupts
• Switch matrix for flexible configuration of each I/O pin function
• CRC engine
• Quadrature Encoder Interface (QEI) Timers
• 2 State Configurable Timers (SCT) in large config.
• 2 State Configurable Timers (SCT) in small config.
• SCT Input Pre-processor Unit (SCTIPU)
• 24-bit, 4-channel, multi-rate timer (MRT)
• Repetitive interrupt timer
• Windowed Watchdog timer (WWDT)
• High-resolution 32-bit Real-time clock (RTC) Analog peripherals:
• 2 12-bit ADC with up to 12 input chn per ADC
• 1 12-bit DAC
• Integrated temperature sensor
• 4 comparators Serial interfaces:
• 3 USART interfaces
• 2 SPI controllers
• 1 I2C-bus interface
• 1 C_CAN controller
• 1 USB 2.0 FS device controller with on-chip PHY Clock generation:
• 12 MHz internal RC osc.
• Crystal osc. (operating range of 1 MHz to 25 MHz)
• Programmable watchdog osc.
• 32 kHz low-power RTC osc.
• System PLL allows CPU operation up to the maximum CPU rate
• 2 additional PLLs for generating the USB and SCT clocks
• Clock output function with divider that can reflect various clocks Power control:
• Integrated PMU (Power Management Unit)
• Reduced power modes: Sleep, Deep-sleep, Power-down, Deep power-down
• APIs provided for optimizing power consumption
• Wake-up from Deep-sleep and Power-down modes on activity on USB, USART, SPI, I2C
• Timer-controlled self wake-up from Deep power-down
• Power-On Reset (POR)
• BrownOut Detect BOD) Unique device serial number for identification