Microchip ATSAM4CMP32C
Hz, , Hz, , , 120 MHz, , 120 MHz, 2 MB ROM, 272 kB RAM
Symmetrical/Asynchronous Dual Core Architecture - Interrupt-based Interprocessor Communication - Cryptography - Physical Anti-tamper Detection I/O - Security bit for Device Protection - Segmented LCD Controller - Two-phase (SAM4CMS) or three-phase (SAM4CMP) Energy Metering Analog-Front-End - SW Controlled On-Chip Reference ranging from 1.6V to 3.4V - Temperature Sensor and Backup Battery Voltage Measurement Channel
- Processor:Hz,
- Processor:Hz,
- Processor:, MPU 120 MHz
- Processor:, FPU 120 MHz
- Cryptographic Engine:1 -bit AES, CPKCC, ICM (SHA), TRNG
- External Bus Interface:8 -bit External Bus Interface
- ROM:1 MB32 kB
- ROM:1 MB
- RAM:256 kB16 kB
- Maximum Clock Frequency: , 120 MHz, 120 MHz,
- SPI:1 x SPI Interface
- UART:2 x UART Interface
- USART:3 x USART Interface
- Other:2 x TWI Two-wire Interface
- Watchdog:1 x Watchdog Timer
- Timer/Counter:6 x 16-bit Timer
- PWM:3 x 16-bit Pulse Width Modulation
- ADC:8-channel x 10 bit ADC
- Other:7 x Energy Metering Analog-Front -End
- I/Os:52 General Purpose I/Os
- Package, QFP:100-lead LQFP Package
| Development Tools | |
| CMSIS Drivers | No CMSIS-Driver in Device Family Pack. |
| Examples |
|
