//----------------------------------------------------------------------------- // C8051F520.h //----------------------------------------------------------------------------- // Copyright 2006 Silicon Laboratories, Inc. // http://www.silabs.com // // Program Description: // // Register/bit definitions for the C8051F52x/F53x family. // // // FID: 52X000008 // Target: C8051F52x, 'F53x // Tool chain: Keil // Command Line: None // // Release 1.0 (CG, based on PKC's 'F32x Golden Standard) // -First release after new firmware coding standard //----------------------------------------------------------------------------- // Header File Preprocessor Directive //----------------------------------------------------------------------------- #ifndef C8051F520_H #define C8051F520_H #ifndef COMPILER_H #define COMPILER_H //----------------------------------------------------------------------------- // Macro definitions //----------------------------------------------------------------------------- // The following macro definitions have been adapted from SDCC file compiler.h // This file is free software; you can redistribute it and/or modify it // under the terms of the GNU Lesser General Public License as published by // the Free Software Foundation; either version 2.1 of the License, or // (at your option) any later version. // This header file is to overcome 8051 compiler differences for specifying // special function registers. The following compilers are supported: // SDCC, Keil, Raisonance, IAR, Hi-Tech, Tasking, Crossware, Wickenhäuser. // SBIT and SFR define special bit and special function registers at the given // address. SFR16 and SFR32 define sfr combinations at adjacent addresses in // little-endian format. SFR16E and SFR32E define sfr combinations without // prerequisite byte order or adjacency. None of these multi-byte sfr // combinations will guarantee the order in which they are accessed when read // or written. // SDCC - Small Device C Compiler // http://sdcc.sf.net #if defined SDCC # define SBIT(name, addr, bit) __sbit __at(addr+bit) name # define SFR(name, addr) __sfr __at(addr) name # define SFR16(name, addr) __sfr16 __at(((addr+1)<<8) | addr) name # define SFR16E(name, fulladdr) __sfr16 __at(fulladdr) name # define SFR32(name, addr) __sfr32 __at(((addr+3)<<24) | ((addr+2)<<16) | ((addr+1)<<8) | addr) name # define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name // Keil C51 // http://www.keil.com #elif defined __C51__ # define SBIT(name, addr, bit) sbit name = addr^bit # define SFR(name, addr) sfr name = addr # define SFR16(name, addr) sfr16 name = addr # define SFR16E(name, fulladdr) /* not supported */ # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ // Raisonance // http://www.raisonance.com #elif defined __RC51__ # define SBIT(name, addr, bit) at (addr+bit) sbit name # define SFR(name, addr) sfr at addr name # define SFR16(name, addr) sfr16 at addr name # define SFR16E(name, fulladdr) /* not supported */ # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ // IAR 8051 // http://www.iar.com #elif defined __ICC8051__ # define SBIT(name, addr, bit) __bit __no_init volatile bool name @ (addr+bit) # define SFR(name, addr) __sfr __no_init volatile unsigned char name @ addr # define SFR16(name, addr) __sfr __no_init volatile unsigned int name @ addr # define SFR16E(name, fulladdr) /* not supported */ # define SFR32(name, fulladdr) __sfr __no_init volatile unsigned long name @ addr # define SFR32E(name, fulladdr) /* not supported */ // Tasking / Altium // http://www.altium.com/tasking #elif defined _CC51 # define SBIT(name, addr, bit) _sfrbit name _at(addr+bit) # define SFR(name, addr) _sfrbyte name _at(addr) # define SFR16(name, addr) /* not supported */ # define SFR16E(name, fulladdr) /* not supported */ # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ // Hi-Tech 8051 // http://www.htsoft.com #elif defined HI_TECH_C # define SBIT(name, addr, bit) volatile bit name @ (addr+bit) # define SFR(name, addr) volatile unsigned char name @ addr # define SFR16(name, addr) /* not supported */ # define SFR16E(name, fulladdr) /* not supported */ # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ // Crossware // http://www.crossware.com #elif defined _XC51_VER # define SBIT(name, addr, bit) _sfrbit name = (addr+bit) # define SFR(name, addr) _sfr name = addr # define SFR16(name, addr) _sfrword name = addr # define SFR16E(name, fulladdr) /* not supported */ # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ // Wickenhäuser // http://www.wickenhaeuser.de #elif defined __UC__ # define SBIT(name, addr, bit) unsigned char bit name @ (addr+bit) # define SFR(name, addr) near unsigned char name @ addr # define SFR16(name, addr) /* not supported */ # define SFR16E(name, fulladdr) /* not supported */ # define SFR32(name, fulladdr) /* not supported */ # define SFR32E(name, fulladdr) /* not supported */ // default // unknown compiler #elif # define SBIT(name, addr, bit) volatile bool # define SFR(name, addr) volatile unsigned char # define SFR16(name, addr) volatile short # define SFR16E(name, fulladdr) volatile short # define SFR32(name, fulladdr) volatile int # define SFR32E(name, fulladdr) volatile int #endif /* BYTE Registers */ SFR (P0, 0x80); // PORT 0 sfr SFR (SP, 0x81); // STACK POINTER SFR (DPL, 0x82); // DATA POINTER - LOW BYTE SFR (DPH, 0x83); // DATA POINTER - HIGH BYTE SFR (PCON, 0x87); // POWER CONTROL SFR (TCON, 0x88); // TIMER CONTROL SFR (TMOD, 0x89); // TIMER MODE SFR (TL0, 0x8A); // TIMER 0 - LOW BYTE SFR (TL1, 0x8B); // TIMER 1 - LOW BYTE SFR (TH0, 0x8C); // TIMER 0 - HIGH BYTE SFR (TH1, 0x8D); // TIMER 1 - HIGH BYTE SFR (CKCON, 0x8E); // CLOCK CONTROL SFR (PSCTL, 0x8F); // PROGRAM STORE R/W CONTROL SFR (P1, 0x90); // PORT 1 SFR (LINADDR, 0x92); // LIN Indirect Access Address Register SFR (LINDATA, 0x93); // LIN Indirect Access Data Register SFR (LINCF, 0x95); // LIN configuration register SFR (SCON0, 0x98); // SERIAL PORT 0 CONTROL SFR (SBUF0, 0x99); // SERIAL PORT 0 BUFFER SFR (CPT0CN, 0x9B); // COMPARATOR 0 MODE SFR (CPT0MD, 0x9D); // COMPARATOR 0 MODE SFR (CPT0MX, 0x9F); // COMPARATOR 0 MUX SFR (DSRFLG, 0xA0); // DSR FLAG Register (DBI only) SFR (SPI0CFG, 0xA1); // SPI CONFIG SFR (SPI0CKR, 0xA2); // SPI CLOCK RATE SFR (SPI0DAT, 0xA3); // SPI DATA SFR (P0MDOUT, 0xA4); // PORT 0 OUTPUT MODE SFR (P1MDOUT, 0xA5); // PORT 1 MODE OUT SFR (IE, 0xA8); // INTERRUPT ENABLE SFR (CLKSEL, 0xA9); // CLOCK SELECT Register SFR (OSCIFIN, 0xB0); // INTERNAL FINE OSCILLATOR CALIBRATION SFR (OSCXCN, 0xB1); // EXTERNAL OSCILLATOR CONTROL SFR (OSCICN, 0xB2); // INTERNAL OSCILLATOR CONTROL SFR (OSCICL, 0xB3); // INTERNAL OSCILLATOR CALIBRATION SFR (FLKEY, 0xB7); // FLASH LOCK & KEY SFR (IP, 0xB8); // INTERRUPT PRIORITY SFR (ADC0TK, 0xBA); // IDAC 0 Control Register SFR (ADC0MX, 0xBB); // ADC 0 MUX CHANNEL SELECTION SFR (ADC0CF, 0xBC); // ADC 0 CONFIGURATION SFR (ADC0L, 0xBD); // ADC 0 LSB Result SFR (ADC0H, 0xBE); // ADC 0 DATA SFR (P1MASK, 0xBF); // Port1 MASK Register SFR (ADC0GTL, 0xC3); // ADC 0 GreaterThan LSB SFR (ADC0GTH, 0xC4); // ADC 0 GreaterThan MSB SFR (ADC0LTL, 0xC5); // ADC 0 LessThan LSB SFR (ADC0LTH, 0xC6); // ADC 0 LessThan MSB SFR (P0MASK, 0xC7); // Port1 MASK Register SFR (TMR2CN, 0xC8); // TIMER 2 CONTROL SFR (REG0CN, 0xC9); // Regulator Control SFR (TMR2RLL, 0xCA); // TIMER 2 RELOAD LOW SFR (TMR2RLH, 0xCB); // TIMER 2 RELOAD HIGH SFR (TMR2L, 0xCC); // TIMER 2 LOW BYTE SFR (TMR2H, 0xCD); // TIMER 2 HIGH BYTE SFR (P1MAT, 0xCF); // Port1 match register SFR (PSW, 0xD0); // PROGRAM STATUS WORD SFR (REF0CN, 0xD1); // VOLTAGE REFERENCE 0 CONTROL SFR (P0SKIP, 0xD4); // PORT 0 SKIP SFR (P1SKIP, 0xD5); // PORT 1 SKIP SFR (P0MAT, 0xD7); // P0 match register SFR (PCA0CN, 0xD8); // PCA0 CONTROL SFR (PCA0MD, 0xD9); // PCA0 MODE SFR (PCA0CPM0, 0xDA); // PCA0 MODULE 0 MODE SFR (PCA0CPM1, 0xDB); // PCA0 MODULE 1 MODE SFR (PCA0CPM2, 0xDC); // PCA0 MODULE 2 MODE SFR (ACC, 0xE0); // ACCUMULATOR SFR (XBR0, 0xE1); // DIGITAL CROSSBAR CONFIGURATION REGISTER 0 SFR (XBR1, 0xE2); // DIGITAL CROSSBAR CONFIGURATION REGISTER 1 SFR (CACHCN, 0xE3); // DIGITAL CROSSBAR CONFIGURATION REGISTER 2 SFR (IT01CF, 0xE4); // INT0/INT1 CONFIGURATION SFR (EIE1, 0xE6); // EXTENDED INTERRUPT ENABLE 1 SFR (ADC0CN, 0xE8); // ADC 0 CONTROL SFR (PCA0CPL1, 0xE9); // PCA0 MODULE 1 CAPTURE/COMPARE REGISTER LOW BYTE SFR (PCA0CPH1, 0xEA); // PCA0 MODULE 1 CAPTURE/COMPARE REGISTER HIGH BYTE SFR (PCA0CPL2, 0xEB); // PCA0 MODULE 2 CAPTURE/COMPARE REGISTER LOW BYTE SFR (PCA0CPH2, 0xEC); // PCA0 MODULE 2 CAPTURE/COMPARE REGISTER HIGH BYTE SFR (RSTSRC, 0xEF); // RESET SOURCE SFR (B, 0xF0); // B REGISTER SFR (P0MDIN, 0xF1); // PORT 0 INPUT MODE REGISTER SFR (P1MDIN, 0xF2); // P1 Input Mode Register SFR (EIP1, 0xF6); // EXTENDED INTERRUPT PRIORITY 1 SFR (SPI0CN, 0xF8); // SPI0 CONTROL SFR (PCA0L, 0xF9); // PCA0 COUNTER REGISTER LOW BYTE SFR (PCA0H, 0xFA); // PCA0 COUNTER REGISTER HIGH BYTE SFR (PCA0CPL0, 0xFB); // PCA MODULE 0 CAPTURE/COMPARE REGISTER LOW BYTE SFR (PCA0CPH0, 0xFC); // PCA MODULE 0 CAPTURE/COMPARE REGISTER HIGH BYTE SFR (VDM0CN, 0xFF); // Vdd Monitor register // BIT Registers */ // TCON 0x88 */ SBIT (IT0, 0x88, 0); // EXT INTERRUPT 0 TYPE SBIT (IE0, 0x88, 1); // EXT INTERRUPT 0 EDGE FLAG SBIT (IT1, 0x88, 2); // EXT INTERRUPT 1 TYPE SBIT (IE1, 0x88, 3); // EXT INTERRUPT 1 EDGE FLAG SBIT (TR0, 0x88, 4); // TIMER 0 ON/OFF CONTROL SBIT (TF0, 0x88, 5); // TIMER 0 OVERFLOW FLAG SBIT (TR1, 0x88, 6); // TIMER 1 ON/OFF CONTROL SBIT (TF1, 0x88, 7); // TIMER 1 OVERFLOW FLAG //; TMR2CN SBIT (TF2H, 0xC8, 7); // T2 High-Byte OVERFLOW FLAG SBIT (TF2L, 0xC8, 6); // T2 Low-Byte OVERFLOW FLAG SBIT (TF2LEN, 0xC8, 5); // T2 Low-Byte FLAG ENABLE SBIT (TF2CEN, 0xC8, 4); // T2 Capture Enable SBIT (T2SPLIT, 0xC8, 3); // T2 SPLIT-MODE ENABLE SBIT (TR2, 0xC8, 2); // TIMER 2 ON/OFF CONTROL SBIT (T2RCLK, 0xC8, 1); // XCLK/RCLK Select SBIT (T2XCLK, 0xC8, 0); // T2 CLK/8 CLOCK SOURCE /* SCON0 0x98 */ SBIT (RI0, 0x98, 0); // RECEIVE INTERRUPT FLAG SBIT (TI0, 0x98, 1); // TRANSMIT INTERRUPT FLAG SBIT (RB80, 0x98, 2); // RECEIVE BIT 8 SBIT (TB80, 0x98, 3); // TRANSMIT BIT 8 SBIT (REN0, 0x98, 4); // RECEIVE ENABLE SBIT (MCE0, 0x98, 5); // MULTIPROCESSOR COMMUNICATION ENABLE SBIT (S0MODE, 0x98, 7); // SERIAL MODE CONTROL BIT 0 /* IE 0xA8 */ SBIT (EX0, 0xA8, 0); // EXTERNAL INTERRUPT 0 ENABLE SBIT (ET0, 0xA8, 1); // TIMER 0 INTERRUPT ENABLE SBIT (EX1, 0xA8, 2); // EXTERNAL INTERRUPT 1 ENABLE SBIT (ET1, 0xA8, 3); // TIMER 1 INTERRUPT ENABLE SBIT (ES0, 0xA8, 4); // UART0 INTERRUPT ENABLE SBIT (ET2, 0xA8, 5); // TIMER 2 INTERRUPT ENABLE SBIT (ESPI0, 0xA8, 6); // CG 6/13 -> SPI0 Interrupt enable SBIT (EA, 0xA8, 7); // GLOBAL INTERRUPT ENABLE /* IP 0xB8 */ SBIT (PX0, 0xB8, 0); // EXTERNAL INTERRUPT 0 PRIORITY SBIT (PT0, 0xB8, 1); // TIMER 0 PRIORITY SBIT (PX1, 0xB8, 2); // EXTERNAL INTERRUPT 1 PRIORITY SBIT (PT1, 0xB8, 3); // TIMER 1 PRIORITY SBIT (PS0, 0xB8, 4); // UART0 PRIORITY SBIT (PT2, 0xB8, 5); // TIMER 2 PRIORITY SBIT (PSPI0, 0xB8, 6); // CG 6/13/06 -> SPI0 Interrupt Priority /* PSW 0xD0 */ SBIT (P, 0xD0, 0); // ACCUMULATOR PARITY FLAG SBIT (F1, 0xD0, 1); // USER FLAG 1 SBIT (OV, 0xD0, 2); // OVERFLOW FLAG SBIT (RS0, 0xD0, 3); // REGISTER BANK SELECT 0 SBIT (RS1, 0xD0, 4); // REGISTER BANK SELECT 1 SBIT (F0, 0xD0, 5); // USER FLAG 0 SBIT (AC, 0xD0, 6); // AUXILIARY CARRY FLAG SBIT (CY, 0xD0, 7); // CARRY FLAG /* PCA0CN 0xD8H */ SBIT (CCF0, 0xD8, 0); // PCA 0 MODULE 0 INTERRUPT FLAG SBIT (CCF1, 0xD8, 1); // PCA 0 MODULE 1 INTERRUPT FLAG SBIT (CCF2, 0xD8, 2); // PCA 0 MODULE 2 INTERRUPT FLAG SBIT (CR, 0xD8, 6); // PCA 0 COUNTER RUN CONTROL BIT SBIT (CF, 0xD8, 7); // PCA 0 COUNTER OVERFLOW FLAG /* ADC0CN 0xE8H */ SBIT (AD0CM0, 0xE8, 0); // ADC 0 START Of CONVERSION MODE BIT 0 SBIT (AD0CM1, 0xE8, 1); // ADC 0 START OF CONVERSION MODE BIT 1 SBIT (AD0LJST, 0xE8, 2); // CG 6/13/06 -> ADC 0 Left Justified SBIT (AD0WINT, 0xE8, 3); // ADC 0 WINDOW COMPARE INTERRUPT FLAG SBIT (AD0BUSY, 0xE8, 4); // ADC 0 BUSY FLAG SBIT (AD0INT, 0xE8, 5); // ADC 0 CONVERSION COMPLETE INTERRUPT FLAG SBIT (BURSTEN, 0xE8, 6); // ADC 0 BURST ENABLE SBIT (AD0EN, 0xE8, 7); // ADC 0 ENABLE //; SPI0CN SBIT (SPIEN, 0xF8, 0); // SPI 0 SPI ENABLE SBIT (TXBMT, 0xF8, 1); // SPI 0 TRANSMIT BUFFER EMPTY FLAG SBIT (NSSMD0, 0xF8, 2); // SPI 0 NSS MODE BIT 0 SBIT (NSSMD1, 0xF8, 3); // SPI 0 NSS MODE BIT 1 SBIT (RXOVRN, 0xF8, 4); // SPI 0 RX OVERRUN FLAG SBIT (MODF, 0xF8, 5); // SPI 0 MODE FAULT FLAG SBIT (WCOL, 0xF8, 6); // SPI 0 WRITE COLLISION FLAG SBIT (SPIF, 0xF8, 7); // SPI 0 INTERRUPT FLAG //----------------------------------------------------------------------------- // Interrupt Priorities //----------------------------------------------------------------------------- #define INTERRUPT_INT0 0 // External Interrupt 0 #define INTERRUPT_TIMER0 1 // Timer0 Overflow #define INTERRUPT_INT1 2 // External Interrupt 1 #define INTERRUPT_TIMER1 3 // Timer1 Overflow #define INTERRUPT_UART0 4 // Serial Port 0 #define INTERRUPT_TIMER2 5 // Timer2 Overflow #define INTERRUPT_SPI0 6 // Serial Peripheral Interface 0 #define INTERRUPT_ADC0_WINDOW 7 // ADC0 Window Comparison #define INTERRUPT_ADC0_EOC 8 // ADC0 End Of Conversion #define INTERRUPT_PCA0 9 // PCA0 Peripheral #define INTERRUPT_COMPARATOR_FALLING 10// Comparator Falling edge #define INTERRUPT_COMPARATOR_RISING 11// Comparator Rising edge #define INTERRUPT_LIN 12 // LIN interrupt #define INTERRUPT_VREG 13 // Voltage Regulator Dropout #define INTERRUPT_PORT_MATCH 14 // Port Match //----------------------------------------------------------------------------- // Header File Preprocessor Directive //----------------------------------------------------------------------------- #endif // #define COMPILER_H #endif // #define C8051F520_H //----------------------------------------------------------------------------- // End Of File //-----------------------------------------------------------------------------