/*-------------------------------------------------------------------------- C167CS.H Register Declarations for Infineon C167CS in alphabetic order Based on the Siemens C167CS User Manual V1.0 1999-05 Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc. All rights reserved. The CAN Control Registers within X-Peripherals are defined in the CAN.H and CAN167.H include files. ---------------------------------------------------------------------------*/ #ifndef __C167CS_H__ #define __C167CS_H__ sfr ADCIC = 0xFF98; // A/D Converter End of Conversion Interrupt Control Register sfr ADCON = 0xFFA0; // A/D Converter Control Register sfr ADDAT = 0xFEA0; // A/D Converter Result Register sfr ADDAT2 = 0xF0A0; // H A/D Converter 2 Result Register sfr ADDRSEL1 = 0xFE18; // Address Select Register 1 sfr ADDRSEL2 = 0xFE1A; // Address Select Register 2 sfr ADDRSEL3 = 0xFE1C; // Address Select Register 3 sfr ADDRSEL4 = 0xFE1E; // Address Select Register 4 sfr ADEIC = 0xFF9A; // A/D Converter Overrun Error Interrupt Control Register sfr BUSCON0 = 0xFF0C; // Bus Configuration Register 0 0XX0 H sfr BUSCON1 = 0xFF14; // Bus Configuration Register 1 sfr BUSCON2 = 0xFF16; // Bus Configuration Register 2 sfr BUSCON3 = 0xFF18; // Bus Configuration Register 3 sfr BUSCON4 = 0xFF1A; // Bus Configuration Register 4 sfr CAPREL = 0xFE4A; // GPT2 Capture/Reload Register sfr CC0 = 0xFE80; // CAPCOM Register 0 sfr CC0IC = 0xFF78; // CAPCOM Register 0 Interrupt Control Register sfr CC1 = 0xFE82; // CAPCOM Register 1 sfr CC10 = 0xFE94; // CAPCOM Register 10 sfr CC10IC = 0xFF8C; // CAPCOM Register 10 Interrupt Control Register sfr CC11 = 0xFE96; // CAPCOM Register 11 sfr CC11IC = 0xFF8E; // CAPCOM Register 11 Interrupt Control Register sfr CC12 = 0xFE98; // CAPCOM Register 12 sfr CC12IC = 0xFF90; // CAPCOM Register 12 Interrupt Control Register sfr CC13 = 0xFE9A; // CAPCOM Register 13 sfr CC13IC = 0xFF92; // CAPCOM Register 13 Interrupt Control Register sfr CC14 = 0xFE9C; // CAPCOM Register 14 sfr CC14IC = 0xFF94; // CAPCOM Register 14 Interrupt Control Register sfr CC15 = 0xFE9E; // CAPCOM Register 15 sfr CC15IC = 0xFF96; // CAPCOM Register 15 Interrupt Control Register sfr CC16 = 0xFE60; // CAPCOM Register 16 sfr CC16IC = 0xF160; // CAPCOM Register 16 Interrupt Control Register sfr CC17 = 0xFE62; // CAPCOM Register 17 sfr CC17IC = 0xF162; // CAPCOM Register 17 Interrupt Control Register sfr CC18 = 0xFE64; // CAPCOM Register 18 sfr CC18IC = 0xF164; // CAPCOM Register 18 Interrupt Control Register sfr CC19 = 0xFE66; // CAPCOM Register 19 sfr CC19IC = 0xF166; // CAPCOM Register 19 Interrupt Control Register sfr CC1IC = 0xFF7A; // CAPCOM Register 1 Interrupt Control Register sfr CC2 = 0xFE84; // CAPCOM Register 2 sfr CC20 = 0xFE68; // CAPCOM Register 20 sfr CC20IC = 0xF168; // CAPCOM Register 20 Interrupt Control Register sfr CC21 = 0xFE6A; // CAPCOM Register 21 sfr CC21IC = 0xF16A; // CAPCOM Register 21 Interrupt Control Register sfr CC22 = 0xFE6C; // CAPCOM Register 22 sfr CC22IC = 0xF16C; // CAPCOM Register 22 Interrupt Control Register sfr CC23 = 0xFE6E; // CAPCOM Register 23 sfr CC23IC = 0xF16E; // CAPCOM Register 23 Interrupt Control Register sfr CC24 = 0xFE70; // CAPCOM Register 24 sfr CC24IC = 0xF170; // CAPCOM Register 24 Interrupt Control Register sfr CC25 = 0xFE72; // CAPCOM Register 25 sfr CC25IC = 0xF172; // CAPCOM Register 25 Interrupt Control Register sfr CC26 = 0xFE74; // CAPCOM Register 26 sfr CC26IC = 0xF174; // CAPCOM Register 26 Interrupt Control Register sfr CC27 = 0xFE76; // CAPCOM Register 27 sfr CC27IC = 0xF176; // CAPCOM Register 27 Interrupt Control Register sfr CC28 = 0xFE78; // CAPCOM Register 28 sfr CC28IC = 0xF178; // CAPCOM Register 28 Interrupt Control Register sfr CC29 = 0xFE7A; // CAPCOM Register 29 sfr CC29IC = 0xF184; // CAPCOM Register 29 Interrupt Control Register sfr CC2IC = 0xFF7C; // CAPCOM Register 2 Interrupt Control Register sfr CC3 = 0xFE86; // CAPCOM Register 3 sfr CC30 = 0xFE7C; // CAPCOM Register 30 sfr CC30IC = 0xF18C; // CAPCOM Register 30 Interrupt Control Register sfr CC31 = 0xFE7E; // CAPCOM Register 31 sfr CC31IC = 0xF194; // CAPCOM Register 31 Interrupt Control Register sfr CC3IC = 0xFF7E; // CAPCOM Register 3 Interrupt Control Register sfr CC4 = 0xFE88; // CAPCOM Register 4 sfr CC4IC = 0xFF80; // CAPCOM Register 4 Interrupt Control Register sfr CC5 = 0xFE8A; // CAPCOM Register 5 sfr CC5IC = 0xFF82; // CAPCOM Register 5 Interrupt Control Register sfr CC6 = 0xFE8C; // CAPCOM Register 6 sfr CC6IC = 0xFF84; // CAPCOM Register 6 Interrupt Control Register sfr CC7 = 0xFE8E; // CAPCOM Register 7 sfr CC7IC = 0xFF86; // CAPCOM Register 7 Interrupt Control Register sfr CC8 = 0xFE90; // CAPCOM Register 8 sfr CC8IC = 0xFF88; // CAPCOM Register 8 Interrupt Control Register sfr CC9 = 0xFE92; // CAPCOM Register 9 sfr CC9IC = 0xFF8A; // CAPCOM Register 9 Interrupt Control Register sfr CCM0 = 0xFF52; // CAPCOM Mode Control Register 0 sfr CCM1 = 0xFF54; // CAPCOM Mode Control Register 1 sfr CCM2 = 0xFF56; // CAPCOM Mode Control Register 2 sfr CCM3 = 0xFF58; // CAPCOM Mode Control Register 3 sfr CCM4 = 0xFF22; // CAPCOM Mode Control Register 4 sfr CCM5 = 0xFF24; // CAPCOM Mode Control Register 5 sfr CCM6 = 0xFF26; // CAPCOM Mode Control Register 6 sfr CCM7 = 0xFF28; // CAPCOM Mode Control Register 7 sfr CP = 0xFE10; // CPU Context Pointer Register FC00 H sfr CRIC = 0xFF6A; // GPT2 CAPREL Interrupt Control Register sfr CSP = 0xFE08; // CPU Code Segment Pointer Register (read only) sfr DP0L = 0xF100; // P0L Direction Control Register sfr DP0H = 0xF102; // P0H Direction Control Register sfr DP1L = 0xF104; // P1L Direction Control Register sfr DP1H = 0xF106; // P1H Direction Control Register sfr DP2 = 0xFFC2; // Port 2 Direction Control Register sfr DP3 = 0xFFC6; // Port 3 Direction Control Register sfr DP4 = 0xFFCA; // Port 4 Direction Control Register sfr DP6 = 0xFFCE; // Port 6 Direction Control Register sfr DP7 = 0xFFD2; // Port 7 Direction Control Register sfr DP8 = 0xFFD6; // Port 8 Direction Control Register sfr DPP0 = 0xFE00; // CPU Data Page Pointer 0 Register (10 bits) sfr DPP1 = 0xFE02; // CPU Data Page Pointer 1 Register (10 bits) sfr DPP2 = 0xFE04; // CPU Data Page Pointer 2 Register (10 bits) sfr DPP3 = 0xFE06; // CPU Data Page Pointer 3 Register (10 bits) sfr EXICON = 0xF1C0; // External Interrupt Control Register sfr EXISEL = 0xF1DA; // External Interrupt Source Select Register sfr FOCON = 0xFFAA; // Frequency Output Control Register sfr IDCHIP = 0xF07C; // Identifier sfr IDMANUF = 0xF07E; // Identifier sfr IDMEM = 0xF07A; // Identifier sfr IDMEM2 = 0xF076; // Identifier sfr IDPROG = 0xF078; // Identifier sfr ISNC = 0xF1DE; // Interrupt Subnode Control Register sfr MDC = 0xFF0E; // CPU Multiply Divide Control Register sfr MDH = 0xFE0C; // CPU Multiply Divide Register - High Word sfr MDL = 0xFE0E; // CPU Multiply Divide Register - Low Word sfr ODP2 = 0xF1C2; // Port 2 Open Drain Control Register sfr ODP3 = 0xF1C6; // Port 3 Open Drain Control Register sfr ODP4 = 0xF1CA; // Port 4 Open Drain Control Register sfr ODP6 = 0xF1CE; // Port 6 Open Drain Control Register sfr ODP7 = 0xF1D2; // Port 7 Open Drain Control Register sfr ODP8 = 0xF1D6; // Port 8 Open Drain Control Register sfr ONES = 0xFF1E; // Constant Value 1’s Register (read only) sfr P0H = 0xFF02; // Port 0 High Register (Upper half of PORT0) sfr P0L = 0xFF00; // Port 0 Low Register (Lower half of PORT0) sfr P1DIDIS = 0xFEA4; // Port 1 Digital Input Disable Register sfr P1H = 0xFF06; // Port 1 High Register (Upper half of PORT1) sfr P1L = 0xFF04; // Port 1 Low Register (Lower half of PORT1) sfr P2 = 0xFFC0; // Port 2 Register sfr P3 = 0xFFC4; // Port 3 Register sfr P4 = 0xFFC8; // Port 4 Register (8 bits) sfr P5 = 0xFFA2; // Port 5 Register (read only) sfr P5DIDIS = 0xFFA4; // Port 5 Digital Input Disable Register sfr P6 = 0xFFCC; // Port 6 Register (8 bits) sfr P7 = 0xFFD0; // Port 7 Register (8 bits) sfr P8 = 0xFFD4; // Port 8 Register (8 bits) sfr PECC0 = 0xFEC0; // PEC Channel 0 Control Register sfr PECC1 = 0xFEC2; // PEC Channel 1 Control Register sfr PECC2 = 0xFEC4; // PEC Channel 2 Control Register sfr PECC3 = 0xFEC6; // PEC Channel 3 Control Register sfr PECC4 = 0xFEC8; // PEC Channel 4 Control Register sfr PECC5 = 0xFECA; // PEC Channel 5 Control Register sfr PECC6 = 0xFECC; // PEC Channel 6 Control Register sfr PECC7 = 0xFECE; // PEC Channel 7 Control Register sfr PICON = 0xF1C4; // Port Input Threshold Control Register sfr POCON0H = 0xF082; // Port P0H Output Control Register sfr POCON0L = 0xF080; // Port P0L Output Control Register sfr POCON1H = 0xF086; // Port P1H Output Control Register sfr POCON1L = 0xF084; // Port P1L Output Control Register sfr POCON2 = 0xF088; // Port P2 Output Control Register sfr POCON20 = 0xF0AA; // Dedicated Pin Output Control Register sfr POCON3 = 0xF08A; // Port P3 Output Control Register sfr POCON4 = 0xF08C; // Port P4 Output Control Register sfr POCON6 = 0xF08E; // Port P6 Output Control Register sfr POCON7 = 0xF090; // Port P7 Output Control Register sfr POCON8 = 0xF092; // Port P8 Output Control Register sfr PP0 = 0xF038; // PWM Module Period Register 0 sfr PP1 = 0xF03A; // PWM Module Period Register 1 sfr PP2 = 0xF03C; // PWM Module Period Register 2 sfr PP3 = 0xF03E; // PWM Module Period Register 3 sfr PSW = 0xFF10; // CPU Program Status Word sfr PT0 = 0xF030; // PWM Module Up/Down Counter 0 sfr PT1 = 0xF032; // PWM Module Up/Down Counter 1 sfr PT2 = 0xF034; // PWM Module Up/Down Counter 2 sfr PT3 = 0xF036; // PWM Module Up/Down Counter 3 sfr PTCR = 0xF0AE; // Port Temperature Compensation Register sfr PW0 = 0xFE30; // PWM Module Pulse Width Register 0 sfr PW1 = 0xFE32; // PWM Module Pulse Width Register 1 sfr PW2 = 0xFE34; // PWM Module Pulse Width Register 2 sfr PW3 = 0xFE36; // PWM Module Pulse Width Register 3 sfr PWMCON0 = 0xFF30; // PWM Module Control Register 0 sfr PWMCON1 = 0xFF32; // PWM Module Control Register 1 sfr PWMIC = 0xF17E; // PWM Module Interrupt Control Register sfr RP0H = 0xF108; // System Startup Configuration Register (Rd. only) sfr RTCH = 0xF0D6; // RTC High Register sfr RTCL = 0xF0D4; // RTC Low Register sfr S0BG = 0xFEB4; // Serial Channel 0 Baud Rate Generator Reload Register sfr S0CON = 0xFFB0; // Serial Channel 0 Control Register sfr S0EIC = 0xFF70; // Serial Channel 0 Error Interrupt Control Register sfr S0RBUF = 0xFEB2; // Serial Channel 0 Receive Buffer Register (read only) sfr S0RIC = 0xFF6E; // Serial Channel 0 Receive Interrupt Control Register sfr S0TBIC = 0xF19C; // Serial Channel 0 Transmit Buffer Interrupt Control Register sfr S0TBUF = 0xFEB0; // Serial Channel 0 Transmit Buffer Register (write only) sfr S0TIC = 0xFF6C; // Serial Channel 0 Transmit Interrupt Control Register sfr SP = 0xFE12; // CPU System Stack Pointer Register sfr SSCBR = 0xF0B4; // SSC Baudrate Register sfr SSCCON = 0xFFB2; // SSC Control Register sfr SSCEIC = 0xFF76; // SSC Error Interrupt Control Register sfr SSCRB = 0xF0B2; // SSC Receive Buffer sfr SSCRIC = 0xFF74; // SSC Receive Interrupt Control Register sfr SSCTB = 0xF0B0; // SSC Transmit Buffer sfr SSCTIC = 0xFF72; // SSC Transmit Interrupt Control Register sfr STKOV = 0xFE14; // CPU Stack Overflow Pointer Register sfr STKUN = 0xFE16; // CPU Stack Underflow Pointer Register sfr SYSCON = 0xFF12; // CPU System Configuration Register sfr SYSCON1 = 0xF1DC; // CPU System Configuration Register 1 sfr SYSCON2 = 0xF1D0; // CPU System Configuration Register 2 sfr SYSCON3 = 0xF1D4; // CPU System Configuration Register 3 sfr T0 = 0xFE50; // CAPCOM Timer 0 Register sfr T01CON = 0xFF50; // CAPCOM Timer 0 and Timer 1 Control Register sfr T0IC = 0xFF9C; // CAPCOM Timer 0 Interrupt Control Register sfr T0REL = 0xFE54; // CAPCOM Timer 0 Reload Register sfr T1 = 0xFE52; // CAPCOM Timer 1 Register sfr T1IC = 0xFF9E; // CAPCOM Timer 1 Interrupt Control Register sfr T1REL = 0xFE56; // CAPCOM Timer 1 Reload Register sfr T14 = 0xF0D2; // RTC Timer 14 Register sfr T14REL = 0xF0D0; // RTC Timer 14 Reload Register sfr T2 = 0xFE40; // GPT1 Timer 2 Register sfr T2CON = 0xFF40; // GPT1 Timer 2 Control Register sfr T2IC = 0xFF60; // GPT1 Timer 2 Interrupt Control Register sfr T3 = 0xFE42; // GPT1 Timer 3 Register sfr T3CON = 0xFF42; // GPT1 Timer 3 Control Register sfr T3IC = 0xFF62; // GPT1 Timer 3 Interrupt Control Register sfr T4 = 0xFE44; // GPT1 Timer 4 Register sfr T4CON = 0xFF44; // GPT1 Timer 4 Control Register sfr T4IC = 0xFF64; // GPT1 Timer 4 Interrupt Control Register sfr T5 = 0xFE46; // GPT2 Timer 5 Register sfr T5CON = 0xFF46; // GPT2 Timer 5 Control Register sfr T5IC = 0xFF66; // GPT2 Timer 5 Interrupt Control Register sfr T6 = 0xFE48; // GPT2 Timer 6 Register sfr T6CON = 0xFF48; // GPT2 Timer 6 Control Register sfr T6IC = 0xFF68; // GPT2 Timer 6 Interrupt Control Register sfr T7 = 0xF050; // CAPCOM Timer 7 Register sfr T78CON = 0xFF20; // CAPCOM Timer 7 and 8 Control Register sfr T7IC = 0xF17A; // CAPCOM Timer 7 Interrupt Control Register sfr T7REL = 0xF054; // CAPCOM Timer 7 Reload Register sfr T8 = 0xF052; // CAPCOM Timer 8 Register sfr T8IC = 0xF17C; // CAPCOM Timer 8 Interrupt Control Register sfr T8REL = 0xF056; // CAPCOM Timer 8 Reload Register sfr TFR = 0xFFAC; // Trap Flag Register sfr WDT = 0xFEAE; // Watchdog Timer Register (read only) sfr WDTCON = 0xFFAE; // Watchdog Timer Control Register sfr XADRS5 = 0xF01C; // XBUS Address Select Register (DataFlash) sfr XP0IC = 0xF186; // CAN1 Module Interrupt Control Register sfr XP1IC = 0xF18E; // CAN2 Module Interrupt Control Register sfr XP2IC = 0xF196; // Flash Termination Interrupt Control Register sfr XP3IC = 0xF19E; // RTC/PLL Interrupt Control Register sfr XPERCON = 0xF024; // X-Peripheral Control Register sfr ZEROS = 0xFF1C; // Constant Value 0’s Register (read only) #define SRCP0 (*((unsigned int volatile sdata *) 0xFCE0)) #define DSTP0 (*((unsigned int volatile sdata *) 0xFCE2)) #define SRCP1 (*((unsigned int volatile sdata *) 0xFCE4)) #define DSTP1 (*((unsigned int volatile sdata *) 0xFCE6)) #define SRCP2 (*((unsigned int volatile sdata *) 0xFCE8)) #define DSTP2 (*((unsigned int volatile sdata *) 0xFCEA)) #define SRCP3 (*((unsigned int volatile sdata *) 0xFCEC)) #define DSTP3 (*((unsigned int volatile sdata *) 0xFCEE)) #define SRCP4 (*((unsigned int volatile sdata *) 0xFCF0)) #define DSTP4 (*((unsigned int volatile sdata *) 0xFCF2)) #define SRCP5 (*((unsigned int volatile sdata *) 0xFCF4)) #define DSTP5 (*((unsigned int volatile sdata *) 0xFCF6)) #define SRCP6 (*((unsigned int volatile sdata *) 0xFCF8)) #define DSTP6 (*((unsigned int volatile sdata *) 0xFCFA)) #define SRCP7 (*((unsigned int volatile sdata *) 0xFCFC)) #define DSTP7 (*((unsigned int volatile sdata *) 0xFCFE)) /* SBIT Definitions */ sfr ADCIC = 0xFF98; sfr ADCON = 0xFFA0; sfr ADDAT = 0xFEA0; sfr ADEIC = 0xFF9A; sfr ADDAT2 = 0xF0A0; sbit ADST = ADCON^7; sbit ADBSY = ADCON^8; sbit ADWR = ADCON^9; sbit ADCIN = ADCON^10; sbit ADCRQ = ADCON^11; sbit ADCIE = ADCIC^6; sbit ADCIR = ADCIC^7; sbit ADEIE = ADEIC^6; sbit ADEIR = ADEIC^7; sbit CC0IR = CC0IC^7; sbit CC0IE = CC0IC^6; sbit CC1IR = CC1IC^7; sbit CC1IE = CC1IC^6; sbit CC2IR = CC2IC^7; sbit CC2IE = CC2IC^6; sbit CC3IR = CC3IC^7; sbit CC3IE = CC3IC^6; sbit CC4IR = CC4IC^7; sbit CC4IE = CC4IC^6; sbit CC5IR = CC5IC^7; sbit CC5IE = CC5IC^6; sbit CC6IR = CC6IC^7; sbit CC6IE = CC6IC^6; sbit CC7IR = CC7IC^7; sbit CC7IE = CC7IC^6; sbit CC8IR = CC8IC^7; sbit CC8IE = CC8IC^6; sbit CC9IR = CC9IC^7; sbit CC9IE = CC9IC^6; sbit CC10IR = CC10IC^7; sbit CC10IE = CC10IC^6; sbit CC11IR = CC11IC^7; sbit CC11IE = CC11IC^6; sbit CC12IR = CC12IC^7; sbit CC12IE = CC12IC^6; sbit CC13IR = CC13IC^7; sbit CC13IE = CC13IC^6; sbit CC14IR = CC14IC^7; sbit CC14IE = CC14IC^6; sbit CC15IR = CC15IC^7; sbit CC15IE = CC15IC^6; sbit CC16IR = CC16IC^7; sbit CC16IE = CC16IC^6; sbit CC17IR = CC17IC^7; sbit CC17IE = CC17IC^6; sbit CC18IR = CC18IC^7; sbit CC18IE = CC18IC^6; sbit CC19IR = CC19IC^7; sbit CC19IE = CC19IC^6; sbit CC20IR = CC20IC^7; sbit CC20IE = CC20IC^6; sbit CC21IR = CC21IC^7; sbit CC21IE = CC21IC^6; sbit CC22IR = CC22IC^7; sbit CC22IE = CC22IC^6; sbit CC23IR = CC23IC^7; sbit CC23IE = CC23IC^6; sbit CC24IR = CC24IC^7; sbit CC24IE = CC24IC^6; sbit CC25IR = CC25IC^7; sbit CC25IE = CC25IC^6; sbit CC26IR = CC26IC^7; sbit CC26IE = CC26IC^6; sbit CC27IR = CC27IC^7; sbit CC27IE = CC27IC^6; sbit CC28IR = CC28IC^7; sbit CC28IE = CC28IC^6; sbit CC29IR = CC29IC^7; sbit CC29IE = CC29IC^6; sbit CC30IR = CC30IC^7; sbit CC30IE = CC30IC^6; sbit CC31IR = CC31IC^7; sbit CC31IE = CC31IC^6; sbit ACC0 = CCM0^3; sbit ACC1 = CCM0^7; sbit ACC2 = CCM0^11; sbit ACC3 = CCM0^15; sbit ACC4 = CCM1^3; sbit ACC5 = CCM1^7; sbit ACC6 = CCM1^11; sbit ACC7 = CCM1^15; sbit ACC8 = CCM2^3; sbit ACC9 = CCM2^7; sbit ACC10 = CCM2^11; sbit ACC11 = CCM2^15; sbit ACC12 = CCM3^3; sbit ACC13 = CCM3^7; sbit ACC14 = CCM3^11; sbit ACC15 = CCM3^15; sbit ACC16 = CCM4^3; sbit ACC17 = CCM4^7; sbit ACC18 = CCM4^11; sbit ACC19 = CCM4^15; sbit ACC20 = CCM5^3; sbit ACC21 = CCM5^7; sbit ACC22 = CCM5^11; sbit ACC23 = CCM5^15; sbit ACC24 = CCM6^3; sbit ACC25 = CCM6^7; sbit ACC26 = CCM6^11; sbit ACC27 = CCM6^15; sbit ACC28 = CCM7^3; sbit ACC29 = CCM7^7; sbit ACC30 = CCM7^11; sbit ACC31 = CCM7^15; sbit T0IE = T0IC^6; sbit T0IR = T0IC^7; sbit T0M = T01CON^3; sbit T0R = T01CON^6; sbit T1IE = T1IC^6; sbit T1IR = T1IC^7; sbit T1M = T01CON^11; sbit T1R = T01CON^14; sbit T7IE = T7IC^6; sbit T7IR = T7IC^7; sbit T7M = T78CON^3; sbit T7R = T78CON^6; sbit T8IE = T8IC^6; sbit T8IR = T8IC^7; sbit T8M = T78CON^11; sbit T8R = T78CON^14; sbit WRCFG = SYSCON^7; sbit CLKEN = SYSCON^8; sbit BYTDIS = SYSCON^9; sbit ROMEN = SYSCON^10; sbit SGTEN = SYSCON^11; sbit ROMS1 = SYSCON^12; sbit MDRIU = MDC^4; sbit N = PSW^0; sbit C = PSW^1; sbit V = PSW^2; sbit Z = PSW^3; sbit E = PSW^4; sbit MULIP = PSW^5; sbit USR0 = PSW^6; sbit HLDEN = PSW^10; sbit IEN = PSW^11; sbit RWDC0 = BUSCON0^4; sbit MTTC0 = BUSCON0^5; sbit ALECTL0 = BUSCON0^9; sbit BUSACT0 = BUSCON0^10; sbit RDYEN0 = BUSCON0^12; sbit RWDC1 = BUSCON1^4; sbit MTTC1 = BUSCON1^5; sbit ALECTL1 = BUSCON1^9; sbit BUSACT1 = BUSCON1^10; sbit RDYEN1 = BUSCON1^12; sbit CSREN1 = BUSCON1^14; sbit CSWEN1 = BUSCON1^15; sbit RWDC2 = BUSCON2^4; sbit MTTC2 = BUSCON2^5; sbit ALECTL2 = BUSCON2^9; sbit BUSACT2 = BUSCON2^10; sbit RDYEN2 = BUSCON2^12; sbit CSREN2 = BUSCON2^14; sbit CSWEN2 = BUSCON2^15; sbit RWDC3 = BUSCON3^4; sbit MTTC3 = BUSCON3^5; sbit ALECTL3 = BUSCON3^9; sbit BUSACT3 = BUSCON3^10; sbit RDYEN3 = BUSCON3^12; sbit CSREN3 = BUSCON3^14; sbit CSWEN3 = BUSCON3^15; sbit RWDC4 = BUSCON4^4; sbit MTTC4 = BUSCON4^5; sbit ALECTL4 = BUSCON4^9; sbit BUSACT4 = BUSCON4^10; sbit RDYEN4 = BUSCON4^12; sbit CSREN4 = BUSCON4^14; sbit CSWEN4 = BUSCON4^15; sbit ILLBUS = TFR^0; sbit ILLINA = TFR^1; sbit ILLOPA = TFR^2; sbit PRTFLT = TFR^3; sbit UNDOPC = TFR^7; sbit STKUF = TFR^13; sbit STKOF = TFR^14; sbit NMI = TFR^15; sfr ISNC = 0xF1DE; sbit RTCIR = ISNC^0; sbit RTCIE = ISNC^1; sbit PLLIR = ISNC^2; sbit PLLIE = ISNC^3; sbit S0STP = S0CON^3; sbit S0REN = S0CON^4; sbit S0PEN = S0CON^5; sbit S0FEN = S0CON^6; sbit S0OEN = S0CON^7; sbit S0PE = S0CON^8; sbit S0FE = S0CON^9; sbit S0OE = S0CON^10; sbit S0ODD = S0CON^12; sbit S0BRS = S0CON^13; sbit S0LB = S0CON^14; sbit S0R = S0CON^15; sbit S0TIE = S0TIC^6; sbit S0TIR = S0TIC^7; sbit S0TBIE = S0TBIC^6; sbit S0TBIR = S0TBIC^7; sbit S0RIE = S0RIC^6; sbit S0RIR = S0RIC^7; sbit S0EIE = S0EIC^6; sbit S0EIR = S0EIC^7; sbit SSCHB = SSCCON^4; sbit SSCPH = SSCCON^5; sbit SSCPO = SSCCON^6; sbit SSCTE = SSCCON^8; sbit SSCTEN = SSCCON^8; sbit SSCRE = SSCCON^9; sbit SSCREN = SSCCON^9; sbit SSCPE = SSCCON^10; sbit SSCPEN = SSCCON^10; sbit SSCBE = SSCCON^11; sbit SSCBEN = SSCCON^11; sbit SSCBSY = SSCCON^12; sbit SSCMS = SSCCON^14; sbit SSCEN = SSCCON^15; sbit SSCTIR = SSCTIC^7; sbit SSCTIE = SSCTIC^6; sbit SSCRIR = SSCRIC^7; sbit SSCRIE = SSCRIC^6; sbit SSCEIR = SSCEIC^7; sbit SSCEIE = SSCEIC^6; sbit CRIE = CRIC^6; sbit CRIR = CRIC^7; sbit T2R = T2CON^6; sbit T2UD = T2CON^7; sbit T2UDE = T2CON^8; sbit T2IE = T2IC^6; sbit T2IR = T2IC^7; sbit T3R = T3CON^6; sbit T3UD = T3CON^7; sbit T3UDE = T3CON^8; sbit T3OE = T3CON^9; sbit T3OTL = T3CON^10; sbit T3IE = T3IC^6; sbit T3IR = T3IC^7; sbit T4R = T4CON^6; sbit T4UD = T4CON^7; sbit T4UDE = T4CON^8; sbit T4IE = T4IC^6; sbit T4IR = T4IC^7; sbit T5R = T5CON^6; sbit T5UD = T5CON^7; sbit T5UDE = T5CON^8; sbit T5CLR = T5CON^14; sbit T5SC = T5CON^15; sbit T5IE = T5IC^6; sbit T5IR = T5IC^7; sbit T6R = T6CON^6; sbit T6UD = T6CON^7; sbit T6UDE = T6CON^8; sbit T6OE = T6CON^9; sbit T6OTL = T6CON^10; sbit T6SR = T6CON^15; sbit T6IE = T6IC^6; sbit T6IR = T6IC^7; sbit T0IN = P3^0; sbit T2IN = P3^7; sbit T3IN = P3^6; sbit T4IN = P3^5; sbit T5IN = P5^13; sbit T6IN = P5^12; sbit T2EUD = P5^15; sbit T3EUD = P3^4; sbit T4EUD = P5^14; sbit T5EUD = P5^11; sbit T6EUD = P5^10; sbit T3OUT = P3^3; sbit CAPIN = P3^2; sbit T6OUT = P3^1; sbit WDTIN = WDTCON^0; sbit WDTR = WDTCON^1; sbit PTR0 = PWMCON0^0; sbit PTR1 = PWMCON0^1; sbit PTR2 = PWMCON0^2; sbit PTR3 = PWMCON0^3; sbit PTI0 = PWMCON0^4; sbit PTI1 = PWMCON0^5; sbit PTI2 = PWMCON0^6; sbit PTI3 = PWMCON0^7; sbit PIE0 = PWMCON0^8; sbit PIE1 = PWMCON0^9; sbit PIE2 = PWMCON0^10; sbit PIE3 = PWMCON0^11; sbit PIR0 = PWMCON0^12; sbit PIR1 = PWMCON0^13; sbit PIR2 = PWMCON0^14; sbit PIR3 = PWMCON0^15; sbit PEN0 = PWMCON1^0; sbit PEN1 = PWMCON1^1; sbit PEN2 = PWMCON1^2; sbit PEN3 = PWMCON1^3; sbit PM0 = PWMCON1^4; sbit PM1 = PWMCON1^5; sbit PM2 = PWMCON1^6; sbit PM3 = PWMCON1^7; sbit PB01 = PWMCON1^12; sbit PS2 = PWMCON1^14; sbit PS3 = PWMCON1^15; sbit PWMIR = PWMIC^7; sbit PWMIE = PWMIC^6; sbit RCS = SYSCON2^6; sbit SCS = SYSCON2^7; sbit CLKLOCK = SYSCON2^15; sbit ADCDIS = SYSCON3^0; sbit ASC0DIS = SYSCON3^1; sbit SSCDIS = SYSCON3^2; sbit GPT1DIS = SYSCON3^3; sbit GPT2DIS = SYSCON3^4; sbit FMDIS = SYSCON3^5; sbit CC1DIS = SYSCON3^6; sbit CC2DIS = SYSCON3^7; sbit PWMDIS = SYSCON3^9; sbit ASC1DIS = SYSCON3^10; sbit I2CDIS = SYSCON3^11; sbit CAN1DIS = SYSCON3^13; sbit CAN2DIS = SYSCON3^14; sbit PCDDIS = SYSCON3^15; sbit XP0IR = XP0IC^7; sbit XP0IE = XP0IC^6; sbit XP1IR = XP1IC^7; sbit XP1IE = XP1IC^6; sbit XP2IR = XP2IC^7; sbit XP2IE = XP2IC^6; sbit XP3IR = XP3IC^7; sbit XP3IE = XP3IC^6; #endif