/******************** (C) COPYRIGHT 2012 Triad Semiconductor, Inc.**************
* File Name : TSX1001.h
* Version : V1.00
* Date : 23 April 2012
* Description : CMSIS Cortex-M0 Device Header File for device TSX1001
*
*******************************************************************************/
#ifndef TSX1001_H
#define TSX1001_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/* --------------------- CM0IKMCU Specific Interrupt Numbers -------------------- */
GPIO0_IRQn = 0, /*!< GPIO Interrupt */
/*!< maximum of 32 Interrupts are possible */
GPIO1_IRQn = 1, /*!< GPIO Interrupt */
ADC_IRQn = 2,
DAC_IRQn = 3,
PWM_IRQn = 4,
TMR_IRQn = 5,
UART_IRQn = 6,
SPI_IRQn = 7,
INT8n_IRQn = 8,
INT9n_IRQn = 9,
INT8_IRQn = 10,
INT9_IRQn = 11,
CM0IKMCU_IRQ12_IRQn = 12,
CM0IKMCU_IRQ13_IRQn = 13,
CM0IKMCU_IRQ14_IRQn = 14,
CM0IKMCU_IRQ15_IRQn = 15,
CM0IKMCU_IRQ16_IRQn = 16,
CM0IKMCU_IRQ17_IRQn = 17,
CM0IKMCU_IRQ18_IRQn = 18,
CM0IKMCU_IRQ19_IRQn = 19,
CM0IKMCU_IRQ20_IRQn = 20,
CM0IKMCU_IRQ21_IRQn = 21,
CM0IKMCU_IRQ22_IRQn = 22,
CM0IKMCU_IRQ23_IRQn = 23,
CM0IKMCU_IRQ24_IRQn = 24,
CM0IKMCU_IRQ25_IRQn = 25,
CM0IKMCU_IRQ26_IRQn = 26,
CM0IKMCU_IRQ27_IRQn = 27,
CM0IKMCU_IRQ28_IRQn = 28,
CM0IKMCU_IRQ29_IRQn = 29,
CM0IKMCU_IRQ30_IRQn = 30,
CM0IKMCU_IRQ31_IRQn = 31
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* -------- Configuration of the Cortex-M0 Processor and Core Peripherals ------- */
#define __CM0_REV 0x0000 /*!< Core revision r0p0 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include <core_cm0.h> /* Processor and core peripherals */
#include "system_TSX1001.h" /* System Header */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined(__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/*--------------------- General Purpose Input and Ouptut ---------------------*/
typedef union
{
__IO uint32_t WORD;
__IO uint16_t HALFWORD[2];
__IO uint8_t BYTE[4];
} AHB_Data_TypeDef;
typedef struct
{
AHB_Data_TypeDef DATA [256];
AHB_Data_TypeDef DIR;
uint32_t RESERVED0[3];
AHB_Data_TypeDef IE_RE; // Rising edge detect IRQ enables
uint32_t RESERVED1[3];
AHB_Data_TypeDef IE_FE; // Falling edge detect IRQ enables
} GPIO_TypeDef;
/*--------------------- System control (EEPROM, clocks, RAM overlay, etc.) ---*/
#define EE_NOWRSTALL 0x00800000UL
#define EE_SPEC 0x00400000UL
#define EE_WREN 0x00200000UL
#define EE_WORD 0x00100000UL
#define EE_WAIT_0 0x00000000UL
#define EE_WAIT_1 0x00010000UL
#define EE_WAIT_2 0x00020000UL
#define EE_WAIT_3 0x00030000UL
#define EE_APB_RATE_1 0x00000000UL
#define EE_APB_RATE_2 0x00000100UL
#define EE_APB_RATE_3 0x00000200UL
#define EE_APB_RATE_4 0x00000300UL
#define EE_CLK_RATE_16 0x00000000UL
#define EE_CLK_RATE_8 0x00000001UL
#define EE_CLK_RATE_4 0x00000002UL
#define EE_CLK_RATE_2 0x00000003UL
#define EE_CLK_RATE_1 0x00000007UL
#define PLL_CP_SEL_5uA (( uint32_t) 0x00000002 )
#define PLL_CP_SEL_10uA (( uint32_t) 0x00000000 )
#define PLL_CP_SEL_15uA (( uint32_t) 0x00000006 )
#define PLL_CP_SEL_20uA (( uint32_t) 0x00000004 )
#define PLL_CT_SEL_40MHz (( uint32_t) 0x00000008 )
#define PLL_CT_SEL_45MHz (( uint32_t) 0x00000000 )
#define PLL_CT_SEL_50MHz (( uint32_t) 0x00000018 )
#define PLL_CT_SEL_55MHz (( uint32_t) 0x00000010 )
#define PLL_CT_MASK (( uint32_t) 0x00000018 )
#define PLL_CP_MASK (( uint32_t) 0x00000006 )
typedef struct
{
__IO uint32_t DATA[3];
} SYSCTRL_TypeDef;
typedef struct
{
__IO uint32_t DATA[8192];
} EEPROM_TypeDef;
typedef struct
{
volatile uint32_t DATA[32];
} EEPROM_Page_TypeDef;
/*--------------------- Watchdog control -------------------------------------*/
typedef struct
{
__IO uint32_t WDOGValue;
__IO uint32_t WDOGControl;
__IO uint32_t WDOGKick;
__IO uint32_t WDOGStatus;
} WDOG_TypeDef;
/*--------------------- Dac control ------------------------------------------*/
typedef struct
{
AHB_Data_TypeDef CFG0[256];
AHB_Data_TypeDef CFG1;
uint32_t RESERVED0[8];
} DACINTF_TypeDef;
typedef struct
{
__IO uint32_t DATA[256];
} DACMEM_TypeDef;
/*--------------------- Adc control ------------------------------------------*/
#define ADC_EN ((uint32_t) 0x00000001)
#define ADC_DECIMATE_64 ((uint32_t) 0x00000000)
#define ADC_DECIMATE_128 ((uint32_t) 0x00000002)
#define ADC_DECIMATE_256 ((uint32_t) 0x00000004)
#define ADC_DECIMATE_512 ((uint32_t) 0x00000006)
#define ADC_DECIMATE_1024 ((uint32_t) 0x00000008)
#define ADC_DECIMATE_mask ((uint32_t) 0x0000000E)
#define ADC_EDGE_SEL_pos ((uint32_t) 0x00000010)
#define ADC_EDGE_SEL_neg ((uint32_t) 0x00000000)
#define ADC_EDGE_SEL_mask ((uint32_t) 0x00000010)
#define ADC_DATA_SEL_fall ((uint32_t) 0x00000020)
#define ADC_DATA_SEL_rise ((uint32_t) 0x00000000)
#define ADC_DATA_SEL_mask ((uint32_t) 0x00000020)
#define ADC_CLK_SEL_fall ((uint32_t) 0x00000040)
#define ADC_CLK_SEL_rise ((uint32_t) 0x00000000)
#define ADC_CLK_SEL_mask ((uint32_t) 0x00000040)
#define ADC_CLK_XTALx0p25 ((uint32_t) 0x00000000)
#define ADC_CLK_XTALx1 ((uint32_t) 0x00000080)
#define ADC_CLK_XTALx3 ((uint32_t) 0x00000100)
#define ADC_CLK_bypass ((uint32_t) 0x00000180)
#define ADC_CLK_mask ((uint32_t) 0x00000180)
#define ADC_REF_VBG ((uint32_t) 0x00000000)
#define ADC_REF_VDDx0p5 ((uint32_t) 0x00000200)
#define ADC_REF_mask ((uint32_t) 0x00000200)
#define ADC_MOD_EN ((uint32_t) 0x00000400)
#define ADC_EOC ((uint32_t) 0x00008000)
typedef struct
{
AHB_Data_TypeDef CFG0 [256];
AHB_Data_TypeDef CFG1;
uint32_t RESERVED0[4];
uint32_t RESERVED1[4];
} ADC_TypeDef;
/*--------------------- Pwm control ------------------------------------------*/
typedef struct
{
AHB_Data_TypeDef CFG0[256];
AHB_Data_TypeDef CFG1;
uint32_t RESERVED0[8];
} PWM_TypeDef;
/*--------------------- Tmr control ------------------------------------------*/
typedef struct
{
AHB_Data_TypeDef CFG0[256];
AHB_Data_TypeDef CFG1;
uint32_t RESERVED0[8];
} TMR_TypeDef;
/*--------------------- Spi control ------------------------------------------*/
#define SPI_TXFULL_MASK (( uint32_t)0x00000010)
#define SPI_RXEMPTY_MASK (( uint32_t)0x00000020)
typedef struct
{
__IO uint32_t TXDATA;
__IO uint32_t RXDATA;
__IO uint32_t CLKDIV;
__IO uint32_t CONTROL;
__IO uint32_t STATUS;
__IO uint32_t SSELECT;
__IO uint32_t SSELPOL;
__IO uint32_t IRQENABLE;
__IO uint32_t IRQSTATUS;
__IO uint32_t IRQCLEAR;
__IO uint32_t TXFIFOCTRL;
__IO uint32_t RXFIFOCTRL;
__IO uint32_t TXFIFOLVL;
__IO uint32_t RXFIFOLVL;
} SPI_TypeDef;
typedef struct
{
uint32_t ByteCount;
uint32_t RxData;
} SPI_RxDataStruct;
/*--------------------- Uart control -----------------------------------------*/
// values for UART->IER
#define IER_STAT_INT (( uint32_t)0x00000008)
#define IER_RXLN_INT (( uint32_t)0x00000004)
#define IER_TXHLD_INT (( uint32_t)0x00000002)
#define IER_RXDAT_INT (( uint32_t)0x00000001)
// values for UART->IIR writes to UART->FCR
#define UART_FIFO_EN (( uint32_t)0x00000001)
#define UART_RX_FIFO_RST (( uint32_t)0x00000002)
#define UART_TX_FIFO_RST (( uint32_t)0x00000004)
#define UART_RX_TRIG_1 (( uint32_t)0x00000000)
#define UART_RX_TRIG_4 (( uint32_t)0x00000040)
#define UART_RX_TRIG_8 (( uint32_t)0x00000080)
#define UART_RX_TRIG_14 (( uint32_t)0x000000C0)
// values for UART->LCR
#define UART_DLAB (( uint32_t)0x00000080)
#define UART_SET_BRK (( uint32_t)0x00000040)
#define UART_STK_PAR (( uint32_t)0x00000020)
#define UART_EVEN_PAR (( uint32_t)0x00000010)
#define UART_PAR_EN (( uint32_t)0x00000008)
#define UART_2_STOP_BITS (( uint32_t)0x00000004)
#define UART_1_STOP_BITS (( uint32_t)0x00000000)
#define UART_5_BITS (( uint32_t)0x00000000)
#define UART_6_BITS (( uint32_t)0x00000001)
#define UART_7_BITS (( uint32_t)0x00000002)
#define UART_8_BITS (( uint32_t)0x00000003)
// values for UART->MCR
#define UART_LOOPBAK (( uint32_t)0x00000010)
#define UART_RTS (( uint32_t)0x00000002)
typedef struct
{
union {
__I uint32_t RBR; /*!< Offset: 0x000 (R/ ) Receiver Buffer Register */
__O uint32_t THR; /*!< Offset: 0x000 ( /W) Transmit Holding Register */
__IO uint32_t DLL; /*!< Offset: 0x000 (R/W) Divisor Latch LSB */
};
union {
__IO uint32_t DLM; /*!< Offset: 0x004 (R/W) Divisor Latch MSB */
__IO uint32_t IER; /*!< Offset: 0x004 (R/W) Interrupt Enable Register */
};
union {
__I uint32_t IIR; /*!< Offset: 0x008 (R/ ) Interrupt ID Register */
__O uint32_t FCR; /*!< Offset: 0x008 ( /W) FIFO Control Register */
};
__IO uint32_t LCR; /*!< Offset: 0x00C (R/W) Line Control Register */
__IO uint32_t MCR; /*!< Offset: 0x010 (R/W) Modem control Register */
__I uint32_t LSR; /*!< Offset: 0x014 (R/ ) Line Status Register */
__I uint32_t MSR; /*!< Offset: 0x018 (R/ ) Modem status Register */
__IO uint32_t SCR; /*!< Offset: 0x01C (R/W) Scratch Pad Register */
} UART_TypeDef;
/* -------------------- End of section using anonymous unions ------------------- */
#if defined(__CC_ARM)
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ Peripheral memory map ================ */
/* ================================================================================ */
/* Peripheral and SRAM base address */
#define SRAM_BASE (( uint32_t)0x20000000)
#define PERIPH_BASE (( uint32_t)0x40000000)
/* GPIO memory map */
#define GPIO_BASE (PERIPH_BASE + 0x10000000UL)
#define GPIO0_BASE (GPIO_BASE)
#define GPIO1_BASE (GPIO_BASE + 0x00000800UL)
#define GPIO2_BASE (GPIO_BASE + 0x00001000UL)
/* SYSCTRL memory map */
#define SYSCTRL_BASE (( uint32_t)0xB0000000UL)
/* EEPROM memory map */
#define EEPROM_BASE (( uint32_t)0xC0000000UL)
/* Watchdog */
#define WDOG_BASE (( uint32_t)0xB0000010UL)
/* DAC */
//===============================================
// DAC Buffer Memory Address Map
//-----------------------------------------------
// 0x40000000-0x400003FF (Read / Write)
//===============================================
// DAC Register Map
//-----------------------------------------------
// 0x40000800-0x40000BFF (Write)
// [0] - DAC Enable
// [1] - Write Enable
// [2] - Circular Buffer Enable
// [11:3] - IRQ Assertion Threshold
// [12] - RESERVED
// [13] - DAC Memory Buffer Port A Enable
// [14] - DAC Memory Buffer Port B Enable
// [31:15] - RESERVED
//-----------------------------------------------
// 0x40000800-0x40000BFF (Read)
// [0] - DAC Enable
// [1] - Write Enable
// [2] - Circular Buffer Enable
// [11:3] - IRQ Assertion Threshold
// [12] - RESERVED
// [13] - DAC Memory Buffer Port A Enable
// [14] - DAC Memory Buffer Port B Enable
// [18:15] - RESERVED
// [19] - DAC Threshold Indicator
// [31:20] - Current Sample Value
//-----------------------------------------------
// 0x40000C00 (Write / Read)
// [23:0] - Sample Rate Divisor
// [31:24] - Read Address Upper Limit
//===============================================
#define DACMEM_BASE (( uint32_t)0x40000000)
#define DAC_BASE (( uint32_t)0x40000800)
/* ADC */
//===============================================
// ADC register map
//-----------------------------------------------
// 0x40001000-0x400013FF (Write)
// [0] - ADC Enable
// [3:1] - Decimation Rate
// 0 - 64 Down-sample
// 1 - 128 Down-sample
// 2 - 256 Down-sample
// 3 - 512 Down-sample
// 4 - 1024 Down-sample
// [4] - ADC DSM Clock Edge Detect Select
// [5] - ADC Reference Voltage Select
// [6] - ADC Modulator Enable
// [7] - ADC Clock Invert Enable
// [9:8] - ADC Clock Frequency Select
// [31:10] - RESERVED
//-----------------------------------------------
// 0x40001000-0x400013FF (Read)
// [0] - ADC Enable
// [3:1] - Decimation Rate
// [4] - ADC DSM Clock Edge Detect Select
// [5] - ADC Reference Voltage Select
// [6] - ADC Modulator Enable
// [7] - ADC Clock Invert Enable
// [9:8] - ADC Clock Frequency Select
// [14:10] - RESERVED
// [15] - ADC Conversion Done Indicator
// [31:16] - ADC Value
//-----------------------------------------------
// 0x40001400 (Write)
// Write to address to clear IRQ / Done indicator
//===============================================
#define ADC_BASE (( uint32_t)0x40001000)
/* PWM */
//===============================================
// PWM Register Map
//-----------------------------------------------
// 0x00000000-0x000003FF (Write)
// [23:0] - Writes duty cycle value
// [29:24] - Writes GPIOOUT0 bus [29:24]
// [30] -Hold indicator, active high
// [31] - Enable indicator, active high
//-----------------------------------------------
// 0x00000000-0x000003FF (Read)
// [23:0] - Reads current PWM counter value
// [29:24] - Reads GPIOIN bus [29:24]
// [30] -Hold indicator, active high
// [31] -Enable indicator, active high
//-----------------------------------------------
// 0x00000400 (Read / Write)
// [23:0] - Configures the PWM divisor value.
// [29:24] - GPIOOUT1 bus signals [31:24]
// [30] - PWM output polarity when PWMEN is deasserted
// 1 - PWMOUT = 1 when PWM disabled
// 0 - PWMOUT = 0 when PWM disabled
// [31] - PWM enable polarity select
// 1 - PWMEN enables when PWMEN = 1
// 0 - PWMEN enables when PWMEN = 0
//-----------------------------------------------
// 0x00000410-0x00000420 Reserved
//===============================================
#define PWM_BASE (( uint32_t)0x40001800)
/* Timer */
//===============================================
// TMR Register Map
//-----------------------------------------------
// 0x00000000-0x000003FF (Write)
// [30:0] - Writes counter IRQn assertion value
// [31] - Enable
//-----------------------------------------------
// 0x00000000-0x000003FF (Read)
// [30:0] - Reads current counter value
// [31] - Enable
//-----------------------------------------------
// 0x00000400 (Read / Write)
// [30:0] - Configures the TMR divisor value.
// [31] - Mode select
// 0 - External clock source mode
// 1 - External halt control mode
//-----------------------------------------------
// 0x00000410-0x00000420 Reserved
//===============================================
#define TMR_BASE (( uint32_t)0x40002000)
/* SPI */
#define SPI_BASE (( uint32_t)0xA0000000)
/* UART */
#define UART_BASE (( uint32_t)0xA0000040)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
#define SYSCTRL ((SYSCTRL_TypeDef *) SYSCTRL_BASE)
#define EEPROM (( EEPROM_TypeDef *) EEPROM_BASE)
#define WDOG (( WDOG_TypeDef *) WDOG_BASE)
#define DACMEM ((DACMEM_TypeDef *) DACMEM_BASE)
#define DAC ((DACINTF_TypeDef *) DAC_BASE)
#define ADC (( ADC_TypeDef *) ADC_BASE)
#define PWM (( PWM_TypeDef *) PWM_BASE)
#define TMR (( TMR_TypeDef *) TMR_BASE)
#define SPI (( SPI_TypeDef *) SPI_BASE)
#define UART (( UART_TypeDef *) UART_BASE)
#ifdef __cplusplus
}
#endif
#endif /* TSX1001_H */