/**************************************************************************//**
* @file TMPM321.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for the
* Toshiba 'TMPM321F10' Device Series
* @version V1.01
* @date 15. March 2010
*
* @note
* Copyright (C) 2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __TMPM321_H__
#define __TMPM321_H__
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup TMPM321_Definitions TMPM321 Definitions
This file defines all structures and symbols for TMPM321:
- registers and bitfields
- peripheral base address
- peripheral ID
- PIO definitions
@{
*/
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup TMPM321_CMSIS TMPM321 CMSIS Definitions
Configuration of the Cortex-M3 Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** TMPM321 Specific Interrupt Numbers *******************************************************/
INT0_Handler = 0, /*!< Interrupt Pin INT0 */
INT1_Handler = 1, /*!< Interrupt Pin INT1 */
INT2_Handler = 2, /*!< Interrupt Pin INT2 */
INT3_Handler = 3, /*!< Interrupt Pin INT3 */
INT4_Handler = 4, /*!< Interrupt Pin INT4 */
INT5_Handler = 5, /*!< Interrupt Pin INT5 */
INT6_Handler = 6, /*!< Interrupt Pin INT6 */
INT7_Handler = 7, /*!< Interrupt Pin INT7 */
/*!< Reserved 8 ~ 15 */
INTRX0_Handler = 16, /*!< Serial Reception (Ch 0) */
INTTX0_Handler = 17, /*!< Serial Transmit (Ch 0) */
INTRX1_Handler = 18, /*!< Serial Reception (Ch 1) */
INTTX1_Handler = 19, /*!< Serial Transmit (Ch 1) */
INTRX2_Handler = 20, /*!< Serial Reception (Ch 2) */
INTTX2_Handler = 21, /*!< Serial Transmit (Ch 2) */
INTRX3_Handler = 22, /*!< Serial Reception (Ch 3) */
INTTX3_Handler = 23, /*!< Serial Transmit (Ch 3) */
INTRX4_Handler = 24, /*!< Serial Reception (Ch 4) */
INTTX4_Handler = 25, /*!< Serial Transmit (Ch 4) */
INTSBI0_Handler = 26, /*!< Serial Bus Interface 0 */
INTSBI1_Handler = 27, /*!< Serial Bus Interface 1 */
INTCECRX_Handler = 28, /*!< CEC Reception */
INTCECTX_Handler = 29, /*!< CEC Transmission */
INTRMCRX0_Handler = 30, /*!< Remote Control Reception 0 */
/*!< Reserved 31 */
INTRTC_Handler = 32, /*!< Real Time Clock */
INTKWUP_Handler = 33, /*!< Key on wake up */
INTSBI2_Handler = 34, /*!< Serial Bus Interface 2 */
INTSBI3_Handler = 35, /*!< Serial Bus Interface 3 */
/*!< Reserved 36 */
INTADHP_Handler = 37, /*!< AD Conversion Complete High. Priority */
INTADM0_Handler = 38, /*!< AD Conversion Monitor 0 */
INTADM1_Handler = 39, /*!< AD Conversion Monitor 1 */
INTTB0_Handler = 40, /*!< TMRB Match Detection 0 */
INTTB1_Handler = 41, /*!< TMRB Match Detection 1 */
INTTB2_Handler = 42, /*!< TMRB Match Detection 2 */
INTTB3_Handler = 43, /*!< TMRB Match Detection 3 */
INTTB4_Handler = 44, /*!< TMRB Match Detection 4 */
INTTB5_Handler = 45, /*!< TMRB Match Detection 5 */
INTTB6_Handler = 46, /*!< TMRB Match Detection 6 */
INTTB7_Handler = 47, /*!< TMRB Match Detection 7 */
/*!< Reserved 48 ~ 55 */
INTUSB_Handler = 56, /*!< USB Interrupt */
/*!< Reserved 57 */
INTAD_Handler = 58, /*!< AD Conversion Complete */
INTSSP0_Handler = 59, /*!< Synchronous serial port 0 */
/*!< Reserved 60 ~ 73 */
INTCAP10_Handler = 74, /*!< TMRB Input Capture 10 */
INTCAP11_Handler = 75, /*!< TMRB Input Capture 11 */
INTCAP20_Handler = 76, /*!< TMRB Input Capture 20 */
INTCAP21_Handler = 77, /*!< TMRB Input Capture 21 */
/*!< Reserved 78, 79 */
INTCAP50_Handler = 80, /*!< TMRB Input Capture 50 */
INTCAP51_Handler = 81, /*!< TMRB Input Capture 51 */
INTCAP60_Handler = 82, /*!< TMRB Input Capture 60 */
INTCAP61_Handler = 83, /*!< TMRB Input Capture 61 */
INTCAP70_Handler = 84, /*!< TMRB Input Capture 70 */
INTCAP71_Handler = 85, /*!< TMRB Input Capture 71 */
/*!< Reserved 86 ~ 97 */
INTDMACERR_Handler = 98, /*!< DMAC transfer Error */
INTDMACTC0_Handler = 99, /*!< DMAC transfer Complete */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 8 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/*@}*/ /* end of group TMPM321_CMSIS */
#include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
#include "system_TMPM321.h" /* TMPM321 System */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup TMPM321_Peripherals TMPM321 Peripherals
TMPM321 Device Specific Peripheral registers structures
@{
*/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- Single Master DMAC Channel(DMAC CH) ---------------------*/
/** @addtogroup TMPM321_DMAC_CH TMPM321 Single Master DMAC Channel(DMAC CH)
@{
*/
typedef struct
{
__IO uint32_t SrcAddr; /*!< Offset: 0x0100 + (Chn * 0x20) Source Address Register */
__IO uint32_t DestAddr; /*!< Offset: 0x0104 + (Chn * 0x20) Destination Address Register */
__IO uint32_t LLI; /*!< Offset: 0x0108 + (Chn * 0x20) Linked List Item Register */
uint32_t Control; /*!< Offset: 0x010C + (Chn * 0x20) Control Register */
__IO uint32_t Configuration; /*!< Offset: 0x0110 + (Chn * 0x20) Configuration Register */
uint32_t RESERVED[3];
} TSB_DMAC_CHN_TypeDef;
/*@}*/ /* end of group TMPM321_DMAC_CH */
/*------------- Single Master DMAC (DMAC) ---------------------*/
/** @addtogroup TMPM321_DMAC TMPM321 Single Master DMAC (DMAC)
@{
*/
typedef struct
{
__IO uint32_t IntStaus; /*!< Offset: 0x0000 Interrupt Status */
__IO uint32_t IntTCStatus; /*!< Offset: 0x0004 Interrupt Terminal Count Status */
__IO uint32_t IntTCClear; /*!< Offset: 0x0008 Interrupt Terminal Count Clear */
__IO uint32_t IntErrorStatus; /*!< Offset: 0x000C Interrupt Error Status */
__IO uint32_t IntErrClr; /*!< Offset: 0x0010 Interrupt Error Clear */
__IO uint32_t RawIntTCStatus; /*!< Offset: 0x0014 Raw Interrupt Terminal Count Status Register */
__IO uint32_t RawIntErrorStatus; /*!< Offset: 0x0018 Raw Error Interrupt Status Register */
__IO uint32_t EnbldChns; /*!< Offset: 0x001C Enabled Channe Register */
__IO uint32_t SoftBReq; /*!< Offset: 0x0020 Software Burst Request Register */
__IO uint32_t SoftSReq; /*!< Offset: 0x0024 Software Single Request Register */
uint32_t RESERVED0[2];
__IO uint32_t Configuration; /*!< Offset: 0x0030 Configuration Register */
uint32_t RESERVED1[51];
TSB_DMAC_CHN_TypeDef CHN[2]; /*!< Offset: 0x0100 Channel registers */
} TSB_DMAC_TypeDef;
/*@}*/ /* end of group TMPM321_DMAC */
/*------------- Synchronous Serial Port(SSP) ---------------------*/
/** @addtogroup TMPM321_SSP TMPM321 Synchronous Serial Port(SSP)
@{
*/
typedef struct
{
__IO uint32_t CR0; /*!< Offset: 0x0000 Control Register 0 */
__IO uint32_t CR1; /*!< Offset: 0x0004 Control Register 1 */
__IO uint32_t DR; /*!< Offset: 0x0008 Data Register */
__IO uint32_t SR; /*!< Offset: 0x000C Status Register */
__IO uint32_t CPSR; /*!< Offset: 0x0010 Clock Prescaler Register */
__IO uint32_t IMSC; /*!< Offset: 0x0014 Interrupt Mask Set and Clear Register */
__IO uint32_t RIS; /*!< Offset: 0x0018 Raw Interrupt Status Register */
__IO uint32_t MIS; /*!< Offset: 0x001C Masked Interrupt Status Register */
__IO uint32_t ICR; /*!< Offset: 0x0020 Interrupt Clear Register */
__IO uint32_t DMACR; /*!< Offset: 0x0024 DMA Control Register */
uint32_t RESERVED0[63];
} TSB_SSP_TypeDef;
/*@}*/ /* end of group TMPM321_SSP */
/*------------- General Purpose Input/Output Port (PORT) ---------------------*/
/** @addtogroup TMPM321_PORT TMPM321 General Purpose Input/Output Port (PORT)
@{
*/
typedef struct
{
__IO uint32_t DATA; /*!< Offset: 0x0000 Port Data Register */
__IO uint32_t CR; /*!< Offset: 0x0004 Port Control Register */
__IO uint32_t FR1; /*!< Offset: 0x0008 Port Function Register 1 */
__IO uint32_t FR2; /*!< Offset: 0x000C Port Function Register 2 */
__IO uint32_t FR3; /*!< Offset: 0x0010 Port Function Register 3 */
uint32_t RESERVED0[5];
__IO uint32_t OD; /*!< Offset: 0x0028 Port Open drain control Register */
__IO uint32_t PUP; /*!< Offset: 0x002C Port Pull up control Register */
uint32_t RESERVED1[2];
__IO uint32_t IE; /*!< Offset: 0x0038 Port Input control enable Register */
} TSB_PORT_TypeDef;
/*@}*/ /* end of group TMPM321_PORT */
/*------------- 16-bit Timer/Event Counter (TMRB) ----------------------------*/
/** @addtogroup TMPM321_TMRB TMPM321 16-bit Timer/Event Counter (TMRB)
@{
*/
typedef struct
{
__IO uint32_t EN; /*!< Offset: 0x0000 Timer Enable Register */
__IO uint32_t RUN; /*!< Offset: 0x0004 Timer RUN Register */
__IO uint32_t CR; /*!< Offset: 0x0008 Timer Control Register */
__IO uint32_t MOD; /*!< Offset: 0x000C Timer Mode Register */
__IO uint32_t FFCR; /*!< Offset: 0x0010 Timer Flip-Flop Control Register */
__IO uint32_t ST; /*!< Offset: 0x0014 Timer Status Register */
__IO uint32_t IM; /*!< Offset: 0x0018 Interrupt Mask Register */
__IO uint32_t UC; /*!< Offset: 0x001C Timer Up Counter Register */
__IO uint32_t RG0; /*!< Offset: 0x0020 Timer Register 0 */
__IO uint32_t RG1; /*!< Offset: 0x0024 Timer Register 1 */
__IO uint32_t CP0; /*!< Offset: 0x0028 Capture register 0 */
__IO uint32_t CP1; /*!< Offset: 0x002C Capture register 1 */
} TSB_TMRB_TypeDef;
/*@}*/ /* end of group TMPM321_TMRB */
/*------------- Serial Bus Interface (SBI/SIO) --------------------------------*/
/** @addtogroup TMPM321_SBI_SIO TMPM321 Serial Bus Interface (SBI/SIO)
@{
*/
typedef struct
{
__IO uint32_t CR0; /*!< Offset: 0x0000 SBI Control Register 0 */
__IO uint32_t CR1; /*!< Offset: 0x0004 SBI Control Register 1 */
__IO uint32_t DBR; /*!< Offset: 0x0008 SBI Data Buffer Register */
__IO uint32_t I2CAR; /*!< Offset: 0x000C SBI I2C bus Address Register */
union {
__O uint32_t CR2; /*!< Offset: 0x0010 SBI Control Register 2 */
__I uint32_t SR; /*!< Offset: 0x0010 SBI Status Register */
};
__IO uint32_t BR0; /*!< Offset: 0x0014 SBI Baud Rate Register 0 */
} TSB_SBI_TypeDef;
/*@}*/ /* end of group TMPM321_SBI_SIO */
/*------------- General-purpose Serial Interface (SIO/UART) ------------------*/
/** @addtogroup TMPM321_SIO_UART TMPM321 General-purpose Serial Interface (SIO/UART)
@{
*/
typedef struct
{
__IO uint32_t EN; /*!< Offset: 0x0000 SIO Enable Register */
__IO uint32_t BUF; /*!< Offset: 0x0004 SIO Transmit/ Receive Buffer Register */
__IO uint32_t CR; /*!< Offset: 0x0008 SIO Control Register */
__IO uint32_t MOD0; /*!< Offset: 0x000C SIO Mode Control Register 0 */
__IO uint32_t BRCR; /*!< Offset: 0x0010 SIO Baud Rate Generator Control */
__IO uint32_t BRADD; /*!< Offset: 0x0014 SIO Baud rate Generator Control 2 */
__IO uint32_t MOD1; /*!< Offset: 0x0018 SIO Mode Control Register 1 */
__IO uint32_t MOD2; /*!< Offset: 0x001C SIO Mode Control Register 2 */
__IO uint32_t RFC; /*!< Offset: 0x0020 SIO Receive FIFO Configuration Register */
__IO uint32_t TFC; /*!< Offset: 0x0024 SIO Transmit FIFO Configuration Register */
__I uint32_t RST; /*!< Offset: 0x0028 SIO Receive FIFO Status Register */
__I uint32_t TST; /*!< Offset: 0x002C SIO Transmit FIFO Status Register */
__IO uint8_t FCNF; /*!< Offset: 0x0030 SIO FIFO Configuration Register */
} TSB_SIO_TypeDef;
/*@}*/ /* end of group TMPM321_SIO_UART */
/*------------- Consumer Electronics Control (CEC) ---------------------------*/
/** @addtogroup TMPM321_CEC TMPM321 Consumer Electronics Control (CEC)
@{
*/
typedef struct
{
__IO uint32_t EN; /*!< Offset: 0x0000 CEC Enable Register */
__IO uint32_t ADD; /*!< Offset: 0x0004 CEC Logical Address Register */
__O uint32_t RESET; /*!< Offset: 0x0008 CEC Software Reset Register */
__IO uint32_t REN; /*!< Offset: 0x000C CEC Receive Enable Register */
__I uint32_t RBUF; /*!< Offset: 0x0010 CEC Receive Buffer Register */
__IO uint32_t RCR1; /*!< Offset: 0x0014 CEC Control Register 1 */
__IO uint32_t RCR2; /*!< Offset: 0x0018 CEC Control Register 2 */
__IO uint32_t RCR3; /*!< Offset: 0x001C CEC Control Register 3 */
__IO uint32_t TEN; /*!< Offset: 0x0020 CEC Transmit Enable Register */
__IO uint32_t TBUF; /*!< Offset: 0x0024 CEC Transmit Buffer Register */
__IO uint32_t TCR; /*!< Offset: 0x0028 CEC Transmit Control Register */
__I uint32_t RSTAT; /*!< Offset: 0x002C CEC Receive Interrupt Status Register */
__I uint32_t TSTAT; /*!< Offset: 0x0030 CEC Transmit Interrupt Status Register */
__I uint32_t FSSEL; /*!< Offset: 0x0034 CEC Frequency Select Register */
} TSB_CEC_TypeDef;
/*@}*/ /* end of group TMPM321_CEC */
/*------------- Remote Control Signal Preprocessor (RMC) ---------------------*/
/** @addtogroup TMPM321_RMC TMPM321 Remote Control Signal Preprocessor (RMC)
@{
*/
typedef struct
{
__IO uint32_t EN; /*!< Offset: 0x0000 RMC Enable Register */
__IO uint32_t REN; /*!< Offset: 0x0004 RMC Receive Enable Register */
__I uint32_t RBUF1; /*!< Offset: 0x0008 RMC Receive Data Buffer Register 1 */
__I uint32_t RBUF2; /*!< Offset: 0x000C RMC Receive Data Buffer Register 2 */
__I uint32_t RBUF3; /*!< Offset: 0x0010 RMC Receive Data Buffer Register 3 */
__IO uint32_t RCR1; /*!< Offset: 0x0014 RMC Control Register 1 */
__IO uint32_t RCR2; /*!< Offset: 0x0018 RMC Control Register 2 */
__IO uint32_t RCR3; /*!< Offset: 0x001C RMC Control Register 3 */
__IO uint32_t RCR4; /*!< Offset: 0x0020 RMC Control Register 4 */
__I uint32_t RSTAT; /*!< Offset: 0x0024 RMC Status Register */
__I uint32_t RNUM1; /*!< Offset: 0x0028 RMC Receive bit Number Register 1 */
__I uint32_t RNUM2; /*!< Offset: 0x002C RMC Receive bit Number Register 2 */
__I uint32_t RNUM3; /*!< Offset: 0x0030 RMC Receive bit Number Register 3 */
__I uint32_t FSSEL; /*!< Offset: 0x0034 RMC Frequency Selection Register */
} TSB_RMC_TypeDef;
/*@}*/ /* end of group TMPM321_RMC */
/*------------- 10-bit A/D Converter (A/DC) ----------------------------------*/
/** @addtogroup TMPM321_ADC TMPM321 10-bit A/D Converter (A/DC)
@{
*/
typedef struct
{
__IO uint32_t CLK; /*!< Offset: 0x0000 A/D Conversion Clock Setting Register */
__IO uint32_t MOD0; /*!< Offset: 0x0004 A/D Mode Control Register 0 */
__IO uint32_t MOD1; /*!< Offset: 0x0008 A/D Mode Control Register 1 */
__IO uint32_t MOD2; /*!< Offset: 0x000C A/D Mode Control Register 2 */
__IO uint32_t MOD3; /*!< Offset: 0x0010 A/D Mode Control Register 3 */
__IO uint32_t MOD4; /*!< Offset: 0x0014 A/D Mode Control Register 4 */
__IO uint32_t MOD5; /*!< Offset: 0x0018 A/D Mode Control Register 5 */
uint32_t RESERVED0;
__IO uint32_t CBAS; /*!< Offset: 0x0020 A/D Conversion Accuracy Setting Register */
uint32_t RESERVED1[3];
__IO uint32_t REG08; /*!< Offset: 0x0030 A/D Conversion Result Register 08L */
__IO uint32_t REG19; /*!< Offset: 0x0034 A/D Conversion Result Register 19L */
__IO uint32_t REG2A; /*!< Offset: 0x0038 A/D Conversion Result Register 2AL */
__IO uint32_t REG3B; /*!< Offset: 0x003C A/D Conversion Result Register 3BL */
__IO uint32_t REG4C; /*!< Offset: 0x0040 A/D Conversion Result Register 4CL */
__IO uint32_t REG5D; /*!< Offset: 0x0044 A/D Conversion Result Register 5DL */
__IO uint32_t REG6E; /*!< Offset: 0x0048 A/D Conversion Result Register 6EL */
__IO uint32_t REG7F; /*!< Offset: 0x004C A/D Conversion Result Register 7FL */
__IO uint32_t REGSP; /*!< Offset: 0x0050 A/D Conversion Result Register SP */
__IO uint32_t CMPREG0; /*!< Offset: 0x0054 A/D Conversion Result Comparison Register 0 */
__IO uint32_t CMPREG1; /*!< Offset: 0x0058 A/D Conversion Result Comparison Register 1 */
} TSB_ADC_TypeDef;
/*@}*/ /* end of group TMPM321_ADC */
/*------------- Key on Wake Up (KWUP) -----------------------------------------*/
/** @addtogroup TMPM321_KWUP TMPM321 Key on Wake Up (KWUP)
@{
*/
typedef struct
{
__IO uint32_t CR0; /*!< Offset: 0x0000 KWUP Control Register 0 */
__IO uint32_t CR1; /*!< Offset: 0x0004 KWUP Control Register 1 */
__IO uint32_t CR2; /*!< Offset: 0x0008 KWUP Control Register 2 */
__IO uint32_t CR3; /*!< Offset: 0x000C KWUP Control Register 3 */
uint32_t RESERVED0[28];
__IO uint32_t PKEY; /*!< Offset: 0x0080 KWUP Port Monitor Register */
__IO uint32_t CNT; /*!< Offset: 0x0084 KWUP Control Register */
__IO uint32_t CLR; /*!< Offset: 0x0088 KWUP Interrupt All Clear Register */
__IO uint32_t INT; /*!< Offset: 0x000C KWUP Interrupt Monitor Register */
} TSB_KWUP_TypeDef;
/*@}*/ /* end of group TMPM321_KWUP */
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
/** @addtogroup TMPM321_WDT TMPM321 Watchdog Timer (WDT)
@{
*/
typedef struct
{
__IO uint32_t MOD; /*!< Offset: 0x0000 WDT Mode Register */
__IO uint32_t CR; /*!< Offset: 0x0004 WDT Control Register */
} TSB_WDT_TypeDef;
/*@}*/ /* end of group TMPM321_WDT */
/*------------- Real Time Clock (RTC) ----------------------------------------*/
/** @addtogroup TMPM321_RTC TMPM321 Real Time Clock (RTC)
@{
*/
typedef struct
{
__IO uint8_t SECR; /*!< Offset: 0x0000 Second Column Register */
__IO uint8_t MINR; /*!< Offset: 0x0001 Minute Column Register */
__IO uint8_t HOURR; /*!< Offset: 0x0002 Hour Column Register */
uint8_t RESERVED0;
__IO uint8_t DAYR; /*!< Offset: 0x0004 Day of the Week Column Register */
__IO uint8_t DATER; /*!< Offset: 0x0005 Day Column Register */
__IO uint8_t MONTHR; /*!< Offset: 0x0006 Month Column Register */
__IO uint8_t YEARR; /*!< Offset: 0x0007 Year Column Register */
__IO uint32_t PAGER; /*!< Offset: 0x0008 PAGE Register */
__O uint32_t RESTR; /*!< Offset: 0x000C Reset Register */
} TSB_RTC_TypeDef;
/*@}*/ /* end of group TMPM321_RTC */
/*------------- Clock Generator (CG) -----------------------------------------*/
/** @addtogroup TMPM321_CG TMPM321 Clock Generator (CG)
@{
*/
typedef struct
{
__IO uint32_t SYSCR; /*!< Offset: 0x0000 System Control Register */
__IO uint32_t OSCCR; /*!< Offset: 0x0004 Oscillation Control Register */
__IO uint32_t STBYCR; /*!< Offset: 0x0008 Standby Control Register */
__IO uint32_t PLLSEL; /*!< Offset: 0x000C PLL Selection Register */
__IO uint32_t CKSEL; /*!< Offset: 0x0010 System Clock Selection Register */
__IO uint32_t ICRCG; /*!< Offset: 0x0014 CG Interrupt Request Clear Register (wr) */
__IO uint32_t NMIFLG; /*!< Offset: 0x0018 NMI Flag Register (rd) */
__IO uint32_t RSTFLG; /*!< Offset: 0x001C Reset Flag Register */
__IO uint32_t IMCGA; /*!< Offset: 0x0020 CG Interrupt Mode Control Register A */
__IO uint32_t IMCGB; /*!< Offset: 0x0024 CG Interrupt Mode Control Register B */
__IO uint32_t IMCGC; /*!< Offset: 0x0028 CG Interrupt Mode Control Register C */
__IO uint32_t IMCGD; /*!< Offset: 0x002C CG Interrupt Mode Control Register D */
__IO uint32_t IMCGE; /*!< Offset: 0x0030 CG Interrupt Mode Control Register E */
__IO uint32_t IMCGF; /*!< Offset: 0x0034 CG Interrupt Mode Control Register F */
} TSB_CG_TypeDef;
/*@}*/ /* end of group TMPM321_CG */
/*------------- FLASH Interface (FIF) -------------------------------------------*/
/** @addtogroup TMPM321_FIF TMPM321 FLASH Interface (FIF)
@{
*/
typedef struct
{
uint32_t RESERVED0[4];
__I uint32_t SECBITF0; /*!< Offset: 0x0010 Security Bit Register 0 */
uint32_t RESERVED1[3];
__I uint32_t FLCSF0; /*!< Offset: 0x0020 FLASH Control Register 0 */
uint32_t RESERVED2[4];
} TSB_FIF_TypeDef;
/*@}*/ /* end of group TMPM321_FIF */
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*@}*/ /* end of group TMPM321_Peripherals */
/******************************************************************************/
/* Memory Mapping */
/******************************************************************************/
/** @addtogroup TMPM321_MemoryMap TMPM321 Memory Mapping
@{
*/
#define TSB_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
#define TSB_RAM_BASE (0x20000000UL) /*!< (RAM ) Base Address */
#define TSB_PERI_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
#define TSB_DMAC_BASE (TSB_PERI_BASE + 0x00000000) /*!< (DMAC ) Base Address */
#define TSB_PA_BASE (TSB_PERI_BASE + 0x000C0000) /*!< (PA ) Base Address */
#define TSB_PB_BASE (TSB_PERI_BASE + 0x000C0100) /*!< (PB ) Base Address */
#define TSB_PE_BASE (TSB_PERI_BASE + 0x000C0400) /*!< (PE ) Base Address */
#define TSB_PF_BASE (TSB_PERI_BASE + 0x000C0500) /*!< (PF ) Base Address */
#define TSB_PG_BASE (TSB_PERI_BASE + 0x000C0600) /*!< (PG ) Base Address */
#define TSB_PI_BASE (TSB_PERI_BASE + 0x000C0800) /*!< (PI ) Base Address */
#define TSB_PJ_BASE (TSB_PERI_BASE + 0x000C0900) /*!< (PJ ) Base Address */
#define TSB_PL_BASE (TSB_PERI_BASE + 0x000C0B00) /*!< (PL ) Base Address */
#define TSB_PM_BASE (TSB_PERI_BASE + 0x000C0C00) /*!< (PM ) Base Address */
#define TSB_PN_BASE (TSB_PERI_BASE + 0x000C0D00) /*!< (PN ) Base Address */
#define TSB_PP_BASE (TSB_PERI_BASE + 0x000C0F00) /*!< (PP ) Base Address */
#define TSB_TB0_BASE (TSB_PERI_BASE + 0x000D0000) /*!< (TB0 ) Base Address */
#define TSB_TB1_BASE (TSB_PERI_BASE + 0x000D0100) /*!< (TB1 ) Base Address */
#define TSB_TB2_BASE (TSB_PERI_BASE + 0x000D0200) /*!< (TB2 ) Base Address */
#define TSB_TB3_BASE (TSB_PERI_BASE + 0x000D0300) /*!< (TB3 ) Base Address */
#define TSB_TB4_BASE (TSB_PERI_BASE + 0x000D0400) /*!< (TB4 ) Base Address */
#define TSB_TB5_BASE (TSB_PERI_BASE + 0x000D0500) /*!< (TB5 ) Base Address */
#define TSB_TB6_BASE (TSB_PERI_BASE + 0x000D0600) /*!< (TB6 ) Base Address */
#define TSB_TB7_BASE (TSB_PERI_BASE + 0x000D0700) /*!< (TB7 ) Base Address */
#define TSB_SBI0_BASE (TSB_PERI_BASE + 0x000E0000) /*!< (SBI0 ) Base Address */
#define TSB_SBI1_BASE (TSB_PERI_BASE + 0x000E0100) /*!< (SBI1 ) Base Address */
#define TSB_SBI2_BASE (TSB_PERI_BASE + 0x000E0200) /*!< (SBI2 ) Base Address */
#define TSB_SBI3_BASE (TSB_PERI_BASE + 0x000E0300) /*!< (SBI3 ) Base Address */
#define TSB_SIO0_BASE (TSB_PERI_BASE + 0x000E1000) /*!< (SIO0 ) Base Address */
#define TSB_SIO1_BASE (TSB_PERI_BASE + 0x000E1100) /*!< (SIO1 ) Base Address */
#define TSB_SIO2_BASE (TSB_PERI_BASE + 0x000E1200) /*!< (SIO2 ) Base Address */
#define TSB_SIO3_BASE (TSB_PERI_BASE + 0x000E1300) /*!< (SIO3 ) Base Address */
#define TSB_SIO4_BASE (TSB_PERI_BASE + 0x000E1400) /*!< (SIO4 ) Base Address */
#define TSB_CEC_BASE (TSB_PERI_BASE + 0x000E2000) /*!< (CEC ) Base Address */
#define TSB_RMC0_BASE (TSB_PERI_BASE + 0x000E3000) /*!< (RMC0 ) Base Address */
#define TSB_ADC_BASE (TSB_PERI_BASE + 0x000F0000) /*!< (ADC ) Base Address */
#define TSB_KWUP_BASE (TSB_PERI_BASE + 0x000F1000) /*!< (KWUP ) Base Address */
#define TSB_WDT_BASE (TSB_PERI_BASE + 0x000F2000) /*!< (WDT ) Base Address */
#define TSB_RTC_BASE (TSB_PERI_BASE + 0x000F3000) /*!< (RTC ) Base Address */
#define TSB_CG_BASE (TSB_PERI_BASE + 0x000F4000) /*!< (CG ) Base Address */
#define TSB_FIF_BASE (TSB_PERI_BASE + 0x01FFF000) /*!< (FIF ) Base Address */
/*@}*/ /* end of group TMPM321_MemoryMap */
/******************************************************************************/
/* Peripheral Declaration */
/******************************************************************************/
/** @addtogroup TMPM321_PeripheralDecl TMPM321 Peripheral Declaration
@{
*/
#define TSB_DMAC (( TSB_DMAC_TypeDef *) TSB_DMAC_BASE)
#define TSB_PA (( TSB_PORT_TypeDef *) TSB_PA_BASE)
#define TSB_PB (( TSB_PORT_TypeDef *) TSB_PB_BASE)
#define TSB_PE (( TSB_PORT_TypeDef *) TSB_PE_BASE)
#define TSB_PF (( TSB_PORT_TypeDef *) TSB_PF_BASE)
#define TSB_PG (( TSB_PORT_TypeDef *) TSB_PG_BASE)
#define TSB_PI (( TSB_PORT_TypeDef *) TSB_PI_BASE)
#define TSB_PJ (( TSB_PORT_TypeDef *) TSB_PJ_BASE)
#define TSB_PL (( TSB_PORT_TypeDef *) TSB_PL_BASE)
#define TSB_PM (( TSB_PORT_TypeDef *) TSB_PM_BASE)
#define TSB_PN (( TSB_PORT_TypeDef *) TSB_PN_BASE)
#define TSB_PP (( TSB_PORT_TypeDef *) TSB_PP_BASE)
#define TSB_TB0 (( TSB_TMRB_TypeDef *) TSB_TB0_BASE)
#define TSB_TB1 (( TSB_TMRB_TypeDef *) TSB_TB1_BASE)
#define TSB_TB2 (( TSB_TMRB_TypeDef *) TSB_TB2_BASE)
#define TSB_TB3 (( TSB_TMRB_TypeDef *) TSB_TB3_BASE)
#define TSB_TB4 (( TSB_TMRB_TypeDef *) TSB_TB4_BASE)
#define TSB_TB5 (( TSB_TMRB_TypeDef *) TSB_TB5_BASE)
#define TSB_TB6 (( TSB_TMRB_TypeDef *) TSB_TB6_BASE)
#define TSB_TB7 (( TSB_TMRB_TypeDef *) TSB_TB7_BASE)
#define TSB_SBI0 (( TSB_SBI_TypeDef *) TSB_SBI0_BASE)
#define TSB_SBI1 (( TSB_SBI_TypeDef *) TSB_SBI1_BASE)
#define TSB_SBI2 (( TSB_SBI_TypeDef *) TSB_SBI2_BASE)
#define TSB_SBI3 (( TSB_SBI_TypeDef *) TSB_SBI3_BASE)
#define TSB_SIO0 (( TSB_SIO_TypeDef *) TSB_SIO0_BASE)
#define TSB_SIO1 (( TSB_SIO_TypeDef *) TSB_SIO1_BASE)
#define TSB_SIO2 (( TSB_SIO_TypeDef *) TSB_SIO2_BASE)
#define TSB_SIO3 (( TSB_SIO_TypeDef *) TSB_SIO3_BASE)
#define TSB_SIO4 (( TSB_SIO_TypeDef *) TSB_SIO4_BASE)
#define TSB_CEC (( TSB_CEC_TypeDef *) TSB_CEC_BASE)
#define TSB_RMC0 (( TSB_RMC_TypeDef *) TSB_RMC0_BASE)
#define TSB_ADC (( TSB_ADC_TypeDef *) TSB_ADC_BASE)
#define TSB_KWUP (( TSB_KWUP_TypeDef *) TSB_KWUP_BASE)
#define TSB_WDT (( TSB_WDT_TypeDef *) TSB_WDT_BASE)
#define TSB_RTC (( TSB_RTC_TypeDef *) TSB_RTC_BASE)
#define TSB_CG (( TSB_CG_TypeDef *) TSB_CG_BASE)
#define TSB_FIF (( TSB_FIF_TypeDef *) TSB_FIF_BASE)
/*@}*/ /* end of group TMPM321_PeripheralDecl */
/*@}*/ /* end of group TMPM321_Definitions */
#ifdef __cplusplus
}
#endif
#endif /* __TMPM321_H__ */