/****************************************************************************************************//** * @file SN32F110.h * * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for * SN32F110 from SONiX Technology Co., Ltd.. * * @version V1.1 * @date 10. June 2013 * * @note Generated with SVDConv V2.79n * from CMSIS SVD File 'SN32F110.svd' Version 1.1, * * @par ARM Limited (ARM) is supplying this software for use with Cortex-M * processor based microcontroller, but can be equally used for other * suitable processor architectures. This file can be freely distributed. * Modifications to this file shall be clearly marked. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * *******************************************************************************************************/ /** @addtogroup SONiX Technology Co., Ltd. * @{ */ /** @addtogroup SN32F110 * @{ */ #ifndef SN32F110_H #define SN32F110_H #ifdef __cplusplus extern "C" { #endif /* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ /* --------------------- SN32F110 Specific Interrupt Numbers -------------------- */ P0_IRQn = 0, /*!< 0 P0 */ P1_IRQn = 1, /*!< 1 P1 */ P2_IRQn = 2, /*!< 2 P2 */ P3_IRQn = 3, /*!< 3 P3 */ CMP_IRQn = 17, /*!< 17 CMP */ CT16B0_IRQn = 18, /*!< 18 CT16B0 */ CT16B1_IRQn = 19, /*!< 19 CT16B1 */ CT32B0_IRQn = 20, /*!< 20 CT32B0 */ CT32B1_IRQn = 21, /*!< 21 CT32B1 */ I2S_IRQn = 22, /*!< 22 I2S */ SSP0_IRQn = 23, /*!< 23 SSP0 */ SSP1_IRQn = 24, /*!< 24 SSP1 */ UART0_IRQn = 25, /*!< 25 UART0 */ UART1_IRQn = 26, /*!< 26 UART1 */ I2C0_IRQn = 27, /*!< 27 I2C0 */ I2C1_IRQn = 28, /*!< 28 I2C1 */ WDT_IRQn = 29, /*!< 29 WDT */ LVD_IRQn = 30, /*!< 30 LVD */ RTC_IRQn = 31 /*!< 31 RTC */ } IRQn_Type; /** @addtogroup Configuration_of_CMSIS * @{ */ /* ================================================================================ */ /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ #define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** @} */ /* End of group Configuration_of_CMSIS */ #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ #include "system_SN32F110.h" /*!< SN32F110 System */ /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ /* ================================================================================ */ /** @addtogroup Device_Peripheral_Registers * @{ */ /* ------------------- Start of section using anonymous unions ------------------ */ #if defined(__CC_ARM) #pragma push #pragma anon_unions #elif defined(__ICCARM__) #pragma language=extended #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) #pragma warning 586 #else #warning Not supported compiler type #endif /* ================================================================================ */ /* ================ SN_SYS0 ================ */ /* ================================================================================ */ /** * @brief System Control Registers (SN_SYS0) */ typedef struct { /*!< SN_SYS0 Structure */ union { __IO uint32_t ANBCTRL; /*!< Offset:0x00 Analog Block Control Register */ struct { __IO uint32_t IHRCEN : 1; /*!< IHRC enable */ uint32_t : 1; __IO uint32_t ELSEN : 1; /*!< ELS XTAL enable */ uint32_t : 1; __IO uint32_t EHSEN : 1; /*!< EHS XTAL enable */ __IO uint32_t EHSFREQ : 1; /*!< EHS XTAL frequency range */ uint32_t : 2; __IO uint32_t AUEHSEN : 1; /*!< Audio external high-speed clock enable */ __IO uint32_t AUEHSFREQ : 1; /*!< AUEHS X'TAL Frequency range */ } ANBCTRL_b; /*!< BitSize */ }; union { __IO uint32_t PLLCTRL; /*!< Offset:0x04 PLL Control Register */ struct { __IO uint32_t MSEL : 5; /*!< M: 3~31 */ __IO uint32_t PSEL : 3; /*!< P=PSEL*2 */ __IO uint32_t FSEL : 1; /*!< F=POWER(2, FSEL) */ uint32_t : 3; __IO uint32_t PLLCLKSEL : 2; /*!< PLL clock source */ uint32_t : 1; __IO uint32_t PLLEN : 1; /*!< PLL enable */ } PLLCTRL_b; /*!< BitSize */ }; union { __I uint32_t CSST; /*!< Offset:0x08 Clock Source Status Register */ struct { __I uint32_t IHRCRDY : 1; /*!< IHRC ready flag */ uint32_t : 1; __I uint32_t ELSRDY : 1; /*!< ELS XTAL ready flag */ uint32_t : 1; __I uint32_t EHSRDY : 1; /*!< EHS XTAL ready flag */ uint32_t : 1; __I uint32_t PLLRDY : 1; /*!< PLL ready flag */ uint32_t : 1; __I uint32_t AUEHSRDY : 1; /*!< Audio external high-speed clock ready flag */ } CSST_b; /*!< BitSize */ }; union { __IO uint32_t CLKCFG; /*!< Offset:0x0C System Clock Configuration Register */ struct { __IO uint32_t SYSCLKSEL : 3; /*!< System clock source selection */ uint32_t : 1; __I uint32_t SYSCLKST : 3; /*!< System clock switch status */ } CLKCFG_b; /*!< BitSize */ }; union { __IO uint32_t AHBCP; /*!< Offset:0x10 AHB Clock Prescale Register */ struct { __IO uint32_t AHBPRE : 4; /*!< AHB clock source prescaler */ } AHBCP_b; /*!< BitSize */ }; union { __IO uint32_t RSTST; /*!< Offset:0x14 System Reset Status Register */ struct { __IO uint32_t SWRSTF : 1; /*!< Software reset flag */ __IO uint32_t WDTRSTF : 1; /*!< WDT reset flag */ __IO uint32_t LVDRSTF : 1; /*!< LVD reset flag */ __IO uint32_t EXTRSTF : 1; /*!< External reset flag */ __IO uint32_t PORRSTF : 1; /*!< POR reset flag */ } RSTST_b; /*!< BitSize */ }; union { __IO uint32_t LVDCTRL; /*!< Offset:0x18 LVD Control Register */ struct { __IO uint32_t LVDRSTLVL : 2; /*!< LVD reset level */ uint32_t : 2; __IO uint32_t LVDINTLVL : 2; /*!< LVD interrupt level */ uint32_t : 8; __IO uint32_t LVDRSTEN : 1; /*!< LVD Reset enable */ __IO uint32_t LVDEN : 1; /*!< LVD enable */ } LVDCTRL_b; /*!< BitSize */ }; union { __IO uint32_t EXRSTCTRL; /*!< Offset:0x1C External Reset Pin Control Register */ struct { __IO uint32_t RESETDIS : 1; /*!< External reset pin disable */ } EXRSTCTRL_b; /*!< BitSize */ }; union { __IO uint32_t SWDCTRL; /*!< Offset:0x20 SWD Pin Control Register */ struct { __IO uint32_t SWDDIS : 1; /*!< SWD pin disable */ } SWDCTRL_b; /*!< BitSize */ }; __I uint32_t RESERVED0[3]; union { __IO uint32_t ANTIEFT; /*!< Offset:0x30 Anti-EFT Ability Control Register */ struct { __IO uint32_t AEFT : 3; /*!< HW anti-EFT ability */ } ANTIEFT_b; /*!< BitSize */ }; } SN_SYS0_Type; /* ================================================================================ */ /* ================ SN_SYS1 ================ */ /* ================================================================================ */ /** * @brief System Control Registers (SN_SYS1) */ typedef struct { /*!< SN_SYS1 Structure */ union { __IO uint32_t AHBCLKEN; /*!< Offset:0x00 AHB Clock Enable Register */ struct { uint32_t : 3; __IO uint32_t GPIOCLKEN : 1; /*!< Enable AHB clock for GPIO */ uint32_t : 2; __IO uint32_t CT16B0CLKEN: 1; /*!< Enable AHB clock for CT16B0 */ __IO uint32_t CT16B1CLKEN: 1; /*!< Enable AHB clock for CT16B1 */ __IO uint32_t CT32B0CLKEN: 1; /*!< Enable AHB clock for CT32B0 */ __IO uint32_t CT32B1CLKEN: 1; /*!< Enable AHB clock for CT32B1 */ uint32_t : 1; __IO uint32_t CMPCLKEN : 1; /*!< Enable AHB clock for comparator */ __IO uint32_t SSP0CLKEN : 1; /*!< Enable AHB clock for SSP0 */ __IO uint32_t SSP1CLKEN : 1; /*!< Enable AHB clock for SSP1 */ uint32_t : 2; __IO uint32_t UART0CLKEN : 1; /*!< Enable AHB clock for UART0 */ __IO uint32_t UART1CLKEN : 1; /*!< Enable AHB clock for UART1 */ uint32_t : 2; __IO uint32_t I2C1CLKEN : 1; /*!< Enable AHB clock for I2C1 */ __IO uint32_t I2C0CLKEN : 1; /*!< Enable AHB clock for I2C0 */ __IO uint32_t I2SCLKEN : 1; /*!< Enable AHB clock for I2S */ __IO uint32_t RTCCLKEN : 1; /*!< Enable AHB clock for RTC */ __IO uint32_t WDTCLKEN : 1; /*!< Enable AHB clock for WDT */ uint32_t : 3; __IO uint32_t CLKOUTSEL : 3; /*!< Clock output source selection */ } AHBCLKEN_b; /*!< BitSize */ }; union { __IO uint32_t APBCP0; /*!< Offset:0x04 APB Clock Prescale Register 0 */ struct { __IO uint32_t CT16B0PRE : 3; /*!< CT16B0 APB clock source prescaler */ uint32_t : 1; __IO uint32_t CT16B1PRE : 3; /*!< CT16B1 APB clock source prescaler */ uint32_t : 1; __IO uint32_t CT32B0PRE : 3; /*!< CT32B0 APB clock source prescaler */ uint32_t : 1; __IO uint32_t CT32B1PRE : 3; /*!< CT32B1 APB clock source prescaler */ uint32_t : 1; __IO uint32_t CMPPRE : 3; /*!< Comparator clock source prescaler */ uint32_t : 1; __IO uint32_t SSP0PRE : 3; /*!< SSP0 APB clock source prescaler */ uint32_t : 1; __IO uint32_t SSP1PRE : 3; /*!< SSP1 APB clock source prescaler */ uint32_t : 1; __IO uint32_t AUEHSPRE : 3; /*!< Audio external high clock source prescaler */ } APBCP0_b; /*!< BitSize */ }; union { __IO uint32_t APBCP1; /*!< Offset:0x08 APB Clock Prescale Register 1 */ struct { __IO uint32_t UART0PRE : 3; /*!< UART0 APB clock source prescaler */ uint32_t : 1; __IO uint32_t UART1PRE : 3; /*!< UART1 APB clock source prescaler */ uint32_t : 1; __IO uint32_t I2C0PRE : 3; /*!< I2C0 APB clock source prescaler */ uint32_t : 1; __IO uint32_t I2SPRE : 3; /*!< I2S APB clock source prescaler */ uint32_t : 1; __IO uint32_t SYSTICKPRE : 2; /*!< SysTick APB clock source prescaler */ uint32_t : 2; __IO uint32_t WDTPRE : 3; /*!< WDT APB clock source prescaler */ uint32_t : 1; __IO uint32_t I2C1PRE : 3; /*!< I2C1 APB clock source prescaler */ uint32_t : 1; __IO uint32_t CLKOUTPRE : 4; /*!< CLKOUT APB clock source prescaler */ } APBCP1_b; /*!< BitSize */ }; union { __IO uint32_t PRST; /*!< Offset:0x0C Peripheral Reset Register */ struct { __IO uint32_t GPIO0RST : 1; /*!< GPIO0 Reset */ __IO uint32_t GPIO1RST : 1; /*!< GPIO1 Reset */ __IO uint32_t GPIO2RST : 1; /*!< GPIO2 Reset */ __IO uint32_t GPIO3RST : 1; /*!< GPIO3 Reset */ uint32_t : 2; __IO uint32_t CT16B0RST : 1; /*!< CT16B0 Reset */ __IO uint32_t CT16B1RST : 1; /*!< CT16B1 Reset */ __IO uint32_t CT32B0RST : 1; /*!< CT32B0 Reset */ __IO uint32_t CT32B1RST : 1; /*!< CT32B1 Reset */ uint32_t : 1; __IO uint32_t CMPRST : 1; /*!< Comparator Reset */ __IO uint32_t SSP0RST : 1; /*!< SSP0 Reset */ __IO uint32_t SSP1RST : 1; /*!< SSP1 Reset */ uint32_t : 2; __IO uint32_t UART0RST : 1; /*!< UART0 Reset */ __IO uint32_t UART1RST : 1; /*!< UART1 Reset */ uint32_t : 2; __IO uint32_t I2C1RST : 1; /*!< I2C1 Reset */ __IO uint32_t I2C0RST : 1; /*!< I2C0 Reset */ __IO uint32_t I2SRST : 1; /*!< I2S Reset */ __IO uint32_t RTCRST : 1; /*!< RTC Reset */ __IO uint32_t WDTRST : 1; /*!< WDT Reset */ __IO uint32_t CODECDARST : 1; /*!< Codec DAC reset */ __IO uint32_t CODECADRST : 1; /*!< Codec ADC reset */ } PRST_b; /*!< BitSize */ }; } SN_SYS1_Type; /* ================================================================================ */ /* ================ SN_GPIO0 ================ */ /* ================================================================================ */ /** * @brief General Purpose I/O (SN_GPIO0) */ typedef struct { /*!< SN_GPIO0 Structure */ union { __IO uint32_t DATA; /*!< Offset:0x00 GPIO Port n Data Register */ struct { __IO uint32_t DATA0 : 1; /*!< Data of Pn.0 */ __IO uint32_t DATA1 : 1; /*!< Data of Pn.1 */ __IO uint32_t DATA2 : 1; /*!< Data of Pn.2 */ __IO uint32_t DATA3 : 1; /*!< Data of Pn.3 */ __IO uint32_t DATA4 : 1; /*!< Data of Pn.4 */ __IO uint32_t DATA5 : 1; /*!< Data of Pn.5 */ __IO uint32_t DATA6 : 1; /*!< Data of Pn.6 */ __IO uint32_t DATA7 : 1; /*!< Data of Pn.7 */ __IO uint32_t DATA8 : 1; /*!< Data of Pn.8 */ __IO uint32_t DATA9 : 1; /*!< Data of Pn.9 */ __IO uint32_t DATA10 : 1; /*!< Data of Pn.10 */ __IO uint32_t DATA11 : 1; /*!< Data of Pn.11 */ __IO uint32_t DATA12 : 1; /*!< Data of Pn.12 */ __IO uint32_t DATA13 : 1; /*!< Data of Pn.13 */ __IO uint32_t DATA14 : 1; /*!< Data of Pn.14 */ __IO uint32_t DATA15 : 1; /*!< Data of Pn.15 */ } DATA_b; /*!< BitSize */ }; union { __IO uint32_t MODE; /*!< Offset:0x04 GPIO Port n Mode Register */ struct { __IO uint32_t MODE0 : 1; /*!< Mode of Pn.0 */ __IO uint32_t MODE1 : 1; /*!< Mode of Pn.1 */ __IO uint32_t MODE2 : 1; /*!< Mode of Pn.2 */ __IO uint32_t MODE3 : 1; /*!< Mode of Pn.3 */ __IO uint32_t MODE4 : 1; /*!< Mode of Pn.4 */ __IO uint32_t MODE5 : 1; /*!< Mode of Pn.5 */ __IO uint32_t MODE6 : 1; /*!< Mode of Pn.6 */ __IO uint32_t MODE7 : 1; /*!< Mode of Pn.7 */ __IO uint32_t MODE8 : 1; /*!< Mode of Pn.8 */ __IO uint32_t MODE9 : 1; /*!< Mode of Pn.9 */ __IO uint32_t MODE10 : 1; /*!< Mode of Pn.10 */ __IO uint32_t MODE11 : 1; /*!< Mode of Pn.11 */ __IO uint32_t MODE12 : 1; /*!< Mode of Pn.12 */ __IO uint32_t MODE13 : 1; /*!< Mode of Pn.13 */ __IO uint32_t MODE14 : 1; /*!< Mode of Pn.14 */ __IO uint32_t MODE15 : 1; /*!< Mode of Pn.15 */ } MODE_b; /*!< BitSize */ }; union { __IO uint32_t CFG; /*!< Offset:0x08 GPIO Port n Configuration Register */ struct { __IO uint32_t CFG0 : 2; /*!< Configuration of Pn.0 */ __IO uint32_t CFG1 : 2; /*!< Configuration of Pn.1 */ __IO uint32_t CFG2 : 2; /*!< Configuration of Pn.2 */ __IO uint32_t CFG3 : 2; /*!< Configuration of Pn.3 */ __IO uint32_t CFG4 : 2; /*!< Configuration of Pn.4 */ __IO uint32_t CFG5 : 2; /*!< Configuration of Pn.5 */ __IO uint32_t CFG6 : 2; /*!< Configuration of Pn.6 */ __IO uint32_t CFG7 : 2; /*!< Configuration of Pn.7 */ __IO uint32_t CFG8 : 2; /*!< Configuration of Pn.8 */ __IO uint32_t CFG9 : 2; /*!< Configuration of Pn.9 */ __IO uint32_t CFG10 : 2; /*!< Configuration of Pn.10 */ __IO uint32_t CFG11 : 2; /*!< Configuration of Pn.11 */ __IO uint32_t CFG12 : 2; /*!< Configuration of Pn.12 */ __IO uint32_t CFG13 : 2; /*!< Configuration of Pn.13 */ __IO uint32_t CFG14 : 2; /*!< Configuration of Pn.14 */ __IO uint32_t CFG15 : 2; /*!< Configuration of Pn.15 */ } CFG_b; /*!< BitSize */ }; union { __IO uint32_t IS; /*!< Offset:0x0C GPIO Port n Interrupt Sense Register */ struct { __IO uint32_t IS0 : 1; /*!< Interrupt on Pn.0 is event or edge sensitive */ __IO uint32_t IS1 : 1; /*!< Interrupt on Pn.1 is event or edge sensitive */ __IO uint32_t IS2 : 1; /*!< Interrupt on Pn.2 is event or edge sensitive */ __IO uint32_t IS3 : 1; /*!< Interrupt on Pn.3 is event or edge sensitive */ __IO uint32_t IS4 : 1; /*!< Interrupt on Pn.4 is event or edge sensitive */ __IO uint32_t IS5 : 1; /*!< Interrupt on Pn.5 is event or edge sensitive */ __IO uint32_t IS6 : 1; /*!< Interrupt on Pn.6 is event or edge sensitive */ __IO uint32_t IS7 : 1; /*!< Interrupt on Pn.7 is event or edge sensitive */ __IO uint32_t IS8 : 1; /*!< Interrupt on Pn.8 is event or edge sensitive */ __IO uint32_t IS9 : 1; /*!< Interrupt on Pn.9 is event or edge sensitive */ __IO uint32_t IS10 : 1; /*!< Interrupt on Pn.10 is event or edge sensitive */ __IO uint32_t IS11 : 1; /*!< Interrupt on Pn.11 is event or edge sensitive */ __IO uint32_t IS12 : 1; /*!< Interrupt on Pn.12 is event or edge sensitive */ __IO uint32_t IS13 : 1; /*!< Interrupt on Pn.13 is event or edge sensitive */ __IO uint32_t IS14 : 1; /*!< Interrupt on Pn.14 is event or edge sensitive */ __IO uint32_t IS15 : 1; /*!< Interrupt on Pn.15 is event or edge sensitive */ } IS_b; /*!< BitSize */ }; union { __IO uint32_t IBS; /*!< Offset:0x10 GPIO Port n Interrupt Both-edge Sense Register */ struct { __IO uint32_t IBS0 : 1; /*!< Interrupt on Pn.0 is triggered ob both edges */ __IO uint32_t IBS1 : 1; /*!< Interrupt on Pn.1 is triggered ob both edges */ __IO uint32_t IBS2 : 1; /*!< Interrupt on Pn.2 is triggered ob both edges */ __IO uint32_t IBS3 : 1; /*!< Interrupt on Pn.3 is triggered ob both edges */ __IO uint32_t IBS4 : 1; /*!< Interrupt on Pn.4 is triggered ob both edges */ __IO uint32_t IBS5 : 1; /*!< Interrupt on Pn.5 is triggered ob both edges */ __IO uint32_t IBS6 : 1; /*!< Interrupt on Pn.6 is triggered ob both edges */ __IO uint32_t IBS7 : 1; /*!< Interrupt on Pn.7 is triggered ob both edges */ __IO uint32_t IBS8 : 1; /*!< Interrupt on Pn.8 is triggered ob both edges */ __IO uint32_t IBS9 : 1; /*!< Interrupt on Pn.9 is triggered ob both edges */ __IO uint32_t IBS10 : 1; /*!< Interrupt on Pn.10 is triggered ob both edges */ __IO uint32_t IBS11 : 1; /*!< Interrupt on Pn.11 is triggered ob both edges */ __IO uint32_t IBS12 : 1; /*!< Interrupt on Pn.12 is triggered ob both edges */ __IO uint32_t IBS13 : 1; /*!< Interrupt on Pn.13 is triggered ob both edges */ __IO uint32_t IBS14 : 1; /*!< Interrupt on Pn.14 is triggered ob both edges */ __IO uint32_t IBS15 : 1; /*!< Interrupt on Pn.15 is triggered ob both edges */ } IBS_b; /*!< BitSize */ }; union { __IO uint32_t IEV; /*!< Offset:0x14 GPIO Port n Interrupt Event Register */ struct { __IO uint32_t IEV0 : 1; /*!< Interrupt trigged evnet on Pn.0 */ __IO uint32_t IEV1 : 1; /*!< Interrupt trigged evnet on Pn.1 */ __IO uint32_t IEV2 : 1; /*!< Interrupt trigged evnet on Pn.2 */ __IO uint32_t IEV3 : 1; /*!< Interrupt trigged evnet on Pn.3 */ __IO uint32_t IEV4 : 1; /*!< Interrupt trigged evnet on Pn.4 */ __IO uint32_t IEV5 : 1; /*!< Interrupt trigged evnet on Pn.5 */ __IO uint32_t IEV6 : 1; /*!< Interrupt trigged evnet on Pn.6 */ __IO uint32_t IEV7 : 1; /*!< Interrupt trigged evnet on Pn.7 */ __IO uint32_t IEV8 : 1; /*!< Interrupt trigged evnet on Pn.8 */ __IO uint32_t IEV9 : 1; /*!< Interrupt trigged evnet on Pn.9 */ __IO uint32_t IEV10 : 1; /*!< Interrupt trigged evnet on Pn.10 */ __IO uint32_t IEV11 : 1; /*!< Interrupt trigged evnet on Pn.11 */ __IO uint32_t IEV12 : 1; /*!< Interrupt trigged evnet on Pn.12 */ __IO uint32_t IEV13 : 1; /*!< Interrupt trigged evnet on Pn.13 */ __IO uint32_t IEV14 : 1; /*!< Interrupt trigged evnet on Pn.14 */ __IO uint32_t IEV15 : 1; /*!< Interrupt trigged evnet on Pn.15 */ } IEV_b; /*!< BitSize */ }; union { __IO uint32_t IE; /*!< Offset:0x18 GPIO Port n Interrupt Enable Register */ struct { __IO uint32_t IE0 : 1; /*!< Interrupt on Pn.0 enable */ __IO uint32_t IE1 : 1; /*!< Interrupt on Pn.1 enable */ __IO uint32_t IE2 : 1; /*!< Interrupt on Pn.2 enable */ __IO uint32_t IE3 : 1; /*!< Interrupt on Pn.3 enable */ __IO uint32_t IE4 : 1; /*!< Interrupt on Pn.4 enable */ __IO uint32_t IE5 : 1; /*!< Interrupt on Pn.5 enable */ __IO uint32_t IE6 : 1; /*!< Interrupt on Pn.6 enable */ __IO uint32_t IE7 : 1; /*!< Interrupt on Pn.7 enable */ __IO uint32_t IE8 : 1; /*!< Interrupt on Pn.8 enable */ __IO uint32_t IE9 : 1; /*!< Interrupt on Pn.9 enable */ __IO uint32_t IE10 : 1; /*!< Interrupt on Pn.10 enable */ __IO uint32_t IE11 : 1; /*!< Interrupt on Pn.11 enable */ __IO uint32_t IE12 : 1; /*!< Interrupt on Pn.11 enable */ __IO uint32_t IE13 : 1; /*!< Interrupt on Pn.13 enable */ __IO uint32_t IE14 : 1; /*!< Interrupt on Pn.14 enable */ __IO uint32_t IE15 : 1; /*!< Interrupt on Pn.15 enable */ } IE_b; /*!< BitSize */ }; union { __I uint32_t RIS; /*!< Offset:0x1C GPIO Port n Raw Interrupt Status Register */ struct { __I uint32_t IF0 : 1; /*!< Pn.0 raw interrupt flag */ __I uint32_t IF1 : 1; /*!< Pn.1 raw interrupt flag */ __I uint32_t IF2 : 1; /*!< Pn.2 raw interrupt flag */ __I uint32_t IF3 : 1; /*!< Pn.3 raw interrupt flag */ __I uint32_t IF4 : 1; /*!< Pn.4 raw interrupt flag */ __I uint32_t IF5 : 1; /*!< Pn.5 raw interrupt flag */ __I uint32_t IF6 : 1; /*!< Pn.6 raw interrupt flag */ __I uint32_t IF7 : 1; /*!< Pn.7 raw interrupt flag */ __I uint32_t IF8 : 1; /*!< Pn.8 raw interrupt flag */ __I uint32_t IF9 : 1; /*!< Pn.9 raw interrupt flag */ __I uint32_t IF10 : 1; /*!< Pn.10 raw interrupt flag */ __I uint32_t IF11 : 1; /*!< Pn.11 raw interrupt flag */ __I uint32_t IF12 : 1; /*!< Pn.12 raw interrupt flag */ __I uint32_t IF13 : 1; /*!< Pn.13 raw interrupt flag */ __I uint32_t IF14 : 1; /*!< Pn.14 raw interrupt flag */ __I uint32_t IF15 : 1; /*!< Pn.15 raw interrupt flag */ } RIS_b; /*!< BitSize */ }; union { __O uint32_t IC; /*!< Offset:0x20 GPIO Port n Interrupt Clear Register */ struct { __O uint32_t IC0 : 1; /*!< Pn.0 interrupt flag clear */ __O uint32_t IC1 : 1; /*!< Pn.1 interrupt flag clear */ __O uint32_t IC2 : 1; /*!< Pn.2 interrupt flag clear */ __O uint32_t IC3 : 1; /*!< Pn.3 interrupt flag clear */ __O uint32_t IC4 : 1; /*!< Pn.4 interrupt flag clear */ __O uint32_t IC5 : 1; /*!< Pn.5 interrupt flag clear */ __O uint32_t IC6 : 1; /*!< Pn.6 interrupt flag clear */ __O uint32_t IC7 : 1; /*!< Pn.7 interrupt flag clear */ __O uint32_t IC8 : 1; /*!< Pn.8 interrupt flag clear */ __O uint32_t IC9 : 1; /*!< Pn.9 interrupt flag clear */ __O uint32_t IC10 : 1; /*!< Pn.10 interrupt flag clear */ __O uint32_t IC11 : 1; /*!< Pn.11 interrupt flag clear */ __O uint32_t IC12 : 1; /*!< Pn.12 interrupt flag clear */ __O uint32_t IC13 : 1; /*!< Pn.13 interrupt flag clear */ __O uint32_t IC14 : 1; /*!< Pn.14 interrupt flag clear */ __O uint32_t IC15 : 1; /*!< Pn.15 interrupt flag clear */ } IC_b; /*!< BitSize */ }; union { __O uint32_t BSET; /*!< Offset:0x24 GPIO Port n Bits Set Operation Register */ struct { __O uint32_t BSET0 : 1; /*!< Set Pn.0 */ __O uint32_t BSET1 : 1; /*!< Set Pn.1 */ __O uint32_t BSET2 : 1; /*!< Set Pn.2 */ __O uint32_t BSET3 : 1; /*!< Set Pn.3 */ __O uint32_t BSET4 : 1; /*!< Set Pn.4 */ __O uint32_t BSET5 : 1; /*!< Set Pn.5 */ __O uint32_t BSET6 : 1; /*!< Set Pn.6 */ __O uint32_t BSET7 : 1; /*!< Set Pn.7 */ __O uint32_t BSET8 : 1; /*!< Set Pn.8 */ __O uint32_t BSET9 : 1; /*!< Set Pn.9 */ __O uint32_t BSET10 : 1; /*!< Set Pn.10 */ __O uint32_t BSET11 : 1; /*!< Set Pn.11 */ __O uint32_t BSET12 : 1; /*!< Set Pn.12 */ __O uint32_t BSET13 : 1; /*!< Set Pn.13 */ __O uint32_t BSET14 : 1; /*!< Set Pn.14 */ __O uint32_t BSET15 : 1; /*!< Set Pn.15 */ } BSET_b; /*!< BitSize */ }; union { __O uint32_t BCLR; /*!< Offset:0x28 GPIO Port n Bits Clear Operation Register */ struct { __O uint32_t BCLR0 : 1; /*!< Clear Pn.0 */ __O uint32_t BCLR1 : 1; /*!< Clear Pn.1 */ __O uint32_t BCLR2 : 1; /*!< Clear Pn.2 */ __O uint32_t BCLR3 : 1; /*!< Clear Pn.3 */ __O uint32_t BCLR4 : 1; /*!< Clear Pn.4 */ __O uint32_t BCLR5 : 1; /*!< Clear Pn.5 */ __O uint32_t BCLR6 : 1; /*!< Clear Pn.6 */ __O uint32_t BCLR7 : 1; /*!< Clear Pn.7 */ __O uint32_t BCLR8 : 1; /*!< Clear Pn.8 */ __O uint32_t BCLR9 : 1; /*!< Clear Pn.9 */ __O uint32_t BCLR10 : 1; /*!< Clear Pn.10 */ __O uint32_t BCLR11 : 1; /*!< Clear Pn.11 */ __O uint32_t BCLR12 : 1; /*!< Clear Pn.12 */ __O uint32_t BCLR13 : 1; /*!< Clear Pn.13 */ __O uint32_t BCLR14 : 1; /*!< Clear Pn.14 */ __O uint32_t BCLR15 : 1; /*!< Clear Pn.15 */ } BCLR_b; /*!< BitSize */ }; union { __IO uint32_t ODCTRL; /*!< Offset:0x2C GPIO Port n Open-drain Control Register */ struct { __IO uint32_t Pn0OC : 1; /*!< Pn.0 open-drain control */ __IO uint32_t Pn1OC : 1; /*!< Pn.1 open-drain control */ __IO uint32_t Pn2OC : 1; /*!< Pn.2 open-drain control */ __IO uint32_t Pn3OC : 1; /*!< Pn.3 open-drain control */ uint32_t : 8; __IO uint32_t Pn12OC : 1; /*!< Pn.12 open-drain control */ __IO uint32_t Pn13OC : 1; /*!< Pn.13 open-drain control */ __IO uint32_t Pn14OC : 1; /*!< Pn.14 open-drain control */ __IO uint32_t Pn15OC : 1; /*!< Pn.15 open-drain control */ } ODCTRL_b; /*!< BitSize */ }; } SN_GPIO0_Type; /* ================================================================================ */ /* ================ SN_WDT ================ */ /* ================================================================================ */ /** * @brief Watchdog Timer (SN_WDT) */ typedef struct { /*!< SN_WDT Structure */ union { __IO uint32_t CFG; /*!< Offset:0x00 WDT Configuration Register */ struct { __IO uint32_t WDTEN : 1; /*!< WDT enable */ __IO uint32_t WDTIE : 1; /*!< WDT interrupt enable */ __IO uint32_t WDTINT : 1; /*!< WDT interrupt flag */ uint32_t : 13; __O uint32_t WDKEY : 16; /*!< Watchdog register key */ } CFG_b; /*!< BitSize */ }; union { __IO uint32_t CLKSOURCE; /*!< Offset:0x04 WDT Clock Source Register */ struct { __IO uint32_t CLKSOURCE : 2; /*!< WDT clock source */ uint32_t : 14; __O uint32_t WDKEY : 16; /*!< Watchdog register key */ } CLKSOURCE_b; /*!< BitSize */ }; union { __IO uint32_t TC; /*!< Offset:0x08 WDT Timer Constant Register */ struct { __IO uint32_t TC : 8; /*!< Watchdog timer constant reload value */ uint32_t : 8; __O uint32_t WDKEY : 16; /*!< Watchdog register key */ } TC_b; /*!< BitSize */ }; union { __O uint32_t FEED; /*!< Offset:0x0C WDT Feed Register */ struct { __O uint32_t FV : 16; /*!< Watchdog feed value */ __O uint32_t WDKEY : 16; /*!< Watchdog register key */ } FEED_b; /*!< BitSize */ }; } SN_WDT_Type; /* ================================================================================ */ /* ================ SN_RTC ================ */ /* ================================================================================ */ /** * @brief Real-time Clock (SN_RTC) */ typedef struct { /*!< SN_RTC Structure */ union { __IO uint32_t CTRL; /*!< Offset:0x00 RTC Control Register */ struct { __IO uint32_t RTCEN : 1; /*!< RTC enable */ } CTRL_b; /*!< BitSize */ }; union { __IO uint32_t CLKS; /*!< Offset:0x04 RTC Clock Source Register */ struct { __IO uint32_t CLKSEL : 2; /*!< RTC clock source */ } CLKS_b; /*!< BitSize */ }; union { __IO uint32_t IE; /*!< Offset:0x08 RTC Interrupt Enable Register */ struct { __IO uint32_t SECIE : 1; /*!< Second interrupt enable */ __IO uint32_t ALMIE : 1; /*!< Alarm interrupt enable */ __IO uint32_t OVFIE : 1; /*!< Overflow interrupt enable */ } IE_b; /*!< BitSize */ }; union { __I uint32_t RIS; /*!< Offset:0x0C RTC Raw Interrupt Status Register */ struct { __I uint32_t SECIF : 1; /*!< Second interrupt flag */ __I uint32_t ALMIF : 1; /*!< Alarm interrupt flag */ __I uint32_t OVFIF : 1; /*!< Overflow interrupt flag */ } RIS_b; /*!< BitSize */ }; union { __O uint32_t IC; /*!< Offset:0x10 RTC Interrupt Clear Register */ struct { __O uint32_t SECIC : 1; /*!< Second interrupt flag clear */ __O uint32_t ALMIC : 1; /*!< Alarm interrupt flag clear */ __O uint32_t OVFIC : 1; /*!< Overflow interrupt flag clear */ } IC_b; /*!< BitSize */ }; __IO uint32_t SECCNTV; /*!< Offset:0x14 RTC Second Counter Reload Value Register */ __I uint32_t SECCNT; /*!< Offset:0x18 RTC Second Counter Register */ __IO uint32_t ALMCNTV; /*!< Offset:0x1C RTC Alarm Counter Reload Value Register */ __I uint32_t ALMCNT; /*!< Offset:0x20 RTC Alarm Counter Register */ } SN_RTC_Type; /* ================================================================================ */ /* ================ SN_CT16B0 ================ */ /* ================================================================================ */ /** * @brief 16-bit Timer 0 with Capture function (SN_CT16B0) */ typedef struct { /*!< SN_CT16B0 Structure */ union { __IO uint32_t TMRCTRL; /*!< Offset:0x00 CT16Bn Timer Control Register */ struct { __IO uint32_t CEN : 1; /*!< Counter enable */ __IO uint32_t CRST : 1; /*!< Counter Reset */ } TMRCTRL_b; /*!< BitSize */ }; union { __IO uint32_t TC; /*!< Offset:0x04 CT16Bn Timer Counter Register */ struct { __IO uint32_t TC : 16; /*!< Timer Counter */ } TC_b; /*!< BitSize */ }; union { __IO uint32_t PRE; /*!< Offset:0x08 CT16Bn Prescale Register */ struct { __IO uint32_t PR : 16; /*!< Prescaler */ } PRE_b; /*!< BitSize */ }; union { __IO uint32_t PC; /*!< Offset:0x0C CT16Bn Prescale Counter Register */ struct { __IO uint32_t PC : 16; /*!< Prescaler Counter */ } PC_b; /*!< BitSize */ }; union { __IO uint32_t CNTCTRL; /*!< Offset:0x10 CT16Bn Counter Control Register */ struct { __IO uint32_t CTM : 2; /*!< Counter/Timer Mode */ __IO uint32_t CIS : 2; /*!< Counter Input Select */ } CNTCTRL_b; /*!< BitSize */ }; union { __IO uint32_t MCTRL; /*!< Offset:0x14 CT16Bn Match Control Register */ struct { __IO uint32_t MR0IE : 1; /*!< Enable generating an interrupt when MR0 matches TC */ __IO uint32_t MR0RST : 1; /*!< Enable reset TC when MR0 matches TC */ __IO uint32_t MR0STOP : 1; /*!< Stop TC and PC and clear CEN bit when MR0 matches TC */ __IO uint32_t MR1IE : 1; /*!< Enable generating an interrupt when MR1 matches TC */ __IO uint32_t MR1RST : 1; /*!< Enable reset TC when MR1 matches TC */ __IO uint32_t MR1STOP : 1; /*!< Stop TC and PC and clear CEN bit when MR1 matches TC */ __IO uint32_t MR2IE : 1; /*!< Enable generating an interrupt when MR2 matches TC */ __IO uint32_t MR2RST : 1; /*!< Enable reset TC when MR2 matches TC */ __IO uint32_t MR2STOP : 1; /*!< Stop TC and PC and clear CEN bit when MR2 matches TC */ __IO uint32_t MR3IE : 1; /*!< Enable generating an interrupt when MR3 matches TC */ __IO uint32_t MR3RST : 1; /*!< Enable reset TC when MR3 matches TC */ __IO uint32_t MR3STOP : 1; /*!< Stop TC and PC and clear CEN bit when MR3 matches TC */ } MCTRL_b; /*!< BitSize */ }; __IO uint32_t MR0; /*!< Offset:0x18 CT16Bn MR0 Register */ __IO uint32_t MR1; /*!< Offset:0x1C CT16Bn MR1 Register */ __IO uint32_t MR2; /*!< Offset:0x20 CT16Bn MR2 Register */ __IO uint32_t MR3; /*!< Offset:0x24 CT16Bn MR3 Register */ union { __IO uint32_t CAPCTRL; /*!< Offset:0x28 CT16Bn Capture Control Register */ struct { __IO uint32_t CAP0RE : 2; /*!< Capture/Reset on CT16Bn_CAP0 signal rising edge */ __IO uint32_t CAP0FE : 2; /*!< Capture/Reset on CT16Bn_CAP0 signal falling edge */ __IO uint32_t CAP0IE : 1; /*!< Interrupt on CT16Bn_CAP0 signal event: a CAP0 load due to a CT16Bn_CAP0 signal event will generate an interrupt. */ __IO uint32_t CAP0EN : 2; /*!< CAP0 function enable bit */ } CAPCTRL_b; /*!< BitSize */ }; union { __I uint32_t CAP0; /*!< Offset:0x2C CT16Bn CAP0 Register */ struct { __I uint32_t CAP0 : 16; /*!< Timer counter capture value */ } CAP0_b; /*!< BitSize */ }; union { __IO uint32_t EM; /*!< Offset:0x30 CT16Bn External Match Register */ struct { __IO uint32_t EM0 : 1; /*!< When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ uint32_t : 3; __IO uint32_t EMC0 : 2; /*!< CT16Bn_PWM0 functionality */ } EM_b; /*!< BitSize */ }; union { __IO uint32_t PWMCTRL; /*!< Offset:0x34 CT16Bn PWM Control Register */ struct { __IO uint32_t PWM0EN : 1; /*!< PWM0 enable */ uint32_t : 19; __IO uint32_t PWM0IOEN : 1; /*!< CT16Bn_PWM0/GPIO selection */ } PWMCTRL_b; /*!< BitSize */ }; union { __I uint32_t RIS; /*!< Offset:0x38 CT16Bn Raw Interrupt Status Register */ struct { __I uint32_t MR0IF : 1; /*!< Match channel 0 interrupt flag */ __I uint32_t MR1IF : 1; /*!< Match channel 1 interrupt flag */ __I uint32_t MR2IF : 1; /*!< Match channel 2 interrupt flag */ __I uint32_t MR3IF : 1; /*!< Match channel 3 interrupt flag */ __I uint32_t CAP0IF : 1; /*!< Capture channel 0 interrupt flag */ } RIS_b; /*!< BitSize */ }; union { __O uint32_t IC; /*!< Offset:0x3C CT16Bn Interrupt Clear Register */ struct { __O uint32_t MR0IC : 1; /*!< MR0IF clear bit */ __O uint32_t MR1IC : 1; /*!< MR1IF clear bit */ __O uint32_t MR2IC : 1; /*!< MR2IF clear bit */ __O uint32_t MR3IC : 1; /*!< MR3IF clear bit */ __O uint32_t CAP0IC : 1; /*!< CAP0IF clear bit */ } IC_b; /*!< BitSize */ }; } SN_CT16B0_Type; /* ================================================================================ */ /* ================ SN_CT32B0 ================ */ /* ================================================================================ */ /** * @brief 32-bit Timer 0 with Capture function (SN_CT32B0) */ typedef struct { /*!< SN_CT32B0 Structure */ union { __IO uint32_t TMRCTRL; /*!< Offset:0x00 CT32Bn Timer Control Register */ struct { __IO uint32_t CEN : 1; /*!< Counter Enable */ __IO uint32_t CRST : 1; /*!< Counter Reset */ } TMRCTRL_b; /*!< BitSize */ }; __IO uint32_t TC; /*!< Offset:0x04 CT32Bn Timer Counter Register */ __IO uint32_t PRE; /*!< Offset:0x08 CT32Bn Prescale Register */ __IO uint32_t PC; /*!< Offset:0x0C CT32Bn Prescale Counter Register */ union { __IO uint32_t CNTCTRL; /*!< Offset:0x10 CT32Bn Counter Control Register */ struct { __IO uint32_t CTM : 2; /*!< Counter/Timer Mode */ __IO uint32_t CIS : 2; /*!< Counter Input Select */ } CNTCTRL_b; /*!< BitSize */ }; union { __IO uint32_t MCTRL; /*!< Offset:0x14 CT32Bn Match Control Register */ struct { __IO uint32_t MR0IE : 1; /*!< Enable generating an interrupt when MR0 matches TC */ __IO uint32_t MR0RST : 1; /*!< Enable reset TC when MR0 matches TC */ __IO uint32_t MR0STOP : 1; /*!< Stop TC and PC and clear CEN bit when MR0 matches TC */ __IO uint32_t MR1IE : 1; /*!< Enable generating an interrupt when MR1 matches TC */ __IO uint32_t MR1RST : 1; /*!< Enable reset TC when MR1 matches TC */ __IO uint32_t MR1STOP : 1; /*!< Stop TC and PC and clear CEN bit when MR1 matches TC */ __IO uint32_t MR2IE : 1; /*!< Enable generating an interrupt when MR2 matches TC */ __IO uint32_t MR2RST : 1; /*!< Enable reset TC when MR2 matches TC */ __IO uint32_t MR2STOP : 1; /*!< Stop TC and PC and clear CEN bit when MR2 matches TC */ __IO uint32_t MR3IE : 1; /*!< Enable generating an interrupt when MR3 matches TC */ __IO uint32_t MR3RST : 1; /*!< Enable reset TC when MR3 matches TC */ __IO uint32_t MR3STOP : 1; /*!< Stop TC and PC and clear CEN bit when MR3 matches TC */ } MCTRL_b; /*!< BitSize */ }; __IO uint32_t MR0; /*!< Offset:0x18 CT32Bn MR0 Register */ __IO uint32_t MR1; /*!< Offset:0x1C CT32Bn MR1 Register */ __IO uint32_t MR2; /*!< Offset:0x20 CT32Bn MR2 Register */ __IO uint32_t MR3; /*!< Offset:0x24 CT32Bn MR3 Register */ union { __IO uint32_t CAPCTRL; /*!< Offset:0x28 CT32Bn Capture Control Register */ struct { __IO uint32_t CAP0RE : 2; /*!< Capture/Reset on CT32Bn_CAP0 signal rising edge. */ __IO uint32_t CAP0FE : 2; /*!< Capture/Reset on CT32Bn_CAP0 signal falling edge. */ __IO uint32_t CAP0IE : 1; /*!< Interrupt on CT32Bn_CAP0 signal event */ __IO uint32_t CAP0EN : 2; /*!< Capture 0 function enable bit */ } CAPCTRL_b; /*!< BitSize */ }; __I uint32_t CAP0; /*!< Offset:0x2C CT32Bn CAP0 Register */ union { __IO uint32_t EM; /*!< Offset:0x30 CT32Bn External Match Register */ struct { __IO uint32_t EM0 : 1; /*!< When the TC matches MR0, this bit will act according to EMC0[1:0], and also drive the state of CT16Bn_PWM0 output. */ __IO uint32_t EM1 : 1; /*!< When the TC matches MR1, this bit will act according to EMC1[1:0], and also drive the state of CT16Bn_PWM1 output. */ uint32_t : 2; __IO uint32_t EMC0 : 2; /*!< CT32Bn_PWM0 functionality */ __IO uint32_t EMC1 : 2; /*!< CT32Bn_PWM1 functionality */ } EM_b; /*!< BitSize */ }; union { __IO uint32_t PWMCTRL; /*!< Offset:0x34 CT32Bn PWM Control Register */ struct { __IO uint32_t PWM0EN : 1; /*!< PWM0 enable */ __IO uint32_t PWM1EN : 1; /*!< PWM1 enable */ uint32_t : 18; __IO uint32_t PWM0IOEN : 1; /*!< CT32Bn_PWM0/GPIO selection */ __IO uint32_t PWM1IOEN : 1; /*!< CT16Bn_PWM1/GPIO selection */ } PWMCTRL_b; /*!< BitSize */ }; union { __I uint32_t RIS; /*!< Offset:0x38 CT32Bn Raw Interrupt Status Register */ struct { __I uint32_t MR0IF : 1; /*!< Match channel 0 interrupt flag */ __I uint32_t MR1IF : 1; /*!< Match channel 1 interrupt flag */ __I uint32_t MR2IF : 1; /*!< Match channel 2 interrupt flag */ __I uint32_t MR3IF : 1; /*!< Match channel 3 interrupt flag */ __I uint32_t CAP0IF : 1; /*!< Capture channel 0 interrupt flag */ } RIS_b; /*!< BitSize */ }; union { __O uint32_t IC; /*!< Offset:0x3C CT32Bn Interrupt Clear Register */ struct { __O uint32_t MR0IC : 1; /*!< MR0IF clear bit */ __O uint32_t MR1IC : 1; /*!< MR1IF clear bit */ __O uint32_t MR2IC : 1; /*!< MR2IF clear bit */ __O uint32_t MR3IC : 1; /*!< MR3IF clear bit */ __O uint32_t CAP0IC : 1; /*!< CAP0IF clear bit */ } IC_b; /*!< BitSize */ }; } SN_CT32B0_Type; /* ================================================================================ */ /* ================ SN_PMU ================ */ /* ================================================================================ */ /** * @brief Power Management Unit (SN_PMU) */ typedef struct { /*!< SN_PMU Structure */ union { __IO uint32_t BKP0; /*!< Offset:0x00 PMU Backup Register 0 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP0_b; /*!< BitSize */ }; union { __IO uint32_t BKP1; /*!< Offset:0x04 PMU Backup Register 1 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP1_b; /*!< BitSize */ }; union { __IO uint32_t BKP2; /*!< Offset:0x08 PMU Backup Register 2 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP2_b; /*!< BitSize */ }; union { __IO uint32_t BKP3; /*!< Offset:0x0C PMU Backup Register 3 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP3_b; /*!< BitSize */ }; union { __IO uint32_t BKP4; /*!< Offset:0x10 PMU Backup Register 4 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP4_b; /*!< BitSize */ }; union { __IO uint32_t BKP5; /*!< Offset:0x14 PMU Backup Register 5 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP5_b; /*!< BitSize */ }; union { __IO uint32_t BKP6; /*!< Offset:0x18 PMU Backup Register 6 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP6_b; /*!< BitSize */ }; union { __IO uint32_t BKP7; /*!< Offset:0x1C PMU Backup Register 7 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP7_b; /*!< BitSize */ }; union { __IO uint32_t BKP8; /*!< Offset:0x20 PMU Backup Register 8 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP8_b; /*!< BitSize */ }; union { __IO uint32_t BKP9; /*!< Offset:0x24 PMU Backup Register 9 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP9_b; /*!< BitSize */ }; union { __IO uint32_t BKP10; /*!< Offset:0x28 PMU Backup Register 10 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP10_b; /*!< BitSize */ }; union { __IO uint32_t BKP11; /*!< Offset:0x2C PMU Backup Register 11 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP11_b; /*!< BitSize */ }; union { __IO uint32_t BKP12; /*!< Offset:0x30 PMU Backup Register 12 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP12_b; /*!< BitSize */ }; union { __IO uint32_t BKP13; /*!< Offset:0x34 PMU Backup Register 13 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP13_b; /*!< BitSize */ }; union { __IO uint32_t BKP14; /*!< Offset:0x38 PMU Backup Register 14 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP14_b; /*!< BitSize */ }; union { __IO uint32_t BKP15; /*!< Offset:0x3C PMU Backup Register 15 */ struct { __IO uint32_t BACKUPDATA : 8; /*!< Data retained during Deep power-down mode */ } BKP15_b; /*!< BitSize */ }; union { __IO uint32_t CTRL; /*!< Offset:0x40 PMU Control Register */ struct { __IO uint32_t DPDEN : 1; /*!< Deep Power-down mode Enable */ __IO uint32_t DSLEEPEN : 1; /*!< Deep Sleep mode Enable */ __IO uint32_t SLEEPEN : 1; /*!< Sleep mode Enable */ } CTRL_b; /*!< BitSize */ }; } SN_PMU_Type; /* ================================================================================ */ /* ================ SN_SSP0 ================ */ /* ================================================================================ */ /** * @brief SSP0 (SN_SSP0) */ typedef struct { /*!< SN_SSP0 Structure */ union { __IO uint32_t CTRL0; /*!< Offset:0x00 SSPn Control Register 0 */ struct { __IO uint32_t SSPEN : 1; /*!< SSP enable */ __IO uint32_t LOOPBACK : 1; /*!< Loopback mode enable */ __IO uint32_t SDODIS : 1; /*!< Slave data out disable */ __IO uint32_t MS : 1; /*!< Master/Slave selection */ __IO uint32_t FORMAT : 1; /*!< Interface format */ uint32_t : 1; __O uint32_t FRESET : 2; /*!< SSP FSM and FIFO Reset */ __IO uint32_t DL : 4; /*!< Data length = DL[3:0]+1 */ __IO uint32_t TXFIFOTH : 3; /*!< TX FIFO Threshold level */ __IO uint32_t RXFIFOTH : 3; /*!< Rx FIFO Threshold level */ __IO uint32_t SELDIS : 1; /*!< Auto-SEL disable bit */ __IO uint32_t SELCTRL : 1; /*!< Source for SEL pin */ } CTRL0_b; /*!< BitSize */ }; union { __IO uint32_t CTRL1; /*!< Offset:0x04 SSPn Control Register 1 */ struct { __IO uint32_t MLSB : 1; /*!< MSB/LSB seletion */ __IO uint32_t CPOL : 1; /*!< Clock priority selection */ __IO uint32_t CPHA : 1; /*!< Clock phase of edge sampling */ } CTRL1_b; /*!< BitSize */ }; union { __IO uint32_t CLKDIV; /*!< Offset:0x08 SSPn Clock Divider Register */ struct { __IO uint32_t DIV : 8; /*!< SSPn SCK=SSPn_PCLK/(2*DIV+2) */ } CLKDIV_b; /*!< BitSize */ }; union { __I uint32_t STAT; /*!< Offset:0x0C SSPn Status Register */ struct { __I uint32_t TX_EMPTY : 1; /*!< TX FIFO empty flag */ __I uint32_t TX_FULL : 1; /*!< TX FIFO full flag */ __I uint32_t RX_EMPTY : 1; /*!< RX FIFO empty flag */ __I uint32_t RX_FULL : 1; /*!< RX FIFO full flag */ __I uint32_t BUSY : 1; /*!< Busy flag */ __I uint32_t TXFIFOTHF : 1; /*!< TX FIFO threshold flag */ __I uint32_t RXFIFOTHF : 1; /*!< RX FIFO threshold flag */ } STAT_b; /*!< BitSize */ }; union { __IO uint32_t IE; /*!< Offset:0x10 SSPn Interrupt Enable Register */ struct { __IO uint32_t RXOVFIE : 1; /*!< RX FIFO overflow interrupt enable */ __IO uint32_t RXTOIE : 1; /*!< RX time-out interrupt enable */ __IO uint32_t RXFIFOTHIE : 1; /*!< RX FIFO threshold interrupt enable */ __IO uint32_t TXFIFOTHIE : 1; /*!< TX FIFO threshold interrupt enable */ } IE_b; /*!< BitSize */ }; union { __I uint32_t RIS; /*!< Offset:0x14 SSPn Raw Interrupt Status Register */ struct { __I uint32_t RXOVFIF : 1; /*!< RX FIFO overflow interrupt flag */ __I uint32_t RXTOIF : 1; /*!< RX time-out interrupt flag */ __I uint32_t RXFIFOTHIF : 1; /*!< RX FIFO threshold interrupt flag */ __I uint32_t TXFIFOTHIF : 1; /*!< TX FIFO threshold interrupt flag */ } RIS_b; /*!< BitSize */ }; union { __O uint32_t IC; /*!< Offset:0x18 SSPn Interrupt Clear Register */ struct { __O uint32_t RXOVFIC : 1; /*!< RX FIFO overflow flag clear */ __O uint32_t RXTOIC : 1; /*!< RX time-out interrupt flag clear */ __O uint32_t RXFIFOTHIC : 1; /*!< RX Interrupt flag Clear */ __O uint32_t TXFIFOTHIC : 1; /*!< TX Interrupt flag Clear */ } IC_b; /*!< BitSize */ }; union { __IO uint32_t DATA; /*!< Offset:0x1C SSPn Data Register */ struct { __IO uint32_t Data : 16; /*!< Data */ } DATA_b; /*!< BitSize */ }; } SN_SSP0_Type; /* ================================================================================ */ /* ================ SN_I2C0 ================ */ /* ================================================================================ */ /** * @brief I2C0 (SN_I2C0) */ typedef struct { /*!< SN_I2C0 Structure */ union { __IO uint32_t CTRL; /*!< Offset:0x00 I2Cn Control Register */ struct { uint32_t : 1; __IO uint32_t NACK : 1; /*!< NACK assert flag */ __IO uint32_t ACK : 1; /*!< ACK assert flag */ uint32_t : 1; __IO uint32_t STO : 1; /*!< STOP assert flag */ __IO uint32_t STA : 1; /*!< START assert flag */ uint32_t : 2; __IO uint32_t I2CEN : 1; /*!< I2Cn interface enable */ } CTRL_b; /*!< BitSize */ }; union { __IO uint32_t STAT; /*!< Offset:0x04 I2Cn Status Register */ struct { __I uint32_t RX_DN : 1; /*!< RX done status */ __I uint32_t ACK_STAT : 1; /*!< ACK done status */ __I uint32_t NACK_STAT : 1; /*!< NACK done status */ __I uint32_t STOP_DN : 1; /*!< STOP done status */ __I uint32_t START_DN : 1; /*!< START done status */ __I uint32_t I2C_MST : 1; /*!< I2C master/slave status */ __I uint32_t SLV_RX_HIT : 1; /*!< Slave RX address hit flag */ __I uint32_t SLV_TX_HIT : 1; /*!< Slave TX address hit flag */ __I uint32_t LOST_ARB : 1; /*!< Lost arbitration status */ __I uint32_t TIMEOUT : 1; /*!< Time-out status */ uint32_t : 5; __IO uint32_t I2CIF : 1; /*!< I2C interrupt flag */ } STAT_b; /*!< BitSize */ }; union { __IO uint32_t TXDATA; /*!< Offset:0x08 I2Cn TX Data Register */ struct { __IO uint32_t Data : 8; /*!< TX Data */ } TXDATA_b; /*!< BitSize */ }; union { __I uint32_t RXDATA; /*!< Offset:0x0C I2Cn RX Data Register */ struct { __I uint32_t Data : 8; /*!< RX Data received when RX_DN=1 */ } RXDATA_b; /*!< BitSize */ }; union { __IO uint32_t SLVADDR0; /*!< Offset:0x10 I2Cn Slave Address 0 Register */ struct { __IO uint32_t ADDR : 10; /*!< I2Cn slave address 0 */ uint32_t : 20; __IO uint32_t GCEN : 1; /*!< General call address enable */ __IO uint32_t ADD_MODE : 1; /*!< Slave address mode */ } SLVADDR0_b; /*!< BitSize */ }; union { __IO uint32_t SLVADDR1; /*!< Offset:0x14 I2Cn Slave Address 1 Register */ struct { __IO uint32_t ADDR : 10; /*!< I2Cn slave address 1 */ } SLVADDR1_b; /*!< BitSize */ }; union { __IO uint32_t SLVADDR2; /*!< Offset:0x18 I2Cn Slave Address 2 Register */ struct { __IO uint32_t ADDR : 10; /*!< I2Cn slave address 2 */ } SLVADDR2_b; /*!< BitSize */ }; union { __IO uint32_t SLVADDR3; /*!< Offset:0x1C I2Cn Slave Address 3 Register */ struct { __IO uint32_t ADDR : 10; /*!< I2Cn slave address 3 */ } SLVADDR3_b; /*!< BitSize */ }; union { __IO uint32_t SCLHT; /*!< Offset:0x20 I2Cn SCL High Time Register */ struct { __IO uint32_t SCLH : 8; /*!< SCLn High period time=(SCLHT+1)*I2Cn_PCLK cycle */ } SCLHT_b; /*!< BitSize */ }; union { __IO uint32_t SCLLT; /*!< Offset:0x24 I2Cn SCL Low Time Register */ struct { __IO uint32_t SCLL : 8; /*!< SCLn Low period time=(SCLLT+1)*I2Cn_PCLK cycle */ } SCLLT_b; /*!< BitSize */ }; __I uint32_t RESERVED0; union { __IO uint32_t TOCTRL; /*!< Offset:0x2C I2Cn Timeout Control Register */ struct { __IO uint32_t TO : 16; /*!< Timeout period time = TO*I2Cn_PCLK cycle */ } TOCTRL_b; /*!< BitSize */ }; union { __IO uint32_t MMCTRL; /*!< Offset:0x30 I2Cn Monitor Mode Control Register */ struct { __IO uint32_t MMEN : 1; /*!< Monitor mode enable */ __IO uint32_t SCLOEN : 1; /*!< SCLn output enable */ __IO uint32_t MATCH_ALL : 1; /*!< Match address selection */ } MMCTRL_b; /*!< BitSize */ }; } SN_I2C0_Type; /* ================================================================================ */ /* ================ SN_UART0 ================ */ /* ================================================================================ */ /** * @brief UART0 (SN_UART0) */ typedef struct { /*!< SN_UART0 Structure */ union { union { __IO uint32_t DLL; /*!< Offset:0x00 UARTn Divisor Latch LSB Register */ struct { __IO uint32_t DLL : 8; /*!< DLL and DLM register determines the baud rate of UARTn */ } DLL_b; /*!< BitSize */ }; union { __O uint32_t TH; /*!< Offset:0x00 UARTn Transmit Holding Register */ struct { __O uint32_t TH : 8; /*!< The oldest byte to be transmitted in UART TX FIFO when transmitter is available */ } TH_b; /*!< BitSize */ }; union { __I uint32_t RB; /*!< Offset:0x00 UARTn Receiver Buffer Register */ struct { __I uint32_t RB : 8; /*!< The oldest received byte in UART RX FIFO */ } RB_b; /*!< BitSize */ }; }; union { union { __IO uint32_t IE; /*!< Offset:0x04 UARTn Interrupt Enable Register */ struct { __IO uint32_t RDAIE : 1; /*!< RDA interrupt enable */ __IO uint32_t THREIE : 1; /*!< THRE interrupt enable */ __IO uint32_t RLSIE : 1; /*!< RLS interrupt enable */ uint32_t : 1; __IO uint32_t TEMTIE : 1; /*!< TEMT interrupt enable */ uint32_t : 3; __IO uint32_t ABEOIE : 1; /*!< ABE0 interrupt enable */ __IO uint32_t ABTOIE : 1; /*!< ABT0 interrupt enable */ } IE_b; /*!< BitSize */ }; union { __IO uint32_t DLM; /*!< Offset:0x04 UARTn Divisor Latch MSB Register */ struct { __IO uint32_t DLM : 8; /*!< DLL and DLM register determines the baud rate of UARTn */ } DLM_b; /*!< BitSize */ }; }; union { union { __O uint32_t FIFOCTRL; /*!< Offset:0x08 UARTn FIFO Control Register */ struct { __O uint32_t FIFOEN : 1; /*!< FIFO enable */ __O uint32_t RXFIFORST: 1; /*!< RX FIFO reset */ __O uint32_t TXFIFORST: 1; /*!< TX FIFO reset */ uint32_t : 3; __O uint32_t RXTL : 2; /*!< RX trigger level */ } FIFOCTRL_b; /*!< BitSize */ }; union { __I uint32_t II; /*!< Offset:0x08 UARTn Interrupt Identification Register */ struct { __I uint32_t INTSTATUS: 1; /*!< Interrupt status */ __I uint32_t INTID : 3; /*!< Interrupt ID of RX FIFO */ uint32_t : 2; __I uint32_t FIFOEN : 2; /*!< Equal to FIFOEN bits in UARTn_FIFOCTRL register */ __I uint32_t ABEOIF : 1; /*!< ABEO interrupt flag */ __I uint32_t ABTOIF : 1; /*!< ABTO interrupt flag */ } II_b; /*!< BitSize */ }; }; union { __IO uint32_t LC; /*!< Offset:0x0C UARTn Line Control Register */ struct { __IO uint32_t WLS : 2; /*!< Word length selection */ __IO uint32_t SBS : 1; /*!< Stop bit selection */ __IO uint32_t PE : 1; /*!< Parity enable */ __IO uint32_t PS : 2; /*!< Parity selection */ __IO uint32_t BC : 1; /*!< Break control */ __IO uint32_t DLAB : 1; /*!< Divisor Latch access */ } LC_b; /*!< BitSize */ }; __I uint32_t RESERVED0; union { __I uint32_t LS; /*!< Offset:0x14 UARTn Line Status Register */ struct { __I uint32_t RDR : 1; /*!< Receiver data ready flag */ __I uint32_t OE : 1; /*!< Overrun error flag */ __I uint32_t PE : 1; /*!< Parity error flag */ __I uint32_t FE : 1; /*!< Framing error flag */ __I uint32_t BI : 1; /*!< Break interrupt flag */ __I uint32_t THRE : 1; /*!< THR empty flag */ __I uint32_t TEMT : 1; /*!< Transmitter empty flag */ __I uint32_t RXFE : 1; /*!< Receiver FIFO error flag */ } LS_b; /*!< BitSize */ }; __I uint32_t RESERVED1; union { __IO uint32_t SP; /*!< Offset:0x1C UARTn Scratch Pad Register */ struct { __IO uint32_t PAD : 8; /*!< Pad informaton */ } SP_b; /*!< BitSize */ }; union { __IO uint32_t ABCTRL; /*!< Offset:0x20 UARTn Auto-baud Control Register */ struct { __IO uint32_t START : 1; /*!< Auto-baud run bit */ __IO uint32_t MODE : 1; /*!< Auto-baud mode selection */ __IO uint32_t AUTORESTART: 1; /*!< Restart mode selection */ uint32_t : 5; __O uint32_t ABEOIFC : 1; /*!< Clear ABEOIF flag */ __O uint32_t ABTOIFC : 1; /*!< Clear ABTOIF flag */ } ABCTRL_b; /*!< BitSize */ }; __I uint32_t RESERVED2; union { __IO uint32_t FD; /*!< Offset:0x28 UARTn Fractional Divider Register */ struct { __IO uint32_t DIVADDVAL : 4; /*!< Baud rate generation prescaler divisor value */ __IO uint32_t MULVAL : 4; /*!< Baud rate generation prescaler multiplier value */ __IO uint32_t OVER8 : 1; /*!< Oversampling value */ } FD_b; /*!< BitSize */ }; __I uint32_t RESERVED3; union { __IO uint32_t CTRL; /*!< Offset:0x30 UARTn Control Register */ struct { __IO uint32_t UARTEN : 1; /*!< UART enable */ uint32_t : 5; __IO uint32_t RXEN : 1; /*!< RX enable */ __IO uint32_t TXEN : 1; /*!< TX enable */ } CTRL_b; /*!< BitSize */ }; union { __IO uint32_t HDEN; /*!< Offset:0x34 UARTn Control Register */ struct { __IO uint32_t HDEN : 1; /*!< Half-duplex mode enable */ } HDEN_b; /*!< BitSize */ }; } SN_UART0_Type; /* ================================================================================ */ /* ================ SN_I2S ================ */ /* ================================================================================ */ /** * @brief I2S (SN_I2S) */ typedef struct { /*!< SN_I2S Structure */ union { __IO uint32_t CTRL; /*!< Offset:0x00 I2S Control Register */ struct { __IO uint32_t START : 1; /*!< Start Transmit/Receive */ __IO uint32_t MUTE : 1; /*!< Mute enable */ __IO uint32_t MONO : 1; /*!< Mono/stereo selection */ __IO uint32_t MS : 1; /*!< Master/Slave selection bit */ __IO uint32_t FORMAT : 2; /*!< I2S operation format */ __IO uint32_t TXEN : 1; /*!< Transmit enable bit */ __O uint32_t RXEN : 1; /*!< Receiver enable bit */ __O uint32_t CLRTXFIFO : 1; /*!< Clear I2S TX FIFO */ __O uint32_t CLRRXFIFO : 1; /*!< Clear I2S RX FIFO */ __IO uint32_t DL : 2; /*!< Data length */ __IO uint32_t TXFIFOTH : 3; /*!< Tx FIFO threshold level */ uint32_t : 1; __IO uint32_t RXFIFOTH : 3; /*!< Rx FIFO threshold level */ uint32_t : 1; __IO uint32_t CHLENGTH : 5; /*!< Bit number of single channel */ uint32_t : 5; __IO uint32_t I2SMOD : 1; /*!< I2S mode select bit */ __IO uint32_t I2SEN : 1; /*!< I2S enable */ } CTRL_b; /*!< BitSize */ }; union { __IO uint32_t CLK; /*!< Offset:0x04 I2S Clock Register */ struct { __IO uint32_t MCLKDIV : 3; /*!< MCLK divider */ __IO uint32_t MCLKOEN : 1; /*!< MLCK output enable */ __IO uint32_t MCLKSEL : 1; /*!< MLCK source selection */ uint32_t : 3; __IO uint32_t BCLKDIV : 8; /*!< BCLK divider */ } CLK_b; /*!< BitSize */ }; union { __I uint32_t STATUS; /*!< Offset:0x08 I2S Status Register */ struct { __I uint32_t I2SINT : 1; /*!< I2S interrupt flag */ __I uint32_t RIGHTCH : 1; /*!< Current channel status */ uint32_t : 4; __I uint32_t TXFIFOTHF : 1; /*!< TX FIFO threshold flag */ __I uint32_t RXFIFOTHF : 1; /*!< RX FIFO threshold flag */ __I uint32_t TXFIFOFULL : 1; /*!< TX FIFO full flag */ __I uint32_t RXFIFOFULL : 1; /*!< RX FIFO full flag */ __I uint32_t TXFIFOEMPTY: 1; /*!< TX FIFO empty flag */ __I uint32_t RXFIFOEMPTY: 1; /*!< RX FIFO empty flag */ __I uint32_t TXFIFOLV : 4; /*!< TX FIFO used level */ uint32_t : 1; __I uint32_t RXFIFOLV : 4; /*!< RX FIFO used level */ } STATUS_b; /*!< BitSize */ }; union { __IO uint32_t IE; /*!< Offset:0x0C I2S Interrupt Enable Register */ struct { uint32_t : 4; __IO uint32_t TXFIFOOVFIEN: 1; /*!< TX FIFO overflow interrupt enable */ __IO uint32_t RXFIFOUDFIEN: 1; /*!< RX FIFO underflow interrupt enable */ __IO uint32_t TXFIFOTHIEN: 1; /*!< TX FIFO threshold interrupt enable */ __IO uint32_t RXFIFOTHIEN: 1; /*!< RX FIFO threshold interrupt enable */ } IE_b; /*!< BitSize */ }; union { __I uint32_t RIS; /*!< Offset:0x10 I2S Raw Interrupt Status Register */ struct { uint32_t : 4; __I uint32_t TXFIFOOVIF : 1; /*!< TX FIFO overflow interrupt flag */ __I uint32_t RXFIFOUDIF : 1; /*!< RX FIFO underflow interrupt flag */ __I uint32_t TXFIFOTHIF : 1; /*!< TX FIFO threshold interrupt flag */ __I uint32_t RXFIFOTHIF : 1; /*!< RX FIFO threshold interrupt flag */ } RIS_b; /*!< BitSize */ }; union { __O uint32_t IC; /*!< Offset:0x14 I2S Interrupt Clear Register */ struct { uint32_t : 4; __O uint32_t TXFIFOOVIC : 1; /*!< TX FIFO overflow interrupt clear */ __O uint32_t RXFIFOUDIC : 1; /*!< RX FIFO underflow interrupt clear */ __O uint32_t TXFIFOTHIC : 1; /*!< TX FIFO threshold interrupt clear */ __O uint32_t RXFIFOTHIC : 1; /*!< RX FIFO threshold interrupt clear */ } IC_b; /*!< BitSize */ }; __I uint32_t RXFIFO; /*!< Offset:0x18 UARTn RX FIFO Register */ __O uint32_t TXFIFO; /*!< Offset:0x1C UARTn TX FIFO Register */ } SN_I2S_Type; /* ================================================================================ */ /* ================ SN_ADC ================ */ /* ================================================================================ */ /** * @brief Codec ADC Control Registers (SN_ADC) */ typedef struct { /*!< SN_ADC Structure */ __I uint32_t RESERVED0[336]; union { __IO uint32_t SET1; /*!< Offset:0x540 ADC Setting 1 Register */ struct { __IO uint32_t LB_H : 8; /*!< AGC Control Low bound setting : High byte */ } SET1_b; /*!< BitSize */ }; __I uint32_t RESERVED1[3]; union { __IO uint32_t SET2; /*!< Offset:0x550 ADC Setting 2 Register */ struct { __IO uint32_t LB_L : 8; /*!< AGC Control Low bound setting : Low byte */ } SET2_b; /*!< BitSize */ }; __I uint32_t RESERVED2[3]; union { __IO uint32_t SET3; /*!< Offset:0x560 ADC Setting 3 Register */ struct { __IO uint32_t HB_H : 8; /*!< AGC Control High bound setting : High byte */ } SET3_b; /*!< BitSize */ }; __I uint32_t RESERVED3[3]; union { __IO uint32_t SET4; /*!< Offset:0x570 ADC Setting 4 Register */ struct { __IO uint32_t HB_L : 8; /*!< AGC Control High bound setting : Low byte */ } SET4_b; /*!< BitSize */ }; __I uint32_t RESERVED4[3]; union { __IO uint32_t SET5; /*!< Offset:0x580 ADC Setting 5 Register */ struct { __IO uint32_t NOR_POD : 4; /*!< AGC Control Gain update period at normal mode */ } SET5_b; /*!< BitSize */ }; __I uint32_t RESERVED5[3]; union { __IO uint32_t SET6; /*!< Offset:0x590 ADC Setting 6 Register */ struct { __IO uint32_t MUTE_POD : 4; /*!< AGC Control Gain update period at mute mode */ } SET6_b; /*!< BitSize */ }; __I uint32_t RESERVED6[3]; union { __IO uint32_t SET7; /*!< Offset:0x5A0 ADC Setting 7 Register */ struct { __IO uint32_t SEARCH_TH_H: 8; /*!< AGC Control Threshold for activating : High byte */ } SET7_b; /*!< BitSize */ }; __I uint32_t RESERVED7[3]; union { __IO uint32_t SET8; /*!< Offset:0x5B0 ADC Setting 8 Register */ struct { __IO uint32_t SEARCH_TH_L: 8; /*!< AGC Control Threshold for activating : Low byte */ } SET8_b; /*!< BitSize */ }; __I uint32_t RESERVED8[3]; union { __IO uint32_t SET9; /*!< Offset:0x5C0 ADC Setting 9 Register */ struct { __IO uint32_t MUTE_TH_H : 8; /*!< AGC Control Threshold for inactivating : High byte */ } SET9_b; /*!< BitSize */ }; __I uint32_t RESERVED9[3]; union { __IO uint32_t SET10; /*!< Offset:0x5D0 ADC Setting 10 Register */ struct { __IO uint32_t MUTE_TH_L : 8; /*!< AGC Control Threshold for inactivating : Low byte */ } SET10_b; /*!< BitSize */ }; __I uint32_t RESERVED10[3]; union { __IO uint32_t SET11; /*!< Offset:0x5E0 ADC Setting 11 Register */ struct { __IO uint32_t MUTE_CAL_POD: 4; /*!< AGC Control Period for inactivating */ } SET11_b; /*!< BitSize */ }; __I uint32_t RESERVED11[3]; union { __IO uint32_t SET12; /*!< Offset:0x5F0 ADC Setting 12 Register */ struct { __IO uint32_t SAT_TH : 4; /*!< AGC Control Threshold for ADC saturation */ } SET12_b; /*!< BitSize */ }; __I uint32_t RESERVED12[3]; union { __IO uint32_t SET13; /*!< Offset:0x600 ADC Setting 13 Register */ struct { __IO uint32_t SAT_POD : 4; /*!< AGC Control Period for ADC saturation */ } SET13_b; /*!< BitSize */ }; __I uint32_t RESERVED13[3]; union { __IO uint32_t SET14; /*!< Offset:0x610 ADC Setting 14 Register */ struct { __IO uint32_t PGA_SET_VAL: 5; /*!< AGC Control PGA setting value at normal mode(1.5dB/step) */ __IO uint32_t BOOST_SET_VAL: 2; /*!< AGC Control Boost setting value at normal mode */ __IO uint32_t AGC_OFF : 1; /*!< AGC Control function */ } SET14_b; /*!< BitSize */ }; __I uint32_t RESERVED14[3]; union { __IO uint32_t SET15; /*!< Offset:0x620 ADC Setting 15 Register */ struct { __IO uint32_t IWL : 2; /*!< World length of DAI */ __IO uint32_t ACTIVE : 1; /*!< Digital Audio Interface Control */ } SET15_b; /*!< BitSize */ }; __I uint32_t RESERVED15[3]; union { __IO uint32_t SET16; /*!< Offset:0x630 ADC Setting 16 Register */ struct { __IO uint32_t PGA : 5; /*!< PGA setting value(1.5dB/step) */ __IO uint32_t BOOST : 2; /*!< Boost setting value */ } SET16_b; /*!< BitSize */ }; __I uint32_t RESERVED16[7]; union { __IO uint32_t SET18; /*!< Offset:0x650 ADC Setting 18 Register */ struct { __IO uint32_t MUTE_CTRL : 4; /*!< Digital volume attenuation control at mute mode */ __IO uint32_t VOL_CTRL : 4; /*!< Digital volume attenuation control at normal mode */ } SET18_b; /*!< BitSize */ }; __I uint32_t RESERVED17[3]; union { __IO uint32_t SET19; /*!< Offset:0x660 ADC Setting 19 Register */ struct { __IO uint32_t PGA_MUTE_VAL: 5; /*!< PGA setting value at mute mode(1.5dB/step) */ __IO uint32_t BOOST_MUTE_VAL: 2; /*!< Boost setting value at mute mode */ } SET19_b; /*!< BitSize */ }; __I uint32_t RESERVED18[3]; union { __IO uint32_t SET20; /*!< Offset:0x670 ADC Setting 20 Register */ struct { __IO uint32_t VOL_MUTE_POD_L: 4; /*!< Period for Digital volume attenuation at mute mode */ __IO uint32_t VOL_MUTE_POD_H: 4; /*!< Period for Digital volume attenuation at normal mode */ } SET20_b; /*!< BitSize */ }; __I uint32_t RESERVED19[15]; union { __IO uint32_t SET21; /*!< Offset:0x6B0 ADC Setting 21 Register */ struct { uint32_t : 4; __IO uint32_t PGA_EN : 1; /*!< PGA power-on enable */ __IO uint32_t MICBT_EN : 1; /*!< MICBOOST power-on enable */ uint32_t : 1; __IO uint32_t ADC_EN : 1; /*!< ADC power-on enable */ } SET21_b; /*!< BitSize */ }; __I uint32_t RESERVED20[3]; union { __IO uint32_t SET22; /*!< Offset:0x6C0 ADC Setting 22 Register */ struct { __IO uint32_t CK_EN : 1; /*!< CKGEN enable */ __IO uint32_t MICB_EN : 1; /*!< Microphone bias enable */ __IO uint32_t VREF_EN : 1; /*!< VREF circuit enable */ __IO uint32_t IREF_EN : 1; /*!< IREF circuit enable */ } SET22_b; /*!< BitSize */ }; __I uint32_t RESERVED21[3]; union { __IO uint32_t SET23; /*!< Offset:0x6D0 ADC Setting 23 Register */ struct { __IO uint32_t SEL_MIX_MIC: 1; /*!< Microphone input path to mixer enable */ uint32_t : 1; __IO uint32_t SEL_MIC : 1; /*!< P1.7/MIC_P and P1.8/MIC_N function selection */ uint32_t : 1; __IO uint32_t SEL_MICB : 1; /*!< Microphone Bias Output select */ } SET23_b; /*!< BitSize */ }; __I uint32_t RESERVED22[3]; union { __I uint32_t SET24; /*!< Offset:0x6E0 ADC Setting 24 Register */ struct { __I uint32_t PGA_AGC : 5; /*!< PGA setting value when AGC is on */ __I uint32_t BOOST_AGC : 2; /*!< Boost setting value when AGC is on */ } SET24_b; /*!< BitSize */ }; } SN_ADC_Type; /* ================================================================================ */ /* ================ SN_DAC ================ */ /* ================================================================================ */ /** * @brief Codec DAC Control Registers (SN_DAC) */ typedef struct { /*!< SN_DAC Structure */ union { __IO uint32_t SET1; /*!< Offset:0x000 DAC Setting 1 Register */ struct { uint32_t : 1; __IO uint32_t VMIDSEL : 1; /*!< Normal mode/Fast Start-up select */ __IO uint32_t PD_VREF : 1; /*!< VREF Circuit Power-down enable */ uint32_t : 2; __IO uint32_t PD_IREF : 1; /*!< IREF Circuit Power-down enable */ __IO uint32_t PD_CLK : 1; /*!< CKGEN Power-down enable */ __IO uint32_t PD_DAC : 1; /*!< DAC Power-down enable */ } SET1_b; /*!< BitSize */ }; __I uint32_t RESERVED0[3]; union { __IO uint32_t SET2; /*!< Offset:0x010 DAC Setting 2 Register */ struct { __IO uint32_t SOFT_RSTN : 1; /*!< Software reset digital circuit(one MCLK pulse trigger) */ __IO uint32_t DAC_EN_IN : 1; /*!< DAC Enable */ __IO uint32_t MUTX : 1; /*!< Mute ON/OFF */ uint32_t : 3; __IO uint32_t RMP : 2; /*!< Attenuation ramp rate */ } SET2_b; /*!< BitSize */ }; __I uint32_t RESERVED1[3]; union { __IO uint32_t SET3; /*!< Offset:0x020 DAC Setting 3 Register */ struct { __IO uint32_t VOL : 8; /*!< DAC VOL setting */ } SET3_b; /*!< BitSize */ }; __I uint32_t RESERVED2[3]; union { __IO uint32_t SET4; /*!< Offset:0x030 DAC Setting 4 Register */ struct { __IO uint32_t INI_RAM_EN : 1; /*!< Initialize RAM enable */ __IO uint32_t DEMS : 2; /*!< Select the DAC de-emphasis response curve */ uint32_t : 4; __IO uint32_t PD_DRV : 1; /*!< Driver Power-down enable */ } SET4_b; /*!< BitSize */ }; __I uint32_t RESERVED3[3]; union { __I uint32_t STATUS; /*!< Offset:0x040 DAC Status Register */ struct { __I uint32_t Ini_RAM_Ready: 1; /*!< Initialize RAM ready */ } STATUS_b; /*!< BitSize */ }; } SN_DAC_Type; /* ================================================================================ */ /* ================ SN_FLASH ================ */ /* ================================================================================ */ /** * @brief FLASH Memory Control Registers (SN_FLASH) */ typedef struct { /*!< SN_FLASH Structure */ __I uint32_t RESERVED0; union { __IO uint32_t STATUS; /*!< Offset:0x04 Flash Status Register */ struct { __IO uint32_t BUSY : 1; /*!< Busy flag */ uint32_t : 1; __IO uint32_t PGERR : 1; /*!< Program error flag */ uint32_t : 2; __IO uint32_t EOP : 1; /*!< End of process flag */ } STATUS_b; /*!< BitSize */ }; union { __IO uint32_t CTRL; /*!< Offset:0x08 Flash Control Register */ struct { __IO uint32_t PG : 1; /*!< Flash program choosen */ __IO uint32_t PER : 1; /*!< Page erase choosen */ uint32_t : 4; __IO uint32_t STARTE : 1; /*!< Start erase operation */ __IO uint32_t CHK : 1; /*!< Checksum calculation choosen */ } CTRL_b; /*!< BitSize */ }; __IO uint32_t DATA; /*!< Offset:0x0C Flash Data Register */ __IO uint32_t ADDR; /*!< Offset:0x10 Flash Address Register */ __I uint32_t CHKSUM; /*!< Offset:0x14 Flash Checksum Register */ } SN_FLASH_Type; /* ================================================================================ */ /* ================ SN_CMP ================ */ /* ================================================================================ */ /** * @brief Comparator Control Register (SN_CMP) */ typedef struct { /*!< SN_CMP Structure */ union { __IO uint32_t CMPM; /*!< Offset:0x00 Comparator Control register */ struct { __IO uint32_t CMCH : 5; /*!< Comparator negative input pin control bit (CMPEN must be "1") */ __IO uint32_t CMPS : 2; /*!< Comparator positive input voltage control bit */ uint32_t : 1; __IO uint32_t CMPG : 1; /*!< Comparator interrupt trigger direction control bit */ __IO uint32_t CMPOEN : 1; /*!< Comparator output pin control bit */ __IO uint32_t CMDB : 2; /*!< Comparator output debounce time select bit(TCHEN=1 is HCLK, TCHEN=0 is CMP_PCLK) */ uint32_t : 2; __IO uint32_t CMPOUT : 1; /*!< Comparator output flag bit (The comparator output status is "1" as comparator disable) */ uint32_t : 16; __IO uint32_t CMPEN : 1; /*!< Comparator control bit */ } CMPM_b; /*!< BitSize */ }; __I uint32_t RESERVED0[3]; union { __IO uint32_t CMP_IE; /*!< Offset:0x10 Comparator Interrupt Enable register */ struct { __IO uint32_t CMPGIE : 1; /*!< Comparator edge trigger interrupt enable (Comparator interrupt trigger direction refer to CMPG) */ } CMP_IE_b; /*!< BitSize */ }; union { __I uint32_t CMP_RIS; /*!< Offset:0x14 Comparator Interrupt Status register */ struct { __I uint32_t CMPGIF : 1; /*!< Comparator edge trigger interrupt flag */ } CMP_RIS_b; /*!< BitSize */ }; union { __O uint32_t CMP_IC; /*!< Offset:0x18 Comparator Interrupt Clear register */ struct { __O uint32_t CMPGIC : 1; /*!< Comparator CMPGIF interrupt flag clear */ } CMP_IC_b; /*!< BitSize */ }; } SN_CMP_Type; /* -------------------- End of section using anonymous unions ------------------- */ #if defined(__CC_ARM) #pragma pop #elif defined(__ICCARM__) /* leave anonymous unions enabled */ #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) #pragma warning restore #else #warning Not supported compiler type #endif /* ================================================================================ */ /* ================ Peripheral memory map ================ */ /* ================================================================================ */ #define SN_SYS0_BASE 0x40060000UL #define SN_SYS1_BASE 0x4005E000UL #define SN_GPIO0_BASE 0x40044000UL #define SN_GPIO1_BASE 0x40046000UL #define SN_GPIO2_BASE 0x40048000UL #define SN_GPIO3_BASE 0x4004A000UL #define SN_WDT_BASE 0x40010000UL #define SN_RTC_BASE 0x40012000UL #define SN_CT16B0_BASE 0x40000000UL #define SN_CT16B1_BASE 0x40002000UL #define SN_CT32B0_BASE 0x40004000UL #define SN_CT32B1_BASE 0x40006000UL #define SN_PMU_BASE 0x40032000UL #define SN_SSP0_BASE 0x4001C000UL #define SN_SSP1_BASE 0x40058000UL #define SN_I2C0_BASE 0x40018000UL #define SN_I2C1_BASE 0x4005A000UL #define SN_UART0_BASE 0x40016000UL #define SN_UART1_BASE 0x40056000UL #define SN_I2S_BASE 0x4001A000UL #define SN_ADC_BASE 0x40064000UL #define SN_DAC_BASE 0x40065000UL #define SN_FLASH_BASE 0x40062000UL #define SN_CMP_BASE 0x40066000UL /* ================================================================================ */ /* ================ Peripheral declaration ================ */ /* ================================================================================ */ #define SN_SYS0 ((SN_SYS0_Type *) SN_SYS0_BASE) #define SN_SYS1 ((SN_SYS1_Type *) SN_SYS1_BASE) #define SN_GPIO0 ((SN_GPIO0_Type *) SN_GPIO0_BASE) #define SN_GPIO1 ((SN_GPIO0_Type *) SN_GPIO1_BASE) #define SN_GPIO2 ((SN_GPIO0_Type *) SN_GPIO2_BASE) #define SN_GPIO3 ((SN_GPIO0_Type *) SN_GPIO3_BASE) #define SN_WDT ((SN_WDT_Type *) SN_WDT_BASE) #define SN_RTC ((SN_RTC_Type *) SN_RTC_BASE) #define SN_CT16B0 ((SN_CT16B0_Type *) SN_CT16B0_BASE) #define SN_CT16B1 ((SN_CT16B0_Type *) SN_CT16B1_BASE) #define SN_CT32B0 ((SN_CT32B0_Type *) SN_CT32B0_BASE) #define SN_CT32B1 ((SN_CT32B0_Type *) SN_CT32B1_BASE) #define SN_PMU ((SN_PMU_Type *) SN_PMU_BASE) #define SN_SSP0 ((SN_SSP0_Type *) SN_SSP0_BASE) #define SN_SSP1 ((SN_SSP0_Type *) SN_SSP1_BASE) #define SN_I2C0 ((SN_I2C0_Type *) SN_I2C0_BASE) #define SN_I2C1 ((SN_I2C0_Type *) SN_I2C1_BASE) #define SN_UART0 ((SN_UART0_Type *) SN_UART0_BASE) #define SN_UART1 ((SN_UART0_Type *) SN_UART1_BASE) #define SN_I2S ((SN_I2S_Type *) SN_I2S_BASE) #define SN_ADC ((SN_ADC_Type *) SN_ADC_BASE) #define SN_DAC ((SN_DAC_Type *) SN_DAC_BASE) #define SN_FLASH ((SN_FLASH_Type *) SN_FLASH_BASE) #define SN_CMP ((SN_CMP_Type *) SN_CMP_BASE) /** @} */ /* End of group Device_Peripheral_Registers */ /** @} */ /* End of group SN32F110 */ /** @} */ /* End of group SONiX Technology Co., Ltd. */ #ifdef __cplusplus } #endif #endif /* SN32F110_H */