/*******************************************************************************
* @file s3fn429.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
* default S3FN429 Device
* @version V1.0
* @date 01. May 2012
*
* @note
* Copyright (C) 2012 by MCU Application Team, Samsung Electronics CO.,LTD..
* All rights reserved.
*
* @attention
* The software is delivered "AS IS" without warranty or condition of any kind,
* either express, implied or statutory. This includes without limitation
* any warranty or condition with respect to merchantability or fitness for
* any particular purpose, or against the infringements of intellectual property
* rights of others.
*
******************************************************************************/
/** @addtogroup (null)
* @{
*/
/** @addtogroup S3FN429
* @{
*/
#ifndef __S3FN429_H__
#define __S3FN429_H__
#ifdef __cplusplus
extern "C" {
#endif
/********************************************
** Start of section using anonymous unions **
*********************************************/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma push
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* Interrupt Number Definition */
typedef enum {
// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
SysTick_IRQn = -1, /*!< 15 System Tick Timer */
// --------------------------- S3FN429 Specific Interrupt Numbers -------------------------------
WDT_IRQn = 0, /*!< 0 WDT */
EDGEDET0_IRQn = 2, /*!< 2 EDGEDET0 */
EDGEDET1_IRQn = 3, /*!< 3 EDGEDET1 */
EDGEDET2_IRQn = 4, /*!< 4 EDGEDET2 */
EDGEDET3_IRQn = 5, /*!< 5 EDGEDET3 */
ZERO_TOP_IRQn = 6, /*!< 6 ZERO_TOP */
ADCRMFM0_IRQn = 7, /*!< 7 ADCRMFM0 */
ADCRMFM1_IRQn = 8, /*!< 8 ADCRMFM1 */
ADCRMFM2_IRQn = 9, /*!< 9 ADCRMFM2 */
ADC_IRQn = 10, /*!< 10 ADC */
PPD_P_IRQn = 11, /*!< 11 PPD_P */
PPD_S_IRQn = 12, /*!< 12 PPD_S */
CM_IRQn = 14, /*!< 14 CM */
IFC_IRQn = 15, /*!< 15 IFC */
EEIA_IRQn = 16, /*!< 16 EEIA */
EEIB_IRQn = 17, /*!< 17 EEIB */
EEIC_IRQn = 18, /*!< 18 EEIC */
EEID_IRQn = 19, /*!< 19 EEID */
EEIE_IRQn = 20, /*!< 20 EEIE */
EEIF_IRQn = 21, /*!< 21 EEIF */
TC0_IRQn = 22, /*!< 22 TC0 */
TC1_IRQn = 23, /*!< 23 TC1 */
TC2_IRQn = 24, /*!< 24 TC2 */
PWM0_IRQn = 25, /*!< 25 PWM0 */
PWM1_IRQn = 26, /*!< 26 PWM1 */
PWM2_IRQn = 27, /*!< 27 PWM2 */
PWM3_IRQn = 28, /*!< 28 PWM3 */
SPI_IRQn = 29, /*!< 29 SPI */
USART_IRQn = 30, /*!< 30 USART */
GPIO_IRQn = 31 /*!< 31 GPIO */
} IRQn_Type;
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
#include "system_s3fn429.h" /*!< S3FN429 System */
/*****************************************************************************
* Memory Specification
* SRAM SIZE : 2KBytes
* FLASH SIZE : 32KBytes
* FLASH SECTOR SIZE : 8KBytes
* FLASH PAGE SIZE : 256Bytes
*****************************************************************************/
#define SRAMSIZE 0x800
#define FLASHSIZE 0x8000
#define SECTORSIZE 0x2000
#define PAGESIZE 0x100
#define BLOCKSIZE 0x4
#define SECTOR_NUM 4
#define BLANKPATTERN 0xffffffff
/** @addtogroup Device_Peripheral_Registers
* @{
*/
// ------------------------------------------------------------------------------------------------
// ----- ADC -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Analog to Digital Converter (ADC)
*/
typedef struct { /*!< ADC Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__O uint32_t CSR; /*!< Control Set Register */
__O uint32_t CCR; /*!< Control Clear Register */
__IO uint32_t CDR; /*!< Clock Divider Register */
__IO uint32_t MR; /*!< Mode Register */
__I uint32_t RESERVED0[9];
__IO uint32_t CCSR0; /*!< Conversion Channel Sequence Register 0 */
__IO uint32_t CCSR1; /*!< Conversion Channel Sequence Register 1 */
__I uint32_t SSR; /*!< Sequence State Register */
__I uint32_t RESERVED1[5];
__I uint32_t SR; /*!< Status Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
__I uint32_t RESERVED2[3];
__I uint32_t CRR0; /*!< Conversion Result Register 0 */
__I uint32_t CRR1; /*!< Conversion Result Register 1 */
__I uint32_t CRR2; /*!< Conversion Result Register 2 */
__I uint32_t CRR3; /*!< Conversion Result Register 3 */
__I uint32_t CRR4; /*!< Conversion Result Register 4 */
__I uint32_t CRR5; /*!< Conversion Result Register 5 */
__I uint32_t CRR6; /*!< Conversion Result Register 6 */
__I uint32_t CRR7; /*!< Conversion Result Register 7 */
__I uint32_t CRR8; /*!< Conversion Result Register 8 */
__I uint32_t CRR9; /*!< Conversion Result Register 9 */
__I uint32_t CRR10; /*!< Conversion Result Register 10 */
__IO uint32_t GCR; /*!< Gain Calibration Register */
__IO uint32_t OCR; /*!< Offset Calibration Register */
__I uint32_t RESERVED3[19];
__I uint32_t CBR0; /*!< Conversion Buffer Register 0 */
__I uint32_t CBR1; /*!< Conversion Buffer Register 1 */
__I uint32_t CBR2; /*!< Conversion Buffer Register 2 */
__I uint32_t CBR3; /*!< Conversion Buffer Register 3 */
__I uint32_t CBR4; /*!< Conversion Buffer Register 4 */
__I uint32_t CBR5; /*!< Conversion Buffer Register 5 */
__I uint32_t CBR6; /*!< Conversion Buffer Register 6 */
__I uint32_t CBR7; /*!< Conversion Buffer Register 7 */
__I uint32_t CBR8; /*!< Conversion Buffer Register 8 */
__I uint32_t CBR9; /*!< Conversion Buffer Register 9 */
__I uint32_t CBR10; /*!< Conversion Buffer Register 10 */
} ADC_Type;
// ------------------------------------------------------------------------------------------------
// ----- CM -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Clock Manager (CM)
*/
typedef struct { /*!< CM Structure */
__I uint32_t IDR; /*!< ID Register */
__O uint32_t SRR; /*!< Software Reset Register */
__O uint32_t CSR; /*!< Control Set Register */
__O uint32_t CCR; /*!< Control Clear Register */
__O uint32_t PCSR; /*!< Peripheral Clock Set Register */
__I uint32_t RESERVED0;
__O uint32_t PCCR; /*!< Peripheral Clock Clear Register */
__I uint32_t RESERVED1;
__I uint32_t PCKSR; /*!< Peripheral Clock Status Register */
__I uint32_t RESERVED2;
__IO uint32_t MR0; /*!< Mode Register 0 */
__IO uint32_t MR1; /*!< Mode Register 1 */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
__IO uint32_t SR; /*!< Status Register */
__IO uint32_t SCDR; /*!< System Clock Divider Register */
__IO uint32_t PCDR; /*!< Peripheral Clock Divider Register */
__I uint32_t RESERVED3[3];
__IO uint32_t PSTR; /*!< PLL Stabilization Time Register */
__IO uint32_t PDPR; /*!< PLL Divider Parameter Register */
__I uint32_t RESERVED4[4];
__IO uint32_t BTCDR; /*!< Basic Timer Clock Divider Register */
__IO uint32_t BTR; /*!< Basic Timer Value Register */
__IO uint32_t EECR0; /*!< External Event Control Register 0 */
__IO uint32_t EECR1; /*!< External Event Control Register 1 */
__I uint32_t RESERVED5[2];
__IO uint32_t EEIMSCR; /*!< External Event Interrupt Mask Set/Clear Register */
__I uint32_t EERISR; /*!< External Event Raw Interrupt Status Register */
__I uint32_t EEMISR; /*!< External Event Masked Interrupt Status Register */
__O uint32_t EEICR; /*!< External Event Interrupt Clear Register */
__IO uint32_t NISR; /*!< NVIC Interrupt Status Regsiter */
__I uint32_t RESERVED6[2];
__I uint32_t PSR; /*!< Power Status Register */
} CM_Type;
// ------------------------------------------------------------------------------------------------
// ----- COMP -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Comparator (COMP)
*/
typedef struct { /*!< COMP Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__IO uint32_t CR0; /*!< Control Register 0 */
__IO uint32_t CR1; /*!< Control Register 1 */
__IO uint32_t CR2; /*!< Control Register 2 */
__I uint32_t SR; /*!< Status Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
} COMP_Type;
// ------------------------------------------------------------------------------------------------
// ----- PPD -----
// ------------------------------------------------------------------------------------------------
/**
* @brief The Pulse Position Decoder (PPD) chapter describes the PPD that you can use for measuring the position and speed. (PPD)
*/
typedef struct { /*!< PPD Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__IO uint32_t CR0; /*!< Control Register 0 */
__IO uint32_t CR1; /*!< Control Register 1 */
__IO uint32_t SR; /*!< Status Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
__IO uint32_t PCR; /*!< Position Counter Register */
__IO uint32_t PCRR; /*!< Position Counter Reference Register */
__IO uint32_t PCTR; /*!< Position Capture Timer Register */
__IO uint32_t PCTVR; /*!< Position Capture Timer Value Register */
__IO uint32_t SCR; /*!< Speed Counter Register */
__IO uint32_t SCRR; /*!< Speed Counter Reference Register */
__IO uint32_t SCTR; /*!< Speed Capture Timer Register */
__IO uint32_t SCTVR; /*!< Speed Capture Timer Value Register */
__IO uint32_t PCHR; /*!< Position Counter Hold Register */
__IO uint32_t PCTHR; /*!< Position Capture Timer Hold Register */
__IO uint32_t PCTVHR; /*!< Position Capture Timer Value Hold Register */
__IO uint32_t SCHR; /*!< Speed Counter Hold Register */
__IO uint32_t SCTHR; /*!< Speed Capture Timer Hold Register */
__IO uint32_t SCTVHR; /*!< Speed Capture Timer Value Hold Register */
} PPD_Type;
// ------------------------------------------------------------------------------------------------
// ----- GPIO -----
// ------------------------------------------------------------------------------------------------
/**
* @brief General Purpose IO chapter describes the configuration of General Purpose IO (GPIO), such as input and output. (GPIO)
*/
typedef struct { /*!< GPIO Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
__O uint32_t OER; /*!< Output Enable Register */
__O uint32_t ODR; /*!< Output Disable Register */
__I uint32_t OSR; /*!< Output Status Register */
__O uint32_t WODR; /*!< Write Output Data Register */
__O uint32_t SODR; /*!< Set Output Data Register */
__O uint32_t CODR; /*!< Clear Output Data Register */
__I uint32_t ODSR; /*!< Output Data Status Register */
__I uint32_t PDSR; /*!< Pin Data Status Register */
} GPIO_Type;
// ------------------------------------------------------------------------------------------------
// ----- IFC -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Internal Flash Controller (IFC) has an on-chip program flash ROM, internally. The flash memory size is 32 KB (IFC)
*/
typedef struct { /*!< IFC Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__IO uint32_t CR; /*!< Control Register */
__IO uint32_t MR; /*!< Mode Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/ Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
__I uint32_t SR; /*!< Status Register */
__IO uint32_t AR; /*!< Address Register */
__IO uint32_t DR; /*!< Data Register */
__O uint32_t KR; /*!< Key Register */
__I uint32_t SOPSR; /*!< Smart Option Protection Status Register */
__I uint32_t SOCSR; /*!< Smart Option Configuration Status Register */
__IO uint32_t IOTR; /*!< Internal OSC Trimming Register */
} IFC_Type;
// ------------------------------------------------------------------------------------------------
// ----- IMC -----
// ------------------------------------------------------------------------------------------------
/**
* @brief You can use the Inverter Motor Controller (IMC) for three phase inverter motor (IMC)
*/
typedef struct { /*!< IMC Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__IO uint32_t CR0; /*!< Control Register 0 */
__IO uint32_t CR1; /*!< Control Register 0 */
__I uint32_t CNTR; /*!< Counter Register */
__IO uint32_t SR; /*!< Status Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
__IO uint32_t TCR; /*!< 16-bit Top Compare Register */
__IO uint32_t DTCR; /*!< 16-bit Dead Time Control Register */
__IO uint32_t PACRR; /*!< 16-bit Phase A Compare Rising Register */
__IO uint32_t PBCRR; /*!< 16-bit Phase B Compare Rising Register */
__IO uint32_t PCCRR; /*!< 16-bit Phase C Compare Rising Register */
__IO uint32_t PACFR; /*!< 16-bit Phase A Compare Falling Register */
__IO uint32_t PBCFR; /*!< 16-bit Phase B Compare Falling Register */
__IO uint32_t PCCFR; /*!< 16-bit Phase C Compare Falling Register */
__IO uint32_t ASTSR; /*!< ADC Start Trigger Selection Register */
__IO uint32_t ASCRR0; /*!< 16-bit ADC Start Compare Rising Register 0 */
__IO uint32_t ASCRR1; /*!< 16-bit ADC Start Compare Rising Register 1 */
__IO uint32_t ASCRR2; /*!< 16-bit ADC Start Compare Rising Register 2 */
__IO uint32_t ASCFR0; /*!< 16-bit ADC Start Compare Falling Register 0 */
__IO uint32_t ASCFR1; /*!< 16-bit ADC Start Compare Falling Register 1 */
__IO uint32_t ASCFR2; /*!< 16-bit ADC Start Compare Falling Register 2 */
} IMC_Type;
// ------------------------------------------------------------------------------------------------
// ----- IOCONF -----
// ------------------------------------------------------------------------------------------------
/**
* @brief The I/O Configuration (IOCONF) chapter describes the configuration of specific function pins mapped to each I/O pin. (IOCONF)
*/
typedef struct { /*!< IOCONF Structure */
__IO uint32_t MLR0; /*!< Mode Low Register */
__IO uint32_t MHR0; /*!< Mode High Register */
__IO uint32_t PUCR0; /*!< Pull-Up Control Register */
__IO uint32_t ODCR0; /*!< Open-Drain Control Register */
} IOCONF_Type;
// ------------------------------------------------------------------------------------------------
// ----- OPAMP -----
// ------------------------------------------------------------------------------------------------
/**
* @brief The Operation Amplifier (OP-AMP) chapter describes OP-AMP that operates separately or with an Analog to Digital Converter (ADC). You can configure OP-AMP gain using control bits (OPAMP)
*/
typedef struct { /*!< OPAMP Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__IO uint32_t CR; /*!< Control Register */
__IO uint32_t GCR; /*!< Gain Control Register */
} OPAMP_Type;
// ------------------------------------------------------------------------------------------------
// ----- PWM0 -----
// ------------------------------------------------------------------------------------------------
/**
* @brief The Pulse Width Modulation (PWM) chapter describes the on chip PWM generator. The PWM is a common technique to control power devices in industrial fields. PWM output channel uses 16-bit up counter to generate rectangular pluses with the programmable period and duty ratio. It has output extensions up to 22-bit resolution. (PWM0)
*/
typedef struct { /*!< PWM0 Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__O uint32_t CSR; /*!< Control Register */
__O uint32_t CCR; /*!< Control Clear Register */
__I uint32_t SR; /*!< Status Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
__IO uint32_t CDR; /*!< Clock Divider Register */
__IO uint32_t PRDR; /*!< Period Register */
__IO uint32_t PULR; /*!< Pulse Register */
__I uint32_t CCDR; /*!< Current Clock Divider Register */
__I uint32_t CPRDR; /*!< Current Period Register */
__I uint32_t CPULR; /*!< Current Pulse Register */
} PWM_Type;
// ------------------------------------------------------------------------------------------------
// ----- SPI -----
// ------------------------------------------------------------------------------------------------
/**
* @brief The PrimeCell Synchronous Serial Port (SSP, PL022) is used for Serial Peripheral Interface . Serial communication is the process of sequentially sending data one bit at a time (SPI)
*/
typedef struct { /*!< SPI Structure */
__IO uint32_t CR0; /*!< SSP Control Register 0 */
__IO uint32_t CR1; /*!< SSP Control Register 1 */
__IO uint32_t DR; /*!< SSP Receive FIFO Data Register (Read)SSP Transmit FIFO Data Register (Write) */
__I uint32_t SR; /*!< SSP Status Register */
__IO uint32_t CPSR; /*!< SSP Clock Rescale Register */
__IO uint32_t IMSCR; /*!< SSP Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< SSP Raw Interrupt Status Register */
__I uint32_t MISR; /*!< SSP Masked Interrupt Status Register */
__O uint32_t ICR; /*!< SSP Interrupt Clear Register */
} SPI_Type;
// ------------------------------------------------------------------------------------------------
// ----- TC0 -----
// ------------------------------------------------------------------------------------------------
/**
* @brief The Timer/Counter (TC) chapter describes TIMER/COUNTER module that operates in match and overflow, capture, interval or in PWM operation (TC0)
*/
typedef struct { /*!< TC0 Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CSSR; /*!< Clock Source Selection Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Software Reset Register */
__O uint32_t CSR; /*!< Control Set Register */
__O uint32_t CCR; /*!< Control Clear Register */
__I uint32_t SR; /*!< Status Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Interrupt Clear Register */
__IO uint32_t CDR; /*!< Clock Divider Register */
__IO uint32_t CSMR; /*!< Counter Size Mask Register */
__IO uint32_t PRDR; /*!< Period Register */
__IO uint32_t PULR; /*!< Pulse Register */
__I uint32_t CCDR; /*!< Current Clock Divider Register */
__I uint32_t CCSMR; /*!< Current Counter Size Mask Register */
__I uint32_t CPRDR; /*!< Current Period Register */
__I uint32_t CPULR; /*!< Current Pulse Register */
__I uint32_t CUCR; /*!< Capture Up Count Register */
__I uint32_t CDCR; /*!< Capture Down Count Register */
__I uint32_t CVR; /*!< Counter Value Register */
} TC_Type;
// ------------------------------------------------------------------------------------------------
// ----- USART -----
// ------------------------------------------------------------------------------------------------
/**
* @brief The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) controller is used to communicate between micro-controllers. The USART at the transmitting end takes bytes of data and transmits the individual bits sequentially starting from the Least Significant Bit (LSB). The USART at the receiving end re-assembles the bits into the originally transmitted byte. (USART)
*/
typedef struct { /*!< USART Structure */
__I uint32_t IDR; /*!< ID Register */
__IO uint32_t CEDR; /*!< Clock Enable/Disable Register */
__IO uint32_t SRR; /*!< Software Reset Register */
__O uint32_t CR; /*!< Control Register */
__IO uint32_t MR; /*!< Mode Register */
__IO uint32_t IMSCR; /*!< Interrupt Mask Set/ Clear Register */
__I uint32_t RISR; /*!< Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Masked Interrupt Status Register */
__IO uint32_t ICR; /*!< Interrupt Clear Register */
__I uint32_t SR; /*!< Status Register */
__I uint32_t RHR; /*!< Receiver Holding Register */
__O uint32_t THR; /*!< Transmitter Holding Register */
__IO uint32_t BRGR; /*!< BaudRate Generator Register */
__IO uint32_t RTOR; /*!< Receiver Time-Out Register */
__IO uint32_t TTGR; /*!< Transmitter Time-Guard Register */
} USART_Type;
// ------------------------------------------------------------------------------------------------
// ----- WDT -----
// ------------------------------------------------------------------------------------------------
/**
* @brief Watchdog Timer (WDT)
*/
typedef struct { /*!< WDT Structure */
__I uint32_t IDR; /*!< Watchdog ID Register */
__O uint32_t CR; /*!< Watchdog Control Register */
__IO uint32_t MR; /*!< Watchdog Mode Register */
__IO uint32_t OMR; /*!< Watchdog Overflow Mode Register */
__I uint32_t SR; /*!< Watchdog Status Register */
__IO uint32_t IMSCR; /*!< Watchdog Interrupt Mask Set /Clear Register */
__I uint32_t RISR; /*!< Watchdog Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Watchdog Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Watchdog Interrupt Clear Register */
__IO uint32_t PWR; /*!< Watchdog Pending Window Register */
__I uint32_t CTR; /*!< Watchdog Counter Test Register */
} WDT_Type;
/********************************************
** End of section using anonymous unions **
*********************************************/
#if defined(__ARMCC_VERSION)
#pragma pop
#elif defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma pop
#else
#error Not supported compiler type
#endif
// ------------------------------------------------------------------------------------------------
// ----- Peripheral memory map -----
// ------------------------------------------------------------------------------------------------
#define ADC_BASE 0x40040000
#define CM_BASE 0x40020000
#define COMP_BASE 0x40042000
#define PPD_BASE 0x400C0000
#define GPIO_BASE 0x40050000
#define IFC_BASE 0x40010000
#define IMC_BASE 0x400B0000
#define IOCONF_BASE 0x40058000
#define OPAMP_BASE 0x40041000
#define PWM0_BASE 0x40070000
#define PWM1_BASE 0x40071000
#define PWM2_BASE 0x40072000
#define PWM3_BASE 0x40073000
#define SPI_BASE 0x40090000
#define TC0_BASE 0x40060000
#define TC1_BASE 0x40061000
#define TC2_BASE 0x40062000
#define USART_BASE 0x40080000
#define WDT_BASE 0x40030000
// ------------------------------------------------------------------------------------------------
// ----- Peripheral declaration -----
// ------------------------------------------------------------------------------------------------
#define ADC0 ((ADC_Type *) ADC_BASE)
#define CM0 ((CM_Type *) CM_BASE)
#define COMP0 ((COMP_Type *) COMP_BASE)
#define PPD0 ((PPD_Type *) PPD_BASE)
#define GPIO0 ((GPIO_Type *) GPIO_BASE)
#define IFC0 ((IFC_Type *) IFC_BASE)
#define IMC0 ((IMC_Type *) IMC_BASE)
#define IOCONF0 ((IOCONF_Type *) IOCONF_BASE)
#define OPAMP ((OPAMP_Type *) OPAMP_BASE)
#define PWM0 ((PWM_Type *) PWM0_BASE)
#define PWM1 ((PWM_Type *) PWM1_BASE)
#define PWM2 ((PWM_Type *) PWM2_BASE)
#define PWM3 ((PWM_Type *) PWM3_BASE)
#define SPI0 ((SPI_Type *) SPI_BASE)
#define TC0 ((TC_Type *) TC0_BASE)
#define TC1 ((TC_Type *) TC1_BASE)
#define TC2 ((TC_Type *) TC2_BASE)
#define USART0 ((USART_Type *) USART_BASE)
#define WDT0 ((WDT_Type *) WDT_BASE)
// ------------------------------------------------------------------------------------------------
// ----- ADC Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : ID Register
******************************************************************************/
#define ADC_IDCODE_MASK (0x03FFFFFFul << 0) /**< IPIDCODE mask */
#define ADC_IDCODE (0x0001001F << 0) /**< IPIDCODE value */
/******************************************************************************
* CEDR : Clock Enable/Disable Register
******************************************************************************/
#define ADC_CLKEN (0x01ul << 0) /**< IP Clock */
#define ADC_DBGEN (0x01ul << 31) /**< Debug Mode Enable */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define ADC_SWRST (0x01ul << 0) /**< Software Reset */
/******************************************************************************
* CSR : Control Set Register
* CCR : Control Clear Register
******************************************************************************/
#define ADC_ADCEN (0x01ul << 0) /**< ADC macro(engine)Enable */
/* CSR only */
#define ADC_START (0x01ul << 1) /**< Conversion Start */
/* CSR only */
#define ADC_CCSTOP (0x01ul << 2) /**< Continuous Conversion Stop */
/* CSR only */
#define ADC_CRRCLR (0x01ul << 7) /**< CRR Clear */
/******************************************************************************
* CDR : Clock Divider Register
******************************************************************************/
#define ADC_CDIV_MASK (0x1Ful << 0) /**< ADC CDIV mask */
#define ADC_CDIV(val) (((val) & 0x1Ful) << 0) /**< Writing Macro */
/******************************************************************************
* MR : ADC Mode Register
******************************************************************************/
#define ADC_TRIG_MASK (0x07ul << 5) /**< external start trigger type */
#define ADC_TRIG(val) ((val) & 0x07ul)/**< writing Macro */
#define ADC_CMODE (0x01ul << 7) /**< Conversion mode */
#define ADC_CCNT(val) (((val) & 0x0Ful) << 8) /**< Conversion count field */
#define ADC_CALEN (0x01ul << 24) /**< Calibration enable */
#define ADC_ICRV (0x01ul << 25) /**< Int.Calibration Reference Volt.*/
#define ADC_EICR (0x01ul << 26) /**< ExtInt Calibration Reference */
#define ADC_SWSTART (0x0)
#define ADC_ADTRG_R (0x1)
#define ADC_ADTRG_F (0x2)
#define ADC_ADTRG_B (0x3)
#define ADC_TC (0x4)
#define ADC_IMC (0x5)
/******************************************************************************
* CCSR0 : ADC Conversion Sequence Registers
******************************************************************************/
#define ADC_ICNUM0(val) (((val) & 0x0Ful) << 0) /**< Conversion count field */
#define ADC_ICNUM1(val) (((val) & 0x0Ful) << 4) /**< Conversion count field */
#define ADC_ICNUM2(val) (((val) & 0x0Ful) << 8) /**< Conversion count field */
#define ADC_ICNUM3(val) (((val) & 0x0Ful) << 12) /**< Conversion count field */
#define ADC_ICNUM4(val) (((val) & 0x0Ful) << 16) /**< Conversion count field */
#define ADC_ICNUM5(val) (((val) & 0x0Ful) << 20) /**< Conversion count field */
#define ADC_ICNUM6(val) (((val) & 0x0Ful) << 24) /**< Conversion count field */
#define ADC_ICNUM7(val) (((val) & 0x0Ful) << 28) /**< Conversion count field */
#define ADC_AIN0 0x0ul /**< ADC Analog Input 0 */
#define ADC_AIN1 0x1ul /**< ADC Analog Input 1 */
#define ADC_AIN2 0x2ul /**< ADC Analog Input 2 */
#define ADC_AIN3 0x3ul /**< ADC Analog Input 3 */
#define ADC_AIN4 0x4ul /**< ADC Analog Input 4 */
#define ADC_AIN5 0x5ul /**< ADC Analog Input 5 */
#define ADC_AIN6 0x6ul /**< ADC Analog Input 6 */
#define ADC_AIN7 0x7ul /**< ADC Analog Input 7 */
#define ADC_AIN8 0x8ul /**< ADC Analog Input 8 */
#define ADC_AIN9 0x9ul /**< ADC Analog Input 9 */
#define ADC_AIN10 0xAul /**< ADC Analog Input 10 */
/******************************************************************************
* CCSR1 : ADC Conversion Sequence Registers
******************************************************************************/
#define ADC_ICNUM8(val) (((val) & 0x0Ful) << 0) /**< Conversion count field */
#define ADC_ICNUM9(val) (((val) & 0x0Ful) << 4) /**< Conversion count field */
#define ADC_ICNUM10(val) (((val) & 0x0Ful) << 8) /**< Conversion count field */
/******************************************************************************
* SSR : ADC Sequence Status Registers
******************************************************************************/
/**< Current Conversion Chnanel Number field */
#define ADC_CCCN(val) (((val) & 0x0Ful) << 0)
/**< Current Conversion Count field */
#define ADC_CCCV(val) (((val) & 0x0Ful) << 24)
/******************************************************************************
* SR : ADC Status Registers
******************************************************************************/
#define ADC_ADCEN (0x01ul << 0) /**< ADC macro enabled & stabled */
#define ADC_BUSY (0x01ul << 1) /**< ADC macro busy for conversion */
#define ADC_CMODE (0x01ul << 7) /**< ADC conversion mode */
#define ADC_OVR0 (0x01ul << 16) /**< ADC Overrun0 flag */
#define ADC_OVR1 (0x01ul << 17) /**< ADC Overrun1 flag */
#define ADC_OVR2 (0x01ul << 18) /**< ADC Overrun2 flag */
#define ADC_OVR3 (0x01ul << 19) /**< ADC Overrun3 flag */
#define ADC_OVR4 (0x01ul << 20) /**< ADC Overrun4 flag */
#define ADC_OVR5 (0x01ul << 21) /**< ADC Overrun5 flag */
#define ADC_OVR6 (0x01ul << 22) /**< ADC Overrun6 flag */
#define ADC_OVR7 (0x01ul << 23) /**< ADC Overrun7 flag */
#define ADC_OVR8 (0x01ul << 24) /**< ADC Overrun8 flag */
#define ADC_OVR9 (0x01ul << 25) /**< ADC Overrun9 flag */
#define ADC_OVR10 (0x01ul << 26) /**< ADC Overrun10 flag */
/******************************************************************************
* IMSCR : Interrupt RST Set/Clear Register
* RISR : Raw Interrupt Status Register
* MISR : Interrupt Status Register
* ICR : Interrupt Clear Register
******************************************************************************/
#define ADC_EOC (0x01ul << 0) /**< End Of Conversion Interrupt */
#define ADC_OVR (0x01ul << 1) /**< Overrun Interrupt */
/******************************************************************************
* CRR/CBR : ADC Conversion Result/Buffer Register
******************************************************************************/
#define ADC_DATA_MASK (0xFFFul << 0) /**< ADC Converted Data Mask */
/**< Current Conversion Count field */
#define ADC_DATA(val) (((val) & ADC_DATA_MASK) << 0)
// ------------------------------------------------------------------------------------------------
// ----- CM Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : Clock Manager ID Register
******************************************************************************/
#define CM_IDCODE_MASK (0x03FFFFFFul << 0)
#define CM_IDCODE (0x0001001Cul << 0) /**< ID Code */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define CM_SWRST (0x1ul << 0) /**< CM Software Reset */
#define CM_SWRSTKEY (0xA66A <<16)
/******************************************************************************
* PCSR : Peripheral Clock Set Register
* PCCR : Peripheral Clock Clear Register
* PCKSR: Peripheral Clock Status Register
******************************************************************************/
#define CM_OPACLK (0x01ul << 0) /**< OPAMP Clock Control Bit */
#define CM_WDTCLK (0x01ul << 1) /**< WDT Clock Control Bit */
#define CM_PWM0CLK (0x01ul << 2) /**< PWM0 Clock Control Bit */
#define CM_PWM1CLK (0x01ul << 3) /**< PWM1 Clock Control Bit */
#define CM_PWM2CLK (0x01ul << 4) /**< PWM0 Clock Control Bit */
#define CM_PWM3CLK (0x01ul << 5) /**< PWM1 Clock Control Bit */
#define CM_PPDCLK (0x01ul << 6) /**< ENC Clock Control Bit */
#define CM_IMCCLK (0x01ul << 7) /**< IMC Clock Control Bit */
#define CM_TC0CLK (0x01ul << 8) /**< TC0 Clock Control Bit */
#define CM_TC1CLK (0x01ul << 9) /**< TC1 Clock Control Bit */
#define CM_TC2CLK (0x01ul << 10) /**< TC2 Clock Control Bit */
#define CM_USARTCLK (0x01ul << 16) /**< USART0 Clock Control Bit */
#define CM_ADCCLK (0x01ul << 22) /**< ADC Clock Control Bit */
#define CM_COMPCLK (0x01ul << 23) /**< ADC Clock Control Bit */
#define CM_SPICLK (0x01ul << 24) /**< SPI0 Clock Control Bit */
#define CM_IFCCLK (0x01ul << 29) /**< PFC Clock Control Bit */
#define CM_IOCLK (0x01ul << 30) /**< IOCONF & GPIO Clock Control Bit*/
/******************************************************************************
* MR0 : Mode register 0
******************************************************************************/
#define CM_LVDRL_MASK (0x7ul << 0)
#define CM_LVDRL(val) ((val & 0x7ul) << 0)/**< LVD Reset level */
#define CM_LVDRSTEN (0x01ul << 3) /**< LVD Reset en/disable */
#define CM_LVDIL_MASK (0x7ul << 4)
#define CM_LVDIL(val) ((val & 0x7ul) << 4)/**< LVD Interrupt level */
#define CM_LVDINTEN (0x01ul << 7) /**< LVD Interrupt en/disable */
#define CM_LVD_LEVEL1 (0x4) /* LVD Detect level - type 4.3V */
#define CM_LVD_LEVEL2 (0x3) /* LVD Detect level - type 3.8V */
#define CM_LVD_LEVEL3 (0x2) /* LVD Detect level - type 2.8V */
#define CM_LVD_LEVEL4 (0x1) /* LVD Detect level - type 2.6V */
#define CM_LVD_LEVEL5 (0x0) /* LVD Detect level - type 2.4V */
#define CM_RXEV (0x01ul<<9) /**< RXEV Enable */
#define CM_STCLKEN (0x01ul<<10) /**< Systick Timer En/Disable */
#define CM_LVDPD (0x01ul<<11) /**< LVD Power-Down En/Disable */
/******************************************************************************
* MR1 : Mode register 1
******************************************************************************/
#define CM_SYSCLK_MASK (0x3ul << 0) /**< SYSCLK Selection mask */
#define CM_WDTCLK_MASK (0x3ul << 4) /**< WDT Clock selection mask */
#define CM_SYSCLK_SEL(val) ((val & 0x3ul) << 0) /**< SYSCLK Selection */
#define CM_WDTCLK_SEL(val) ((val & 0x3ul) << 4) /**< WDT Clock selection */
/******************************************************************************
* SR : Status Register
******************************************************************************/
#define CM_EMCLK (0x01ul << 0) /**< External Main Clock En/Disable */
#define CM_IMCLK (0x01ul << 1) /**< Internal Main Clock En/Disable */
#define CM_WDTCLKS (0x01ul << 3) /**< Watchdog Clock Status */
#define CM_STABLE (0x01ul << 4) /**< Clock Switching Sable */
#define CM_FWAKE (0x01ul << 5) /**< External Main Clock */
#define CM_PLL (0x01ul << 7) /**< PLL status */
#define CM_STCLK (0x01ul << 8)
#define CM_PCLK (0x01ul << 9)
#define CM_IDLEW (0x01ul << 11)
#define CM_EMCKFAIL_END (0x01ul << 14) /**< EMCLk fail status end */
#define CM_EMCLKFAIL (0x01ul << 15) /**< EMCLK fail (clock monitor) */
#define CM_LVDINT (0x01ul << 16) /**< LVD Interrupt Flag */
#define CM_LVDRS (0x01ul << 17) /**< LVD Reset Flag */
#define CM_CMDERR (0x01ul << 18) /**< BAD Command Flag */
#define CM_EMCMRST (0x01ul << 22) /**< External Main Clock */
#define CM_EMCM (0x01ul << 23) /**< External Main Clock */
#define CM_SWRSTS (0x01ul << 24) /**< Software Reset Flag */
#define CM_NRSTS (0x01ul << 25) /**< nReset Flag */
#define CM_LVDRSTS (0x01ul << 26) /**< LVD Reset Flag */
#define CM_WDTRSTS (0x01ul << 27) /**< WDT Reset Flag */
#define CM_PORRSTS (0x01ul << 28) /**< POR Reset Flag */
#define CM_EMCMRSTS (0x01ul << 30) /**< EMCLK Clock Monitor Reset Flag */
#define CM_SYSRSTS (0x01ul << 31) /**< CortexM0 System Reset */
/******************************************************************************
* SCDR : System Clock Divider Register
******************************************************************************/
#define CM_SDIVKEY_MASK (0xFFFFul << 16) /**< SDIVKEY mask */
#define CM_SDIVKEY (0xACDCul << 16) /**< Key for write access */
#define CM_SDIV_MASK (0x07ul << 0) /**< SysClock select mask */
#define CM_SDIV(val) ((val & 0x7ul) << 0)/**< SYSCLK divider */
#define CM_SYSCLK_DIV1 (0x00ul)
#define CM_SYSCLK_DIV2 (0x01ul)
#define CM_SYSCLK_DIV3 (0x02ul)
#define CM_SYSCLK_DIV4 (0x03ul)
#define CM_SYSCLK_DIV5 (0x04ul)
#define CM_SYSCLK_DIV6 (0x05ul)
#define CM_SYSCLK_DIV7 (0x06ul)
#define CM_SYSCLK_DIV8 (0x07ul)
/******************************************************************************
* PCDR : Peripheral Clock Divider Register
******************************************************************************/
#define CM_PDIVKEY_MASK (0xFFFFul << 16) /**< PDIVKEY mask */
#define CM_PDIVKEY (0xA3C5ul << 16) /**< Key for write access */
#define CM_PDIV_MASK (0xFul << 0) /**< PCLK mask */
#define CM_PDIV(val) ((val & 0xFul) << 0) /**< PCLK macro */
#define CM_PCLK_DIV1 (0x00ul)
#define CM_PCLK_DIV2 (0x01ul << 0)
#define CM_PCLK_DIV4 (0x02ul << 0)
#define CM_PCLK_DIV8 (0x04ul << 0)
#define CM_PCLK_DIV16 (0x08ul << 0)
/******************************************************************************
* PSTR : PLL Stabilization Time Register
******************************************************************************/
#define CM_PLLSKEY_MASK (0xFFFFul << 16) /**< PLLSKEY mask */
#define CM_PLLSKEY (0x59C1ul << 16) /**< Key for write access */
#define CM_PST_MASK (0x7FFul << 0)
#define CM_PST(val) ((val & 0x7FFul) << 0) /**< PLL stabilization time */
/******************************************************************************
* PDPR : PLL Divider Parameter Register
******************************************************************************/
#define CM_PLLMUL_MASK ((0xFFul)<< 0) /**< PLL Multiplier mask */
#define CM_PLLPRE_MASK ((0x3Ful)<< 8) /**< Pre divider parameter mask*/
#define CM_PLLPOST_MASK ((0x03ul)<< 16) /**< Post scalar parameter mask*/
#define CM_PLLKEY_MASK (0xFFul << 24) /**< PLLKEY mask */
#define CM_PLLMUL(val) ((val & 0xFFul) << 0) /**< PLL Multiplier macro */
#define CM_PLLPRE(val) ((val & 0x3Ful) << 8) /**< Pre divider parameter */
#define CM_PLLPOST(val) ((val & 0x03ul) << 16)/**< Post scalar parameter */
#define CM_LFPASS (0x01ul << 23) /**< LFPASS Enable */
#define CM_PLLKEY (0xC1ul << 24) /**< Key for write access */
/******************************************************************************
* BTCDR : Basic Timer Clock Divider Register
******************************************************************************/
#define CM_BTCDKEY_MASK (0xFFFFul << 16) /**< BT KEY mask */
#define CM_BTCDKEY (0x3569ul << 16) /**< Key for write access */
#define CM_BTCDIV_MASK (0xFul << 0)
#define CM_BTCDIV(val) ((val & 0xFul) << 0)/**< BT Clock divider */
#define CM_BTCDIV4096 (0xFul) /**< divider 4096 */
#define CM_BTCDIV2048 (0xEul) /**< divider 2048 */
#define CM_BTCDIV1024 (0xDul) /**< divider 1024 */
#define CM_BTCDIV512 (0xCul) /**< divider 512 */
#define CM_BTCDIV256 (0xBul) /**< divider 256 */
#define CM_BTCDIV128 (0xAul) /**< divider 128 */
#define CM_BTCDIV64 (0x9ul) /**< divider 64 */
#define CM_BTCDIV32 (0x8ul) /**< divider 32 */
#define CM_BTCDIV16 (0x7ul) /**< divider 16 */
#define CM_BTCDIV8 (0x6ul) /**< divider 8 */
#define CM_BTCDIV4 (0x5ul) /**< divider 4 */
#define CM_BTCDIV2 (0x4ul) /**< divider 2 */
#define CM_BTCDIV1 (0x3ul) /**< divider 1 */
/******************************************************************************
* EECR0 : External Event Control Register 0
******************************************************************************/
#define CM_EESRC(val) (val & 0x1Ful) /**< Wakeup Source X */
#define CM_EESRC0(val) ((val & 0x1Ful) << 0) /**< Wakeup Source0 */
#define CM_EDGE0(val) ((val & 0x3ul) << 5) /**< Wakeup Source0 Edge */
#define CM_EEEN0 (0x01ul << 7) /**< Wakeup Source0 Enable */
#define CM_EESRC1(val) ((val & 0x1Ful) << 8) /**< Wakeup Source1 */
#define CM_EDGE1(val) ((val & 0x3ul) << 13) /**< Wakeup Source1 Edge */
#define CM_EEEN1 (0x01ul << 15) /**< Wakeup Source1 Enable */
#define CM_EESRC2(val) ((val & 0x1Ful) << 16) /**< Wakeup Source2 */
#define CM_EDGE2(val) ((val & 0x3ul) << 21) /**< Wakeup Source2 Edge */
#define CM_EEEN2 (0x01ul << 23) /**< Wakeup Source2 Enable */
#define CM_EESRC3(val) ((val & 0x1Ful) << 24) /**< Wakeup Source3 */
#define CM_EDGE3(val) ((val & 0x3ul) << 29) /**< Wakeup Source3 Edge */
#define CM_EEEN3 (0x01ul << 31) /**< Wakeup Source3 Enable */
/******************************************************************************
* EECR1 : External Event Control Register 1
******************************************************************************/
#define CM_EESRC4(val) ((val & 0x1Ful) << 0) /**< Wakeup Source4 */
#define CM_EDGE4(val) ((val & 0x3ul) << 5) /**< Wakeup Source4 Edge */
#define CM_EEEN4 (0x01ul << 7) /**< Wakeup Source4 Enable */
#define CM_EESRC5(val) ((val & 0x1Ful) << 8) /**< Wakeup Source5 */
#define CM_EDGE5(val) ((val & 0x3ul) << 13) /**< Wakeup Source5 Edge */
#define CM_EEEN5 (0x01ul << 15) /**< Wakeup Source5 Enable */
#define CM_EESRC6(val) ((val & 0x1Ful) << 16) /**< Wakeup Source6 */
#define CM_EDGE6(val) ((val & 0x3ul) << 21) /**< Wakeup Source6 Edge */
#define CM_EEEN6 (0x01ul << 23) /**< Wakeup Source6 Enable */
#define CM_EESRC7(val) ((val & 0x1Ful) << 24) /**< Wakeup Source7 */
#define CM_EDGE7(val) ((val & 0x3ul) << 29) /**< Wakeup Source7 Edge */
#define CM_EEEN7 (0x01ul << 31) /**< Wakeup Source7 Enable */
#define CM_EESRC_EXI0 (0) /**< Wake-up Source - EXI0 */
#define CM_EESRC_EXI1 (1) /**< Wake-up Source - EXI1 */
#define CM_EESRC_EXI2 (2) /**< Wake-up Source - EXI2 */
#define CM_EESRC_EXI3 (3) /**< Wake-up Source - EXI3 */
#define CM_EESRC_EXI4 (4) /**< Wake-up Source - EXI4 */
#define CM_EESRC_EXI5 (5) /**< Wake-up Source - EXI5 */
#define CM_EESRC_EXI6 (6) /**< Wake-up Source - EXI6 */
#define CM_EESRC_EXI7 (7) /**< Wake-up Source - EXI7 */
#define CM_EESRC_EXI8 (8) /**< Wake-up Source - EXI8 */
#define CM_EESRC_EXI9 (9) /**< Wake-up Source - EXI9 */
#define CM_EESRC_EXI10 (10) /**< Wake-up Source - EXI10 */
#define CM_EESRC_EXI11 (11) /**< Wake-up Source - EXI11 */
#define CM_EESRC_EXI12 (12) /**< Wake-up Source - EXI12 */
#define CM_EESRC_EXI13 (13) /**< Wake-up Source - EXI13 */
#define CM_EESRC_EXI14 (14) /**< Wake-up Source - EXI14 */
#define CM_EESRC_EXI15 (15) /**< Wake-up Source - EXI15 */
#define CM_EESRC_EXI16 (16) /**< Wake-up Source - EXI16 */
#define CM_EESRC_EXI17 (17) /**< Wake-up Source - EXI17 */
#define CM_EESRC_EXI18 (18) /**< Wake-up Source - EXI18 */
#define CM_EESRC_EXI19 (19) /**< Wake-up Source - EXI19 */
#define CM_EESRC_EXI20 (20) /**< Wake-up Source - EXI20 */
#define CM_EESRC_EXI21 (21) /**< Wake-up Source - EXI21 */
#define CM_EESRC_EXI22 (22) /**< Wake-up Source - EXI22 */
#define CM_EESRC_EXI23 (23) /**< Wake-up Source - EXI23 */
#define CM_EESRC_SPI0 (24) /**< Wake-up Source - SPI0 */
#define CM_EESRC_USARTRX0 (25) /**< Wake-up Source - USARTRX0 */
/******************************************************************************
* WIMSCR: Wake-up Interrupt Mask Set/Clear Register
* WISR : Wake-up Raw Interrupt Status Register
* WMISR : Wake-up Masked Interrupt Status Register
* WICR : Wake-up Interrupt Clear Register
******************************************************************************/
#define CM_EE0 (0x01ul << 0) /**< Wake-up interrupt 0 en/disable */
#define CM_EE1 (0x01ul << 1) /**< Wake-up interrupt 1 en/disable */
#define CM_EE2 (0x01ul << 2) /**< Wake-up interrupt 2 en/disable */
#define CM_EE3 (0x01ul << 3) /**< Wake-up interrupt 3 en/disable */
#define CM_EE4 (0x01ul << 4) /**< Wake-up interrupt 4 en/disable */
#define CM_EE5 (0x01ul << 5) /**< Wake-up interrupt 5 en/disable */
#define CM_EE6 (0x01ul << 6) /**< Wake-up interrupt 6 en/disable */
#define CM_EE7 (0x01ul << 7) /**< Wake-up interrupt 7 en/disable */
/******************************************************************************
* NISR : NVIC Interrupt Status Register
******************************************************************************/
#define CM_NVIC(n) (0x01ul << n) /**< NVIC interrupt 0 status */
#define CM_NVIC0 (0x01ul << 0) /**< NVIC interrupt 0 status */
#define CM_NVIC1 (0x01ul << 1) /**< NVIC interrupt 1 status */
#define CM_NVIC2 (0x01ul << 2) /**< NVIC interrupt 2 status */
#define CM_NVIC3 (0x01ul << 3) /**< NVIC interrupt 3 status */
#define CM_NVIC4 (0x01ul << 4) /**< NVIC interrupt 4 status */
#define CM_NVIC5 (0x01ul << 5) /**< NVIC interrupt 5 status */
#define CM_NVIC6 (0x01ul << 6) /**< NVIC interrupt 6 status */
#define CM_NVIC7 (0x01ul << 7) /**< NVIC interrupt 7 status */
#define CM_NVIC8 (0x01ul << 8) /**< NVIC interrupt 8 status */
#define CM_NVIC9 (0x01ul << 9) /**< NVIC interrupt 9 status */
#define CM_NVIC10 (0x01ul << 10) /**< NVIC interrupt 10 status */
#define CM_NVIC11 (0x01ul << 11) /**< NVIC interrupt 11 status */
#define CM_NVIC12 (0x01ul << 12) /**< NVIC interrupt 12 status */
#define CM_NVIC13 (0x01ul << 13) /**< NVIC interrupt 13 status */
#define CM_NVIC14 (0x01ul << 14) /**< NVIC interrupt 14 status */
#define CM_NVIC15 (0x01ul << 15) /**< NVIC interrupt 15 status */
#define CM_NVIC16 (0x01ul << 16) /**< NVIC interrupt 16 status */
#define CM_NVIC17 (0x01ul << 17) /**< NVIC interrupt 17 status */
#define CM_NVIC18 (0x01ul << 18) /**< NVIC interrupt 18 status */
#define CM_NVIC19 (0x01ul << 19) /**< NVIC interrupt 19 status */
#define CM_NVIC20 (0x01ul << 20) /**< NVIC interrupt 20 status */
#define CM_NVIC21 (0x01ul << 21) /**< NVIC interrupt 21 status */
#define CM_NVIC22 (0x01ul << 22) /**< NVIC interrupt 22 status */
#define CM_NVIC23 (0x01ul << 23) /**< NVIC interrupt 23 status */
#define CM_NVIC24 (0x01ul << 24) /**< NVIC interrupt 24 status */
#define CM_NVIC25 (0x01ul << 25) /**< NVIC interrupt 25 status */
#define CM_NVIC26 (0x01ul << 26) /**< NVIC interrupt 26 status */
#define CM_NVIC27 (0x01ul << 27) /**< NVIC interrupt 27 status */
#define CM_NVIC28 (0x01ul << 28) /**< NVIC interrupt 28 status */
#define CM_NVIC29 (0x01ul << 29) /**< NVIC interrupt 29 status */
#define CM_NVIC30 (0x01ul << 30) /**< NVIC interrupt 30 status */
#define CM_NVIC31 (0x01ul << 31) /**< NVIC interrupt 31 status */
// ------------------------------------------------------------------------------------------------
// ----- COMPARATOR Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : ID Register
******************************************************************************/
#define COMP_IPIDCODE_MASK (0x03FFFFFFul << 0) /**< IPIDCODE mask */
#define COMP_IPIDCODE (0x00010038 << 0) /**< IPIDCODE value */
/******************************************************************************
* CEDR : Clock Enable/Disable Register
******************************************************************************/
#define COMP_CLKEN (0x01ul << 0) /**< IP Clock */
#define COMP_DBGEN (0x01ul << 31) /**< DBGEN */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define COMP_SWRST (0x01ul << 0) /**< Software Reset */
/******************************************************************************
* CR0 : Control Register
******************************************************************************/
#define COMP_COMP0EN (0x01ul << 0) /**< Comparator0 enable */
#define COMP_COMP0PINSEL (0x01ul << 1) /**< Positive input select */
#define COMP_COMP0NINSEL (0x01ul << 2) /**< Negative input select */
#define COMP_COMP0EDGESEL(val) ((val & 0x03ul) << 3) /**< Edge selection */
#define COMP_COMP1EN (0x01ul << 8) /**< Comparator1 enable */
#define COMP_COMP1PINSEL (0x01ul << 9) /**< Positive input select */
#define COMP_COMP1NINSEL (0x01ul << 10) /**< Negative input select */
#define COMP_COMP1EDGESEL(val) ((val & 0x03ul) << 11) /**< Edge selection */
#define COMP_COMP2EN (0x01ul << 16) /**< Comparator2 enable */
#define COMP_COMP2PINSEL (0x01ul << 17) /**< Positive input select */
#define COMP_COMP2NINSEL (0x01ul << 18) /**< Negative input select */
#define COMP_COMP2EDGESEL(val) ((val & 0x03ul) << 19) /**< Edge selection */
#define COMP_COMP3EN (0x01ul << 24) /**< Comparator3 enable */
#define COMP_COMP3PINSEL (0x01ul << 25) /**< Positive input select */
#define COMP_COMP3NINSEL (0x01ul << 26) /**< Negative input select */
#define COMP_COMP3EDGESEL(val) ((val & 0x03ul) << 27) /**< Edge selection */
/******************************************************************************
* CR2 : Control Register 2
******************************************************************************/
#define COMP_CHKSRCSEL0(val) ((val & 0x07ul) << 0) /**< Check source selection */
#define COMP_COMP0IMCEN (0x01ul << 3) /**< dege detection for IMC */
#define COMP_COMP0PPDEN(val) ((val & 0x07ul) << 4) /**< edte detection for PPD */
#define COMP_CHKSRCSEL1(val) ((val & 0x07ul) << 8) /**< Check source selection */
#define COMP_COMP1IMCEN (0x01ul << 11) /**< dege detection for IMC */
#define COMP_COMP1PPDEN(val) ((val & 0x07ul) << 12) /**< edte detection for PPD */
#define COMP_CHKSRCSEL2(val) ((val & 0x07ul) << 16) /**< Check source selection */
#define COMP_COMP2IMCEN (0x01ul << 19) /**< dege detection for IMC */
#define COMP_COMP2PPDEN(val) ((val & 0x07ul) << 20) /**< edte detection for PPD */
#define COMP_CHKSRCSEL3(val) ((val & 0x07ul) << 24) /**< Check source selection */
#define COMP_COMP3IMCEN (0x01ul << 27) /**< dege detection for IMC */
#define COMP_COMP3PPDEN(val) ((val & 0x07ul) << 28) /**< edte detection for PPD */
/******************************************************************************
* SR : Comparator Output Status Register
******************************************************************************/
#define COMP_EDGEDETSTATUS0 (0x01ul << 0) /**< COMP output detect status */
#define COMP_EDGEDETSTATUS1 (0x01ul << 1) /**< COMP output detect status */
#define COMP_EDGEDETSTATUS2 (0x01ul << 2) /**< COMP output detect status */
#define COMP_EDGEDETSTATUS3 (0x01ul << 3) /**< COMP output detect status */
#define COMP_COMPOUTSTATUS0 (0x01ul << 16)/**< COMP output(real time) status*/
#define COMP_COMPOUTSTATUS1 (0x01ul << 17)/**< COMP output(real time) status*/
#define COMP_COMPOUTSTATUS2 (0x01ul << 18)/**< COMP output(real time) status*/
#define COMP_COMPOUTSTATUS3 (0x01ul << 19)/**< COMP output(real time) status*/
/******************************************************************************
* IMSCR : Interrupt Mask Set/Clear Register
* RISR : Raw Interrupt Status Register
* MISR : Masked Interrupt Status Register
* ICR : Interrupt Clear Register
******************************************************************************/
#define COMP_EDGEDET0 (0x01ul << 0) /**< COMP output detect */
#define COMP_EDGEDET1 (0x01ul << 1) /**< COMP output detect */
#define COMP_EDGEDET2 (0x01ul << 2) /**< COMP output detect */
#define COMP_EDGEDET3 (0x01ul << 3) /**< COMP output detect */
// ------------------------------------------------------------------------------------------------
// ----- GPIO Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* OER, ODR, OSR :
* WODR, SODR, CODR, ODSR, PDSR, MDER, MDDR : PIO Registers, Status Register and
* MDSR, CSR, SR, IER, IDR, IMR : Interrupt Registers
******************************************************************************/
#define GPIO_P0 (0x01ul << 0) /**< GPIO 0 pin */
#define GPIO_P1 (0x01ul << 1) /**< GPIO 1 pin */
#define GPIO_P2 (0x01ul << 2) /**< GPIO 2 pin */
#define GPIO_P3 (0x01ul << 3) /**< GPIO 3 pin */
#define GPIO_P4 (0x01ul << 4) /**< GPIO 4 pin */
#define GPIO_P5 (0x01ul << 5) /**< GPIO 5 pin */
#define GPIO_P6 (0x01ul << 6) /**< GPIO 6 pin */
#define GPIO_P7 (0x01ul << 7) /**< GPIO 7 pin */
#define GPIO_P8 (0x01ul << 8) /**< GPIO 8 pin */
#define GPIO_P9 (0x01ul << 9) /**< GPIO 9 pin */
#define GPIO_P10 (0x01ul << 10) /**< GPIO 10 pin */
#define GPIO_P11 (0x01ul << 11) /**< GPIO 11 pin */
#define GPIO_P12 (0x01ul << 12) /**< GPIO 12 pin */
#define GPIO_P13 (0x01ul << 13) /**< GPIO 13 pin */
#define GPIO_P14 (0x01ul << 14) /**< GPIO 14 pin */
#define GPIO_P15 (0x01ul << 15) /**< GPIO 15 pin */
#define GPIO_P16 (0x01ul << 16) /**< GPIO 16 pin */
#define GPIO_P17 (0x01ul << 17) /**< GPIO 17 pin */
#define GPIO_P18 (0x01ul << 18) /**< GPIO 18 pin */
#define GPIO_P19 (0x01ul << 19) /**< GPIO 19 pin */
#define GPIO_P20 (0x01ul << 20) /**< GPIO 20 pin */
#define GPIO_P21 (0x01ul << 21) /**< GPIO 21 pin */
#define GPIO_P22 (0x01ul << 22) /**< GPIO 22 pin */
#define GPIO_P23 (0x01ul << 23) /**< GPIO 23 pin */
#define GPIO_P24 (0x01ul << 24) /**< GPIO 24 pin */
#define GPIO_P25 (0x01ul << 25) /**< GPIO 25 pin */
#define GPIO_P26 (0x01ul << 26) /**< GPIO 26 pin */
#define GPIO_P27 (0x01ul << 27) /**< GPIO 27 pin */
#define GPIO_P28 (0x01ul << 28) /**< GPIO 28 pin */
#define GPIO_P29 (0x01ul << 29) /**< GPIO 29 pin */
#define GPIO_P30 (0x01ul << 30) /**< GPIO 30 pin */
#define GPIO_P31 (0x01ul << 31) /**< GPIO 31 pin */
/******************************************************************************
* IDR : ID Register
******************************************************************************/
#define GPIO_IPIDCODE_MASK (0x03FFFFFFul << 0) /**< IPIDCODE mask */
#define GPIO_IPIDCODE (0x00010020 << 0) /**< IPIDCODE value */
/******************************************************************************
* CEDR : Clock Enable/Disable Register
******************************************************************************/
#define GPIO_CLKEN (0x01ul << 0) /**< GPIO Clock enable */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define GPIO_SWRST (0x01ul << 0) /**< GPIO Software Reset */
// ------------------------------------------------------------------------------------------------
// ----- IFC Bit/Field -----
// ------------------------------------------------------------------------------------------------
/********************************************************************************
* IDR : ID Register
*******************************************************************************/
#define IFC_IDCODE_MASK (0x3FFFFFF << 0) /**< IDCODE mask */
#define IFC_IDCODE (0x00020039ul << 0) /**< flash ID code */
/*******************************************************************************
* CEDR : Clock Enable/Disable Register
******************************************************************************/
#define IFC_CLKEN (0x01ul << 0) /**< flash clock enable */
/*******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define IFC_SWRST (0x01ul << 0) /**< software reset */
/*******************************************************************************
* CR Register
******************************************************************************/
#define IFC_START (0x01ul << 0) /**< flash operation (P/ER) start bit*/
#define IFC_CMD(val) ((0x7ul & val) << 4)
#define IFC_CMD_MASK (0x7ul << 4)
#define IFC_NP (0x01ul) /**< flash normal program */
#define IFC_PE (0x02ul) /**< flash page erase */
#define IFC_SE (0x03ul) /**< flash sector erase */
#define IFC_CE (0x04ul) /**< flash chip erase */
#define IFC_SOP (0x05ul) /**< flash smart option program */
#define IFC_SOE (0x06ul) /**< flash smart option erase */
/*******************************************************************************
* MR Register
******************************************************************************/
#define IFC_BACEN (0x01ul << 0) /**< Boot area enable */
#define IFC_FSMODE (0x01ul << 7) /**< flash high speed mode selection */
/******************************************************************************
* IMSCR : Interrupt Mask Set/Clear Register
* RISR : Raw Interrupt Status Register
* MISR : Masked Interrupt Status Register
* ICR : Interrupt Clear Register
******************************************************************************/
#define IFC_END (0x01ul << 0) /**< Sable */
#define IFC_ERR0 (0x01ul << 8) /**< ESCLK fail status end */
#define IFC_ERR1 (0x01ul << 9) /**< ESCLK fail (clock monitor) */
#define IFC_ERR2 (0x01ul << 10) /**< EMCLk fail status end */
/*******************************************************************************
* SR : Status Register
******************************************************************************/
#define IFC_BUSY (0x01ul << 0) /**< Busy flag */
/*******************************************************************************
* AR : Address Register
******************************************************************************/
#define IFC_ADDR_MASK (0xFFFFFFFFul << 0)
#define IFC_ADDR(val) ((0xFFFFFFFFul & val) << 0)
#define IFC_SOCADDR (0x000000C0ul << 0)
#define IFC_SOPADDR (0x000000C4ul << 0)
/*******************************************************************************
* KR : KEY Registers
******************************************************************************/
#define IFC_KEY_MASK (0xFFFFFFFF << 0)
#define IFC_KEYDAT(val) ((0xFFFFFFFF & val) << 0)
#define IFC_KEY (0x5A5A5A5Aul <<0)
/*******************************************************************************
* SOPSR : Smart Option Protection Status Register
******************************************************************************/
#define IFC_NJTAGP (0x01ul << 8)
#define IFC_NHWP (0x01ul << 17)
#define IFC_NSRP (0x01ul << 27)
#define IFC_NHWPA0 (0x01ul << 4)
#define IFC_NHWPA1 (0x01ul << 5)
#define IFC_NHWPA2 (0x01ul << 6)
#define IFC_NHWPA3 (0x01ul << 7)
#define IFC_NHWPA_ALL (0x0Ful << 4)
/*******************************************************************************
* SOCSR : Smart Option Configuration Status Register
*******************************************************************************/
#define IFC_POCCS (0x01ul << 0)
#define IFC_SO_EMCLK (0x00ul << 0)
#define IFC_SO_IMCLK (0x01ul << 0)
#define IFC_XIN (0x01ul << 2)
#define IFC_XOUT (0x01ul << 3)
#define IFC_BTDIV(val) ((0xFul & val) << 12)
#define IFC_BTDIV1 (0x03ul)
#define IFC_BTDIV2 (0x04ul)
#define IFC_BTDIV4 (0x05ul)
#define IFC_BTDIV8 (0x06ul)
#define IFC_BTDIV16 (0x07ul)
#define IFC_BTDIV32 (0x08ul)
#define IFC_BTDIV64 (0x09ul)
#define IFC_BTDIV128 (0x0Aul)
#define IFC_BTDIV256 (0x0Bul)
#define IFC_BTDIV512 (0x0Cul)
#define IFC_BTDIV1024 (0x0Dul)
#define IFC_BTDIV2048 (0x0Eul)
#define IFC_BTDIV4096 (0x0Ful)
/*******************************************************************************
* IOTR : Internal OSC Trimming Register
******************************************************************************/
#define IFC_OSC0(val) ((0x7Ful & val) << 0)
#define IFC_IOTKEY ((0x53 & 0xFF) << 24)
// ------------------------------------------------------------------------------------------------
// ----- IMC Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : Clock Manager ID Register
******************************************************************************/
#define IMC_IDCODE (0x00010012ul << 0) /**< ID Code value */
/******************************************************************************
* CEDR : Clock En/disable Register
******************************************************************************/
#define IMC_CLKEN (0x01ul << 0) /**< Clock Enable */
#define IMC_DBGEN (0x01ul << 31) /**< Debug Enable */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define IMC_SWRST (0x01ul << 0) /**< Software Reset */
/*******************************************************************************
* CR0 : Inverter Motor Control Register 0
*******************************************************************************/
#define IMC_IMEN (0x01ul << 0) /**< Inverter Motor Enable Bit */
#define IMC_IMMODE (0x01ul << 1) /**< Inverter Motor Mode Bit */
#define IMC_WMODE (0x01ul << 2) /**< Write Mode of Compare Register */
#define IMC_PWMSWAP (0x01ul << 3) /**< Swapping of PWMxUx and PWMxDx */
#define IMC_PWMPOLU (0x01ul << 4) /**< Polarity of PWM in PWMxU0/1/2 */
#define IMC_PWMPOLD (0x01ul << 5) /**< Polarity of PWM in PWMxD0/1/2 */
#define IMC_ESELPWMOFF(val) (((val) & 0x03) << 6)/**< PWMxOFF Active Select */
#define IMC_IMFILTER(val) (((val) & 0x07) << 8)/**< Filter Clock Selection of PWMxOFFP */
#define IMC_PWMOFFEN (0x01ul << 12) /**< PWMxOFF Enable Bit */
#define IMC_PWMOUTOFFEN (0x01ul << 13) /**< PWM output Disable by PWMxOFF */
#define IMC_PWMOUTEN (0x01ul << 14) /**< PWM output Enable Bit */
#define IMC_PWMOUTOFFENBYCOMP (0x01ul << 15) /**< PWM output Enable by comparator status */
#define IMC_IMCLKSEL(val) (((val) & 0x07) << 16) /**< IMCLK Selection */
#define IMC_NUMSKIP(val) (((val) & 0x1F) << 20) /**< Number of Skip for Motor Match Interrupt */
#define IMC_SYNCSEL(val) (((val) & 0x03) << 26) /**< Synchronous write */
#define IMC_PACRWM (0x01ul << 28) /**< PhaseA Compare Register Write Mode */
#define IMC_PBCRWM (0x01ul << 29) /**< PhaseB Compare Register Write Mode */
#define IMC_PCCRWM (0x01ul << 30) /**< PhaseC Compare Register Write Mode */
/*******************************************************************************
* CR1 : Inverter Motor Control Register 1
*******************************************************************************/
#define IMC_PWMxD2EN (0x01ul << 0) /**< PWMxD2 PWM Output Disable */
#define IMC_PWMxD1EN (0x01ul << 1) /**< PWMxD1 PWM Output Disable */
#define IMC_PWMxD0EN (0x01ul << 2) /**< PWMxD0 PWM Output Disable */
#define IMC_PWMxU2EN (0x01ul << 3) /**< PWMxU2 PWM Output Disable */
#define IMC_PWMxU1EN (0x01ul << 4) /**< PWMxU1 PWM Output Disable */
#define IMC_PWMxU0EN (0x01ul << 5) /**< PWMxU0 PWM Output Disable */
#define IMC_PWMxD2LEVEL (0x01ul << 8) /**< PWMxD2 Output Level: High */
#define IMC_PWMxD1LEVEL (0x01ul << 9) /**< PWMxD1 Output Level: High */
#define IMC_PWMxD0LEVEL (0x01ul << 10) /**< PWMxD0 Output Level: High */
#define IMC_PWMxU2LEVEL (0x01ul << 11) /**< PWMxU2 Output Level: High */
#define IMC_PWMxU1LEVEL (0x01ul << 12) /**< PWMxU1 Output Level: High */
#define IMC_PWMxU0LEVEL (0x01ul << 13) /**< PWMxU0 Output Level: High */
#define IMC_PWMxD2DT (0x01ul << 16) /**< PWMxD2 Deadtime insert */
#define IMC_PWMxD1DT (0x01ul << 17) /**< PWMxD1 Deadtime insert */
#define IMC_PWMxD0DT (0x01ul << 18) /**< PWMxD0 Deadtime insert */
#define IMC_PWMxU2DT (0x01ul << 19) /**< PWMxU2 Deadtime insert */
#define IMC_PWMxU1DT (0x01ul << 20) /**< PWMxU1 Deadtime insert */
#define IMC_PWMxU0DT (0x01ul << 21) /**< PWMxU0 Deadtime insert */
/*******************************************************************************
* CNTR : Inverter motor Counter Register
*******************************************************************************/
#define IMC_CV(val) (((val) & 0x0FFFF) << 0) /**< Count value */
/*******************************************************************************
* SR : Inverter Motor Status Register
*******************************************************************************/
#define IMC_FAULTSTAT (0x01ul << 0) /**< Status of PWM Output:High-Z */
#define IMC_UPDOWNSTAT (0x01ul << 1) /**< Status of PWM Down Counting */
#define IMC_COMPEDGEDET (0x01ul << 2) /**< Status of Comparator edge detect*/
/******************************************************************************
* IMSCR : Interrupt Mask Set/Clear Register
* RISR : Raw Interrupt Status Register
* MISR : Interrupt Status Register
* ICR : Interrupt Clear Register
******************************************************************************/
#define IMC_FAULT (0x01ul << 0)
#define IMC_ZERO (0x01ul << 6)
#define IMC_TOP (0x01ul << 7)
#define IMC_ADCRM0 (0x01ul << 8)
#define IMC_ADCFM0 (0x01ul << 9)
#define IMC_ADCRM1 (0x01ul << 10)
#define IMC_ADCFM1 (0x01ul << 11)
#define IMC_ADCRM2 (0x01ul << 12)
#define IMC_ADCFM2 (0x01ul << 13)
/*******************************************************************************
* TCR : Top Compare Register
*******************************************************************************/
#define IMC_TOPCMPDATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
/*******************************************************************************
* DTCR : Deadtime compare Register
*******************************************************************************/
#define IMC_DTCMPDATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
/*******************************************************************************
* ASTSR : ADC Start Signal Select Register
*******************************************************************************/
#define IMC_TOPCMPSEL (0x01ul << 0)
/**< ADC Start Trigger Signal by TOPCMP Match */
#define IMC_0SEL (0x01ul << 1)
/**< ADC Start Trigger Signal by Counter Zero Match */
#define IMC_ADCCMPR0SEL (0x01ul << 2)
/**< ADC Start Trigger Signal by ADCCMPR0 Match */
#define IMC_ADCCMPF0SEL (0x01ul << 3)
/**< ADC Start Trigger Signal by ADCCMPF0 Match */
#define IMC_ADCCMPR1SEL (0x01ul << 4)
/**< ADC Start Trigger Signal by ADCCMPR1 Match */
#define IMC_ADCCMPF1SEL (0x01ul << 5)
/**< ADC Start Trigger Signal by ADCCMPF1 Match */
#define IMC_ADCCMPR2SEL (0x01ul << 6)
/**< ADC Start Trigger Signal by ADCCMPR2 Match */
#define IMC_ADCCMPF2SEL (0x01ul << 7)
/**< ADC Start Trigger Signal by ADCCMPF2 Match */
/*******************************************************************************
* PACRR : Phase A compare register for Rising
* PBCRR : Phase B compare register for Rising
* PCCRR : Phase C compare register for Rising
*******************************************************************************/
#define IMC_PACMPRDATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
#define IMC_PBCMPRDATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
#define IMC_PCCMPRDATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
/*******************************************************************************
* PACFR : Phase A compare register for Rising
* PBCFR : Phase B compare register for Rising
* PCCFR : Phase C compare register for Rising
*******************************************************************************/
#define IMC_PACMPFDATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
#define IMC_PBCMPFDATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
#define IMC_PCCMPFDATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
/*******************************************************************************
* ASTSR : ADC Start Trigger SElect Rising
*******************************************************************************/
#define IMC_TOPCMPSEL (0x01ul << 0)
/**< ADC Start Trigger Signal by TOPCMP Match */
#define IMC_0SEL (0x01ul << 1)
/**< ADC Start Trigger Signal by Counter Zero Match */
#define IMC_ADCCMPR0SEL (0x01ul << 2)
/**< ADC Start Trigger Signal by ADCCMPR0 Match */
#define IMC_ADCCMPF0SEL (0x01ul << 3)
/**< ADC Start Trigger Signal by ADCCMPF0 Match */
#define IMC_ADCCMPR1SEL (0x01ul << 4)
/**< ADC Start Trigger Signal by ADCCMPR1 Match */
#define IMC_ADCCMPF1SEL (0x01ul << 5)
/**< ADC Start Trigger Signal by ADCCMPF1 Match */
#define IMC_ADCCMPR2SEL (0x01ul << 6)
/**< ADC Start Trigger Signal by ADCCMPR2 Match */
#define IMC_ADCCMPF2SEL (0x01ul << 7)
/**< ADC Start Trigger Signal by ADCCMPF2 Match */
/*******************************************************************************
* ASCRR0 : ADC Start Compare Register of Rising 0
* ASCRR1 : ADC Start Compare Register of Rising 1
* ASCRR2 : ADC Start Compare Register of Rising 2
*******************************************************************************/
#define IMC_ADCCMPR0DATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
#define IMC_ADCCMPR1DATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
#define IMC_ADCCMPR2DATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
/*******************************************************************************
* ASCFR0 : ADC Start Compare Register of Falling 0
* ASCFR1 : ADC Start Compare Register of Falling 1
* ASCFR2 : ADC Start Compare Register of Falling 2
* *******************************************************************************/
#define IMC_ADCCMPF0DATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
#define IMC_ADCCMPF1DATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
#define IMC_ADCCMPF2DATA(val) (((val) & 0x0FFFF) << 0) /**< Data value */
// ------------------------------------------------------------------------------------------------
// ----- IOCONF Bit/Field -----
// ------------------------------------------------------------------------------------------------
#define IO_Port0 (0x00ul) /**< IO 0 pin */
#define IO_Port1 (0x01ul) /**< IO 1 pin */
#define IO_Port2 (0x02ul) /**< IO 2 pin */
#define IO_Port3 (0x03ul) /**< IO 3 pin */
#define IO_Port4 (0x04ul) /**< IO 4 pin */
#define IO_Port5 (0x05ul) /**< IO 5 pin */
#define IO_Port6 (0x06ul) /**< IO 6 pin */
#define IO_Port7 (0x07ul) /**< IO 7 pin */
#define IO_Port8 (0x08ul) /**< IO 8 pin */
#define IO_Port9 (0x09ul) /**< IO 9 pin */
#define IO_Port10 (0x0Aul) /**< IO 10 pin */
#define IO_Port11 (0x0Bul) /**< IO 11 pin */
#define IO_Port12 (0x0Cul) /**< IO 12 pin */
#define IO_Port13 (0x0Dul) /**< IO 13 pin */
#define IO_Port14 (0x0Eul) /**< IO 14 pin */
#define IO_Port15 (0x0Ful) /**< IO 15 pin */
#define IO_Port16 (0x10ul) /**< IO 16 pin */
#define IO_Port17 (0x11ul) /**< IO 17 pin */
#define IO_Port18 (0x12ul) /**< IO 18 pin */
#define IO_Port19 (0x13ul) /**< IO 19 pin */
#define IO_Port20 (0x14ul) /**< IO 20 pin */
#define IO_Port21 (0x15ul) /**< IO 21 pin */
#define IO_Port22 (0x16ul) /**< IO 22 pin */
#define IO_Port23 (0x17ul) /**< IO 23 pin */
#define IO_Port24 (0x18ul) /**< IO 24 pin */
#define IO_Port25 (0x19ul) /**< IO 25 pin */
#define IO_Port26 (0x1Aul) /**< IO 26 pin */
#define IO_Port27 (0x1Bul) /**< IO 27 pin */
#define IO_Port28 (0x1Cul) /**< IO 28 pin */
#define IO_Port29 (0x1Dul) /**< IO 29 pin */
#define IO_Port30 (0x1Eul) /**< IO 30 pin */
#define IO_Port31 (0x1Ful) /**< IO 31 pin */
/******************************************************************************
* MLRx : Mode Low Register x
* MHRx : Mode High Register x
******************************************************************************/
#define IOCONF_FSEL_MASK (0x3ul)
#define IOCONF_F0 (0x0) /* Function 0 - GPIO */
#define IOCONF_F1 (0x1) /* Function 1 */
#define IOCONF_F2 (0x2) /* Function 2 */
#define IOCONF_F3 (0x3) /* Function 3 */
/******************************************************************************
* PUCRx: Pull-up enable/disable
******************************************************************************/
#define IOCONF_PUCR_OFFSET(group) (0x0 + IOCONF0_OFFSET + 0x4 * (group))
#define IOCONF_PUEN(port) (0x1ul << (port)) /**< pull-up control */
#define IOCONF_PUEN_BIT(port) (port)
/******************************************************************************
* ODCRx: Open-drain enable/disable
******************************************************************************/
#define IOCONF_ODCR_OFFSET(group) (0x0 + IOCONF0_OFFSET + 0x4 * (group))
#define IOCONF_ODEN(port) (0x1ul << (port)) /**< open-drain control */
#define IOCONF_ODEN_BIT(port) (port)
// ------------------------------------------------------------------------------------------------
// ----- NVIC, SCB Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* System Handlers
******************************************************************************/
#define SystemHandler_NMI ((U32_T)0x00001F) /* NMI Handler */
#define SystemHandler_HardFault ((U32_T)0x000000) /* Hard Fault Handler */
#define SystemHandler_SVCall ((U32_T)0x01FF40) /* SVCall Handler */
#define SystemHandler_PSV ((U32_T)0x02829C) /* PSV Handler */
#define SystemHandler_SysTick ((U32_T)0x02C39A) /* SysTick Handler */
/******************************************************************************
* Vector Table Base
******************************************************************************/
#define NVIC_VECTAB_RAM ((U32_T)0x00300000)
#define NVIC_VECTAB_FLASH ((U32_T)0x00000000)
/******************************************************************************
* ENABLE, DISABLE, SET, CLEAR, ACTIVE: NVIC Interrupt Registers
******************************************************************************/
#define NVIC_INT0 (0x01ul << 0) /**< Peripheral Interrupt 0 */
#define NVIC_INT1 (0x01ul << 1) /**< Peripheral Interrupt 1 */
#define NVIC_INT2 (0x01ul << 2) /**< Peripheral Interrupt 2 */
#define NVIC_INT3 (0x01ul << 3) /**< Peripheral Interrupt 3 */
#define NVIC_INT4 (0x01ul << 4) /**< Peripheral Interrupt 4 */
#define NVIC_INT5 (0x01ul << 5) /**< Peripheral Interrupt 5 */
#define NVIC_INT6 (0x01ul << 6) /**< Peripheral Interrupt 6 */
#define NVIC_INT7 (0x01ul << 7) /**< Peripheral Interrupt 7 */
#define NVIC_INT8 (0x01ul << 8) /**< Peripheral Interrupt 8 */
#define NVIC_INT9 (0x01ul << 9) /**< Peripheral Interrupt 9 */
#define NVIC_INT10 (0x01ul << 10) /**< Peripheral Interrupt 10 */
#define NVIC_INT11 (0x01ul << 11) /**< Peripheral Interrupt 11 */
#define NVIC_INT12 (0x01ul << 12) /**< Peripheral Interrupt 12 */
#define NVIC_INT13 (0x01ul << 13) /**< Peripheral Interrupt 13 */
#define NVIC_INT14 (0x01ul << 14) /**< Peripheral Interrupt 14 */
#define NVIC_INT15 (0x01ul << 15) /**< Peripheral Interrupt 15 */
#define NVIC_INT16 (0x01ul << 16) /**< Peripheral Interrupt 16 */
#define NVIC_INT17 (0x01ul << 17) /**< Peripheral Interrupt 17 */
#define NVIC_INT18 (0x01ul << 18) /**< Peripheral Interrupt 18 */
#define NVIC_INT19 (0x01ul << 19) /**< Peripheral Interrupt 19 */
#define NVIC_INT20 (0x01ul << 20) /**< Peripheral Interrupt 20 */
#define NVIC_INT21 (0x01ul << 21) /**< Peripheral Interrupt 21 */
#define NVIC_INT22 (0x01ul << 22) /**< Peripheral Interrupt 22 */
#define NVIC_INT23 (0x01ul << 23) /**< Peripheral Interrupt 23 */
#define NVIC_INT24 (0x01ul << 24) /**< Peripheral Interrupt 24 */
#define NVIC_INT25 (0x01ul << 25) /**< Peripheral Interrupt 25 */
#define NVIC_INT26 (0x01ul << 26) /**< Peripheral Interrupt 26 */
#define NVIC_INT27 (0x01ul << 27) /**< Peripheral Interrupt 27 */
#define NVIC_INT28 (0x01ul << 28) /**< Peripheral Interrupt 28 */
#define NVIC_INT29 (0x01ul << 29) /**< Peripheral Interrupt 29 */
#define NVIC_INT30 (0x01ul << 30) /**< Peripheral Interrupt 30 */
#define NVIC_INT31 (0x01ul << 31) /**< Peripheral Interrupt 31 */
/******************************************************************************
* Priority register: NVIC Interrupt Registers
******************************************************************************/
#define NVIC_PRIORITY_0 (0x00ul)
#define NVIC_PRIORITY_1 (0x01ul)
#define NVIC_PRIORITY_2 (0x02ul)
#define NVIC_PRIORITY_3 (0x03ul)
/******************************************************************************
* CPUID : CPU ID register
******************************************************************************/
#define SCB_REVISION_MASK ((0x0Ful) << 0)
#define SCB_PARTNO_MASK ((0xFFFul)<< 4)
#define SCB_VARIANT_MASK ((0x0Ful) << 20)
#define SCB_IMPLEMENTER_MASK ((0xFFul) << 24)
#define SCB_CPUID (0x410CC200)
/******************************************************************************
* ICSR : Interrupt Control State Register
******************************************************************************/
#define SCB_RETTOBASE (0x01ul << 11)
#define SCB_ISRPENDING (0x01ul << 22) /**< Interrupt pending flag */
#define SCB_ISRPREEMPT (0x01ul << 23) /**< Pending flag active */
#define SCB_PENDSTCLR (0x01ul << 25) /**< Clear pending SysTick bit */
#define SCB_PENDSTSET (0x01ul << 26) /**< Set SysTick pending bit */
#define SCB_PENDSVCLR (0x01ul << 27) /**< Clear pending pendSV bit */
#define SCB_PENDSVSET (0x01ul << 28) /**< Set pendSV pending bit */
#define SCB_NMIPENDSET (0x01ul << 31) /**< Set NMI pending pit */
#define SCB_VECTACTIVE_MASK ((0x1FFul) << 0) /**< Active ISR number */
#define SCB_VECTPENDING_MASK ((0x3FFul) << 12) /**< Pending ISR number */
/******************************************************************************
* VTOR : Vector Table Offset Register
******************************************************************************/
#define SCB_TBLBASE (0x01ul << 29) /**< Vector Table Location */
#define SCB_TBLOFF_MASK ((0x3FFFFFul) << 7) /**< Vector Table Base Offset */
/******************************************************************************
* AIRCR : Application Interrupt and Reset Control Register
******************************************************************************/
#define SCB_VECKEY_MASK (0xFFFFul << 16) /**< AIRCR key mask */
#define SCB_VECKEY (0x5FAul << 16) /**< AIRCR key */
#define SCB_VECTRESET (0x01ul << 0) /**< System Reset (except Debug)*/
#define SCB_VECTCLRACTIVE (0x01ul << 1) /**< Clear active vector bit */
#define SCB_SYSRESETREQ (0x01ul << 2) /**< Reset signal asserted to
outer system */
#define SCB_PRIGROUP_MASK ((0x07ul) << 8) /**< Priority Group mask */
#define SCB_ENDIANESS (0x01ul << 15) /**< Data endianness bit */
/* Preemption Priority Group -----------------------------------------------*/
#define NVIC_PRIOGRP_7 ((U32_T)0x7ul) /**< 0 bits (pre), 4 bits (sub) */
#define NVIC_PRIOGRP_6 ((U32_T)0x6ul) /**< 1 bits (pre), 3 bits (sub) */
#define NVIC_PRIOGRP_5 ((U32_T)0x5ul) /**< 2 bits (pre), 2 bits (sub) */
#define NVIC_PRIOGRP_4 ((U32_T)0x4ul) /**< 3 bits (pre), 1 bits (sub) */
#define NVIC_PRIOGRP_3 ((U32_T)0x3ul) /**< 4 bits (pre), 0 bits (sub) */
/******************************************************************************
* SCR : System Control Register
******************************************************************************/
#define SCB_SLEEPONEXIT (0x01ul << 1) /**< WFE wakeup with interrupt */
#define SCB_SLEEPDEEP (0x01ul << 2) /**< Sleep Deep */
#define SCB_SEVONPEND (0x01ul << 4) /**< Sleep on exit when */
/******************************************************************************
* CCR : Configuration Control Register
******************************************************************************/
#define SCB_NONEBASETHRDENA (0x01ul << 0) /**< Thread mode from last exception */
#define SCB_USERSETMPEND (0x01ul << 1) /**< Enable Software trigger Interrupt */
#define SCB_UNALIGN_TRP (0x01ul << 3) /**< Trap for unaligned access */
#define SCB_DIV_0_TRP (0x01ul << 4) /**< Trap on Divide by 0 */
#define SCB_BFHFNMIGN (0x01ul << 8) /**< Handlers at priority -1, -2 */
#define SCB_STKALIGN (0x01ul << 9) /**< SP alignment in 8bytes */
/******************************************************************************
* SHPR : System Handler Priority Registers
******************************************************************************/
#define SCB_PRIORITY_0 (0x00ul)
#define SCB_PRIORITY_1 (0x01ul)
#define SCB_PRIORITY_2 (0x02ul)
#define SCB_PRIORITY_3 (0x03ul)
/******************************************************************************
* SHCSR : System Handler Control and State Register
******************************************************************************/
#define SCB_SVCALLPENDED (0x01ul << 15) /**< SVCall pended */
// ------------------------------------------------------------------------------------------------
// ----- OPAMP Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : ID Register
******************************************************************************/
#define OPAMP_IPIDCODE_MASK (0x03FFFFFFul << 0) /**< IPIDCODE mask */
#define OPAMP_IPIDCODE (0x0001001D << 0) /**< IPIDCODE value */
/******************************************************************************
* CEDR : Clock Enable/Disable Register
******************************************************************************/
#define OPAMP_CLKEN (0x01ul << 0) /**< OPAMP Clock enable */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define OPAMP_SWRST (0x01ul << 0) /**< Software Reset */
/******************************************************************************
* CR : Control Register
******************************************************************************/
#define OPAMP_OPA (0x01ul << 0) /**< opamp 0 enable */
/******************************************************************************
* GCR : Gain Control Register
******************************************************************************/
#define CSP_OPAMP_GV(val) ((val & 0xFul) <<0)
#define OPAMP_GCT (0x01ul << 7) /**< opamp gain control type0 */
// ------------------------------------------------------------------------------------------------
// ----- PPD Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : Clock Manager ID Register
******************************************************************************/
#define PPD_IDCODE (0x0018703ul << 0) /**< ID Code value */
/******************************************************************************
* CEDR : Clock En/disable Register
******************************************************************************/
#define PPD_CLKEN (0x01ul << 0) /**< Clock Enable */
#define PPD_DBGEN (0x01ul << 31) /**< Debug Enable */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define PPD_SWRST (0x01ul << 0) /**< Software Reset */
/******************************************************************************
* CR0 : Control Register 0
******************************************************************************/
#define PPD_PPDCLKSEL(val) (((val) & 0x07ul) << 0)
#define PPD_PPDEN (0x01ul << 3) /**< Speed Counter(SPCR) Clear */
#define PPD_PPDTYPE(val) (((val) & 0x03ul) << 4)
#define PPD_SCDCTRL (0x01ul << 6) /**< Speed Counter(SPCR) Clear */
#define PPD_PHASEA(val) (((val) & 0x07ul) << 8)
#define PPD_ESELA(val) (((val) & 0x03ul) << 11)
#define PPD_PHASEB(val) (((val) & 0x07ul) << 13)
#define PPD_ESELB(val) (((val) & 0x03ul) << 16)
#define PPD_PHASEZ(val) (((val) & 0x07ul) << 18)
#define PPD_ESELZ(val) (((val) & 0x03ul) << 21)
#define PPD_PPDFILTER(val) (((val) & 0x07ul) << 24)
#define PPD_HOLDTRIG(val) (((val) & 0x0Ful) << 28)
/******************************************************************************
* CR1 : Control Register 1
******************************************************************************/
#define PPD_PCTEN (0x01ul << 0) /**< Phase B(PBCCR) Counter Clear Bit */
#define PPD_PCTCL (0x01ul << 1) /**< Phase B(PBCCR) Counter Clear Bit */
#define PPD_PCCL (0x01ul << 2) /**< Phase B(PBCCR) Counter Clear Bit */
#define PPD_PCSYNCHCL (0x01ul << 3) /**< Phase B(PBCCR) Counter Clear Bit*/
#define PPD_PCTPRESCALE(val) (((val) & 0x0Ful) << 8)
#define PPD_SCTEN (0x01ul << 16) /**< Phase B(PBCCR) Counter Clear Bit */
#define PPD_SCTCL (0x01ul << 17) /**< Phase B(PBCCR) Counter Clear Bit */
#define PPD_SCCL (0x01ul << 18) /**< Phase B(PBCCR) Counter Clear Bit */
#define PPD_SCSYNCHCL (0x01ul << 19) /**< Phase B(PBCCR) Counter Clear Bit*/
#define PPD_SCTPRESCALE(val) (((val) & 0x0Ful) << 24)
#define PPD_PZCL (0x01ul << 31) /**< Phase B(PBCCR) Counter Clear Bit */
/******************************************************************************
* SR : Status Register
******************************************************************************/
#define PPD_DIRECTION (0x01ul << 0) /**< Direction of Motor Rotation */
#define PPD_GLITCH (0x01ul << 1) /**< Glitch Detection of PHASE A/B/Z */
#define PPD_PASTAT (0x01ul << 2) /**< Phase B status bit */
#define PPD_PBSTAT (0x01ul << 3) /**< Phase A status bit */
/******************************************************************************
* IMSCR, RISR, MISR, ICR: Interrupt Register
******************************************************************************/
#define PPD_PCMAT (0x01ul << 0) /**< Direction of Motor Rotation */
#define PPD_PCSOVF (0x01ul << 1) /**< Direction of Motor Rotation */
#define PPD_PCSUNF (0x01ul << 2) /**< Direction of Motor Rotation */
#define PPD_PCAPT (0x01ul << 3) /**< Direction of Motor Rotation */
#define PPD_PCTOVF (0x01ul << 4) /**< Direction of Motor Rotation */
#define PPD_PCCOVF (0x01ul << 5) /**< Direction of Motor Rotation */
#define PPD_PCCUNF (0x01ul << 6) /**< Direction of Motor Rotation */
#define PPD_SCMAT (0x01ul << 8) /**< Direction of Motor Rotation */
#define PPD_SCSOVF (0x01ul << 9) /**< Direction of Motor Rotation */
#define PPD_SCSUNF (0x01ul << 10) /**< Direction of Motor Rotation */
#define PPD_SCAPT (0x01ul << 11) /**< Direction of Motor Rotation */
#define PPD_SCTOVF (0x01ul << 12) /**< Direction of Motor Rotation */
#define PPD_SCCOVF (0x01ul << 13) /**< Direction of Motor Rotation */
#define PPD_SCCUNF (0x01ul << 14) /**< Direction of Motor Rotation */
/******************************************************************************
* PCR : 16bit Position Counter Register
******************************************************************************/
#define PPD_PCV(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* PCRR : 16bit Position Counter Reference Register
******************************************************************************/
#define PPD_PREFDAT(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* PCHR : 16bit Position Counter Hold Register
******************************************************************************/
#define PPD_PCHDAT(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* PCTVHR : 16bit Position Counter Timer Value Hold Register
******************************************************************************/
#define PPD_PCVTVDAT(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* PCTVR : 16bit Position Counter Timer Value Register
******************************************************************************/
#define PPD_PCTV(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* PCTR : 16bit Position Capture Timer Register
******************************************************************************/
#define PPD_PCAPTV(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* PCTHR : 16bit Position Capture Timer Hold Register
******************************************************************************/
#define PPD_PCTHR(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* SCR : 16bit Speed Counter Register
******************************************************************************/
#define PPD_SCV(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* SCRR : 16bit Speed Counter Reference Register
******************************************************************************/
#define PPD_SREFDAT(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* SCHR : 16bit Speed Counter Hold Register
******************************************************************************/
#define PPD_SCHDAT(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* SCTVHR : 16bit Speed Counter Timer Value Hold Register
******************************************************************************/
#define PPD_SCVTVDAT(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* SCTVR : 16bit Speed Counter Timer Value Register
******************************************************************************/
#define PPD_SCTV(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* SCTR : 16bit Speed Capture Timer Register
******************************************************************************/
#define PPD_SCAPTV(val) (((val) & 0x0FFFF) << 0)
/******************************************************************************
* SCTHR : 16bit Speed Capture Timer Hold Register
******************************************************************************/
#define PPD_SCTHR(val) (((val) & 0x0FFFF) << 0)
// ------------------------------------------------------------------------------------------------
// ----- PWM Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : ID Register
******************************************************************************/
#define PWM_IPIDCODE_MASK (0x03FFFFFFul << 0) /**< PWM IPIDCODE mask */
#define PWM_IPIDCODE (0x00010009 << 0) /**< PWM IPIDCODE mask */
/******************************************************************************
* CEDR : Clock Enable/Disable Register
******************************************************************************/
#define PWM_CLKEN (0x01ul << 0) /**< PWM Clock */
#define PWM_DBGEN (0x01ul << 31) /**< Debug Mode Enable */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define PWM_SWRST (0x01ul << 0) /**< Software Reset */
/******************************************************************************
* CSR : Control Set Register
* CCR : Control Clear Register
* SR : Statis Register
******************************************************************************/
#define PWM_PWMEX_MASK (0x03Ful << 24)
#define PWM_START (0x01ul << 0) /**< PWM Start */
#define PWM_UPDATE (0x01ul << 1) /**< PWM Configuration update */
#define PWM_IDLESL (0x01ul << 8) /**< Idle level for 0 */
#define PWM_OUTSL (0x01ul << 9) /**< Sample level for 0 */
#define PWM_KEEP (0x01ul << 10) /**< Dual mode for 0 */
#define PWM_PWMIM (0x01ul << 11) /**< Interval Mode */
#define PWM_PWMEX0 (0x01ul << 24) /**< PWM Extension 0 */
#define PWM_PWMEX1 (0x01ul << 25) /**< PWM Extension 1 */
#define PWM_PWMEX2 (0x01ul << 26) /**< PWM Extension 2 */
#define PWM_PWMEX3 (0x01ul << 27) /**< PWM Extension 3 */
#define PWM_PWMEX4 (0x01ul << 28) /**< PWM Extension 4 */
#define PWM_PWMEX5 (0x01ul << 29) /**< PWM Extension 5 */
/******************************************************************************
* IMSCR : Interrupt Mask Set/Clear Register
* RISR : Raw Interrupt Status Register
* MISR : Interrupt Status Register
* ICR : Interrupt Clear Register
******************************************************************************/
#define PWM_START (0x01ul << 0) /**< PWM Start Interrupt */
#define PWM_STOP (0x01ul << 1) /**< PWM Stop Interrupt */
#define PWM_PSTART (0x01ul << 2) /**< Period Start Interrupt */
#define PWM_PEND (0x01ul << 3) /**< Period End Interrupt */
#define PWM_PMATCH (0x01ul << 4) /**< Pulse Match Interrupt */
/******************************************************************************
* CDR : Clock Divider Register
******************************************************************************/
#define PWM_DIVN_MASK (0x0Ful << 0) /**< Clock Divider N */
#define PWM_DIVM_MASK (0xFFFul << 4) /**< Clock Divider M */
#define PWM_DIVN(val) (((val) & 0x0Ful) <<0) /**< Divier N */
#define PWM_DIVM(val) (((val) & 0xFFFul)<<4) /**< Divier N */
/******************************************************************************
* PRDR : Period Register
******************************************************************************/
#define PWM_PERIOD_MASK (0xFFFFul << 0) /**< Period Mask */
#define PWM_PERIOD(val) (((val) & PWM_PERIOD_MASK)) /**< Period Macro */
/******************************************************************************
* PULR : Pulse Register
******************************************************************************/
#define PWM_PULSE_MASK (0xFFFFul << 0) /**< Pulse Width Mask */
#define PWM_PULSE(val) ((val) & PWM_PULSE_MASK) /**< Pulse Writing Macro*/
// ------------------------------------------------------------------------------------------------
// ----- (SPI) Bit/Field -----
// ------------------------------------------------------------------------------------------------
/*******************************************************************************
* SSPCR0 : Control Register 0
*******************************************************************************/
#define SSP_DSS(val) (((val) & 0x0Ful) << 0) /**< Data Size Select */
#define SSP_DSS_4BIT (0x03ul << 0) /**< Data Size 4Bit Select */
#define SSP_DSS_5BIT (0x04ul << 0) /**< Data Size 5Bit Select */
#define SSP_DSS_6BIT (0x05ul << 0) /**< Data Size 6Bit Select */
#define SSP_DSS_7BIT (0x06ul << 0) /**< Data Size 7Bit Select */
#define SSP_DSS_8BIT (0x07ul << 0) /**< Data Size 8Bit Select */
#define SSP_DSS_9BIT (0x08ul << 0) /**< Data Size 9Bit Select */
#define SSP_DSS_10BIT (0x09ul << 0) /**< Data Size 10Bit Select */
#define SSP_DSS_11BIT (0x0Aul << 0) /**< Data Size 11Bit Select */
#define SSP_DSS_12BIT (0x0Bul << 0) /**< Data Size 12Bit Select */
#define SSP_DSS_13BIT (0x0Cul << 0) /**< Data Size 13Bit Select */
#define SSP_DSS_14BIT (0x0Dul << 0) /**< Data Size 14Bit Select */
#define SSP_DSS_15BIT (0x0Eul << 0) /**< Data Size 15Bit Select */
#define SSP_DSS_16BIT (0x0Ful << 0) /**< Data Size 16Bit Select */
// re-alias
#define SPI_BITS_4 (SSP_DSS_4BIT) /**< 4 Bits Per Transfer */
#define SPI_BITS_5 (SSP_DSS_5BIT) /**< 5 Bits Per Transfer */
#define SPI_BITS_6 (SSP_DSS_6BIT) /**< 6 Bits Per Transfer */
#define SPI_BITS_7 (SSP_DSS_7BIT) /**< 7 Bits Per Transfer */
#define SPI_BITS_8 (SSP_DSS_8BIT) /**< 8 Bits Per Transfer */
#define SPI_BITS_9 (SSP_DSS_9BIT) /**< 9 Bits Per Transfer */
#define SPI_BITS_10 (SSP_DSS_10BIT) /**< 10 Bits Per Transfer */
#define SPI_BITS_11 (SSP_DSS_11BIT) /**< 11 Bits Per Transfer */
#define SPI_BITS_12 (SSP_DSS_12BIT) /**< 12 Bits Per Transfer */
#define SPI_BITS_13 (SSP_DSS_13BIT) /**< 13 Bits Per Transfer */
#define SPI_BITS_14 (SSP_DSS_14BIT) /**< 14 Bits Per Transfer */
#define SPI_BITS_15 (SSP_DSS_15BIT) /**< 15 Bits Per Transfer */
#define SPI_BITS_16 (SSP_DSS_16BIT) /**< 16 Bits Per Transfer */
#define SSP_FRF(val) (((val) & 0x03ul) << 4) /**< Frame Format */
#define SSP_SPO (0x01ul << 6) /**< SSPCLK Polarity */
#define SSP_SPH (0x01ul << 7) /**< SSPCLK Phase */
#define SSP_SCR(val) (((val) & 0x0FFul) << 8)/**< Serial Clock Rate */
#define IS_SPI_BAUDRATE(BAUDRATE) (BAUDRATE <= 0xFF)
#define IS_SPI_BITNUMBER(BITNUM) (BITNUM <= SPI_BITS_16)
/*******************************************************************************
* SSPCR1 : Control Register 1
*******************************************************************************/
#define SSP_LBM (0x01ul << 0) /**< Loopback mode */
#define SSP_SSE (0x01ul << 1) /**< Synchronous Serial Port Enable */
#define SSP_MS (0x01ul << 2) /**< Master or Slave Mode Select */
#define SSP_SOD (0x01ul << 3) /**< Slave Mode Output Disable */
#define SSP_RXIFLSELFRF(val) (((val) & 0x07ul) << 4)
/**< Receive interrupt FIFO level select */
/*******************************************************************************
* SSPDR : Data Register
*******************************************************************************/
#define SSP_DATA(val) (((val) & 0x0FFFF) << 0) /**< Transmit/Receive FIFO */
#define IS_SPI_DATA(DATA) (DATA <= 0xFFFF)
/*******************************************************************************
* SSPSR : Status Register
*******************************************************************************/
#define SSP_TFE (0x01ul << 0) /**< Transmit FIFO Empty */
#define SSP_TNF (0x01ul << 1) /**< Transmit FIFO Full */
#define SSP_RNE (0x01ul << 2) /**< Receive is not Empty */
#define SSP_RFF (0x01ul << 3) /**< Receive FIFO Full */
#define SSP_BSY (0x01ul << 4) /**< PrimeCell SSP Busy Flag */
#define SPI_ALLFLAG (SSP_TFE | SSP_TNF | SSP_RNE | SSP_RFF | SSP_BSY)
#define IS_SPI_FLAG(FLAG) ((FLAG | SPI_ALLFLAG) == SPI_ALLFLAG)
/*******************************************************************************
* SSPCPSR : Clock prescale register
*******************************************************************************/
#define SSP_CPSDVSR(val) (((val) & 0x0FF) << 0) /**< Clock Prescale Devisor */
#define IS_SPI_DIVIDER(DIV) ((DIV < 255) && (DIV > 1) && ((DIV & 0x1) != 0x1))
/*******************************************************************************
* SSPIMSC : Interrupt mask set and clear register
*******************************************************************************/
#define SSP_RORIM (0x01ul << 0) /**< Receive Overrun Interrupt Mask */
#define SSP_RTIM (0x01ul << 1) /**< Receive Timeout Interrupt Mask */
#define SSP_RXIM (0x01ul << 2) /**< Receive FIFO Interrupt Mask */
#define SSP_TXIM (0x01ul << 3) /**< Transmit FIFO interrupt Mask */
#define SPI_ALLITMASK (SSP_RORIM | SSP_RTIM | SSP_RXIM | SSP_TXIM)
#define IS_SPI_ITMASK(ITMASK) ((ITMASK | SPI_ALLITMASK) == SPI_ALLITMASK)
/*******************************************************************************
* SSPRIS : Raw interrupt status register
*******************************************************************************/
#define SSP_RORRIS (0x01ul << 0)
/**< Gives the Raw Interrupt Status of the SSPRORINTR Interrupt */
#define SSP_RTRIS (0x01ul << 1)
/**< Gives the raw interrupt state of the SSPRTINTR interrupt */
#define SSP_RXRIS (0x01ul << 2)
/**< Gives the raw interrupt state of the SSPRXINTR interrupt */
#define SSP_TXRIS (0x01ul << 3)
/**< Gives the raw interrupt state of the SSPTXINTR interrupt */
/*******************************************************************************
* SSPMIS : Masked interrupt status register
*******************************************************************************/
#define SSP_RORRIS (0x01ul << 0)
/**<Gives the receive over run masked interrupt status of SSPRORINTR interrupt*/
#define SSP_RTRIS (0x01ul << 1)
/**<Gives the receive timeout masked interrupt state of SSPRTINTR interrupt */
#define SSP_RXRIS (0x01ul << 2)
/**<Gives the receive FIFO masked interrupt state of SSPRXINTR interrupt */
#define SSP_TXRIS (0x01ul << 3)
/**<Gives the transmit FIFO masked interrupt state of SSPTXINTR interrupt */
/*******************************************************************************
* SSPICR : Interrupt clear register
*******************************************************************************/
#define SSP_RORIC (0x01ul << 0) /**< Clears the SSPRORINTR interrupt*/
#define SSP_RTIC (0x01ul << 1) /**< Clears the SSPRTINTR interrupt */
/*******************************************************************************
***************************** SSP REGISTER MASK *******************************
*******************************************************************************/
#define SSP_CR0_MASK (0x0000FFFFul) /**< Control Register 0 mask */
#define SSP_CR1_MASK (0x0000007Ful) /**< Control Register 1 mask */
#define SSP_DR_MASK (0x0000FFFFul)
/**< Receive FIFO(read) and transmit FIFO data register(write) mask */
#define SSP_SR_MASK (0x0000001Ful) /**< Status register mask */
#define SSP_CPSR_MASK (0x000000FFul) /**< Clock prescale register mask */
#define SSP_IMSCR_MASK (0x0000000Ful)
/**< Interrupt mask set and clear register mask */
#define SSP_RISR_MASK (0x0000000Ful) /**< Raw interrupt status reg. mask */
#define SSP_MISR_MASK (0x0000000Ful)
/**< Masked interrupt status register mask */
#define SSP_ICR_MASK (0x00000003ul) /**< Interrupt clear register mask */
/*******************************************************************************
************************* SSP REGISTER RESET VALUE ****************************
*******************************************************************************/
#define SSP_CR0_RST (0x00000000ul) /**< Control Register 0 reset value */
#define SSP_CR1_RST (0x00000010ul) /**< Control Register 1 reset value */
#define SSP_DR_RST (0x00000000ul)
/**< Receive FIFO(read) and transmit FIFO data register(write) reset value */
#define SSP_SR_RST (0x00000003ul) /**< Status register reset value */
#define SSP_CPSR_RST (0x00000000ul)
/**< Clock prescale register reset value */
#define SSP_IMSCR_RST (0x00000000ul)
/**< Interrupt mask set and clear register reset value */
#define SSP_RISR_RST (0x00000008ul)
/**< Raw interrupt status register reset value */
#define SSP_MISR_RST (0x00000000ul)
/**< Masked interrupt status register reset value */
#define SSP_ICR_RST (0x00000000ul)
/**< Interrupt clear register reset value */
// ------------------------------------------------------------------------------------------------
// ----- SYSTICK Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* CR : Control register
******************************************************************************/
#define SYSTICK_COUNTFLAG (0x01ul << 16) /**< Systick Counter expires */
#define SYSTICK_CLKSOURCE (0x01ul << 2) /**< Systick Clock source */
#define SYSTICK_TICKINT (0x01ul << 1) /**< Systick Interrupt en/dis */
#define SYSTICK_ENABLE (0x01ul << 0) /**< Systick counter en/dis */
#define SYSTICK_CLKSOURCE_CORECLK (0x01ul << 2)
#define SYSTICK_CLKSOURCE_CORECLK_DIV8 ~(0x01ul << 2)
#define SYSTICK_COUNTER_ENABLE (0x01ul << 0)
#define SYSTICK_COUNTER_DISABLE ~(0x01ul << 0)
#define SYSTICK_COUNTER_CLEAR (0x00000000ul)
/******************************************************************************
* LDR : Reload value register
******************************************************************************/
#define SYSTICK_RELOAD_MASK (0xFFFFFFul << 0) /**< reload value mask */
#define SYSTICK_RELOAD(val) ((val & 0xFFFFFFul) << 0) /**< reload value */
/******************************************************************************
* VALR : Current value register
******************************************************************************/
#define SYSTICK_CURRENT_MASK (0xFFFFFFul << 0) /**< current value mask */
#define SYSTICK_CURRENT(val) ((val & 0xFFFFFFul) << 0) /**< current value */
/******************************************************************************
* CALIBR : Calibration value register
******************************************************************************/
#define SYSTICK_NOREF (0x01ul << 31) /**< Systick Ref clock provision */
#define SYSTICK_SKEW (0x01ul << 30) /**< Systick Cal value suitability*/
#define SYSTICK_TENMS_MASK (0xFFFFFFul << 0) /**< ten ms value mask */
#define SYSTICK_TENMS(val) ((val & 0xFFFFFFul) << 0)/**< ten ms value */
/******************************************************************************
*************************** SYSTICK Registers mask ****************************
******************************************************************************/
#define SYSTICK_CSR_MASK (0x00010007ul) /**< CSR mask */
#define SYSTICK_RVR_MASK (0x00FFFFFFul) /**< RVR mask */
#define SYSTICK_CVR_MASK (0x00FFFFFFul) /**< CVR mask */
#define SYSTICK_CALIBR_MASK (0xC0FFFFFFul) /**< CALIB mask */
/******************************************************************************
************************* SYSTICK Registers reset value ***********************
******************************************************************************/
#define SYSTICK_CSR_RST (0x00000000ul) /**< CSR reset value */
#define SYSTICK_RVR_RST (0x00000000ul) /**< RVR reset value */
#define SYSTICK_CVR_RST (0x00000000ul) /**< CVR reset value */
#define SYSTICK_CALIBR_RST (0x400186A0ul) /**< CALIB reset value */
// ------------------------------------------------------------------------------------------------
// ----- Timer/Counter Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : ID Register
******************************************************************************/
#define TC16_IPIDCODE_MASK (0x03FFFFFFul << 0) /**< IPIDCODE mask */
#define TC16_IPIDCODE (0x0011000Aul << 0) /**< IPIDCODE value */
/******************************************************************************
* CSSR : Clock Source Selection Register
******************************************************************************/
#define TC16_CLKSRC (0x01ul << 0) /**< IP Clock Source */
/******************************************************************************
* CEDR : Clock Enable/Disable Register
******************************************************************************/
#define TC16_CLKEN (0x01ul << 0) /**< IP Clock */
#define TC16_DBGEN (0x01ul << 31) /**< Debug Mode Enable */
/******************************************************************************
* SRR : Software Reset Register
******************************************************************************/
#define TC16_SWRST (0x01ul << 0) /**< Software Reset */
/******************************************************************************
* CSR : Control Set Register
* CCR : Control Clear Register
* SR : Status Register
******************************************************************************/
#define TC16_START (0x01ul << 0) /**< TC Start/Stop control */
#define TC16_UPDATE (0x01ul << 1) /**< TC Configuration update */
#define TC16_STOPHOLD (0x01ul << 2) /**< TC count hold when TC stops */
#define TC16_STOPCLEAR (0x01ul << 3) /**< TC count clear when TC stops */
#define TC16_IDLESL (0x01ul << 8) /**< TC_PWM idle level control */
#define TC16_OUTSL (0x01ul << 9) /**< TC_PWM start level control */
#define TC16_KEEP (0x01ul << 10) /**< Keep out-level when TC_PWM stops */
#define TC16_PWMIM (0x01ul << 11) /**< TC_PWM interval mode control */
#define TC16_PWMEN (0x01ul << 12) /**< TC_PWM en/disable control */
#define TC16_REPEAT (0x01ul << 13) /**< Repeat mode control */
#define TC16_OVFM (0x01ul << 14) /**< Overflow mode control */
#define TC16_ADTRIG (0x01ul << 15) /**< ADC trigger signal out control */
#define TC16_CAPTEN (0x01ul << 16) /**< Capture en/disable control */
#define TC16_CAPT_F (0x01ul << 17) /**< Capture edge type control-falling */
#define TC16_CAPT_R (0x01ul << 18) /**< Capture edge type control-rising */
#define TC16_PWMEX0 (0x01ul << 24) /**< TC_PWM extension control bit 0 */
#define TC16_PWMEX1 (0x01ul << 25) /**< TC_PWM extension control bit 1 */
#define TC16_PWMEX2 (0x01ul << 26) /**< TC_PWM extension control bit 2 */
#define TC16_PWMEX3 (0x01ul << 27) /**< TC_PWM extension control bit 3 */
#define TC16_PWMEX4 (0x01ul << 28) /**< TC_PWM extension control bit 4 */
#define TC16_PWMEX5 (0x01ul << 29) /**< TC_PWM extension control bit 5 */
/******************************************************************************
* IMSCR : Interrupt MASK Set/Clear Register
* RISR : Raw Interrupt Status Register
* MISR : Interrupt Status Register
* ICR : Interrupt Clear Register
******************************************************************************/
#define TC16_STARTI (0x01ul << 0) /**< Overflow Interrupt */
#define TC16_STOPI (0x01ul << 1) /**< Stop Interrupt */
#define TC16_PSTARTI (0x01ul << 2) /**< Period Start Interrupt */
#define TC16_PENDI (0x01ul << 3) /**< Period End Interrupt */
#define TC16_MATI (0x01ul << 4) /**< Match Interrupt */
#define TC16_OVFI (0x01ul << 5) /**< Overflow Interrupt */
#define TC16_CAPTI (0x01ul << 6) /**< Capture Interrupt */
#define TC32_STARTI (0x01ul << 0) /**< Overflow Interrupt */
#define TC32_STOPI (0x01ul << 1) /**< Stop Interrupt */
#define TC32_PSTARTI (0x01ul << 2) /**< Period Start Interrupt */
#define TC32_PENDI (0x01ul << 3) /**< Period End Interrupt */
#define TC32_MATI (0x01ul << 4) /**< Match Interrupt */
#define TC32_OVFI (0x01ul << 5) /**< Overflow Interrupt */
#define TC32_CAPTI (0x01ul << 6) /**< Capture Interrupt */
/******************************************************************************
* CDR : Clock Divider Register
******************************************************************************/
#define TC16_DIVN_MASK (0x0Ful << 0) /**< Clock Divider N mask */
#define TC16_DIVM_MASK (0x7FFul << 4) /**< Clock Divider M mask */
#define TC16_DIVN(val) (((val) & 0x0Ful) <<0) /**< Divier N value */
#define TC16_DIVM(val) (((val) & 0x7FFul)<<4) /**< Divier M value */
/******************************************************************************
* CVR : Counter Value Register
******************************************************************************/
#define TC16_COUNT(val) (((val) & 0xFFFFFFFFul) << 0) /**< Count value */
// ------------------------------------------------------------------------------------------------
// ----- USART Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR : USART ID Registers
******************************************************************************/
#define USART_IPIDCODE_MASK (0x03FFFFFFul << 0) /**< USART IPIDCODE MASK */
#define USART_IDCODE (0x0011001Bul << 0) /**< ID Code value */
/******************************************************************************
* CEDR : Clock Enable/Disable Registers
******************************************************************************/
#define USART_CLKEN (0x01ul << 0) /**< USART Clock */
#define USART_DBGEN (0x01ul << 31) /**< Debug Mode Enable */
/******************************************************************************
* SRR : USART Software Reset Register
******************************************************************************/
#define USART_SWRST (0x01ul << 0) /**< Software Reset */
/******************************************************************************
* CR : USART Control Register
******************************************************************************/
#define USART_RSTRX (0x01ul << 2) /**< Reset Receiver */
#define USART_RSTTX (0x01ul << 3) /**< Reset Transmitter */
#define USART_RXEN (0x01ul << 4) /**< Receiver Enable */
#define USART_RXDIS (0x01ul << 5) /**< Receiver Disable */
#define USART_TXEN (0x01ul << 6) /**< Transmitter Enable */
#define USART_TXDIS (0x01ul << 7) /**< Transmitter Disable */
#define USART_STTBRK (0x01ul << 9) /**< Start Break */
#define USART_STPBRK (0x01ul << 10) /**< Stop Break */
#define USART_STTTO (0x01ul << 11) /**< Start Time-out */
#define USART_SENDA (0x01ul << 12) /**< Send Address */
#define USART_STHEADER (0x01ul << 16) /**< Start Header */
#define USART_STRESP (0x01ul << 17) /**< Start Response */
#define USART_STMESSAGE (0x01ul << 18) /**< Send Response after Header*/
#define USART_RSTLIN (0x01ul << 19) /**< Reset LIN APB register */
/******************************************************************************
* MR : USART Mode Register
******************************************************************************/
/** SENDTIME : Send Time */
#define USART_SENDTIME_MASK (0x07ul << 1) /**< SENDTIME Mask */
#define USART_SENDTIME(val) (((val) & 0x07ul) << 1) /**< Writing Macro */
#define USART_SENDTIME_0 (0x00ul << 1) /**< Number of Time = 0 */
#define USART_SENDTIME_1 (0x01ul << 1) /**< Number of Time = 1 */
#define USART_SENDTIME_2 (0x02ul << 1) /**< Number of Time = 2 */
#define USART_SENDTIME_3 (0x03ul << 1) /**< Number of Time = 3 */
#define USART_SENDTIME_4 (0x04ul << 1) /**< Number of Time = 4 */
#define USART_SENDTIME_5 (0x05ul << 1) /**< Number of Time = 5 */
#define USART_SENDTIME_6 (0x06ul << 1) /**< Number of Time = 6 */
#define USART_SENDTIME_7 (0x07ul << 1) /**< Number of Time = 7 */
/** USCLKS : Clock Selection */
#define USART_CLKS_MASK (0x03ul << 4) /**< CLKS Mask */
#define USART_CLKS(val) (((val) & 0x03ul) << 4) /**< Writing Macro */
#define USART_CLKS_MCKI (0x00ul << 4) /**< (MCKI) */
#define USART_CLKS_MCKI_8 (0x01ul << 4) /**< (MCKI/8) */
#define USART_CLKS_SCK (0x02ul << 4) /**< Ext Clock (SCK) */
/** CHRL : Character Length */
#define USART_CHRL_MASK (0x03ul << 6) /**< CHRL Mask */
#define USART_CHRL(val) (((val) & 0x03ul) << 6) /**< Writing Macro */
#define USART_CHRL_5 (0x00ul << 6) /**< Five bits length */
#define USART_CHRL_6 (0x01ul << 6) /**< Six bits length */
#define USART_CHRL_7 (0x02ul << 6) /**< Seven bits length */
#define USART_CHRL_8 (0x03ul << 6) /**< Height bits length */
/** SYNC : Synchronous Mode Select */
#define USART_SYNC (0x01ul << 8) /**< Synchronous mode */
#define USART_ASYNC (0x00ul << 8) /**< Asynchronous mode */
/** PAR : Parity Type */
#define USART_PAR_MASK (0x07ul << 9) /**< PAR Mask */
#define USART_PAR(val) (((val) & 0x07ul) << 9) /**< Writing Macro */
#define USART_PAR_EVEN (0x00ul << 9) /**< Even parity */
#define USART_PAR_ODD (0x01ul << 9) /**< Odd parity */
#define USART_PAR_SPACE (0x02ul << 9) /**< Space parity(forced to 0)*/
#define USART_PAR_MARK (0x03ul << 9) /**< Mark parity(forced to 1) */
#define USART_PAR_NO (0x04ul << 9) /**< No parity */
#define USART_PAR_MULTIDROP (0x06ul << 9) /**< Multi Drop parity */
/** NBSTOP : Number of Stop Bits */
#define USART_NBSTOP_MASK (0x03ul << 12) /**< NBSTOP Mask */
#define USART_NBSTOP(val) (((val) & 0x03ul) << 12) /**< Writing Macro */
#define USART_NBSTOP_1 (0x00ul << 12) /**< 1 Stop bit */
#define USART_NBSTOP_15 (0x01ul << 12) /**< 1.5 Stop bit */
#define USART_NBSTOP_2 (0x02ul << 12) /**< 2 Stop bit */
/** CHMODE : Channel Mode */
#define USART_CHMODE_MASK (0x03ul << 14) /**< CHMODE Mask */
#define USART_CHMODE(val) (((val) & 0x03ul) << 14) /**< Writing Macro */
#define USART_CHMODE_NORMAL (0x00ul << 14) /**< Normal channel */
#define USART_CHMODE_AUTO (0x01ul << 14) /**< Automatic echo channel */
#define USART_CHMODE_LOCAL (0x02ul << 14) /**< Local loop back channel */
#define USART_CHMODE_REMOTE (0x03ul << 14) /**< Remote loop back channel*/
#define USART_SMCARDPT (0x01ul << 16) /**< Smart Card Protocol */
/** MODE9 : 9-Bit Character Length */
#define USART_MODE8 (0x00ul << 17) /**< 8-Bits Mode */
#define USART_MODE9 (0x01ul << 17) /**< 9-Bits Mode */
/** CLKO : Clock Output Select */
#define USART_CLKO (0x01ul << 18) /**< Clock Output */
#define USART_CLKI (0x00ul << 18) /**< Clock Input */
/* DSB : Data transmit direction */
#define USART_DFSB (0x01ul << 20) /**< DataFrame Start Bit */
/******************************************************************************
* IMSCR : Interrupt Mask Set/Clear Register
* RISR : Raw Interrupt Status Register
* MISR : Masked Interrupt Status Register
* ICR : Interrupt Clear Register
* SR : Status Register
******************************************************************************/
#define USART_RXRDY (0x01ul << 0) /**< Receiver ready */
#define USART_TXRDY (0x01ul << 1) /**< Transmitter ready */
#define USART_RXBRK (0x01ul << 2) /**< Receiver break */
#define USART_OVRE (0x01ul << 5) /**< Overrun Error */
#define USART_FRAME (0x01ul << 6) /**< Framing Error */
#define USART_PARE (0x01ul << 7) /**< Parity Error */
#define USART_TIMEOUT (0x01ul << 8) /**< Receiver time out */
#define USART_TXEMPTY (0x01ul << 9) /**< Transmitter empty */
#define USART_IDLE (0x01ul << 10) /**< IDLE */
#define USART_IDLEFLAG (0x01ul << 11) /**< IDLE Flag - SR only */
/******************************************************************************
* RHR : USART Receiver Holding Register
******************************************************************************/
#define USART_RXCHR_MASK (0x1FFul << 0) /**< Received Character Mask */
/******************************************************************************
* THR : USART Transmit Holding Register
******************************************************************************/
#define USART_TXCHR_MASK (0x1FFul << 0) /**< Character to be transmitted Mask*/
/******************************************************************************
* BRGR : USART Baud Rate Generator Register
******************************************************************************/
/** FRACTION */
#define USART_FRACTION_MASK (0xFul << 0) /**< Fraction Mask */
#define USART_FRACTION(val) ((0xFul & val) << 0) /**< Fraction value */
/** CD : Clock Divisor */
#define USART_CD_MASK (0xFFFul << 4) /**< CD Mask */
#define USART_CD(val) ((0xFFFul & val) << 4) /**< CD value */
#define USART_CD_DISABLE (0x00000ul <<4) /**< Disable Clock */
#define USART_CD_BYPASS (0x00001ul <<4) /**< Clk Divisor Bypass */
/******************************************************************************
* RTOR : Receiver Time-out Register
******************************************************************************/
#define USART_TO_MASK (0xFFFFul << 0) /**< Time-out value Mask*/
#define USART_TO(val) ((0xFFFFul & val) << 0) /**< Writing macro */
#define USART_TO_DISABLE (0x0000ul) /**< Disable Receiver Time-out */
/******************************************************************************
* TTGR : Transmit Time-guard Register
******************************************************************************/
#define USART_TG_MASK (0xFFul << 0) /**< Time-guard value Mask */
#define USART_TG(val) ((0xFFul & val) << 0)/**< Writing macro */
#define USART_TG_DISABLE (0x00ul << 0) /**< Disable Transmit Time-guard */
// ------------------------------------------------------------------------------------------------
// ----- WDT Bit/Field -----
// ------------------------------------------------------------------------------------------------
/******************************************************************************
* IDR: ID RegisterRegisters
******************************************************************************/
#define WDT_IPIDCODE (0x00010000ul ) /**< WDT version number */
/******************************************************************************
* CR : WDT Control Register
******************************************************************************/
#define WDT_RSTKEY_MASK (0xFFFFul << 0) /**< Restart key mask */
#define WDT_RSTKEY (0xC071ul << 0) /**< Restart key */
#define WDT_DBGEN (0x01ul << 31) /**< Debug Mode Enable */
/******************************************************************************
* MR : WDT Mode Register
******************************************************************************/
/* WDTPDIV : Clock Divider */
#define WDT_WDTPDIV_MASK (0x07ul << 0) /**< WDTPDIV Mask */
#define WDT_WDTPDIV(val) ((0x07ul & val) << 0) /**< Writing macro */
#define WDT_WDTPDIVCLK_2 (0x00ul) /**< WDTPDIVCLK / 2 */
#define WDT_WDTPDIVCLK_4 (0x01ul) /**< WDTPDIVCLK / 4 */
#define WDT_WDTPDIVCLK_8 (0x02ul) /**< WDTPDIVCLK / 8 */
#define WDT_WDTPDIVCLK_16 (0x03ul) /**< WDTPDIVCLK / 16 */
#define WDT_WDTPDIVCLK_32 (0x04ul) /**< WDTPDIVCLK / 32 */
#define WDT_WDTPDIVCLK_128 (0x05ul) /**< WDTPDIVCLK / 128 */
#define WDT_WDTPDIVCLK_256 (0x06ul) /**< WDTPDIVCLK / 256 */
#define WDT_WDTPDIVCLK_512 (0x07ul) /**< WDTPDIVCLK / 512 */
/* PCV : High Preload Counter Value */
#define WDT_PCV_MASK (0xFFFFul << 8) /**< Mask */
#define WDT_PCV(val) (((val) & 0xFFFFul) << 8) /**< Writing Macro */
/* CKEY : Clock access Key */
#define WDT_CKEY_MASK (0xFFul << 24) /**< CKEY Mask */
#define WDT_CKEY (0x37ul << 24) /**< Write Access in MR allowed */
/******************************************************************************
* OMR : WDT Overflow Mode Register
******************************************************************************/
#define WDT_WDTEN (0x01ul << 0) /**< Watchdog Enable */
#define WDT_RSTEN (0x01ul << 1) /**< Reset Enable */
#define WDT_LOCKRSTEN (0x01ul << 2) /**< Lockup reset enable */
/* OKEY : Overflow access key */
#define WDT_OKEY_MASK (0xFFFul << 4) /**< OKEY Mask */
#define WDT_OKEY (0x234ul << 4) /**< Write Access in OMR allowed */
/******************************************************************************
* SR : WDT Status Register
******************************************************************************/
/* SR Register Only */
#define WDT_PENDING (0x01ul << 8) /**< WatchDog Pending Status */
#define WDT_CLEAR_STATUS (0x01ul << 9) /**< Watchdog Clear Status */
/******************************************************************************
* IMSCR : Interrupt Mask Set/Clear Register
* RISR : Raw Interrupt Status Register
* MISR : Masked Interrupt Status Register
: ICR : Interrupt Clear Register
******************************************************************************/
#define WDT_WDTPEND (0x01ul << 0) /**< Watchdog Pending */
#define WDT_WDTOVF (0x01ul << 1) /**< Watchdog Overflow */
/******************************************************************************
* PWR : WDT Pending Window Register
******************************************************************************/
#define WDT_RSTALW (0x01ul << 0) /**< Restart allowed */
/* PWL : Pending Window Length */
#define WDT_PWL_MASK (0xFFFFul << 8) /**< PWL Mask */
#define WDT_PWL(val) (((val) & 0xFFFFul) << 8) /**< Writing Macro */
/* PWKEY : Clock access key */
#define WDT_PWKEY_MASK (0xFFul << 24) /**< PWKEY Mask */
#define WDT_PWKEY (0x91ul << 24) /**< Write Access in PWR Allowed */
/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group S3FN429 */
/** @} */ /* End of group (null) */
#ifdef __cplusplus
}
#endif
#endif // __S3FN429_H__