/**************************************************************************//**
* @file S3FM02G.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for the
* Samsung 'S3FM02G' Device Series
* @version V0.01
* @date 01. Feb 2011
*
* @note
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __S3FM02G_H
#define __S3FM02G_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup S3FM02G_Definitions S3FM02G Definitions
This file defines all structures and symbols for S3FM02G:
- registers and bitfields
- peripheral base address
- peripheral ID
- PIO definitions
@{
*/
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup S3FM02G_CMSIS S3FM02G CMSIS Definitions
Configuration of the Cortex-M3 Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ****************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** S3FM02G Specific Interrupt Numbers ********************************************************/
WDTINT_IRQn = 0, /*!< Watch-dog Timer Interrupt */
CMINT_IRQn = 1, /*!< Clock Manager Interrupt */
PFCINT_IRQn = 2, /*!< Program Flash Controller Interrupt */
DFCINT_IRQn = 3, /*!< Data Flash Controller Interrupt */
DMAINT_IRQn = 4, /*!< DMA Controller Interrupt */
FRTINT_IRQn = 5, /*!< Free-running Timer Interrupt */
WSI0INT_IRQn = 6, /*!< Wakeup source 0 */
WSI1INT_IRQn = 7, /*!< Wakeup source 1 */
IMC0INT_IRQn = 8, /*!< Inverter Motor Controller 0 Interrupt */
ENC0INT_IRQn = 9, /*!< Encoder Counter 0 Interrupt */
IMC1INT_IRQn = 10, /*!< Inverter Motor Controller 1 Interrupt */
ENC1INT_IRQn = 11, /*!< Encoder Counter 1 Interrupt */
CAN0INT_IRQn = 12, /*!< CAN0 Interrupt */
USART0INT_IRQn = 13, /*!< USART0 Interrupt */
ADC0INT_IRQn = 14, /*!< ADC0 Interrupt */
ADC1INT_IRQn = 15, /*!< ADC1 Interrupt */
SSP0INT_IRQn = 16, /*!< SSP0 Interrupt */
I2C0INT_IRQn = 17, /*!< I2C0 Interrupt */
TC0INT_IRQn = 18, /*!< Timer/Counter0 Interrupt */
PWM0INT_IRQn = 19, /*!< PWM0 Interrupt */
WSI2INT_IRQn = 20, /*!< Wakeup source 2 */
WSI3INT_IRQn = 21, /*!< Wakeup source 3 */
TC1INT_IRQn = 22, /*!< Timer/Counter1 Interrupt */
PWM1INT_IRQn = 23, /*!< PWM1 Interrupt */
USART1INT_IRQn = 24, /*!< USART1 Interrupt */
SSP1INT_IRQn = 25, /*!< SSP1 Interrupt */
I2C1INT_IRQn = 26, /*!< I2C1 Interrupt */
CAN1INT_IRQn = 27, /*!< CAN1 Interrupt */
STTINT_IRQn = 28, /*!< STT Interrupt */
USART2INT_IRQn = 29, /*!< USART2 Interrupt */
TC2INT_IRQn = 30, /*!< Timer/Counter2 Interrupt */
TC3INT_IRQn = 31, /*!< Timer/Counter3 Interrupt */
PWM2INT_IRQn = 32, /*!< PWM2 Interrupt */
WSI4INT_IRQn = 33, /*!< Wakeup source 4 */
WSI5INT_IRQn = 34, /*!< Wakeup source 5 */
PWM3INT_IRQn = 35, /*!< PWM3 Interrupt */
USART3INT_IRQn = 36, /*!< USART4 Interrupt */
GPIO0INT_IRQn = 37, /*!< GPIO 0 Interrupt */
GPIO1INT_IRQn = 38, /*!< GPIO 1 Interrupt */
TC4INT_IRQn = 39, /*!< Timer/Counter4 Interrupt */
WSI6INT_IRQn = 40, /*!< Wakeup source 6 */
WSI7INT_IRQn = 41, /*!< Wakeup source 7 */
PWM4INT_IRQn = 42, /*!< PWM4 Interrupt */
TC5INT_IRQn = 43, /*!< Timer/Counter5 Interrupt */
WSI8INT_IRQn = 44, /*!< Wakeup source 8 */
WSI9INT_IRQn = 45, /*!< Wakeup source 9 */
WSI10INT_IRQn = 46, /*!< Wakeup source 10 */
WSI11INT_IRQn = 47, /*!< Wakeup source 11 */
PWM5INT_IRQn = 48, /*!< PWM5 Interrupt */
TC6INT_IRQn = 49, /*!< Timer/Counter6 Interrupt */
WSI12INT_IRQn = 50, /*!< Wakeup source 12 */
WSI13INT_IRQn = 51, /*!< Wakeup source 13 */
WSI14INT_IRQn = 52, /*!< Wakeup source 14 */
WSI15INT_IRQn = 53, /*!< Wakeup source 15 */
PWM6INT_IRQn = 54, /*!< PWM6 Interrupt */
TC7INT_IRQn = 55, /*!< Timer/Counter7 Interrupt */
PWM7INT_IRQn = 56, /*!< PWM8 Interrupt */
GPIO2INT_IRQn = 57, /*!< GPIO 2 Interrupt */
GPIO3INT_IRQn = 58, /*!< GPIO 3 Interrupt */
OPAMPINT_IRQn = 59, /*!< OP-AMP interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/*@}*/ /* end of group S3FM02G_CMSIS */
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
#include "system_S3FM02G.h" /* S3FM02G System */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
/** @addtogroup S3FM02G_Peripherals S3FM02G Peripherals
S3FM02G Device Specific Peripheral registers structures
@{
*/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- A/D Converter 0 (ADC0) ---------------------------*/
/** @addtogroup S3FM02G_ADC0 A/D Converter 0 (ADC0)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset: 0x000 (R ) ID Register */
__IO uint32_t CEDR; /*!< Offset: 0x004 (R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset: 0x008 ( W) Software Reset Register */
__O uint32_t CSR; /*!< Offset: 0x00C ( W) Control Set Register */
__O uint32_t CCR; /*!< Offset: 0x010 ( W) Control Clear Register */
__IO uint32_t CDR; /*!< Offset: 0x014 (R/W) Clock Divider Register */
__IO uint32_t MR; /*!< Offset: 0x018 (R/W) Mode Register */
__I uint32_t CCSR0; /*!< Offset: 0x01C (R ) Conversion Channel Register */
__I uint32_t CCSR1; /*!< Offset: 0x020 (R ) Conversion Channel Register */
__I uint32_t SR; /*!< Offset: 0x024 (R ) Status Register */
__IO uint32_t IMSCR; /*!< Offset: 0x028 (R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset: 0x02C (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset: 0x030 (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset: 0x034 ( W) Interrupt Clear Register */
__I uint32_t CRR0; /*!< Offset: 0x038 (R ) Conversion Result Register */
__I uint32_t CRR1; /*!< Offset: 0x03C (R ) Conversion Result Register */
__IO uint32_t GCR0; /*!< Offset: 0x040 (R/W) Gain Calibration Register */
__IO uint32_t OCR0; /*!< Offset: 0x044 (R/W) Offset Calibration Register */
__IO uint32_t GCR1; /*!< Offset: 0x048 (R/W) Gain Calibration Register */
__IO uint32_t OCR1; /*!< Offset: 0x04C (R/W) Offset Calibration Register */
__IO uint32_t DMACR; /*!< Offset: 0x050 (R/W) DMA Control Register */
} S3FM_ADC0_TypeDef;
/*@}*/ /* end of group S3FM02G_ADC0 */
/*------------- A/D Converter 1 (ADC1) ---------------------------*/
/** @addtogroup S3FM02G_ADC1 A/D Converter 0 (ADC1)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset: 0x000 (R ) ID Register */
__IO uint32_t CEDR; /*!< Offset: 0x004 (R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset: 0x008 ( W) Software Reset Register */
__O uint32_t CSR; /*!< Offset: 0x00C ( W) Control Set Register */
__O uint32_t CCR; /*!< Offset: 0x010 ( W) Control Clear Register */
__IO uint32_t CDR; /*!< Offset: 0x014 (R/W) Clock Divider Register */
__IO uint32_t MR; /*!< Offset: 0x018 (R/W) Mode Register */
__I uint32_t CCSR; /*!< Offset: 0x01C (R ) Conversion Channel Sequence Register */
__I uint32_t SR; /*!< Offset: 0x020 (R ) Status Register */
__IO uint32_t IMSCR; /*!< Offset: 0x024 (R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset: 0x028 (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset: 0x02C (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset: 0x030 ( W) Interrupt Clear Register */
__I uint32_t CRR; /*!< Offset: 0x034 (R ) Conversion Result Register */
__IO uint32_t GCR; /*!< Offset: 0x038 (R/W) Gain Calibration Register */
__IO uint32_t OCR; /*!< Offset: 0x03C (R/W) Calibration Register */
__IO uint32_t DMACR; /*!< Offset: 0x040 (R/W) DMA Control Register */
} S3FM_ADC1_TypeDef;
/*@}*/ /* end of group S3FM02G_ADC1 */
/*------------- CAN Interface Structure ---------------------------*/
/** @addtogroup S3FM02G_CAN_IF Structure (CAN_IF)
@{
*/
typedef struct
{
__IO uint32_t TMR; /*!< Offset 0x000 (R/W) Command Register */
__IO uint32_t DAR; /*!< Offset 0x004( R/W) Data Register A Interface X */
__IO uint32_t DBR; /*!< Offset 0x008 (R/W) Data Register B Interface X */
__IO uint32_t MSKR; /*!< Offset 0x00C (R/W) Mask Register Interface X */
__IO uint32_t IR; /*!< Offset 0x010 (R/W) Identifier Register Interface X */
__IO uint32_t MCR; /*!< Offset 0x014 (R/W) Message Control Register Interface X */
__I uint32_t STPR; /*!< Offset 0x018 (R ) Stamp Register Interface X */
uint32_t ReservedA;
} S3FM_CAN_IF_TypeDef;
/*@}*/ /* end of group S3FM02G_CAN_IF */
/*------------- CAN Interface Structure ---------------------------*/
/** @addtogroup S3FM02G_CAN Structure (CAN)
@{
*/
typedef struct
{
uint32_t ReservedA[20];
__O uint32_t ECR; /*!< Offset 0x050 ( W) Enable Clock Register */
__IO uint32_t DCR; /*!< Offset 0x054 ( W) Disable Clock Register */
__IO uint32_t PMSR; /*!< Offset 0x058 (R ) Power Management Status Register */
__IO uint32_t ReservedB;
__IO uint32_t CR; /*!< Offset 0x060 ( W) Control Register */
__IO uint32_t MR; /*!< Offset 0x064 (R/W) Mode Register */
__IO uint32_t ReservedC;
__IO uint32_t CSR; /*!< Offset 0x06C ( W) Clear Status Register */
__IO uint32_t SR; /*!< Offset 0x070 (R ) Status Register */
__IO uint32_t IER; /*!< Offset 0x074 ( W) Interrupt Enable Register */
__IO uint32_t IDR; /*!< Offset 0x078 ( W) Interrupt Disable Register */
__IO uint32_t IMR; /*!< Offset 0x07C (R ) Interrupt Mask Register */
__IO uint32_t ReservedD;
__IO uint32_t ISSR; /*!< Offset 0x084 (R ) Interrupt Source Status Register */
__IO uint32_t SIER; /*!< Offset 0x088 ( W) Source Interrupt Enable Register */
__IO uint32_t SIDR; /*!< Offset 0x08C ( W) Source Interrupt Disable Register */
__IO uint32_t SIMR; /*!< Offset 0x090 (R ) Source Interrupt Mask Register */
__IO uint32_t HPIR; /*!< Offset 0x094 (R ) Highest Priority Interrupt Register*/
__IO uint32_t ERCR; /*!< Offset 0x098 (R ) Error Counter Register */
__IO uint32_t ReservedE[25];
S3FM_CAN_IF_TypeDef IF[2]; /*!< Offset 0x100 (R/W) CAN interface */
__IO uint32_t TRR; /*!< Offset 0x140 (R ) Transmission Request Register */
__IO uint32_t NDR; /*!< Offset 0x144 (R ) New Data Register */
__IO uint32_t MVR; /*!< Offset 0x148 (R ) Message Valid Register */
__IO uint32_t TSTR; /*!< Offset 0x14C (R/W) Test Register */
} S3FM_CAN_TypeDef;
/*@}*/ /* end of group S3FM02G_CAN */
/*------------- Clock Manager (CM) ---------------------------*/
/** @addtogroup S3FM02G_CM (CM)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R ) Id Register */
__O uint32_t SRR; /*!< Offset 0x004 (R ) Software Reset Register */
__O uint32_t CSR; /*!< Offset 0x008 (R ) Control Set Register */
__O uint32_t CCR; /*!< Offset 0x00C (R ) Control Clear Register */
__O uint32_t PCSR0; /*!< Offset 0x010 Peripheral Clock Set Register 0 */
__O uint32_t PCSR1; /*!< Offset 0x014 Peripheral Clock Set Register 1 */
__O uint32_t PCCR0; /*!< Offset 0x018 Peripheral Clock Clear Register 0 */
__O uint32_t PCCR1; /*!< Offset 0x01C Peripheral Clock Clear Register 1 */
__I uint32_t PCKSR0; /*!< Offset 0x020 Peripheral Clock Status Register 0 */
__I uint32_t PCKSR1; /*!< Offset 0x024 Peripheral Clock Status Register 1 */
__IO uint32_t MR0; /*!< Offset 0x028 Mode Register 0 */
__IO uint32_t MR1; /*!< Offset 0x02C Mode Register 1 */
__O uint32_t IMSCR; /*!< Offset 0x030 Interrupt Mask Set Clear Register*/
__I uint32_t RISR; /*!< Offset 0x034 Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x038 Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x03C Interrupt Clear Register */
__IO uint32_t SR; /*!< Offset 0x040 Status Register */
__IO uint32_t SCDR; /*!< Offset 0x044 System Clock Divider Register */
__IO uint32_t PCDR; /*!< Offset 0x048 Peripheral Clock Divider Register*/
__IO uint32_t FCDR; /*!< Offset 0x04C FRT Clock Divider Register */
__IO uint32_t STCDR; /*!< Offset 0x050 STT Clock Divider Register */
__IO uint32_t LCDR; /*!< Offset 0x054 LCD Clock Divider Register */
__IO uint32_t PSTR; /*!< Offset 0x058 PLL Stabilization Time Register */
__IO uint32_t PDPR; /*!< Offset 0x05C PLL Divider Parameter Register */
uint32_t ReservedA[2];
__IO uint32_t EMSTR; /*!< Offset 0x068 EMCLK Stabilization Time Register*/
__IO uint32_t ESSTR; /*!< Offset 0x06C ESCLK Stabilization Time Register*/
__IO uint32_t BTCDR; /*!< Offset 0x070 Basic Timer Register */
__IO uint32_t BTR; /*!< Offset 0x074 Basic Timer Register */
__IO uint32_t WCR0; /*!< Offset 0x078 Wakeup Control Register0 */
__IO uint32_t WCR1; /*!< Offset 0x07C Wakeup Control Register1 */
__IO uint32_t WCR2; /*!< Offset 0x080 Wakeup Control Register2 */
__IO uint32_t WCR3; /*!< Offset 0x084 Wakeup Control Register3 */
__IO uint32_t WIMSCR; /*!< Offset 0x088 Wakeup Interrupt Mask Set/Clear Register */
__I uint32_t WRISR; /*!< Offset 0x08C Wakeup Raw Interrupt Status Reg. */
__I uint32_t WMISR; /*!< Offset 0x090 Wakeup Masked Interrupt Status Register */
__O uint32_t WICR; /*!< Offset 0x094 Wakeup Interrupt Clear Register */
__IO uint32_t NISR0; /*!< Offset 0x098 NVIC Interrupt Status Register 0 */
__IO uint32_t NISR1; /*!< Offset 0x09C NVIC Interrupt Status Register 1 */
} S3FM_CM_TypeDef;
/*@}*/ /* end of group S3FM02G_CM */
/** DFC Controller Structure *****/
/*------------- DFC Controller 1 (DFC) ---------------------------*/
/** @addtogroup S3FM02G_DFC DFC Controller (DFC)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004 Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008 Software Reset Register */
__IO uint32_t CR; /*!< Offset 0x00C Control Register */
__IO uint32_t MR; /*!< Offset 0x010 Mode Register */
__IO uint32_t IMSCR; /*!< Offset 0x014 Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x018 Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x01C Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x020 Interrupt Clear Register */
__IO uint32_t AR; /*!< Offset 0x024 Address Register */
__IO uint32_t DR; /*!< Offset 0x028 Data Register */
__O uint32_t KR; /*!< Offset 0x02C Key Register */
__IO uint32_t PCR; /*!< Offset 0x030 Protection Control Register */
} S3FM_DFC_TypeDef;
/*@}*/ /* end of group S3FM02G_DFC */
/** DMA Channel Structure *****/
/*------------- DMA channel (DMA_C) ---------------------------*/
/** @addtogroup S3FM02G_DMA_C (DMA_C)
@{
*/
typedef struct
{
__IO uint32_t ISR; /*!< Offset 0x000 Channel Control Register */
__IO uint32_t ISCR; /*!< Offset 0x004 Channel Mode Register */
__IO uint32_t IDR; /*!< Offset 0x008 Channel Clear Status Register */
__IO uint32_t IDCR; /*!< Offset 0x00C Channel Status Register */
__IO uint32_t CR; /*!< Offset 0x010 Channel Interrupt Enable Register */
__I uint32_t SR; /*!< Offset 0x014 Status Register */
__I uint32_t CSR; /*!< Offset 0x018 Current Source Register */
__I uint32_t CDR; /*!< Offset 0x01C Current Destination Register */
__IO uint32_t MTR; /*!< Offset 0x020 Channel Interrupt Disable Register */
__IO uint32_t RSR; /*!< Offset 0x024 Channel Interrupt Mode Register */
uint32_t ReservedB[22];
} S3FM_DMA_CHANNEL_TypeDef;
/*@}*/ /* end of group S3FM02G_DMA_C */
/** DMA Controller Structure *****/
/*------------- DMA Controller (DMAC) ---------------------------*/
/** @addtogroup S3FM02G_DMA (DMAC)
@{
*/
typedef struct
{
S3FM_DMA_CHANNEL_TypeDef CHANNEL[6];
uint32_t Reserved[128];
__I uint32_t IDR; /*!< Offset 0x500 (R ) ID Register */
__O uint32_t SRR; /*!< Offset 0x504 ( W) Software Reset Register */
__I uint32_t CESR; /*!< Offset 0x508 (R ) Channel Enable Status Register */
__I uint32_t ISR; /*!< Offset 0x50C (R ) Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x510 ( W) Interrupt Clear Register */
}S3FM_DMAC_TypeDef;
/*@}*/ /* end of group S3FM02G_DMAC */
/** Encoder Interface Structure *****/
/*------------- Encoder Interface (ENC) ---------------------------*/
/** @addtogroup S3FM02G_ENC (ENC)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R ) Encoder Control Register 0 */
__IO uint32_t CEDR; /*!< Offset 0x004 (R/W) Encoder Control Register 1 */
__O uint32_t SRR; /*!< Offset 0x008 ( W) Encoder Control Register 0 */
__IO uint32_t CR0; /*!< Offset 0x00C (R/W) Encoder Control Register 0 */
__IO uint32_t CR1; /*!< Offset 0x010 (R/W) Encoder Control Register 1 */
__IO uint32_t SR; /*!< Offset 0x014 (R/W) Encoder Status Register */
__IO uint32_t IMSCR; /*!< Offset 0x018 (R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x01C (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x020 (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x024 ( W) Interrupt Clear Register */
__IO uint32_t PCR; /*!< Offset 0x028 (R/W) 16bit Position Counter Register */
__IO uint32_t PRR; /*!< Offset 0x02C (R/W) 16bit Position Reference Register */
__IO uint32_t SPCR; /*!< Offset 0x030 (R/W) 16bit Speed Counter Register */
__IO uint32_t SPRR; /*!< Offset 0x034 (R/W) 16bit Speed Reference Register */
__IO uint32_t PACCR; /*!< Offset 0x038 (R/W) 16bit Phase A Capture Counter Register */
__IO uint32_t PACDR; /*!< Offset 0x03C (R/W) 16bit Phase A Capture Data Register */
__IO uint32_t PBCCR; /*!< Offset 0x040 (R/W) 16bit Phase B Capture Counter Register */
__IO uint32_t PBCDR; /*!< Offset 0x044 (R/W) 16bit Phase B Capture Data Register */
} S3FM_ENC_TypeDef;
/*@}*/ /* end of group S3FM02G_ENC */
/** Free Running Timer Structure *****/
/*------------- Free Running Timer (FRT) ---------------------------*/
/** @addtogroup S3FM02G_FRT (FRT)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R ) ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004 (R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008 ( W) Software Reset Register */
__IO uint32_t CR; /*!< Offset 0x00C (R/W)Control Register */
__I uint32_t SR; /*!< Offset 0x010 (R )Status Register */
__IO uint32_t IMSCR; /*!< Offset 0x014 (R/W)Interrupt Mask Set/Clear Register*/
__I uint32_t RISR; /*!< Offset 0x018 (R )Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x01C (R )Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x020 ( W) Interrupt Clear Register */
__IO uint32_t DR; /*!< Offset 0x024 (R/W) Data Register */
__I uint32_t DBR; /*!< Offset 0x028 (R ) Data Buffer Register */
__I uint32_t CVR; /*!< Offset 0x02C (R )Counter Value Register */
} S3FM_FRT_TypeDef;
/*@}*/ /* end of group S3FM02G_FRT */
/** General Purpose IO *****/
/*------------- General Purpose IO (GPIO) ---------------------------*/
/** @addtogroup S3FM02G_GPIO (GPIO)
@{
*/
typedef struct
{
__I uint32_t IDR; /*! <Offset 0x000 (R ) ID Register */
__IO uint32_t CEDR; /*! <Offset 0x004 (R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*! <Offset 0x008 ( W) Software Reset Register */
__IO uint32_t IMSCR; /*! <Offset 0x00C (R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*! <Offset 0x010 (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*! <Offset 0x014 (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*! <Offset 0x018 ( W) Interrupt Clear Register */
__O uint32_t OER; /*! <Offset 0x01C ( W) Output Enable Register */
__O uint32_t ODR; /*! <Offset 0x020 ( W) Output Disable Register */
__I uint32_t OSR; /*! <Offset 0x024 (R ) Output Status Register */
__O uint32_t WODR; /*! <Offset 0x028 ( W) Output Enable Register */
__O uint32_t SODR; /*! <Offset 0x02C ( W) Output Disable Register */
__O uint32_t CODR; /*! <Offset 0x030 ( W) Output Status Register */
__I uint32_t ODSR; /*! <Offset 0x034 (R ) Output Enable Register */
__I uint32_t PDSR; /*! <Offset 0x038 (R ) Output Disable Register */
} S3FM_GPIO_TypeDef;
/*@}*/ /* end of group S3FM02G_GPIO */
/** INTER-INTERGRATED CIRCUIT *****/
/*------------- INTER-INTERGRATED CIRCUIT (I2C) ---------------------------*/
/** @addtogroup S3FM02G_I2C (I2C)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R ) ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004 (R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008 ( W) Software Reset Register */
__IO uint32_t CR; /*!< Offset 0x00C (R/W) Control Register */
__IO uint32_t MR; /*!< Offset 0x010 (R/W) Mode Register */
__I uint32_t SR; /*!< Offset 0x014 (R ) Status Register */
__IO uint32_t IMSCR; /*!< Offset 0x018 (R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x01C (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x020 (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x024 ( W) Interrupt Clear Register */
__IO uint32_t SDR; /*!< Offset 0x028 (R/W) Serial Data Register */
__IO uint32_t SSAR; /*!< Offset 0x02C (R/W) Serial Slave Address Register */
__IO uint32_t HSDR; /*!< Offset 0x030 (R/W) Hold/Setup Delay Register */
__IO uint32_t DMACR; /*!< Offset 0x034 (R/W) DMA Control Register */
} S3FM_I2C_TypeDef;
/*@}*/ /* end of group S3FM02G_I2C */
/** INVERTER MOTOR CONTROLLER *****/
/*------------- INVERTER MOTOR CONTROLLER (IMC) ---------------------------*/
/** @addtogroup S3FM02G_IMC (IMC)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000(R ) ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004(R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008( W) Software Reset Register */
__IO uint32_t CR0; /*!< Offset 0x00C(R/W) Inverter Motor Control Register 0 */
__IO uint32_t CR1; /*!< Offset 0x010(R/W) Inverter Motor Control Register 1 */
__I uint32_t CNTR; /*!< Offset 0x014(R ) Inverter motor Counter Register */
__IO uint32_t SR; /*!< Offset 0x018(R/W) Inverter Motor Status Register */
__IO uint32_t IMSCR; /*!< Offset 0x01C(R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x020(R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x024(R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x028( W) Interrupt Clear Register */
__IO uint32_t TCR; /*!< Offset 0x02C(R/W) Top Compare Register */
__IO uint32_t DTCR; /*!< Offset 0x030(R/W) Deadtime compare Register */
__IO uint32_t PACRR; /*!< Offset 0x034(R/W) Phase A compare register for Rising */
__IO uint32_t PBCRR; /*!< Offset 0x038(R/W) Phase B compare register for Rising */
__IO uint32_t PCCRR; /*!< Offset 0x03C(R/W) Phase C compare register for Rising */
__IO uint32_t PACFR; /*!< Offset 0x040(R/W) Phase A compare register for Falling */
__IO uint32_t PBCFR; /*!< Offset 0x044(R/W) Phase B compare register for Falling */
__IO uint32_t PCCFR; /*!< Offset 0x048(R/W) Phase C compare register for Falling */
__IO uint32_t ASTSR; /*!< Offset 0x04C(R/W) ADC Start Signal Select Register */
__IO uint32_t ASCRR0; /*!< Offset 0x050(R/W) ADC Start Compare Register of Rising0 */
__IO uint32_t ASCRR1; /*!< Offset 0x054(R/W) ADC Start Compare Register of Rising1 */
__IO uint32_t ASCRR2; /*!< Offset 0x058(R/W) ADC Start Compare Register of Rising2 */
__IO uint32_t ASCFR0; /*!< Offset 0x05C(R/W) ADC Start Compare Register of Falling0*/
__IO uint32_t ASCFR1; /*!< Offset 0x060(R/W) ADC Start Compare Register of Falling1*/
__IO uint32_t ASCFR2; /*!< Offset 0x064(R/W) ADC Start Compare Register of Falling2*/
} S3FM_IMC_TypeDef;
/*@}*/ /* end of group S3FM02G_IMC */
/** I/O CONFIGURATION *****/
/*------------- I/O CONFIGURATION (IOCONF) ---------------------------*/
/** @addtogroup S3FM02G_IOCONF (IOCONF)
@{
*/
typedef struct
{
__IO uint32_t MLR0; /*!< Offset 0x000( R/W) Mode Low Register */
__IO uint32_t MHR0; /*!< Offset 0x004(R/W) Mode High Register */
__IO uint32_t PUCR0; /*!< Offset 0x008((R/W) Pull-Up Control Register*/
__IO uint32_t ODCR0; /*!< Offset 0x00C(R/W) Open-Drain Control Register*/
__IO uint32_t MLR1; /*!< Offset 0x010(R/W) Mode Low Register*/
__IO uint32_t MHR1; /*!< Offset 0x014(R/W) Mode High Register*/
__IO uint32_t PUCR1; /*!< Offset 0x018(R/W) Pull-Up Control Register*/
__IO uint32_t ODCR1; /*!< Offset 0x01C(R/W) Open-Drain Control Register*/
__IO uint32_t MLR2; /*!< Offset 0x020((R/W) Mode Low Register */
__IO uint32_t MHR2; /*!< Offset 0x024((R/W) Mode High Register */
__IO uint32_t PUCR2; /*!< Offset 0x028((R/W) Pull-Up Control Register */
__IO uint32_t ODCR2; /*!< Offset 0x02C(R/W) Open-Drain Control Register */
__IO uint32_t MLR3; /*!< Offset 0x030(R/W) Mode Low Register */
uint32_t Reserved;
__IO uint32_t PUCR3; /*!< Offset 0x038(R/W) Pull-Up Control Register */
__IO uint32_t ODCR3; /*!< Offset 0x03C(R/W) Open-Drain Control Register */
} S3FM_IOCONF_TypeDef;
/*@}*/ /* end of group S3FM02G_IOCONF */
/** LCD CONTROLLER *****/
/*------------- LCD CONTROLLER (LCDC) ---------------------------*/
/** @addtogroup S3FM02G_LCDC (LCDC)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000(R ) ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004(R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008( W) Software Reset Register */
__IO uint32_t CR; /*!< Offset 0x00C(R/W) Control Register */
__IO uint32_t CDR; /*!< Offset 0x010(R/W) Clock Divider Register */
uint32_t Reserved[251];
__IO uint32_t DMR[40]; /*!< Offset 0x400(R/W) LCD Display Memory Register */
} S3FM_LCDC_TypeDef;
/*@}*/ /* end of group S3FM02G_LCDC */
/** OPERATIONAL AMPLIFIER *****/
/*------------- OPERATIONAL AMPLIFIER (OPAMP) ---------------------------*/
/** @addtogroup S3FM02G_OPAMP (OPAMP)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000(R ) OP-AMP ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004(R/W) OP-AMP Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008( W) OP-AMP Software Reset Register */
__IO uint32_t CR0; /*!< Offset 0x00C(R/W) OP-AMP Control Register 0 */
__IO uint32_t CR1; /*!< Offset 0x010(R/W) OP-AMP Control Register 1 */
__IO uint32_t GCR0; /*!< Offset 0x014(R/W) OP-AMP Gain Control Register 0 */
__IO uint32_t GCR1; /*!< Offset 0x018(R/W) OP-AMP Gain Control Register 1 */
__IO uint32_t IMSCR; /*!< Offset 0x01C(R/W) Interrupt Mask Set/Clear Register */
__IO uint32_t RISR; /*!< Offset 0x020(R/W) Raw Interrupt Status Register */
__IO uint32_t MISR; /*!< Offset 0x024(R/W) Masked Interrupt Status Register */
__IO uint32_t ICR; /*!< Offset 0x028(R/W) Interrupt Clear Register */
} S3FM_OPAMP_TypeDef;
/*@}*/ /* end of group S3FM02G_OPAMP */
/** PROGRAM FLASH CONTROLLER *****/
/*------------- PROGRAM FLASH CONTROLLER (PFC) ---------------------------*/
/** @addtogroup S3FM02G_PFC (PFC)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000(R ) ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004(R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008( W) Software Reset Register */
__IO uint32_t CR; /*!< Offset 0x00C(R/W) Control Register */
__IO uint32_t MR; /*!< Offset 0x010(R/W) Mode Register */
__IO uint32_t IMSCR; /*!< Offset 0x014(R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x018(R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x01C(R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x020( W) Interrupt Clear Register */
__I uint32_t SR; /*!< Offset 0x024(R ) Address Register */
__IO uint32_t AR; /*!< Offset 0x028(R/W) Address Register */
__IO uint32_t DR; /*!< Offset 0x02C(R/W) Data Register */
__O uint32_t KR; /*!< Offset 0x030( W) Key Register */
__I uint32_t SO_PSR; /*!< Offset 0x034(R ) Smart Option Protection Status Register */
__I uint32_t SO_CSR; /*!< Offset 0x038(R ) Smart Option Configuration Status Register */
__IO uint32_t PF_IOTR; /*!< Offset 0x03C(R/W) Internal OSC Trimming Register */
} S3FM_PFC_TypeDef;
/*@}*/ /* end of group S3FM02G_PFC */
/** PULSE WIDTH MODULATION (PWM) *****/
/*------------- PULSE WIDTH MODULATION (PWM) ---------------------------*/
/** @addtogroup S3FM02G_PWM (PWM)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R ) ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004 (R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008 ( W) Software Reset Register */
__O uint32_t CSR; /*!< Offset 0x00C ( W) Control Set Register */
__O uint32_t CCR; /*!< Offset 0x010 ( W) Control Clear Register */
__I uint32_t SR; /*!< Offset 0x014 (R ) Status Register */
__IO uint32_t IMSCR; /*!< Offset 0x018 (R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x01C (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x020 (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x024 ( W) Interrupt Clear Register */
__IO uint32_t CDR; /*!< Offset 0x028 (R/W) Clock Divider Register */
__IO uint32_t PRDR; /*!< Offset 0x02C (R/W) Period Register */
__IO uint32_t PULR; /*!< Offset 0x030 (R/W) Pulse Register */
__I uint32_t CCDR; /*!< Offset 0x034 (R ) Current Clock Divider Register */
__I uint32_t CPRDR; /*!< Offset 0x038 (R ) Current Period Register */
__I uint32_t CPULR; /*!< Offset 0x03C (R ) Current Pulse Register */
} S3FM_PWM_TypeDef;
/*@}*/ /* end of group S3FM02G_PWM */
/** SERIAL PERIPHERAL INTERFACE (SPI) *****/
/*------------- SERIAL PERIPHERAL INTERFACE (SPI) ---------------------------*/
/** @addtogroup S3FM02G_SPI (SPI)
@{
*/
typedef struct
{
__IO uint32_t CR0; /*!< Offset 0x000(R/W) Control Register 0 */
__IO uint32_t CR1; /*!< Offset 0x004(R/W) Control Register 1 */
__IO uint32_t DR; /*!< Offset 0x008(R/W) Receive FIFO(read) and transmit FIFO data register(write) */
__I uint32_t SR; /*!< Offset 0x00C(R ) Status register */
__IO uint32_t CPSR; /*!< Offset 0x010(R/W) Clock prescale register */
__IO uint32_t IMSCR; /*!< Offset 0x014(R/W) Interrupt mask set and clear register */
__I uint32_t RISR; /*!< Offset 0x018(R ) Raw interrupt status register */
__I uint32_t MISR; /*!< Offset 0x01C(R ) Masked interrupt status register */
__O uint32_t ICR; /*!< Offset 0x020( W) Interrupt clear register */
__IO uint32_t DMACR; /*!< Offset 0x024(R/W) DMA control register */
} S3FM_SSP_TypeDef;
/*@}*/ /* end of group S3FM02G_SPI */
/** STAMP TIMER (STT) *****/
/*------------- STAMP TIMER (STT) ---------------------------*/
/** @addtogroup S3FM02G_STT (STT)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R ) ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004 (R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008 ( W) Software Reset Register */
__O uint32_t CR; /*!< Offset 0x00C ( W) Control Register */
__IO uint32_t MR; /*!< Offset 0x010 (R/W) Mode Register */
__IO uint32_t IMSCR; /*!< Offset 0x014 (R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x018 (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x01C (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x020 ( W) Interrupt Clear Register */
__I uint32_t SR; /*!< Offset 0x024 (R ) Status Register */
__IO uint32_t CNTR; /*!< Offset 0x028 (R/W) Counter Register */
__IO uint32_t ALR; /*!< Offset 0x02C (R/W) Alarm Register */
} S3FM_STT_TypeDef;
/*@}*/ /* end of group S3FM02G_STT */
/** TIMER/COUNTER (TC16) *****/
/*------------- TIMER/COUNTER (TC16) ---------------------------*/
/** @addtogroup S3FM02G_TC16 (TC16)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R ) ID Register */
__IO uint32_t CSSR; /*!< Offset 0x004 (R/W) Clock Source Selection Register */
__IO uint32_t CEDR; /*!< Offset 0x008 (R/W) Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x00C ( W) Software Reset Register */
__O uint32_t CSR; /*!< Offset 0x010 ( W) Control Set Register */
__O uint32_t CCR; /*!< Offset 0x014 ( W) Control Clear Register */
__I uint32_t SR; /*!< Offset 0x018 (R ) Status Register */
__IO uint32_t IMSCR; /*!< Offset 0x01C (R/W) Interrupt Mask Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x020 (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x024 (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x028 ( W) Interrupt Clear Register */
__IO uint32_t CDR; /*!< Offset 0x02C (R/W) Clock Divider Register */
__IO uint32_t CSMR ; /*!< Offset 0x030 (R/W) Counter Size Mask Register */
__IO uint32_t PRDR ; /*!< Offset 0x034 (R/W) Period Register */
__IO uint32_t PULR ; /*!< Offset 0x038 (R/W) Pulse Register */
__I uint32_t CCDR ; /*!< Offset 0x03C (R ) Current Clock Divider Register */
__I uint32_t CCSMR; /*!< Offset 0x040 (R ) Current Counter Size Mask Register */
__I uint32_t CPRDR; /*!< Offset 0x044 (R ) Current Period Register */
__I uint32_t CPULR; /*!< Offset 0x048 (R ) Current Pulse Register */
__I uint32_t CUCR ; /*!< Offset 0x04C (R ) Capture Up Count Register */
__I uint32_t CDCR ; /*!< Offset 0x050 (R ) Capture Down Count Register */
__I uint32_t CVR; /*!< Offset 0x054 (R ) Counter Value Register */
} S3FM_TC16_TypeDef;
/*@}*/ /* end of group S3FM02G_TC16 */
/** UNIVERAL SYNC/ASYNC RECEIVER/TRANSMITTER(USART) *****/
/*------------- UNIVERAL SYNC/ASYNC RECEIVER/TRANSMITTER(USART) ---------------------------*/
/** @addtogroup S3FM02G_USART (USART)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R )ID Register */
__IO uint32_t CEDR; /*!< Offset 0x004 (R/W)Clock Enable/Disable Register */
__O uint32_t SRR; /*!< Offset 0x008 ( W)Software Reset Register */
__O uint32_t CR; /*!< Offset 0x00C ( W)Control Register */
__IO uint32_t MR; /*!< Offset 0x010 (R/W)Mode Register */
__IO uint32_t IMSCR; /*!< Offset 0x014 (R/W)Interrupt Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x018 (R )Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x01C (R )Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x020 ( W)Clear Status Register */
__I uint32_t SR; /*!< Offset 0x024 (R )Status Register */
__I uint32_t RHR; /*!< Offset 0x028 (R )Receiver Holding Register */
__O uint32_t THR; /*!< Offset 0x02C ( W)Transmit Holding Register */
__IO uint32_t BRGR; /*!< Offset 0x030 (R/W)Baud Rate Generator Register */
__IO uint32_t RTOR; /*!< Offset 0x034 (R/W)Receiver Time-out Register */
__IO uint32_t TTGR; /*!< Offset 0x038 (R/W)Transmitter Time-guard Register */
__IO uint32_t LIR; /*!< Offset 0x03C (R/W)LIN Identifier Register */
__IO uint32_t DFWR0; /*!< Offset 0x040 (R/W)Data Field Write 0 Register */
__IO uint32_t DFWR1; /*!< Offset 0x044 (R/W)Data Field Write 1 Register */
__I uint32_t DFRR0; /*!< Offset 0x048 (R )Data Field Read 0 Register */
__I uint32_t DFRR1; /*!< Offset 0x04C (R )Data Field Read 1 Register */
__IO uint32_t SBLR; /*!< Offset 0x050 (R/W)Sync Break Length Register */
__IO uint32_t LCP1; /*!< Offset 0x054 (R/W)Limit counter protocol 1 */
__IO uint32_t LCP2; /*!< Offset 0x058 (R/W)Limit counter protocol 2 */
__IO uint32_t DMACR; /*!< Offset 0x05C (R/W)DMA Control Register */
} S3FM_USART_TypeDef;
/*@}*/ /* end of group S3FM02G_USART */
/** WATCHDOG TIMER(WDT) *****/
/*------------- WATCHDOG TIMER(WDT) ---------------------------*/
/** @addtogroup S3FM02G_WDT (WDT)
@{
*/
typedef struct
{
__I uint32_t IDR; /*!< Offset 0x000 (R ) ID Register */
__O uint32_t CR; /*!< Offset 0x004 ( W) Control Register */
__IO uint32_t MR; /*!< Offset 0x008 (R/W) Mode Register */
__IO uint32_t OMR; /*!< Offset 0x00C (R/W) Overflow Mode Register */
__I uint32_t SR; /*!< Offset 0x010 (R ) Status Register */
__IO uint32_t IMSCR; /*!< Offset 0x014 (R/W) Interrupt Set/Clear Register */
__I uint32_t RISR; /*!< Offset 0x018 (R ) Raw Interrupt Status Register */
__I uint32_t MISR; /*!< Offset 0x01C (R ) Masked Interrupt Status Register */
__O uint32_t ICR; /*!< Offset 0x020 ( W) Clear Status Register */
__IO uint32_t PWR; /*!< Offset 0x024 (R/W) Pending Window Register */
__I uint32_t CTR; /*!< Offset 0x028 (R ) Counter Test Register */
} S3FM_WDT_TypeDef;
/*@}*/ /* end of group S3FM02G_WDT */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
/** Peripheral base address */
#define PSEL0_BASE_ADDRESS (0x40000000UL)
/** SFM base address */
#define SFM_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x00000)
/** Memory part */
#define MEM_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x10000)
#define IFC0_BASE_ADDRESS (MEM_BASE_ADDRESS + 0x0000)
/** System part */
#define SYS_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x20000)
#define CM0_BASE_ADDRESS (SYS_BASE_ADDRESS + 0x0000)
/** Watchdog Timer & Free Running Timer Part */
#define WDT_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x30000)
#define WDT0_BASE_ADDRESS (WDT_BASE_ADDRESS + 0x0000)
#define FRT0_BASE_ADDRESS (WDT_BASE_ADDRESS + 0x1000)
/** ADC & DAC & OP-AMP part */
#define ADC_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x40000)
#define ADC0_BASE_ADDRESS (ADC_BASE_ADDRESS + 0x0000)
#define ADC1_BASE_ADDRESS (ADC_BASE_ADDRESS + 0x1000)
/** OP-AMP part */
#define OPAMP_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x42000)
#define OPAMP0_BASE_ADDRESS (OPAMP_BASE_ADDRESS + 0x0000)
/** GPIO part */
#define GPIO_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x50000)
#define GPIO0_BASE_ADDRESS (GPIO_BASE_ADDRESS + 0x0000)
#define GPIO1_BASE_ADDRESS (GPIO_BASE_ADDRESS + 0x1000)
#define GPIO2_BASE_ADDRESS (GPIO_BASE_ADDRESS + 0x2000)
#define GPIO3_BASE_ADDRESS (GPIO_BASE_ADDRESS + 0x3000)
#define IOCONF0_BASE_ADDRESS (GPIO_BASE_ADDRESS + 0x8000)
/** Timer part */
#define TC_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x60000)
#define TC0_BASE_ADDRESS (TC_BASE_ADDRESS + 0x0000)
#define TC1_BASE_ADDRESS (TC_BASE_ADDRESS + 0x1000)
#define TC2_BASE_ADDRESS (TC_BASE_ADDRESS + 0x2000)
#define TC3_BASE_ADDRESS (TC_BASE_ADDRESS + 0x3000)
#define TC4_BASE_ADDRESS (TC_BASE_ADDRESS + 0x4000)
#define TC5_BASE_ADDRESS (TC_BASE_ADDRESS + 0x5000)
#define TC6_BASE_ADDRESS (TC_BASE_ADDRESS + 0x6000)
#define TC7_BASE_ADDRESS (TC_BASE_ADDRESS + 0x7000)
#define STT0_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x78000)
/** PWM */
#define PWM_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x70000)
#define PWM0_BASE_ADDRESS (PWM_BASE_ADDRESS + 0x0000)
#define PWM1_BASE_ADDRESS (PWM_BASE_ADDRESS + 0x1000)
#define PWM2_BASE_ADDRESS (PWM_BASE_ADDRESS + 0x2000)
#define PWM3_BASE_ADDRESS (PWM_BASE_ADDRESS + 0x3000)
#define PWM4_BASE_ADDRESS (PWM_BASE_ADDRESS + 0x4000)
#define PWM5_BASE_ADDRESS (PWM_BASE_ADDRESS + 0x5000)
#define PWM6_BASE_ADDRESS (PWM_BASE_ADDRESS + 0x6000)
#define PWM7_BASE_ADDRESS (PWM_BASE_ADDRESS + 0x7000)
/** USART part */
#define USART_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x80000)
#define USART0_BASE_ADDRESS (USART_BASE_ADDRESS + 0x0000)
#define USART1_BASE_ADDRESS (USART_BASE_ADDRESS + 0x1000)
#define USART2_BASE_ADDRESS (USART_BASE_ADDRESS + 0x2000)
#define USART3_BASE_ADDRESS (USART_BASE_ADDRESS + 0x3000)
/** SPI part */
#define SSP_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x90000)
#define SSP0_BASE_ADDRESS (SSP_BASE_ADDRESS + 0x0000)
#define SSP1_BASE_ADDRESS (SSP_BASE_ADDRESS + 0x1000)
/** I2C part */
#define I2C_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0xA0000)
#define I2C0_BASE_ADDRESS (I2C_BASE_ADDRESS + 0x0000)
#define I2C1_BASE_ADDRESS (I2C_BASE_ADDRESS + 0x1000)
/** IMC part */
#define IMC_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0xB0000)
#define IMC0_BASE_ADDRESS (IMC_BASE_ADDRESS + 0x0000)
#define IMC1_BASE_ADDRESS (IMC_BASE_ADDRESS + 0x1000)
#define IMC1_OFFSET (IMC1_BASE_ADDRESS - IMC0_BASE_ADDRESS)
/** ENC part */
#define ENC_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0xC0000)
#define ENC0_BASE_ADDRESS (ENC_BASE_ADDRESS + 0x0000)
#define ENC1_BASE_ADDRESS (ENC_BASE_ADDRESS + 0x1000)
/** LCDC part */
#define LCDC_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0xD0000)
#define LCDC0_BASE_ADDRESS (LCDC_BASE_ADDRESS + 0x0000)
/** CAN part */
#define CAN_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0xE0000)
#define CAN0_BASE_ADDRESS (CAN_BASE_ADDRESS + 0x0000)
#define CAN1_BASE_ADDRESS (CAN_BASE_ADDRESS + 0x1000)
/** DMA part */
#define DMA_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0xF0000)
#define DMA0_BASE_ADDRESS (DMA_BASE_ADDRESS + 0x0000)
/** DFC part */
#define DFC_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x11000)
#define DFC0_BASE_ADDRESS (DFC_BASE_ADDRESS + 0x0000)
/** PFC part */
#define PFC_BASE_ADDRESS (PSEL0_BASE_ADDRESS + 0x10000)
#define PFC0_BASE_ADDRESS (PFC_BASE_ADDRESS + 0x0000)
#define S3FM_ADC0 ((S3FM_ADC0_TypeDef *) ADC0_BASE_ADDRESS )
#define S3FM_ADC1 ((S3FM_ADC1_TypeDef *) ADC1_BASE_ADDRESS )
#define S3FM_CAN0 ((S3FM_CAN_TypeDef *) CAN0_BASE_ADDRESS )
#define S3FM_CAN1 ((S3FM_CAN_TypeDef *) CAN1_BASE_ADDRESS )
#define S3FM_CM ((S3FM_CM_TypeDef *) CM0_BASE_ADDRESS )
#define S3FM_DMAC ((S3FM_DMAC_TypeDef *) DMA0_BASE_ADDRESS )
#define S3FM_DFC ((S3FM_DFC_TypeDef *) DFC0_BASE_ADDRESS )
#define S3FM_PFC ((S3FM_PFC_TypeDef *) PFC0_BASE_ADDRESS )
#define S3FM_ENC0 ((S3FM_ENC_TypeDef *) ENC0_BASE_ADDRESS )
#define S3FM_ENC1 ((S3FM_ENC_TypeDef *) ENC1_BASE_ADDRESS )
#define S3FM_FRT0 ((S3FM_FRT_TypeDef *) FRT0_BASE_ADDRESS )
#define S3FM_GPIO0 ((S3FM_GPIO_TypeDef *) GPIO0_BASE_ADDRESS )
#define S3FM_GPIO1 ((S3FM_GPIO_TypeDef *) GPIO1_BASE_ADDRESS )
#define S3FM_GPIO2 ((S3FM_GPIO_TypeDef *) GPIO2_BASE_ADDRESS )
#define S3FM_GPIO3 ((S3FM_GPIO_TypeDef *) GPIO3_BASE_ADDRESS )
#define S3FM_I2C0 ((S3FM_I2C_TypeDef *) I2C0_BASE_ADDRESS )
#define S3FM_I2C1 ((S3FM_I2C_TypeDef *) I2C1_BASE_ADDRESS )
#define S3FM_IMC0 ((S3FM_IMC_TypeDef *) IMC0_BASE_ADDRESS )
#define S3FM_IMC1 ((S3FM_IMC_TypeDef *) IMC1_BASE_ADDRESS )
#define S3FM_IOCONF ((S3FM_IOCONF_TypeDef *) IOCONF0_BASE_ADDRESS)
#define S3FM_LCDC ((S3FM_LCDC_TypeDef *) LCDC0_BASE_ADDRESS )
#define S3FM_OPAMP ((S3FM_OPAMP_TypeDef *) OPAMP0_BASE_ADDRESS )
#define S3FM_PWM0 ((S3FM_PWM_TypeDef *) PWM0_BASE_ADDRESS )
#define S3FM_PWM1 ((S3FM_PWM_TypeDef *) PWM1_BASE_ADDRESS )
#define S3FM_PWM2 ((S3FM_PWM_TypeDef *) PWM2_BASE_ADDRESS )
#define S3FM_PWM3 ((S3FM_PWM_TypeDef *) PWM3_BASE_ADDRESS )
#define S3FM_PWM4 ((S3FM_PWM_TypeDef *) PWM4_BASE_ADDRESS )
#define S3FM_PWM5 ((S3FM_PWM_TypeDef *) PWM5_BASE_ADDRESS )
#define S3FM_PWM6 ((S3FM_PWM_TypeDef *) PWM6_BASE_ADDRESS )
#define S3FM_PWM7 ((S3FM_PWM_TypeDef *) PWM7_BASE_ADDRESS )
#define S3FM_SSP0 ((S3FM_SSP_TypeDef *) SSP0_BASE_ADDRESS )
#define S3FM_SSP1 ((S3FM_SSP_TypeDef *) SSP1_BASE_ADDRESS )
#define S3FM_TC0 ((S3FM_TC16_TypeDef *) TC0_BASE_ADDRESS )
#define S3FM_TC1 ((S3FM_TC16_TypeDef *) TC1_BASE_ADDRESS )
#define S3FM_TC2 ((S3FM_TC16_TypeDef *) TC2_BASE_ADDRESS )
#define S3FM_TC3 ((S3FM_TC16_TypeDef *) TC3_BASE_ADDRESS )
#define S3FM_TC4 ((S3FM_TC16_TypeDef *) TC4_BASE_ADDRESS )
#define S3FM_TC5 ((S3FM_TC16_TypeDef *) TC5_BASE_ADDRESS )
#define S3FM_TC6 ((S3FM_TC16_TypeDef *) TC6_BASE_ADDRESS )
#define S3FM_TC7 ((S3FM_TC16_TypeDef *) TC7_BASE_ADDRESS )
#define S3FM_STT ((S3FM_STT_TypeDef *) STT0_BASE_ADDRESS )
#define S3FM_USART0 ((S3FM_USART_TypeDef *) USART0_BASE_ADDRESS )
#define S3FM_USART1 ((S3FM_USART_TypeDef *) USART1_BASE_ADDRESS )
#define S3FM_USART2 ((S3FM_USART_TypeDef *) USART2_BASE_ADDRESS )
#define S3FM_USART3 ((S3FM_USART_TypeDef *) USART3_BASE_ADDRESS )
#define S3FM_WDT ((S3FM_WDT_TypeDef *) WDT0_BASE_ADDRESS )
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#ifdef __cplusplus
}
#endif
#endif /* __S3FM02G_H__ */