/***********************************************************************/ /* This file is part of the uVision/ARM development tools */ /* Copyright KEIL ELEKTRONIK GmbH 2002-2007 */ /***********************************************************************/ /* */ /* LPC29xx.H: Header file for NXP LPC29xx */ /* */ /***********************************************************************/ #ifndef __LPC29xx_H #define __LPC29xx_H #define UART0_BASE_ADDR 0xE0045000 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) #define U0IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) #define U0FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) #define RxInt_4 0x40 #define DMA_M 8 #define CLR_TXF 4 #define CLR_RXF 2 #define FIFO_EN 1 #define U0LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) #define DLAB 0x80 #define WLS8BIT 3 #define U0LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) #define UART1_BASE_ADDR 0xE0046000 #define U1RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U1THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U1DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U1DLM (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x04)) #define U1IIR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) #define U1FCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x08)) #define U1LCR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x0C)) #define U1LSR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x14)) #define TMR0_BASE_ADDR 0xE0041000 #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) #define COUNTER_RESET 2 #define COUNTER_RUN 1 #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) #define T0PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) #define AUTO3_TIMER T0TC #define ADC1_BASE_ADDR 0xE00C3000 #define ADC1_ACC0 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 0 )) #define ADC1_ACC1 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 1 )) #define ADC1_ACC2 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 2 )) #define ADC1_ACC3 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 3 )) #define ADC1_ACC4 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 4 )) #define ADC1_ACC5 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 5 )) #define ADC1_ACC6 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 6 )) #define ADC1_ACC7 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 7 )) #define ADC1_ACC8 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 8 )) #define ADC1_ACC9 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 9 )) #define ADC1_ACC10 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 10)) #define ADC1_ACC11 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 11)) #define ADC1_ACC12 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 12)) #define ADC1_ACC13 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 13)) #define ADC1_ACC14 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 14)) #define ADC1_ACC15 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x000 + 4 * 15)) #define ADC1_COMP0 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 0 )) #define ADC1_COMP1 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 1 )) #define ADC1_COMP2 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 2 )) #define ADC1_COMP3 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 3 )) #define ADC1_COMP4 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 4 )) #define ADC1_COMP5 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 5 )) #define ADC1_COMP6 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 6 )) #define ADC1_COMP7 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 7 )) #define ADC1_COMP8 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 8 )) #define ADC1_COMP9 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 9 )) #define ADC1_COMP10 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 10)) #define ADC1_COMP11 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 11)) #define ADC1_COMP12 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 12)) #define ADC1_COMP13 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 13)) #define ADC1_COMP14 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 14)) #define ADC1_COMP15 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x100 + 4 * 15)) #define ADC1_ADCD0 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 0 )) #define ADC1_ADCD1 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 1 )) #define ADC1_ADCD2 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 2 )) #define ADC1_ADCD3 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 3 )) #define ADC1_ADCD4 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 4 )) #define ADC1_ADCD5 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 5 )) #define ADC1_ADCD6 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 6 )) #define ADC1_ADCD7 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 7 )) #define ADC1_ADCD8 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 8 )) #define ADC1_ADCD9 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 9 )) #define ADC1_ADCD10 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 10)) #define ADC1_ADCD11 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 11)) #define ADC1_ADCD12 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 12)) #define ADC1_ADCD13 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 13)) #define ADC1_ADCD14 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 14)) #define ADC1_ADCD15 (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x200 + 4 * 15)) #define ADC1_COMP_STATUS (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x300)) #define ADC1_COMP_STATUS_CLR (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x304)) #define ADC1_ADC_CONFIG (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x400)) #define ADC1_ADC_CONTROL (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x404)) #define ADC1_ADC_STATUS (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0x408)) #define ADC1_INT_CLR_ENABLE (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0xFD8)) #define ADC1_INT_SET_ENABLE (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0xFDC)) #define ADC1_INT_STATUS (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0xFE0)) #define ADC1_INT_ENABLE (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0xFE4)) #define ADC1_INT_CLR_STATUS (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0xFE8)) #define ADC1_INT_SET_STATUS (*(volatile unsigned long *)(ADC1_BASE_ADDR + 0xFEC)) #define ADC2_BASE_ADDR 0xE00C4000 #define ADC2_ACC0 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 0 )) #define ADC2_ACC1 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 1 )) #define ADC2_ACC2 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 2 )) #define ADC2_ACC3 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 3 )) #define ADC2_ACC4 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 4 )) #define ADC2_ACC5 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 5 )) #define ADC2_ACC6 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 6 )) #define ADC2_ACC7 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 7 )) #define ADC2_ACC8 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 8 )) #define ADC2_ACC9 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 9 )) #define ADC2_ACC10 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 10)) #define ADC2_ACC11 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 11)) #define ADC2_ACC12 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 12)) #define ADC2_ACC13 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 13)) #define ADC2_ACC14 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 14)) #define ADC2_ACC15 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x000 + 4 * 15)) #define ADC2_COMP0 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 0 )) #define ADC2_COMP1 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 1 )) #define ADC2_COMP2 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 2 )) #define ADC2_COMP3 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 3 )) #define ADC2_COMP4 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 4 )) #define ADC2_COMP5 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 5 )) #define ADC2_COMP6 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 6 )) #define ADC2_COMP7 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 7 )) #define ADC2_COMP8 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 8 )) #define ADC2_COMP9 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 9 )) #define ADC2_COMP10 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 10)) #define ADC2_COMP11 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 11)) #define ADC2_COMP12 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 12)) #define ADC2_COMP13 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 13)) #define ADC2_COMP14 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 14)) #define ADC2_COMP15 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x100 + 4 * 15)) #define ADC2_ADCD0 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 0 )) #define ADC2_ADCD1 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 1 )) #define ADC2_ADCD2 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 2 )) #define ADC2_ADCD3 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 3 )) #define ADC2_ADCD4 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 4 )) #define ADC2_ADCD5 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 5 )) #define ADC2_ADCD6 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 6 )) #define ADC2_ADCD7 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 7 )) #define ADC2_ADCD8 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 8 )) #define ADC2_ADCD9 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 9 )) #define ADC2_ADCD10 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 10)) #define ADC2_ADCD11 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 11)) #define ADC2_ADCD12 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 12)) #define ADC2_ADCD13 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 13)) #define ADC2_ADCD14 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 14)) #define ADC2_ADCD15 (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x200 + 4 * 15)) #define ADC2_COMP_STATUS (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x300)) #define ADC2_COMP_STATUS_CLR (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x304)) #define ADC2_ADC_CONFIG (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x400)) #define ADC2_ADC_CONTROL (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x404)) #define ADC2_ADC_STATUS (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0x408)) #define ADC2_INT_CLR_ENABLE (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0xFD8)) #define ADC2_INT_SET_ENABLE (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0xFDC)) #define ADC2_INT_STATUS (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0xFE0)) #define ADC2_INT_ENABLE (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0xFE4)) #define ADC2_INT_CLR_STATUS (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0xFE8)) #define ADC2_INT_SET_STATUS (*(volatile unsigned long *)(ADC2_BASE_ADDR + 0xFEC)) #define CGU_BASE_ADDR 0xFFFF8000 #define PLL_CONTROL (*(volatile unsigned long *)(CGU_BASE_ADDR + 0x28)) #define PLL_XTAL_SEL 0x01000000 #define MSEL_SHIFT 16 #define P23EN 4 #define PLL_PD 1 #define PLL_STATUS (*(volatile unsigned long *)(CGU_BASE_ADDR + 0x24)) #define PLL_LOCK 1 #define RDET (*(volatile unsigned long *)(CGU_BASE_ADDR + 0x18)) #define PLL_PRESENT 4 #define SYS_CLK_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0x70)) #define CLK_SEL_XTAL 0x01000000 #define CLK_SEL_PLL 0x02000000 #define AUTOBLK 0x800 #define DIV8 0x1C #define DIV4 0xC #define DIV2 0x4 #define IVNSS_CLK_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0x80)) #define MSCSS_CLK_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0x88)) #define FRSS_CLK_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0x90)) #define UART_CLK_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0x98)) #define SPI_CLK_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0xA0)) #define TMR_CLK_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0xA8)) #define ADC_CLK_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0xB0)) #define CLK_TESTSHELL_CONF (*(volatile unsigned long *)(CGU_BASE_ADDR + 0xB8)) #define FMC_BASE_ADDR 0x20200000 #define FCTR (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x000)) #define FS_LOADREQ (1 << 15) #define FS_CACHECLR (1 << 14) #define FS_CACHEBYP (1 << 13) #define FS_PROGREQ (1 << 12) #define FS_RLS (1 << 11) #define FS_PDL (1 << 10) #define FS_PD (1 << 9) #define FS_WPB (1 << 7) #define FS_RLD (1 << 5) #define FS_DCR (1 << 4) #define FS_WEB (1 << 2) #define FS_WRE (1 << 1) #define FS_CS (1 << 0) #define FPTR (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x008)) #define FBWST (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x010)) #define CACHE2EN 0x8000 #define SPECALWAYS 0x4000 #define WST4 4 #define FCRA (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x01C)) #define FMSSTART (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x020)) #define FMSSTOP (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x024)) #define FMSW0 (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x02C)) #define FMSW1 (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x030)) #define FMSW2 (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x034)) #define FMSW3 (*(volatile unsigned long *)(FMC_BASE_ADDR + 0x038)) #define FMC_INT_CLR_ENABLE (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFD8)) #define FMC_INT_SET_ENABLE (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFDC)) #define FMC_INT_STATUS (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFE0)) #define FMC_INT_ENABLE (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFE4)) #define FMC_INT_CLR_STATUS (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFE8)) #define FMC_INT_SET_STATUS (*(volatile unsigned long *)(FMC_BASE_ADDR + 0xFEC)) #define GPIO0_BASE_ADDR 0xE004A000 #define GPIO0_PINS (*(volatile unsigned long *)(GPIO0_BASE_ADDR + 0x000)) #define GPIO0_OR (*(volatile unsigned long *)(GPIO0_BASE_ADDR + 0x004)) #define GPIO0_DR (*(volatile unsigned long *)(GPIO0_BASE_ADDR + 0x008)) #define GPIO1_BASE_ADDR 0xE004B000 #define GPIO1_PINS (*(volatile unsigned long *)(GPIO1_BASE_ADDR + 0x000)) #define GPIO1_OR (*(volatile unsigned long *)(GPIO1_BASE_ADDR + 0x004)) #define GPIO1_DR (*(volatile unsigned long *)(GPIO1_BASE_ADDR + 0x008)) #define GPIO2_BASE_ADDR 0xE004C000 #define GPIO2_PINS (*(volatile unsigned long *)(GPIO2_BASE_ADDR + 0x000)) #define GPIO2_OR (*(volatile unsigned long *)(GPIO2_BASE_ADDR + 0x004)) #define GPIO2_DR (*(volatile unsigned long *)(GPIO2_BASE_ADDR + 0x008)) #define GPIO3_BASE_ADDR 0xE004D000 #define GPIO3_PINS (*(volatile unsigned long *)(GPIO3_BASE_ADDR + 0x000)) #define GPIO3_OR (*(volatile unsigned long *)(GPIO3_BASE_ADDR + 0x004)) #define GPIO3_DR (*(volatile unsigned long *)(GPIO3_BASE_ADDR + 0x008)) #define SCU_BASE_ADDR 0xE0001000 #define SFSP0_BASE (SCU_BASE_ADDR + 0x000) #define SFSP0_0 (*(volatile unsigned long *)(SFSP0_BASE + 0x00)) #define SFSP0_1 (*(volatile unsigned long *)(SFSP0_BASE + 0x04)) #define SFSP0_2 (*(volatile unsigned long *)(SFSP0_BASE + 0x08)) #define SFSP0_3 (*(volatile unsigned long *)(SFSP0_BASE + 0x0C)) #define SFSP0_4 (*(volatile unsigned long *)(SFSP0_BASE + 0x10)) #define SFSP0_5 (*(volatile unsigned long *)(SFSP0_BASE + 0x14)) #define SFSP0_6 (*(volatile unsigned long *)(SFSP0_BASE + 0x18)) #define SFSP0_7 (*(volatile unsigned long *)(SFSP0_BASE + 0x1C)) #define SFSP0_8 (*(volatile unsigned long *)(SFSP0_BASE + 0x20)) #define SFSP0_9 (*(volatile unsigned long *)(SFSP0_BASE + 0x24)) #define SFSP0_10 (*(volatile unsigned long *)(SFSP0_BASE + 0x28)) #define SFSP0_11 (*(volatile unsigned long *)(SFSP0_BASE + 0x2C)) #define SFSP0_12 (*(volatile unsigned long *)(SFSP0_BASE + 0x30)) #define SFSP0_13 (*(volatile unsigned long *)(SFSP0_BASE + 0x34)) #define SFSP0_14 (*(volatile unsigned long *)(SFSP0_BASE + 0x38)) #define SFSP0_15 (*(volatile unsigned long *)(SFSP0_BASE + 0x3C)) #define SFSP0_16 (*(volatile unsigned long *)(SFSP0_BASE + 0x40)) #define SFSP0_17 (*(volatile unsigned long *)(SFSP0_BASE + 0x44)) #define SFSP0_18 (*(volatile unsigned long *)(SFSP0_BASE + 0x48)) #define SFSP0_19 (*(volatile unsigned long *)(SFSP0_BASE + 0x4C)) #define SFSP0_20 (*(volatile unsigned long *)(SFSP0_BASE + 0x50)) #define SFSP0_21 (*(volatile unsigned long *)(SFSP0_BASE + 0x54)) #define SFSP0_22 (*(volatile unsigned long *)(SFSP0_BASE + 0x58)) #define SFSP0_23 (*(volatile unsigned long *)(SFSP0_BASE + 0x5C)) #define SFSP0_24 (*(volatile unsigned long *)(SFSP0_BASE + 0x60)) #define SFSP0_25 (*(volatile unsigned long *)(SFSP0_BASE + 0x64)) #define SFSP0_26 (*(volatile unsigned long *)(SFSP0_BASE + 0x68)) #define SFSP0_27 (*(volatile unsigned long *)(SFSP0_BASE + 0x6C)) #define SFSP0_28 (*(volatile unsigned long *)(SFSP0_BASE + 0x70)) #define SFSP0_29 (*(volatile unsigned long *)(SFSP0_BASE + 0x74)) #define SFSP0_30 (*(volatile unsigned long *)(SFSP0_BASE + 0x78)) #define SFSP0_31 (*(volatile unsigned long *)(SFSP0_BASE + 0x7C)) #define SFSP1_BASE (SCU_BASE_ADDR + 0x100) #define SFSP1_0 (*(volatile unsigned long *)(SFSP1_BASE + 0x00)) #define SFSP1_1 (*(volatile unsigned long *)(SFSP1_BASE + 0x04)) #define SFSP1_2 (*(volatile unsigned long *)(SFSP1_BASE + 0x08)) #define SFSP1_3 (*(volatile unsigned long *)(SFSP1_BASE + 0x0C)) #define SFSP1_4 (*(volatile unsigned long *)(SFSP1_BASE + 0x10)) #define SFSP1_5 (*(volatile unsigned long *)(SFSP1_BASE + 0x14)) #define SFSP1_6 (*(volatile unsigned long *)(SFSP1_BASE + 0x18)) #define SFSP1_7 (*(volatile unsigned long *)(SFSP1_BASE + 0x1C)) #define SFSP1_8 (*(volatile unsigned long *)(SFSP1_BASE + 0x20)) #define SFSP1_9 (*(volatile unsigned long *)(SFSP1_BASE + 0x24)) #define SFSP1_10 (*(volatile unsigned long *)(SFSP1_BASE + 0x28)) #define SFSP1_11 (*(volatile unsigned long *)(SFSP1_BASE + 0x2C)) #define SFSP1_12 (*(volatile unsigned long *)(SFSP1_BASE + 0x30)) #define SFSP1_13 (*(volatile unsigned long *)(SFSP1_BASE + 0x34)) #define SFSP1_14 (*(volatile unsigned long *)(SFSP1_BASE + 0x38)) #define SFSP1_15 (*(volatile unsigned long *)(SFSP1_BASE + 0x3C)) #define SFSP1_16 (*(volatile unsigned long *)(SFSP1_BASE + 0x40)) #define SFSP1_17 (*(volatile unsigned long *)(SFSP1_BASE + 0x44)) #define SFSP1_18 (*(volatile unsigned long *)(SFSP1_BASE + 0x48)) #define SFSP1_19 (*(volatile unsigned long *)(SFSP1_BASE + 0x4C)) #define SFSP1_20 (*(volatile unsigned long *)(SFSP1_BASE + 0x50)) #define SFSP1_21 (*(volatile unsigned long *)(SFSP1_BASE + 0x54)) #define SFSP1_22 (*(volatile unsigned long *)(SFSP1_BASE + 0x58)) #define SFSP1_23 (*(volatile unsigned long *)(SFSP1_BASE + 0x5C)) #define SFSP1_24 (*(volatile unsigned long *)(SFSP1_BASE + 0x60)) #define SFSP1_25 (*(volatile unsigned long *)(SFSP1_BASE + 0x64)) #define SFSP1_26 (*(volatile unsigned long *)(SFSP1_BASE + 0x68)) #define SFSP1_27 (*(volatile unsigned long *)(SFSP1_BASE + 0x6C)) #define SFSP1_28 (*(volatile unsigned long *)(SFSP1_BASE + 0x70)) #define SFSP1_29 (*(volatile unsigned long *)(SFSP1_BASE + 0x74)) #define SFSP1_30 (*(volatile unsigned long *)(SFSP1_BASE + 0x78)) #define SFSP1_31 (*(volatile unsigned long *)(SFSP1_BASE + 0x7C)) #define SFSP2_BASE (SCU_BASE_ADDR + 0x200) #define SFSP2_0 (*(volatile unsigned long *)(SFSP2_BASE + 0x00)) #define SFSP2_1 (*(volatile unsigned long *)(SFSP2_BASE + 0x04)) #define SFSP2_2 (*(volatile unsigned long *)(SFSP2_BASE + 0x08)) #define SFSP2_3 (*(volatile unsigned long *)(SFSP2_BASE + 0x0C)) #define SFSP2_4 (*(volatile unsigned long *)(SFSP2_BASE + 0x10)) #define SFSP2_5 (*(volatile unsigned long *)(SFSP2_BASE + 0x14)) #define SFSP2_6 (*(volatile unsigned long *)(SFSP2_BASE + 0x18)) #define SFSP2_7 (*(volatile unsigned long *)(SFSP2_BASE + 0x1C)) #define SFSP2_8 (*(volatile unsigned long *)(SFSP2_BASE + 0x20)) #define SFSP2_9 (*(volatile unsigned long *)(SFSP2_BASE + 0x24)) #define SFSP2_10 (*(volatile unsigned long *)(SFSP2_BASE + 0x28)) #define SFSP2_11 (*(volatile unsigned long *)(SFSP2_BASE + 0x2C)) #define SFSP2_12 (*(volatile unsigned long *)(SFSP2_BASE + 0x30)) #define SFSP2_13 (*(volatile unsigned long *)(SFSP2_BASE + 0x34)) #define SFSP2_14 (*(volatile unsigned long *)(SFSP2_BASE + 0x38)) #define SFSP2_15 (*(volatile unsigned long *)(SFSP2_BASE + 0x3C)) #define SFSP2_16 (*(volatile unsigned long *)(SFSP2_BASE + 0x40)) #define SFSP2_17 (*(volatile unsigned long *)(SFSP2_BASE + 0x44)) #define SFSP2_18 (*(volatile unsigned long *)(SFSP2_BASE + 0x48)) #define SFSP2_19 (*(volatile unsigned long *)(SFSP2_BASE + 0x4C)) #define SFSP2_20 (*(volatile unsigned long *)(SFSP2_BASE + 0x50)) #define SFSP2_21 (*(volatile unsigned long *)(SFSP2_BASE + 0x54)) #define SFSP2_22 (*(volatile unsigned long *)(SFSP2_BASE + 0x58)) #define SFSP2_23 (*(volatile unsigned long *)(SFSP2_BASE + 0x5C)) #define SFSP2_24 (*(volatile unsigned long *)(SFSP2_BASE + 0x60)) #define SFSP2_25 (*(volatile unsigned long *)(SFSP2_BASE + 0x64)) #define SFSP2_26 (*(volatile unsigned long *)(SFSP2_BASE + 0x68)) #define SFSP2_27 (*(volatile unsigned long *)(SFSP2_BASE + 0x6C)) #define SFSP3_BASE (SCU_BASE_ADDR + 0x300) #define SFSP3_0 (*(volatile unsigned long *)(SFSP3_BASE + 0x00)) #define SFSP3_1 (*(volatile unsigned long *)(SFSP3_BASE + 0x04)) #define SFSP3_2 (*(volatile unsigned long *)(SFSP3_BASE + 0x08)) #define SFSP3_3 (*(volatile unsigned long *)(SFSP3_BASE + 0x0C)) #define SFSP3_4 (*(volatile unsigned long *)(SFSP3_BASE + 0x10)) #define SFSP3_5 (*(volatile unsigned long *)(SFSP3_BASE + 0x14)) #define SFSP3_6 (*(volatile unsigned long *)(SFSP3_BASE + 0x18)) #define SFSP3_7 (*(volatile unsigned long *)(SFSP3_BASE + 0x1C)) #define SFSP3_8 (*(volatile unsigned long *)(SFSP3_BASE + 0x20)) #define SFSP3_9 (*(volatile unsigned long *)(SFSP3_BASE + 0x24)) #define SFSP3_10 (*(volatile unsigned long *)(SFSP3_BASE + 0x28)) #define SFSP3_11 (*(volatile unsigned long *)(SFSP3_BASE + 0x2C)) #define SFSP3_12 (*(volatile unsigned long *)(SFSP3_BASE + 0x30)) #define SFSP3_13 (*(volatile unsigned long *)(SFSP3_BASE + 0x34)) #define SFSP3_14 (*(volatile unsigned long *)(SFSP3_BASE + 0x38)) #define SFSP3_15 (*(volatile unsigned long *)(SFSP3_BASE + 0x3C)) #define DIGITAL_NO_RES 4 #define PIN_FUNC2 2 #define VIC_BASE_ADDR 0xFFFFF000 #define INT_PRIOR_MASK_0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) #define INT_PRIOR_MASK_1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) #define INT_VECTOR_0 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x100)) #define INT_VECTOR_1 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x104)) #define INT_PENDING_1_31 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x200)) #define INT_PENDING_32_53 (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x204)) #define INT_FEATURES (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x300)) #define INT_REQUEST_(x) (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x400 + ((x)*4))) #define INT_REQUEST_1 INT_REQUEST_( 1) #define INT_REQUEST_2 INT_REQUEST_( 2) #define INT_REQUEST_3 INT_REQUEST_( 3) #define INT_REQUEST_4 INT_REQUEST_( 4) #define INT_REQUEST_5 INT_REQUEST_( 5) #define INT_REQUEST_6 INT_REQUEST_( 6) #define INT_REQUEST_7 INT_REQUEST_( 7) #define INT_REQUEST_8 INT_REQUEST_( 8) #define INT_REQUEST_9 INT_REQUEST_( 9) #define INT_REQUEST_10 INT_REQUEST_(10) #define INT_REQUEST_11 INT_REQUEST_(11) #define INT_REQUEST_12 INT_REQUEST_(12) #define INT_REQUEST_13 INT_REQUEST_(13) #define INT_REQUEST_14 INT_REQUEST_(14) #define INT_REQUEST_15 INT_REQUEST_(15) #define INT_REQUEST_16 INT_REQUEST_(16) #define INT_REQUEST_17 INT_REQUEST_(17) #define INT_REQUEST_18 INT_REQUEST_(18) #define INT_REQUEST_19 INT_REQUEST_(19) #define INT_REQUEST_20 INT_REQUEST_(20) #define INT_REQUEST_21 INT_REQUEST_(21) #define INT_REQUEST_22 INT_REQUEST_(22) #define INT_REQUEST_23 INT_REQUEST_(23) #define INT_REQUEST_24 INT_REQUEST_(24) #define INT_REQUEST_25 INT_REQUEST_(25) #define INT_REQUEST_26 INT_REQUEST_(26) #define INT_REQUEST_27 INT_REQUEST_(27) #define INT_REQUEST_28 INT_REQUEST_(28) #define INT_REQUEST_29 INT_REQUEST_(29) #define INT_REQUEST_30 INT_REQUEST_(30) #define INT_REQUEST_31 INT_REQUEST_(31) #define INT_REQUEST_32 INT_REQUEST_(32) #define INT_REQUEST_33 INT_REQUEST_(33) #define INT_REQUEST_34 INT_REQUEST_(34) #define INT_REQUEST_35 INT_REQUEST_(35) #define INT_REQUEST_36 INT_REQUEST_(36) #define INT_REQUEST_37 INT_REQUEST_(37) #define INT_REQUEST_38 INT_REQUEST_(38) #define INT_REQUEST_39 INT_REQUEST_(39) #define INT_REQUEST_40 INT_REQUEST_(40) #define INT_REQUEST_41 INT_REQUEST_(41) #define INT_REQUEST_42 INT_REQUEST_(42) #define INT_REQUEST_43 INT_REQUEST_(43) #define INT_REQUEST_44 INT_REQUEST_(44) #define INT_REQUEST_45 INT_REQUEST_(45) #define INT_REQUEST_46 INT_REQUEST_(46) #define INT_REQUEST_47 INT_REQUEST_(47) #define INT_REQUEST_48 INT_REQUEST_(48) #define INT_REQUEST_49 INT_REQUEST_(49) #define INT_REQUEST_50 INT_REQUEST_(50) #define INT_REQUEST_51 INT_REQUEST_(51) #define INT_REQUEST_52 INT_REQUEST_(52) #define INT_REQUEST_53 INT_REQUEST_(53) #define INT_REQUEST_54 INT_REQUEST_(54) #define INT_REQUEST_55 INT_REQUEST_(55) #define TMR0_BASE_ADDR 0xE0041000 #define TIM0_TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x000)) #define TIM0_TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x004)) #define TIM0_PR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x008)) #define TIM0_MCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00C)) #define TIM0_EMR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x010)) #define TIM0_MR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x014)) #define TIM0_MR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x018)) #define TIM0_MR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x01C)) #define TIM0_MR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x020)) #define TIM0_CCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x024)) #define TIM0_CR0 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x028)) #define TIM0_CR1 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x02C)) #define TIM0_CR2 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x030)) #define TIM0_CR3 (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x034)) #define TIM0_INT_CLR_ENABLE (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFD8)) #define TIM0_INT_SET_ENABLE (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFDC)) #define TIM0_INT_STATUS (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFE0)) #define TIM0_INT_ENABLE (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFE4)) #define TIM0_INT_CLR_STATUS (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFE8)) #define TIM0_INT_SET_STATUS (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0xFEC)) #define TMR1_BASE_ADDR 0xE0042000 #define TIM1_TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x000)) #define TIM1_TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x004)) #define TIM1_PR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x008)) #define TIM1_MCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00C)) #define TIM1_EMR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x010)) #define TIM1_MR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x014)) #define TIM1_MR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x018)) #define TIM1_MR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x01C)) #define TIM1_MR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x020)) #define TIM1_CCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x024)) #define TIM1_CR0 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x028)) #define TIM1_CR1 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x02C)) #define TIM1_CR2 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x030)) #define TIM1_CR3 (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x034)) #define TIM1_INT_CLR_ENABLE (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFD8)) #define TIM1_INT_SET_ENABLE (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFDC)) #define TIM1_INT_STATUS (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFE0)) #define TIM1_INT_ENABLE (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFE4)) #define TIM1_INT_CLR_STATUS (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFE8)) #define TIM1_INT_SET_STATUS (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0xFEC)) #define TMR2_BASE_ADDR 0xE0043000 #define TIM2_TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x000)) #define TIM2_TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x004)) #define TIM2_PR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x008)) #define TIM2_MCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00C)) #define TIM2_EMR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x010)) #define TIM2_MR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x014)) #define TIM2_MR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x018)) #define TIM2_MR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x01C)) #define TIM2_MR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x020)) #define TIM2_CCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x024)) #define TIM2_CR0 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x028)) #define TIM2_CR1 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x02C)) #define TIM2_CR2 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x030)) #define TIM2_CR3 (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x034)) #define TIM2_INT_CLR_ENABLE (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFD8)) #define TIM2_INT_SET_ENABLE (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFDC)) #define TIM2_INT_STATUS (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFE0)) #define TIM2_INT_ENABLE (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFE4)) #define TIM2_INT_CLR_STATUS (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFE8)) #define TIM2_INT_SET_STATUS (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0xFEC)) #define TMR3_BASE_ADDR 0xE0044000 #define TIM3_TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x000)) #define TIM3_TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x004)) #define TIM3_PR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x008)) #define TIM3_MCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00C)) #define TIM3_EMR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x010)) #define TIM3_MR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x014)) #define TIM3_MR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x018)) #define TIM3_MR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x01C)) #define TIM3_MR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x020)) #define TIM3_CCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x024)) #define TIM3_CR0 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x028)) #define TIM3_CR1 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x02C)) #define TIM3_CR2 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x030)) #define TIM3_CR3 (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x034)) #define TIM3_INT_CLR_ENABLE (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFD8)) #define TIM3_INT_SET_ENABLE (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFDC)) #define TIM3_INT_STATUS (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFE0)) #define TIM3_INT_ENABLE (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFE4)) #define TIM3_INT_CLR_STATUS (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFE8)) #define TIM3_INT_SET_STATUS (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0xFEC)) #define AUTO3_TX_RDY (U0LSR & 0x20) #define AUTO3_RX_RDY (U0LSR & 1) #define AUTO3_RX_CHAR U0RBR #define AUTO3_TX_CHAR U0THR #define AUTO3_TIMER T0TC #endif // __LPC29xx_H