/****************************************************************************************************//** * @file LPC43xx.h * * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for * LPC43xx from . * * @version V9 * @date 4. September 2013 * * @note Generated with SVDConv V2.80 * from CMSIS SVD File 'LPC43xx.svd' Version 9, * * Modified by KEIL *******************************************************************************************************/ /** @addtogroup (null) * @{ */ /** @addtogroup LPC43xx * @{ */ #ifndef LPC43XX_H #define LPC43XX_H #ifdef __cplusplus extern "C" { #endif /* Following defines are used: CORE_M4 LPC43xx M4 Application core CORE_M0 LPC43xx M0 Application core CORE_M0SUB LPC43xx M0 Subsystem core */ #if !defined (CORE_M4) && !defined (CORE_M0) && !defined (CORE_M0SUB) #define CORE_M4 #endif /* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { #ifdef CORE_M4 /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ MemoryManagement_IRQn = -12, /*!< 4 Memory Management */ BusFault_IRQn = -11, /*!< 5 Bus Fault */ UsageFault_IRQn = -10, /*!< 6 Usage Fault */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ // --------------------------- LPC43xx/M4 Specific Interrupt Numbers ---------------------------- DAC_IRQn = 0, /*!< 0 DAC interrupt */ M0APP_IRQn = 1, /*!< 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication */ DMA_IRQn = 2, /*!< 2 DMA interrupt */ FLASHEEPROM_IRQn = 4, /*!< 4 flash bank A, flash bank B, EEPROM ORed interrupt */ ETHERNET_IRQn = 5, /*!< 5 Etherne interrupt */ SDIO_IRQn = 6, /*!< 6 SD/MMC interrupt */ LCD_IRQn = 7, /*!< 7 LCD interrupt */ USB0_IRQn = 8, /*!< 8 OTG interrupt */ USB1_IRQn = 9, /*!< 9 USB1 interrupt */ SCT_IRQn = 10, /*!< 10 SCT combined interrupt */ RITIMER_IRQn = 11, /*!< 11 RI Timer interrupt */ TIMER0_IRQn = 12, /*!< 12 Timer 0 interrupt */ TIMER1_IRQn = 13, /*!< 13 Timer 1 interrupt */ TIMER2_IRQn = 14, /*!< 14 Timer 2 interrupt */ TIMER3_IRQn = 15, /*!< 15 Timer 3 interrupt */ MCPWM_IRQn = 16, /*!< 16 Motor control PWM interrupt */ ADC0_IRQn = 17, /*!< 17 ADC0 interrupt */ I2C0_IRQn = 18, /*!< 18 I2C0 interrupt */ I2C1_IRQn = 19, /*!< 19 I2C1 interrupt */ SPI_IRQn = 20, /*!< 20 SPI interrupt */ ADC1_IRQn = 21, /*!< 21 ADC1 interrupt */ SSP0_IRQn = 22, /*!< 22 SSP0 interrupt */ SSP1_IRQn = 23, /*!< 23 SSP1 interrupt */ USART0_IRQn = 24, /*!< 24 USART0 interrupt */ UART1_IRQn = 25, /*!< 25 Combined UART1, Modem interrupt */ USART2_IRQn = 26, /*!< 26 USART2 interrupt */ USART3_IRQn = 27, /*!< 27 Combined USART3, IrDA interrupt */ I2S0_IRQn = 28, /*!< 28 I2S0 interrupt */ I2S1_IRQn = 29, /*!< 29 I2S1 interrupt */ SPIFI_IRQn = 30, /*!< 30 SPISI interrupt */ SGPIO_IRQn = 31, /*!< 31 SGPIO interrupt */ PIN_INT0_IRQn = 32, /*!< 32 GPIO pin interrupt 0 */ PIN_INT1_IRQn = 33, /*!< 33 GPIO pin interrupt 1 */ PIN_INT2_IRQn = 34, /*!< 34 GPIO pin interrupt 2 */ PIN_INT3_IRQn = 35, /*!< 35 GPIO pin interrupt 3 */ PIN_INT4_IRQn = 36, /*!< 36 GPIO pin interrupt 4 */ PIN_INT5_IRQn = 37, /*!< 37 GPIO pin interrupt 5 */ PIN_INT6_IRQn = 38, /*!< 38 GPIO pin interrupt 6 */ PIN_INT7_IRQn = 39, /*!< 39 GPIO pin interrupt 7 */ GINT0_IRQn = 40, /*!< 40 GPIO global interrupt 0 */ GINT1_IRQn = 41, /*!< 41 GPIO global interrupt 1 */ EVENTROUTER_IRQn = 42, /*!< 42 Event router interrupt */ C_CAN1_IRQn = 43, /*!< 43 C_CAN1 interrupt */ ADCHS_IRQn = 45, /*!< 45 ADCHS combined interrupt */ ATIMER_IRQn = 46, /*!< 46 Alarm timer interrupt */ RTC_IRQn = 47, /*!< 47 RTC interrupt */ WWDT_IRQn = 49, /*!< 49 WWDT interrupt */ M0SUB_IRQn = 50, /*!< 50 TXEV instruction from the M0 subsystem core interrupt */ C_CAN0_IRQn = 51, /*!< 51 C_CAN0 interrupt */ QEI_IRQn = 52, /*!< 52 QEI interrupt */ #endif #ifdef CORE_M0 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ // --------------------------- LPC43xx/M0App Specific Interrupt Numbers ------------------------- M0_RTC_IRQn = 0, /*!< 0 RTC interrupt */ M0_M4CORE_IRQn = 1, /*!< 1 M4 core interrupt */ M0_DMA_IRQn = 2, /*!< 2 DMA interrupt */ M0_FLASHEEPROMAT_IRQn = 4, /*!< 4 flash bank A, flash bank B, EEPROM, Atimer ORed interrupt */ M0_ETHERNET_IRQn = 5, /*!< 5 Ethernet interrupt */ M0_SDIO_IRQn = 6, /*!< 6 SD/MMC interrupt */ M0_LCD_IRQn = 7, /*!< 7 LCD interrupt */ M0_USB0_IRQn = 8, /*!< 8 OTG interrupt */ M0_USB1_IRQn = 9, /*!< 9 USB1 interrupt */ M0_SCT_IRQn = 10, /*!< 10 SCT combined interrupt */ M0_RITIMER_OR_WWDT_IRQn = 11, /*!< 11 RI timer, WWDT ORed interrupt */ M0_TIMER0_IRQn = 12, /*!< 12 Timer 0 interrupt */ M0_GINT1_IRQn = 13, /*!< 13 GPIO global interrupt 1 */ M0_PIN_INT4_IRQn = 14, /*!< 14 GPIO pin interrupt 4 */ M0_TIMER3_IRQn = 15, /*!< 15 Timer 3 */ M0_MCPWM_IRQn = 16, /*!< 16 Motor control PWM interrupt */ M0_ADC0_IRQn = 17, /*!< 17 ADC0 interrupt */ M0_I2C0_OR_I2C1_IRQn = 18, /*!< 18 I2C0, I2C1 ORed interrupt */ M0_SGPIO_IRQn = 19, /*!< 19 SGPIO interrupt */ M0_SPI_OR_DAC_IRQn = 20, /*!< 20 SPI, DAC ORed interrupt */ M0_ADC1_IRQn = 21, /*!< 21 ADC1 interrupt */ M0_SSP0_OR_SSP1_IRQn = 22, /*!< 22 SSP0, SSP 1 ORed interrupt */ M0_EVENTROUTER_IRQn = 23, /*!< 23 Event router interrupt */ M0_USART0_IRQn = 24, /*!< 24 USART0 interrupt */ M0_UART1_IRQn = 25, /*!< 25 Modem/UART1 interrupt */ M0_USART2_OR_C_CAN1_IRQn = 26, /*!< 26 USART2, C_CAN1 ORed interrupt */ M0_USART3_IRQn = 27, /*!< 27 USART3 interrupt */ M0_I2S0_OR_I2S1_QEI_IRQn = 28, /*!< 28 I2S0, I2S1, QEI ORed interrupt */ M0_C_CAN0_IRQn = 29, /*!< 29 C_CAN0 interrupt */ M0_SPIFI_OR_ADCHS_IRQn = 30, /*!< 30 SPIFI, ADCHS ORed interrupt */ M0_M0SUB_IRQn = 31, /*!< 31 M0SUB core interrupt */ #endif #ifdef CORE_M0SUB /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ SysTick_IRQn = -1, /*!< 15 System Tick Timer */ // --------------------------- LPC43xx/M0Sub Specific Interrupt Numbers ------------------------- M0S_RTC_IRQn = 0, /*!< 0 RTC interrupt */ M0S_M4CORE_IRQn = 1, /*!< 1 M4 core interrupt */ M0S_DMA_IRQn = 2, /*!< 2 DMA interrupt */ M0S_SGPIO_INPUT_IRQn = 4, /*!< 4 SGPIO input bit match interrupt */ M0S_SGPIO_MATCH_IRQn = 5, /*!< 5 SGPIO pattern match interrupt */ M0S_SGPIO_SHIFT_IRQn = 6, /*!< 6 SGPIO shift clock interrupt */ M0S_SGPIO_POS_IRQn = 7, /*!< 7 SGPIO capture clock interrupt */ M0S_USB0_IRQn = 8, /*!< 8 OTG interrupt */ M0S_USB1_IRQn = 9, /*!< 9 USB1 interrupt */ M0S_SCT_IRQn = 10, /*!< 10 SCT combined interrup */ M0S_RITIMER_IRQn = 11, /*!< 11 RI timer interrupt */ M0S_GINT1_IRQn = 12, /*!< 12 GPIO global interrupt 1 */ M0S_TIMER1_IRQn = 13, /*!< 13 Timer 1 interrupt */ M0S_TIMER2_IRQn = 14, /*!< 14 Timer 2 interrupt */ M0S_PIN_INT5_IRQn = 15, /*!< 15 GPIO pin interrupt 5 */ M0S_MCPWM_IRQn = 16, /*!< 16 Motor control PWM interrupt */ M0S_ADC0_IRQn = 17, /*!< 17 ADC0 interrupt */ M0S_I2C0_IRQn = 18, /*!< 18 I2C0 interrupt */ M0S_I2C1_IRQn = 19, /*!< 19 I2C1 interrupt */ M0S_SPI_IRQn = 20, /*!< 20 SPI interrupt */ M0S_ADC1_IRQn = 21, /*!< 21 ADC1 interrupt */ M0S_SSP0_OR_SSP1_IRQn = 22, /*!< 22 SSP0, SSP1 ORed interrupt */ M0S_EVENTROUTER_IRQn = 23, /*!< 23 Event router interrupt */ M0S_USART0_IRQn = 24, /*!< 24 USART0 interrupt */ M0S_UART1_IRQn = 25, /*!< 25 Modem/UART1 interrupt */ MS0_USART2_OR_C_CAN1_IRQn = 26, /*!< 26 USART2, C_CAN1 ORed interrupt */ M0S_USART3_IRQn = 27, /*!< 27 USART3 interrupt */ M0S_I2S0_OR_I2S1_OR_QEI_IRQn = 28, /*!< 28 I2S0, I2S1, QEI ORed interrupt */ M0S_C_CAN0_IRQn = 29, /*!< 29 C_CAN0 interrupt */ M0S_SPIFI_OR_ADCHS_IRQn = 30, /*!< 30 SPIFI, ADCHS ORed interrupt */ M0S_M0APP_IRQn = 31, /*!< 31 M0APP core interrupt */ #endif } IRQn_Type; /* Event Router Input (ERI) Number Definitions */ typedef enum { WAKEUP0_ERIn = 0, WAKEUP1_ERIn = 1, WAKEUP2_ERIn = 2, WAKEUP3_ERIn = 3, ATIMER_ERIn = 4, RTC_ERIn = 5, BOD1_ERIn = 6, /* Bod trip 1 */ WWDT_ERIn = 7, ETH_ERIn = 8, USB0_ERIn = 9, USB1_ERIn = 10, SDIO_ERIn = 11, CAN_ERIn = 12, /* CAN0/1 or'ed */ TIM2_ERIn = 13, TIM6_ERIn = 14, QEI_ERIn = 15, TIM14_ERIn = 16, RESERVED0_ERIn = 17, /* M0s */ RESERVED1_ERIn = 18, /* M3/M4 */ RESET_ERIn = 19 }ERIn_Type; /** @addtogroup Configuration_of_CMSIS * @{ */ /* ================================================================================ */ /* ================ Processor and Core Peripheral Section ================ */ /* ================================================================================ */ #if defined CORE_M4 /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */ #define __MPU_PRESENT 1 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /*!< FPU present or not */ #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ #endif #if defined CORE_M0 || defined CORE_M0SUB /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ #define __MPU_PRESENT 0 /*!< MPU present or not */ #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 0 /*!< FPU present or not */ #include "core_cm0.h" /*!< Cortex-M4 processor and core peripherals */ #endif /** @} */ /* End of group Configuration_of_CMSIS */ #include "system_LPC43xx.h" /*!< LPC43xx System */ /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ /* ================================================================================ */ /** @addtogroup Device_Peripheral_Registers * @{ */ /* ------------------- Start of section using anonymous unions ------------------ */ #if defined(__CC_ARM) #pragma push #pragma anon_unions #elif defined(__ICCARM__) #pragma language=extended #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) #pragma warning 586 #else #warning Not supported compiler type #endif /* ================================================================================ */ /* ================ SCT ================ */ /* ================================================================================ */ /** * @brief State Configurable Timer (SCT) with dither engine (SCT) */ typedef struct { /*!< (@ 0x40000000) SCT Structure */ __IO uint32_t CONFIG; /*!< (@ 0x40000000) SCT configuration register */ __IO uint32_t CTRL; /*!< (@ 0x40000004) SCT control register */ __IO uint32_t LIMIT; /*!< (@ 0x40000008) SCT limit register */ __IO uint32_t HALT; /*!< (@ 0x4000000C) SCT halt condition register */ __IO uint32_t STOP; /*!< (@ 0x40000010) SCT stop condition register */ __IO uint32_t START; /*!< (@ 0x40000014) SCT start condition register */ __IO uint32_t DITHER; /*!< (@ 0x40000018) SCT dither condition register */ __I uint32_t RESERVED0[9]; __IO uint32_t COUNT; /*!< (@ 0x40000040) SCT counter register */ __IO uint32_t STATE; /*!< (@ 0x40000044) SCT state register */ __I uint32_t INPUT; /*!< (@ 0x40000048) SCT input register */ __IO uint32_t REGMODE; /*!< (@ 0x4000004C) SCT match/capture registers mode register */ __IO uint32_t OUTPUT; /*!< (@ 0x40000050) SCT output register */ __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x40000054) SCT output counter direction control register */ __IO uint32_t RES; /*!< (@ 0x40000058) SCT conflict resolution register */ __IO uint32_t DMAREQ0; /*!< (@ 0x4000005C) SCT DMA request 0 register */ __IO uint32_t DMAREQ1; /*!< (@ 0x40000060) SCT DMA request 1 register */ __I uint32_t RESERVED1[35]; __IO uint32_t EVEN; /*!< (@ 0x400000F0) SCT event enable register */ __IO uint32_t EVFLAG; /*!< (@ 0x400000F4) SCT event flag register */ __IO uint32_t CONEN; /*!< (@ 0x400000F8) SCT conflict enable register */ __IO uint32_t CONFLAG; /*!< (@ 0x400000FC) SCT conflict flag register */ union { __IO uint32_t CAP0; /*!< (@ 0x40000100) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ __IO uint32_t MATCH0; /*!< (@ 0x40000100) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ }; union { __IO uint32_t CAP1; /*!< (@ 0x40000104) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ __IO uint32_t MATCH1; /*!< (@ 0x40000104) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ }; union { __IO uint32_t CAP2; /*!< (@ 0x40000108) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ __IO uint32_t MATCH2; /*!< (@ 0x40000108) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ }; union { __IO uint32_t CAP3; /*!< (@ 0x4000010C) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ __IO uint32_t MATCH3; /*!< (@ 0x4000010C) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ }; union { __IO uint32_t MATCH4; /*!< (@ 0x40000110) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP4; /*!< (@ 0x40000110) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t CAP5; /*!< (@ 0x40000114) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ __IO uint32_t MATCH5; /*!< (@ 0x40000114) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ }; union { __IO uint32_t MATCH6; /*!< (@ 0x40000118) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP6; /*!< (@ 0x40000118) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t MATCH7; /*!< (@ 0x4000011C) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP7; /*!< (@ 0x4000011C) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t MATCH8; /*!< (@ 0x40000120) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP8; /*!< (@ 0x40000120) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t MATCH9; /*!< (@ 0x40000124) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP9; /*!< (@ 0x40000124) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t MATCH10; /*!< (@ 0x40000128) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP10; /*!< (@ 0x40000128) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t MATCH11; /*!< (@ 0x4000012C) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP11; /*!< (@ 0x4000012C) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t MATCH12; /*!< (@ 0x40000130) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP12; /*!< (@ 0x40000130) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t CAP13; /*!< (@ 0x40000134) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ __IO uint32_t MATCH13; /*!< (@ 0x40000134) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ }; union { __IO uint32_t MATCH14; /*!< (@ 0x40000138) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ __IO uint32_t CAP14; /*!< (@ 0x40000138) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ }; union { __IO uint32_t CAP15; /*!< (@ 0x4000013C) SCT capture register of capture channel 0 to 15; REGMOD0 to REGMODE15 = 1 */ __IO uint32_t MATCH15; /*!< (@ 0x4000013C) SCT match value register of match channels 0 to 15; REGMOD0 to REGMODE15 = 0 */ }; __IO uint32_t FRACMAT0; /*!< (@ 0x40000140) Fractional match registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMAT1; /*!< (@ 0x40000144) Fractional match registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMAT2; /*!< (@ 0x40000148) Fractional match registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMAT3; /*!< (@ 0x4000014C) Fractional match registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMAT4; /*!< (@ 0x40000150) Fractional match registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMAT5; /*!< (@ 0x40000154) Fractional match registers 0 to 5 for SCT match value registers 0 to 5. */ __I uint32_t RESERVED2[42]; union { __IO uint32_t CAPCTRL0; /*!< (@ 0x40000200) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL0; /*!< (@ 0x40000200) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; union { __IO uint32_t MATCHREL1; /*!< (@ 0x40000204) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ __IO uint32_t CAPCTRL1; /*!< (@ 0x40000204) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ }; union { __IO uint32_t CAPCTRL2; /*!< (@ 0x40000208) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL2; /*!< (@ 0x40000208) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; union { __IO uint32_t MATCHREL3; /*!< (@ 0x4000020C) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ __IO uint32_t CAPCTRL3; /*!< (@ 0x4000020C) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ }; union { __IO uint32_t CAPCTRL4; /*!< (@ 0x40000210) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL4; /*!< (@ 0x40000210) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; union { __IO uint32_t CAPCTRL5; /*!< (@ 0x40000214) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL5; /*!< (@ 0x40000214) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; union { __IO uint32_t MATCHREL6; /*!< (@ 0x40000218) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ __IO uint32_t CAPCTRL6; /*!< (@ 0x40000218) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ }; union { __IO uint32_t CAPCTRL7; /*!< (@ 0x4000021C) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL7; /*!< (@ 0x4000021C) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; union { __IO uint32_t MATCHREL8; /*!< (@ 0x40000220) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ __IO uint32_t CAPCTRL8; /*!< (@ 0x40000220) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ }; union { __IO uint32_t CAPCTRL9; /*!< (@ 0x40000224) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL9; /*!< (@ 0x40000224) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; union { __IO uint32_t MATCHREL10; /*!< (@ 0x40000228) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ __IO uint32_t CAPCTRL10; /*!< (@ 0x40000228) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ }; union { __IO uint32_t MATCHREL11; /*!< (@ 0x4000022C) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ __IO uint32_t CAPCTRL11; /*!< (@ 0x4000022C) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ }; union { __IO uint32_t MATCHREL12; /*!< (@ 0x40000230) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ __IO uint32_t CAPCTRL12; /*!< (@ 0x40000230) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ }; union { __IO uint32_t CAPCTRL13; /*!< (@ 0x40000234) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL13; /*!< (@ 0x40000234) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; union { __IO uint32_t CAPCTRL14; /*!< (@ 0x40000238) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL14; /*!< (@ 0x40000238) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; union { __IO uint32_t CAPCTRL15; /*!< (@ 0x4000023C) SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15 = 1 */ __IO uint32_t MATCHREL15; /*!< (@ 0x4000023C) SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15 = 0 */ }; __IO uint32_t FRACMATREL0; /*!< (@ 0x40000240) Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMATREL1; /*!< (@ 0x40000244) Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMATREL2; /*!< (@ 0x40000248) Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMATREL3; /*!< (@ 0x4000024C) Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMATREL4; /*!< (@ 0x40000250) Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5. */ __IO uint32_t FRACMATREL5; /*!< (@ 0x40000254) Fractional match reload registers 0 to 5 for SCT match value registers 0 to 5. */ __I uint32_t RESERVED3[42]; __IO uint32_t EV0_STATE; /*!< (@ 0x40000300) SCT event state register 0 */ __IO uint32_t EV0_CTRL; /*!< (@ 0x40000304) SCT event control register 0 */ __IO uint32_t EV1_STATE; /*!< (@ 0x40000308) SCT event state register 0 */ __IO uint32_t EV1_CTRL; /*!< (@ 0x4000030C) SCT event control register 0 */ __IO uint32_t EV2_STATE; /*!< (@ 0x40000310) SCT event state register 0 */ __IO uint32_t EV2_CTRL; /*!< (@ 0x40000314) SCT event control register 0 */ __IO uint32_t EV3_STATE; /*!< (@ 0x40000318) SCT event state register 0 */ __IO uint32_t EV3_CTRL; /*!< (@ 0x4000031C) SCT event control register 0 */ __IO uint32_t EV4_STATE; /*!< (@ 0x40000320) SCT event state register 0 */ __IO uint32_t EV4_CTRL; /*!< (@ 0x40000324) SCT event control register 0 */ __IO uint32_t EV5_STATE; /*!< (@ 0x40000328) SCT event state register 0 */ __IO uint32_t EV5_CTRL; /*!< (@ 0x4000032C) SCT event control register 0 */ __IO uint32_t EV6_STATE; /*!< (@ 0x40000330) SCT event state register 0 */ __IO uint32_t EV6_CTRL; /*!< (@ 0x40000334) SCT event control register 0 */ __IO uint32_t EV7_STATE; /*!< (@ 0x40000338) SCT event state register 0 */ __IO uint32_t EV7_CTRL; /*!< (@ 0x4000033C) SCT event control register 0 */ __IO uint32_t EV8_STATE; /*!< (@ 0x40000340) SCT event state register 0 */ __IO uint32_t EV8_CTRL; /*!< (@ 0x40000344) SCT event control register 0 */ __IO uint32_t EV9_STATE; /*!< (@ 0x40000348) SCT event state register 0 */ __IO uint32_t EV9_CTRL; /*!< (@ 0x4000034C) SCT event control register 0 */ __IO uint32_t EV10_STATE; /*!< (@ 0x40000350) SCT event state register 0 */ __IO uint32_t EV10_CTRL; /*!< (@ 0x40000354) SCT event control register 0 */ __IO uint32_t EV11_STATE; /*!< (@ 0x40000358) SCT event state register 0 */ __IO uint32_t EV11_CTRL; /*!< (@ 0x4000035C) SCT event control register 0 */ __IO uint32_t EV12_STATE; /*!< (@ 0x40000360) SCT event state register 0 */ __IO uint32_t EV12_CTRL; /*!< (@ 0x40000364) SCT event control register 0 */ __IO uint32_t EV13_STATE; /*!< (@ 0x40000368) SCT event state register 0 */ __IO uint32_t EV13_CTRL; /*!< (@ 0x4000036C) SCT event control register 0 */ __IO uint32_t EV14_STATE; /*!< (@ 0x40000370) SCT event state register 0 */ __IO uint32_t EV14_CTRL; /*!< (@ 0x40000374) SCT event control register 0 */ __IO uint32_t EV15_STATE; /*!< (@ 0x40000378) SCT event state register 0 */ __IO uint32_t EV15_CTRL; /*!< (@ 0x4000037C) SCT event control register 0 */ __I uint32_t RESERVED4[96]; __IO uint32_t OUT0_SET; /*!< (@ 0x40000500) SCT output 0 set register */ __IO uint32_t OUT0_CLR; /*!< (@ 0x40000504) SCT output 0 clear register */ __IO uint32_t OUT1_SET; /*!< (@ 0x40000508) SCT output 0 set register */ __IO uint32_t OUT1_CLR; /*!< (@ 0x4000050C) SCT output 0 clear register */ __IO uint32_t OUT2_SET; /*!< (@ 0x40000510) SCT output 0 set register */ __IO uint32_t OUT2_CLR; /*!< (@ 0x40000514) SCT output 0 clear register */ __IO uint32_t OUT3_SET; /*!< (@ 0x40000518) SCT output 0 set register */ __IO uint32_t OUT3_CLR; /*!< (@ 0x4000051C) SCT output 0 clear register */ __IO uint32_t OUT4_SET; /*!< (@ 0x40000520) SCT output 0 set register */ __IO uint32_t OUT4_CLR; /*!< (@ 0x40000524) SCT output 0 clear register */ __IO uint32_t OUT5_SET; /*!< (@ 0x40000528) SCT output 0 set register */ __IO uint32_t OUT5_CLR; /*!< (@ 0x4000052C) SCT output 0 clear register */ __IO uint32_t OUT6_SET; /*!< (@ 0x40000530) SCT output 0 set register */ __IO uint32_t OUT6_CLR; /*!< (@ 0x40000534) SCT output 0 clear register */ __IO uint32_t OUT7_SET; /*!< (@ 0x40000538) SCT output 0 set register */ __IO uint32_t OUT7_CLR; /*!< (@ 0x4000053C) SCT output 0 clear register */ __IO uint32_t OUT8_SET; /*!< (@ 0x40000540) SCT output 0 set register */ __IO uint32_t OUT8_CLR; /*!< (@ 0x40000544) SCT output 0 clear register */ __IO uint32_t OUT9_SET; /*!< (@ 0x40000548) SCT output 0 set register */ __IO uint32_t OUT9_CLR; /*!< (@ 0x4000054C) SCT output 0 clear register */ __IO uint32_t OUT10_SET; /*!< (@ 0x40000550) SCT output 0 set register */ __IO uint32_t OUT10_CLR; /*!< (@ 0x40000554) SCT output 0 clear register */ __IO uint32_t OUT11_SET; /*!< (@ 0x40000558) SCT output 0 set register */ __IO uint32_t OUT11_CLR; /*!< (@ 0x4000055C) SCT output 0 clear register */ __IO uint32_t OUT12_SET; /*!< (@ 0x40000560) SCT output 0 set register */ __IO uint32_t OUT12_CLR; /*!< (@ 0x40000564) SCT output 0 clear register */ __IO uint32_t OUT13_SET; /*!< (@ 0x40000568) SCT output 0 set register */ __IO uint32_t OUT13_CLR; /*!< (@ 0x4000056C) SCT output 0 clear register */ __IO uint32_t OUT14_SET; /*!< (@ 0x40000570) SCT output 0 set register */ __IO uint32_t OUT14_CLR; /*!< (@ 0x40000574) SCT output 0 clear register */ __IO uint32_t OUT15_SET; /*!< (@ 0x40000578) SCT output 0 set register */ __IO uint32_t OUT15_CLR; /*!< (@ 0x4000057C) SCT output 0 clear register */ } LPC_SCT_Type; /* ================================================================================ */ /* ================ GPDMA ================ */ /* ================================================================================ */ /** * @brief General Purpose DMA (GPDMA) (GPDMA) */ typedef struct { /*!< (@ 0x40002000) GPDMA Structure */ __I uint32_t INTSTAT; /*!< (@ 0x40002000) DMA Interrupt Status Register */ __I uint32_t INTTCSTAT; /*!< (@ 0x40002004) DMA Interrupt Terminal Count Request Status Register */ __O uint32_t INTTCCLEAR; /*!< (@ 0x40002008) DMA Interrupt Terminal Count Request Clear Register */ __I uint32_t INTERRSTAT; /*!< (@ 0x4000200C) DMA Interrupt Error Status Register */ __O uint32_t INTERRCLR; /*!< (@ 0x40002010) DMA Interrupt Error Clear Register */ __I uint32_t RAWINTTCSTAT; /*!< (@ 0x40002014) DMA Raw Interrupt Terminal Count Status Register */ __I uint32_t RAWINTERRSTAT; /*!< (@ 0x40002018) DMA Raw Error Interrupt Status Register */ __I uint32_t ENBLDCHNS; /*!< (@ 0x4000201C) DMA Enabled Channel Register */ __IO uint32_t SOFTBREQ; /*!< (@ 0x40002020) DMA Software Burst Request Register */ __IO uint32_t SOFTSREQ; /*!< (@ 0x40002024) DMA Software Single Request Register */ __IO uint32_t SOFTLBREQ; /*!< (@ 0x40002028) DMA Software Last Burst Request Register */ __IO uint32_t SOFTLSREQ; /*!< (@ 0x4000202C) DMA Software Last Single Request Register */ __IO uint32_t CONFIG; /*!< (@ 0x40002030) DMA Configuration Register */ __IO uint32_t SYNC; /*!< (@ 0x40002034) DMA Synchronization Register */ __I uint32_t RESERVED0[50]; __IO uint32_t C0SRCADDR; /*!< (@ 0x40002100) DMA Channel Source Address Register */ __IO uint32_t C0DESTADDR; /*!< (@ 0x40002104) DMA Channel Destination Address Register */ __IO uint32_t C0LLI; /*!< (@ 0x40002108) DMA Channel Linked List Item Register */ __IO uint32_t C0CONTROL; /*!< (@ 0x4000210C) DMA Channel Control Register */ __IO uint32_t C0CONFIG; /*!< (@ 0x40002110) DMA Channel Configuration Register */ __I uint32_t RESERVED1[3]; __IO uint32_t C1SRCADDR; /*!< (@ 0x40002120) DMA Channel Source Address Register */ __IO uint32_t C1DESTADDR; /*!< (@ 0x40002124) DMA Channel Destination Address Register */ __IO uint32_t C1LLI; /*!< (@ 0x40002128) DMA Channel Linked List Item Register */ __IO uint32_t C1CONTROL; /*!< (@ 0x4000212C) DMA Channel Control Register */ __IO uint32_t C1CONFIG; /*!< (@ 0x40002130) DMA Channel Configuration Register */ __I uint32_t RESERVED2[3]; __IO uint32_t C2SRCADDR; /*!< (@ 0x40002140) DMA Channel Source Address Register */ __IO uint32_t C2DESTADDR; /*!< (@ 0x40002144) DMA Channel Destination Address Register */ __IO uint32_t C2LLI; /*!< (@ 0x40002148) DMA Channel Linked List Item Register */ __IO uint32_t C2CONTROL; /*!< (@ 0x4000214C) DMA Channel Control Register */ __IO uint32_t C2CONFIG; /*!< (@ 0x40002150) DMA Channel Configuration Register */ __I uint32_t RESERVED3[3]; __IO uint32_t C3SRCADDR; /*!< (@ 0x40002160) DMA Channel Source Address Register */ __IO uint32_t C3DESTADDR; /*!< (@ 0x40002164) DMA Channel Destination Address Register */ __IO uint32_t C3LLI; /*!< (@ 0x40002168) DMA Channel Linked List Item Register */ __IO uint32_t C3CONTROL; /*!< (@ 0x4000216C) DMA Channel Control Register */ __IO uint32_t C3CONFIG; /*!< (@ 0x40002170) DMA Channel Configuration Register */ __I uint32_t RESERVED4[3]; __IO uint32_t C4SRCADDR; /*!< (@ 0x40002180) DMA Channel Source Address Register */ __IO uint32_t C4DESTADDR; /*!< (@ 0x40002184) DMA Channel Destination Address Register */ __IO uint32_t C4LLI; /*!< (@ 0x40002188) DMA Channel Linked List Item Register */ __IO uint32_t C4CONTROL; /*!< (@ 0x4000218C) DMA Channel Control Register */ __IO uint32_t C4CONFIG; /*!< (@ 0x40002190) DMA Channel Configuration Register */ __I uint32_t RESERVED5[3]; __IO uint32_t C5SRCADDR; /*!< (@ 0x400021A0) DMA Channel Source Address Register */ __IO uint32_t C5DESTADDR; /*!< (@ 0x400021A4) DMA Channel Destination Address Register */ __IO uint32_t C5LLI; /*!< (@ 0x400021A8) DMA Channel Linked List Item Register */ __IO uint32_t C5CONTROL; /*!< (@ 0x400021AC) DMA Channel Control Register */ __IO uint32_t C5CONFIG; /*!< (@ 0x400021B0) DMA Channel Configuration Register */ __I uint32_t RESERVED6[3]; __IO uint32_t C6SRCADDR; /*!< (@ 0x400021C0) DMA Channel Source Address Register */ __IO uint32_t C6DESTADDR; /*!< (@ 0x400021C4) DMA Channel Destination Address Register */ __IO uint32_t C6LLI; /*!< (@ 0x400021C8) DMA Channel Linked List Item Register */ __IO uint32_t C6CONTROL; /*!< (@ 0x400021CC) DMA Channel Control Register */ __IO uint32_t C6CONFIG; /*!< (@ 0x400021D0) DMA Channel Configuration Register */ __I uint32_t RESERVED7[3]; __IO uint32_t C7SRCADDR; /*!< (@ 0x400021E0) DMA Channel Source Address Register */ __IO uint32_t C7DESTADDR; /*!< (@ 0x400021E4) DMA Channel Destination Address Register */ __IO uint32_t C7LLI; /*!< (@ 0x400021E8) DMA Channel Linked List Item Register */ __IO uint32_t C7CONTROL; /*!< (@ 0x400021EC) DMA Channel Control Register */ __IO uint32_t C7CONFIG; /*!< (@ 0x400021F0) DMA Channel Configuration Register */ } LPC_GPDMA_Type; /* ================================================================================ */ /* ================ SPIFI ================ */ /* ================================================================================ */ /** * @brief SPI Flash Interface (SPIFI) (SPIFI) */ typedef struct { /*!< (@ 0x40003000) SPIFI Structure */ __IO uint32_t CTRL; /*!< (@ 0x40003000) SPIFI control register */ __IO uint32_t CMD; /*!< (@ 0x40003004) SPIFI command register */ __IO uint32_t ADDR; /*!< (@ 0x40003008) SPIFI address register */ __IO uint32_t IDATA; /*!< (@ 0x4000300C) SPIFI intermediate data register */ __IO uint32_t CLIMIT; /*!< (@ 0x40003010) SPIFI cache limit register */ __IO uint32_t DATA; /*!< (@ 0x40003014) SPIFI data register */ __IO uint32_t MCMD; /*!< (@ 0x40003018) SPIFI memory command register */ __IO uint32_t STAT; /*!< (@ 0x4000301C) SPIFI status register */ } LPC_SPIFI_Type; /* ================================================================================ */ /* ================ SDMMC ================ */ /* ================================================================================ */ /** * @brief SD/MMC (SDMMC) */ typedef struct { /*!< (@ 0x40004000) SDMMC Structure */ __IO uint32_t CTRL; /*!< (@ 0x40004000) Control Register */ __IO uint32_t PWREN; /*!< (@ 0x40004004) Power Enable Register */ __IO uint32_t CLKDIV; /*!< (@ 0x40004008) Clock Divider Register */ __IO uint32_t CLKSRC; /*!< (@ 0x4000400C) SD Clock Source Register */ __IO uint32_t CLKENA; /*!< (@ 0x40004010) Clock Enable Register */ __IO uint32_t TMOUT; /*!< (@ 0x40004014) Time-out Register */ __IO uint32_t CTYPE; /*!< (@ 0x40004018) Card Type Register */ __IO uint32_t BLKSIZ; /*!< (@ 0x4000401C) Block Size Register */ __IO uint32_t BYTCNT; /*!< (@ 0x40004020) Byte Count Register */ __IO uint32_t INTMASK; /*!< (@ 0x40004024) Interrupt Mask Register */ __IO uint32_t CMDARG; /*!< (@ 0x40004028) Command Argument Register */ __IO uint32_t CMD; /*!< (@ 0x4000402C) Command Register */ __I uint32_t RESP0; /*!< (@ 0x40004030) Response Register 0 */ __I uint32_t RESP1; /*!< (@ 0x40004034) Response Register 1 */ __I uint32_t RESP2; /*!< (@ 0x40004038) Response Register 2 */ __I uint32_t RESP3; /*!< (@ 0x4000403C) Response Register 3 */ __I uint32_t MINTSTS; /*!< (@ 0x40004040) Masked Interrupt Status Register */ __IO uint32_t RINTSTS; /*!< (@ 0x40004044) Raw Interrupt Status Register */ __I uint32_t STATUS; /*!< (@ 0x40004048) Status Register */ __IO uint32_t FIFOTH; /*!< (@ 0x4000404C) FIFO Threshold Watermark Register */ __I uint32_t CDETECT; /*!< (@ 0x40004050) Card Detect Register */ __I uint32_t WRTPRT; /*!< (@ 0x40004054) Write Protect Register */ __I uint32_t RESERVED0; __I uint32_t TCBCNT; /*!< (@ 0x4000405C) Transferred CIU Card Byte Count Register */ __I uint32_t TBBCNT; /*!< (@ 0x40004060) Transferred Host to BIU-FIFO Byte Count Register */ __IO uint32_t DEBNCE; /*!< (@ 0x40004064) Debounce Count Register */ __I uint32_t RESERVED1[4]; __IO uint32_t RST_N; /*!< (@ 0x40004078) Hardware Reset */ __I uint32_t RESERVED2; __IO uint32_t BMOD; /*!< (@ 0x40004080) Bus Mode Register */ __O uint32_t PLDMND; /*!< (@ 0x40004084) Poll Demand Register */ __IO uint32_t DBADDR; /*!< (@ 0x40004088) Descriptor List Base Address Register */ __IO uint32_t IDSTS; /*!< (@ 0x4000408C) Internal DMAC Status Register */ __IO uint32_t IDINTEN; /*!< (@ 0x40004090) Internal DMAC Interrupt Enable Register */ __I uint32_t DSCADDR; /*!< (@ 0x40004094) Current Host Descriptor Address Register */ __I uint32_t BUFADDR; /*!< (@ 0x40004098) Current Buffer Descriptor Address Register */ } LPC_SDMMC_Type; /* ================================================================================ */ /* ================ EMC ================ */ /* ================================================================================ */ /** * @brief External Memory Controller (EMC) (EMC) */ typedef struct { /*!< (@ 0x40005000) EMC Structure */ __IO uint32_t CONTROL; /*!< (@ 0x40005000) Controls operation of the memory controller. */ __I uint32_t STATUS; /*!< (@ 0x40005004) Provides EMC status information. */ __IO uint32_t CONFIG; /*!< (@ 0x40005008) Configures operation of the memory controller. */ __I uint32_t RESERVED0[5]; __IO uint32_t DYNAMICCONTROL; /*!< (@ 0x40005020) Controls dynamic memory operation. */ __IO uint32_t DYNAMICREFRESH; /*!< (@ 0x40005024) Configures dynamic memory refresh operation. */ __IO uint32_t DYNAMICREADCONFIG; /*!< (@ 0x40005028) Configures the dynamic memory read strategy. */ __I uint32_t RESERVED1; __IO uint32_t DYNAMICRP; /*!< (@ 0x40005030) Selects the precharge command period. */ __IO uint32_t DYNAMICRAS; /*!< (@ 0x40005034) Selects the active to precharge command period. */ __IO uint32_t DYNAMICSREX; /*!< (@ 0x40005038) Selects the self-refresh exit time. */ __IO uint32_t DYNAMICAPR; /*!< (@ 0x4000503C) Selects the last-data-out to active command time. */ __IO uint32_t DYNAMICDAL; /*!< (@ 0x40005040) Selects the data-in to active command time. */ __IO uint32_t DYNAMICWR; /*!< (@ 0x40005044) Selects the write recovery time. */ __IO uint32_t DYNAMICRC; /*!< (@ 0x40005048) Selects the active to active command period. */ __IO uint32_t DYNAMICRFC; /*!< (@ 0x4000504C) Selects the auto-refresh period. */ __IO uint32_t DYNAMICXSR; /*!< (@ 0x40005050) Selects the exit self-refresh to active command time. */ __IO uint32_t DYNAMICRRD; /*!< (@ 0x40005054) Selects the active bank A to active bank B latency. */ __IO uint32_t DYNAMICMRD; /*!< (@ 0x40005058) Selects the load mode register to active command time. */ __I uint32_t RESERVED2[9]; __IO uint32_t STATICEXTENDEDWAIT; /*!< (@ 0x40005080) Selects time for long static memory read and write transfers. */ __I uint32_t RESERVED3[31]; __IO uint32_t DYNAMICCONFIG0; /*!< (@ 0x40005100) Selects the configuration information for dynamic memory chip select 0. */ __IO uint32_t DYNAMICRASCAS0; /*!< (@ 0x40005104) Selects the RAS and CAS latencies for dynamic memory chip select 0. */ __I uint32_t RESERVED4[6]; __IO uint32_t DYNAMICCONFIG1; /*!< (@ 0x40005120) Selects the configuration information for dynamic memory chip select 0. */ __IO uint32_t DYNAMICRASCAS1; /*!< (@ 0x40005124) Selects the RAS and CAS latencies for dynamic memory chip select 0. */ __I uint32_t RESERVED5[6]; __IO uint32_t DYNAMICCONFIG2; /*!< (@ 0x40005140) Selects the configuration information for dynamic memory chip select 0. */ __IO uint32_t DYNAMICRASCAS2; /*!< (@ 0x40005144) Selects the RAS and CAS latencies for dynamic memory chip select 0. */ __I uint32_t RESERVED6[6]; __IO uint32_t DYNAMICCONFIG3; /*!< (@ 0x40005160) Selects the configuration information for dynamic memory chip select 0. */ __IO uint32_t DYNAMICRASCAS3; /*!< (@ 0x40005164) Selects the RAS and CAS latencies for dynamic memory chip select 0. */ __I uint32_t RESERVED7[38]; __IO uint32_t STATICCONFIG0; /*!< (@ 0x40005200) Selects the memory configuration for static chip select 0. */ __IO uint32_t STATICWAITWEN0; /*!< (@ 0x40005204) Selects the delay from chip select 0 to write enable. */ __IO uint32_t STATICWAITOEN0; /*!< (@ 0x40005208) Selects the delay from chip select 0 or address change, whichever is later, to output enable. */ __IO uint32_t STATICWAITRD0; /*!< (@ 0x4000520C) Selects the delay from chip select 0 to a read access. */ __IO uint32_t STATICWAITPAGE0; /*!< (@ 0x40005210) Selects the delay for asynchronous page mode sequential accesses for chip select 0. */ __IO uint32_t STATICWAITWR0; /*!< (@ 0x40005214) Selects the delay from chip select 0 to a write access. */ __IO uint32_t STATICWAITTURN0; /*!< (@ 0x40005218) Selects the number of bus turnaround cycles for chip select 0. */ __I uint32_t RESERVED8; __IO uint32_t STATICCONFIG1; /*!< (@ 0x40005220) Selects the memory configuration for static chip select 0. */ __IO uint32_t STATICWAITWEN1; /*!< (@ 0x40005224) Selects the delay from chip select 0 to write enable. */ __IO uint32_t STATICWAITOEN1; /*!< (@ 0x40005228) Selects the delay from chip select 0 or address change, whichever is later, to output enable. */ __IO uint32_t STATICWAITRD1; /*!< (@ 0x4000522C) Selects the delay from chip select 0 to a read access. */ __IO uint32_t STATICWAITPAGE1; /*!< (@ 0x40005230) Selects the delay for asynchronous page mode sequential accesses for chip select 0. */ __IO uint32_t STATICWAITWR1; /*!< (@ 0x40005234) Selects the delay from chip select 0 to a write access. */ __IO uint32_t STATICWAITTURN1; /*!< (@ 0x40005238) Selects the number of bus turnaround cycles for chip select 0. */ __I uint32_t RESERVED9; __IO uint32_t STATICCONFIG2; /*!< (@ 0x40005240) Selects the memory configuration for static chip select 0. */ __IO uint32_t STATICWAITWEN2; /*!< (@ 0x40005244) Selects the delay from chip select 0 to write enable. */ __IO uint32_t STATICWAITOEN2; /*!< (@ 0x40005248) Selects the delay from chip select 0 or address change, whichever is later, to output enable. */ __IO uint32_t STATICWAITRD2; /*!< (@ 0x4000524C) Selects the delay from chip select 0 to a read access. */ __IO uint32_t STATICWAITPAGE2; /*!< (@ 0x40005250) Selects the delay for asynchronous page mode sequential accesses for chip select 0. */ __IO uint32_t STATICWAITWR2; /*!< (@ 0x40005254) Selects the delay from chip select 0 to a write access. */ __IO uint32_t STATICWAITTURN2; /*!< (@ 0x40005258) Selects the number of bus turnaround cycles for chip select 0. */ __I uint32_t RESERVED10; __IO uint32_t STATICCONFIG3; /*!< (@ 0x40005260) Selects the memory configuration for static chip select 0. */ __IO uint32_t STATICWAITWEN3; /*!< (@ 0x40005264) Selects the delay from chip select 0 to write enable. */ __IO uint32_t STATICWAITOEN3; /*!< (@ 0x40005268) Selects the delay from chip select 0 or address change, whichever is later, to output enable. */ __IO uint32_t STATICWAITRD3; /*!< (@ 0x4000526C) Selects the delay from chip select 0 to a read access. */ __IO uint32_t STATICWAITPAGE3; /*!< (@ 0x40005270) Selects the delay for asynchronous page mode sequential accesses for chip select 0. */ __IO uint32_t STATICWAITWR3; /*!< (@ 0x40005274) Selects the delay from chip select 0 to a write access. */ __IO uint32_t STATICWAITTURN3; /*!< (@ 0x40005278) Selects the number of bus turnaround cycles for chip select 0. */ } LPC_EMC_Type; /* ================================================================================ */ /* ================ USB0 ================ */ /* ================================================================================ */ /** * @brief USB0 Host/Device/OTG controller (USB0) */ typedef struct { /*!< (@ 0x40006000) USB0 Structure */ __I uint32_t RESERVED0[64]; __I uint32_t CAPLENGTH; /*!< (@ 0x40006100) Capability register length */ __I uint32_t HCSPARAMS; /*!< (@ 0x40006104) Host controller structural parameters */ __I uint32_t HCCPARAMS; /*!< (@ 0x40006108) Host controller capability parameters */ __I uint32_t RESERVED1[5]; __I uint32_t DCIVERSION; /*!< (@ 0x40006120) Device interface version number */ __I uint32_t RESERVED2[7]; union { __IO uint32_t USBCMD_H; /*!< (@ 0x40006140) USB command (host mode) */ __IO uint32_t USBCMD_D; /*!< (@ 0x40006140) USB command (device mode) */ }; union { __IO uint32_t USBSTS_H; /*!< (@ 0x40006144) USB status (host mode) */ __IO uint32_t USBSTS_D; /*!< (@ 0x40006144) USB status (device mode) */ }; union { __IO uint32_t USBINTR_H; /*!< (@ 0x40006148) USB interrupt enable (host mode) */ __IO uint32_t USBINTR_D; /*!< (@ 0x40006148) USB interrupt enable (device mode) */ }; union { __IO uint32_t FRINDEX_H; /*!< (@ 0x4000614C) USB frame index (host mode) */ __IO uint32_t FRINDEX_D; /*!< (@ 0x4000614C) USB frame index (device mode) */ }; __I uint32_t RESERVED3; union { __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40006154) Frame list base address (host mode) */ __IO uint32_t DEVICEADDR; /*!< (@ 0x40006154) USB device address (device mode) */ }; union { __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */ __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40006158) Address of endpoint list in memory */ }; __IO uint32_t TTCTRL; /*!< (@ 0x4000615C) Asynchronous buffer status for embedded TT (host mode) */ __IO uint32_t BURSTSIZE; /*!< (@ 0x40006160) Programmable burst size */ __IO uint32_t TXFILLTUNING; /*!< (@ 0x40006164) Host transmit pre-buffer packet tuning (host mode) */ __I uint32_t RESERVED4[3]; __IO uint32_t BINTERVAL; /*!< (@ 0x40006174) Length of virtual frame */ __IO uint32_t ENDPTNAK; /*!< (@ 0x40006178) Endpoint NAK (device mode) */ __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000617C) Endpoint NAK Enable (device mode) */ __I uint32_t RESERVED5; union { __IO uint32_t PORTSC1_H; /*!< (@ 0x40006184) Port 1 status/control (host mode) */ __IO uint32_t PORTSC1_D; /*!< (@ 0x40006184) Port 1 status/control (device mode) */ }; __I uint32_t RESERVED6[7]; __IO uint32_t OTGSC; /*!< (@ 0x400061A4) OTG status and control */ union { __IO uint32_t USBMODE_H; /*!< (@ 0x400061A8) USB mode (host mode) */ __IO uint32_t USBMODE_D; /*!< (@ 0x400061A8) USB device mode (device mode) */ }; __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400061AC) Endpoint setup status */ __IO uint32_t ENDPTPRIME; /*!< (@ 0x400061B0) Endpoint initialization */ __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400061B4) Endpoint de-initialization */ __I uint32_t ENDPTSTAT; /*!< (@ 0x400061B8) Endpoint status */ __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400061BC) Endpoint complete */ __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400061C0) Endpoint control 0 */ __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400061C4) Endpoint control */ __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400061C8) Endpoint control */ __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400061CC) Endpoint control */ __IO uint32_t ENDPTCTRL4; /*!< (@ 0x400061D0) Endpoint control */ __IO uint32_t ENDPTCTRL5; /*!< (@ 0x400061D4) Endpoint control */ } LPC_USB0_Type; /* ================================================================================ */ /* ================ USB1 ================ */ /* ================================================================================ */ /** * @brief USB1 Host/Device controller (USB1) */ typedef struct { /*!< (@ 0x40007000) USB1 Structure */ __I uint32_t RESERVED0[64]; __I uint32_t CAPLENGTH; /*!< (@ 0x40007100) Capability register length */ __I uint32_t HCSPARAMS; /*!< (@ 0x40007104) Host controller structural parameters */ __I uint32_t HCCPARAMS; /*!< (@ 0x40007108) Host controller capability parameters */ __I uint32_t RESERVED1[5]; __I uint32_t DCIVERSION; /*!< (@ 0x40007120) Device interface version number */ __I uint32_t RESERVED2[7]; union { __IO uint32_t USBCMD_H; /*!< (@ 0x40007140) USB command (host mode) */ __IO uint32_t USBCMD_D; /*!< (@ 0x40007140) USB command (device mode) */ }; union { __IO uint32_t USBSTS_H; /*!< (@ 0x40007144) USB status (host mode) */ __IO uint32_t USBSTS_D; /*!< (@ 0x40007144) USB status (device mode) */ }; union { __IO uint32_t USBINTR_H; /*!< (@ 0x40007148) USB interrupt enable (host mode) */ __IO uint32_t USBINTR_D; /*!< (@ 0x40007148) USB interrupt enable (device mode) */ }; union { __IO uint32_t FRINDEX_H; /*!< (@ 0x4000714C) USB frame index (host mode) */ __I uint32_t FRINDEX_D; /*!< (@ 0x4000714C) USB frame index (device mode) */ }; __I uint32_t RESERVED3; union { __IO uint32_t PERIODICLISTBASE; /*!< (@ 0x40007154) Frame list base address */ __IO uint32_t DEVICEADDR; /*!< (@ 0x40007154) USB device address */ }; union { __IO uint32_t ASYNCLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (host mode) */ __IO uint32_t ENDPOINTLISTADDR; /*!< (@ 0x40007158) Address of endpoint list in memory (device mode) */ }; __IO uint32_t TTCTRL; /*!< (@ 0x4000715C) Asynchronous buffer status for embedded TT (host mode) */ __IO uint32_t BURSTSIZE; /*!< (@ 0x40007160) Programmable burst size */ __IO uint32_t TXFILLTUNING; /*!< (@ 0x40007164) Host transmit pre-buffer packet tuning (host mode) */ __I uint32_t RESERVED4[2]; __IO uint32_t ULPIVIEWPORT; /*!< (@ 0x40007170) ULPI viewport */ __IO uint32_t BINTERVAL; /*!< (@ 0x40007174) Length of virtual frame */ __IO uint32_t ENDPTNAK; /*!< (@ 0x40007178) Endpoint NAK (device mode) */ __IO uint32_t ENDPTNAKEN; /*!< (@ 0x4000717C) Endpoint NAK Enable (device mode) */ __I uint32_t RESERVED5; union { __IO uint32_t PORTSC1_H; /*!< (@ 0x40007184) Port 1 status/control (host mode) */ __IO uint32_t PORTSC1_D; /*!< (@ 0x40007184) Port 1 status/control (device mode) */ }; __I uint32_t RESERVED6[8]; union { __IO uint32_t USBMODE_H; /*!< (@ 0x400071A8) USB mode (host mode) */ __IO uint32_t USBMODE_D; /*!< (@ 0x400071A8) USB mode (device mode) */ }; __IO uint32_t ENDPTSETUPSTAT; /*!< (@ 0x400071AC) Endpoint setup status */ __IO uint32_t ENDPTPRIME; /*!< (@ 0x400071B0) Endpoint initialization */ __IO uint32_t ENDPTFLUSH; /*!< (@ 0x400071B4) Endpoint de-initialization */ __I uint32_t ENDPTSTAT; /*!< (@ 0x400071B8) Endpoint status */ __IO uint32_t ENDPTCOMPLETE; /*!< (@ 0x400071BC) Endpoint complete */ __IO uint32_t ENDPTCTRL0; /*!< (@ 0x400071C0) Endpoint control 0 */ __IO uint32_t ENDPTCTRL1; /*!< (@ 0x400071C4) Endpoint control */ __IO uint32_t ENDPTCTRL2; /*!< (@ 0x400071C8) Endpoint control */ __IO uint32_t ENDPTCTRL3; /*!< (@ 0x400071CC) Endpoint control */ } LPC_USB1_Type; /* ================================================================================ */ /* ================ LCD ================ */ /* ================================================================================ */ /** * @brief LCD controller (LCD) */ typedef struct { /*!< (@ 0x40008000) LCD Structure */ __IO uint32_t TIMH; /*!< (@ 0x40008000) Horizontal Timing Control register */ __IO uint32_t TIMV; /*!< (@ 0x40008004) Vertical Timing Control register */ __IO uint32_t POL; /*!< (@ 0x40008008) Clock and Signal Polarity Control register */ __IO uint32_t LE; /*!< (@ 0x4000800C) Line End Control register */ __IO uint32_t UPBASE; /*!< (@ 0x40008010) Upper Panel Frame Base Address register */ __IO uint32_t LPBASE; /*!< (@ 0x40008014) Lower Panel Frame Base Address register */ __IO uint32_t CTRL; /*!< (@ 0x40008018) LCD Control register */ __IO uint32_t INTMSK; /*!< (@ 0x4000801C) Interrupt Mask register */ __I uint32_t INTRAW; /*!< (@ 0x40008020) Raw Interrupt Status register */ __I uint32_t INTSTAT; /*!< (@ 0x40008024) Masked Interrupt Status register */ __O uint32_t INTCLR; /*!< (@ 0x40008028) Interrupt Clear register */ __I uint32_t UPCURR; /*!< (@ 0x4000802C) Upper Panel Current Address Value register */ __I uint32_t LPCURR; /*!< (@ 0x40008030) Lower Panel Current Address Value register */ __I uint32_t RESERVED0[115]; __IO uint32_t PAL[256]; /*!< (@ 0x40008200) 256x16-bit Color Palette registers */ __I uint32_t RESERVED1[128]; __IO uint32_t CRSR_IMG[256]; /*!< (@ 0x40008800) Cursor Image registers */ __IO uint32_t CRSR_CTRL; /*!< (@ 0x40008C00) Cursor Control register */ __IO uint32_t CRSR_CFG; /*!< (@ 0x40008C04) Cursor Configuration register */ __IO uint32_t CRSR_PAL0; /*!< (@ 0x40008C08) Cursor Palette register 0 */ __IO uint32_t CRSR_PAL1; /*!< (@ 0x40008C0C) Cursor Palette register 1 */ __IO uint32_t CRSR_XY; /*!< (@ 0x40008C10) Cursor XY Position register */ __IO uint32_t CRSR_CLIP; /*!< (@ 0x40008C14) Cursor Clip Position register */ __I uint32_t RESERVED2[2]; __IO uint32_t CRSR_INTMSK; /*!< (@ 0x40008C20) Cursor Interrupt Mask register */ __O uint32_t CRSR_INTCLR; /*!< (@ 0x40008C24) Cursor Interrupt Clear register */ __I uint32_t CRSR_INTRAW; /*!< (@ 0x40008C28) Cursor Raw Interrupt Status register */ __I uint32_t CRSR_INTSTAT; /*!< (@ 0x40008C2C) Cursor Masked Interrupt Status register */ } LPC_LCD_Type; /* ================================================================================ */ /* ================ EEPROM ================ */ /* ================================================================================ */ /** * @brief EEPROM (EEPROM) */ typedef struct { /*!< (@ 0x4000E000) EEPROM Structure */ __IO uint32_t CMD; /*!< (@ 0x4000E000) EEPROM command register */ __I uint32_t RESERVED0; __IO uint32_t RWSTATE; /*!< (@ 0x4000E008) EEPROM read wait state register */ __IO uint32_t AUTOPROG; /*!< (@ 0x4000E00C) EEPROM auto programming register */ __IO uint32_t WSTATE; /*!< (@ 0x4000E010) EEPROM wait state register */ __IO uint32_t CLKDIV; /*!< (@ 0x4000E014) EEPROM clock divider register */ __IO uint32_t PWRDWN; /*!< (@ 0x4000E018) EEPROM power-down register */ __I uint32_t RESERVED1[1007]; __O uint32_t INTENCLR; /*!< (@ 0x4000EFD8) EEPROM interrupt enable clear */ __O uint32_t INTENSET; /*!< (@ 0x4000EFDC) EEPROM interrupt enable set */ __I uint32_t INTSTAT; /*!< (@ 0x4000EFE0) EEPROM interrupt status */ __I uint32_t INTEN; /*!< (@ 0x4000EFE4) EEPROM interrupt enable */ __O uint32_t INTSTATCLR; /*!< (@ 0x4000EFE8) EEPROM interrupt status clear */ } LPC_EEPROM_Type; /* ================================================================================ */ /* ================ ETHERNET ================ */ /* ================================================================================ */ /** * @brief Ethernet (ETHERNET) */ typedef struct { /*!< (@ 0x40010000) ETHERNET Structure */ __IO uint32_t MAC_CONFIG; /*!< (@ 0x40010000) MAC configuration register */ __IO uint32_t MAC_FRAME_FILTER; /*!< (@ 0x40010004) MAC frame filter */ __IO uint32_t MAC_HASHTABLE_HIGH; /*!< (@ 0x40010008) Hash table high register */ __IO uint32_t MAC_HASHTABLE_LOW; /*!< (@ 0x4001000C) Hash table low register */ __IO uint32_t MAC_MII_ADDR; /*!< (@ 0x40010010) MII address register */ __IO uint32_t MAC_MII_DATA; /*!< (@ 0x40010014) MII data register */ __IO uint32_t MAC_FLOW_CTRL; /*!< (@ 0x40010018) Flow control register */ __IO uint32_t MAC_VLAN_TAG; /*!< (@ 0x4001001C) VLAN tag register */ __I uint32_t RESERVED0; __I uint32_t MAC_DEBUG; /*!< (@ 0x40010024) Debug register */ __IO uint32_t MAC_RWAKE_FRFLT; /*!< (@ 0x40010028) Remote wake-up frame filter */ __IO uint32_t MAC_PMT_CTRL_STAT; /*!< (@ 0x4001002C) PMT control and status */ __I uint32_t RESERVED1[2]; __I uint32_t MAC_INTR; /*!< (@ 0x40010038) Interrupt status register */ __IO uint32_t MAC_INTR_MASK; /*!< (@ 0x4001003C) Interrupt mask register */ __IO uint32_t MAC_ADDR0_HIGH; /*!< (@ 0x40010040) MAC address 0 high register */ __IO uint32_t MAC_ADDR0_LOW; /*!< (@ 0x40010044) MAC address 0 low register */ __I uint32_t RESERVED2[430]; __IO uint32_t MAC_TIMESTP_CTRL; /*!< (@ 0x40010700) Time stamp control register */ __IO uint32_t SUBSECOND_INCR; /*!< (@ 0x40010704) Sub-second increment register */ __I uint32_t SECONDS; /*!< (@ 0x40010708) System time seconds register */ __I uint32_t NANOSECONDS; /*!< (@ 0x4001070C) System time nanoseconds register */ __IO uint32_t SECONDSUPDATE; /*!< (@ 0x40010710) System time seconds update register */ __IO uint32_t NANOSECONDSUPDATE; /*!< (@ 0x40010714) System time nanoseconds update register */ __IO uint32_t ADDEND; /*!< (@ 0x40010718) Time stamp addend register */ __IO uint32_t TARGETSECONDS; /*!< (@ 0x4001071C) Target time seconds register */ __IO uint32_t TARGETNANOSECONDS; /*!< (@ 0x40010720) Target time nanoseconds register */ __IO uint32_t HIGHWORD; /*!< (@ 0x40010724) System time higher word seconds register */ __I uint32_t TIMESTAMPSTAT; /*!< (@ 0x40010728) Time stamp status register */ __I uint32_t RESERVED3[565]; __IO uint32_t DMA_BUS_MODE; /*!< (@ 0x40011000) Bus Mode Register */ __IO uint32_t DMA_TRANS_POLL_DEMAND; /*!< (@ 0x40011004) Transmit poll demand register */ __IO uint32_t DMA_REC_POLL_DEMAND; /*!< (@ 0x40011008) Receive poll demand register */ __IO uint32_t DMA_REC_DES_ADDR; /*!< (@ 0x4001100C) Receive descriptor list address register */ __IO uint32_t DMA_TRANS_DES_ADDR; /*!< (@ 0x40011010) Transmit descriptor list address register */ __IO uint32_t DMA_STAT; /*!< (@ 0x40011014) Status register */ __IO uint32_t DMA_OP_MODE; /*!< (@ 0x40011018) Operation mode register */ __IO uint32_t DMA_INT_EN; /*!< (@ 0x4001101C) Interrupt enable register */ __I uint32_t DMA_MFRM_BUFOF; /*!< (@ 0x40011020) Missed frame and buffer overflow register */ __IO uint32_t DMA_REC_INT_WDT; /*!< (@ 0x40011024) Receive interrupt watchdog timer register */ __I uint32_t RESERVED4[8]; __I uint32_t DMA_CURHOST_TRANS_DES; /*!< (@ 0x40011048) Current host transmit descriptor register */ __I uint32_t DMA_CURHOST_REC_DES; /*!< (@ 0x4001104C) Current host receive descriptor register */ __I uint32_t DMA_CURHOST_TRANS_BUF; /*!< (@ 0x40011050) Current host transmit buffer address register */ __I uint32_t DMA_CURHOST_REC_BUF; /*!< (@ 0x40011054) Current host receive buffer address register */ } LPC_ETHERNET_Type; /* ================================================================================ */ /* ================ ATIMER ================ */ /* ================================================================================ */ /** * @brief Alarm timer (ATIMER) */ typedef struct { /*!< (@ 0x40040000) ATIMER Structure */ __IO uint32_t DOWNCOUNTER; /*!< (@ 0x40040000) Downcounter register */ __IO uint32_t PRESET; /*!< (@ 0x40040004) Preset value register */ __I uint32_t RESERVED0[1012]; __O uint32_t CLR_EN; /*!< (@ 0x40040FD8) Interrupt clear enable register */ __O uint32_t SET_EN; /*!< (@ 0x40040FDC) Interrupt set enable register */ __I uint32_t STATUS; /*!< (@ 0x40040FE0) Status register */ __I uint32_t ENABLE; /*!< (@ 0x40040FE4) Enable register */ __O uint32_t CLR_STAT; /*!< (@ 0x40040FE8) Clear register */ __O uint32_t SET_STAT; /*!< (@ 0x40040FEC) Set register */ } LPC_ATIMER_Type; /* ================================================================================ */ /* ================ REGFILE ================ */ /* ================================================================================ */ /** * @brief RTC REGFILE (REGFILE) */ typedef struct { /*!< (@ 0x40041000) REGFILE Structure */ __IO uint32_t REGFILE[64]; /*!< (@ 0x40041000) General purpose storage register */ } LPC_REGFILE_Type; /* ================================================================================ */ /* ================ PMC ================ */ /* ================================================================================ */ /** * @brief Power Management Controller (PMC) (PMC) */ typedef struct { /*!< (@ 0x40042000) PMC Structure */ __IO uint32_t PD0_SLEEP0_HW_ENA; /*!< (@ 0x40042000) Hardware sleep event enable register */ __I uint32_t RESERVED0[6]; __IO uint32_t PD0_SLEEP0_MODE; /*!< (@ 0x4004201C) Sleep power mode register */ } LPC_PMC_Type; /* ================================================================================ */ /* ================ CREG ================ */ /* ================================================================================ */ /** * @brief Configuration Registers (CREG) (CREG) */ typedef struct { /*!< (@ 0x40043000) CREG Structure */ __I uint32_t RESERVED0; __IO uint32_t CREG0; /*!< (@ 0x40043004) Chip configuration register 32 kHz oscillator output and BOD control register. */ __I uint32_t RESERVED1[62]; __IO uint32_t M4MEMMAP; /*!< (@ 0x40043100) ARM Cortex-M4 memory mapping */ __I uint32_t RESERVED2[5]; __IO uint32_t CREG5; /*!< (@ 0x40043118) Chip configuration register 5. Controls JTAG access. */ __IO uint32_t DMAMUX; /*!< (@ 0x4004311C) DMA mux control */ __IO uint32_t FLASHCFGA; /*!< (@ 0x40043120) Flash accelerator configuration register for flash bank A */ __IO uint32_t FLASHCFGB; /*!< (@ 0x40043124) Flash accelerator configuration register for flash bank B */ __IO uint32_t ETBCFG; /*!< (@ 0x40043128) ETB RAM configuration */ __IO uint32_t CREG6; /*!< (@ 0x4004312C) Chip configuration register 6. Controls multiple functions : Ethernet interface, SCT output, I2S0/1 inputs, EMC clock. */ __IO uint32_t M4TXEVENT; /*!< (@ 0x40043130) Cortex-M4 TXEV event clear */ __I uint32_t RESERVED3[51]; __I uint32_t CHIPID; /*!< (@ 0x40043200) Part ID */ __I uint32_t RESERVED4[65]; __IO uint32_t M0SUBMEMMAP; /*!< (@ 0x40043308) ARM Cortex-M0SUB memory mapping */ __I uint32_t RESERVED5[2]; __IO uint32_t M0SUBTXEVENT; /*!< (@ 0x40043314) Cortex-M0SUB TXEV event clear */ __I uint32_t RESERVED6[58]; __IO uint32_t M0APPTXEVENT; /*!< (@ 0x40043400) Cortex-M0APP TXEV event clear */ __IO uint32_t M0APPMEMMAP; /*!< (@ 0x40043404) ARM Cortex-M0APP memory mapping */ __I uint32_t RESERVED7[62]; __IO uint32_t USB0FLADJ; /*!< (@ 0x40043500) USB0 frame length adjust register */ __I uint32_t RESERVED8[63]; __IO uint32_t USB1FLADJ; /*!< (@ 0x40043600) USB1 frame length adjust register */ } LPC_CREG_Type; /* ================================================================================ */ /* ================ EVENTROUTER ================ */ /* ================================================================================ */ /** * @brief Event router (EVENTROUTER) */ typedef struct { /*!< (@ 0x40044000) EVENTROUTER Structure */ __IO uint32_t HILO; /*!< (@ 0x40044000) Level configuration register */ __IO uint32_t EDGE; /*!< (@ 0x40044004) Edge configuration */ __I uint32_t RESERVED0[1012]; __O uint32_t CLR_EN; /*!< (@ 0x40044FD8) Clear event enable register */ __O uint32_t SET_EN; /*!< (@ 0x40044FDC) Set event enable register */ __I uint32_t STATUS; /*!< (@ 0x40044FE0) Event Status register */ __I uint32_t ENABLE; /*!< (@ 0x40044FE4) Event Enable register */ __O uint32_t CLR_STAT; /*!< (@ 0x40044FE8) Clear event status register */ __O uint32_t SET_STAT; /*!< (@ 0x40044FEC) Set event status register */ } LPC_EVENTROUTER_Type; /* ================================================================================ */ /* ================ RTC ================ */ /* ================================================================================ */ /** * @brief Real-Time Clock (RTC) and event recorder (RTC) */ typedef struct { /*!< (@ 0x40046000) RTC Structure */ __O uint32_t ILR; /*!< (@ 0x40046000) Interrupt Location Register */ __I uint32_t RESERVED0; __IO uint32_t CCR; /*!< (@ 0x40046008) Clock Control Register */ __IO uint32_t CIIR; /*!< (@ 0x4004600C) Counter Increment Interrupt Register */ __IO uint32_t AMR; /*!< (@ 0x40046010) Alarm Mask Register */ __I uint32_t CTIME0; /*!< (@ 0x40046014) Consolidated Time Register 0 */ __I uint32_t CTIME1; /*!< (@ 0x40046018) Consolidated Time Register 1 */ __I uint32_t CTIME2; /*!< (@ 0x4004601C) Consolidated Time Register 2 */ __IO uint32_t SEC; /*!< (@ 0x40046020) Seconds Register */ __IO uint32_t MIN; /*!< (@ 0x40046024) Minutes Register */ __IO uint32_t HRS; /*!< (@ 0x40046028) Hours Register */ __IO uint32_t DOM; /*!< (@ 0x4004602C) Day of Month Register */ __IO uint32_t DOW; /*!< (@ 0x40046030) Day of Week Register */ __IO uint32_t DOY; /*!< (@ 0x40046034) Day of Year Register */ __IO uint32_t MONTH; /*!< (@ 0x40046038) Months Register */ __IO uint32_t YEAR; /*!< (@ 0x4004603C) Years Register */ __IO uint32_t CALIBRATION; /*!< (@ 0x40046040) Calibration Value Register */ __I uint32_t RESERVED1[7]; __IO uint32_t ASEC; /*!< (@ 0x40046060) Alarm value for Seconds */ __IO uint32_t AMIN; /*!< (@ 0x40046064) Alarm value for Minutes */ __IO uint32_t AHRS; /*!< (@ 0x40046068) Alarm value for Hours */ __IO uint32_t ADOM; /*!< (@ 0x4004606C) Alarm value for Day of Month */ __IO uint32_t ADOW; /*!< (@ 0x40046070) Alarm value for Day of Week */ __IO uint32_t ADOY; /*!< (@ 0x40046074) Alarm value for Day of Year */ __IO uint32_t AMON; /*!< (@ 0x40046078) Alarm value for Months */ __IO uint32_t AYRS; /*!< (@ 0x4004607C) Alarm value for Year */ __IO uint32_t ERSTATUS; /*!< (@ 0x40046080) Event Monitor/Recorder Status register. Contains status flags for event channels and other Event Monitor/Recorder conditions. */ __IO uint32_t ERCONTRO; /*!< (@ 0x40046084) Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup. */ __I uint32_t ERCOUNTERS; /*!< (@ 0x40046088) Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels. */ __I uint32_t RESERVED2; __I uint32_t ERFIRSTSTAMP0; /*!< (@ 0x40046090) Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0. */ __I uint32_t ERFIRSTSTAMP1; /*!< (@ 0x40046094) Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0. */ __I uint32_t ERFIRSTSTAMP2; /*!< (@ 0x40046098) Event Monitor/Recorder First Stamp register for channel 0. Retains the time stamp for the first event on channel 0. */ __I uint32_t RESERVED3; __I uint32_t ERLASTSTAMP0; /*!< (@ 0x400460A0) Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0. */ __I uint32_t ERLASTSTAMP1; /*!< (@ 0x400460A4) Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0. */ __I uint32_t ERLASTSTAMP2; /*!< (@ 0x400460A8) Event Monitor/Recorder Last Stamp register for channel 0. Retains the time stamp for the last (i.e. most recent) event on channel 0. */ } LPC_RTC_Type; /* ================================================================================ */ /* ================ CGU ================ */ /* ================================================================================ */ /** * @brief Clock Generation Unit (CGU) (CGU) */ typedef struct { /*!< (@ 0x40050000) CGU Structure */ __I uint32_t RESERVED0[5]; __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */ __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */ __I uint32_t PLL0USB_STAT; /*!< (@ 0x4005001C) PLL0USB status register */ __IO uint32_t PLL0USB_CTRL; /*!< (@ 0x40050020) PLL0USB control register */ __IO uint32_t PLL0USB_MDIV; /*!< (@ 0x40050024) PLL0USB M-divider register */ __IO uint32_t PLL0USB_NP_DIV; /*!< (@ 0x40050028) PLL0USB N/P-divider register */ __I uint32_t PLL0AUDIO_STAT; /*!< (@ 0x4005002C) PLL0AUDIO status register */ __IO uint32_t PLL0AUDIO_CTRL; /*!< (@ 0x40050030) PLL0AUDIO control register */ __IO uint32_t PLL0AUDIO_MDIV; /*!< (@ 0x40050034) PLL0AUDIO M-divider register */ __IO uint32_t PLL0AUDIO_NP_DIV; /*!< (@ 0x40050038) PLL0AUDIO N/P-divider register */ __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0AUDIO fractional divider register */ __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */ __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */ __IO uint32_t IDIVA_CTRL; /*!< (@ 0x40050048) Integer divider A control register */ __IO uint32_t IDIVB_CTRL; /*!< (@ 0x4005004C) Integer divider B control register */ __IO uint32_t IDIVC_CTRL; /*!< (@ 0x40050050) Integer divider C control register */ __IO uint32_t IDIVD_CTRL; /*!< (@ 0x40050054) Integer divider D control register */ __IO uint32_t IDIVE_CTRL; /*!< (@ 0x40050058) Integer divider E control register */ __I uint32_t BASE_SAFE_CLK; /*!< (@ 0x4005005C) Output stage 0 control register for base clock BASE_SAFE_CLK */ __IO uint32_t BASE_USB0_CLK; /*!< (@ 0x40050060) Output stage 1 control register for base clock BASE_USB0_CLK */ __IO uint32_t BASE_PERIPH_CLK; /*!< (@ 0x40050064) Output stage 2 control register for base clock BASE_PERIPH_CLK */ __IO uint32_t BASE_USB1_CLK; /*!< (@ 0x40050068) Output stage 3 control register for base clock BASE_USB1_CLK */ __IO uint32_t BASE_M4_CLK; /*!< (@ 0x4005006C) Output stage BASE_M4_CLK control register */ __IO uint32_t BASE_SPIFI_CLK; /*!< (@ 0x40050070) Output stage BASE_SPIFI_CLK control register */ __IO uint32_t BASE_SPI_CLK; /*!< (@ 0x40050074) Output stage BASE_SPI_CLK control register */ __IO uint32_t BASE_PHY_RX_CLK; /*!< (@ 0x40050078) Output stage BASE_PHY_RX_CLK control register */ __IO uint32_t BASE_PHY_TX_CLK; /*!< (@ 0x4005007C) Output stage BASE_PHY_TX_CLK control register */ __IO uint32_t BASE_APB1_CLK; /*!< (@ 0x40050080) Output stage BASE_APB1_CLK control register */ __IO uint32_t BASE_APB3_CLK; /*!< (@ 0x40050084) Output stage BASE_APB3_CLK control register */ __IO uint32_t BASE_LCD_CLK; /*!< (@ 0x40050088) Output stage BASE_LCD_CLK control register */ __I uint32_t RESERVED1; __IO uint32_t BASE_SDIO_CLK; /*!< (@ 0x40050090) Output stage BASE_SDIO_CLK control register */ __IO uint32_t BASE_SSP0_CLK; /*!< (@ 0x40050094) Output stage BASE_SSP0_CLK control register */ __IO uint32_t BASE_SSP1_CLK; /*!< (@ 0x40050098) Output stage BASE_SSP1_CLK control register */ __IO uint32_t BASE_UART0_CLK; /*!< (@ 0x4005009C) Output stage BASE_UART0_CLK control register */ __IO uint32_t BASE_UART1_CLK; /*!< (@ 0x400500A0) Output stage BASE_UART1_CLK control register */ __IO uint32_t BASE_UART2_CLK; /*!< (@ 0x400500A4) Output stage BASE_UART2_CLK control register */ __IO uint32_t BASE_UART3_CLK; /*!< (@ 0x400500A8) Output stage BASE_UART3_CLK control register */ __IO uint32_t BASE_OUT_CLK; /*!< (@ 0x400500AC) Output stage 20 control register for base clock BASE_OUT_CLK */ __I uint32_t RESERVED2[4]; __IO uint32_t BASE_APLL_CLK; /*!< (@ 0x400500C0) Output stage 25 control register for base clock BASE_APLL_CLK */ __IO uint32_t BASE_CGU_OUT0_CLK; /*!< (@ 0x400500C4) Output stage 25 control register for base clock BASE_CGU_OUT0_CLK */ __IO uint32_t BASE_CGU_OUT1_CLK; /*!< (@ 0x400500C8) Output stage 25 control register for base clock BASE_CGU_OUT1_CLK */ } LPC_CGU_Type; /* ================================================================================ */ /* ================ CCU1 ================ */ /* ================================================================================ */ /** * @brief Clock Control Unit (CCU) (CCU1) */ typedef struct { /*!< (@ 0x40051000) CCU1 Structure */ __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */ __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */ __I uint32_t RESERVED0[62]; __IO uint32_t CLK_APB3_BUS_CFG; /*!< (@ 0x40051100) CLK_APB3_BUS clock configuration register */ __I uint32_t CLK_APB3_BUS_STAT; /*!< (@ 0x40051104) CLK_APB3_BUS clock status register */ __IO uint32_t CLK_APB3_I2C1_CFG; /*!< (@ 0x40051108) CLK_APB3_I2C1 clock configuration register */ __I uint32_t CLK_APB3_I2C1_STAT; /*!< (@ 0x4005110C) CLK_APB3_I2C1 clock status register */ __IO uint32_t CLK_APB3_DAC_CFG; /*!< (@ 0x40051110) CLK_APB3_DAC clock configuration register */ __I uint32_t CLK_APB3_DAC_STAT; /*!< (@ 0x40051114) CLK_APB3_DAC clock status register */ __IO uint32_t CLK_APB3_ADC0_CFG; /*!< (@ 0x40051118) CLK_APB3_ADC0 clock configuration register */ __I uint32_t CLK_APB3_ADC0_STAT; /*!< (@ 0x4005111C) CLK_APB3_ADC0 clock status register */ __IO uint32_t CLK_APB3_ADC1_CFG; /*!< (@ 0x40051120) CLK_APB3_ADC1 clock configuration register */ __I uint32_t CLK_APB3_ADC1_STAT; /*!< (@ 0x40051124) CLK_APB3_ADC1 clock status register */ __IO uint32_t CLK_APB3_CAN0_CFG; /*!< (@ 0x40051128) CLK_APB3_CAN0 clock configuration register */ __I uint32_t CLK_APB3_CAN0_STAT; /*!< (@ 0x4005112C) CLK_APB3_CAN0 clock status register */ __I uint32_t RESERVED1[52]; __IO uint32_t CLK_APB1_BUS_CFG; /*!< (@ 0x40051200) CLK_APB1_BUS clock configuration register */ __I uint32_t CLK_APB1_BUS_STAT; /*!< (@ 0x40051204) CLK_APB1_BUS clock status register */ __IO uint32_t CLK_APB1_MOTOCONPWM_CFG; /*!< (@ 0x40051208) CLK_APB1_MOTOCONPWM clock configuration register */ __I uint32_t CLK_APB1_MOTOCONPWM_STAT; /*!< (@ 0x4005120C) CLK_APB1_MOTOCONPWM clock status register */ __IO uint32_t CLK_APB1_I2C0_CFG; /*!< (@ 0x40051210) CLK_ABP1_I2C0 clock configuration register */ __I uint32_t CLK_APB1_I2C0_STAT; /*!< (@ 0x40051214) CLK_APB1_I2C0 clock status register */ __IO uint32_t CLK_APB1_I2S_CFG; /*!< (@ 0x40051218) CLK_APB1_I2S clock configuration register */ __I uint32_t CLK_APB1_I2S_STAT; /*!< (@ 0x4005121C) CLK_APB1_I2S clock status register */ __IO uint32_t CLK_APB1_CAN1_CFG; /*!< (@ 0x40051220) CLK_APB1_CAN1 clock configuration register */ __I uint32_t CLK_APB1_CAN1_STAT; /*!< (@ 0x40051224) CLK_APB1_CAN1 clock status register */ __I uint32_t RESERVED2[54]; __IO uint32_t CLK_SPIFI_CFG; /*!< (@ 0x40051300) CLK_SPIFI clock configuration register */ __I uint32_t CLK_SPIFI_STAT; /*!< (@ 0x40051304) CLK_APB1_SPIFI clock status register */ __I uint32_t RESERVED3[62]; __IO uint32_t CLK_M4_BUS_CFG; /*!< (@ 0x40051400) CLK_M4_BUS clock configuration register */ __I uint32_t CLK_M4_BUS_STAT; /*!< (@ 0x40051404) CLK_M4_BUSclock status register */ __IO uint32_t CLK_M4_SPIFI_CFG; /*!< (@ 0x40051408) CLK_M4_SPIFI clock configuration register */ __I uint32_t CLK_M4_SPIFI_STAT; /*!< (@ 0x4005140C) CLK_M4_SPIFI clock status register */ __IO uint32_t CLK_M4_GPIO_CFG; /*!< (@ 0x40051410) CLK_M4_GPIO clock configuration register */ __I uint32_t CLK_M4_GPIO_STAT; /*!< (@ 0x40051414) CLK_M4_GPIO clock status register */ __IO uint32_t CLK_M4_LCD_CFG; /*!< (@ 0x40051418) CLK_M4_LCD clock configuration register */ __I uint32_t CLK_M4_LCD_STAT; /*!< (@ 0x4005141C) CLK_M4_LCD clock status register */ __IO uint32_t CLK_M4_ETHERNET_CFG; /*!< (@ 0x40051420) CLK_M4_ETHERNET clock configuration register */ __I uint32_t CLK_M4_ETHERNET_STAT; /*!< (@ 0x40051424) CLK_M4_ETHERNET clock status register */ __IO uint32_t CLK_M4_USB0_CFG; /*!< (@ 0x40051428) CLK_M4_USB0 clock configuration register */ __I uint32_t CLK_M4_USB0_STAT; /*!< (@ 0x4005142C) CLK_M4_USB0 clock status register */ __IO uint32_t CLK_M4_EMC_CFG; /*!< (@ 0x40051430) CLK_M4_EMC clock configuration register */ __I uint32_t CLK_M4_EMC_STAT; /*!< (@ 0x40051434) CLK_M4_EMC clock status register */ __IO uint32_t CLK_M4_SDIO_CFG; /*!< (@ 0x40051438) CLK_M4_SDIO clock configuration register */ __I uint32_t CLK_M4_SDIO_STAT; /*!< (@ 0x4005143C) CLK_M4_SDIO clock status register */ __IO uint32_t CLK_M4_DMA_CFG; /*!< (@ 0x40051440) CLK_M4_DMA clock configuration register */ __I uint32_t CLK_M4_DMA_STAT; /*!< (@ 0x40051444) CLK_M4_DMA clock status register */ __IO uint32_t CLK_M4_M4CORE_CFG; /*!< (@ 0x40051448) CLK_M4_M4CORE clock configuration register */ __I uint32_t CLK_M4_M4CORE_STAT; /*!< (@ 0x4005144C) CLK_M4_M3CORE clock status register */ __I uint32_t RESERVED4[6]; __IO uint32_t CLK_M4_SCT_CFG; /*!< (@ 0x40051468) CLK_M4_SCT clock configuration register */ __I uint32_t CLK_M4_SCT_STAT; /*!< (@ 0x4005146C) CLK_M4_SCT clock status register */ __IO uint32_t CLK_M4_USB1_CFG; /*!< (@ 0x40051470) CLK_M4_USB1 clock configuration register */ __I uint32_t CLK_M4_USB1_STAT; /*!< (@ 0x40051474) CLK_M4_USB1 clock status register */ __IO uint32_t CLK_M4_EMCDIV_CFG; /*!< (@ 0x40051478) CLK_M4_EMCDIV clock configuration register */ __I uint32_t CLK_M4_EMCDIV_STAT; /*!< (@ 0x4005147C) CLK_M4_EMCDIV clock status register */ __IO uint32_t CLK_M4_FLASHA_CFG; /*!< (@ 0x40051480) CLK_M4_FLASHA clock configuration register */ __I uint32_t CLK_M4_FLASHA_STAT; /*!< (@ 0x40051484) CLK_M4_FLASHA clock status register */ __IO uint32_t CLK_M4_FLASHB_CFG; /*!< (@ 0x40051488) CLK_M4_FLASHB clock configuration register */ __I uint32_t CLK_M4_FLASHB_STAT; /*!< (@ 0x4005148C) CLK_M4_FLASHB clock status register */ __IO uint32_t CLK_M4_M0APP_CFG; /*!< (@ 0x40051490) CLK_M0APP_CFG clock configuration register */ __I uint32_t CLK_M4_M0APP_STAT; /*!< (@ 0x40051494) CLK_M4_MOAPP clock status register */ __IO uint32_t CLK_M4_ADCHS_CFG; /*!< (@ 0x40051498) CLK_ADCHS_CFG clock configuration register */ __I uint32_t CLK_M4_ADCHS_STAT; /*!< (@ 0x4005149C) CLK_M4_ADCHS clock status register */ __IO uint32_t CLK_M4_EEPROM_CFG; /*!< (@ 0x400514A0) CLK_EEPROM_CFG clock configuration register */ __I uint32_t CLK_M4_EEPROM_STAT; /*!< (@ 0x400514A4) CLK_M4_EEPROM clock status register */ __I uint32_t RESERVED5[22]; __IO uint32_t CLK_M4_WWDT_CFG; /*!< (@ 0x40051500) CLK_M4_WWDT clock configuration register */ __I uint32_t CLK_M4_WWDT_STAT; /*!< (@ 0x40051504) CLK_M4_WWDT clock status register */ __IO uint32_t CLK_M4_USART0_CFG; /*!< (@ 0x40051508) CLK_M4_USART0 clock configuration register */ __I uint32_t CLK_M4_USART0_STAT; /*!< (@ 0x4005150C) CLK_M4_USART0 clock status register */ __IO uint32_t CLK_M4_UART1_CFG; /*!< (@ 0x40051510) CLK_M4_UART1 clock configuration register */ __I uint32_t CLK_M4_UART1_STAT; /*!< (@ 0x40051514) CLK_M4_UART1 clock status register */ __IO uint32_t CLK_M4_SSP0_CFG; /*!< (@ 0x40051518) CLK_M4_SSP0 clock configuration register */ __I uint32_t CLK_M4_SSP0_STAT; /*!< (@ 0x4005151C) CLK_M4_SSP0 clock status register */ __IO uint32_t CLK_M4_TIMER0_CFG; /*!< (@ 0x40051520) CLK_M4_TIMER0 clock configuration register */ __I uint32_t CLK_M4_TIMER0_STAT; /*!< (@ 0x40051524) CLK_M4_TIMER0 clock status register */ __IO uint32_t CLK_M4_TIMER1_CFG; /*!< (@ 0x40051528) CLK_M4_TIMER1clock configuration register */ __I uint32_t CLK_M4_TIMER1_STAT; /*!< (@ 0x4005152C) CLK_M4_TIMER1 clock status register */ __IO uint32_t CLK_M4_SCU_CFG; /*!< (@ 0x40051530) CLK_M4_SCU clock configuration register */ __I uint32_t CLK_M4_SCU_STAT; /*!< (@ 0x40051534) CLK_SCU_XXX clock status register */ __IO uint32_t CLK_M4_CREG_CFG; /*!< (@ 0x40051538) CLK_M4_CREGclock configuration register */ __I uint32_t CLK_M4_CREG_STAT; /*!< (@ 0x4005153C) CLK_M4_CREG clock status register */ __I uint32_t RESERVED6[48]; __IO uint32_t CLK_M4_RITIMER_CFG; /*!< (@ 0x40051600) CLK_M4_RITIMER clock configuration register */ __I uint32_t CLK_M4_RITIMER_STAT; /*!< (@ 0x40051604) CLK_M4_RITIMER clock status register */ __IO uint32_t CLK_M4_USART2_CFG; /*!< (@ 0x40051608) CLK_M4_USART2 clock configuration register */ __I uint32_t CLK_M4_USART2_STAT; /*!< (@ 0x4005160C) CLK_M4_USART2 clock status register */ __IO uint32_t CLK_M4_USART3_CFG; /*!< (@ 0x40051610) CLK_M4_USART3 clock configuration register */ __I uint32_t CLK_M4_USART3_STAT; /*!< (@ 0x40051614) CLK_M4_USART3 clock status register */ __IO uint32_t CLK_M4_TIMER2_CFG; /*!< (@ 0x40051618) CLK_M4_TIMER2 clock configuration register */ __I uint32_t CLK_M4_TIMER2_STAT; /*!< (@ 0x4005161C) CLK_M4_TIMER2 clock status register */ __IO uint32_t CLK_M4_TIMER3_CFG; /*!< (@ 0x40051620) CLK_M4_TIMER3 clock configuration register */ __I uint32_t CLK_M4_TIMER3_STAT; /*!< (@ 0x40051624) CLK_M4_TIMER3 clock status register */ __IO uint32_t CLK_M4_SSP1_CFG; /*!< (@ 0x40051628) CLK_M4_SSP1 clock configuration register */ __I uint32_t CLK_M4_SSP1_STAT; /*!< (@ 0x4005162C) CLK_M4_SSP1 clock status register */ __IO uint32_t CLK_M4_QEI_CFG; /*!< (@ 0x40051630) CLK_M4_QEIclock configuration register */ __I uint32_t CLK_M4_QEI_STAT; /*!< (@ 0x40051634) CLK_M4_QEI clock status register */ __I uint32_t RESERVED7[50]; __IO uint32_t CLK_PERIPH_BUS_CFG; /*!< (@ 0x40051700) CLK_PERIPH_BUS_CFG clock configuration register */ __I uint32_t CLK_PERIPH_BUS_STAT; /*!< (@ 0x40051704) CLK_PERIPH_BUS_STAT clock status register */ __I uint32_t RESERVED8[2]; __IO uint32_t CLK_PERIPH_CORE_CFG; /*!< (@ 0x40051710) CLK_PERIPH_CORE_CFG clock configuration register */ __I uint32_t CLK_PERIPH_CORE_STAT; /*!< (@ 0x40051714) CLK_CORE_BUS_STAT clock status register */ __IO uint32_t CLK_PERIPH_SGPIO_CFG; /*!< (@ 0x40051718) CLK_PERIPH_SGPIO_CFG clock configuration register */ __I uint32_t CLK_PERIPH_SGPIO_STAT; /*!< (@ 0x4005171C) CLK_CORE_SGPIO_STAT clock status register */ __I uint32_t RESERVED9[56]; __IO uint32_t CLK_USB0_CFG; /*!< (@ 0x40051800) CLK_M4_USB0 clock configuration register */ __I uint32_t CLK_USB0_STAT; /*!< (@ 0x40051804) CLK_USB0 clock status register */ __I uint32_t RESERVED10[62]; __IO uint32_t CLK_USB1_CFG; /*!< (@ 0x40051900) CLK_USB1 clock configuration register */ __I uint32_t CLK_USB1_STAT; /*!< (@ 0x40051904) CLK_USB1 clock status register */ __I uint32_t RESERVED11[62]; __IO uint32_t CLK_SPI_CFG; /*!< (@ 0x40051A00) CLK_SPI clock configuration register */ __I uint32_t CLK_SPI_STAT; /*!< (@ 0x40051A04) CLK_SPI clock status register */ __I uint32_t RESERVED12[62]; __IO uint32_t CLK_ADCHS_CFG; /*!< (@ 0x40051B00) CLK_ADCHS clock configuration register */ __I uint32_t CLK_ADCHS_STAT; /*!< (@ 0x40051B04) CLK_ADCHS clock status register */ } LPC_CCU1_Type; /* ================================================================================ */ /* ================ CCU2 ================ */ /* ================================================================================ */ /** * @brief Clock Control Unit (CCU2) (CCU2) */ typedef struct { /*!< (@ 0x40052000) CCU2 Structure */ __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */ __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */ __I uint32_t RESERVED0[62]; __IO uint32_t CLK_AUDIO_CFG; /*!< (@ 0x40052100) CLK_AUDIO clock configuration register */ __I uint32_t CLK_AUDIO_STAT; /*!< (@ 0x40052104) CLK_AUDIO clock status register */ __I uint32_t RESERVED1[62]; __IO uint32_t CLK_APB2_USART3_CFG; /*!< (@ 0x40052200) CLK_APB2_USART3 clock configuration register */ __I uint32_t CLK_APB2_USART3_STAT; /*!< (@ 0x40052204) CLK_APB2_USART3 clock status register */ __I uint32_t RESERVED2[62]; __IO uint32_t CLK_APB2_USART2_CFG; /*!< (@ 0x40052300) CLK_APB2_USART2 clock configuration register */ __I uint32_t CLK_APB2_USART2_STAT; /*!< (@ 0x40052304) CLK_APB2_USART clock status register */ __I uint32_t RESERVED3[62]; __IO uint32_t CLK_APB0_UART1_BUS_CFG; /*!< (@ 0x40052400) CLK_APB2_UART1 clock configuration register */ __I uint32_t CLK_APB0_UART1_STAT; /*!< (@ 0x40052404) CLK_APB0_UART1 clock status register */ __I uint32_t RESERVED4[62]; __IO uint32_t CLK_APB0_USART0_CFG; /*!< (@ 0x40052500) CLK_APB2_USART0 clock configuration register */ __I uint32_t CLK_APB0_USART0_STAT; /*!< (@ 0x40052504) CLK_APB0_USART0 clock status register */ __I uint32_t RESERVED5[62]; __IO uint32_t CLK_APB2_SSP1_CFG; /*!< (@ 0x40052600) CLK_APB2_SSP1 clock configuration register */ __I uint32_t CLK_APB2_SSP1_STAT; /*!< (@ 0x40052604) CLK_APB2_SSP1 clock status register */ __I uint32_t RESERVED6[62]; __IO uint32_t CLK_APB0_SSP0_CFG; /*!< (@ 0x40052700) CLK_APB0_SSP0 clock configuration register */ __I uint32_t CLK_APB0_SSP0_STAT; /*!< (@ 0x40052704) CLK_APB0_SSP0 clock status register */ __I uint32_t RESERVED7[62]; __IO uint32_t CLK_SDIO_CFG; /*!< (@ 0x40052800) CLK_SDIO clock configuration register */ __I uint32_t CLK_SDIO_STAT; /*!< (@ 0x40052804) CLK_SDIO clock status register */ } LPC_CCU2_Type; /* ================================================================================ */ /* ================ RGU ================ */ /* ================================================================================ */ /** * @brief Reset Generation Unit (RGU) (RGU) */ typedef struct { /*!< (@ 0x40053000) RGU Structure */ __I uint32_t RESERVED0[64]; __O uint32_t RESET_CTRL0; /*!< (@ 0x40053100) Reset control register 0 */ __O uint32_t RESET_CTRL1; /*!< (@ 0x40053104) Reset control register 1 */ __I uint32_t RESERVED1[2]; __IO uint32_t RESET_STATUS0; /*!< (@ 0x40053110) Reset status register 0 */ __IO uint32_t RESET_STATUS1; /*!< (@ 0x40053114) Reset status register 1 */ __IO uint32_t RESET_STATUS2; /*!< (@ 0x40053118) Reset status register 2 */ __IO uint32_t RESET_STATUS3; /*!< (@ 0x4005311C) Reset status register 3 */ __I uint32_t RESERVED2[12]; __I uint32_t RESET_ACTIVE_STATUS0; /*!< (@ 0x40053150) Reset active status register 0 */ __I uint32_t RESET_ACTIVE_STATUS1; /*!< (@ 0x40053154) Reset active status register 1 */ __I uint32_t RESERVED3[171]; __IO uint32_t RESET_EXT_STAT1; /*!< (@ 0x40053404) Reset external status register 1 for PERIPH_RST */ __IO uint32_t RESET_EXT_STAT2; /*!< (@ 0x40053408) Reset external status register 2 for MASTER_RST */ __I uint32_t RESERVED4[2]; __IO uint32_t RESET_EXT_STAT5; /*!< (@ 0x40053414) Reset external status register 5 for CREG_RST */ __I uint32_t RESERVED5[2]; __IO uint32_t RESET_EXT_STAT8; /*!< (@ 0x40053420) Reset external status register */ __IO uint32_t RESET_EXT_STAT9; /*!< (@ 0x40053424) Reset external status register */ __I uint32_t RESERVED6[2]; __IO uint32_t RESET_EXT_STAT12; /*!< (@ 0x40053430) Reset external status register */ __IO uint32_t RESET_EXT_STAT13; /*!< (@ 0x40053434) Reset external status register */ __I uint32_t RESERVED7[2]; __IO uint32_t RESET_EXT_STAT16; /*!< (@ 0x40053440) Reset external status register */ __IO uint32_t RESET_EXT_STAT17; /*!< (@ 0x40053444) Reset external status register */ __IO uint32_t RESET_EXT_STAT18; /*!< (@ 0x40053448) Reset external status register */ __IO uint32_t RESET_EXT_STAT19; /*!< (@ 0x4005344C) Reset external status register */ __IO uint32_t RESET_EXT_STAT20; /*!< (@ 0x40053450) Reset external status register */ __IO uint32_t RESET_EXT_STAT21; /*!< (@ 0x40053454) Reset external status register */ __IO uint32_t RESET_EXT_STAT22; /*!< (@ 0x40053458) Reset external status register */ __I uint32_t RESERVED8[2]; __IO uint32_t RESET_EXT_STAT25; /*!< (@ 0x40053464) Reset external status register */ __I uint32_t RESERVED9; __IO uint32_t RESET_EXT_STAT27; /*!< (@ 0x4005346C) Reset external status register */ __IO uint32_t RESET_EXT_STAT28; /*!< (@ 0x40053470) Reset external status register */ __IO uint32_t RESET_EXT_STAT29; /*!< (@ 0x40053474) Reset external status register */ __I uint32_t RESERVED10[2]; __IO uint32_t RESET_EXT_STAT32; /*!< (@ 0x40053480) Reset external status register */ __IO uint32_t RESET_EXT_STAT33; /*!< (@ 0x40053484) Reset external status register */ __IO uint32_t RESET_EXT_STAT34; /*!< (@ 0x40053488) Reset external status register */ __IO uint32_t RESET_EXT_STAT35; /*!< (@ 0x4005348C) Reset external status register */ __IO uint32_t RESET_EXT_STAT36; /*!< (@ 0x40053490) Reset external status register */ __IO uint32_t RESET_EXT_STAT37; /*!< (@ 0x40053494) Reset external status register */ __IO uint32_t RESET_EXT_STAT38; /*!< (@ 0x40053498) Reset external status register */ __IO uint32_t RESET_EXT_STAT39; /*!< (@ 0x4005349C) Reset external status register */ __IO uint32_t RESET_EXT_STAT40; /*!< (@ 0x400534A0) Reset external status register */ __IO uint32_t RESET_EXT_STAT41; /*!< (@ 0x400534A4) Reset external status register */ __IO uint32_t RESET_EXT_STAT42; /*!< (@ 0x400534A8) Reset external status register */ __I uint32_t RESERVED11; __IO uint32_t RESET_EXT_STAT44; /*!< (@ 0x400534B0) Reset external status register */ __IO uint32_t RESET_EXT_STAT45; /*!< (@ 0x400534B4) Reset external status register */ __IO uint32_t RESET_EXT_STAT46; /*!< (@ 0x400534B8) Reset external status register */ __IO uint32_t RESET_EXT_STAT47; /*!< (@ 0x400534BC) Reset external status register */ __IO uint32_t RESET_EXT_STAT48; /*!< (@ 0x400534C0) Reset external status register */ __IO uint32_t RESET_EXT_STAT49; /*!< (@ 0x400534C4) Reset external status register */ __IO uint32_t RESET_EXT_STAT50; /*!< (@ 0x400534C8) Reset external status register */ __IO uint32_t RESET_EXT_STAT51; /*!< (@ 0x400534CC) Reset external status register */ __IO uint32_t RESET_EXT_STAT52; /*!< (@ 0x400534D0) Reset external status register */ __IO uint32_t RESET_EXT_STAT53; /*!< (@ 0x400534D4) Reset external status register */ __IO uint32_t RESET_EXT_STAT54; /*!< (@ 0x400534D8) Reset external status register */ __IO uint32_t RESET_EXT_STAT55; /*!< (@ 0x400534DC) Reset external status register */ __IO uint32_t RESET_EXT_STAT56; /*!< (@ 0x400534E0) Reset external status register */ __IO uint32_t RESET_EXT_STAT57; /*!< (@ 0x400534E4) Reset external status register */ __IO uint32_t RESET_EXT_STAT58; /*!< (@ 0x400534E8) Reset external status register */ __I uint32_t RESERVED12; __IO uint32_t RESET_EXT_STAT60; /*!< (@ 0x400534F0) Reset external status register */ } LPC_RGU_Type; /* ================================================================================ */ /* ================ WWDT ================ */ /* ================================================================================ */ /** * @brief Windowed Watchdog timer (WWDT) (WWDT) */ typedef struct { /*!< (@ 0x40080000) WWDT Structure */ __IO uint32_t MOD; /*!< (@ 0x40080000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ __IO uint32_t TC; /*!< (@ 0x40080004) Watchdog timer constant register. This register determines the time-out value. */ __O uint32_t FEED; /*!< (@ 0x40080008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */ __I uint32_t TV; /*!< (@ 0x4008000C) Watchdog timer value register. This register reads out the current value of the Watchdog timer. */ __I uint32_t RESERVED0; __IO uint32_t WARNINT; /*!< (@ 0x40080014) Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */ __IO uint32_t WINDOW; /*!< (@ 0x40080018) Watchdog timer window register. This register contains the Watchdog window value. */ } LPC_WWDT_Type; /* ================================================================================ */ /* ================ USARTn [USART0] ================ */ /* ================================================================================ */ /** * @brief USART0_2_3 (USARTn) */ typedef struct { /*!< (@ 0x40081000) USARTn Structure */ union { __IO uint32_t DLL; /*!< (@ 0x40081000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ __O uint32_t THR; /*!< (@ 0x40081000) Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */ __I uint32_t RBR; /*!< (@ 0x40081000) Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */ }; union { __IO uint32_t IER; /*!< (@ 0x40081004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0). */ __IO uint32_t DLM; /*!< (@ 0x40081004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */ }; union { __O uint32_t FCR; /*!< (@ 0x40081008) FIFO Control Register. Controls USART FIFO usage and modes. */ __I uint32_t IIR; /*!< (@ 0x40081008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ }; __IO uint32_t LCR; /*!< (@ 0x4008100C) Line Control Register. Contains controls for frame formatting and break generation. */ __I uint32_t RESERVED0; __I uint32_t LSR; /*!< (@ 0x40081014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ __I uint32_t RESERVED1; __IO uint32_t SCR; /*!< (@ 0x4008101C) Scratch Pad Register. Eight-bit temporary storage for software. */ __IO uint32_t ACR; /*!< (@ 0x40081020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ __IO uint32_t ICR; /*!< (@ 0x40081024) IrDA control register (USART3 only) */ __IO uint32_t FDR; /*!< (@ 0x40081028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ __IO uint32_t OSR; /*!< (@ 0x4008102C) Oversampling Register. Controls the degree of oversampling during each bit time. */ __I uint32_t RESERVED2[4]; __IO uint32_t HDEN; /*!< (@ 0x40081040) Half-duplex enable Register */ __I uint32_t RESERVED3; __IO uint32_t SCICTRL; /*!< (@ 0x40081048) Smart card interface control register */ __IO uint32_t RS485CTRL; /*!< (@ 0x4008104C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40081050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ __IO uint32_t RS485DLY; /*!< (@ 0x40081054) RS-485/EIA-485 direction control delay. */ __IO uint32_t SYNCCTRL; /*!< (@ 0x40081058) Synchronous mode control register. */ __IO uint32_t TER; /*!< (@ 0x4008105C) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ } LPC_USARTn_Type; /* ================================================================================ */ /* ================ UART1 ================ */ /* ================================================================================ */ /** * @brief UART1 (UART1) */ typedef struct { /*!< (@ 0x40082000) UART1 Structure */ union { __IO uint32_t DLL; /*!< (@ 0x40082000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ __O uint32_t THR; /*!< (@ 0x40082000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ __I uint32_t RBR; /*!< (@ 0x40082000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ }; union { __IO uint32_t IER; /*!< (@ 0x40082004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts. (DLAB=0) */ __IO uint32_t DLM; /*!< (@ 0x40082004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.(DLAB=1) */ }; union { __O uint32_t FCR; /*!< (@ 0x40082008) FIFO Control Register. Controls UART1 FIFO usage and modes. */ __I uint32_t IIR; /*!< (@ 0x40082008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ }; __IO uint32_t LCR; /*!< (@ 0x4008200C) Line Control Register. Contains controls for frame formatting and break generation. */ __IO uint32_t MCR; /*!< (@ 0x40082010) Modem Control Register. Contains controls for flow control handshaking and loopback mode. */ __I uint32_t LSR; /*!< (@ 0x40082014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ __I uint32_t MSR; /*!< (@ 0x40082018) Modem Status Register. Contains handshake signal status flags. */ __IO uint32_t SCR; /*!< (@ 0x4008201C) Scratch Pad Register. 8-bit temporary storage for software. */ __IO uint32_t ACR; /*!< (@ 0x40082020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ __I uint32_t RESERVED0; __IO uint32_t FDR; /*!< (@ 0x40082028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ __I uint32_t RESERVED1[8]; __IO uint32_t RS485CTRL; /*!< (@ 0x4008204C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40082050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ __IO uint32_t RS485DLY; /*!< (@ 0x40082054) RS-485/EIA-485 direction control delay. */ __I uint32_t RESERVED2; __IO uint32_t TER; /*!< (@ 0x4008205C) Transmit Enable Register. Turns off UART transmitter for use with software flow control. */ } LPC_UART1_Type; /* ================================================================================ */ /* ================ SSPn [SSP0] ================ */ /* ================================================================================ */ /** * @brief SSP0/1 (SSPn) */ typedef struct { /*!< (@ 0x40083000) SSPn Structure */ __IO uint32_t CR0; /*!< (@ 0x40083000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ __IO uint32_t CR1; /*!< (@ 0x40083004) Control Register 1. Selects master/slave and other modes. */ __IO uint32_t DR; /*!< (@ 0x40083008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ __I uint32_t SR; /*!< (@ 0x4008300C) Status Register */ __IO uint32_t CPSR; /*!< (@ 0x40083010) Clock Prescale Register */ __IO uint32_t IMSC; /*!< (@ 0x40083014) Interrupt Mask Set and Clear Register */ __I uint32_t RIS; /*!< (@ 0x40083018) Raw Interrupt Status Register */ __I uint32_t MIS; /*!< (@ 0x4008301C) Masked Interrupt Status Register */ __O uint32_t ICR; /*!< (@ 0x40083020) SSPICR Interrupt Clear Register */ __IO uint32_t DMACR; /*!< (@ 0x40083024) SSP0 DMA control register */ } LPC_SSPn_Type; /* ================================================================================ */ /* ================ TIMERn [TIMER0] ================ */ /* ================================================================================ */ /** * @brief Timer0/1/2/3 (TIMERn) */ typedef struct { /*!< (@ 0x40084000) TIMERn Structure */ __IO uint32_t IR; /*!< (@ 0x40084000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ __IO uint32_t TCR; /*!< (@ 0x40084004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ __IO uint32_t TC; /*!< (@ 0x40084008) Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */ __IO uint32_t PR; /*!< (@ 0x4008400C) Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ __IO uint32_t PC; /*!< (@ 0x40084010) Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ __IO uint32_t MCR; /*!< (@ 0x40084014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ __IO uint32_t MR0; /*!< (@ 0x40084018) Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. */ __IO uint32_t MR1; /*!< (@ 0x4008401C) Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. */ __IO uint32_t MR2; /*!< (@ 0x40084020) Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. */ __IO uint32_t MR3; /*!< (@ 0x40084024) Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. */ __IO uint32_t CCR; /*!< (@ 0x40084028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ __I uint32_t CR0; /*!< (@ 0x4008402C) Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. */ __I uint32_t CR1; /*!< (@ 0x40084030) Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. */ __I uint32_t CR2; /*!< (@ 0x40084034) Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. */ __I uint32_t CR3; /*!< (@ 0x40084038) Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input. */ __IO uint32_t EMR; /*!< (@ 0x4008403C) External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */ __I uint32_t RESERVED0[12]; __IO uint32_t CTCR; /*!< (@ 0x40084070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ } LPC_TIMERn_Type; /* ================================================================================ */ /* ================ SCU ================ */ /* ================================================================================ */ /** * @brief System Control Unit (SCU) I/O configuration (SCU) */ typedef struct { /*!< (@ 0x40086000) SCU Structure */ __IO uint32_t SFSP0_0; /*!< (@ 0x40086000) Pin configuration register for pins P0 */ __IO uint32_t SFSP0_1; /*!< (@ 0x40086004) Pin configuration register for pins P0 */ __I uint32_t RESERVED0[30]; __IO uint32_t SFSP1_0; /*!< (@ 0x40086080) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_1; /*!< (@ 0x40086084) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_2; /*!< (@ 0x40086088) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_3; /*!< (@ 0x4008608C) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_4; /*!< (@ 0x40086090) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_5; /*!< (@ 0x40086094) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_6; /*!< (@ 0x40086098) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_7; /*!< (@ 0x4008609C) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_8; /*!< (@ 0x400860A0) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_9; /*!< (@ 0x400860A4) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_10; /*!< (@ 0x400860A8) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_11; /*!< (@ 0x400860AC) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_12; /*!< (@ 0x400860B0) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_13; /*!< (@ 0x400860B4) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_14; /*!< (@ 0x400860B8) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_15; /*!< (@ 0x400860BC) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_16; /*!< (@ 0x400860C0) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_17; /*!< (@ 0x400860C4) Pin configuration register for pins P1_17 */ __IO uint32_t SFSP1_18; /*!< (@ 0x400860C8) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_19; /*!< (@ 0x400860CC) Pin configuration register for pins P1 */ __IO uint32_t SFSP1_20; /*!< (@ 0x400860D0) Pin configuration register for pins P1 */ __I uint32_t RESERVED1[11]; __IO uint32_t SFSP2_0; /*!< (@ 0x40086100) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_1; /*!< (@ 0x40086104) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_2; /*!< (@ 0x40086108) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_3; /*!< (@ 0x4008610C) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_4; /*!< (@ 0x40086110) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_5; /*!< (@ 0x40086114) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_6; /*!< (@ 0x40086118) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_7; /*!< (@ 0x4008611C) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_8; /*!< (@ 0x40086120) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_9; /*!< (@ 0x40086124) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_10; /*!< (@ 0x40086128) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_11; /*!< (@ 0x4008612C) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_12; /*!< (@ 0x40086130) Pin configuration register for pins P2 */ __IO uint32_t SFSP2_13; /*!< (@ 0x40086134) Pin configuration register for pins P2 */ __I uint32_t RESERVED2[18]; __IO uint32_t SFSP3_0; /*!< (@ 0x40086180) Pin configuration register for pins P3 */ __IO uint32_t SFSP3_1; /*!< (@ 0x40086184) Pin configuration register for pins P3 */ __IO uint32_t SFSP3_2; /*!< (@ 0x40086188) Pin configuration register for pins P3 */ __IO uint32_t SFSP3_3; /*!< (@ 0x4008618C) Pin configuration register for pins P3 */ __IO uint32_t SFSP3_4; /*!< (@ 0x40086190) Pin configuration register for pins P3 */ __IO uint32_t SFSP3_5; /*!< (@ 0x40086194) Pin configuration register for pins P3 */ __IO uint32_t SFSP3_6; /*!< (@ 0x40086198) Pin configuration register for pins P3 */ __IO uint32_t SFSP3_7; /*!< (@ 0x4008619C) Pin configuration register for pins P3 */ __IO uint32_t SFSP3_8; /*!< (@ 0x400861A0) Pin configuration register for pins P3 */ __I uint32_t RESERVED3[23]; __IO uint32_t SFSP4_0; /*!< (@ 0x40086200) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_1; /*!< (@ 0x40086204) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_2; /*!< (@ 0x40086208) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_3; /*!< (@ 0x4008620C) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_4; /*!< (@ 0x40086210) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_5; /*!< (@ 0x40086214) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_6; /*!< (@ 0x40086218) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_7; /*!< (@ 0x4008621C) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_8; /*!< (@ 0x40086220) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_9; /*!< (@ 0x40086224) Pin configuration register for pins P4 */ __IO uint32_t SFSP4_10; /*!< (@ 0x40086228) Pin configuration register for pins P4 */ __I uint32_t RESERVED4[21]; __IO uint32_t SFSP5_0; /*!< (@ 0x40086280) Pin configuration register for pins P5 */ __IO uint32_t SFSP5_1; /*!< (@ 0x40086284) Pin configuration register for pins P5 */ __IO uint32_t SFSP5_2; /*!< (@ 0x40086288) Pin configuration register for pins P5 */ __IO uint32_t SFSP5_3; /*!< (@ 0x4008628C) Pin configuration register for pins P5 */ __IO uint32_t SFSP5_4; /*!< (@ 0x40086290) Pin configuration register for pins P5 */ __IO uint32_t SFSP5_5; /*!< (@ 0x40086294) Pin configuration register for pins P5 */ __IO uint32_t SFSP5_6; /*!< (@ 0x40086298) Pin configuration register for pins P5 */ __IO uint32_t SFSP5_7; /*!< (@ 0x4008629C) Pin configuration register for pins P5 */ __I uint32_t RESERVED5[24]; __IO uint32_t SFSP6_0; /*!< (@ 0x40086300) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_1; /*!< (@ 0x40086304) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_2; /*!< (@ 0x40086308) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_3; /*!< (@ 0x4008630C) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_4; /*!< (@ 0x40086310) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_5; /*!< (@ 0x40086314) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_6; /*!< (@ 0x40086318) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_7; /*!< (@ 0x4008631C) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_8; /*!< (@ 0x40086320) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_9; /*!< (@ 0x40086324) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_10; /*!< (@ 0x40086328) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_11; /*!< (@ 0x4008632C) Pin configuration register for pins P6 */ __IO uint32_t SFSP6_12; /*!< (@ 0x40086330) Pin configuration register for pins P6 */ __I uint32_t RESERVED6[19]; __IO uint32_t SFSP7_0; /*!< (@ 0x40086380) Pin configuration register for pins P7 */ __IO uint32_t SFSP7_1; /*!< (@ 0x40086384) Pin configuration register for pins P7 */ __IO uint32_t SFSP7_2; /*!< (@ 0x40086388) Pin configuration register for pins P7 */ __IO uint32_t SFSP7_3; /*!< (@ 0x4008638C) Pin configuration register for pins P7 */ __IO uint32_t SFSP7_4; /*!< (@ 0x40086390) Pin configuration register for pins P7 */ __IO uint32_t SFSP7_5; /*!< (@ 0x40086394) Pin configuration register for pins P7 */ __IO uint32_t SFSP7_6; /*!< (@ 0x40086398) Pin configuration register for pins P7 */ __IO uint32_t SFSP7_7; /*!< (@ 0x4008639C) Pin configuration register for pins P7 */ __I uint32_t RESERVED7[24]; __IO uint32_t SFSP8_0; /*!< (@ 0x40086400) Pin configuration register for pins P8 */ __IO uint32_t SFSP8_1; /*!< (@ 0x40086404) Pin configuration register for pins P8 */ __IO uint32_t SFSP8_2; /*!< (@ 0x40086408) Pin configuration register for pins P8 */ __IO uint32_t SFSP8_3; /*!< (@ 0x4008640C) Pin configuration register for pins P8 */ __IO uint32_t SFSP8_4; /*!< (@ 0x40086410) Pin configuration register for pins P8 */ __IO uint32_t SFSP8_5; /*!< (@ 0x40086414) Pin configuration register for pins P8 */ __IO uint32_t SFSP8_6; /*!< (@ 0x40086418) Pin configuration register for pins P8 */ __IO uint32_t SFSP8_7; /*!< (@ 0x4008641C) Pin configuration register for pins P8 */ __IO uint32_t SFSP8_8; /*!< (@ 0x40086420) Pin configuration register for pins P8 */ __I uint32_t RESERVED8[23]; __IO uint32_t SFSP9_0; /*!< (@ 0x40086480) Pin configuration register for pins P9 */ __IO uint32_t SFSP9_1; /*!< (@ 0x40086484) Pin configuration register for pins P9 */ __IO uint32_t SFSP9_2; /*!< (@ 0x40086488) Pin configuration register for pins P9 */ __IO uint32_t SFSP9_3; /*!< (@ 0x4008648C) Pin configuration register for pins P9 */ __IO uint32_t SFSP9_4; /*!< (@ 0x40086490) Pin configuration register for pins P9 */ __IO uint32_t SFSP9_5; /*!< (@ 0x40086494) Pin configuration register for pins P9 */ __IO uint32_t SFSP9_6; /*!< (@ 0x40086498) Pin configuration register for pins P9 */ __I uint32_t RESERVED9[25]; __IO uint32_t SFSPA_0; /*!< (@ 0x40086500) Pin configuration register for pins PA */ __IO uint32_t SFSPA_1; /*!< (@ 0x40086504) Pin configuration register for pins PA */ __IO uint32_t SFSPA_2; /*!< (@ 0x40086508) Pin configuration register for pins PA */ __IO uint32_t SFSPA_3; /*!< (@ 0x4008650C) Pin configuration register for pins PA */ __IO uint32_t SFSPA_4; /*!< (@ 0x40086510) Pin configuration register for pins PA */ __I uint32_t RESERVED10[27]; __IO uint32_t SFSPB_0; /*!< (@ 0x40086580) Pin configuration register for pins PB */ __IO uint32_t SFSPB_1; /*!< (@ 0x40086584) Pin configuration register for pins PB */ __IO uint32_t SFSPB_2; /*!< (@ 0x40086588) Pin configuration register for pins PB */ __IO uint32_t SFSPB_3; /*!< (@ 0x4008658C) Pin configuration register for pins PB */ __IO uint32_t SFSPB_4; /*!< (@ 0x40086590) Pin configuration register for pins PB */ __IO uint32_t SFSPB_5; /*!< (@ 0x40086594) Pin configuration register for pins PB */ __IO uint32_t SFSPB_6; /*!< (@ 0x40086598) Pin configuration register for pins PB */ __I uint32_t RESERVED11[25]; __IO uint32_t SFSPC_0; /*!< (@ 0x40086600) Pin configuration register for pins PC */ __IO uint32_t SFSPC_1; /*!< (@ 0x40086604) Pin configuration register for pins PC */ __IO uint32_t SFSPC_2; /*!< (@ 0x40086608) Pin configuration register for pins PC */ __IO uint32_t SFSPC_3; /*!< (@ 0x4008660C) Pin configuration register for pins PC */ __IO uint32_t SFSPC_4; /*!< (@ 0x40086610) Pin configuration register for pins PC */ __IO uint32_t SFSPC_5; /*!< (@ 0x40086614) Pin configuration register for pins PC */ __IO uint32_t SFSPC_6; /*!< (@ 0x40086618) Pin configuration register for pins PC */ __IO uint32_t SFSPC_7; /*!< (@ 0x4008661C) Pin configuration register for pins PC */ __IO uint32_t SFSPC_8; /*!< (@ 0x40086620) Pin configuration register for pins PC */ __IO uint32_t SFSPC_9; /*!< (@ 0x40086624) Pin configuration register for pins PC */ __IO uint32_t SFSPC_10; /*!< (@ 0x40086628) Pin configuration register for pins PC */ __IO uint32_t SFSPC_11; /*!< (@ 0x4008662C) Pin configuration register for pins PC */ __IO uint32_t SFSPC_12; /*!< (@ 0x40086630) Pin configuration register for pins PC */ __IO uint32_t SFSPC_13; /*!< (@ 0x40086634) Pin configuration register for pins PC */ __IO uint32_t SFSPC_14; /*!< (@ 0x40086638) Pin configuration register for pins PC */ __I uint32_t RESERVED12[17]; __IO uint32_t SFSPD_0; /*!< (@ 0x40086680) Pin configuration register for pins PD */ __IO uint32_t SFSPD_1; /*!< (@ 0x40086684) Pin configuration register for pins PD */ __IO uint32_t SFSPD_2; /*!< (@ 0x40086688) Pin configuration register for pins PD */ __IO uint32_t SFSPD_3; /*!< (@ 0x4008668C) Pin configuration register for pins PD */ __IO uint32_t SFSPD_4; /*!< (@ 0x40086690) Pin configuration register for pins PD */ __IO uint32_t SFSPD_5; /*!< (@ 0x40086694) Pin configuration register for pins PD */ __IO uint32_t SFSPD_6; /*!< (@ 0x40086698) Pin configuration register for pins PD */ __IO uint32_t SFSPD_7; /*!< (@ 0x4008669C) Pin configuration register for pins PD */ __IO uint32_t SFSPD_8; /*!< (@ 0x400866A0) Pin configuration register for pins PD */ __IO uint32_t SFSPD_9; /*!< (@ 0x400866A4) Pin configuration register for pins PD */ __IO uint32_t SFSPD_10; /*!< (@ 0x400866A8) Pin configuration register for pins PD */ __IO uint32_t SFSPD_11; /*!< (@ 0x400866AC) Pin configuration register for pins PD */ __IO uint32_t SFSPD_12; /*!< (@ 0x400866B0) Pin configuration register for pins PD */ __IO uint32_t SFSPD_13; /*!< (@ 0x400866B4) Pin configuration register for pins PD */ __IO uint32_t SFSPD_14; /*!< (@ 0x400866B8) Pin configuration register for pins PD */ __IO uint32_t SFSPD_15; /*!< (@ 0x400866BC) Pin configuration register for pins PD */ __IO uint32_t SFSPD_16; /*!< (@ 0x400866C0) Pin configuration register for pins PD */ __I uint32_t RESERVED13[15]; __IO uint32_t SFSPE_0; /*!< (@ 0x40086700) Pin configuration register for pins PE */ __IO uint32_t SFSPE_1; /*!< (@ 0x40086704) Pin configuration register for pins PE */ __IO uint32_t SFSPE_2; /*!< (@ 0x40086708) Pin configuration register for pins PE */ __IO uint32_t SFSPE_3; /*!< (@ 0x4008670C) Pin configuration register for pins PE */ __IO uint32_t SFSPE_4; /*!< (@ 0x40086710) Pin configuration register for pins PE */ __IO uint32_t SFSPE_5; /*!< (@ 0x40086714) Pin configuration register for pins PE */ __IO uint32_t SFSPE_6; /*!< (@ 0x40086718) Pin configuration register for pins PE */ __IO uint32_t SFSPE_7; /*!< (@ 0x4008671C) Pin configuration register for pins PE */ __IO uint32_t SFSPE_8; /*!< (@ 0x40086720) Pin configuration register for pins PE */ __IO uint32_t SFSPE_9; /*!< (@ 0x40086724) Pin configuration register for pins PE */ __IO uint32_t SFSPE_10; /*!< (@ 0x40086728) Pin configuration register for pins PE */ __IO uint32_t SFSPE_11; /*!< (@ 0x4008672C) Pin configuration register for pins PE */ __IO uint32_t SFSPE_12; /*!< (@ 0x40086730) Pin configuration register for pins PE */ __IO uint32_t SFSPE_13; /*!< (@ 0x40086734) Pin configuration register for pins PE */ __IO uint32_t SFSPE_14; /*!< (@ 0x40086738) Pin configuration register for pins PE */ __IO uint32_t SFSPE_15; /*!< (@ 0x4008673C) Pin configuration register for pins PE */ __I uint32_t RESERVED14[16]; __IO uint32_t SFSPF_0; /*!< (@ 0x40086780) Pin configuration register for pins PF */ __IO uint32_t SFSPF_1; /*!< (@ 0x40086784) Pin configuration register for pins PF */ __IO uint32_t SFSPF_2; /*!< (@ 0x40086788) Pin configuration register for pins PF */ __IO uint32_t SFSPF_3; /*!< (@ 0x4008678C) Pin configuration register for pins PF */ __IO uint32_t SFSPF_4; /*!< (@ 0x40086790) Pin configuration register for pins PF */ __IO uint32_t SFSPF_5; /*!< (@ 0x40086794) Pin configuration register for pins PF */ __IO uint32_t SFSPF_6; /*!< (@ 0x40086798) Pin configuration register for pins PF */ __IO uint32_t SFSPF_7; /*!< (@ 0x4008679C) Pin configuration register for pins PF */ __IO uint32_t SFSPF_8; /*!< (@ 0x400867A0) Pin configuration register for pins PF */ __IO uint32_t SFSPF_9; /*!< (@ 0x400867A4) Pin configuration register for pins PF */ __IO uint32_t SFSPF_10; /*!< (@ 0x400867A8) Pin configuration register for pins PF */ __IO uint32_t SFSPF_11; /*!< (@ 0x400867AC) Pin configuration register for pins PF */ __I uint32_t RESERVED15[276]; __IO uint32_t SFSCLK_0; /*!< (@ 0x40086C00) Pin configuration register for pins CLK */ __IO uint32_t SFSCLK_1; /*!< (@ 0x40086C04) Pin configuration register for pins CLK */ __IO uint32_t SFSCLK_2; /*!< (@ 0x40086C08) Pin configuration register for pins CLK */ __IO uint32_t SFSCLK_3; /*!< (@ 0x40086C0C) Pin configuration register for pins CLK */ __I uint32_t RESERVED16[28]; __IO uint32_t SFSUSB; /*!< (@ 0x40086C80) Pin configuration register for pins USB1_DM and USB1_DP */ __IO uint32_t SFSI2C0; /*!< (@ 0x40086C84) Pin configuration register for I2C0-bus pins */ __IO uint32_t ENAIO0; /*!< (@ 0x40086C88) ADC0 function select register */ __IO uint32_t ENAIO1; /*!< (@ 0x40086C8C) ADC1 function select register */ __IO uint32_t ENAIO2; /*!< (@ 0x40086C90) Analog function select register */ __I uint32_t RESERVED17[27]; __IO uint32_t EMCDELAYCLK; /*!< (@ 0x40086D00) EMC clock delay register */ __I uint32_t RESERVED18[31]; __IO uint32_t SDDELAY; /*!< (@ 0x40086D80) SD/MMC sample and drive delay register */ __I uint32_t RESERVED19[31]; __IO uint32_t PINTSEL0; /*!< (@ 0x40086E00) Pin interrupt select register for pin interrupts 0 to 3. */ __IO uint32_t PINTSEL1; /*!< (@ 0x40086E04) Pin interrupt select register for pin interrupts 4 to 7. */ } LPC_SCU_Type; /* ================================================================================ */ /* ================ GPIO_PIN_INT ================ */ /* ================================================================================ */ /** * @brief GPIO pin interrupt (GPIO_PIN_INT) */ typedef struct { /*!< (@ 0x40087000) GPIO_PIN_INT Structure */ __IO uint32_t ISEL; /*!< (@ 0x40087000) Pin Interrupt Mode register */ __IO uint32_t IENR; /*!< (@ 0x40087004) Pin Interrupt Enable (Rising) register */ __O uint32_t SIENR; /*!< (@ 0x40087008) Set Pin Interrupt Enable (Rising) register */ __O uint32_t CIENR; /*!< (@ 0x4008700C) Clear Pin Interrupt Enable (Rising) register */ __IO uint32_t IENF; /*!< (@ 0x40087010) Pin Interrupt Enable Falling Edge / Active Level register */ __O uint32_t SIENF; /*!< (@ 0x40087014) Set Pin Interrupt Enable Falling Edge / Active Level register */ __O uint32_t CIENF; /*!< (@ 0x40087018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ __IO uint32_t RISE; /*!< (@ 0x4008701C) Pin Interrupt Rising Edge register */ __IO uint32_t FALL; /*!< (@ 0x40087020) Pin Interrupt Falling Edge register */ __IO uint32_t IST; /*!< (@ 0x40087024) Pin Interrupt Status register */ } LPC_GPIO_PIN_INT_Type; /* ================================================================================ */ /* ================ GPIO_GROUP_INTn [GPIO_GROUP_INT0] ================ */ /* ================================================================================ */ /** * @brief GPIO group interrupt 0 (GPIO_GROUP_INTn) */ typedef struct { /*!< (@ 0x40088000) GPIO_GROUP_INTn Structure */ __IO uint32_t CTRL; /*!< (@ 0x40088000) GPIO grouped interrupt control register */ __I uint32_t RESERVED0[7]; __IO uint32_t PORT_POL0; /*!< (@ 0x40088020) GPIO grouped interrupt port polarity register */ __IO uint32_t PORT_POL1; /*!< (@ 0x40088024) GPIO grouped interrupt port polarity register */ __IO uint32_t PORT_POL2; /*!< (@ 0x40088028) GPIO grouped interrupt port polarity register */ __IO uint32_t PORT_POL3; /*!< (@ 0x4008802C) GPIO grouped interrupt port polarity register */ __IO uint32_t PORT_POL4; /*!< (@ 0x40088030) GPIO grouped interrupt port polarity register */ __IO uint32_t PORT_POL5; /*!< (@ 0x40088034) GPIO grouped interrupt port polarity register */ __IO uint32_t PORT_POL6; /*!< (@ 0x40088038) GPIO grouped interrupt port polarity register */ __IO uint32_t PORT_POL7; /*!< (@ 0x4008803C) GPIO grouped interrupt port polarity register */ __IO uint32_t PORT_ENA0; /*!< (@ 0x40088040) GPIO grouped interrupt port m enable register */ __IO uint32_t PORT_ENA1; /*!< (@ 0x40088044) GPIO grouped interrupt port m enable register */ __IO uint32_t PORT_ENA2; /*!< (@ 0x40088048) GPIO grouped interrupt port m enable register */ __IO uint32_t PORT_ENA3; /*!< (@ 0x4008804C) GPIO grouped interrupt port m enable register */ __IO uint32_t PORT_ENA4; /*!< (@ 0x40088050) GPIO grouped interrupt port m enable register */ __IO uint32_t PORT_ENA5; /*!< (@ 0x40088054) GPIO grouped interrupt port m enable register */ __IO uint32_t PORT_ENA6; /*!< (@ 0x40088058) GPIO grouped interrupt port m enable register */ __IO uint32_t PORT_ENA7; /*!< (@ 0x4008805C) GPIO grouped interrupt port m enable register */ } LPC_GPIO_GROUP_INTn_Type; /* ================================================================================ */ /* ================ MCPWM ================ */ /* ================================================================================ */ /** * @brief Motor Control PWM (MOTOCONPWM) (MCPWM) */ typedef struct { /*!< (@ 0x400A0000) MCPWM Structure */ __I uint32_t CON; /*!< (@ 0x400A0000) PWM Control read address */ __O uint32_t CON_SET; /*!< (@ 0x400A0004) PWM Control set address */ __O uint32_t CON_CLR; /*!< (@ 0x400A0008) PWM Control clear address */ __I uint32_t CAPCON; /*!< (@ 0x400A000C) Capture Control read address */ __O uint32_t CAPCON_SET; /*!< (@ 0x400A0010) Capture Control set address */ __O uint32_t CAPCON_CLR; /*!< (@ 0x400A0014) Event Control clear address */ __IO uint32_t TC0; /*!< (@ 0x400A0018) Timer Counter register */ __IO uint32_t TC1; /*!< (@ 0x400A001C) Timer Counter register */ __IO uint32_t TC2; /*!< (@ 0x400A0020) Timer Counter register */ __IO uint32_t LIM0; /*!< (@ 0x400A0024) Limit register */ __IO uint32_t LIM1; /*!< (@ 0x400A0028) Limit register */ __IO uint32_t LIM2; /*!< (@ 0x400A002C) Limit register */ __IO uint32_t MAT0; /*!< (@ 0x400A0030) Match register */ __IO uint32_t MAT1; /*!< (@ 0x400A0034) Match register */ __IO uint32_t MAT2; /*!< (@ 0x400A0038) Match register */ __IO uint32_t DT; /*!< (@ 0x400A003C) Dead time register */ __IO uint32_t CCP; /*!< (@ 0x400A0040) Communication Pattern register */ __I uint32_t CAP0; /*!< (@ 0x400A0044) Capture register */ __I uint32_t CAP1; /*!< (@ 0x400A0048) Capture register */ __I uint32_t CAP2; /*!< (@ 0x400A004C) Capture register */ __I uint32_t INTEN; /*!< (@ 0x400A0050) Interrupt Enable read address */ __O uint32_t INTEN_SET; /*!< (@ 0x400A0054) Interrupt Enable set address */ __O uint32_t INTEN_CLR; /*!< (@ 0x400A0058) Interrupt Enable clear address */ __I uint32_t CNTCON; /*!< (@ 0x400A005C) Count Control read address */ __O uint32_t CNTCON_SET; /*!< (@ 0x400A0060) Count Control set address */ __O uint32_t CNTCON_CLR; /*!< (@ 0x400A0064) Count Control clear address */ __I uint32_t INTF; /*!< (@ 0x400A0068) Interrupt flags read address */ __O uint32_t INTF_SET; /*!< (@ 0x400A006C) Interrupt flags set address */ __O uint32_t INTF_CLR; /*!< (@ 0x400A0070) Interrupt flags clear address */ __O uint32_t CAP_CLR; /*!< (@ 0x400A0074) Capture clear address */ } LPC_MCPWM_Type; /* ================================================================================ */ /* ================ I2Cn [I2C0] ================ */ /* ================================================================================ */ /** * @brief I2C-bus interface (I2Cn) */ typedef struct { /*!< (@ 0x400A1000) I2Cn Structure */ __IO uint32_t CONSET; /*!< (@ 0x400A1000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */ __I uint32_t STAT; /*!< (@ 0x400A1004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */ __IO uint32_t DAT; /*!< (@ 0x400A1008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */ __IO uint32_t ADR0; /*!< (@ 0x400A100C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ __IO uint32_t SCLH; /*!< (@ 0x400A1010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */ __IO uint32_t SCLL; /*!< (@ 0x400A1014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */ __O uint32_t CONCLR; /*!< (@ 0x400A1018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */ __IO uint32_t MMCTRL; /*!< (@ 0x400A101C) Monitor mode control register. */ __IO uint32_t ADR1; /*!< (@ 0x400A1020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ __IO uint32_t ADR2; /*!< (@ 0x400A1024) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ __IO uint32_t ADR3; /*!< (@ 0x400A1028) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */ __I uint32_t DATA_BUFFER; /*!< (@ 0x400A102C) Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */ __IO uint32_t MASK0; /*!< (@ 0x400A1030) I2C Slave address mask register */ __IO uint32_t MASK1; /*!< (@ 0x400A1034) I2C Slave address mask register */ __IO uint32_t MASK2; /*!< (@ 0x400A1038) I2C Slave address mask register */ __IO uint32_t MASK3; /*!< (@ 0x400A103C) I2C Slave address mask register */ } LPC_I2Cn_Type; /* ================================================================================ */ /* ================ I2Sn [I2S0] ================ */ /* ================================================================================ */ /** * @brief I2S interface (I2Sn) */ typedef struct { /*!< (@ 0x400A2000) I2Sn Structure */ __IO uint32_t DAO; /*!< (@ 0x400A2000) I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. */ __IO uint32_t DAI; /*!< (@ 0x400A2004) I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. */ __O uint32_t TXFIFO; /*!< (@ 0x400A2008) I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. */ __I uint32_t RXFIFO; /*!< (@ 0x400A200C) I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. */ __I uint32_t STATE; /*!< (@ 0x400A2010) I2S Status Feedback Register. Contains status information about the I2S interface. */ __IO uint32_t DMA1; /*!< (@ 0x400A2014) I2S DMA Configuration Register 1. Contains control information for DMA request 1. */ __IO uint32_t DMA2; /*!< (@ 0x400A2018) I2S DMA Configuration Register 2. Contains control information for DMA request 2. */ __IO uint32_t IRQ; /*!< (@ 0x400A201C) I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. */ __IO uint32_t TXRATE; /*!< (@ 0x400A2020) I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */ __IO uint32_t RXRATE; /*!< (@ 0x400A2024) I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. */ __IO uint32_t TXBITRATE; /*!< (@ 0x400A2028) I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. */ __IO uint32_t RXBITRATE; /*!< (@ 0x400A202C) I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. */ __IO uint32_t TXMODE; /*!< (@ 0x400A2030) I2S Transmit mode control. */ __IO uint32_t RXMODE; /*!< (@ 0x400A2034) I2S Receive mode control. */ } LPC_I2Sn_Type; /* ================================================================================ */ /* ================ C_CANn [C_CAN1] ================ */ /* ================================================================================ */ /** * @brief C_CAN (C_CANn) */ typedef struct { /*!< (@ 0x400A4000) C_CANn Structure */ __IO uint32_t CNTL; /*!< (@ 0x400A4000) CAN control */ __IO uint32_t STAT; /*!< (@ 0x400A4004) Status register */ __I uint32_t EC; /*!< (@ 0x400A4008) Error counter */ __IO uint32_t BT; /*!< (@ 0x400A400C) Bit timing register */ __I uint32_t INT; /*!< (@ 0x400A4010) Interrupt register */ __IO uint32_t TEST; /*!< (@ 0x400A4014) Test register */ __IO uint32_t BRPE; /*!< (@ 0x400A4018) Baud rate prescaler extension register */ __I uint32_t RESERVED0; __IO uint32_t IF1_CMDREQ; /*!< (@ 0x400A4020) Message interface command request */ union { __IO uint32_t IF1_CMDMSK_R; /*!< (@ 0x400A4024) Message interface command mask (read direction) */ __IO uint32_t IF1_CMDMSK_W; /*!< (@ 0x400A4024) Message interface command mask (write direction) */ }; __IO uint32_t IF1_MSK1; /*!< (@ 0x400A4028) Message interface mask 1 */ __IO uint32_t IF1_MSK2; /*!< (@ 0x400A402C) Message interface 1 mask 2 */ __IO uint32_t IF1_ARB1; /*!< (@ 0x400A4030) Message interface 1 arbitration 1 */ __IO uint32_t IF1_ARB2; /*!< (@ 0x400A4034) Message interface 1 arbitration 2 */ __IO uint32_t IF1_MCTRL; /*!< (@ 0x400A4038) Message interface 1 message control */ __IO uint32_t IF1_DA1; /*!< (@ 0x400A403C) Message interface data A1 */ __IO uint32_t IF1_DA2; /*!< (@ 0x400A4040) Message interface 1 data A2 */ __IO uint32_t IF1_DB1; /*!< (@ 0x400A4044) Message interface 1 data B1 */ __IO uint32_t IF1_DB2; /*!< (@ 0x400A4048) Message interface 1 data B2 */ __I uint32_t RESERVED1[13]; __IO uint32_t IF2_CMDREQ; /*!< (@ 0x400A4080) Message interface command request */ union { __IO uint32_t IF2_CMDMSK_R; /*!< (@ 0x400A4084) Message interface command mask (read direction) */ __IO uint32_t IF2_CMDMSK_W; /*!< (@ 0x400A4084) Message interface command mask (write direction) */ }; __IO uint32_t IF2_MSK1; /*!< (@ 0x400A4088) Message interface mask 1 */ __IO uint32_t IF2_MSK2; /*!< (@ 0x400A408C) Message interface 1 mask 2 */ __IO uint32_t IF2_ARB1; /*!< (@ 0x400A4090) Message interface 1 arbitration 1 */ __IO uint32_t IF2_ARB2; /*!< (@ 0x400A4094) Message interface 1 arbitration 2 */ __IO uint32_t IF2_MCTRL; /*!< (@ 0x400A4098) Message interface 1 message control */ __IO uint32_t IF2_DA1; /*!< (@ 0x400A409C) Message interface data A1 */ __IO uint32_t IF2_DA2; /*!< (@ 0x400A40A0) Message interface 1 data A2 */ __IO uint32_t IF2_DB1; /*!< (@ 0x400A40A4) Message interface 1 data B1 */ __IO uint32_t IF2_DB2; /*!< (@ 0x400A40A8) Message interface 1 data B2 */ __I uint32_t RESERVED2[21]; __I uint32_t TXREQ1; /*!< (@ 0x400A4100) Transmission request 1 */ __I uint32_t TXREQ2; /*!< (@ 0x400A4104) Transmission request 2 */ __I uint32_t RESERVED3[6]; __I uint32_t ND1; /*!< (@ 0x400A4120) New data 1 */ __I uint32_t ND2; /*!< (@ 0x400A4124) New data 2 */ __I uint32_t RESERVED4[6]; __I uint32_t IR1; /*!< (@ 0x400A4140) Interrupt pending 1 */ __I uint32_t IR2; /*!< (@ 0x400A4144) Interrupt pending 2 */ __I uint32_t RESERVED5[6]; __I uint32_t MSGV1; /*!< (@ 0x400A4160) Message valid 1 */ __I uint32_t MSGV2; /*!< (@ 0x400A4164) Message valid 2 */ __I uint32_t RESERVED6[6]; __IO uint32_t CLKDIV; /*!< (@ 0x400A4180) CAN clock divider register */ } LPC_C_CANn_Type; /* ================================================================================ */ /* ================ RITIMER ================ */ /* ================================================================================ */ /** * @brief Repetitive Interrupt Timer (RIT) (RITIMER) */ typedef struct { /*!< (@ 0x400C0000) RITIMER Structure */ __IO uint32_t COMPVAL; /*!< (@ 0x400C0000) Compare register */ __IO uint32_t MASK; /*!< (@ 0x400C0004) Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */ __IO uint32_t CTRL; /*!< (@ 0x400C0008) Control register. */ __IO uint32_t COUNTER; /*!< (@ 0x400C000C) 32-bit counter */ } LPC_RITIMER_Type; /* ================================================================================ */ /* ================ QEI ================ */ /* ================================================================================ */ /** * @brief Quadrature Encoder Interface (QEI) (QEI) */ typedef struct { /*!< (@ 0x400C6000) QEI Structure */ __O uint32_t CON; /*!< (@ 0x400C6000) Control register */ __I uint32_t STAT; /*!< (@ 0x400C6004) Encoder status register */ __IO uint32_t CONF; /*!< (@ 0x400C6008) Configuration register */ __I uint32_t POS; /*!< (@ 0x400C600C) Position register */ __IO uint32_t MAXPOS; /*!< (@ 0x400C6010) Maximum position register */ __IO uint32_t CMPOS0; /*!< (@ 0x400C6014) position compare register 0 */ __IO uint32_t CMPOS1; /*!< (@ 0x400C6018) position compare register 1 */ __IO uint32_t CMPOS2; /*!< (@ 0x400C601C) position compare register 2 */ __I uint32_t INXCNT; /*!< (@ 0x400C6020) Index count register */ __IO uint32_t INXCMP0; /*!< (@ 0x400C6024) Index compare register 0 */ __IO uint32_t LOAD; /*!< (@ 0x400C6028) Velocity timer reload register */ __I uint32_t TIME; /*!< (@ 0x400C602C) Velocity timer register */ __I uint32_t VEL; /*!< (@ 0x400C6030) Velocity counter register */ __I uint32_t CAP; /*!< (@ 0x400C6034) Velocity capture register */ __IO uint32_t VELCOMP; /*!< (@ 0x400C6038) Velocity compare register */ __IO uint32_t FILTERPHA; /*!< (@ 0x400C603C) Digital filter register on input phase A (QEI_A) */ __IO uint32_t FILTERPHB; /*!< (@ 0x400C6040) Digital filter register on input phase B (QEI_B) */ __IO uint32_t FILTERINX; /*!< (@ 0x400C6044) Digital filter register on input index (QEI_IDX) */ __IO uint32_t WINDOW; /*!< (@ 0x400C6048) Index acceptance window register */ __IO uint32_t INXCMP1; /*!< (@ 0x400C604C) Index compare register 1 */ __IO uint32_t INXCMP2; /*!< (@ 0x400C6050) Index compare register 2 */ __I uint32_t RESERVED0[993]; __O uint32_t IEC; /*!< (@ 0x400C6FD8) Interrupt enable clear register */ __O uint32_t IES; /*!< (@ 0x400C6FDC) Interrupt enable set register */ __I uint32_t INTSTAT; /*!< (@ 0x400C6FE0) Interrupt status register */ __I uint32_t IE; /*!< (@ 0x400C6FE4) Interrupt enable register */ __O uint32_t CLR; /*!< (@ 0x400C6FE8) Interrupt status clear register */ __O uint32_t SET; /*!< (@ 0x400C6FEC) Interrupt status set register */ } LPC_QEI_Type; /* ================================================================================ */ /* ================ GIMA ================ */ /* ================================================================================ */ /** * @brief Global Input Multiplexer Array (GIMA) (GIMA) */ typedef struct { /*!< (@ 0x400C7000) GIMA Structure */ __IO uint32_t CAP0_0_IN; /*!< (@ 0x400C7000) Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */ __IO uint32_t CAP0_1_IN; /*!< (@ 0x400C7004) Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */ __IO uint32_t CAP0_2_IN; /*!< (@ 0x400C7008) Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */ __IO uint32_t CAP0_3_IN; /*!< (@ 0x400C700C) Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */ __IO uint32_t CAP1_0_IN; /*!< (@ 0x400C7010) Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */ __IO uint32_t CAP1_1_IN; /*!< (@ 0x400C7014) Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */ __IO uint32_t CAP1_2_IN; /*!< (@ 0x400C7018) Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */ __IO uint32_t CAP1_3_IN; /*!< (@ 0x400C701C) Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */ __IO uint32_t CAP2_0_IN; /*!< (@ 0x400C7020) Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */ __IO uint32_t CAP2_1_IN; /*!< (@ 0x400C7024) Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */ __IO uint32_t CAP2_2_IN; /*!< (@ 0x400C7028) Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */ __IO uint32_t CAP2_3_IN; /*!< (@ 0x400C702C) Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */ __IO uint32_t CAP3_0_IN; /*!< (@ 0x400C7030) Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */ __IO uint32_t CAP3_1_IN; /*!< (@ 0x400C7034) Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */ __IO uint32_t CAP3_2_IN; /*!< (@ 0x400C7038) Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */ __IO uint32_t CAP3_3_IN; /*!< (@ 0x400C703C) Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */ __IO uint32_t CTIN_0_IN; /*!< (@ 0x400C7040) SCT CTIN_0 capture input multiplexer (GIMA output 16) */ __IO uint32_t CTIN_1_IN; /*!< (@ 0x400C7044) SCT CTIN_1 capture input multiplexer (GIMA output 17) */ __IO uint32_t CTIN_2_IN; /*!< (@ 0x400C7048) SCT CTIN_2 capture input multiplexer (GIMA output 18) */ __IO uint32_t CTIN_3_IN; /*!< (@ 0x400C704C) SCT CTIN_3 capture input multiplexer (GIMA output 19) */ __IO uint32_t CTIN_4_IN; /*!< (@ 0x400C7050) SCT CTIN_4 capture input multiplexer (GIMA output 20) */ __IO uint32_t CTIN_5_IN; /*!< (@ 0x400C7054) SCT CTIN_5 capture input multiplexer (GIMA output 21) */ __IO uint32_t CTIN_6_IN; /*!< (@ 0x400C7058) SCT CTIN_6 capture input multiplexer (GIMA output 22) */ __IO uint32_t CTIN_7_IN; /*!< (@ 0x400C705C) SCT CTIN_7 capture input multiplexer (GIMA output 23) */ __IO uint32_t ADCHS_TRIGGER_IN; /*!< (@ 0x400C7060) ADCHS trigger input multiplexer (GIMA output 24) */ __IO uint32_t EVENTROUTER_13_IN; /*!< (@ 0x400C7064) Event router input 13 multiplexer (GIMA output 25) */ __IO uint32_t EVENTROUTER_14_IN; /*!< (@ 0x400C7068) Event router input 14 multiplexer (GIMA output 26) */ __IO uint32_t EVENTROUTER_16_IN; /*!< (@ 0x400C706C) Event router input 16 multiplexer (GIMA output 27) */ __IO uint32_t ADCSTART0_IN; /*!< (@ 0x400C7070) ADC start0 input multiplexer (GIMA output 28) */ __IO uint32_t ADCSTART1_IN; /*!< (@ 0x400C7074) ADC start1 input multiplexer (GIMA output 29) */ } LPC_GIMA_Type; /* ================================================================================ */ /* ================ DAC ================ */ /* ================================================================================ */ /** * @brief Digital-to-Analog Converter (DAC) (DAC) */ typedef struct { /*!< (@ 0x400E1000) DAC Structure */ __IO uint32_t CR; /*!< (@ 0x400E1000) DAC register. Holds the conversion data. */ __IO uint32_t CTRL; /*!< (@ 0x400E1004) DAC control register. */ __IO uint32_t CNTVAL; /*!< (@ 0x400E1008) DAC counter value register. */ } LPC_DAC_Type; /* ================================================================================ */ /* ================ ADCn [ADC0] ================ */ /* ================================================================================ */ /** * @brief 10-bit Analog-to-Digital Converter (ADC) (ADCn) */ typedef struct { /*!< (@ 0x400E3000) ADCn Structure */ __IO uint32_t CR; /*!< (@ 0x400E3000) A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */ __I uint32_t GDR; /*!< (@ 0x400E3004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */ __I uint32_t RESERVED0; __IO uint32_t INTEN; /*!< (@ 0x400E300C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */ __I uint32_t DR[8]; /*!< (@ 0x400E3010) A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */ __I uint32_t STAT; /*!< (@ 0x400E3030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */ } LPC_ADCn_Type; /* ================================================================================ */ /* ================ ADCHS ================ */ /* ================================================================================ */ /** * @brief 12-bit Analog-to-Digital Converter High-Speed (ADCHS) (ADCHS) */ typedef struct { /*!< (@ 0x400F0000) ADCHS Structure */ __O uint32_t FLUSH; /*!< (@ 0x400F0000) Flushes FIFO */ __IO uint32_t DMA_REQ; /*!< (@ 0x400F0004) Set or clear DMA write request */ __I uint32_t FIFO_STS; /*!< (@ 0x400F0008) Indicates FIFO fill level status */ __IO uint32_t FIFO_CFG; /*!< (@ 0x400F000C) Configures FIFO fill level that triggers interrupt and packing 1 or 2 samples per word. */ __O uint32_t TRIGGER; /*!< (@ 0x400F0010) Enable software trigger to start descriptor processing */ __IO uint32_t DSCR_STS; /*!< (@ 0x400F0014) Indicates active descriptor table and descriptor entry */ __IO uint32_t POWER_DOWN; /*!< (@ 0x400F0018) Set or clear power down mode */ __IO uint32_t CONFIG; /*!< (@ 0x400F001C) Configures external trigger mode, store channel ID in FIFO and walk-up recovery time from power down. */ __IO uint32_t THR_A; /*!< (@ 0x400F0020) Configures window comparator A levels. */ __IO uint32_t THR_B; /*!< (@ 0x400F0024) Configures window comparator B levels. */ __I uint32_t LAST_SAMPLE[6]; /*!< (@ 0x400F0028) Contains last converted sample of input M [M=0..5) and result of window comparator. */ __I uint32_t RESERVED0[49]; __IO uint32_t ADC_SPEED; /*!< (@ 0x400F0104) ADC speed control */ __IO uint32_t POWER_CONTROL; /*!< (@ 0x400F0108) Configures ADC power vs. speed, DC-in biasing, output format and power gating. */ __I uint32_t RESERVED1[61]; __I uint32_t FIFO_OUTPUT[16]; /*!< (@ 0x400F0200) FIFO output mapped to 16 consecutive address locations. An output contains the value and input channel ID of one or two converted samples */ __I uint32_t RESERVED2[48]; __IO uint32_t DESCRIPTOR0_[8]; /*!< (@ 0x400F0300) Table 0 descriptor n, n= 0 to 7 */ __IO uint32_t DESCRIPTOR1_[8]; /*!< (@ 0x400F0320) Table 1 descriptors n, n=0 to 7 */ __I uint32_t RESERVED3[752]; __O uint32_t CLR_EN0; /*!< (@ 0x400F0F00) Interrupt 0 clear mask */ __O uint32_t SET_EN0; /*!< (@ 0x400F0F04) Interrupt 0 set mask */ __I uint32_t MASK0; /*!< (@ 0x400F0F08) Interrupt 0 mask */ __I uint32_t STATUS0; /*!< (@ 0x400F0F0C) Interrupt 0 status. Interrupt 0 contains FIFO fill level, descriptor status and ADC range under/overflow */ __O uint32_t CLR_STAT0; /*!< (@ 0x400F0F10) Interrupt 0 clear status */ __O uint32_t SET_STAT0; /*!< (@ 0x400F0F14) Interrupt 0 set status */ __I uint32_t RESERVED4[2]; __O uint32_t CLR_EN1; /*!< (@ 0x400F0F20) Interrupt 1 mask clear enable. */ __O uint32_t SET_EN1; /*!< (@ 0x400F0F24) Interrupt 1 mask set enable */ __I uint32_t MASK1; /*!< (@ 0x400F0F28) Interrupt 1 mask */ __I uint32_t STATUS1; /*!< (@ 0x400F0F2C) Interrupt 1 status. Interrupt 1 contains window comparator results and register last LAST_SAMPLE[M] overrun. */ __O uint32_t CLR_STAT1; /*!< (@ 0x400F0F30) Interrupt 1 clear status */ __O uint32_t SET_STAT1; /*!< (@ 0x400F0F34) Interrupt 1 set status */ } LPC_ADCHS_Type; /* ================================================================================ */ /* ================ GPIO_PORT ================ */ /* ================================================================================ */ /** * @brief GPIO port (GPIO_PORT) */ typedef struct { /*!< (@ 0x400F4000) GPIO_PORT Structure */ __IO uint8_t B[256]; /*!< (@ 0x400F4000) Byte pin registers port 0 to 5; pins PIOn_0 to PIOn_31 */ __I uint32_t RESERVED0[960]; __IO uint32_t W[256]; /*!< (@ 0x400F5000) Word pin registers port 0 to 5 */ __I uint32_t RESERVED1[768]; __IO uint32_t DIR[8]; /*!< (@ 0x400F6000) Direction registers port m */ __I uint32_t RESERVED2[24]; __IO uint32_t MASK[8]; /*!< (@ 0x400F6080) Mask register port m */ __I uint32_t RESERVED3[24]; __IO uint32_t PIN[8]; /*!< (@ 0x400F6100) Port pin register port m */ __I uint32_t RESERVED4[24]; __IO uint32_t MPIN[8]; /*!< (@ 0x400F6180) Masked port register port m */ __I uint32_t RESERVED5[24]; __IO uint32_t SET[8]; /*!< (@ 0x400F6200) Write: Set register for port m Read: output bits for port m */ __I uint32_t RESERVED6[24]; __O uint32_t CLR[8]; /*!< (@ 0x400F6280) Clear port m */ __I uint32_t RESERVED7[24]; __O uint32_t NOT[8]; /*!< (@ 0x400F6300) Toggle port m */ } LPC_GPIO_PORT_Type; /* ================================================================================ */ /* ================ SPI ================ */ /* ================================================================================ */ /** * @brief SPI (SPI) */ typedef struct { /*!< (@ 0x40100000) SPI Structure */ __IO uint32_t CR; /*!< (@ 0x40100000) SPI Control Register. This register controls the operation of the SPI. */ __I uint32_t SR; /*!< (@ 0x40100004) SPI Status Register. This register shows the status of the SPI. */ __IO uint32_t DR; /*!< (@ 0x40100008) SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register. */ __IO uint32_t CCR; /*!< (@ 0x4010000C) SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */ __IO uint32_t TCR; /*!< (@ 0x40100010) SPI Test Control register. For functional testing only. */ __IO uint32_t TSR; /*!< (@ 0x40100014) SPI Test Status register. For functional testing only. */ __I uint32_t RESERVED0; __IO uint32_t INT; /*!< (@ 0x4010001C) SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */ } LPC_SPI_Type; /* ================================================================================ */ /* ================ SGPIO ================ */ /* ================================================================================ */ /** * @brief Serial GPIO (SGPIO) (SGPIO) */ typedef struct { /*!< (@ 0x40101000) SGPIO Structure */ __IO uint32_t OUT_MUX_CFG[16]; /*!< (@ 0x40101000) Pin multiplexer configuration registers. */ __IO uint32_t SGPIO_MUX_CFG[16]; /*!< (@ 0x40101040) SGPIO multiplexer configuration registers. */ __IO uint32_t SLICE_MUX_CFG[16]; /*!< (@ 0x40101080) Slice multiplexer configuration registers. */ __IO uint32_t REG[16]; /*!< (@ 0x401010C0) Slice data registers. Each time COUNT0 reaches 0x0 the register shifts loading bit 31 with data captured from DIN(n). DOUT(n) is set to REG(0) */ __IO uint32_t REG_SS[16]; /*!< (@ 0x40101100) Slice data shadow registers. Each time POS reaches 0x0 the contents of REG_SS is exchanged with the content of REG */ __IO uint32_t PRESET[16]; /*!< (@ 0x40101140) Reload value of COUNT0, loaded when COUNT0 reaches 0x0 */ __IO uint32_t COUNT[16]; /*!< (@ 0x40101180) Down counter, counts down each clock cycle. */ __IO uint32_t POS[16]; /*!< (@ 0x401011C0) Each time COUNT0 reaches 0x0 POS counts down. */ __IO uint32_t MASK_A; /*!< (@ 0x40101200) Mask for pattern match function of slice A */ __IO uint32_t MASK_H; /*!< (@ 0x40101204) Mask for pattern match function of slice H */ __IO uint32_t MASK_I; /*!< (@ 0x40101208) Mask for pattern match function of slice I */ __IO uint32_t MASK_P; /*!< (@ 0x4010120C) Mask for pattern match function of slice P */ __I uint32_t GPIO_INREG; /*!< (@ 0x40101210) GPIO input status register */ __IO uint32_t GPIO_OUTREG; /*!< (@ 0x40101214) GPIO output control register */ __IO uint32_t GPIO_OENREG; /*!< (@ 0x40101218) GPIO OE control register */ __IO uint32_t CTRL_ENABLE; /*!< (@ 0x4010121C) Enables the slice COUNT counter */ __IO uint32_t CTRL_DISABLE; /*!< (@ 0x40101220) Disables the slice POS counter */ __I uint32_t RESERVED0[823]; __O uint32_t CLR_EN_0; /*!< (@ 0x40101F00) Shift clock interrupt clear mask */ __O uint32_t SET_EN_0; /*!< (@ 0x40101F04) Shift clock interrupt set mask */ __I uint32_t ENABLE_0; /*!< (@ 0x40101F08) Shift clock interrupt enable */ __I uint32_t STATUS_0; /*!< (@ 0x40101F0C) Shift clock interrupt status */ __O uint32_t CLR_STATUS_0; /*!< (@ 0x40101F10) Shift clock interrupt clear status */ __O uint32_t SET_STATUS_0; /*!< (@ 0x40101F14) Shift clock interrupt set status */ __I uint32_t RESERVED1[2]; __O uint32_t CLR_EN_1; /*!< (@ 0x40101F20) Exchange clock interrupt clear mask */ __O uint32_t SET_EN_1; /*!< (@ 0x40101F24) Exchange clock interrupt set mask */ __I uint32_t ENABLE_1; /*!< (@ 0x40101F28) Exchange clock interrupt enable */ __I uint32_t STATUS_1; /*!< (@ 0x40101F2C) Exchange clock interrupt status */ __O uint32_t CLR_STATUS_1; /*!< (@ 0x40101F30) Exchange clock interrupt clear status */ __O uint32_t SET_STATUS_1; /*!< (@ 0x40101F34) Exchange clock interrupt set status */ __I uint32_t RESERVED2[2]; __O uint32_t CLR_EN_2; /*!< (@ 0x40101F40) Pattern match interrupt clear mask */ __O uint32_t SET_EN_2; /*!< (@ 0x40101F44) Pattern match interrupt set mask */ __I uint32_t ENABLE_2; /*!< (@ 0x40101F48) Pattern match interrupt enable */ __I uint32_t STATUS_2; /*!< (@ 0x40101F4C) Pattern match interrupt status */ __O uint32_t CLR_STATUS_2; /*!< (@ 0x40101F50) Pattern match interrupt clear status */ __O uint32_t SET_STATUS_2; /*!< (@ 0x40101F54) Pattern match interrupt set status */ __I uint32_t RESERVED3[2]; __O uint32_t CLR_EN_3; /*!< (@ 0x40101F60) Input interrupt clear mask */ __O uint32_t SET_EN_3; /*!< (@ 0x40101F64) Input bit match interrupt set mask */ __I uint32_t ENABLE_3; /*!< (@ 0x40101F68) Input bit match interrupt enable */ __I uint32_t STATUS_3; /*!< (@ 0x40101F6C) Input bit match interrupt status */ __O uint32_t CLR_STATUS_3; /*!< (@ 0x40101F70) Input bit match interrupt clear status */ __O uint32_t SET_STATUS_3; /*!< (@ 0x40101F74) Input bit match interrupt set status */ } LPC_SGPIO_Type; /* -------------------- End of section using anonymous unions ------------------- */ #if defined(__CC_ARM) #pragma pop #elif defined(__ICCARM__) /* leave anonymous unions enabled */ #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__TMS470__) /* anonymous unions are enabled by default */ #elif defined(__TASKING__) #pragma warning restore #else #warning Not supported compiler type #endif /* ================================================================================ */ /* ================ struct 'SCT' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- SCT_CONFIG --------------------------------- */ #define SCT_CONFIG_UNIFY_Pos 0 /*!< SCT CONFIG: UNIFY Position */ #define SCT_CONFIG_UNIFY_Msk (0x01UL << SCT_CONFIG_UNIFY_Pos) /*!< SCT CONFIG: UNIFY Mask */ #define SCT_CONFIG_CLKMODE_Pos 1 /*!< SCT CONFIG: CLKMODE Position */ #define SCT_CONFIG_CLKMODE_Msk (0x03UL << SCT_CONFIG_CLKMODE_Pos) /*!< SCT CONFIG: CLKMODE Mask */ #define SCT_CONFIG_CKSEL_Pos 3 /*!< SCT CONFIG: CKSEL Position */ #define SCT_CONFIG_CKSEL_Msk (0x0fUL << SCT_CONFIG_CKSEL_Pos) /*!< SCT CONFIG: CKSEL Mask */ #define SCT_CONFIG_NORELAOD_L_Pos 7 /*!< SCT CONFIG: NORELAOD_L Position */ #define SCT_CONFIG_NORELAOD_L_Msk (0x01UL << SCT_CONFIG_NORELAOD_L_Pos) /*!< SCT CONFIG: NORELAOD_L Mask */ #define SCT_CONFIG_NORELOAD_H_Pos 8 /*!< SCT CONFIG: NORELOAD_H Position */ #define SCT_CONFIG_NORELOAD_H_Msk (0x01UL << SCT_CONFIG_NORELOAD_H_Pos) /*!< SCT CONFIG: NORELOAD_H Mask */ #define SCT_CONFIG_INSYNC_Pos 9 /*!< SCT CONFIG: INSYNC Position */ #define SCT_CONFIG_INSYNC_Msk (0x000000ffUL << SCT_CONFIG_INSYNC_Pos) /*!< SCT CONFIG: INSYNC Mask */ #define SCT_CONFIG_AUTOLIMIT_L_Pos 17 /*!< SCT CONFIG: AUTOLIMIT_L Position */ #define SCT_CONFIG_AUTOLIMIT_L_Msk (0x01UL << SCT_CONFIG_AUTOLIMIT_L_Pos) /*!< SCT CONFIG: AUTOLIMIT_L Mask */ #define SCT_CONFIG_AUTOLIMIT_H_Pos 18 /*!< SCT CONFIG: AUTOLIMIT_H Position */ #define SCT_CONFIG_AUTOLIMIT_H_Msk (0x01UL << SCT_CONFIG_AUTOLIMIT_H_Pos) /*!< SCT CONFIG: AUTOLIMIT_H Mask */ /* ---------------------------------- SCT_CTRL ---------------------------------- */ #define SCT_CTRL_DOWN_L_Pos 0 /*!< SCT CTRL: DOWN_L Position */ #define SCT_CTRL_DOWN_L_Msk (0x01UL << SCT_CTRL_DOWN_L_Pos) /*!< SCT CTRL: DOWN_L Mask */ #define SCT_CTRL_STOP_L_Pos 1 /*!< SCT CTRL: STOP_L Position */ #define SCT_CTRL_STOP_L_Msk (0x01UL << SCT_CTRL_STOP_L_Pos) /*!< SCT CTRL: STOP_L Mask */ #define SCT_CTRL_HALT_L_Pos 2 /*!< SCT CTRL: HALT_L Position */ #define SCT_CTRL_HALT_L_Msk (0x01UL << SCT_CTRL_HALT_L_Pos) /*!< SCT CTRL: HALT_L Mask */ #define SCT_CTRL_CLRCTR_L_Pos 3 /*!< SCT CTRL: CLRCTR_L Position */ #define SCT_CTRL_CLRCTR_L_Msk (0x01UL << SCT_CTRL_CLRCTR_L_Pos) /*!< SCT CTRL: CLRCTR_L Mask */ #define SCT_CTRL_BIDIR_L_Pos 4 /*!< SCT CTRL: BIDIR_L Position */ #define SCT_CTRL_BIDIR_L_Msk (0x01UL << SCT_CTRL_BIDIR_L_Pos) /*!< SCT CTRL: BIDIR_L Mask */ #define SCT_CTRL_PRE_L_Pos 5 /*!< SCT CTRL: PRE_L Position */ #define SCT_CTRL_PRE_L_Msk (0x000000ffUL << SCT_CTRL_PRE_L_Pos) /*!< SCT CTRL: PRE_L Mask */ #define SCT_CTRL_DOWN_H_Pos 16 /*!< SCT CTRL: DOWN_H Position */ #define SCT_CTRL_DOWN_H_Msk (0x01UL << SCT_CTRL_DOWN_H_Pos) /*!< SCT CTRL: DOWN_H Mask */ #define SCT_CTRL_STOP_H_Pos 17 /*!< SCT CTRL: STOP_H Position */ #define SCT_CTRL_STOP_H_Msk (0x01UL << SCT_CTRL_STOP_H_Pos) /*!< SCT CTRL: STOP_H Mask */ #define SCT_CTRL_HALT_H_Pos 18 /*!< SCT CTRL: HALT_H Position */ #define SCT_CTRL_HALT_H_Msk (0x01UL << SCT_CTRL_HALT_H_Pos) /*!< SCT CTRL: HALT_H Mask */ #define SCT_CTRL_CLRCTR_H_Pos 19 /*!< SCT CTRL: CLRCTR_H Position */ #define SCT_CTRL_CLRCTR_H_Msk (0x01UL << SCT_CTRL_CLRCTR_H_Pos) /*!< SCT CTRL: CLRCTR_H Mask */ #define SCT_CTRL_BIDIR_H_Pos 20 /*!< SCT CTRL: BIDIR_H Position */ #define SCT_CTRL_BIDIR_H_Msk (0x01UL << SCT_CTRL_BIDIR_H_Pos) /*!< SCT CTRL: BIDIR_H Mask */ #define SCT_CTRL_PRE_H_Pos 21 /*!< SCT CTRL: PRE_H Position */ #define SCT_CTRL_PRE_H_Msk (0x000000ffUL << SCT_CTRL_PRE_H_Pos) /*!< SCT CTRL: PRE_H Mask */ /* ---------------------------------- SCT_LIMIT --------------------------------- */ #define SCT_LIMIT_LIMMSK_L_Pos 0 /*!< SCT LIMIT: LIMMSK_L Position */ #define SCT_LIMIT_LIMMSK_L_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_L_Pos) /*!< SCT LIMIT: LIMMSK_L Mask */ #define SCT_LIMIT_LIMMSK_H_Pos 16 /*!< SCT LIMIT: LIMMSK_H Position */ #define SCT_LIMIT_LIMMSK_H_Msk (0x0000ffffUL << SCT_LIMIT_LIMMSK_H_Pos) /*!< SCT LIMIT: LIMMSK_H Mask */ /* ---------------------------------- SCT_HALT ---------------------------------- */ #define SCT_HALT_HALTMSK_L_Pos 0 /*!< SCT HALT: HALTMSK_L Position */ #define SCT_HALT_HALTMSK_L_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_L_Pos) /*!< SCT HALT: HALTMSK_L Mask */ #define SCT_HALT_HALTMSK_H_Pos 16 /*!< SCT HALT: HALTMSK_H Position */ #define SCT_HALT_HALTMSK_H_Msk (0x0000ffffUL << SCT_HALT_HALTMSK_H_Pos) /*!< SCT HALT: HALTMSK_H Mask */ /* ---------------------------------- SCT_STOP ---------------------------------- */ #define SCT_STOP_STOPMSK_L_Pos 0 /*!< SCT STOP: STOPMSK_L Position */ #define SCT_STOP_STOPMSK_L_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_L_Pos) /*!< SCT STOP: STOPMSK_L Mask */ #define SCT_STOP_STOPMSK_H_Pos 16 /*!< SCT STOP: STOPMSK_H Position */ #define SCT_STOP_STOPMSK_H_Msk (0x0000ffffUL << SCT_STOP_STOPMSK_H_Pos) /*!< SCT STOP: STOPMSK_H Mask */ /* ---------------------------------- SCT_START --------------------------------- */ #define SCT_START_STARTMSK_L_Pos 0 /*!< SCT START: STARTMSK_L Position */ #define SCT_START_STARTMSK_L_Msk (0x0000ffffUL << SCT_START_STARTMSK_L_Pos) /*!< SCT START: STARTMSK_L Mask */ #define SCT_START_STARTMSK_H_Pos 16 /*!< SCT START: STARTMSK_H Position */ #define SCT_START_STARTMSK_H_Msk (0x0000ffffUL << SCT_START_STARTMSK_H_Pos) /*!< SCT START: STARTMSK_H Mask */ /* --------------------------------- SCT_DITHER --------------------------------- */ #define SCT_DITHER_DITHMSK_L_Pos 0 /*!< SCT DITHER: DITHMSK_L Position */ #define SCT_DITHER_DITHMSK_L_Msk (0x0000ffffUL << SCT_DITHER_DITHMSK_L_Pos) /*!< SCT DITHER: DITHMSK_L Mask */ #define SCT_DITHER_DITHMSK_H_Pos 16 /*!< SCT DITHER: DITHMSK_H Position */ #define SCT_DITHER_DITHMSK_H_Msk (0x0000ffffUL << SCT_DITHER_DITHMSK_H_Pos) /*!< SCT DITHER: DITHMSK_H Mask */ /* ---------------------------------- SCT_COUNT --------------------------------- */ #define SCT_COUNT_CTR_L_Pos 0 /*!< SCT COUNT: CTR_L Position */ #define SCT_COUNT_CTR_L_Msk (0x0000ffffUL << SCT_COUNT_CTR_L_Pos) /*!< SCT COUNT: CTR_L Mask */ #define SCT_COUNT_CTR_H_Pos 16 /*!< SCT COUNT: CTR_H Position */ #define SCT_COUNT_CTR_H_Msk (0x0000ffffUL << SCT_COUNT_CTR_H_Pos) /*!< SCT COUNT: CTR_H Mask */ /* ---------------------------------- SCT_STATE --------------------------------- */ #define SCT_STATE_STATE_L_Pos 0 /*!< SCT STATE: STATE_L Position */ #define SCT_STATE_STATE_L_Msk (0x1fUL << SCT_STATE_STATE_L_Pos) /*!< SCT STATE: STATE_L Mask */ #define SCT_STATE_STATE_H_Pos 16 /*!< SCT STATE: STATE_H Position */ #define SCT_STATE_STATE_H_Msk (0x1fUL << SCT_STATE_STATE_H_Pos) /*!< SCT STATE: STATE_H Mask */ /* ---------------------------------- SCT_INPUT --------------------------------- */ #define SCT_INPUT_AIN0_Pos 0 /*!< SCT INPUT: AIN0 Position */ #define SCT_INPUT_AIN0_Msk (0x01UL << SCT_INPUT_AIN0_Pos) /*!< SCT INPUT: AIN0 Mask */ #define SCT_INPUT_AIN1_Pos 1 /*!< SCT INPUT: AIN1 Position */ #define SCT_INPUT_AIN1_Msk (0x01UL << SCT_INPUT_AIN1_Pos) /*!< SCT INPUT: AIN1 Mask */ #define SCT_INPUT_AIN2_Pos 2 /*!< SCT INPUT: AIN2 Position */ #define SCT_INPUT_AIN2_Msk (0x01UL << SCT_INPUT_AIN2_Pos) /*!< SCT INPUT: AIN2 Mask */ #define SCT_INPUT_AIN3_Pos 3 /*!< SCT INPUT: AIN3 Position */ #define SCT_INPUT_AIN3_Msk (0x01UL << SCT_INPUT_AIN3_Pos) /*!< SCT INPUT: AIN3 Mask */ #define SCT_INPUT_AIN4_Pos 4 /*!< SCT INPUT: AIN4 Position */ #define SCT_INPUT_AIN4_Msk (0x01UL << SCT_INPUT_AIN4_Pos) /*!< SCT INPUT: AIN4 Mask */ #define SCT_INPUT_AIN5_Pos 5 /*!< SCT INPUT: AIN5 Position */ #define SCT_INPUT_AIN5_Msk (0x01UL << SCT_INPUT_AIN5_Pos) /*!< SCT INPUT: AIN5 Mask */ #define SCT_INPUT_AIN6_Pos 6 /*!< SCT INPUT: AIN6 Position */ #define SCT_INPUT_AIN6_Msk (0x01UL << SCT_INPUT_AIN6_Pos) /*!< SCT INPUT: AIN6 Mask */ #define SCT_INPUT_AIN7_Pos 7 /*!< SCT INPUT: AIN7 Position */ #define SCT_INPUT_AIN7_Msk (0x01UL << SCT_INPUT_AIN7_Pos) /*!< SCT INPUT: AIN7 Mask */ #define SCT_INPUT_SIN0_Pos 16 /*!< SCT INPUT: SIN0 Position */ #define SCT_INPUT_SIN0_Msk (0x01UL << SCT_INPUT_SIN0_Pos) /*!< SCT INPUT: SIN0 Mask */ #define SCT_INPUT_SIN1_Pos 17 /*!< SCT INPUT: SIN1 Position */ #define SCT_INPUT_SIN1_Msk (0x01UL << SCT_INPUT_SIN1_Pos) /*!< SCT INPUT: SIN1 Mask */ #define SCT_INPUT_SIN2_Pos 18 /*!< SCT INPUT: SIN2 Position */ #define SCT_INPUT_SIN2_Msk (0x01UL << SCT_INPUT_SIN2_Pos) /*!< SCT INPUT: SIN2 Mask */ #define SCT_INPUT_SIN3_Pos 19 /*!< SCT INPUT: SIN3 Position */ #define SCT_INPUT_SIN3_Msk (0x01UL << SCT_INPUT_SIN3_Pos) /*!< SCT INPUT: SIN3 Mask */ #define SCT_INPUT_SIN4_Pos 20 /*!< SCT INPUT: SIN4 Position */ #define SCT_INPUT_SIN4_Msk (0x01UL << SCT_INPUT_SIN4_Pos) /*!< SCT INPUT: SIN4 Mask */ #define SCT_INPUT_SIN5_Pos 21 /*!< SCT INPUT: SIN5 Position */ #define SCT_INPUT_SIN5_Msk (0x01UL << SCT_INPUT_SIN5_Pos) /*!< SCT INPUT: SIN5 Mask */ #define SCT_INPUT_SIN6_Pos 22 /*!< SCT INPUT: SIN6 Position */ #define SCT_INPUT_SIN6_Msk (0x01UL << SCT_INPUT_SIN6_Pos) /*!< SCT INPUT: SIN6 Mask */ #define SCT_INPUT_SIN7_Pos 23 /*!< SCT INPUT: SIN7 Position */ #define SCT_INPUT_SIN7_Msk (0x01UL << SCT_INPUT_SIN7_Pos) /*!< SCT INPUT: SIN7 Mask */ /* --------------------------------- SCT_REGMODE -------------------------------- */ #define SCT_REGMODE_REGMOD_L_Pos 0 /*!< SCT REGMODE: REGMOD_L Position */ #define SCT_REGMODE_REGMOD_L_Msk (0x0000ffffUL << SCT_REGMODE_REGMOD_L_Pos) /*!< SCT REGMODE: REGMOD_L Mask */ #define SCT_REGMODE_REGMOD_H_Pos 16 /*!< SCT REGMODE: REGMOD_H Position */ #define SCT_REGMODE_REGMOD_H_Msk (0x0000ffffUL << SCT_REGMODE_REGMOD_H_Pos) /*!< SCT REGMODE: REGMOD_H Mask */ /* --------------------------------- SCT_OUTPUT --------------------------------- */ #define SCT_OUTPUT_OUT_Pos 0 /*!< SCT OUTPUT: OUT Position */ #define SCT_OUTPUT_OUT_Msk (0x0000ffffUL << SCT_OUTPUT_OUT_Pos) /*!< SCT OUTPUT: OUT Mask */ /* ------------------------------ SCT_OUTPUTDIRCTRL ----------------------------- */ #define SCT_OUTPUTDIRCTRL_SETCLR0_Pos 0 /*!< SCT OUTPUTDIRCTRL: SETCLR0 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR0_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR0_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR0 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR1_Pos 2 /*!< SCT OUTPUTDIRCTRL: SETCLR1 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR1_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR1_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR1 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR2_Pos 4 /*!< SCT OUTPUTDIRCTRL: SETCLR2 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR2_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR2_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR2 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR3_Pos 6 /*!< SCT OUTPUTDIRCTRL: SETCLR3 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR3_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR3_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR3 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR4_Pos 8 /*!< SCT OUTPUTDIRCTRL: SETCLR4 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR4_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR4_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR4 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR5_Pos 10 /*!< SCT OUTPUTDIRCTRL: SETCLR5 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR5_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR5_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR5 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR6_Pos 12 /*!< SCT OUTPUTDIRCTRL: SETCLR6 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR6_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR6_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR6 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR7_Pos 14 /*!< SCT OUTPUTDIRCTRL: SETCLR7 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR7_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR7_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR7 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR8_Pos 16 /*!< SCT OUTPUTDIRCTRL: SETCLR8 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR8_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR8_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR8 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR9_Pos 18 /*!< SCT OUTPUTDIRCTRL: SETCLR9 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR9_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR9_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR9 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR10_Pos 20 /*!< SCT OUTPUTDIRCTRL: SETCLR10 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR10_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR10_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR10 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR11_Pos 22 /*!< SCT OUTPUTDIRCTRL: SETCLR11 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR11_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR11_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR11 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR12_Pos 24 /*!< SCT OUTPUTDIRCTRL: SETCLR12 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR12_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR12_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR12 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR13_Pos 26 /*!< SCT OUTPUTDIRCTRL: SETCLR13 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR13_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR13_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR13 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR14_Pos 28 /*!< SCT OUTPUTDIRCTRL: SETCLR14 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR14_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR14_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR14 Mask */ #define SCT_OUTPUTDIRCTRL_SETCLR15_Pos 30 /*!< SCT OUTPUTDIRCTRL: SETCLR15 Position */ #define SCT_OUTPUTDIRCTRL_SETCLR15_Msk (0x03UL << SCT_OUTPUTDIRCTRL_SETCLR15_Pos) /*!< SCT OUTPUTDIRCTRL: SETCLR15 Mask */ /* ----------------------------------- SCT_RES ---------------------------------- */ #define SCT_RES_O0RES_Pos 0 /*!< SCT RES: O0RES Position */ #define SCT_RES_O0RES_Msk (0x03UL << SCT_RES_O0RES_Pos) /*!< SCT RES: O0RES Mask */ #define SCT_RES_O1RES_Pos 2 /*!< SCT RES: O1RES Position */ #define SCT_RES_O1RES_Msk (0x03UL << SCT_RES_O1RES_Pos) /*!< SCT RES: O1RES Mask */ #define SCT_RES_O2RES_Pos 4 /*!< SCT RES: O2RES Position */ #define SCT_RES_O2RES_Msk (0x03UL << SCT_RES_O2RES_Pos) /*!< SCT RES: O2RES Mask */ #define SCT_RES_O3RES_Pos 6 /*!< SCT RES: O3RES Position */ #define SCT_RES_O3RES_Msk (0x03UL << SCT_RES_O3RES_Pos) /*!< SCT RES: O3RES Mask */ #define SCT_RES_O4RES_Pos 8 /*!< SCT RES: O4RES Position */ #define SCT_RES_O4RES_Msk (0x03UL << SCT_RES_O4RES_Pos) /*!< SCT RES: O4RES Mask */ #define SCT_RES_O5RES_Pos 10 /*!< SCT RES: O5RES Position */ #define SCT_RES_O5RES_Msk (0x03UL << SCT_RES_O5RES_Pos) /*!< SCT RES: O5RES Mask */ #define SCT_RES_O6RES_Pos 12 /*!< SCT RES: O6RES Position */ #define SCT_RES_O6RES_Msk (0x03UL << SCT_RES_O6RES_Pos) /*!< SCT RES: O6RES Mask */ #define SCT_RES_O7RES_Pos 14 /*!< SCT RES: O7RES Position */ #define SCT_RES_O7RES_Msk (0x03UL << SCT_RES_O7RES_Pos) /*!< SCT RES: O7RES Mask */ #define SCT_RES_O8RES_Pos 16 /*!< SCT RES: O8RES Position */ #define SCT_RES_O8RES_Msk (0x03UL << SCT_RES_O8RES_Pos) /*!< SCT RES: O8RES Mask */ #define SCT_RES_O9RES_Pos 18 /*!< SCT RES: O9RES Position */ #define SCT_RES_O9RES_Msk (0x03UL << SCT_RES_O9RES_Pos) /*!< SCT RES: O9RES Mask */ #define SCT_RES_O10RES_Pos 20 /*!< SCT RES: O10RES Position */ #define SCT_RES_O10RES_Msk (0x03UL << SCT_RES_O10RES_Pos) /*!< SCT RES: O10RES Mask */ #define SCT_RES_O11RES_Pos 22 /*!< SCT RES: O11RES Position */ #define SCT_RES_O11RES_Msk (0x03UL << SCT_RES_O11RES_Pos) /*!< SCT RES: O11RES Mask */ #define SCT_RES_O12RES_Pos 24 /*!< SCT RES: O12RES Position */ #define SCT_RES_O12RES_Msk (0x03UL << SCT_RES_O12RES_Pos) /*!< SCT RES: O12RES Mask */ #define SCT_RES_O13RES_Pos 26 /*!< SCT RES: O13RES Position */ #define SCT_RES_O13RES_Msk (0x03UL << SCT_RES_O13RES_Pos) /*!< SCT RES: O13RES Mask */ #define SCT_RES_O14RES_Pos 28 /*!< SCT RES: O14RES Position */ #define SCT_RES_O14RES_Msk (0x03UL << SCT_RES_O14RES_Pos) /*!< SCT RES: O14RES Mask */ #define SCT_RES_O15RES_Pos 30 /*!< SCT RES: O15RES Position */ #define SCT_RES_O15RES_Msk (0x03UL << SCT_RES_O15RES_Pos) /*!< SCT RES: O15RES Mask */ /* --------------------------------- SCT_DMAREQ0 -------------------------------- */ #define SCT_DMAREQ0_DEV_00_Pos 0 /*!< SCT DMAREQ0: DEV_00 Position */ #define SCT_DMAREQ0_DEV_00_Msk (0x01UL << SCT_DMAREQ0_DEV_00_Pos) /*!< SCT DMAREQ0: DEV_00 Mask */ #define SCT_DMAREQ0_DEV_01_Pos 1 /*!< SCT DMAREQ0: DEV_01 Position */ #define SCT_DMAREQ0_DEV_01_Msk (0x01UL << SCT_DMAREQ0_DEV_01_Pos) /*!< SCT DMAREQ0: DEV_01 Mask */ #define SCT_DMAREQ0_DEV_02_Pos 2 /*!< SCT DMAREQ0: DEV_02 Position */ #define SCT_DMAREQ0_DEV_02_Msk (0x01UL << SCT_DMAREQ0_DEV_02_Pos) /*!< SCT DMAREQ0: DEV_02 Mask */ #define SCT_DMAREQ0_DEV_03_Pos 3 /*!< SCT DMAREQ0: DEV_03 Position */ #define SCT_DMAREQ0_DEV_03_Msk (0x01UL << SCT_DMAREQ0_DEV_03_Pos) /*!< SCT DMAREQ0: DEV_03 Mask */ #define SCT_DMAREQ0_DEV_04_Pos 4 /*!< SCT DMAREQ0: DEV_04 Position */ #define SCT_DMAREQ0_DEV_04_Msk (0x01UL << SCT_DMAREQ0_DEV_04_Pos) /*!< SCT DMAREQ0: DEV_04 Mask */ #define SCT_DMAREQ0_DEV_05_Pos 5 /*!< SCT DMAREQ0: DEV_05 Position */ #define SCT_DMAREQ0_DEV_05_Msk (0x01UL << SCT_DMAREQ0_DEV_05_Pos) /*!< SCT DMAREQ0: DEV_05 Mask */ #define SCT_DMAREQ0_DEV_06_Pos 6 /*!< SCT DMAREQ0: DEV_06 Position */ #define SCT_DMAREQ0_DEV_06_Msk (0x01UL << SCT_DMAREQ0_DEV_06_Pos) /*!< SCT DMAREQ0: DEV_06 Mask */ #define SCT_DMAREQ0_DEV_07_Pos 7 /*!< SCT DMAREQ0: DEV_07 Position */ #define SCT_DMAREQ0_DEV_07_Msk (0x01UL << SCT_DMAREQ0_DEV_07_Pos) /*!< SCT DMAREQ0: DEV_07 Mask */ #define SCT_DMAREQ0_DEV_08_Pos 8 /*!< SCT DMAREQ0: DEV_08 Position */ #define SCT_DMAREQ0_DEV_08_Msk (0x01UL << SCT_DMAREQ0_DEV_08_Pos) /*!< SCT DMAREQ0: DEV_08 Mask */ #define SCT_DMAREQ0_DEV_09_Pos 9 /*!< SCT DMAREQ0: DEV_09 Position */ #define SCT_DMAREQ0_DEV_09_Msk (0x01UL << SCT_DMAREQ0_DEV_09_Pos) /*!< SCT DMAREQ0: DEV_09 Mask */ #define SCT_DMAREQ0_DEV_010_Pos 10 /*!< SCT DMAREQ0: DEV_010 Position */ #define SCT_DMAREQ0_DEV_010_Msk (0x01UL << SCT_DMAREQ0_DEV_010_Pos) /*!< SCT DMAREQ0: DEV_010 Mask */ #define SCT_DMAREQ0_DEV_011_Pos 11 /*!< SCT DMAREQ0: DEV_011 Position */ #define SCT_DMAREQ0_DEV_011_Msk (0x01UL << SCT_DMAREQ0_DEV_011_Pos) /*!< SCT DMAREQ0: DEV_011 Mask */ #define SCT_DMAREQ0_DEV_012_Pos 12 /*!< SCT DMAREQ0: DEV_012 Position */ #define SCT_DMAREQ0_DEV_012_Msk (0x01UL << SCT_DMAREQ0_DEV_012_Pos) /*!< SCT DMAREQ0: DEV_012 Mask */ #define SCT_DMAREQ0_DEV_013_Pos 13 /*!< SCT DMAREQ0: DEV_013 Position */ #define SCT_DMAREQ0_DEV_013_Msk (0x01UL << SCT_DMAREQ0_DEV_013_Pos) /*!< SCT DMAREQ0: DEV_013 Mask */ #define SCT_DMAREQ0_DEV_014_Pos 14 /*!< SCT DMAREQ0: DEV_014 Position */ #define SCT_DMAREQ0_DEV_014_Msk (0x01UL << SCT_DMAREQ0_DEV_014_Pos) /*!< SCT DMAREQ0: DEV_014 Mask */ #define SCT_DMAREQ0_DEV_015_Pos 15 /*!< SCT DMAREQ0: DEV_015 Position */ #define SCT_DMAREQ0_DEV_015_Msk (0x01UL << SCT_DMAREQ0_DEV_015_Pos) /*!< SCT DMAREQ0: DEV_015 Mask */ #define SCT_DMAREQ0_DRL0_Pos 30 /*!< SCT DMAREQ0: DRL0 Position */ #define SCT_DMAREQ0_DRL0_Msk (0x01UL << SCT_DMAREQ0_DRL0_Pos) /*!< SCT DMAREQ0: DRL0 Mask */ #define SCT_DMAREQ0_DRQ0_Pos 31 /*!< SCT DMAREQ0: DRQ0 Position */ #define SCT_DMAREQ0_DRQ0_Msk (0x01UL << SCT_DMAREQ0_DRQ0_Pos) /*!< SCT DMAREQ0: DRQ0 Mask */ /* --------------------------------- SCT_DMAREQ1 -------------------------------- */ #define SCT_DMAREQ1_DEV_10_Pos 0 /*!< SCT DMAREQ1: DEV_10 Position */ #define SCT_DMAREQ1_DEV_10_Msk (0x01UL << SCT_DMAREQ1_DEV_10_Pos) /*!< SCT DMAREQ1: DEV_10 Mask */ #define SCT_DMAREQ1_DEV_11_Pos 1 /*!< SCT DMAREQ1: DEV_11 Position */ #define SCT_DMAREQ1_DEV_11_Msk (0x01UL << SCT_DMAREQ1_DEV_11_Pos) /*!< SCT DMAREQ1: DEV_11 Mask */ #define SCT_DMAREQ1_DEV_12_Pos 2 /*!< SCT DMAREQ1: DEV_12 Position */ #define SCT_DMAREQ1_DEV_12_Msk (0x01UL << SCT_DMAREQ1_DEV_12_Pos) /*!< SCT DMAREQ1: DEV_12 Mask */ #define SCT_DMAREQ1_DEV_13_Pos 3 /*!< SCT DMAREQ1: DEV_13 Position */ #define SCT_DMAREQ1_DEV_13_Msk (0x01UL << SCT_DMAREQ1_DEV_13_Pos) /*!< SCT DMAREQ1: DEV_13 Mask */ #define SCT_DMAREQ1_DEV_14_Pos 4 /*!< SCT DMAREQ1: DEV_14 Position */ #define SCT_DMAREQ1_DEV_14_Msk (0x01UL << SCT_DMAREQ1_DEV_14_Pos) /*!< SCT DMAREQ1: DEV_14 Mask */ #define SCT_DMAREQ1_DEV_15_Pos 5 /*!< SCT DMAREQ1: DEV_15 Position */ #define SCT_DMAREQ1_DEV_15_Msk (0x01UL << SCT_DMAREQ1_DEV_15_Pos) /*!< SCT DMAREQ1: DEV_15 Mask */ #define SCT_DMAREQ1_DEV_16_Pos 6 /*!< SCT DMAREQ1: DEV_16 Position */ #define SCT_DMAREQ1_DEV_16_Msk (0x01UL << SCT_DMAREQ1_DEV_16_Pos) /*!< SCT DMAREQ1: DEV_16 Mask */ #define SCT_DMAREQ1_DEV_17_Pos 7 /*!< SCT DMAREQ1: DEV_17 Position */ #define SCT_DMAREQ1_DEV_17_Msk (0x01UL << SCT_DMAREQ1_DEV_17_Pos) /*!< SCT DMAREQ1: DEV_17 Mask */ #define SCT_DMAREQ1_DEV_18_Pos 8 /*!< SCT DMAREQ1: DEV_18 Position */ #define SCT_DMAREQ1_DEV_18_Msk (0x01UL << SCT_DMAREQ1_DEV_18_Pos) /*!< SCT DMAREQ1: DEV_18 Mask */ #define SCT_DMAREQ1_DEV_19_Pos 9 /*!< SCT DMAREQ1: DEV_19 Position */ #define SCT_DMAREQ1_DEV_19_Msk (0x01UL << SCT_DMAREQ1_DEV_19_Pos) /*!< SCT DMAREQ1: DEV_19 Mask */ #define SCT_DMAREQ1_DEV_110_Pos 10 /*!< SCT DMAREQ1: DEV_110 Position */ #define SCT_DMAREQ1_DEV_110_Msk (0x01UL << SCT_DMAREQ1_DEV_110_Pos) /*!< SCT DMAREQ1: DEV_110 Mask */ #define SCT_DMAREQ1_DEV_111_Pos 11 /*!< SCT DMAREQ1: DEV_111 Position */ #define SCT_DMAREQ1_DEV_111_Msk (0x01UL << SCT_DMAREQ1_DEV_111_Pos) /*!< SCT DMAREQ1: DEV_111 Mask */ #define SCT_DMAREQ1_DEV_112_Pos 12 /*!< SCT DMAREQ1: DEV_112 Position */ #define SCT_DMAREQ1_DEV_112_Msk (0x01UL << SCT_DMAREQ1_DEV_112_Pos) /*!< SCT DMAREQ1: DEV_112 Mask */ #define SCT_DMAREQ1_DEV_113_Pos 13 /*!< SCT DMAREQ1: DEV_113 Position */ #define SCT_DMAREQ1_DEV_113_Msk (0x01UL << SCT_DMAREQ1_DEV_113_Pos) /*!< SCT DMAREQ1: DEV_113 Mask */ #define SCT_DMAREQ1_DEV_114_Pos 14 /*!< SCT DMAREQ1: DEV_114 Position */ #define SCT_DMAREQ1_DEV_114_Msk (0x01UL << SCT_DMAREQ1_DEV_114_Pos) /*!< SCT DMAREQ1: DEV_114 Mask */ #define SCT_DMAREQ1_DEV_115_Pos 15 /*!< SCT DMAREQ1: DEV_115 Position */ #define SCT_DMAREQ1_DEV_115_Msk (0x01UL << SCT_DMAREQ1_DEV_115_Pos) /*!< SCT DMAREQ1: DEV_115 Mask */ #define SCT_DMAREQ1_DRL1_Pos 30 /*!< SCT DMAREQ1: DRL1 Position */ #define SCT_DMAREQ1_DRL1_Msk (0x01UL << SCT_DMAREQ1_DRL1_Pos) /*!< SCT DMAREQ1: DRL1 Mask */ #define SCT_DMAREQ1_DRQ1_Pos 31 /*!< SCT DMAREQ1: DRQ1 Position */ #define SCT_DMAREQ1_DRQ1_Msk (0x01UL << SCT_DMAREQ1_DRQ1_Pos) /*!< SCT DMAREQ1: DRQ1 Mask */ /* ---------------------------------- SCT_EVEN ---------------------------------- */ #define SCT_EVEN_IEN0_Pos 0 /*!< SCT EVEN: IEN0 Position */ #define SCT_EVEN_IEN0_Msk (0x01UL << SCT_EVEN_IEN0_Pos) /*!< SCT EVEN: IEN0 Mask */ #define SCT_EVEN_IEN1_Pos 1 /*!< SCT EVEN: IEN1 Position */ #define SCT_EVEN_IEN1_Msk (0x01UL << SCT_EVEN_IEN1_Pos) /*!< SCT EVEN: IEN1 Mask */ #define SCT_EVEN_IEN2_Pos 2 /*!< SCT EVEN: IEN2 Position */ #define SCT_EVEN_IEN2_Msk (0x01UL << SCT_EVEN_IEN2_Pos) /*!< SCT EVEN: IEN2 Mask */ #define SCT_EVEN_IEN3_Pos 3 /*!< SCT EVEN: IEN3 Position */ #define SCT_EVEN_IEN3_Msk (0x01UL << SCT_EVEN_IEN3_Pos) /*!< SCT EVEN: IEN3 Mask */ #define SCT_EVEN_IEN4_Pos 4 /*!< SCT EVEN: IEN4 Position */ #define SCT_EVEN_IEN4_Msk (0x01UL << SCT_EVEN_IEN4_Pos) /*!< SCT EVEN: IEN4 Mask */ #define SCT_EVEN_IEN5_Pos 5 /*!< SCT EVEN: IEN5 Position */ #define SCT_EVEN_IEN5_Msk (0x01UL << SCT_EVEN_IEN5_Pos) /*!< SCT EVEN: IEN5 Mask */ #define SCT_EVEN_IEN6_Pos 6 /*!< SCT EVEN: IEN6 Position */ #define SCT_EVEN_IEN6_Msk (0x01UL << SCT_EVEN_IEN6_Pos) /*!< SCT EVEN: IEN6 Mask */ #define SCT_EVEN_IEN7_Pos 7 /*!< SCT EVEN: IEN7 Position */ #define SCT_EVEN_IEN7_Msk (0x01UL << SCT_EVEN_IEN7_Pos) /*!< SCT EVEN: IEN7 Mask */ #define SCT_EVEN_IEN8_Pos 8 /*!< SCT EVEN: IEN8 Position */ #define SCT_EVEN_IEN8_Msk (0x01UL << SCT_EVEN_IEN8_Pos) /*!< SCT EVEN: IEN8 Mask */ #define SCT_EVEN_IEN9_Pos 9 /*!< SCT EVEN: IEN9 Position */ #define SCT_EVEN_IEN9_Msk (0x01UL << SCT_EVEN_IEN9_Pos) /*!< SCT EVEN: IEN9 Mask */ #define SCT_EVEN_IEN10_Pos 10 /*!< SCT EVEN: IEN10 Position */ #define SCT_EVEN_IEN10_Msk (0x01UL << SCT_EVEN_IEN10_Pos) /*!< SCT EVEN: IEN10 Mask */ #define SCT_EVEN_IEN11_Pos 11 /*!< SCT EVEN: IEN11 Position */ #define SCT_EVEN_IEN11_Msk (0x01UL << SCT_EVEN_IEN11_Pos) /*!< SCT EVEN: IEN11 Mask */ #define SCT_EVEN_IEN12_Pos 12 /*!< SCT EVEN: IEN12 Position */ #define SCT_EVEN_IEN12_Msk (0x01UL << SCT_EVEN_IEN12_Pos) /*!< SCT EVEN: IEN12 Mask */ #define SCT_EVEN_IEN13_Pos 13 /*!< SCT EVEN: IEN13 Position */ #define SCT_EVEN_IEN13_Msk (0x01UL << SCT_EVEN_IEN13_Pos) /*!< SCT EVEN: IEN13 Mask */ #define SCT_EVEN_IEN14_Pos 14 /*!< SCT EVEN: IEN14 Position */ #define SCT_EVEN_IEN14_Msk (0x01UL << SCT_EVEN_IEN14_Pos) /*!< SCT EVEN: IEN14 Mask */ #define SCT_EVEN_IEN15_Pos 15 /*!< SCT EVEN: IEN15 Position */ #define SCT_EVEN_IEN15_Msk (0x01UL << SCT_EVEN_IEN15_Pos) /*!< SCT EVEN: IEN15 Mask */ /* --------------------------------- SCT_EVFLAG --------------------------------- */ #define SCT_EVFLAG_FLAG0_Pos 0 /*!< SCT EVFLAG: FLAG0 Position */ #define SCT_EVFLAG_FLAG0_Msk (0x01UL << SCT_EVFLAG_FLAG0_Pos) /*!< SCT EVFLAG: FLAG0 Mask */ #define SCT_EVFLAG_FLAG1_Pos 1 /*!< SCT EVFLAG: FLAG1 Position */ #define SCT_EVFLAG_FLAG1_Msk (0x01UL << SCT_EVFLAG_FLAG1_Pos) /*!< SCT EVFLAG: FLAG1 Mask */ #define SCT_EVFLAG_FLAG2_Pos 2 /*!< SCT EVFLAG: FLAG2 Position */ #define SCT_EVFLAG_FLAG2_Msk (0x01UL << SCT_EVFLAG_FLAG2_Pos) /*!< SCT EVFLAG: FLAG2 Mask */ #define SCT_EVFLAG_FLAG3_Pos 3 /*!< SCT EVFLAG: FLAG3 Position */ #define SCT_EVFLAG_FLAG3_Msk (0x01UL << SCT_EVFLAG_FLAG3_Pos) /*!< SCT EVFLAG: FLAG3 Mask */ #define SCT_EVFLAG_FLAG4_Pos 4 /*!< SCT EVFLAG: FLAG4 Position */ #define SCT_EVFLAG_FLAG4_Msk (0x01UL << SCT_EVFLAG_FLAG4_Pos) /*!< SCT EVFLAG: FLAG4 Mask */ #define SCT_EVFLAG_FLAG5_Pos 5 /*!< SCT EVFLAG: FLAG5 Position */ #define SCT_EVFLAG_FLAG5_Msk (0x01UL << SCT_EVFLAG_FLAG5_Pos) /*!< SCT EVFLAG: FLAG5 Mask */ #define SCT_EVFLAG_FLAG6_Pos 6 /*!< SCT EVFLAG: FLAG6 Position */ #define SCT_EVFLAG_FLAG6_Msk (0x01UL << SCT_EVFLAG_FLAG6_Pos) /*!< SCT EVFLAG: FLAG6 Mask */ #define SCT_EVFLAG_FLAG7_Pos 7 /*!< SCT EVFLAG: FLAG7 Position */ #define SCT_EVFLAG_FLAG7_Msk (0x01UL << SCT_EVFLAG_FLAG7_Pos) /*!< SCT EVFLAG: FLAG7 Mask */ #define SCT_EVFLAG_FLAG8_Pos 8 /*!< SCT EVFLAG: FLAG8 Position */ #define SCT_EVFLAG_FLAG8_Msk (0x01UL << SCT_EVFLAG_FLAG8_Pos) /*!< SCT EVFLAG: FLAG8 Mask */ #define SCT_EVFLAG_FLAG9_Pos 9 /*!< SCT EVFLAG: FLAG9 Position */ #define SCT_EVFLAG_FLAG9_Msk (0x01UL << SCT_EVFLAG_FLAG9_Pos) /*!< SCT EVFLAG: FLAG9 Mask */ #define SCT_EVFLAG_FLAG10_Pos 10 /*!< SCT EVFLAG: FLAG10 Position */ #define SCT_EVFLAG_FLAG10_Msk (0x01UL << SCT_EVFLAG_FLAG10_Pos) /*!< SCT EVFLAG: FLAG10 Mask */ #define SCT_EVFLAG_FLAG11_Pos 11 /*!< SCT EVFLAG: FLAG11 Position */ #define SCT_EVFLAG_FLAG11_Msk (0x01UL << SCT_EVFLAG_FLAG11_Pos) /*!< SCT EVFLAG: FLAG11 Mask */ #define SCT_EVFLAG_FLAG12_Pos 12 /*!< SCT EVFLAG: FLAG12 Position */ #define SCT_EVFLAG_FLAG12_Msk (0x01UL << SCT_EVFLAG_FLAG12_Pos) /*!< SCT EVFLAG: FLAG12 Mask */ #define SCT_EVFLAG_FLAG13_Pos 13 /*!< SCT EVFLAG: FLAG13 Position */ #define SCT_EVFLAG_FLAG13_Msk (0x01UL << SCT_EVFLAG_FLAG13_Pos) /*!< SCT EVFLAG: FLAG13 Mask */ #define SCT_EVFLAG_FLAG14_Pos 14 /*!< SCT EVFLAG: FLAG14 Position */ #define SCT_EVFLAG_FLAG14_Msk (0x01UL << SCT_EVFLAG_FLAG14_Pos) /*!< SCT EVFLAG: FLAG14 Mask */ #define SCT_EVFLAG_FLAG15_Pos 15 /*!< SCT EVFLAG: FLAG15 Position */ #define SCT_EVFLAG_FLAG15_Msk (0x01UL << SCT_EVFLAG_FLAG15_Pos) /*!< SCT EVFLAG: FLAG15 Mask */ /* ---------------------------------- SCT_CONEN --------------------------------- */ #define SCT_CONEN_NCEN0_Pos 0 /*!< SCT CONEN: NCEN0 Position */ #define SCT_CONEN_NCEN0_Msk (0x01UL << SCT_CONEN_NCEN0_Pos) /*!< SCT CONEN: NCEN0 Mask */ #define SCT_CONEN_NCEN1_Pos 1 /*!< SCT CONEN: NCEN1 Position */ #define SCT_CONEN_NCEN1_Msk (0x01UL << SCT_CONEN_NCEN1_Pos) /*!< SCT CONEN: NCEN1 Mask */ #define SCT_CONEN_NCEN2_Pos 2 /*!< SCT CONEN: NCEN2 Position */ #define SCT_CONEN_NCEN2_Msk (0x01UL << SCT_CONEN_NCEN2_Pos) /*!< SCT CONEN: NCEN2 Mask */ #define SCT_CONEN_NCEN3_Pos 3 /*!< SCT CONEN: NCEN3 Position */ #define SCT_CONEN_NCEN3_Msk (0x01UL << SCT_CONEN_NCEN3_Pos) /*!< SCT CONEN: NCEN3 Mask */ #define SCT_CONEN_NCEN4_Pos 4 /*!< SCT CONEN: NCEN4 Position */ #define SCT_CONEN_NCEN4_Msk (0x01UL << SCT_CONEN_NCEN4_Pos) /*!< SCT CONEN: NCEN4 Mask */ #define SCT_CONEN_NCEN5_Pos 5 /*!< SCT CONEN: NCEN5 Position */ #define SCT_CONEN_NCEN5_Msk (0x01UL << SCT_CONEN_NCEN5_Pos) /*!< SCT CONEN: NCEN5 Mask */ #define SCT_CONEN_NCEN6_Pos 6 /*!< SCT CONEN: NCEN6 Position */ #define SCT_CONEN_NCEN6_Msk (0x01UL << SCT_CONEN_NCEN6_Pos) /*!< SCT CONEN: NCEN6 Mask */ #define SCT_CONEN_NCEN7_Pos 7 /*!< SCT CONEN: NCEN7 Position */ #define SCT_CONEN_NCEN7_Msk (0x01UL << SCT_CONEN_NCEN7_Pos) /*!< SCT CONEN: NCEN7 Mask */ #define SCT_CONEN_NCEN8_Pos 8 /*!< SCT CONEN: NCEN8 Position */ #define SCT_CONEN_NCEN8_Msk (0x01UL << SCT_CONEN_NCEN8_Pos) /*!< SCT CONEN: NCEN8 Mask */ #define SCT_CONEN_NCEN9_Pos 9 /*!< SCT CONEN: NCEN9 Position */ #define SCT_CONEN_NCEN9_Msk (0x01UL << SCT_CONEN_NCEN9_Pos) /*!< SCT CONEN: NCEN9 Mask */ #define SCT_CONEN_NCEN10_Pos 10 /*!< SCT CONEN: NCEN10 Position */ #define SCT_CONEN_NCEN10_Msk (0x01UL << SCT_CONEN_NCEN10_Pos) /*!< SCT CONEN: NCEN10 Mask */ #define SCT_CONEN_NCEN11_Pos 11 /*!< SCT CONEN: NCEN11 Position */ #define SCT_CONEN_NCEN11_Msk (0x01UL << SCT_CONEN_NCEN11_Pos) /*!< SCT CONEN: NCEN11 Mask */ #define SCT_CONEN_NCEN12_Pos 12 /*!< SCT CONEN: NCEN12 Position */ #define SCT_CONEN_NCEN12_Msk (0x01UL << SCT_CONEN_NCEN12_Pos) /*!< SCT CONEN: NCEN12 Mask */ #define SCT_CONEN_NCEN13_Pos 13 /*!< SCT CONEN: NCEN13 Position */ #define SCT_CONEN_NCEN13_Msk (0x01UL << SCT_CONEN_NCEN13_Pos) /*!< SCT CONEN: NCEN13 Mask */ #define SCT_CONEN_NCEN14_Pos 14 /*!< SCT CONEN: NCEN14 Position */ #define SCT_CONEN_NCEN14_Msk (0x01UL << SCT_CONEN_NCEN14_Pos) /*!< SCT CONEN: NCEN14 Mask */ #define SCT_CONEN_NCEN15_Pos 15 /*!< SCT CONEN: NCEN15 Position */ #define SCT_CONEN_NCEN15_Msk (0x01UL << SCT_CONEN_NCEN15_Pos) /*!< SCT CONEN: NCEN15 Mask */ /* --------------------------------- SCT_CONFLAG -------------------------------- */ #define SCT_CONFLAG_NCFLAG0_Pos 0 /*!< SCT CONFLAG: NCFLAG0 Position */ #define SCT_CONFLAG_NCFLAG0_Msk (0x01UL << SCT_CONFLAG_NCFLAG0_Pos) /*!< SCT CONFLAG: NCFLAG0 Mask */ #define SCT_CONFLAG_NCFLAG1_Pos 1 /*!< SCT CONFLAG: NCFLAG1 Position */ #define SCT_CONFLAG_NCFLAG1_Msk (0x01UL << SCT_CONFLAG_NCFLAG1_Pos) /*!< SCT CONFLAG: NCFLAG1 Mask */ #define SCT_CONFLAG_NCFLAG2_Pos 2 /*!< SCT CONFLAG: NCFLAG2 Position */ #define SCT_CONFLAG_NCFLAG2_Msk (0x01UL << SCT_CONFLAG_NCFLAG2_Pos) /*!< SCT CONFLAG: NCFLAG2 Mask */ #define SCT_CONFLAG_NCFLAG3_Pos 3 /*!< SCT CONFLAG: NCFLAG3 Position */ #define SCT_CONFLAG_NCFLAG3_Msk (0x01UL << SCT_CONFLAG_NCFLAG3_Pos) /*!< SCT CONFLAG: NCFLAG3 Mask */ #define SCT_CONFLAG_NCFLAG4_Pos 4 /*!< SCT CONFLAG: NCFLAG4 Position */ #define SCT_CONFLAG_NCFLAG4_Msk (0x01UL << SCT_CONFLAG_NCFLAG4_Pos) /*!< SCT CONFLAG: NCFLAG4 Mask */ #define SCT_CONFLAG_NCFLAG5_Pos 5 /*!< SCT CONFLAG: NCFLAG5 Position */ #define SCT_CONFLAG_NCFLAG5_Msk (0x01UL << SCT_CONFLAG_NCFLAG5_Pos) /*!< SCT CONFLAG: NCFLAG5 Mask */ #define SCT_CONFLAG_NCFLAG6_Pos 6 /*!< SCT CONFLAG: NCFLAG6 Position */ #define SCT_CONFLAG_NCFLAG6_Msk (0x01UL << SCT_CONFLAG_NCFLAG6_Pos) /*!< SCT CONFLAG: NCFLAG6 Mask */ #define SCT_CONFLAG_NCFLAG7_Pos 7 /*!< SCT CONFLAG: NCFLAG7 Position */ #define SCT_CONFLAG_NCFLAG7_Msk (0x01UL << SCT_CONFLAG_NCFLAG7_Pos) /*!< SCT CONFLAG: NCFLAG7 Mask */ #define SCT_CONFLAG_NCFLAG8_Pos 8 /*!< SCT CONFLAG: NCFLAG8 Position */ #define SCT_CONFLAG_NCFLAG8_Msk (0x01UL << SCT_CONFLAG_NCFLAG8_Pos) /*!< SCT CONFLAG: NCFLAG8 Mask */ #define SCT_CONFLAG_NCFLAG9_Pos 9 /*!< SCT CONFLAG: NCFLAG9 Position */ #define SCT_CONFLAG_NCFLAG9_Msk (0x01UL << SCT_CONFLAG_NCFLAG9_Pos) /*!< SCT CONFLAG: NCFLAG9 Mask */ #define SCT_CONFLAG_NCFLAG10_Pos 10 /*!< SCT CONFLAG: NCFLAG10 Position */ #define SCT_CONFLAG_NCFLAG10_Msk (0x01UL << SCT_CONFLAG_NCFLAG10_Pos) /*!< SCT CONFLAG: NCFLAG10 Mask */ #define SCT_CONFLAG_NCFLAG11_Pos 11 /*!< SCT CONFLAG: NCFLAG11 Position */ #define SCT_CONFLAG_NCFLAG11_Msk (0x01UL << SCT_CONFLAG_NCFLAG11_Pos) /*!< SCT CONFLAG: NCFLAG11 Mask */ #define SCT_CONFLAG_NCFLAG12_Pos 12 /*!< SCT CONFLAG: NCFLAG12 Position */ #define SCT_CONFLAG_NCFLAG12_Msk (0x01UL << SCT_CONFLAG_NCFLAG12_Pos) /*!< SCT CONFLAG: NCFLAG12 Mask */ #define SCT_CONFLAG_NCFLAG13_Pos 13 /*!< SCT CONFLAG: NCFLAG13 Position */ #define SCT_CONFLAG_NCFLAG13_Msk (0x01UL << SCT_CONFLAG_NCFLAG13_Pos) /*!< SCT CONFLAG: NCFLAG13 Mask */ #define SCT_CONFLAG_NCFLAG14_Pos 14 /*!< SCT CONFLAG: NCFLAG14 Position */ #define SCT_CONFLAG_NCFLAG14_Msk (0x01UL << SCT_CONFLAG_NCFLAG14_Pos) /*!< SCT CONFLAG: NCFLAG14 Mask */ #define SCT_CONFLAG_NCFLAG15_Pos 15 /*!< SCT CONFLAG: NCFLAG15 Position */ #define SCT_CONFLAG_NCFLAG15_Msk (0x01UL << SCT_CONFLAG_NCFLAG15_Pos) /*!< SCT CONFLAG: NCFLAG15 Mask */ #define SCT_CONFLAG_BUSERRL_Pos 30 /*!< SCT CONFLAG: BUSERRL Position */ #define SCT_CONFLAG_BUSERRL_Msk (0x01UL << SCT_CONFLAG_BUSERRL_Pos) /*!< SCT CONFLAG: BUSERRL Mask */ #define SCT_CONFLAG_BUSERRH_Pos 31 /*!< SCT CONFLAG: BUSERRH Position */ #define SCT_CONFLAG_BUSERRH_Msk (0x01UL << SCT_CONFLAG_BUSERRH_Pos) /*!< SCT CONFLAG: BUSERRH Mask */ /* --------------------------------- SCT_MATCH0 --------------------------------- */ #define SCT_MATCH0_MATCH_L_Pos 0 /*!< SCT MATCH0: MATCH_L Position */ #define SCT_MATCH0_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH0_MATCH_L_Pos) /*!< SCT MATCH0: MATCH_L Mask */ #define SCT_MATCH0_MATCH_H_Pos 16 /*!< SCT MATCH0: MATCH_H Position */ #define SCT_MATCH0_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH0_MATCH_H_Pos) /*!< SCT MATCH0: MATCH_H Mask */ /* ---------------------------------- SCT_CAP0 ---------------------------------- */ #define SCT_CAP0_CAP_L_Pos 0 /*!< SCT CAP0: CAP_L Position */ #define SCT_CAP0_CAP_L_Msk (0x0000ffffUL << SCT_CAP0_CAP_L_Pos) /*!< SCT CAP0: CAP_L Mask */ #define SCT_CAP0_CAP_H_Pos 16 /*!< SCT CAP0: CAP_H Position */ #define SCT_CAP0_CAP_H_Msk (0x0000ffffUL << SCT_CAP0_CAP_H_Pos) /*!< SCT CAP0: CAP_H Mask */ /* --------------------------------- SCT_MATCH1 --------------------------------- */ #define SCT_MATCH1_MATCH_L_Pos 0 /*!< SCT MATCH1: MATCH_L Position */ #define SCT_MATCH1_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH1_MATCH_L_Pos) /*!< SCT MATCH1: MATCH_L Mask */ #define SCT_MATCH1_MATCH_H_Pos 16 /*!< SCT MATCH1: MATCH_H Position */ #define SCT_MATCH1_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH1_MATCH_H_Pos) /*!< SCT MATCH1: MATCH_H Mask */ /* ---------------------------------- SCT_CAP1 ---------------------------------- */ #define SCT_CAP1_CAP_L_Pos 0 /*!< SCT CAP1: CAP_L Position */ #define SCT_CAP1_CAP_L_Msk (0x0000ffffUL << SCT_CAP1_CAP_L_Pos) /*!< SCT CAP1: CAP_L Mask */ #define SCT_CAP1_CAP_H_Pos 16 /*!< SCT CAP1: CAP_H Position */ #define SCT_CAP1_CAP_H_Msk (0x0000ffffUL << SCT_CAP1_CAP_H_Pos) /*!< SCT CAP1: CAP_H Mask */ /* --------------------------------- SCT_MATCH2 --------------------------------- */ #define SCT_MATCH2_MATCH_L_Pos 0 /*!< SCT MATCH2: MATCH_L Position */ #define SCT_MATCH2_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH2_MATCH_L_Pos) /*!< SCT MATCH2: MATCH_L Mask */ #define SCT_MATCH2_MATCH_H_Pos 16 /*!< SCT MATCH2: MATCH_H Position */ #define SCT_MATCH2_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH2_MATCH_H_Pos) /*!< SCT MATCH2: MATCH_H Mask */ /* ---------------------------------- SCT_CAP2 ---------------------------------- */ #define SCT_CAP2_CAP_L_Pos 0 /*!< SCT CAP2: CAP_L Position */ #define SCT_CAP2_CAP_L_Msk (0x0000ffffUL << SCT_CAP2_CAP_L_Pos) /*!< SCT CAP2: CAP_L Mask */ #define SCT_CAP2_CAP_H_Pos 16 /*!< SCT CAP2: CAP_H Position */ #define SCT_CAP2_CAP_H_Msk (0x0000ffffUL << SCT_CAP2_CAP_H_Pos) /*!< SCT CAP2: CAP_H Mask */ /* --------------------------------- SCT_MATCH3 --------------------------------- */ #define SCT_MATCH3_MATCH_L_Pos 0 /*!< SCT MATCH3: MATCH_L Position */ #define SCT_MATCH3_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH3_MATCH_L_Pos) /*!< SCT MATCH3: MATCH_L Mask */ #define SCT_MATCH3_MATCH_H_Pos 16 /*!< SCT MATCH3: MATCH_H Position */ #define SCT_MATCH3_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH3_MATCH_H_Pos) /*!< SCT MATCH3: MATCH_H Mask */ /* ---------------------------------- SCT_CAP3 ---------------------------------- */ #define SCT_CAP3_CAP_L_Pos 0 /*!< SCT CAP3: CAP_L Position */ #define SCT_CAP3_CAP_L_Msk (0x0000ffffUL << SCT_CAP3_CAP_L_Pos) /*!< SCT CAP3: CAP_L Mask */ #define SCT_CAP3_CAP_H_Pos 16 /*!< SCT CAP3: CAP_H Position */ #define SCT_CAP3_CAP_H_Msk (0x0000ffffUL << SCT_CAP3_CAP_H_Pos) /*!< SCT CAP3: CAP_H Mask */ /* ---------------------------------- SCT_CAP4 ---------------------------------- */ #define SCT_CAP4_CAP_L_Pos 0 /*!< SCT CAP4: CAP_L Position */ #define SCT_CAP4_CAP_L_Msk (0x0000ffffUL << SCT_CAP4_CAP_L_Pos) /*!< SCT CAP4: CAP_L Mask */ #define SCT_CAP4_CAP_H_Pos 16 /*!< SCT CAP4: CAP_H Position */ #define SCT_CAP4_CAP_H_Msk (0x0000ffffUL << SCT_CAP4_CAP_H_Pos) /*!< SCT CAP4: CAP_H Mask */ /* --------------------------------- SCT_MATCH4 --------------------------------- */ #define SCT_MATCH4_MATCH_L_Pos 0 /*!< SCT MATCH4: MATCH_L Position */ #define SCT_MATCH4_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH4_MATCH_L_Pos) /*!< SCT MATCH4: MATCH_L Mask */ #define SCT_MATCH4_MATCH_H_Pos 16 /*!< SCT MATCH4: MATCH_H Position */ #define SCT_MATCH4_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH4_MATCH_H_Pos) /*!< SCT MATCH4: MATCH_H Mask */ /* --------------------------------- SCT_MATCH5 --------------------------------- */ #define SCT_MATCH5_MATCH_L_Pos 0 /*!< SCT MATCH5: MATCH_L Position */ #define SCT_MATCH5_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH5_MATCH_L_Pos) /*!< SCT MATCH5: MATCH_L Mask */ #define SCT_MATCH5_MATCH_H_Pos 16 /*!< SCT MATCH5: MATCH_H Position */ #define SCT_MATCH5_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH5_MATCH_H_Pos) /*!< SCT MATCH5: MATCH_H Mask */ /* ---------------------------------- SCT_CAP5 ---------------------------------- */ #define SCT_CAP5_CAP_L_Pos 0 /*!< SCT CAP5: CAP_L Position */ #define SCT_CAP5_CAP_L_Msk (0x0000ffffUL << SCT_CAP5_CAP_L_Pos) /*!< SCT CAP5: CAP_L Mask */ #define SCT_CAP5_CAP_H_Pos 16 /*!< SCT CAP5: CAP_H Position */ #define SCT_CAP5_CAP_H_Msk (0x0000ffffUL << SCT_CAP5_CAP_H_Pos) /*!< SCT CAP5: CAP_H Mask */ /* ---------------------------------- SCT_CAP6 ---------------------------------- */ #define SCT_CAP6_CAP_L_Pos 0 /*!< SCT CAP6: CAP_L Position */ #define SCT_CAP6_CAP_L_Msk (0x0000ffffUL << SCT_CAP6_CAP_L_Pos) /*!< SCT CAP6: CAP_L Mask */ #define SCT_CAP6_CAP_H_Pos 16 /*!< SCT CAP6: CAP_H Position */ #define SCT_CAP6_CAP_H_Msk (0x0000ffffUL << SCT_CAP6_CAP_H_Pos) /*!< SCT CAP6: CAP_H Mask */ /* --------------------------------- SCT_MATCH6 --------------------------------- */ #define SCT_MATCH6_MATCH_L_Pos 0 /*!< SCT MATCH6: MATCH_L Position */ #define SCT_MATCH6_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH6_MATCH_L_Pos) /*!< SCT MATCH6: MATCH_L Mask */ #define SCT_MATCH6_MATCH_H_Pos 16 /*!< SCT MATCH6: MATCH_H Position */ #define SCT_MATCH6_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH6_MATCH_H_Pos) /*!< SCT MATCH6: MATCH_H Mask */ /* ---------------------------------- SCT_CAP7 ---------------------------------- */ #define SCT_CAP7_CAP_L_Pos 0 /*!< SCT CAP7: CAP_L Position */ #define SCT_CAP7_CAP_L_Msk (0x0000ffffUL << SCT_CAP7_CAP_L_Pos) /*!< SCT CAP7: CAP_L Mask */ #define SCT_CAP7_CAP_H_Pos 16 /*!< SCT CAP7: CAP_H Position */ #define SCT_CAP7_CAP_H_Msk (0x0000ffffUL << SCT_CAP7_CAP_H_Pos) /*!< SCT CAP7: CAP_H Mask */ /* --------------------------------- SCT_MATCH7 --------------------------------- */ #define SCT_MATCH7_MATCH_L_Pos 0 /*!< SCT MATCH7: MATCH_L Position */ #define SCT_MATCH7_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH7_MATCH_L_Pos) /*!< SCT MATCH7: MATCH_L Mask */ #define SCT_MATCH7_MATCH_H_Pos 16 /*!< SCT MATCH7: MATCH_H Position */ #define SCT_MATCH7_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH7_MATCH_H_Pos) /*!< SCT MATCH7: MATCH_H Mask */ /* ---------------------------------- SCT_CAP8 ---------------------------------- */ #define SCT_CAP8_CAP_L_Pos 0 /*!< SCT CAP8: CAP_L Position */ #define SCT_CAP8_CAP_L_Msk (0x0000ffffUL << SCT_CAP8_CAP_L_Pos) /*!< SCT CAP8: CAP_L Mask */ #define SCT_CAP8_CAP_H_Pos 16 /*!< SCT CAP8: CAP_H Position */ #define SCT_CAP8_CAP_H_Msk (0x0000ffffUL << SCT_CAP8_CAP_H_Pos) /*!< SCT CAP8: CAP_H Mask */ /* --------------------------------- SCT_MATCH8 --------------------------------- */ #define SCT_MATCH8_MATCH_L_Pos 0 /*!< SCT MATCH8: MATCH_L Position */ #define SCT_MATCH8_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH8_MATCH_L_Pos) /*!< SCT MATCH8: MATCH_L Mask */ #define SCT_MATCH8_MATCH_H_Pos 16 /*!< SCT MATCH8: MATCH_H Position */ #define SCT_MATCH8_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH8_MATCH_H_Pos) /*!< SCT MATCH8: MATCH_H Mask */ /* ---------------------------------- SCT_CAP9 ---------------------------------- */ #define SCT_CAP9_CAP_L_Pos 0 /*!< SCT CAP9: CAP_L Position */ #define SCT_CAP9_CAP_L_Msk (0x0000ffffUL << SCT_CAP9_CAP_L_Pos) /*!< SCT CAP9: CAP_L Mask */ #define SCT_CAP9_CAP_H_Pos 16 /*!< SCT CAP9: CAP_H Position */ #define SCT_CAP9_CAP_H_Msk (0x0000ffffUL << SCT_CAP9_CAP_H_Pos) /*!< SCT CAP9: CAP_H Mask */ /* --------------------------------- SCT_MATCH9 --------------------------------- */ #define SCT_MATCH9_MATCH_L_Pos 0 /*!< SCT MATCH9: MATCH_L Position */ #define SCT_MATCH9_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH9_MATCH_L_Pos) /*!< SCT MATCH9: MATCH_L Mask */ #define SCT_MATCH9_MATCH_H_Pos 16 /*!< SCT MATCH9: MATCH_H Position */ #define SCT_MATCH9_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH9_MATCH_H_Pos) /*!< SCT MATCH9: MATCH_H Mask */ /* ---------------------------------- SCT_CAP10 --------------------------------- */ #define SCT_CAP10_CAP_L_Pos 0 /*!< SCT CAP10: CAP_L Position */ #define SCT_CAP10_CAP_L_Msk (0x0000ffffUL << SCT_CAP10_CAP_L_Pos) /*!< SCT CAP10: CAP_L Mask */ #define SCT_CAP10_CAP_H_Pos 16 /*!< SCT CAP10: CAP_H Position */ #define SCT_CAP10_CAP_H_Msk (0x0000ffffUL << SCT_CAP10_CAP_H_Pos) /*!< SCT CAP10: CAP_H Mask */ /* --------------------------------- SCT_MATCH10 -------------------------------- */ #define SCT_MATCH10_MATCH_L_Pos 0 /*!< SCT MATCH10: MATCH_L Position */ #define SCT_MATCH10_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH10_MATCH_L_Pos) /*!< SCT MATCH10: MATCH_L Mask */ #define SCT_MATCH10_MATCH_H_Pos 16 /*!< SCT MATCH10: MATCH_H Position */ #define SCT_MATCH10_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH10_MATCH_H_Pos) /*!< SCT MATCH10: MATCH_H Mask */ /* ---------------------------------- SCT_CAP11 --------------------------------- */ #define SCT_CAP11_CAP_L_Pos 0 /*!< SCT CAP11: CAP_L Position */ #define SCT_CAP11_CAP_L_Msk (0x0000ffffUL << SCT_CAP11_CAP_L_Pos) /*!< SCT CAP11: CAP_L Mask */ #define SCT_CAP11_CAP_H_Pos 16 /*!< SCT CAP11: CAP_H Position */ #define SCT_CAP11_CAP_H_Msk (0x0000ffffUL << SCT_CAP11_CAP_H_Pos) /*!< SCT CAP11: CAP_H Mask */ /* --------------------------------- SCT_MATCH11 -------------------------------- */ #define SCT_MATCH11_MATCH_L_Pos 0 /*!< SCT MATCH11: MATCH_L Position */ #define SCT_MATCH11_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH11_MATCH_L_Pos) /*!< SCT MATCH11: MATCH_L Mask */ #define SCT_MATCH11_MATCH_H_Pos 16 /*!< SCT MATCH11: MATCH_H Position */ #define SCT_MATCH11_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH11_MATCH_H_Pos) /*!< SCT MATCH11: MATCH_H Mask */ /* ---------------------------------- SCT_CAP12 --------------------------------- */ #define SCT_CAP12_CAP_L_Pos 0 /*!< SCT CAP12: CAP_L Position */ #define SCT_CAP12_CAP_L_Msk (0x0000ffffUL << SCT_CAP12_CAP_L_Pos) /*!< SCT CAP12: CAP_L Mask */ #define SCT_CAP12_CAP_H_Pos 16 /*!< SCT CAP12: CAP_H Position */ #define SCT_CAP12_CAP_H_Msk (0x0000ffffUL << SCT_CAP12_CAP_H_Pos) /*!< SCT CAP12: CAP_H Mask */ /* --------------------------------- SCT_MATCH12 -------------------------------- */ #define SCT_MATCH12_MATCH_L_Pos 0 /*!< SCT MATCH12: MATCH_L Position */ #define SCT_MATCH12_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH12_MATCH_L_Pos) /*!< SCT MATCH12: MATCH_L Mask */ #define SCT_MATCH12_MATCH_H_Pos 16 /*!< SCT MATCH12: MATCH_H Position */ #define SCT_MATCH12_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH12_MATCH_H_Pos) /*!< SCT MATCH12: MATCH_H Mask */ /* --------------------------------- SCT_MATCH13 -------------------------------- */ #define SCT_MATCH13_MATCH_L_Pos 0 /*!< SCT MATCH13: MATCH_L Position */ #define SCT_MATCH13_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH13_MATCH_L_Pos) /*!< SCT MATCH13: MATCH_L Mask */ #define SCT_MATCH13_MATCH_H_Pos 16 /*!< SCT MATCH13: MATCH_H Position */ #define SCT_MATCH13_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH13_MATCH_H_Pos) /*!< SCT MATCH13: MATCH_H Mask */ /* ---------------------------------- SCT_CAP13 --------------------------------- */ #define SCT_CAP13_CAP_L_Pos 0 /*!< SCT CAP13: CAP_L Position */ #define SCT_CAP13_CAP_L_Msk (0x0000ffffUL << SCT_CAP13_CAP_L_Pos) /*!< SCT CAP13: CAP_L Mask */ #define SCT_CAP13_CAP_H_Pos 16 /*!< SCT CAP13: CAP_H Position */ #define SCT_CAP13_CAP_H_Msk (0x0000ffffUL << SCT_CAP13_CAP_H_Pos) /*!< SCT CAP13: CAP_H Mask */ /* ---------------------------------- SCT_CAP14 --------------------------------- */ #define SCT_CAP14_CAP_L_Pos 0 /*!< SCT CAP14: CAP_L Position */ #define SCT_CAP14_CAP_L_Msk (0x0000ffffUL << SCT_CAP14_CAP_L_Pos) /*!< SCT CAP14: CAP_L Mask */ #define SCT_CAP14_CAP_H_Pos 16 /*!< SCT CAP14: CAP_H Position */ #define SCT_CAP14_CAP_H_Msk (0x0000ffffUL << SCT_CAP14_CAP_H_Pos) /*!< SCT CAP14: CAP_H Mask */ /* --------------------------------- SCT_MATCH14 -------------------------------- */ #define SCT_MATCH14_MATCH_L_Pos 0 /*!< SCT MATCH14: MATCH_L Position */ #define SCT_MATCH14_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH14_MATCH_L_Pos) /*!< SCT MATCH14: MATCH_L Mask */ #define SCT_MATCH14_MATCH_H_Pos 16 /*!< SCT MATCH14: MATCH_H Position */ #define SCT_MATCH14_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH14_MATCH_H_Pos) /*!< SCT MATCH14: MATCH_H Mask */ /* --------------------------------- SCT_MATCH15 -------------------------------- */ #define SCT_MATCH15_MATCH_L_Pos 0 /*!< SCT MATCH15: MATCH_L Position */ #define SCT_MATCH15_MATCH_L_Msk (0x0000ffffUL << SCT_MATCH15_MATCH_L_Pos) /*!< SCT MATCH15: MATCH_L Mask */ #define SCT_MATCH15_MATCH_H_Pos 16 /*!< SCT MATCH15: MATCH_H Position */ #define SCT_MATCH15_MATCH_H_Msk (0x0000ffffUL << SCT_MATCH15_MATCH_H_Pos) /*!< SCT MATCH15: MATCH_H Mask */ /* ---------------------------------- SCT_CAP15 --------------------------------- */ #define SCT_CAP15_CAP_L_Pos 0 /*!< SCT CAP15: CAP_L Position */ #define SCT_CAP15_CAP_L_Msk (0x0000ffffUL << SCT_CAP15_CAP_L_Pos) /*!< SCT CAP15: CAP_L Mask */ #define SCT_CAP15_CAP_H_Pos 16 /*!< SCT CAP15: CAP_H Position */ #define SCT_CAP15_CAP_H_Msk (0x0000ffffUL << SCT_CAP15_CAP_H_Pos) /*!< SCT CAP15: CAP_H Mask */ /* -------------------------------- SCT_FRACMAT0 -------------------------------- */ #define SCT_FRACMAT0_FRACMAT_L_Pos 0 /*!< SCT FRACMAT0: FRACMAT_L Position */ #define SCT_FRACMAT0_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT0_FRACMAT_L_Pos) /*!< SCT FRACMAT0: FRACMAT_L Mask */ #define SCT_FRACMAT0_FRACMAT_H_Pos 16 /*!< SCT FRACMAT0: FRACMAT_H Position */ #define SCT_FRACMAT0_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT0_FRACMAT_H_Pos) /*!< SCT FRACMAT0: FRACMAT_H Mask */ /* -------------------------------- SCT_FRACMAT1 -------------------------------- */ #define SCT_FRACMAT1_FRACMAT_L_Pos 0 /*!< SCT FRACMAT1: FRACMAT_L Position */ #define SCT_FRACMAT1_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT1_FRACMAT_L_Pos) /*!< SCT FRACMAT1: FRACMAT_L Mask */ #define SCT_FRACMAT1_FRACMAT_H_Pos 16 /*!< SCT FRACMAT1: FRACMAT_H Position */ #define SCT_FRACMAT1_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT1_FRACMAT_H_Pos) /*!< SCT FRACMAT1: FRACMAT_H Mask */ /* -------------------------------- SCT_FRACMAT2 -------------------------------- */ #define SCT_FRACMAT2_FRACMAT_L_Pos 0 /*!< SCT FRACMAT2: FRACMAT_L Position */ #define SCT_FRACMAT2_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT2_FRACMAT_L_Pos) /*!< SCT FRACMAT2: FRACMAT_L Mask */ #define SCT_FRACMAT2_FRACMAT_H_Pos 16 /*!< SCT FRACMAT2: FRACMAT_H Position */ #define SCT_FRACMAT2_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT2_FRACMAT_H_Pos) /*!< SCT FRACMAT2: FRACMAT_H Mask */ /* -------------------------------- SCT_FRACMAT3 -------------------------------- */ #define SCT_FRACMAT3_FRACMAT_L_Pos 0 /*!< SCT FRACMAT3: FRACMAT_L Position */ #define SCT_FRACMAT3_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT3_FRACMAT_L_Pos) /*!< SCT FRACMAT3: FRACMAT_L Mask */ #define SCT_FRACMAT3_FRACMAT_H_Pos 16 /*!< SCT FRACMAT3: FRACMAT_H Position */ #define SCT_FRACMAT3_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT3_FRACMAT_H_Pos) /*!< SCT FRACMAT3: FRACMAT_H Mask */ /* -------------------------------- SCT_FRACMAT4 -------------------------------- */ #define SCT_FRACMAT4_FRACMAT_L_Pos 0 /*!< SCT FRACMAT4: FRACMAT_L Position */ #define SCT_FRACMAT4_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT4_FRACMAT_L_Pos) /*!< SCT FRACMAT4: FRACMAT_L Mask */ #define SCT_FRACMAT4_FRACMAT_H_Pos 16 /*!< SCT FRACMAT4: FRACMAT_H Position */ #define SCT_FRACMAT4_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT4_FRACMAT_H_Pos) /*!< SCT FRACMAT4: FRACMAT_H Mask */ /* -------------------------------- SCT_FRACMAT5 -------------------------------- */ #define SCT_FRACMAT5_FRACMAT_L_Pos 0 /*!< SCT FRACMAT5: FRACMAT_L Position */ #define SCT_FRACMAT5_FRACMAT_L_Msk (0x0fUL << SCT_FRACMAT5_FRACMAT_L_Pos) /*!< SCT FRACMAT5: FRACMAT_L Mask */ #define SCT_FRACMAT5_FRACMAT_H_Pos 16 /*!< SCT FRACMAT5: FRACMAT_H Position */ #define SCT_FRACMAT5_FRACMAT_H_Msk (0x0fUL << SCT_FRACMAT5_FRACMAT_H_Pos) /*!< SCT FRACMAT5: FRACMAT_H Mask */ /* -------------------------------- SCT_MATCHREL0 ------------------------------- */ #define SCT_MATCHREL0_RELOAD_L_Pos 0 /*!< SCT MATCHREL0: RELOAD_L Position */ #define SCT_MATCHREL0_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOAD_L_Pos) /*!< SCT MATCHREL0: RELOAD_L Mask */ #define SCT_MATCHREL0_RELOAD_H_Pos 16 /*!< SCT MATCHREL0: RELOAD_H Position */ #define SCT_MATCHREL0_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL0_RELOAD_H_Pos) /*!< SCT MATCHREL0: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL0 -------------------------------- */ #define SCT_CAPCTRL0_CAPCON_L_Pos 0 /*!< SCT CAPCTRL0: CAPCON_L Position */ #define SCT_CAPCTRL0_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCON_L_Pos) /*!< SCT CAPCTRL0: CAPCON_L Mask */ #define SCT_CAPCTRL0_CAPCON_H_Pos 16 /*!< SCT CAPCTRL0: CAPCON_H Position */ #define SCT_CAPCTRL0_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL0_CAPCON_H_Pos) /*!< SCT CAPCTRL0: CAPCON_H Mask */ /* -------------------------------- SCT_CAPCTRL1 -------------------------------- */ #define SCT_CAPCTRL1_CAPCON_L_Pos 0 /*!< SCT CAPCTRL1: CAPCON_L Position */ #define SCT_CAPCTRL1_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCON_L_Pos) /*!< SCT CAPCTRL1: CAPCON_L Mask */ #define SCT_CAPCTRL1_CAPCON_H_Pos 16 /*!< SCT CAPCTRL1: CAPCON_H Position */ #define SCT_CAPCTRL1_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL1_CAPCON_H_Pos) /*!< SCT CAPCTRL1: CAPCON_H Mask */ /* -------------------------------- SCT_MATCHREL1 ------------------------------- */ #define SCT_MATCHREL1_RELOAD_L_Pos 0 /*!< SCT MATCHREL1: RELOAD_L Position */ #define SCT_MATCHREL1_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOAD_L_Pos) /*!< SCT MATCHREL1: RELOAD_L Mask */ #define SCT_MATCHREL1_RELOAD_H_Pos 16 /*!< SCT MATCHREL1: RELOAD_H Position */ #define SCT_MATCHREL1_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL1_RELOAD_H_Pos) /*!< SCT MATCHREL1: RELOAD_H Mask */ /* -------------------------------- SCT_MATCHREL2 ------------------------------- */ #define SCT_MATCHREL2_RELOAD_L_Pos 0 /*!< SCT MATCHREL2: RELOAD_L Position */ #define SCT_MATCHREL2_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOAD_L_Pos) /*!< SCT MATCHREL2: RELOAD_L Mask */ #define SCT_MATCHREL2_RELOAD_H_Pos 16 /*!< SCT MATCHREL2: RELOAD_H Position */ #define SCT_MATCHREL2_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL2_RELOAD_H_Pos) /*!< SCT MATCHREL2: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL2 -------------------------------- */ #define SCT_CAPCTRL2_CAPCON_L_Pos 0 /*!< SCT CAPCTRL2: CAPCON_L Position */ #define SCT_CAPCTRL2_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCON_L_Pos) /*!< SCT CAPCTRL2: CAPCON_L Mask */ #define SCT_CAPCTRL2_CAPCON_H_Pos 16 /*!< SCT CAPCTRL2: CAPCON_H Position */ #define SCT_CAPCTRL2_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL2_CAPCON_H_Pos) /*!< SCT CAPCTRL2: CAPCON_H Mask */ /* -------------------------------- SCT_CAPCTRL3 -------------------------------- */ #define SCT_CAPCTRL3_CAPCON_L_Pos 0 /*!< SCT CAPCTRL3: CAPCON_L Position */ #define SCT_CAPCTRL3_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCON_L_Pos) /*!< SCT CAPCTRL3: CAPCON_L Mask */ #define SCT_CAPCTRL3_CAPCON_H_Pos 16 /*!< SCT CAPCTRL3: CAPCON_H Position */ #define SCT_CAPCTRL3_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL3_CAPCON_H_Pos) /*!< SCT CAPCTRL3: CAPCON_H Mask */ /* -------------------------------- SCT_MATCHREL3 ------------------------------- */ #define SCT_MATCHREL3_RELOAD_L_Pos 0 /*!< SCT MATCHREL3: RELOAD_L Position */ #define SCT_MATCHREL3_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOAD_L_Pos) /*!< SCT MATCHREL3: RELOAD_L Mask */ #define SCT_MATCHREL3_RELOAD_H_Pos 16 /*!< SCT MATCHREL3: RELOAD_H Position */ #define SCT_MATCHREL3_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL3_RELOAD_H_Pos) /*!< SCT MATCHREL3: RELOAD_H Mask */ /* -------------------------------- SCT_MATCHREL4 ------------------------------- */ #define SCT_MATCHREL4_RELOAD_L_Pos 0 /*!< SCT MATCHREL4: RELOAD_L Position */ #define SCT_MATCHREL4_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOAD_L_Pos) /*!< SCT MATCHREL4: RELOAD_L Mask */ #define SCT_MATCHREL4_RELOAD_H_Pos 16 /*!< SCT MATCHREL4: RELOAD_H Position */ #define SCT_MATCHREL4_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL4_RELOAD_H_Pos) /*!< SCT MATCHREL4: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL4 -------------------------------- */ #define SCT_CAPCTRL4_CAPCON_L_Pos 0 /*!< SCT CAPCTRL4: CAPCON_L Position */ #define SCT_CAPCTRL4_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCON_L_Pos) /*!< SCT CAPCTRL4: CAPCON_L Mask */ #define SCT_CAPCTRL4_CAPCON_H_Pos 16 /*!< SCT CAPCTRL4: CAPCON_H Position */ #define SCT_CAPCTRL4_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL4_CAPCON_H_Pos) /*!< SCT CAPCTRL4: CAPCON_H Mask */ /* -------------------------------- SCT_MATCHREL5 ------------------------------- */ #define SCT_MATCHREL5_RELOAD_L_Pos 0 /*!< SCT MATCHREL5: RELOAD_L Position */ #define SCT_MATCHREL5_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOAD_L_Pos) /*!< SCT MATCHREL5: RELOAD_L Mask */ #define SCT_MATCHREL5_RELOAD_H_Pos 16 /*!< SCT MATCHREL5: RELOAD_H Position */ #define SCT_MATCHREL5_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL5_RELOAD_H_Pos) /*!< SCT MATCHREL5: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL5 -------------------------------- */ #define SCT_CAPCTRL5_CAPCON_L_Pos 0 /*!< SCT CAPCTRL5: CAPCON_L Position */ #define SCT_CAPCTRL5_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCON_L_Pos) /*!< SCT CAPCTRL5: CAPCON_L Mask */ #define SCT_CAPCTRL5_CAPCON_H_Pos 16 /*!< SCT CAPCTRL5: CAPCON_H Position */ #define SCT_CAPCTRL5_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL5_CAPCON_H_Pos) /*!< SCT CAPCTRL5: CAPCON_H Mask */ /* -------------------------------- SCT_CAPCTRL6 -------------------------------- */ #define SCT_CAPCTRL6_CAPCON_L_Pos 0 /*!< SCT CAPCTRL6: CAPCON_L Position */ #define SCT_CAPCTRL6_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCON_L_Pos) /*!< SCT CAPCTRL6: CAPCON_L Mask */ #define SCT_CAPCTRL6_CAPCON_H_Pos 16 /*!< SCT CAPCTRL6: CAPCON_H Position */ #define SCT_CAPCTRL6_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL6_CAPCON_H_Pos) /*!< SCT CAPCTRL6: CAPCON_H Mask */ /* -------------------------------- SCT_MATCHREL6 ------------------------------- */ #define SCT_MATCHREL6_RELOAD_L_Pos 0 /*!< SCT MATCHREL6: RELOAD_L Position */ #define SCT_MATCHREL6_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOAD_L_Pos) /*!< SCT MATCHREL6: RELOAD_L Mask */ #define SCT_MATCHREL6_RELOAD_H_Pos 16 /*!< SCT MATCHREL6: RELOAD_H Position */ #define SCT_MATCHREL6_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL6_RELOAD_H_Pos) /*!< SCT MATCHREL6: RELOAD_H Mask */ /* -------------------------------- SCT_MATCHREL7 ------------------------------- */ #define SCT_MATCHREL7_RELOAD_L_Pos 0 /*!< SCT MATCHREL7: RELOAD_L Position */ #define SCT_MATCHREL7_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOAD_L_Pos) /*!< SCT MATCHREL7: RELOAD_L Mask */ #define SCT_MATCHREL7_RELOAD_H_Pos 16 /*!< SCT MATCHREL7: RELOAD_H Position */ #define SCT_MATCHREL7_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL7_RELOAD_H_Pos) /*!< SCT MATCHREL7: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL7 -------------------------------- */ #define SCT_CAPCTRL7_CAPCON_L_Pos 0 /*!< SCT CAPCTRL7: CAPCON_L Position */ #define SCT_CAPCTRL7_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCON_L_Pos) /*!< SCT CAPCTRL7: CAPCON_L Mask */ #define SCT_CAPCTRL7_CAPCON_H_Pos 16 /*!< SCT CAPCTRL7: CAPCON_H Position */ #define SCT_CAPCTRL7_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL7_CAPCON_H_Pos) /*!< SCT CAPCTRL7: CAPCON_H Mask */ /* -------------------------------- SCT_CAPCTRL8 -------------------------------- */ #define SCT_CAPCTRL8_CAPCON_L_Pos 0 /*!< SCT CAPCTRL8: CAPCON_L Position */ #define SCT_CAPCTRL8_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCON_L_Pos) /*!< SCT CAPCTRL8: CAPCON_L Mask */ #define SCT_CAPCTRL8_CAPCON_H_Pos 16 /*!< SCT CAPCTRL8: CAPCON_H Position */ #define SCT_CAPCTRL8_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL8_CAPCON_H_Pos) /*!< SCT CAPCTRL8: CAPCON_H Mask */ /* -------------------------------- SCT_MATCHREL8 ------------------------------- */ #define SCT_MATCHREL8_RELOAD_L_Pos 0 /*!< SCT MATCHREL8: RELOAD_L Position */ #define SCT_MATCHREL8_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOAD_L_Pos) /*!< SCT MATCHREL8: RELOAD_L Mask */ #define SCT_MATCHREL8_RELOAD_H_Pos 16 /*!< SCT MATCHREL8: RELOAD_H Position */ #define SCT_MATCHREL8_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL8_RELOAD_H_Pos) /*!< SCT MATCHREL8: RELOAD_H Mask */ /* -------------------------------- SCT_MATCHREL9 ------------------------------- */ #define SCT_MATCHREL9_RELOAD_L_Pos 0 /*!< SCT MATCHREL9: RELOAD_L Position */ #define SCT_MATCHREL9_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOAD_L_Pos) /*!< SCT MATCHREL9: RELOAD_L Mask */ #define SCT_MATCHREL9_RELOAD_H_Pos 16 /*!< SCT MATCHREL9: RELOAD_H Position */ #define SCT_MATCHREL9_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL9_RELOAD_H_Pos) /*!< SCT MATCHREL9: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL9 -------------------------------- */ #define SCT_CAPCTRL9_CAPCON_L_Pos 0 /*!< SCT CAPCTRL9: CAPCON_L Position */ #define SCT_CAPCTRL9_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCON_L_Pos) /*!< SCT CAPCTRL9: CAPCON_L Mask */ #define SCT_CAPCTRL9_CAPCON_H_Pos 16 /*!< SCT CAPCTRL9: CAPCON_H Position */ #define SCT_CAPCTRL9_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL9_CAPCON_H_Pos) /*!< SCT CAPCTRL9: CAPCON_H Mask */ /* -------------------------------- SCT_CAPCTRL10 ------------------------------- */ #define SCT_CAPCTRL10_CAPCON_L_Pos 0 /*!< SCT CAPCTRL10: CAPCON_L Position */ #define SCT_CAPCTRL10_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCON_L_Pos) /*!< SCT CAPCTRL10: CAPCON_L Mask */ #define SCT_CAPCTRL10_CAPCON_H_Pos 16 /*!< SCT CAPCTRL10: CAPCON_H Position */ #define SCT_CAPCTRL10_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL10_CAPCON_H_Pos) /*!< SCT CAPCTRL10: CAPCON_H Mask */ /* ------------------------------- SCT_MATCHREL10 ------------------------------- */ #define SCT_MATCHREL10_RELOAD_L_Pos 0 /*!< SCT MATCHREL10: RELOAD_L Position */ #define SCT_MATCHREL10_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOAD_L_Pos) /*!< SCT MATCHREL10: RELOAD_L Mask */ #define SCT_MATCHREL10_RELOAD_H_Pos 16 /*!< SCT MATCHREL10: RELOAD_H Position */ #define SCT_MATCHREL10_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL10_RELOAD_H_Pos) /*!< SCT MATCHREL10: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL11 ------------------------------- */ #define SCT_CAPCTRL11_CAPCON_L_Pos 0 /*!< SCT CAPCTRL11: CAPCON_L Position */ #define SCT_CAPCTRL11_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCON_L_Pos) /*!< SCT CAPCTRL11: CAPCON_L Mask */ #define SCT_CAPCTRL11_CAPCON_H_Pos 16 /*!< SCT CAPCTRL11: CAPCON_H Position */ #define SCT_CAPCTRL11_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL11_CAPCON_H_Pos) /*!< SCT CAPCTRL11: CAPCON_H Mask */ /* ------------------------------- SCT_MATCHREL11 ------------------------------- */ #define SCT_MATCHREL11_RELOAD_L_Pos 0 /*!< SCT MATCHREL11: RELOAD_L Position */ #define SCT_MATCHREL11_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOAD_L_Pos) /*!< SCT MATCHREL11: RELOAD_L Mask */ #define SCT_MATCHREL11_RELOAD_H_Pos 16 /*!< SCT MATCHREL11: RELOAD_H Position */ #define SCT_MATCHREL11_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL11_RELOAD_H_Pos) /*!< SCT MATCHREL11: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL12 ------------------------------- */ #define SCT_CAPCTRL12_CAPCON_L_Pos 0 /*!< SCT CAPCTRL12: CAPCON_L Position */ #define SCT_CAPCTRL12_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCON_L_Pos) /*!< SCT CAPCTRL12: CAPCON_L Mask */ #define SCT_CAPCTRL12_CAPCON_H_Pos 16 /*!< SCT CAPCTRL12: CAPCON_H Position */ #define SCT_CAPCTRL12_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL12_CAPCON_H_Pos) /*!< SCT CAPCTRL12: CAPCON_H Mask */ /* ------------------------------- SCT_MATCHREL12 ------------------------------- */ #define SCT_MATCHREL12_RELOAD_L_Pos 0 /*!< SCT MATCHREL12: RELOAD_L Position */ #define SCT_MATCHREL12_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOAD_L_Pos) /*!< SCT MATCHREL12: RELOAD_L Mask */ #define SCT_MATCHREL12_RELOAD_H_Pos 16 /*!< SCT MATCHREL12: RELOAD_H Position */ #define SCT_MATCHREL12_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL12_RELOAD_H_Pos) /*!< SCT MATCHREL12: RELOAD_H Mask */ /* ------------------------------- SCT_MATCHREL13 ------------------------------- */ #define SCT_MATCHREL13_RELOAD_L_Pos 0 /*!< SCT MATCHREL13: RELOAD_L Position */ #define SCT_MATCHREL13_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOAD_L_Pos) /*!< SCT MATCHREL13: RELOAD_L Mask */ #define SCT_MATCHREL13_RELOAD_H_Pos 16 /*!< SCT MATCHREL13: RELOAD_H Position */ #define SCT_MATCHREL13_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL13_RELOAD_H_Pos) /*!< SCT MATCHREL13: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL13 ------------------------------- */ #define SCT_CAPCTRL13_CAPCON_L_Pos 0 /*!< SCT CAPCTRL13: CAPCON_L Position */ #define SCT_CAPCTRL13_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCON_L_Pos) /*!< SCT CAPCTRL13: CAPCON_L Mask */ #define SCT_CAPCTRL13_CAPCON_H_Pos 16 /*!< SCT CAPCTRL13: CAPCON_H Position */ #define SCT_CAPCTRL13_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL13_CAPCON_H_Pos) /*!< SCT CAPCTRL13: CAPCON_H Mask */ /* ------------------------------- SCT_MATCHREL14 ------------------------------- */ #define SCT_MATCHREL14_RELOAD_L_Pos 0 /*!< SCT MATCHREL14: RELOAD_L Position */ #define SCT_MATCHREL14_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOAD_L_Pos) /*!< SCT MATCHREL14: RELOAD_L Mask */ #define SCT_MATCHREL14_RELOAD_H_Pos 16 /*!< SCT MATCHREL14: RELOAD_H Position */ #define SCT_MATCHREL14_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL14_RELOAD_H_Pos) /*!< SCT MATCHREL14: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL14 ------------------------------- */ #define SCT_CAPCTRL14_CAPCON_L_Pos 0 /*!< SCT CAPCTRL14: CAPCON_L Position */ #define SCT_CAPCTRL14_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCON_L_Pos) /*!< SCT CAPCTRL14: CAPCON_L Mask */ #define SCT_CAPCTRL14_CAPCON_H_Pos 16 /*!< SCT CAPCTRL14: CAPCON_H Position */ #define SCT_CAPCTRL14_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL14_CAPCON_H_Pos) /*!< SCT CAPCTRL14: CAPCON_H Mask */ /* ------------------------------- SCT_MATCHREL15 ------------------------------- */ #define SCT_MATCHREL15_RELOAD_L_Pos 0 /*!< SCT MATCHREL15: RELOAD_L Position */ #define SCT_MATCHREL15_RELOAD_L_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOAD_L_Pos) /*!< SCT MATCHREL15: RELOAD_L Mask */ #define SCT_MATCHREL15_RELOAD_H_Pos 16 /*!< SCT MATCHREL15: RELOAD_H Position */ #define SCT_MATCHREL15_RELOAD_H_Msk (0x0000ffffUL << SCT_MATCHREL15_RELOAD_H_Pos) /*!< SCT MATCHREL15: RELOAD_H Mask */ /* -------------------------------- SCT_CAPCTRL15 ------------------------------- */ #define SCT_CAPCTRL15_CAPCON_L_Pos 0 /*!< SCT CAPCTRL15: CAPCON_L Position */ #define SCT_CAPCTRL15_CAPCON_L_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCON_L_Pos) /*!< SCT CAPCTRL15: CAPCON_L Mask */ #define SCT_CAPCTRL15_CAPCON_H_Pos 16 /*!< SCT CAPCTRL15: CAPCON_H Position */ #define SCT_CAPCTRL15_CAPCON_H_Msk (0x0000ffffUL << SCT_CAPCTRL15_CAPCON_H_Pos) /*!< SCT CAPCTRL15: CAPCON_H Mask */ /* ------------------------------- SCT_FRACMATREL0 ------------------------------ */ #define SCT_FRACMATREL0_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL0: RELFRAC_L Position */ #define SCT_FRACMATREL0_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL0_RELFRAC_L_Pos) /*!< SCT FRACMATREL0: RELFRAC_L Mask */ #define SCT_FRACMATREL0_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL0: RELFRAC_H Position */ #define SCT_FRACMATREL0_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL0_RELFRAC_H_Pos) /*!< SCT FRACMATREL0: RELFRAC_H Mask */ /* ------------------------------- SCT_FRACMATREL1 ------------------------------ */ #define SCT_FRACMATREL1_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL1: RELFRAC_L Position */ #define SCT_FRACMATREL1_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL1_RELFRAC_L_Pos) /*!< SCT FRACMATREL1: RELFRAC_L Mask */ #define SCT_FRACMATREL1_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL1: RELFRAC_H Position */ #define SCT_FRACMATREL1_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL1_RELFRAC_H_Pos) /*!< SCT FRACMATREL1: RELFRAC_H Mask */ /* ------------------------------- SCT_FRACMATREL2 ------------------------------ */ #define SCT_FRACMATREL2_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL2: RELFRAC_L Position */ #define SCT_FRACMATREL2_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL2_RELFRAC_L_Pos) /*!< SCT FRACMATREL2: RELFRAC_L Mask */ #define SCT_FRACMATREL2_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL2: RELFRAC_H Position */ #define SCT_FRACMATREL2_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL2_RELFRAC_H_Pos) /*!< SCT FRACMATREL2: RELFRAC_H Mask */ /* ------------------------------- SCT_FRACMATREL3 ------------------------------ */ #define SCT_FRACMATREL3_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL3: RELFRAC_L Position */ #define SCT_FRACMATREL3_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL3_RELFRAC_L_Pos) /*!< SCT FRACMATREL3: RELFRAC_L Mask */ #define SCT_FRACMATREL3_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL3: RELFRAC_H Position */ #define SCT_FRACMATREL3_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL3_RELFRAC_H_Pos) /*!< SCT FRACMATREL3: RELFRAC_H Mask */ /* ------------------------------- SCT_FRACMATREL4 ------------------------------ */ #define SCT_FRACMATREL4_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL4: RELFRAC_L Position */ #define SCT_FRACMATREL4_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL4_RELFRAC_L_Pos) /*!< SCT FRACMATREL4: RELFRAC_L Mask */ #define SCT_FRACMATREL4_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL4: RELFRAC_H Position */ #define SCT_FRACMATREL4_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL4_RELFRAC_H_Pos) /*!< SCT FRACMATREL4: RELFRAC_H Mask */ /* ------------------------------- SCT_FRACMATREL5 ------------------------------ */ #define SCT_FRACMATREL5_RELFRAC_L_Pos 0 /*!< SCT FRACMATREL5: RELFRAC_L Position */ #define SCT_FRACMATREL5_RELFRAC_L_Msk (0x0fUL << SCT_FRACMATREL5_RELFRAC_L_Pos) /*!< SCT FRACMATREL5: RELFRAC_L Mask */ #define SCT_FRACMATREL5_RELFRAC_H_Pos 16 /*!< SCT FRACMATREL5: RELFRAC_H Position */ #define SCT_FRACMATREL5_RELFRAC_H_Msk (0x0fUL << SCT_FRACMATREL5_RELFRAC_H_Pos) /*!< SCT FRACMATREL5: RELFRAC_H Mask */ /* -------------------------------- SCT_EV0_STATE ------------------------------- */ #define SCT_EV0_STATE_STATEMSK0_Pos 0 /*!< SCT EV0_STATE: STATEMSK0 Position */ #define SCT_EV0_STATE_STATEMSK0_Msk (0x01UL << SCT_EV0_STATE_STATEMSK0_Pos) /*!< SCT EV0_STATE: STATEMSK0 Mask */ #define SCT_EV0_STATE_STATEMSK1_Pos 1 /*!< SCT EV0_STATE: STATEMSK1 Position */ #define SCT_EV0_STATE_STATEMSK1_Msk (0x01UL << SCT_EV0_STATE_STATEMSK1_Pos) /*!< SCT EV0_STATE: STATEMSK1 Mask */ #define SCT_EV0_STATE_STATEMSK2_Pos 2 /*!< SCT EV0_STATE: STATEMSK2 Position */ #define SCT_EV0_STATE_STATEMSK2_Msk (0x01UL << SCT_EV0_STATE_STATEMSK2_Pos) /*!< SCT EV0_STATE: STATEMSK2 Mask */ #define SCT_EV0_STATE_STATEMSK3_Pos 3 /*!< SCT EV0_STATE: STATEMSK3 Position */ #define SCT_EV0_STATE_STATEMSK3_Msk (0x01UL << SCT_EV0_STATE_STATEMSK3_Pos) /*!< SCT EV0_STATE: STATEMSK3 Mask */ #define SCT_EV0_STATE_STATEMSK4_Pos 4 /*!< SCT EV0_STATE: STATEMSK4 Position */ #define SCT_EV0_STATE_STATEMSK4_Msk (0x01UL << SCT_EV0_STATE_STATEMSK4_Pos) /*!< SCT EV0_STATE: STATEMSK4 Mask */ #define SCT_EV0_STATE_STATEMSK5_Pos 5 /*!< SCT EV0_STATE: STATEMSK5 Position */ #define SCT_EV0_STATE_STATEMSK5_Msk (0x01UL << SCT_EV0_STATE_STATEMSK5_Pos) /*!< SCT EV0_STATE: STATEMSK5 Mask */ #define SCT_EV0_STATE_STATEMSK6_Pos 6 /*!< SCT EV0_STATE: STATEMSK6 Position */ #define SCT_EV0_STATE_STATEMSK6_Msk (0x01UL << SCT_EV0_STATE_STATEMSK6_Pos) /*!< SCT EV0_STATE: STATEMSK6 Mask */ #define SCT_EV0_STATE_STATEMSK7_Pos 7 /*!< SCT EV0_STATE: STATEMSK7 Position */ #define SCT_EV0_STATE_STATEMSK7_Msk (0x01UL << SCT_EV0_STATE_STATEMSK7_Pos) /*!< SCT EV0_STATE: STATEMSK7 Mask */ #define SCT_EV0_STATE_STATEMSK8_Pos 8 /*!< SCT EV0_STATE: STATEMSK8 Position */ #define SCT_EV0_STATE_STATEMSK8_Msk (0x01UL << SCT_EV0_STATE_STATEMSK8_Pos) /*!< SCT EV0_STATE: STATEMSK8 Mask */ #define SCT_EV0_STATE_STATEMSK9_Pos 9 /*!< SCT EV0_STATE: STATEMSK9 Position */ #define SCT_EV0_STATE_STATEMSK9_Msk (0x01UL << SCT_EV0_STATE_STATEMSK9_Pos) /*!< SCT EV0_STATE: STATEMSK9 Mask */ #define SCT_EV0_STATE_STATEMSK10_Pos 10 /*!< SCT EV0_STATE: STATEMSK10 Position */ #define SCT_EV0_STATE_STATEMSK10_Msk (0x01UL << SCT_EV0_STATE_STATEMSK10_Pos) /*!< SCT EV0_STATE: STATEMSK10 Mask */ #define SCT_EV0_STATE_STATEMSK11_Pos 11 /*!< SCT EV0_STATE: STATEMSK11 Position */ #define SCT_EV0_STATE_STATEMSK11_Msk (0x01UL << SCT_EV0_STATE_STATEMSK11_Pos) /*!< SCT EV0_STATE: STATEMSK11 Mask */ #define SCT_EV0_STATE_STATEMSK12_Pos 12 /*!< SCT EV0_STATE: STATEMSK12 Position */ #define SCT_EV0_STATE_STATEMSK12_Msk (0x01UL << SCT_EV0_STATE_STATEMSK12_Pos) /*!< SCT EV0_STATE: STATEMSK12 Mask */ #define SCT_EV0_STATE_STATEMSK13_Pos 13 /*!< SCT EV0_STATE: STATEMSK13 Position */ #define SCT_EV0_STATE_STATEMSK13_Msk (0x01UL << SCT_EV0_STATE_STATEMSK13_Pos) /*!< SCT EV0_STATE: STATEMSK13 Mask */ #define SCT_EV0_STATE_STATEMSK14_Pos 14 /*!< SCT EV0_STATE: STATEMSK14 Position */ #define SCT_EV0_STATE_STATEMSK14_Msk (0x01UL << SCT_EV0_STATE_STATEMSK14_Pos) /*!< SCT EV0_STATE: STATEMSK14 Mask */ #define SCT_EV0_STATE_STATEMSK15_Pos 15 /*!< SCT EV0_STATE: STATEMSK15 Position */ #define SCT_EV0_STATE_STATEMSK15_Msk (0x01UL << SCT_EV0_STATE_STATEMSK15_Pos) /*!< SCT EV0_STATE: STATEMSK15 Mask */ #define SCT_EV0_STATE_STATEMSK16_Pos 16 /*!< SCT EV0_STATE: STATEMSK16 Position */ #define SCT_EV0_STATE_STATEMSK16_Msk (0x01UL << SCT_EV0_STATE_STATEMSK16_Pos) /*!< SCT EV0_STATE: STATEMSK16 Mask */ #define SCT_EV0_STATE_STATEMSK17_Pos 17 /*!< SCT EV0_STATE: STATEMSK17 Position */ #define SCT_EV0_STATE_STATEMSK17_Msk (0x01UL << SCT_EV0_STATE_STATEMSK17_Pos) /*!< SCT EV0_STATE: STATEMSK17 Mask */ #define SCT_EV0_STATE_STATEMSK18_Pos 18 /*!< SCT EV0_STATE: STATEMSK18 Position */ #define SCT_EV0_STATE_STATEMSK18_Msk (0x01UL << SCT_EV0_STATE_STATEMSK18_Pos) /*!< SCT EV0_STATE: STATEMSK18 Mask */ #define SCT_EV0_STATE_STATEMSK19_Pos 19 /*!< SCT EV0_STATE: STATEMSK19 Position */ #define SCT_EV0_STATE_STATEMSK19_Msk (0x01UL << SCT_EV0_STATE_STATEMSK19_Pos) /*!< SCT EV0_STATE: STATEMSK19 Mask */ #define SCT_EV0_STATE_STATEMSK20_Pos 20 /*!< SCT EV0_STATE: STATEMSK20 Position */ #define SCT_EV0_STATE_STATEMSK20_Msk (0x01UL << SCT_EV0_STATE_STATEMSK20_Pos) /*!< SCT EV0_STATE: STATEMSK20 Mask */ #define SCT_EV0_STATE_STATEMSK21_Pos 21 /*!< SCT EV0_STATE: STATEMSK21 Position */ #define SCT_EV0_STATE_STATEMSK21_Msk (0x01UL << SCT_EV0_STATE_STATEMSK21_Pos) /*!< SCT EV0_STATE: STATEMSK21 Mask */ #define SCT_EV0_STATE_STATEMSK22_Pos 22 /*!< SCT EV0_STATE: STATEMSK22 Position */ #define SCT_EV0_STATE_STATEMSK22_Msk (0x01UL << SCT_EV0_STATE_STATEMSK22_Pos) /*!< SCT EV0_STATE: STATEMSK22 Mask */ #define SCT_EV0_STATE_STATEMSK23_Pos 23 /*!< SCT EV0_STATE: STATEMSK23 Position */ #define SCT_EV0_STATE_STATEMSK23_Msk (0x01UL << SCT_EV0_STATE_STATEMSK23_Pos) /*!< SCT EV0_STATE: STATEMSK23 Mask */ #define SCT_EV0_STATE_STATEMSK24_Pos 24 /*!< SCT EV0_STATE: STATEMSK24 Position */ #define SCT_EV0_STATE_STATEMSK24_Msk (0x01UL << SCT_EV0_STATE_STATEMSK24_Pos) /*!< SCT EV0_STATE: STATEMSK24 Mask */ #define SCT_EV0_STATE_STATEMSK25_Pos 25 /*!< SCT EV0_STATE: STATEMSK25 Position */ #define SCT_EV0_STATE_STATEMSK25_Msk (0x01UL << SCT_EV0_STATE_STATEMSK25_Pos) /*!< SCT EV0_STATE: STATEMSK25 Mask */ #define SCT_EV0_STATE_STATEMSK26_Pos 26 /*!< SCT EV0_STATE: STATEMSK26 Position */ #define SCT_EV0_STATE_STATEMSK26_Msk (0x01UL << SCT_EV0_STATE_STATEMSK26_Pos) /*!< SCT EV0_STATE: STATEMSK26 Mask */ #define SCT_EV0_STATE_STATEMSK27_Pos 27 /*!< SCT EV0_STATE: STATEMSK27 Position */ #define SCT_EV0_STATE_STATEMSK27_Msk (0x01UL << SCT_EV0_STATE_STATEMSK27_Pos) /*!< SCT EV0_STATE: STATEMSK27 Mask */ #define SCT_EV0_STATE_STATEMSK28_Pos 28 /*!< SCT EV0_STATE: STATEMSK28 Position */ #define SCT_EV0_STATE_STATEMSK28_Msk (0x01UL << SCT_EV0_STATE_STATEMSK28_Pos) /*!< SCT EV0_STATE: STATEMSK28 Mask */ #define SCT_EV0_STATE_STATEMSK29_Pos 29 /*!< SCT EV0_STATE: STATEMSK29 Position */ #define SCT_EV0_STATE_STATEMSK29_Msk (0x01UL << SCT_EV0_STATE_STATEMSK29_Pos) /*!< SCT EV0_STATE: STATEMSK29 Mask */ #define SCT_EV0_STATE_STATEMSK30_Pos 30 /*!< SCT EV0_STATE: STATEMSK30 Position */ #define SCT_EV0_STATE_STATEMSK30_Msk (0x01UL << SCT_EV0_STATE_STATEMSK30_Pos) /*!< SCT EV0_STATE: STATEMSK30 Mask */ #define SCT_EV0_STATE_STATEMSK31_Pos 31 /*!< SCT EV0_STATE: STATEMSK31 Position */ #define SCT_EV0_STATE_STATEMSK31_Msk (0x01UL << SCT_EV0_STATE_STATEMSK31_Pos) /*!< SCT EV0_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV0_CTRL -------------------------------- */ #define SCT_EV0_CTRL_MATCHSEL_Pos 0 /*!< SCT EV0_CTRL: MATCHSEL Position */ #define SCT_EV0_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV0_CTRL_MATCHSEL_Pos) /*!< SCT EV0_CTRL: MATCHSEL Mask */ #define SCT_EV0_CTRL_HEVENT_Pos 4 /*!< SCT EV0_CTRL: HEVENT Position */ #define SCT_EV0_CTRL_HEVENT_Msk (0x01UL << SCT_EV0_CTRL_HEVENT_Pos) /*!< SCT EV0_CTRL: HEVENT Mask */ #define SCT_EV0_CTRL_OUTSEL_Pos 5 /*!< SCT EV0_CTRL: OUTSEL Position */ #define SCT_EV0_CTRL_OUTSEL_Msk (0x01UL << SCT_EV0_CTRL_OUTSEL_Pos) /*!< SCT EV0_CTRL: OUTSEL Mask */ #define SCT_EV0_CTRL_IOSEL_Pos 6 /*!< SCT EV0_CTRL: IOSEL Position */ #define SCT_EV0_CTRL_IOSEL_Msk (0x0fUL << SCT_EV0_CTRL_IOSEL_Pos) /*!< SCT EV0_CTRL: IOSEL Mask */ #define SCT_EV0_CTRL_IOCOND_Pos 10 /*!< SCT EV0_CTRL: IOCOND Position */ #define SCT_EV0_CTRL_IOCOND_Msk (0x03UL << SCT_EV0_CTRL_IOCOND_Pos) /*!< SCT EV0_CTRL: IOCOND Mask */ #define SCT_EV0_CTRL_COMBMODE_Pos 12 /*!< SCT EV0_CTRL: COMBMODE Position */ #define SCT_EV0_CTRL_COMBMODE_Msk (0x03UL << SCT_EV0_CTRL_COMBMODE_Pos) /*!< SCT EV0_CTRL: COMBMODE Mask */ #define SCT_EV0_CTRL_STATELD_Pos 14 /*!< SCT EV0_CTRL: STATELD Position */ #define SCT_EV0_CTRL_STATELD_Msk (0x01UL << SCT_EV0_CTRL_STATELD_Pos) /*!< SCT EV0_CTRL: STATELD Mask */ #define SCT_EV0_CTRL_STATEV_Pos 15 /*!< SCT EV0_CTRL: STATEV Position */ #define SCT_EV0_CTRL_STATEV_Msk (0x1fUL << SCT_EV0_CTRL_STATEV_Pos) /*!< SCT EV0_CTRL: STATEV Mask */ #define SCT_EV0_CTRL_MATCHMEM_Pos 20 /*!< SCT EV0_CTRL: MATCHMEM Position */ #define SCT_EV0_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV0_CTRL_MATCHMEM_Pos) /*!< SCT EV0_CTRL: MATCHMEM Mask */ #define SCT_EV0_CTRL_DIRECTION_Pos 21 /*!< SCT EV0_CTRL: DIRECTION Position */ #define SCT_EV0_CTRL_DIRECTION_Msk (0x03UL << SCT_EV0_CTRL_DIRECTION_Pos) /*!< SCT EV0_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV1_STATE ------------------------------- */ #define SCT_EV1_STATE_STATEMSK0_Pos 0 /*!< SCT EV1_STATE: STATEMSK0 Position */ #define SCT_EV1_STATE_STATEMSK0_Msk (0x01UL << SCT_EV1_STATE_STATEMSK0_Pos) /*!< SCT EV1_STATE: STATEMSK0 Mask */ #define SCT_EV1_STATE_STATEMSK1_Pos 1 /*!< SCT EV1_STATE: STATEMSK1 Position */ #define SCT_EV1_STATE_STATEMSK1_Msk (0x01UL << SCT_EV1_STATE_STATEMSK1_Pos) /*!< SCT EV1_STATE: STATEMSK1 Mask */ #define SCT_EV1_STATE_STATEMSK2_Pos 2 /*!< SCT EV1_STATE: STATEMSK2 Position */ #define SCT_EV1_STATE_STATEMSK2_Msk (0x01UL << SCT_EV1_STATE_STATEMSK2_Pos) /*!< SCT EV1_STATE: STATEMSK2 Mask */ #define SCT_EV1_STATE_STATEMSK3_Pos 3 /*!< SCT EV1_STATE: STATEMSK3 Position */ #define SCT_EV1_STATE_STATEMSK3_Msk (0x01UL << SCT_EV1_STATE_STATEMSK3_Pos) /*!< SCT EV1_STATE: STATEMSK3 Mask */ #define SCT_EV1_STATE_STATEMSK4_Pos 4 /*!< SCT EV1_STATE: STATEMSK4 Position */ #define SCT_EV1_STATE_STATEMSK4_Msk (0x01UL << SCT_EV1_STATE_STATEMSK4_Pos) /*!< SCT EV1_STATE: STATEMSK4 Mask */ #define SCT_EV1_STATE_STATEMSK5_Pos 5 /*!< SCT EV1_STATE: STATEMSK5 Position */ #define SCT_EV1_STATE_STATEMSK5_Msk (0x01UL << SCT_EV1_STATE_STATEMSK5_Pos) /*!< SCT EV1_STATE: STATEMSK5 Mask */ #define SCT_EV1_STATE_STATEMSK6_Pos 6 /*!< SCT EV1_STATE: STATEMSK6 Position */ #define SCT_EV1_STATE_STATEMSK6_Msk (0x01UL << SCT_EV1_STATE_STATEMSK6_Pos) /*!< SCT EV1_STATE: STATEMSK6 Mask */ #define SCT_EV1_STATE_STATEMSK7_Pos 7 /*!< SCT EV1_STATE: STATEMSK7 Position */ #define SCT_EV1_STATE_STATEMSK7_Msk (0x01UL << SCT_EV1_STATE_STATEMSK7_Pos) /*!< SCT EV1_STATE: STATEMSK7 Mask */ #define SCT_EV1_STATE_STATEMSK8_Pos 8 /*!< SCT EV1_STATE: STATEMSK8 Position */ #define SCT_EV1_STATE_STATEMSK8_Msk (0x01UL << SCT_EV1_STATE_STATEMSK8_Pos) /*!< SCT EV1_STATE: STATEMSK8 Mask */ #define SCT_EV1_STATE_STATEMSK9_Pos 9 /*!< SCT EV1_STATE: STATEMSK9 Position */ #define SCT_EV1_STATE_STATEMSK9_Msk (0x01UL << SCT_EV1_STATE_STATEMSK9_Pos) /*!< SCT EV1_STATE: STATEMSK9 Mask */ #define SCT_EV1_STATE_STATEMSK10_Pos 10 /*!< SCT EV1_STATE: STATEMSK10 Position */ #define SCT_EV1_STATE_STATEMSK10_Msk (0x01UL << SCT_EV1_STATE_STATEMSK10_Pos) /*!< SCT EV1_STATE: STATEMSK10 Mask */ #define SCT_EV1_STATE_STATEMSK11_Pos 11 /*!< SCT EV1_STATE: STATEMSK11 Position */ #define SCT_EV1_STATE_STATEMSK11_Msk (0x01UL << SCT_EV1_STATE_STATEMSK11_Pos) /*!< SCT EV1_STATE: STATEMSK11 Mask */ #define SCT_EV1_STATE_STATEMSK12_Pos 12 /*!< SCT EV1_STATE: STATEMSK12 Position */ #define SCT_EV1_STATE_STATEMSK12_Msk (0x01UL << SCT_EV1_STATE_STATEMSK12_Pos) /*!< SCT EV1_STATE: STATEMSK12 Mask */ #define SCT_EV1_STATE_STATEMSK13_Pos 13 /*!< SCT EV1_STATE: STATEMSK13 Position */ #define SCT_EV1_STATE_STATEMSK13_Msk (0x01UL << SCT_EV1_STATE_STATEMSK13_Pos) /*!< SCT EV1_STATE: STATEMSK13 Mask */ #define SCT_EV1_STATE_STATEMSK14_Pos 14 /*!< SCT EV1_STATE: STATEMSK14 Position */ #define SCT_EV1_STATE_STATEMSK14_Msk (0x01UL << SCT_EV1_STATE_STATEMSK14_Pos) /*!< SCT EV1_STATE: STATEMSK14 Mask */ #define SCT_EV1_STATE_STATEMSK15_Pos 15 /*!< SCT EV1_STATE: STATEMSK15 Position */ #define SCT_EV1_STATE_STATEMSK15_Msk (0x01UL << SCT_EV1_STATE_STATEMSK15_Pos) /*!< SCT EV1_STATE: STATEMSK15 Mask */ #define SCT_EV1_STATE_STATEMSK16_Pos 16 /*!< SCT EV1_STATE: STATEMSK16 Position */ #define SCT_EV1_STATE_STATEMSK16_Msk (0x01UL << SCT_EV1_STATE_STATEMSK16_Pos) /*!< SCT EV1_STATE: STATEMSK16 Mask */ #define SCT_EV1_STATE_STATEMSK17_Pos 17 /*!< SCT EV1_STATE: STATEMSK17 Position */ #define SCT_EV1_STATE_STATEMSK17_Msk (0x01UL << SCT_EV1_STATE_STATEMSK17_Pos) /*!< SCT EV1_STATE: STATEMSK17 Mask */ #define SCT_EV1_STATE_STATEMSK18_Pos 18 /*!< SCT EV1_STATE: STATEMSK18 Position */ #define SCT_EV1_STATE_STATEMSK18_Msk (0x01UL << SCT_EV1_STATE_STATEMSK18_Pos) /*!< SCT EV1_STATE: STATEMSK18 Mask */ #define SCT_EV1_STATE_STATEMSK19_Pos 19 /*!< SCT EV1_STATE: STATEMSK19 Position */ #define SCT_EV1_STATE_STATEMSK19_Msk (0x01UL << SCT_EV1_STATE_STATEMSK19_Pos) /*!< SCT EV1_STATE: STATEMSK19 Mask */ #define SCT_EV1_STATE_STATEMSK20_Pos 20 /*!< SCT EV1_STATE: STATEMSK20 Position */ #define SCT_EV1_STATE_STATEMSK20_Msk (0x01UL << SCT_EV1_STATE_STATEMSK20_Pos) /*!< SCT EV1_STATE: STATEMSK20 Mask */ #define SCT_EV1_STATE_STATEMSK21_Pos 21 /*!< SCT EV1_STATE: STATEMSK21 Position */ #define SCT_EV1_STATE_STATEMSK21_Msk (0x01UL << SCT_EV1_STATE_STATEMSK21_Pos) /*!< SCT EV1_STATE: STATEMSK21 Mask */ #define SCT_EV1_STATE_STATEMSK22_Pos 22 /*!< SCT EV1_STATE: STATEMSK22 Position */ #define SCT_EV1_STATE_STATEMSK22_Msk (0x01UL << SCT_EV1_STATE_STATEMSK22_Pos) /*!< SCT EV1_STATE: STATEMSK22 Mask */ #define SCT_EV1_STATE_STATEMSK23_Pos 23 /*!< SCT EV1_STATE: STATEMSK23 Position */ #define SCT_EV1_STATE_STATEMSK23_Msk (0x01UL << SCT_EV1_STATE_STATEMSK23_Pos) /*!< SCT EV1_STATE: STATEMSK23 Mask */ #define SCT_EV1_STATE_STATEMSK24_Pos 24 /*!< SCT EV1_STATE: STATEMSK24 Position */ #define SCT_EV1_STATE_STATEMSK24_Msk (0x01UL << SCT_EV1_STATE_STATEMSK24_Pos) /*!< SCT EV1_STATE: STATEMSK24 Mask */ #define SCT_EV1_STATE_STATEMSK25_Pos 25 /*!< SCT EV1_STATE: STATEMSK25 Position */ #define SCT_EV1_STATE_STATEMSK25_Msk (0x01UL << SCT_EV1_STATE_STATEMSK25_Pos) /*!< SCT EV1_STATE: STATEMSK25 Mask */ #define SCT_EV1_STATE_STATEMSK26_Pos 26 /*!< SCT EV1_STATE: STATEMSK26 Position */ #define SCT_EV1_STATE_STATEMSK26_Msk (0x01UL << SCT_EV1_STATE_STATEMSK26_Pos) /*!< SCT EV1_STATE: STATEMSK26 Mask */ #define SCT_EV1_STATE_STATEMSK27_Pos 27 /*!< SCT EV1_STATE: STATEMSK27 Position */ #define SCT_EV1_STATE_STATEMSK27_Msk (0x01UL << SCT_EV1_STATE_STATEMSK27_Pos) /*!< SCT EV1_STATE: STATEMSK27 Mask */ #define SCT_EV1_STATE_STATEMSK28_Pos 28 /*!< SCT EV1_STATE: STATEMSK28 Position */ #define SCT_EV1_STATE_STATEMSK28_Msk (0x01UL << SCT_EV1_STATE_STATEMSK28_Pos) /*!< SCT EV1_STATE: STATEMSK28 Mask */ #define SCT_EV1_STATE_STATEMSK29_Pos 29 /*!< SCT EV1_STATE: STATEMSK29 Position */ #define SCT_EV1_STATE_STATEMSK29_Msk (0x01UL << SCT_EV1_STATE_STATEMSK29_Pos) /*!< SCT EV1_STATE: STATEMSK29 Mask */ #define SCT_EV1_STATE_STATEMSK30_Pos 30 /*!< SCT EV1_STATE: STATEMSK30 Position */ #define SCT_EV1_STATE_STATEMSK30_Msk (0x01UL << SCT_EV1_STATE_STATEMSK30_Pos) /*!< SCT EV1_STATE: STATEMSK30 Mask */ #define SCT_EV1_STATE_STATEMSK31_Pos 31 /*!< SCT EV1_STATE: STATEMSK31 Position */ #define SCT_EV1_STATE_STATEMSK31_Msk (0x01UL << SCT_EV1_STATE_STATEMSK31_Pos) /*!< SCT EV1_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV1_CTRL -------------------------------- */ #define SCT_EV1_CTRL_MATCHSEL_Pos 0 /*!< SCT EV1_CTRL: MATCHSEL Position */ #define SCT_EV1_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV1_CTRL_MATCHSEL_Pos) /*!< SCT EV1_CTRL: MATCHSEL Mask */ #define SCT_EV1_CTRL_HEVENT_Pos 4 /*!< SCT EV1_CTRL: HEVENT Position */ #define SCT_EV1_CTRL_HEVENT_Msk (0x01UL << SCT_EV1_CTRL_HEVENT_Pos) /*!< SCT EV1_CTRL: HEVENT Mask */ #define SCT_EV1_CTRL_OUTSEL_Pos 5 /*!< SCT EV1_CTRL: OUTSEL Position */ #define SCT_EV1_CTRL_OUTSEL_Msk (0x01UL << SCT_EV1_CTRL_OUTSEL_Pos) /*!< SCT EV1_CTRL: OUTSEL Mask */ #define SCT_EV1_CTRL_IOSEL_Pos 6 /*!< SCT EV1_CTRL: IOSEL Position */ #define SCT_EV1_CTRL_IOSEL_Msk (0x0fUL << SCT_EV1_CTRL_IOSEL_Pos) /*!< SCT EV1_CTRL: IOSEL Mask */ #define SCT_EV1_CTRL_IOCOND_Pos 10 /*!< SCT EV1_CTRL: IOCOND Position */ #define SCT_EV1_CTRL_IOCOND_Msk (0x03UL << SCT_EV1_CTRL_IOCOND_Pos) /*!< SCT EV1_CTRL: IOCOND Mask */ #define SCT_EV1_CTRL_COMBMODE_Pos 12 /*!< SCT EV1_CTRL: COMBMODE Position */ #define SCT_EV1_CTRL_COMBMODE_Msk (0x03UL << SCT_EV1_CTRL_COMBMODE_Pos) /*!< SCT EV1_CTRL: COMBMODE Mask */ #define SCT_EV1_CTRL_STATELD_Pos 14 /*!< SCT EV1_CTRL: STATELD Position */ #define SCT_EV1_CTRL_STATELD_Msk (0x01UL << SCT_EV1_CTRL_STATELD_Pos) /*!< SCT EV1_CTRL: STATELD Mask */ #define SCT_EV1_CTRL_STATEV_Pos 15 /*!< SCT EV1_CTRL: STATEV Position */ #define SCT_EV1_CTRL_STATEV_Msk (0x1fUL << SCT_EV1_CTRL_STATEV_Pos) /*!< SCT EV1_CTRL: STATEV Mask */ #define SCT_EV1_CTRL_MATCHMEM_Pos 20 /*!< SCT EV1_CTRL: MATCHMEM Position */ #define SCT_EV1_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV1_CTRL_MATCHMEM_Pos) /*!< SCT EV1_CTRL: MATCHMEM Mask */ #define SCT_EV1_CTRL_DIRECTION_Pos 21 /*!< SCT EV1_CTRL: DIRECTION Position */ #define SCT_EV1_CTRL_DIRECTION_Msk (0x03UL << SCT_EV1_CTRL_DIRECTION_Pos) /*!< SCT EV1_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV2_STATE ------------------------------- */ #define SCT_EV2_STATE_STATEMSK0_Pos 0 /*!< SCT EV2_STATE: STATEMSK0 Position */ #define SCT_EV2_STATE_STATEMSK0_Msk (0x01UL << SCT_EV2_STATE_STATEMSK0_Pos) /*!< SCT EV2_STATE: STATEMSK0 Mask */ #define SCT_EV2_STATE_STATEMSK1_Pos 1 /*!< SCT EV2_STATE: STATEMSK1 Position */ #define SCT_EV2_STATE_STATEMSK1_Msk (0x01UL << SCT_EV2_STATE_STATEMSK1_Pos) /*!< SCT EV2_STATE: STATEMSK1 Mask */ #define SCT_EV2_STATE_STATEMSK2_Pos 2 /*!< SCT EV2_STATE: STATEMSK2 Position */ #define SCT_EV2_STATE_STATEMSK2_Msk (0x01UL << SCT_EV2_STATE_STATEMSK2_Pos) /*!< SCT EV2_STATE: STATEMSK2 Mask */ #define SCT_EV2_STATE_STATEMSK3_Pos 3 /*!< SCT EV2_STATE: STATEMSK3 Position */ #define SCT_EV2_STATE_STATEMSK3_Msk (0x01UL << SCT_EV2_STATE_STATEMSK3_Pos) /*!< SCT EV2_STATE: STATEMSK3 Mask */ #define SCT_EV2_STATE_STATEMSK4_Pos 4 /*!< SCT EV2_STATE: STATEMSK4 Position */ #define SCT_EV2_STATE_STATEMSK4_Msk (0x01UL << SCT_EV2_STATE_STATEMSK4_Pos) /*!< SCT EV2_STATE: STATEMSK4 Mask */ #define SCT_EV2_STATE_STATEMSK5_Pos 5 /*!< SCT EV2_STATE: STATEMSK5 Position */ #define SCT_EV2_STATE_STATEMSK5_Msk (0x01UL << SCT_EV2_STATE_STATEMSK5_Pos) /*!< SCT EV2_STATE: STATEMSK5 Mask */ #define SCT_EV2_STATE_STATEMSK6_Pos 6 /*!< SCT EV2_STATE: STATEMSK6 Position */ #define SCT_EV2_STATE_STATEMSK6_Msk (0x01UL << SCT_EV2_STATE_STATEMSK6_Pos) /*!< SCT EV2_STATE: STATEMSK6 Mask */ #define SCT_EV2_STATE_STATEMSK7_Pos 7 /*!< SCT EV2_STATE: STATEMSK7 Position */ #define SCT_EV2_STATE_STATEMSK7_Msk (0x01UL << SCT_EV2_STATE_STATEMSK7_Pos) /*!< SCT EV2_STATE: STATEMSK7 Mask */ #define SCT_EV2_STATE_STATEMSK8_Pos 8 /*!< SCT EV2_STATE: STATEMSK8 Position */ #define SCT_EV2_STATE_STATEMSK8_Msk (0x01UL << SCT_EV2_STATE_STATEMSK8_Pos) /*!< SCT EV2_STATE: STATEMSK8 Mask */ #define SCT_EV2_STATE_STATEMSK9_Pos 9 /*!< SCT EV2_STATE: STATEMSK9 Position */ #define SCT_EV2_STATE_STATEMSK9_Msk (0x01UL << SCT_EV2_STATE_STATEMSK9_Pos) /*!< SCT EV2_STATE: STATEMSK9 Mask */ #define SCT_EV2_STATE_STATEMSK10_Pos 10 /*!< SCT EV2_STATE: STATEMSK10 Position */ #define SCT_EV2_STATE_STATEMSK10_Msk (0x01UL << SCT_EV2_STATE_STATEMSK10_Pos) /*!< SCT EV2_STATE: STATEMSK10 Mask */ #define SCT_EV2_STATE_STATEMSK11_Pos 11 /*!< SCT EV2_STATE: STATEMSK11 Position */ #define SCT_EV2_STATE_STATEMSK11_Msk (0x01UL << SCT_EV2_STATE_STATEMSK11_Pos) /*!< SCT EV2_STATE: STATEMSK11 Mask */ #define SCT_EV2_STATE_STATEMSK12_Pos 12 /*!< SCT EV2_STATE: STATEMSK12 Position */ #define SCT_EV2_STATE_STATEMSK12_Msk (0x01UL << SCT_EV2_STATE_STATEMSK12_Pos) /*!< SCT EV2_STATE: STATEMSK12 Mask */ #define SCT_EV2_STATE_STATEMSK13_Pos 13 /*!< SCT EV2_STATE: STATEMSK13 Position */ #define SCT_EV2_STATE_STATEMSK13_Msk (0x01UL << SCT_EV2_STATE_STATEMSK13_Pos) /*!< SCT EV2_STATE: STATEMSK13 Mask */ #define SCT_EV2_STATE_STATEMSK14_Pos 14 /*!< SCT EV2_STATE: STATEMSK14 Position */ #define SCT_EV2_STATE_STATEMSK14_Msk (0x01UL << SCT_EV2_STATE_STATEMSK14_Pos) /*!< SCT EV2_STATE: STATEMSK14 Mask */ #define SCT_EV2_STATE_STATEMSK15_Pos 15 /*!< SCT EV2_STATE: STATEMSK15 Position */ #define SCT_EV2_STATE_STATEMSK15_Msk (0x01UL << SCT_EV2_STATE_STATEMSK15_Pos) /*!< SCT EV2_STATE: STATEMSK15 Mask */ #define SCT_EV2_STATE_STATEMSK16_Pos 16 /*!< SCT EV2_STATE: STATEMSK16 Position */ #define SCT_EV2_STATE_STATEMSK16_Msk (0x01UL << SCT_EV2_STATE_STATEMSK16_Pos) /*!< SCT EV2_STATE: STATEMSK16 Mask */ #define SCT_EV2_STATE_STATEMSK17_Pos 17 /*!< SCT EV2_STATE: STATEMSK17 Position */ #define SCT_EV2_STATE_STATEMSK17_Msk (0x01UL << SCT_EV2_STATE_STATEMSK17_Pos) /*!< SCT EV2_STATE: STATEMSK17 Mask */ #define SCT_EV2_STATE_STATEMSK18_Pos 18 /*!< SCT EV2_STATE: STATEMSK18 Position */ #define SCT_EV2_STATE_STATEMSK18_Msk (0x01UL << SCT_EV2_STATE_STATEMSK18_Pos) /*!< SCT EV2_STATE: STATEMSK18 Mask */ #define SCT_EV2_STATE_STATEMSK19_Pos 19 /*!< SCT EV2_STATE: STATEMSK19 Position */ #define SCT_EV2_STATE_STATEMSK19_Msk (0x01UL << SCT_EV2_STATE_STATEMSK19_Pos) /*!< SCT EV2_STATE: STATEMSK19 Mask */ #define SCT_EV2_STATE_STATEMSK20_Pos 20 /*!< SCT EV2_STATE: STATEMSK20 Position */ #define SCT_EV2_STATE_STATEMSK20_Msk (0x01UL << SCT_EV2_STATE_STATEMSK20_Pos) /*!< SCT EV2_STATE: STATEMSK20 Mask */ #define SCT_EV2_STATE_STATEMSK21_Pos 21 /*!< SCT EV2_STATE: STATEMSK21 Position */ #define SCT_EV2_STATE_STATEMSK21_Msk (0x01UL << SCT_EV2_STATE_STATEMSK21_Pos) /*!< SCT EV2_STATE: STATEMSK21 Mask */ #define SCT_EV2_STATE_STATEMSK22_Pos 22 /*!< SCT EV2_STATE: STATEMSK22 Position */ #define SCT_EV2_STATE_STATEMSK22_Msk (0x01UL << SCT_EV2_STATE_STATEMSK22_Pos) /*!< SCT EV2_STATE: STATEMSK22 Mask */ #define SCT_EV2_STATE_STATEMSK23_Pos 23 /*!< SCT EV2_STATE: STATEMSK23 Position */ #define SCT_EV2_STATE_STATEMSK23_Msk (0x01UL << SCT_EV2_STATE_STATEMSK23_Pos) /*!< SCT EV2_STATE: STATEMSK23 Mask */ #define SCT_EV2_STATE_STATEMSK24_Pos 24 /*!< SCT EV2_STATE: STATEMSK24 Position */ #define SCT_EV2_STATE_STATEMSK24_Msk (0x01UL << SCT_EV2_STATE_STATEMSK24_Pos) /*!< SCT EV2_STATE: STATEMSK24 Mask */ #define SCT_EV2_STATE_STATEMSK25_Pos 25 /*!< SCT EV2_STATE: STATEMSK25 Position */ #define SCT_EV2_STATE_STATEMSK25_Msk (0x01UL << SCT_EV2_STATE_STATEMSK25_Pos) /*!< SCT EV2_STATE: STATEMSK25 Mask */ #define SCT_EV2_STATE_STATEMSK26_Pos 26 /*!< SCT EV2_STATE: STATEMSK26 Position */ #define SCT_EV2_STATE_STATEMSK26_Msk (0x01UL << SCT_EV2_STATE_STATEMSK26_Pos) /*!< SCT EV2_STATE: STATEMSK26 Mask */ #define SCT_EV2_STATE_STATEMSK27_Pos 27 /*!< SCT EV2_STATE: STATEMSK27 Position */ #define SCT_EV2_STATE_STATEMSK27_Msk (0x01UL << SCT_EV2_STATE_STATEMSK27_Pos) /*!< SCT EV2_STATE: STATEMSK27 Mask */ #define SCT_EV2_STATE_STATEMSK28_Pos 28 /*!< SCT EV2_STATE: STATEMSK28 Position */ #define SCT_EV2_STATE_STATEMSK28_Msk (0x01UL << SCT_EV2_STATE_STATEMSK28_Pos) /*!< SCT EV2_STATE: STATEMSK28 Mask */ #define SCT_EV2_STATE_STATEMSK29_Pos 29 /*!< SCT EV2_STATE: STATEMSK29 Position */ #define SCT_EV2_STATE_STATEMSK29_Msk (0x01UL << SCT_EV2_STATE_STATEMSK29_Pos) /*!< SCT EV2_STATE: STATEMSK29 Mask */ #define SCT_EV2_STATE_STATEMSK30_Pos 30 /*!< SCT EV2_STATE: STATEMSK30 Position */ #define SCT_EV2_STATE_STATEMSK30_Msk (0x01UL << SCT_EV2_STATE_STATEMSK30_Pos) /*!< SCT EV2_STATE: STATEMSK30 Mask */ #define SCT_EV2_STATE_STATEMSK31_Pos 31 /*!< SCT EV2_STATE: STATEMSK31 Position */ #define SCT_EV2_STATE_STATEMSK31_Msk (0x01UL << SCT_EV2_STATE_STATEMSK31_Pos) /*!< SCT EV2_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV2_CTRL -------------------------------- */ #define SCT_EV2_CTRL_MATCHSEL_Pos 0 /*!< SCT EV2_CTRL: MATCHSEL Position */ #define SCT_EV2_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV2_CTRL_MATCHSEL_Pos) /*!< SCT EV2_CTRL: MATCHSEL Mask */ #define SCT_EV2_CTRL_HEVENT_Pos 4 /*!< SCT EV2_CTRL: HEVENT Position */ #define SCT_EV2_CTRL_HEVENT_Msk (0x01UL << SCT_EV2_CTRL_HEVENT_Pos) /*!< SCT EV2_CTRL: HEVENT Mask */ #define SCT_EV2_CTRL_OUTSEL_Pos 5 /*!< SCT EV2_CTRL: OUTSEL Position */ #define SCT_EV2_CTRL_OUTSEL_Msk (0x01UL << SCT_EV2_CTRL_OUTSEL_Pos) /*!< SCT EV2_CTRL: OUTSEL Mask */ #define SCT_EV2_CTRL_IOSEL_Pos 6 /*!< SCT EV2_CTRL: IOSEL Position */ #define SCT_EV2_CTRL_IOSEL_Msk (0x0fUL << SCT_EV2_CTRL_IOSEL_Pos) /*!< SCT EV2_CTRL: IOSEL Mask */ #define SCT_EV2_CTRL_IOCOND_Pos 10 /*!< SCT EV2_CTRL: IOCOND Position */ #define SCT_EV2_CTRL_IOCOND_Msk (0x03UL << SCT_EV2_CTRL_IOCOND_Pos) /*!< SCT EV2_CTRL: IOCOND Mask */ #define SCT_EV2_CTRL_COMBMODE_Pos 12 /*!< SCT EV2_CTRL: COMBMODE Position */ #define SCT_EV2_CTRL_COMBMODE_Msk (0x03UL << SCT_EV2_CTRL_COMBMODE_Pos) /*!< SCT EV2_CTRL: COMBMODE Mask */ #define SCT_EV2_CTRL_STATELD_Pos 14 /*!< SCT EV2_CTRL: STATELD Position */ #define SCT_EV2_CTRL_STATELD_Msk (0x01UL << SCT_EV2_CTRL_STATELD_Pos) /*!< SCT EV2_CTRL: STATELD Mask */ #define SCT_EV2_CTRL_STATEV_Pos 15 /*!< SCT EV2_CTRL: STATEV Position */ #define SCT_EV2_CTRL_STATEV_Msk (0x1fUL << SCT_EV2_CTRL_STATEV_Pos) /*!< SCT EV2_CTRL: STATEV Mask */ #define SCT_EV2_CTRL_MATCHMEM_Pos 20 /*!< SCT EV2_CTRL: MATCHMEM Position */ #define SCT_EV2_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV2_CTRL_MATCHMEM_Pos) /*!< SCT EV2_CTRL: MATCHMEM Mask */ #define SCT_EV2_CTRL_DIRECTION_Pos 21 /*!< SCT EV2_CTRL: DIRECTION Position */ #define SCT_EV2_CTRL_DIRECTION_Msk (0x03UL << SCT_EV2_CTRL_DIRECTION_Pos) /*!< SCT EV2_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV3_STATE ------------------------------- */ #define SCT_EV3_STATE_STATEMSK0_Pos 0 /*!< SCT EV3_STATE: STATEMSK0 Position */ #define SCT_EV3_STATE_STATEMSK0_Msk (0x01UL << SCT_EV3_STATE_STATEMSK0_Pos) /*!< SCT EV3_STATE: STATEMSK0 Mask */ #define SCT_EV3_STATE_STATEMSK1_Pos 1 /*!< SCT EV3_STATE: STATEMSK1 Position */ #define SCT_EV3_STATE_STATEMSK1_Msk (0x01UL << SCT_EV3_STATE_STATEMSK1_Pos) /*!< SCT EV3_STATE: STATEMSK1 Mask */ #define SCT_EV3_STATE_STATEMSK2_Pos 2 /*!< SCT EV3_STATE: STATEMSK2 Position */ #define SCT_EV3_STATE_STATEMSK2_Msk (0x01UL << SCT_EV3_STATE_STATEMSK2_Pos) /*!< SCT EV3_STATE: STATEMSK2 Mask */ #define SCT_EV3_STATE_STATEMSK3_Pos 3 /*!< SCT EV3_STATE: STATEMSK3 Position */ #define SCT_EV3_STATE_STATEMSK3_Msk (0x01UL << SCT_EV3_STATE_STATEMSK3_Pos) /*!< SCT EV3_STATE: STATEMSK3 Mask */ #define SCT_EV3_STATE_STATEMSK4_Pos 4 /*!< SCT EV3_STATE: STATEMSK4 Position */ #define SCT_EV3_STATE_STATEMSK4_Msk (0x01UL << SCT_EV3_STATE_STATEMSK4_Pos) /*!< SCT EV3_STATE: STATEMSK4 Mask */ #define SCT_EV3_STATE_STATEMSK5_Pos 5 /*!< SCT EV3_STATE: STATEMSK5 Position */ #define SCT_EV3_STATE_STATEMSK5_Msk (0x01UL << SCT_EV3_STATE_STATEMSK5_Pos) /*!< SCT EV3_STATE: STATEMSK5 Mask */ #define SCT_EV3_STATE_STATEMSK6_Pos 6 /*!< SCT EV3_STATE: STATEMSK6 Position */ #define SCT_EV3_STATE_STATEMSK6_Msk (0x01UL << SCT_EV3_STATE_STATEMSK6_Pos) /*!< SCT EV3_STATE: STATEMSK6 Mask */ #define SCT_EV3_STATE_STATEMSK7_Pos 7 /*!< SCT EV3_STATE: STATEMSK7 Position */ #define SCT_EV3_STATE_STATEMSK7_Msk (0x01UL << SCT_EV3_STATE_STATEMSK7_Pos) /*!< SCT EV3_STATE: STATEMSK7 Mask */ #define SCT_EV3_STATE_STATEMSK8_Pos 8 /*!< SCT EV3_STATE: STATEMSK8 Position */ #define SCT_EV3_STATE_STATEMSK8_Msk (0x01UL << SCT_EV3_STATE_STATEMSK8_Pos) /*!< SCT EV3_STATE: STATEMSK8 Mask */ #define SCT_EV3_STATE_STATEMSK9_Pos 9 /*!< SCT EV3_STATE: STATEMSK9 Position */ #define SCT_EV3_STATE_STATEMSK9_Msk (0x01UL << SCT_EV3_STATE_STATEMSK9_Pos) /*!< SCT EV3_STATE: STATEMSK9 Mask */ #define SCT_EV3_STATE_STATEMSK10_Pos 10 /*!< SCT EV3_STATE: STATEMSK10 Position */ #define SCT_EV3_STATE_STATEMSK10_Msk (0x01UL << SCT_EV3_STATE_STATEMSK10_Pos) /*!< SCT EV3_STATE: STATEMSK10 Mask */ #define SCT_EV3_STATE_STATEMSK11_Pos 11 /*!< SCT EV3_STATE: STATEMSK11 Position */ #define SCT_EV3_STATE_STATEMSK11_Msk (0x01UL << SCT_EV3_STATE_STATEMSK11_Pos) /*!< SCT EV3_STATE: STATEMSK11 Mask */ #define SCT_EV3_STATE_STATEMSK12_Pos 12 /*!< SCT EV3_STATE: STATEMSK12 Position */ #define SCT_EV3_STATE_STATEMSK12_Msk (0x01UL << SCT_EV3_STATE_STATEMSK12_Pos) /*!< SCT EV3_STATE: STATEMSK12 Mask */ #define SCT_EV3_STATE_STATEMSK13_Pos 13 /*!< SCT EV3_STATE: STATEMSK13 Position */ #define SCT_EV3_STATE_STATEMSK13_Msk (0x01UL << SCT_EV3_STATE_STATEMSK13_Pos) /*!< SCT EV3_STATE: STATEMSK13 Mask */ #define SCT_EV3_STATE_STATEMSK14_Pos 14 /*!< SCT EV3_STATE: STATEMSK14 Position */ #define SCT_EV3_STATE_STATEMSK14_Msk (0x01UL << SCT_EV3_STATE_STATEMSK14_Pos) /*!< SCT EV3_STATE: STATEMSK14 Mask */ #define SCT_EV3_STATE_STATEMSK15_Pos 15 /*!< SCT EV3_STATE: STATEMSK15 Position */ #define SCT_EV3_STATE_STATEMSK15_Msk (0x01UL << SCT_EV3_STATE_STATEMSK15_Pos) /*!< SCT EV3_STATE: STATEMSK15 Mask */ #define SCT_EV3_STATE_STATEMSK16_Pos 16 /*!< SCT EV3_STATE: STATEMSK16 Position */ #define SCT_EV3_STATE_STATEMSK16_Msk (0x01UL << SCT_EV3_STATE_STATEMSK16_Pos) /*!< SCT EV3_STATE: STATEMSK16 Mask */ #define SCT_EV3_STATE_STATEMSK17_Pos 17 /*!< SCT EV3_STATE: STATEMSK17 Position */ #define SCT_EV3_STATE_STATEMSK17_Msk (0x01UL << SCT_EV3_STATE_STATEMSK17_Pos) /*!< SCT EV3_STATE: STATEMSK17 Mask */ #define SCT_EV3_STATE_STATEMSK18_Pos 18 /*!< SCT EV3_STATE: STATEMSK18 Position */ #define SCT_EV3_STATE_STATEMSK18_Msk (0x01UL << SCT_EV3_STATE_STATEMSK18_Pos) /*!< SCT EV3_STATE: STATEMSK18 Mask */ #define SCT_EV3_STATE_STATEMSK19_Pos 19 /*!< SCT EV3_STATE: STATEMSK19 Position */ #define SCT_EV3_STATE_STATEMSK19_Msk (0x01UL << SCT_EV3_STATE_STATEMSK19_Pos) /*!< SCT EV3_STATE: STATEMSK19 Mask */ #define SCT_EV3_STATE_STATEMSK20_Pos 20 /*!< SCT EV3_STATE: STATEMSK20 Position */ #define SCT_EV3_STATE_STATEMSK20_Msk (0x01UL << SCT_EV3_STATE_STATEMSK20_Pos) /*!< SCT EV3_STATE: STATEMSK20 Mask */ #define SCT_EV3_STATE_STATEMSK21_Pos 21 /*!< SCT EV3_STATE: STATEMSK21 Position */ #define SCT_EV3_STATE_STATEMSK21_Msk (0x01UL << SCT_EV3_STATE_STATEMSK21_Pos) /*!< SCT EV3_STATE: STATEMSK21 Mask */ #define SCT_EV3_STATE_STATEMSK22_Pos 22 /*!< SCT EV3_STATE: STATEMSK22 Position */ #define SCT_EV3_STATE_STATEMSK22_Msk (0x01UL << SCT_EV3_STATE_STATEMSK22_Pos) /*!< SCT EV3_STATE: STATEMSK22 Mask */ #define SCT_EV3_STATE_STATEMSK23_Pos 23 /*!< SCT EV3_STATE: STATEMSK23 Position */ #define SCT_EV3_STATE_STATEMSK23_Msk (0x01UL << SCT_EV3_STATE_STATEMSK23_Pos) /*!< SCT EV3_STATE: STATEMSK23 Mask */ #define SCT_EV3_STATE_STATEMSK24_Pos 24 /*!< SCT EV3_STATE: STATEMSK24 Position */ #define SCT_EV3_STATE_STATEMSK24_Msk (0x01UL << SCT_EV3_STATE_STATEMSK24_Pos) /*!< SCT EV3_STATE: STATEMSK24 Mask */ #define SCT_EV3_STATE_STATEMSK25_Pos 25 /*!< SCT EV3_STATE: STATEMSK25 Position */ #define SCT_EV3_STATE_STATEMSK25_Msk (0x01UL << SCT_EV3_STATE_STATEMSK25_Pos) /*!< SCT EV3_STATE: STATEMSK25 Mask */ #define SCT_EV3_STATE_STATEMSK26_Pos 26 /*!< SCT EV3_STATE: STATEMSK26 Position */ #define SCT_EV3_STATE_STATEMSK26_Msk (0x01UL << SCT_EV3_STATE_STATEMSK26_Pos) /*!< SCT EV3_STATE: STATEMSK26 Mask */ #define SCT_EV3_STATE_STATEMSK27_Pos 27 /*!< SCT EV3_STATE: STATEMSK27 Position */ #define SCT_EV3_STATE_STATEMSK27_Msk (0x01UL << SCT_EV3_STATE_STATEMSK27_Pos) /*!< SCT EV3_STATE: STATEMSK27 Mask */ #define SCT_EV3_STATE_STATEMSK28_Pos 28 /*!< SCT EV3_STATE: STATEMSK28 Position */ #define SCT_EV3_STATE_STATEMSK28_Msk (0x01UL << SCT_EV3_STATE_STATEMSK28_Pos) /*!< SCT EV3_STATE: STATEMSK28 Mask */ #define SCT_EV3_STATE_STATEMSK29_Pos 29 /*!< SCT EV3_STATE: STATEMSK29 Position */ #define SCT_EV3_STATE_STATEMSK29_Msk (0x01UL << SCT_EV3_STATE_STATEMSK29_Pos) /*!< SCT EV3_STATE: STATEMSK29 Mask */ #define SCT_EV3_STATE_STATEMSK30_Pos 30 /*!< SCT EV3_STATE: STATEMSK30 Position */ #define SCT_EV3_STATE_STATEMSK30_Msk (0x01UL << SCT_EV3_STATE_STATEMSK30_Pos) /*!< SCT EV3_STATE: STATEMSK30 Mask */ #define SCT_EV3_STATE_STATEMSK31_Pos 31 /*!< SCT EV3_STATE: STATEMSK31 Position */ #define SCT_EV3_STATE_STATEMSK31_Msk (0x01UL << SCT_EV3_STATE_STATEMSK31_Pos) /*!< SCT EV3_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV3_CTRL -------------------------------- */ #define SCT_EV3_CTRL_MATCHSEL_Pos 0 /*!< SCT EV3_CTRL: MATCHSEL Position */ #define SCT_EV3_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV3_CTRL_MATCHSEL_Pos) /*!< SCT EV3_CTRL: MATCHSEL Mask */ #define SCT_EV3_CTRL_HEVENT_Pos 4 /*!< SCT EV3_CTRL: HEVENT Position */ #define SCT_EV3_CTRL_HEVENT_Msk (0x01UL << SCT_EV3_CTRL_HEVENT_Pos) /*!< SCT EV3_CTRL: HEVENT Mask */ #define SCT_EV3_CTRL_OUTSEL_Pos 5 /*!< SCT EV3_CTRL: OUTSEL Position */ #define SCT_EV3_CTRL_OUTSEL_Msk (0x01UL << SCT_EV3_CTRL_OUTSEL_Pos) /*!< SCT EV3_CTRL: OUTSEL Mask */ #define SCT_EV3_CTRL_IOSEL_Pos 6 /*!< SCT EV3_CTRL: IOSEL Position */ #define SCT_EV3_CTRL_IOSEL_Msk (0x0fUL << SCT_EV3_CTRL_IOSEL_Pos) /*!< SCT EV3_CTRL: IOSEL Mask */ #define SCT_EV3_CTRL_IOCOND_Pos 10 /*!< SCT EV3_CTRL: IOCOND Position */ #define SCT_EV3_CTRL_IOCOND_Msk (0x03UL << SCT_EV3_CTRL_IOCOND_Pos) /*!< SCT EV3_CTRL: IOCOND Mask */ #define SCT_EV3_CTRL_COMBMODE_Pos 12 /*!< SCT EV3_CTRL: COMBMODE Position */ #define SCT_EV3_CTRL_COMBMODE_Msk (0x03UL << SCT_EV3_CTRL_COMBMODE_Pos) /*!< SCT EV3_CTRL: COMBMODE Mask */ #define SCT_EV3_CTRL_STATELD_Pos 14 /*!< SCT EV3_CTRL: STATELD Position */ #define SCT_EV3_CTRL_STATELD_Msk (0x01UL << SCT_EV3_CTRL_STATELD_Pos) /*!< SCT EV3_CTRL: STATELD Mask */ #define SCT_EV3_CTRL_STATEV_Pos 15 /*!< SCT EV3_CTRL: STATEV Position */ #define SCT_EV3_CTRL_STATEV_Msk (0x1fUL << SCT_EV3_CTRL_STATEV_Pos) /*!< SCT EV3_CTRL: STATEV Mask */ #define SCT_EV3_CTRL_MATCHMEM_Pos 20 /*!< SCT EV3_CTRL: MATCHMEM Position */ #define SCT_EV3_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV3_CTRL_MATCHMEM_Pos) /*!< SCT EV3_CTRL: MATCHMEM Mask */ #define SCT_EV3_CTRL_DIRECTION_Pos 21 /*!< SCT EV3_CTRL: DIRECTION Position */ #define SCT_EV3_CTRL_DIRECTION_Msk (0x03UL << SCT_EV3_CTRL_DIRECTION_Pos) /*!< SCT EV3_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV4_STATE ------------------------------- */ #define SCT_EV4_STATE_STATEMSK0_Pos 0 /*!< SCT EV4_STATE: STATEMSK0 Position */ #define SCT_EV4_STATE_STATEMSK0_Msk (0x01UL << SCT_EV4_STATE_STATEMSK0_Pos) /*!< SCT EV4_STATE: STATEMSK0 Mask */ #define SCT_EV4_STATE_STATEMSK1_Pos 1 /*!< SCT EV4_STATE: STATEMSK1 Position */ #define SCT_EV4_STATE_STATEMSK1_Msk (0x01UL << SCT_EV4_STATE_STATEMSK1_Pos) /*!< SCT EV4_STATE: STATEMSK1 Mask */ #define SCT_EV4_STATE_STATEMSK2_Pos 2 /*!< SCT EV4_STATE: STATEMSK2 Position */ #define SCT_EV4_STATE_STATEMSK2_Msk (0x01UL << SCT_EV4_STATE_STATEMSK2_Pos) /*!< SCT EV4_STATE: STATEMSK2 Mask */ #define SCT_EV4_STATE_STATEMSK3_Pos 3 /*!< SCT EV4_STATE: STATEMSK3 Position */ #define SCT_EV4_STATE_STATEMSK3_Msk (0x01UL << SCT_EV4_STATE_STATEMSK3_Pos) /*!< SCT EV4_STATE: STATEMSK3 Mask */ #define SCT_EV4_STATE_STATEMSK4_Pos 4 /*!< SCT EV4_STATE: STATEMSK4 Position */ #define SCT_EV4_STATE_STATEMSK4_Msk (0x01UL << SCT_EV4_STATE_STATEMSK4_Pos) /*!< SCT EV4_STATE: STATEMSK4 Mask */ #define SCT_EV4_STATE_STATEMSK5_Pos 5 /*!< SCT EV4_STATE: STATEMSK5 Position */ #define SCT_EV4_STATE_STATEMSK5_Msk (0x01UL << SCT_EV4_STATE_STATEMSK5_Pos) /*!< SCT EV4_STATE: STATEMSK5 Mask */ #define SCT_EV4_STATE_STATEMSK6_Pos 6 /*!< SCT EV4_STATE: STATEMSK6 Position */ #define SCT_EV4_STATE_STATEMSK6_Msk (0x01UL << SCT_EV4_STATE_STATEMSK6_Pos) /*!< SCT EV4_STATE: STATEMSK6 Mask */ #define SCT_EV4_STATE_STATEMSK7_Pos 7 /*!< SCT EV4_STATE: STATEMSK7 Position */ #define SCT_EV4_STATE_STATEMSK7_Msk (0x01UL << SCT_EV4_STATE_STATEMSK7_Pos) /*!< SCT EV4_STATE: STATEMSK7 Mask */ #define SCT_EV4_STATE_STATEMSK8_Pos 8 /*!< SCT EV4_STATE: STATEMSK8 Position */ #define SCT_EV4_STATE_STATEMSK8_Msk (0x01UL << SCT_EV4_STATE_STATEMSK8_Pos) /*!< SCT EV4_STATE: STATEMSK8 Mask */ #define SCT_EV4_STATE_STATEMSK9_Pos 9 /*!< SCT EV4_STATE: STATEMSK9 Position */ #define SCT_EV4_STATE_STATEMSK9_Msk (0x01UL << SCT_EV4_STATE_STATEMSK9_Pos) /*!< SCT EV4_STATE: STATEMSK9 Mask */ #define SCT_EV4_STATE_STATEMSK10_Pos 10 /*!< SCT EV4_STATE: STATEMSK10 Position */ #define SCT_EV4_STATE_STATEMSK10_Msk (0x01UL << SCT_EV4_STATE_STATEMSK10_Pos) /*!< SCT EV4_STATE: STATEMSK10 Mask */ #define SCT_EV4_STATE_STATEMSK11_Pos 11 /*!< SCT EV4_STATE: STATEMSK11 Position */ #define SCT_EV4_STATE_STATEMSK11_Msk (0x01UL << SCT_EV4_STATE_STATEMSK11_Pos) /*!< SCT EV4_STATE: STATEMSK11 Mask */ #define SCT_EV4_STATE_STATEMSK12_Pos 12 /*!< SCT EV4_STATE: STATEMSK12 Position */ #define SCT_EV4_STATE_STATEMSK12_Msk (0x01UL << SCT_EV4_STATE_STATEMSK12_Pos) /*!< SCT EV4_STATE: STATEMSK12 Mask */ #define SCT_EV4_STATE_STATEMSK13_Pos 13 /*!< SCT EV4_STATE: STATEMSK13 Position */ #define SCT_EV4_STATE_STATEMSK13_Msk (0x01UL << SCT_EV4_STATE_STATEMSK13_Pos) /*!< SCT EV4_STATE: STATEMSK13 Mask */ #define SCT_EV4_STATE_STATEMSK14_Pos 14 /*!< SCT EV4_STATE: STATEMSK14 Position */ #define SCT_EV4_STATE_STATEMSK14_Msk (0x01UL << SCT_EV4_STATE_STATEMSK14_Pos) /*!< SCT EV4_STATE: STATEMSK14 Mask */ #define SCT_EV4_STATE_STATEMSK15_Pos 15 /*!< SCT EV4_STATE: STATEMSK15 Position */ #define SCT_EV4_STATE_STATEMSK15_Msk (0x01UL << SCT_EV4_STATE_STATEMSK15_Pos) /*!< SCT EV4_STATE: STATEMSK15 Mask */ #define SCT_EV4_STATE_STATEMSK16_Pos 16 /*!< SCT EV4_STATE: STATEMSK16 Position */ #define SCT_EV4_STATE_STATEMSK16_Msk (0x01UL << SCT_EV4_STATE_STATEMSK16_Pos) /*!< SCT EV4_STATE: STATEMSK16 Mask */ #define SCT_EV4_STATE_STATEMSK17_Pos 17 /*!< SCT EV4_STATE: STATEMSK17 Position */ #define SCT_EV4_STATE_STATEMSK17_Msk (0x01UL << SCT_EV4_STATE_STATEMSK17_Pos) /*!< SCT EV4_STATE: STATEMSK17 Mask */ #define SCT_EV4_STATE_STATEMSK18_Pos 18 /*!< SCT EV4_STATE: STATEMSK18 Position */ #define SCT_EV4_STATE_STATEMSK18_Msk (0x01UL << SCT_EV4_STATE_STATEMSK18_Pos) /*!< SCT EV4_STATE: STATEMSK18 Mask */ #define SCT_EV4_STATE_STATEMSK19_Pos 19 /*!< SCT EV4_STATE: STATEMSK19 Position */ #define SCT_EV4_STATE_STATEMSK19_Msk (0x01UL << SCT_EV4_STATE_STATEMSK19_Pos) /*!< SCT EV4_STATE: STATEMSK19 Mask */ #define SCT_EV4_STATE_STATEMSK20_Pos 20 /*!< SCT EV4_STATE: STATEMSK20 Position */ #define SCT_EV4_STATE_STATEMSK20_Msk (0x01UL << SCT_EV4_STATE_STATEMSK20_Pos) /*!< SCT EV4_STATE: STATEMSK20 Mask */ #define SCT_EV4_STATE_STATEMSK21_Pos 21 /*!< SCT EV4_STATE: STATEMSK21 Position */ #define SCT_EV4_STATE_STATEMSK21_Msk (0x01UL << SCT_EV4_STATE_STATEMSK21_Pos) /*!< SCT EV4_STATE: STATEMSK21 Mask */ #define SCT_EV4_STATE_STATEMSK22_Pos 22 /*!< SCT EV4_STATE: STATEMSK22 Position */ #define SCT_EV4_STATE_STATEMSK22_Msk (0x01UL << SCT_EV4_STATE_STATEMSK22_Pos) /*!< SCT EV4_STATE: STATEMSK22 Mask */ #define SCT_EV4_STATE_STATEMSK23_Pos 23 /*!< SCT EV4_STATE: STATEMSK23 Position */ #define SCT_EV4_STATE_STATEMSK23_Msk (0x01UL << SCT_EV4_STATE_STATEMSK23_Pos) /*!< SCT EV4_STATE: STATEMSK23 Mask */ #define SCT_EV4_STATE_STATEMSK24_Pos 24 /*!< SCT EV4_STATE: STATEMSK24 Position */ #define SCT_EV4_STATE_STATEMSK24_Msk (0x01UL << SCT_EV4_STATE_STATEMSK24_Pos) /*!< SCT EV4_STATE: STATEMSK24 Mask */ #define SCT_EV4_STATE_STATEMSK25_Pos 25 /*!< SCT EV4_STATE: STATEMSK25 Position */ #define SCT_EV4_STATE_STATEMSK25_Msk (0x01UL << SCT_EV4_STATE_STATEMSK25_Pos) /*!< SCT EV4_STATE: STATEMSK25 Mask */ #define SCT_EV4_STATE_STATEMSK26_Pos 26 /*!< SCT EV4_STATE: STATEMSK26 Position */ #define SCT_EV4_STATE_STATEMSK26_Msk (0x01UL << SCT_EV4_STATE_STATEMSK26_Pos) /*!< SCT EV4_STATE: STATEMSK26 Mask */ #define SCT_EV4_STATE_STATEMSK27_Pos 27 /*!< SCT EV4_STATE: STATEMSK27 Position */ #define SCT_EV4_STATE_STATEMSK27_Msk (0x01UL << SCT_EV4_STATE_STATEMSK27_Pos) /*!< SCT EV4_STATE: STATEMSK27 Mask */ #define SCT_EV4_STATE_STATEMSK28_Pos 28 /*!< SCT EV4_STATE: STATEMSK28 Position */ #define SCT_EV4_STATE_STATEMSK28_Msk (0x01UL << SCT_EV4_STATE_STATEMSK28_Pos) /*!< SCT EV4_STATE: STATEMSK28 Mask */ #define SCT_EV4_STATE_STATEMSK29_Pos 29 /*!< SCT EV4_STATE: STATEMSK29 Position */ #define SCT_EV4_STATE_STATEMSK29_Msk (0x01UL << SCT_EV4_STATE_STATEMSK29_Pos) /*!< SCT EV4_STATE: STATEMSK29 Mask */ #define SCT_EV4_STATE_STATEMSK30_Pos 30 /*!< SCT EV4_STATE: STATEMSK30 Position */ #define SCT_EV4_STATE_STATEMSK30_Msk (0x01UL << SCT_EV4_STATE_STATEMSK30_Pos) /*!< SCT EV4_STATE: STATEMSK30 Mask */ #define SCT_EV4_STATE_STATEMSK31_Pos 31 /*!< SCT EV4_STATE: STATEMSK31 Position */ #define SCT_EV4_STATE_STATEMSK31_Msk (0x01UL << SCT_EV4_STATE_STATEMSK31_Pos) /*!< SCT EV4_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV4_CTRL -------------------------------- */ #define SCT_EV4_CTRL_MATCHSEL_Pos 0 /*!< SCT EV4_CTRL: MATCHSEL Position */ #define SCT_EV4_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV4_CTRL_MATCHSEL_Pos) /*!< SCT EV4_CTRL: MATCHSEL Mask */ #define SCT_EV4_CTRL_HEVENT_Pos 4 /*!< SCT EV4_CTRL: HEVENT Position */ #define SCT_EV4_CTRL_HEVENT_Msk (0x01UL << SCT_EV4_CTRL_HEVENT_Pos) /*!< SCT EV4_CTRL: HEVENT Mask */ #define SCT_EV4_CTRL_OUTSEL_Pos 5 /*!< SCT EV4_CTRL: OUTSEL Position */ #define SCT_EV4_CTRL_OUTSEL_Msk (0x01UL << SCT_EV4_CTRL_OUTSEL_Pos) /*!< SCT EV4_CTRL: OUTSEL Mask */ #define SCT_EV4_CTRL_IOSEL_Pos 6 /*!< SCT EV4_CTRL: IOSEL Position */ #define SCT_EV4_CTRL_IOSEL_Msk (0x0fUL << SCT_EV4_CTRL_IOSEL_Pos) /*!< SCT EV4_CTRL: IOSEL Mask */ #define SCT_EV4_CTRL_IOCOND_Pos 10 /*!< SCT EV4_CTRL: IOCOND Position */ #define SCT_EV4_CTRL_IOCOND_Msk (0x03UL << SCT_EV4_CTRL_IOCOND_Pos) /*!< SCT EV4_CTRL: IOCOND Mask */ #define SCT_EV4_CTRL_COMBMODE_Pos 12 /*!< SCT EV4_CTRL: COMBMODE Position */ #define SCT_EV4_CTRL_COMBMODE_Msk (0x03UL << SCT_EV4_CTRL_COMBMODE_Pos) /*!< SCT EV4_CTRL: COMBMODE Mask */ #define SCT_EV4_CTRL_STATELD_Pos 14 /*!< SCT EV4_CTRL: STATELD Position */ #define SCT_EV4_CTRL_STATELD_Msk (0x01UL << SCT_EV4_CTRL_STATELD_Pos) /*!< SCT EV4_CTRL: STATELD Mask */ #define SCT_EV4_CTRL_STATEV_Pos 15 /*!< SCT EV4_CTRL: STATEV Position */ #define SCT_EV4_CTRL_STATEV_Msk (0x1fUL << SCT_EV4_CTRL_STATEV_Pos) /*!< SCT EV4_CTRL: STATEV Mask */ #define SCT_EV4_CTRL_MATCHMEM_Pos 20 /*!< SCT EV4_CTRL: MATCHMEM Position */ #define SCT_EV4_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV4_CTRL_MATCHMEM_Pos) /*!< SCT EV4_CTRL: MATCHMEM Mask */ #define SCT_EV4_CTRL_DIRECTION_Pos 21 /*!< SCT EV4_CTRL: DIRECTION Position */ #define SCT_EV4_CTRL_DIRECTION_Msk (0x03UL << SCT_EV4_CTRL_DIRECTION_Pos) /*!< SCT EV4_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV5_STATE ------------------------------- */ #define SCT_EV5_STATE_STATEMSK0_Pos 0 /*!< SCT EV5_STATE: STATEMSK0 Position */ #define SCT_EV5_STATE_STATEMSK0_Msk (0x01UL << SCT_EV5_STATE_STATEMSK0_Pos) /*!< SCT EV5_STATE: STATEMSK0 Mask */ #define SCT_EV5_STATE_STATEMSK1_Pos 1 /*!< SCT EV5_STATE: STATEMSK1 Position */ #define SCT_EV5_STATE_STATEMSK1_Msk (0x01UL << SCT_EV5_STATE_STATEMSK1_Pos) /*!< SCT EV5_STATE: STATEMSK1 Mask */ #define SCT_EV5_STATE_STATEMSK2_Pos 2 /*!< SCT EV5_STATE: STATEMSK2 Position */ #define SCT_EV5_STATE_STATEMSK2_Msk (0x01UL << SCT_EV5_STATE_STATEMSK2_Pos) /*!< SCT EV5_STATE: STATEMSK2 Mask */ #define SCT_EV5_STATE_STATEMSK3_Pos 3 /*!< SCT EV5_STATE: STATEMSK3 Position */ #define SCT_EV5_STATE_STATEMSK3_Msk (0x01UL << SCT_EV5_STATE_STATEMSK3_Pos) /*!< SCT EV5_STATE: STATEMSK3 Mask */ #define SCT_EV5_STATE_STATEMSK4_Pos 4 /*!< SCT EV5_STATE: STATEMSK4 Position */ #define SCT_EV5_STATE_STATEMSK4_Msk (0x01UL << SCT_EV5_STATE_STATEMSK4_Pos) /*!< SCT EV5_STATE: STATEMSK4 Mask */ #define SCT_EV5_STATE_STATEMSK5_Pos 5 /*!< SCT EV5_STATE: STATEMSK5 Position */ #define SCT_EV5_STATE_STATEMSK5_Msk (0x01UL << SCT_EV5_STATE_STATEMSK5_Pos) /*!< SCT EV5_STATE: STATEMSK5 Mask */ #define SCT_EV5_STATE_STATEMSK6_Pos 6 /*!< SCT EV5_STATE: STATEMSK6 Position */ #define SCT_EV5_STATE_STATEMSK6_Msk (0x01UL << SCT_EV5_STATE_STATEMSK6_Pos) /*!< SCT EV5_STATE: STATEMSK6 Mask */ #define SCT_EV5_STATE_STATEMSK7_Pos 7 /*!< SCT EV5_STATE: STATEMSK7 Position */ #define SCT_EV5_STATE_STATEMSK7_Msk (0x01UL << SCT_EV5_STATE_STATEMSK7_Pos) /*!< SCT EV5_STATE: STATEMSK7 Mask */ #define SCT_EV5_STATE_STATEMSK8_Pos 8 /*!< SCT EV5_STATE: STATEMSK8 Position */ #define SCT_EV5_STATE_STATEMSK8_Msk (0x01UL << SCT_EV5_STATE_STATEMSK8_Pos) /*!< SCT EV5_STATE: STATEMSK8 Mask */ #define SCT_EV5_STATE_STATEMSK9_Pos 9 /*!< SCT EV5_STATE: STATEMSK9 Position */ #define SCT_EV5_STATE_STATEMSK9_Msk (0x01UL << SCT_EV5_STATE_STATEMSK9_Pos) /*!< SCT EV5_STATE: STATEMSK9 Mask */ #define SCT_EV5_STATE_STATEMSK10_Pos 10 /*!< SCT EV5_STATE: STATEMSK10 Position */ #define SCT_EV5_STATE_STATEMSK10_Msk (0x01UL << SCT_EV5_STATE_STATEMSK10_Pos) /*!< SCT EV5_STATE: STATEMSK10 Mask */ #define SCT_EV5_STATE_STATEMSK11_Pos 11 /*!< SCT EV5_STATE: STATEMSK11 Position */ #define SCT_EV5_STATE_STATEMSK11_Msk (0x01UL << SCT_EV5_STATE_STATEMSK11_Pos) /*!< SCT EV5_STATE: STATEMSK11 Mask */ #define SCT_EV5_STATE_STATEMSK12_Pos 12 /*!< SCT EV5_STATE: STATEMSK12 Position */ #define SCT_EV5_STATE_STATEMSK12_Msk (0x01UL << SCT_EV5_STATE_STATEMSK12_Pos) /*!< SCT EV5_STATE: STATEMSK12 Mask */ #define SCT_EV5_STATE_STATEMSK13_Pos 13 /*!< SCT EV5_STATE: STATEMSK13 Position */ #define SCT_EV5_STATE_STATEMSK13_Msk (0x01UL << SCT_EV5_STATE_STATEMSK13_Pos) /*!< SCT EV5_STATE: STATEMSK13 Mask */ #define SCT_EV5_STATE_STATEMSK14_Pos 14 /*!< SCT EV5_STATE: STATEMSK14 Position */ #define SCT_EV5_STATE_STATEMSK14_Msk (0x01UL << SCT_EV5_STATE_STATEMSK14_Pos) /*!< SCT EV5_STATE: STATEMSK14 Mask */ #define SCT_EV5_STATE_STATEMSK15_Pos 15 /*!< SCT EV5_STATE: STATEMSK15 Position */ #define SCT_EV5_STATE_STATEMSK15_Msk (0x01UL << SCT_EV5_STATE_STATEMSK15_Pos) /*!< SCT EV5_STATE: STATEMSK15 Mask */ #define SCT_EV5_STATE_STATEMSK16_Pos 16 /*!< SCT EV5_STATE: STATEMSK16 Position */ #define SCT_EV5_STATE_STATEMSK16_Msk (0x01UL << SCT_EV5_STATE_STATEMSK16_Pos) /*!< SCT EV5_STATE: STATEMSK16 Mask */ #define SCT_EV5_STATE_STATEMSK17_Pos 17 /*!< SCT EV5_STATE: STATEMSK17 Position */ #define SCT_EV5_STATE_STATEMSK17_Msk (0x01UL << SCT_EV5_STATE_STATEMSK17_Pos) /*!< SCT EV5_STATE: STATEMSK17 Mask */ #define SCT_EV5_STATE_STATEMSK18_Pos 18 /*!< SCT EV5_STATE: STATEMSK18 Position */ #define SCT_EV5_STATE_STATEMSK18_Msk (0x01UL << SCT_EV5_STATE_STATEMSK18_Pos) /*!< SCT EV5_STATE: STATEMSK18 Mask */ #define SCT_EV5_STATE_STATEMSK19_Pos 19 /*!< SCT EV5_STATE: STATEMSK19 Position */ #define SCT_EV5_STATE_STATEMSK19_Msk (0x01UL << SCT_EV5_STATE_STATEMSK19_Pos) /*!< SCT EV5_STATE: STATEMSK19 Mask */ #define SCT_EV5_STATE_STATEMSK20_Pos 20 /*!< SCT EV5_STATE: STATEMSK20 Position */ #define SCT_EV5_STATE_STATEMSK20_Msk (0x01UL << SCT_EV5_STATE_STATEMSK20_Pos) /*!< SCT EV5_STATE: STATEMSK20 Mask */ #define SCT_EV5_STATE_STATEMSK21_Pos 21 /*!< SCT EV5_STATE: STATEMSK21 Position */ #define SCT_EV5_STATE_STATEMSK21_Msk (0x01UL << SCT_EV5_STATE_STATEMSK21_Pos) /*!< SCT EV5_STATE: STATEMSK21 Mask */ #define SCT_EV5_STATE_STATEMSK22_Pos 22 /*!< SCT EV5_STATE: STATEMSK22 Position */ #define SCT_EV5_STATE_STATEMSK22_Msk (0x01UL << SCT_EV5_STATE_STATEMSK22_Pos) /*!< SCT EV5_STATE: STATEMSK22 Mask */ #define SCT_EV5_STATE_STATEMSK23_Pos 23 /*!< SCT EV5_STATE: STATEMSK23 Position */ #define SCT_EV5_STATE_STATEMSK23_Msk (0x01UL << SCT_EV5_STATE_STATEMSK23_Pos) /*!< SCT EV5_STATE: STATEMSK23 Mask */ #define SCT_EV5_STATE_STATEMSK24_Pos 24 /*!< SCT EV5_STATE: STATEMSK24 Position */ #define SCT_EV5_STATE_STATEMSK24_Msk (0x01UL << SCT_EV5_STATE_STATEMSK24_Pos) /*!< SCT EV5_STATE: STATEMSK24 Mask */ #define SCT_EV5_STATE_STATEMSK25_Pos 25 /*!< SCT EV5_STATE: STATEMSK25 Position */ #define SCT_EV5_STATE_STATEMSK25_Msk (0x01UL << SCT_EV5_STATE_STATEMSK25_Pos) /*!< SCT EV5_STATE: STATEMSK25 Mask */ #define SCT_EV5_STATE_STATEMSK26_Pos 26 /*!< SCT EV5_STATE: STATEMSK26 Position */ #define SCT_EV5_STATE_STATEMSK26_Msk (0x01UL << SCT_EV5_STATE_STATEMSK26_Pos) /*!< SCT EV5_STATE: STATEMSK26 Mask */ #define SCT_EV5_STATE_STATEMSK27_Pos 27 /*!< SCT EV5_STATE: STATEMSK27 Position */ #define SCT_EV5_STATE_STATEMSK27_Msk (0x01UL << SCT_EV5_STATE_STATEMSK27_Pos) /*!< SCT EV5_STATE: STATEMSK27 Mask */ #define SCT_EV5_STATE_STATEMSK28_Pos 28 /*!< SCT EV5_STATE: STATEMSK28 Position */ #define SCT_EV5_STATE_STATEMSK28_Msk (0x01UL << SCT_EV5_STATE_STATEMSK28_Pos) /*!< SCT EV5_STATE: STATEMSK28 Mask */ #define SCT_EV5_STATE_STATEMSK29_Pos 29 /*!< SCT EV5_STATE: STATEMSK29 Position */ #define SCT_EV5_STATE_STATEMSK29_Msk (0x01UL << SCT_EV5_STATE_STATEMSK29_Pos) /*!< SCT EV5_STATE: STATEMSK29 Mask */ #define SCT_EV5_STATE_STATEMSK30_Pos 30 /*!< SCT EV5_STATE: STATEMSK30 Position */ #define SCT_EV5_STATE_STATEMSK30_Msk (0x01UL << SCT_EV5_STATE_STATEMSK30_Pos) /*!< SCT EV5_STATE: STATEMSK30 Mask */ #define SCT_EV5_STATE_STATEMSK31_Pos 31 /*!< SCT EV5_STATE: STATEMSK31 Position */ #define SCT_EV5_STATE_STATEMSK31_Msk (0x01UL << SCT_EV5_STATE_STATEMSK31_Pos) /*!< SCT EV5_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV5_CTRL -------------------------------- */ #define SCT_EV5_CTRL_MATCHSEL_Pos 0 /*!< SCT EV5_CTRL: MATCHSEL Position */ #define SCT_EV5_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV5_CTRL_MATCHSEL_Pos) /*!< SCT EV5_CTRL: MATCHSEL Mask */ #define SCT_EV5_CTRL_HEVENT_Pos 4 /*!< SCT EV5_CTRL: HEVENT Position */ #define SCT_EV5_CTRL_HEVENT_Msk (0x01UL << SCT_EV5_CTRL_HEVENT_Pos) /*!< SCT EV5_CTRL: HEVENT Mask */ #define SCT_EV5_CTRL_OUTSEL_Pos 5 /*!< SCT EV5_CTRL: OUTSEL Position */ #define SCT_EV5_CTRL_OUTSEL_Msk (0x01UL << SCT_EV5_CTRL_OUTSEL_Pos) /*!< SCT EV5_CTRL: OUTSEL Mask */ #define SCT_EV5_CTRL_IOSEL_Pos 6 /*!< SCT EV5_CTRL: IOSEL Position */ #define SCT_EV5_CTRL_IOSEL_Msk (0x0fUL << SCT_EV5_CTRL_IOSEL_Pos) /*!< SCT EV5_CTRL: IOSEL Mask */ #define SCT_EV5_CTRL_IOCOND_Pos 10 /*!< SCT EV5_CTRL: IOCOND Position */ #define SCT_EV5_CTRL_IOCOND_Msk (0x03UL << SCT_EV5_CTRL_IOCOND_Pos) /*!< SCT EV5_CTRL: IOCOND Mask */ #define SCT_EV5_CTRL_COMBMODE_Pos 12 /*!< SCT EV5_CTRL: COMBMODE Position */ #define SCT_EV5_CTRL_COMBMODE_Msk (0x03UL << SCT_EV5_CTRL_COMBMODE_Pos) /*!< SCT EV5_CTRL: COMBMODE Mask */ #define SCT_EV5_CTRL_STATELD_Pos 14 /*!< SCT EV5_CTRL: STATELD Position */ #define SCT_EV5_CTRL_STATELD_Msk (0x01UL << SCT_EV5_CTRL_STATELD_Pos) /*!< SCT EV5_CTRL: STATELD Mask */ #define SCT_EV5_CTRL_STATEV_Pos 15 /*!< SCT EV5_CTRL: STATEV Position */ #define SCT_EV5_CTRL_STATEV_Msk (0x1fUL << SCT_EV5_CTRL_STATEV_Pos) /*!< SCT EV5_CTRL: STATEV Mask */ #define SCT_EV5_CTRL_MATCHMEM_Pos 20 /*!< SCT EV5_CTRL: MATCHMEM Position */ #define SCT_EV5_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV5_CTRL_MATCHMEM_Pos) /*!< SCT EV5_CTRL: MATCHMEM Mask */ #define SCT_EV5_CTRL_DIRECTION_Pos 21 /*!< SCT EV5_CTRL: DIRECTION Position */ #define SCT_EV5_CTRL_DIRECTION_Msk (0x03UL << SCT_EV5_CTRL_DIRECTION_Pos) /*!< SCT EV5_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV6_STATE ------------------------------- */ #define SCT_EV6_STATE_STATEMSK0_Pos 0 /*!< SCT EV6_STATE: STATEMSK0 Position */ #define SCT_EV6_STATE_STATEMSK0_Msk (0x01UL << SCT_EV6_STATE_STATEMSK0_Pos) /*!< SCT EV6_STATE: STATEMSK0 Mask */ #define SCT_EV6_STATE_STATEMSK1_Pos 1 /*!< SCT EV6_STATE: STATEMSK1 Position */ #define SCT_EV6_STATE_STATEMSK1_Msk (0x01UL << SCT_EV6_STATE_STATEMSK1_Pos) /*!< SCT EV6_STATE: STATEMSK1 Mask */ #define SCT_EV6_STATE_STATEMSK2_Pos 2 /*!< SCT EV6_STATE: STATEMSK2 Position */ #define SCT_EV6_STATE_STATEMSK2_Msk (0x01UL << SCT_EV6_STATE_STATEMSK2_Pos) /*!< SCT EV6_STATE: STATEMSK2 Mask */ #define SCT_EV6_STATE_STATEMSK3_Pos 3 /*!< SCT EV6_STATE: STATEMSK3 Position */ #define SCT_EV6_STATE_STATEMSK3_Msk (0x01UL << SCT_EV6_STATE_STATEMSK3_Pos) /*!< SCT EV6_STATE: STATEMSK3 Mask */ #define SCT_EV6_STATE_STATEMSK4_Pos 4 /*!< SCT EV6_STATE: STATEMSK4 Position */ #define SCT_EV6_STATE_STATEMSK4_Msk (0x01UL << SCT_EV6_STATE_STATEMSK4_Pos) /*!< SCT EV6_STATE: STATEMSK4 Mask */ #define SCT_EV6_STATE_STATEMSK5_Pos 5 /*!< SCT EV6_STATE: STATEMSK5 Position */ #define SCT_EV6_STATE_STATEMSK5_Msk (0x01UL << SCT_EV6_STATE_STATEMSK5_Pos) /*!< SCT EV6_STATE: STATEMSK5 Mask */ #define SCT_EV6_STATE_STATEMSK6_Pos 6 /*!< SCT EV6_STATE: STATEMSK6 Position */ #define SCT_EV6_STATE_STATEMSK6_Msk (0x01UL << SCT_EV6_STATE_STATEMSK6_Pos) /*!< SCT EV6_STATE: STATEMSK6 Mask */ #define SCT_EV6_STATE_STATEMSK7_Pos 7 /*!< SCT EV6_STATE: STATEMSK7 Position */ #define SCT_EV6_STATE_STATEMSK7_Msk (0x01UL << SCT_EV6_STATE_STATEMSK7_Pos) /*!< SCT EV6_STATE: STATEMSK7 Mask */ #define SCT_EV6_STATE_STATEMSK8_Pos 8 /*!< SCT EV6_STATE: STATEMSK8 Position */ #define SCT_EV6_STATE_STATEMSK8_Msk (0x01UL << SCT_EV6_STATE_STATEMSK8_Pos) /*!< SCT EV6_STATE: STATEMSK8 Mask */ #define SCT_EV6_STATE_STATEMSK9_Pos 9 /*!< SCT EV6_STATE: STATEMSK9 Position */ #define SCT_EV6_STATE_STATEMSK9_Msk (0x01UL << SCT_EV6_STATE_STATEMSK9_Pos) /*!< SCT EV6_STATE: STATEMSK9 Mask */ #define SCT_EV6_STATE_STATEMSK10_Pos 10 /*!< SCT EV6_STATE: STATEMSK10 Position */ #define SCT_EV6_STATE_STATEMSK10_Msk (0x01UL << SCT_EV6_STATE_STATEMSK10_Pos) /*!< SCT EV6_STATE: STATEMSK10 Mask */ #define SCT_EV6_STATE_STATEMSK11_Pos 11 /*!< SCT EV6_STATE: STATEMSK11 Position */ #define SCT_EV6_STATE_STATEMSK11_Msk (0x01UL << SCT_EV6_STATE_STATEMSK11_Pos) /*!< SCT EV6_STATE: STATEMSK11 Mask */ #define SCT_EV6_STATE_STATEMSK12_Pos 12 /*!< SCT EV6_STATE: STATEMSK12 Position */ #define SCT_EV6_STATE_STATEMSK12_Msk (0x01UL << SCT_EV6_STATE_STATEMSK12_Pos) /*!< SCT EV6_STATE: STATEMSK12 Mask */ #define SCT_EV6_STATE_STATEMSK13_Pos 13 /*!< SCT EV6_STATE: STATEMSK13 Position */ #define SCT_EV6_STATE_STATEMSK13_Msk (0x01UL << SCT_EV6_STATE_STATEMSK13_Pos) /*!< SCT EV6_STATE: STATEMSK13 Mask */ #define SCT_EV6_STATE_STATEMSK14_Pos 14 /*!< SCT EV6_STATE: STATEMSK14 Position */ #define SCT_EV6_STATE_STATEMSK14_Msk (0x01UL << SCT_EV6_STATE_STATEMSK14_Pos) /*!< SCT EV6_STATE: STATEMSK14 Mask */ #define SCT_EV6_STATE_STATEMSK15_Pos 15 /*!< SCT EV6_STATE: STATEMSK15 Position */ #define SCT_EV6_STATE_STATEMSK15_Msk (0x01UL << SCT_EV6_STATE_STATEMSK15_Pos) /*!< SCT EV6_STATE: STATEMSK15 Mask */ #define SCT_EV6_STATE_STATEMSK16_Pos 16 /*!< SCT EV6_STATE: STATEMSK16 Position */ #define SCT_EV6_STATE_STATEMSK16_Msk (0x01UL << SCT_EV6_STATE_STATEMSK16_Pos) /*!< SCT EV6_STATE: STATEMSK16 Mask */ #define SCT_EV6_STATE_STATEMSK17_Pos 17 /*!< SCT EV6_STATE: STATEMSK17 Position */ #define SCT_EV6_STATE_STATEMSK17_Msk (0x01UL << SCT_EV6_STATE_STATEMSK17_Pos) /*!< SCT EV6_STATE: STATEMSK17 Mask */ #define SCT_EV6_STATE_STATEMSK18_Pos 18 /*!< SCT EV6_STATE: STATEMSK18 Position */ #define SCT_EV6_STATE_STATEMSK18_Msk (0x01UL << SCT_EV6_STATE_STATEMSK18_Pos) /*!< SCT EV6_STATE: STATEMSK18 Mask */ #define SCT_EV6_STATE_STATEMSK19_Pos 19 /*!< SCT EV6_STATE: STATEMSK19 Position */ #define SCT_EV6_STATE_STATEMSK19_Msk (0x01UL << SCT_EV6_STATE_STATEMSK19_Pos) /*!< SCT EV6_STATE: STATEMSK19 Mask */ #define SCT_EV6_STATE_STATEMSK20_Pos 20 /*!< SCT EV6_STATE: STATEMSK20 Position */ #define SCT_EV6_STATE_STATEMSK20_Msk (0x01UL << SCT_EV6_STATE_STATEMSK20_Pos) /*!< SCT EV6_STATE: STATEMSK20 Mask */ #define SCT_EV6_STATE_STATEMSK21_Pos 21 /*!< SCT EV6_STATE: STATEMSK21 Position */ #define SCT_EV6_STATE_STATEMSK21_Msk (0x01UL << SCT_EV6_STATE_STATEMSK21_Pos) /*!< SCT EV6_STATE: STATEMSK21 Mask */ #define SCT_EV6_STATE_STATEMSK22_Pos 22 /*!< SCT EV6_STATE: STATEMSK22 Position */ #define SCT_EV6_STATE_STATEMSK22_Msk (0x01UL << SCT_EV6_STATE_STATEMSK22_Pos) /*!< SCT EV6_STATE: STATEMSK22 Mask */ #define SCT_EV6_STATE_STATEMSK23_Pos 23 /*!< SCT EV6_STATE: STATEMSK23 Position */ #define SCT_EV6_STATE_STATEMSK23_Msk (0x01UL << SCT_EV6_STATE_STATEMSK23_Pos) /*!< SCT EV6_STATE: STATEMSK23 Mask */ #define SCT_EV6_STATE_STATEMSK24_Pos 24 /*!< SCT EV6_STATE: STATEMSK24 Position */ #define SCT_EV6_STATE_STATEMSK24_Msk (0x01UL << SCT_EV6_STATE_STATEMSK24_Pos) /*!< SCT EV6_STATE: STATEMSK24 Mask */ #define SCT_EV6_STATE_STATEMSK25_Pos 25 /*!< SCT EV6_STATE: STATEMSK25 Position */ #define SCT_EV6_STATE_STATEMSK25_Msk (0x01UL << SCT_EV6_STATE_STATEMSK25_Pos) /*!< SCT EV6_STATE: STATEMSK25 Mask */ #define SCT_EV6_STATE_STATEMSK26_Pos 26 /*!< SCT EV6_STATE: STATEMSK26 Position */ #define SCT_EV6_STATE_STATEMSK26_Msk (0x01UL << SCT_EV6_STATE_STATEMSK26_Pos) /*!< SCT EV6_STATE: STATEMSK26 Mask */ #define SCT_EV6_STATE_STATEMSK27_Pos 27 /*!< SCT EV6_STATE: STATEMSK27 Position */ #define SCT_EV6_STATE_STATEMSK27_Msk (0x01UL << SCT_EV6_STATE_STATEMSK27_Pos) /*!< SCT EV6_STATE: STATEMSK27 Mask */ #define SCT_EV6_STATE_STATEMSK28_Pos 28 /*!< SCT EV6_STATE: STATEMSK28 Position */ #define SCT_EV6_STATE_STATEMSK28_Msk (0x01UL << SCT_EV6_STATE_STATEMSK28_Pos) /*!< SCT EV6_STATE: STATEMSK28 Mask */ #define SCT_EV6_STATE_STATEMSK29_Pos 29 /*!< SCT EV6_STATE: STATEMSK29 Position */ #define SCT_EV6_STATE_STATEMSK29_Msk (0x01UL << SCT_EV6_STATE_STATEMSK29_Pos) /*!< SCT EV6_STATE: STATEMSK29 Mask */ #define SCT_EV6_STATE_STATEMSK30_Pos 30 /*!< SCT EV6_STATE: STATEMSK30 Position */ #define SCT_EV6_STATE_STATEMSK30_Msk (0x01UL << SCT_EV6_STATE_STATEMSK30_Pos) /*!< SCT EV6_STATE: STATEMSK30 Mask */ #define SCT_EV6_STATE_STATEMSK31_Pos 31 /*!< SCT EV6_STATE: STATEMSK31 Position */ #define SCT_EV6_STATE_STATEMSK31_Msk (0x01UL << SCT_EV6_STATE_STATEMSK31_Pos) /*!< SCT EV6_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV6_CTRL -------------------------------- */ #define SCT_EV6_CTRL_MATCHSEL_Pos 0 /*!< SCT EV6_CTRL: MATCHSEL Position */ #define SCT_EV6_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV6_CTRL_MATCHSEL_Pos) /*!< SCT EV6_CTRL: MATCHSEL Mask */ #define SCT_EV6_CTRL_HEVENT_Pos 4 /*!< SCT EV6_CTRL: HEVENT Position */ #define SCT_EV6_CTRL_HEVENT_Msk (0x01UL << SCT_EV6_CTRL_HEVENT_Pos) /*!< SCT EV6_CTRL: HEVENT Mask */ #define SCT_EV6_CTRL_OUTSEL_Pos 5 /*!< SCT EV6_CTRL: OUTSEL Position */ #define SCT_EV6_CTRL_OUTSEL_Msk (0x01UL << SCT_EV6_CTRL_OUTSEL_Pos) /*!< SCT EV6_CTRL: OUTSEL Mask */ #define SCT_EV6_CTRL_IOSEL_Pos 6 /*!< SCT EV6_CTRL: IOSEL Position */ #define SCT_EV6_CTRL_IOSEL_Msk (0x0fUL << SCT_EV6_CTRL_IOSEL_Pos) /*!< SCT EV6_CTRL: IOSEL Mask */ #define SCT_EV6_CTRL_IOCOND_Pos 10 /*!< SCT EV6_CTRL: IOCOND Position */ #define SCT_EV6_CTRL_IOCOND_Msk (0x03UL << SCT_EV6_CTRL_IOCOND_Pos) /*!< SCT EV6_CTRL: IOCOND Mask */ #define SCT_EV6_CTRL_COMBMODE_Pos 12 /*!< SCT EV6_CTRL: COMBMODE Position */ #define SCT_EV6_CTRL_COMBMODE_Msk (0x03UL << SCT_EV6_CTRL_COMBMODE_Pos) /*!< SCT EV6_CTRL: COMBMODE Mask */ #define SCT_EV6_CTRL_STATELD_Pos 14 /*!< SCT EV6_CTRL: STATELD Position */ #define SCT_EV6_CTRL_STATELD_Msk (0x01UL << SCT_EV6_CTRL_STATELD_Pos) /*!< SCT EV6_CTRL: STATELD Mask */ #define SCT_EV6_CTRL_STATEV_Pos 15 /*!< SCT EV6_CTRL: STATEV Position */ #define SCT_EV6_CTRL_STATEV_Msk (0x1fUL << SCT_EV6_CTRL_STATEV_Pos) /*!< SCT EV6_CTRL: STATEV Mask */ #define SCT_EV6_CTRL_MATCHMEM_Pos 20 /*!< SCT EV6_CTRL: MATCHMEM Position */ #define SCT_EV6_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV6_CTRL_MATCHMEM_Pos) /*!< SCT EV6_CTRL: MATCHMEM Mask */ #define SCT_EV6_CTRL_DIRECTION_Pos 21 /*!< SCT EV6_CTRL: DIRECTION Position */ #define SCT_EV6_CTRL_DIRECTION_Msk (0x03UL << SCT_EV6_CTRL_DIRECTION_Pos) /*!< SCT EV6_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV7_STATE ------------------------------- */ #define SCT_EV7_STATE_STATEMSK0_Pos 0 /*!< SCT EV7_STATE: STATEMSK0 Position */ #define SCT_EV7_STATE_STATEMSK0_Msk (0x01UL << SCT_EV7_STATE_STATEMSK0_Pos) /*!< SCT EV7_STATE: STATEMSK0 Mask */ #define SCT_EV7_STATE_STATEMSK1_Pos 1 /*!< SCT EV7_STATE: STATEMSK1 Position */ #define SCT_EV7_STATE_STATEMSK1_Msk (0x01UL << SCT_EV7_STATE_STATEMSK1_Pos) /*!< SCT EV7_STATE: STATEMSK1 Mask */ #define SCT_EV7_STATE_STATEMSK2_Pos 2 /*!< SCT EV7_STATE: STATEMSK2 Position */ #define SCT_EV7_STATE_STATEMSK2_Msk (0x01UL << SCT_EV7_STATE_STATEMSK2_Pos) /*!< SCT EV7_STATE: STATEMSK2 Mask */ #define SCT_EV7_STATE_STATEMSK3_Pos 3 /*!< SCT EV7_STATE: STATEMSK3 Position */ #define SCT_EV7_STATE_STATEMSK3_Msk (0x01UL << SCT_EV7_STATE_STATEMSK3_Pos) /*!< SCT EV7_STATE: STATEMSK3 Mask */ #define SCT_EV7_STATE_STATEMSK4_Pos 4 /*!< SCT EV7_STATE: STATEMSK4 Position */ #define SCT_EV7_STATE_STATEMSK4_Msk (0x01UL << SCT_EV7_STATE_STATEMSK4_Pos) /*!< SCT EV7_STATE: STATEMSK4 Mask */ #define SCT_EV7_STATE_STATEMSK5_Pos 5 /*!< SCT EV7_STATE: STATEMSK5 Position */ #define SCT_EV7_STATE_STATEMSK5_Msk (0x01UL << SCT_EV7_STATE_STATEMSK5_Pos) /*!< SCT EV7_STATE: STATEMSK5 Mask */ #define SCT_EV7_STATE_STATEMSK6_Pos 6 /*!< SCT EV7_STATE: STATEMSK6 Position */ #define SCT_EV7_STATE_STATEMSK6_Msk (0x01UL << SCT_EV7_STATE_STATEMSK6_Pos) /*!< SCT EV7_STATE: STATEMSK6 Mask */ #define SCT_EV7_STATE_STATEMSK7_Pos 7 /*!< SCT EV7_STATE: STATEMSK7 Position */ #define SCT_EV7_STATE_STATEMSK7_Msk (0x01UL << SCT_EV7_STATE_STATEMSK7_Pos) /*!< SCT EV7_STATE: STATEMSK7 Mask */ #define SCT_EV7_STATE_STATEMSK8_Pos 8 /*!< SCT EV7_STATE: STATEMSK8 Position */ #define SCT_EV7_STATE_STATEMSK8_Msk (0x01UL << SCT_EV7_STATE_STATEMSK8_Pos) /*!< SCT EV7_STATE: STATEMSK8 Mask */ #define SCT_EV7_STATE_STATEMSK9_Pos 9 /*!< SCT EV7_STATE: STATEMSK9 Position */ #define SCT_EV7_STATE_STATEMSK9_Msk (0x01UL << SCT_EV7_STATE_STATEMSK9_Pos) /*!< SCT EV7_STATE: STATEMSK9 Mask */ #define SCT_EV7_STATE_STATEMSK10_Pos 10 /*!< SCT EV7_STATE: STATEMSK10 Position */ #define SCT_EV7_STATE_STATEMSK10_Msk (0x01UL << SCT_EV7_STATE_STATEMSK10_Pos) /*!< SCT EV7_STATE: STATEMSK10 Mask */ #define SCT_EV7_STATE_STATEMSK11_Pos 11 /*!< SCT EV7_STATE: STATEMSK11 Position */ #define SCT_EV7_STATE_STATEMSK11_Msk (0x01UL << SCT_EV7_STATE_STATEMSK11_Pos) /*!< SCT EV7_STATE: STATEMSK11 Mask */ #define SCT_EV7_STATE_STATEMSK12_Pos 12 /*!< SCT EV7_STATE: STATEMSK12 Position */ #define SCT_EV7_STATE_STATEMSK12_Msk (0x01UL << SCT_EV7_STATE_STATEMSK12_Pos) /*!< SCT EV7_STATE: STATEMSK12 Mask */ #define SCT_EV7_STATE_STATEMSK13_Pos 13 /*!< SCT EV7_STATE: STATEMSK13 Position */ #define SCT_EV7_STATE_STATEMSK13_Msk (0x01UL << SCT_EV7_STATE_STATEMSK13_Pos) /*!< SCT EV7_STATE: STATEMSK13 Mask */ #define SCT_EV7_STATE_STATEMSK14_Pos 14 /*!< SCT EV7_STATE: STATEMSK14 Position */ #define SCT_EV7_STATE_STATEMSK14_Msk (0x01UL << SCT_EV7_STATE_STATEMSK14_Pos) /*!< SCT EV7_STATE: STATEMSK14 Mask */ #define SCT_EV7_STATE_STATEMSK15_Pos 15 /*!< SCT EV7_STATE: STATEMSK15 Position */ #define SCT_EV7_STATE_STATEMSK15_Msk (0x01UL << SCT_EV7_STATE_STATEMSK15_Pos) /*!< SCT EV7_STATE: STATEMSK15 Mask */ #define SCT_EV7_STATE_STATEMSK16_Pos 16 /*!< SCT EV7_STATE: STATEMSK16 Position */ #define SCT_EV7_STATE_STATEMSK16_Msk (0x01UL << SCT_EV7_STATE_STATEMSK16_Pos) /*!< SCT EV7_STATE: STATEMSK16 Mask */ #define SCT_EV7_STATE_STATEMSK17_Pos 17 /*!< SCT EV7_STATE: STATEMSK17 Position */ #define SCT_EV7_STATE_STATEMSK17_Msk (0x01UL << SCT_EV7_STATE_STATEMSK17_Pos) /*!< SCT EV7_STATE: STATEMSK17 Mask */ #define SCT_EV7_STATE_STATEMSK18_Pos 18 /*!< SCT EV7_STATE: STATEMSK18 Position */ #define SCT_EV7_STATE_STATEMSK18_Msk (0x01UL << SCT_EV7_STATE_STATEMSK18_Pos) /*!< SCT EV7_STATE: STATEMSK18 Mask */ #define SCT_EV7_STATE_STATEMSK19_Pos 19 /*!< SCT EV7_STATE: STATEMSK19 Position */ #define SCT_EV7_STATE_STATEMSK19_Msk (0x01UL << SCT_EV7_STATE_STATEMSK19_Pos) /*!< SCT EV7_STATE: STATEMSK19 Mask */ #define SCT_EV7_STATE_STATEMSK20_Pos 20 /*!< SCT EV7_STATE: STATEMSK20 Position */ #define SCT_EV7_STATE_STATEMSK20_Msk (0x01UL << SCT_EV7_STATE_STATEMSK20_Pos) /*!< SCT EV7_STATE: STATEMSK20 Mask */ #define SCT_EV7_STATE_STATEMSK21_Pos 21 /*!< SCT EV7_STATE: STATEMSK21 Position */ #define SCT_EV7_STATE_STATEMSK21_Msk (0x01UL << SCT_EV7_STATE_STATEMSK21_Pos) /*!< SCT EV7_STATE: STATEMSK21 Mask */ #define SCT_EV7_STATE_STATEMSK22_Pos 22 /*!< SCT EV7_STATE: STATEMSK22 Position */ #define SCT_EV7_STATE_STATEMSK22_Msk (0x01UL << SCT_EV7_STATE_STATEMSK22_Pos) /*!< SCT EV7_STATE: STATEMSK22 Mask */ #define SCT_EV7_STATE_STATEMSK23_Pos 23 /*!< SCT EV7_STATE: STATEMSK23 Position */ #define SCT_EV7_STATE_STATEMSK23_Msk (0x01UL << SCT_EV7_STATE_STATEMSK23_Pos) /*!< SCT EV7_STATE: STATEMSK23 Mask */ #define SCT_EV7_STATE_STATEMSK24_Pos 24 /*!< SCT EV7_STATE: STATEMSK24 Position */ #define SCT_EV7_STATE_STATEMSK24_Msk (0x01UL << SCT_EV7_STATE_STATEMSK24_Pos) /*!< SCT EV7_STATE: STATEMSK24 Mask */ #define SCT_EV7_STATE_STATEMSK25_Pos 25 /*!< SCT EV7_STATE: STATEMSK25 Position */ #define SCT_EV7_STATE_STATEMSK25_Msk (0x01UL << SCT_EV7_STATE_STATEMSK25_Pos) /*!< SCT EV7_STATE: STATEMSK25 Mask */ #define SCT_EV7_STATE_STATEMSK26_Pos 26 /*!< SCT EV7_STATE: STATEMSK26 Position */ #define SCT_EV7_STATE_STATEMSK26_Msk (0x01UL << SCT_EV7_STATE_STATEMSK26_Pos) /*!< SCT EV7_STATE: STATEMSK26 Mask */ #define SCT_EV7_STATE_STATEMSK27_Pos 27 /*!< SCT EV7_STATE: STATEMSK27 Position */ #define SCT_EV7_STATE_STATEMSK27_Msk (0x01UL << SCT_EV7_STATE_STATEMSK27_Pos) /*!< SCT EV7_STATE: STATEMSK27 Mask */ #define SCT_EV7_STATE_STATEMSK28_Pos 28 /*!< SCT EV7_STATE: STATEMSK28 Position */ #define SCT_EV7_STATE_STATEMSK28_Msk (0x01UL << SCT_EV7_STATE_STATEMSK28_Pos) /*!< SCT EV7_STATE: STATEMSK28 Mask */ #define SCT_EV7_STATE_STATEMSK29_Pos 29 /*!< SCT EV7_STATE: STATEMSK29 Position */ #define SCT_EV7_STATE_STATEMSK29_Msk (0x01UL << SCT_EV7_STATE_STATEMSK29_Pos) /*!< SCT EV7_STATE: STATEMSK29 Mask */ #define SCT_EV7_STATE_STATEMSK30_Pos 30 /*!< SCT EV7_STATE: STATEMSK30 Position */ #define SCT_EV7_STATE_STATEMSK30_Msk (0x01UL << SCT_EV7_STATE_STATEMSK30_Pos) /*!< SCT EV7_STATE: STATEMSK30 Mask */ #define SCT_EV7_STATE_STATEMSK31_Pos 31 /*!< SCT EV7_STATE: STATEMSK31 Position */ #define SCT_EV7_STATE_STATEMSK31_Msk (0x01UL << SCT_EV7_STATE_STATEMSK31_Pos) /*!< SCT EV7_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV7_CTRL -------------------------------- */ #define SCT_EV7_CTRL_MATCHSEL_Pos 0 /*!< SCT EV7_CTRL: MATCHSEL Position */ #define SCT_EV7_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV7_CTRL_MATCHSEL_Pos) /*!< SCT EV7_CTRL: MATCHSEL Mask */ #define SCT_EV7_CTRL_HEVENT_Pos 4 /*!< SCT EV7_CTRL: HEVENT Position */ #define SCT_EV7_CTRL_HEVENT_Msk (0x01UL << SCT_EV7_CTRL_HEVENT_Pos) /*!< SCT EV7_CTRL: HEVENT Mask */ #define SCT_EV7_CTRL_OUTSEL_Pos 5 /*!< SCT EV7_CTRL: OUTSEL Position */ #define SCT_EV7_CTRL_OUTSEL_Msk (0x01UL << SCT_EV7_CTRL_OUTSEL_Pos) /*!< SCT EV7_CTRL: OUTSEL Mask */ #define SCT_EV7_CTRL_IOSEL_Pos 6 /*!< SCT EV7_CTRL: IOSEL Position */ #define SCT_EV7_CTRL_IOSEL_Msk (0x0fUL << SCT_EV7_CTRL_IOSEL_Pos) /*!< SCT EV7_CTRL: IOSEL Mask */ #define SCT_EV7_CTRL_IOCOND_Pos 10 /*!< SCT EV7_CTRL: IOCOND Position */ #define SCT_EV7_CTRL_IOCOND_Msk (0x03UL << SCT_EV7_CTRL_IOCOND_Pos) /*!< SCT EV7_CTRL: IOCOND Mask */ #define SCT_EV7_CTRL_COMBMODE_Pos 12 /*!< SCT EV7_CTRL: COMBMODE Position */ #define SCT_EV7_CTRL_COMBMODE_Msk (0x03UL << SCT_EV7_CTRL_COMBMODE_Pos) /*!< SCT EV7_CTRL: COMBMODE Mask */ #define SCT_EV7_CTRL_STATELD_Pos 14 /*!< SCT EV7_CTRL: STATELD Position */ #define SCT_EV7_CTRL_STATELD_Msk (0x01UL << SCT_EV7_CTRL_STATELD_Pos) /*!< SCT EV7_CTRL: STATELD Mask */ #define SCT_EV7_CTRL_STATEV_Pos 15 /*!< SCT EV7_CTRL: STATEV Position */ #define SCT_EV7_CTRL_STATEV_Msk (0x1fUL << SCT_EV7_CTRL_STATEV_Pos) /*!< SCT EV7_CTRL: STATEV Mask */ #define SCT_EV7_CTRL_MATCHMEM_Pos 20 /*!< SCT EV7_CTRL: MATCHMEM Position */ #define SCT_EV7_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV7_CTRL_MATCHMEM_Pos) /*!< SCT EV7_CTRL: MATCHMEM Mask */ #define SCT_EV7_CTRL_DIRECTION_Pos 21 /*!< SCT EV7_CTRL: DIRECTION Position */ #define SCT_EV7_CTRL_DIRECTION_Msk (0x03UL << SCT_EV7_CTRL_DIRECTION_Pos) /*!< SCT EV7_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV8_STATE ------------------------------- */ #define SCT_EV8_STATE_STATEMSK0_Pos 0 /*!< SCT EV8_STATE: STATEMSK0 Position */ #define SCT_EV8_STATE_STATEMSK0_Msk (0x01UL << SCT_EV8_STATE_STATEMSK0_Pos) /*!< SCT EV8_STATE: STATEMSK0 Mask */ #define SCT_EV8_STATE_STATEMSK1_Pos 1 /*!< SCT EV8_STATE: STATEMSK1 Position */ #define SCT_EV8_STATE_STATEMSK1_Msk (0x01UL << SCT_EV8_STATE_STATEMSK1_Pos) /*!< SCT EV8_STATE: STATEMSK1 Mask */ #define SCT_EV8_STATE_STATEMSK2_Pos 2 /*!< SCT EV8_STATE: STATEMSK2 Position */ #define SCT_EV8_STATE_STATEMSK2_Msk (0x01UL << SCT_EV8_STATE_STATEMSK2_Pos) /*!< SCT EV8_STATE: STATEMSK2 Mask */ #define SCT_EV8_STATE_STATEMSK3_Pos 3 /*!< SCT EV8_STATE: STATEMSK3 Position */ #define SCT_EV8_STATE_STATEMSK3_Msk (0x01UL << SCT_EV8_STATE_STATEMSK3_Pos) /*!< SCT EV8_STATE: STATEMSK3 Mask */ #define SCT_EV8_STATE_STATEMSK4_Pos 4 /*!< SCT EV8_STATE: STATEMSK4 Position */ #define SCT_EV8_STATE_STATEMSK4_Msk (0x01UL << SCT_EV8_STATE_STATEMSK4_Pos) /*!< SCT EV8_STATE: STATEMSK4 Mask */ #define SCT_EV8_STATE_STATEMSK5_Pos 5 /*!< SCT EV8_STATE: STATEMSK5 Position */ #define SCT_EV8_STATE_STATEMSK5_Msk (0x01UL << SCT_EV8_STATE_STATEMSK5_Pos) /*!< SCT EV8_STATE: STATEMSK5 Mask */ #define SCT_EV8_STATE_STATEMSK6_Pos 6 /*!< SCT EV8_STATE: STATEMSK6 Position */ #define SCT_EV8_STATE_STATEMSK6_Msk (0x01UL << SCT_EV8_STATE_STATEMSK6_Pos) /*!< SCT EV8_STATE: STATEMSK6 Mask */ #define SCT_EV8_STATE_STATEMSK7_Pos 7 /*!< SCT EV8_STATE: STATEMSK7 Position */ #define SCT_EV8_STATE_STATEMSK7_Msk (0x01UL << SCT_EV8_STATE_STATEMSK7_Pos) /*!< SCT EV8_STATE: STATEMSK7 Mask */ #define SCT_EV8_STATE_STATEMSK8_Pos 8 /*!< SCT EV8_STATE: STATEMSK8 Position */ #define SCT_EV8_STATE_STATEMSK8_Msk (0x01UL << SCT_EV8_STATE_STATEMSK8_Pos) /*!< SCT EV8_STATE: STATEMSK8 Mask */ #define SCT_EV8_STATE_STATEMSK9_Pos 9 /*!< SCT EV8_STATE: STATEMSK9 Position */ #define SCT_EV8_STATE_STATEMSK9_Msk (0x01UL << SCT_EV8_STATE_STATEMSK9_Pos) /*!< SCT EV8_STATE: STATEMSK9 Mask */ #define SCT_EV8_STATE_STATEMSK10_Pos 10 /*!< SCT EV8_STATE: STATEMSK10 Position */ #define SCT_EV8_STATE_STATEMSK10_Msk (0x01UL << SCT_EV8_STATE_STATEMSK10_Pos) /*!< SCT EV8_STATE: STATEMSK10 Mask */ #define SCT_EV8_STATE_STATEMSK11_Pos 11 /*!< SCT EV8_STATE: STATEMSK11 Position */ #define SCT_EV8_STATE_STATEMSK11_Msk (0x01UL << SCT_EV8_STATE_STATEMSK11_Pos) /*!< SCT EV8_STATE: STATEMSK11 Mask */ #define SCT_EV8_STATE_STATEMSK12_Pos 12 /*!< SCT EV8_STATE: STATEMSK12 Position */ #define SCT_EV8_STATE_STATEMSK12_Msk (0x01UL << SCT_EV8_STATE_STATEMSK12_Pos) /*!< SCT EV8_STATE: STATEMSK12 Mask */ #define SCT_EV8_STATE_STATEMSK13_Pos 13 /*!< SCT EV8_STATE: STATEMSK13 Position */ #define SCT_EV8_STATE_STATEMSK13_Msk (0x01UL << SCT_EV8_STATE_STATEMSK13_Pos) /*!< SCT EV8_STATE: STATEMSK13 Mask */ #define SCT_EV8_STATE_STATEMSK14_Pos 14 /*!< SCT EV8_STATE: STATEMSK14 Position */ #define SCT_EV8_STATE_STATEMSK14_Msk (0x01UL << SCT_EV8_STATE_STATEMSK14_Pos) /*!< SCT EV8_STATE: STATEMSK14 Mask */ #define SCT_EV8_STATE_STATEMSK15_Pos 15 /*!< SCT EV8_STATE: STATEMSK15 Position */ #define SCT_EV8_STATE_STATEMSK15_Msk (0x01UL << SCT_EV8_STATE_STATEMSK15_Pos) /*!< SCT EV8_STATE: STATEMSK15 Mask */ #define SCT_EV8_STATE_STATEMSK16_Pos 16 /*!< SCT EV8_STATE: STATEMSK16 Position */ #define SCT_EV8_STATE_STATEMSK16_Msk (0x01UL << SCT_EV8_STATE_STATEMSK16_Pos) /*!< SCT EV8_STATE: STATEMSK16 Mask */ #define SCT_EV8_STATE_STATEMSK17_Pos 17 /*!< SCT EV8_STATE: STATEMSK17 Position */ #define SCT_EV8_STATE_STATEMSK17_Msk (0x01UL << SCT_EV8_STATE_STATEMSK17_Pos) /*!< SCT EV8_STATE: STATEMSK17 Mask */ #define SCT_EV8_STATE_STATEMSK18_Pos 18 /*!< SCT EV8_STATE: STATEMSK18 Position */ #define SCT_EV8_STATE_STATEMSK18_Msk (0x01UL << SCT_EV8_STATE_STATEMSK18_Pos) /*!< SCT EV8_STATE: STATEMSK18 Mask */ #define SCT_EV8_STATE_STATEMSK19_Pos 19 /*!< SCT EV8_STATE: STATEMSK19 Position */ #define SCT_EV8_STATE_STATEMSK19_Msk (0x01UL << SCT_EV8_STATE_STATEMSK19_Pos) /*!< SCT EV8_STATE: STATEMSK19 Mask */ #define SCT_EV8_STATE_STATEMSK20_Pos 20 /*!< SCT EV8_STATE: STATEMSK20 Position */ #define SCT_EV8_STATE_STATEMSK20_Msk (0x01UL << SCT_EV8_STATE_STATEMSK20_Pos) /*!< SCT EV8_STATE: STATEMSK20 Mask */ #define SCT_EV8_STATE_STATEMSK21_Pos 21 /*!< SCT EV8_STATE: STATEMSK21 Position */ #define SCT_EV8_STATE_STATEMSK21_Msk (0x01UL << SCT_EV8_STATE_STATEMSK21_Pos) /*!< SCT EV8_STATE: STATEMSK21 Mask */ #define SCT_EV8_STATE_STATEMSK22_Pos 22 /*!< SCT EV8_STATE: STATEMSK22 Position */ #define SCT_EV8_STATE_STATEMSK22_Msk (0x01UL << SCT_EV8_STATE_STATEMSK22_Pos) /*!< SCT EV8_STATE: STATEMSK22 Mask */ #define SCT_EV8_STATE_STATEMSK23_Pos 23 /*!< SCT EV8_STATE: STATEMSK23 Position */ #define SCT_EV8_STATE_STATEMSK23_Msk (0x01UL << SCT_EV8_STATE_STATEMSK23_Pos) /*!< SCT EV8_STATE: STATEMSK23 Mask */ #define SCT_EV8_STATE_STATEMSK24_Pos 24 /*!< SCT EV8_STATE: STATEMSK24 Position */ #define SCT_EV8_STATE_STATEMSK24_Msk (0x01UL << SCT_EV8_STATE_STATEMSK24_Pos) /*!< SCT EV8_STATE: STATEMSK24 Mask */ #define SCT_EV8_STATE_STATEMSK25_Pos 25 /*!< SCT EV8_STATE: STATEMSK25 Position */ #define SCT_EV8_STATE_STATEMSK25_Msk (0x01UL << SCT_EV8_STATE_STATEMSK25_Pos) /*!< SCT EV8_STATE: STATEMSK25 Mask */ #define SCT_EV8_STATE_STATEMSK26_Pos 26 /*!< SCT EV8_STATE: STATEMSK26 Position */ #define SCT_EV8_STATE_STATEMSK26_Msk (0x01UL << SCT_EV8_STATE_STATEMSK26_Pos) /*!< SCT EV8_STATE: STATEMSK26 Mask */ #define SCT_EV8_STATE_STATEMSK27_Pos 27 /*!< SCT EV8_STATE: STATEMSK27 Position */ #define SCT_EV8_STATE_STATEMSK27_Msk (0x01UL << SCT_EV8_STATE_STATEMSK27_Pos) /*!< SCT EV8_STATE: STATEMSK27 Mask */ #define SCT_EV8_STATE_STATEMSK28_Pos 28 /*!< SCT EV8_STATE: STATEMSK28 Position */ #define SCT_EV8_STATE_STATEMSK28_Msk (0x01UL << SCT_EV8_STATE_STATEMSK28_Pos) /*!< SCT EV8_STATE: STATEMSK28 Mask */ #define SCT_EV8_STATE_STATEMSK29_Pos 29 /*!< SCT EV8_STATE: STATEMSK29 Position */ #define SCT_EV8_STATE_STATEMSK29_Msk (0x01UL << SCT_EV8_STATE_STATEMSK29_Pos) /*!< SCT EV8_STATE: STATEMSK29 Mask */ #define SCT_EV8_STATE_STATEMSK30_Pos 30 /*!< SCT EV8_STATE: STATEMSK30 Position */ #define SCT_EV8_STATE_STATEMSK30_Msk (0x01UL << SCT_EV8_STATE_STATEMSK30_Pos) /*!< SCT EV8_STATE: STATEMSK30 Mask */ #define SCT_EV8_STATE_STATEMSK31_Pos 31 /*!< SCT EV8_STATE: STATEMSK31 Position */ #define SCT_EV8_STATE_STATEMSK31_Msk (0x01UL << SCT_EV8_STATE_STATEMSK31_Pos) /*!< SCT EV8_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV8_CTRL -------------------------------- */ #define SCT_EV8_CTRL_MATCHSEL_Pos 0 /*!< SCT EV8_CTRL: MATCHSEL Position */ #define SCT_EV8_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV8_CTRL_MATCHSEL_Pos) /*!< SCT EV8_CTRL: MATCHSEL Mask */ #define SCT_EV8_CTRL_HEVENT_Pos 4 /*!< SCT EV8_CTRL: HEVENT Position */ #define SCT_EV8_CTRL_HEVENT_Msk (0x01UL << SCT_EV8_CTRL_HEVENT_Pos) /*!< SCT EV8_CTRL: HEVENT Mask */ #define SCT_EV8_CTRL_OUTSEL_Pos 5 /*!< SCT EV8_CTRL: OUTSEL Position */ #define SCT_EV8_CTRL_OUTSEL_Msk (0x01UL << SCT_EV8_CTRL_OUTSEL_Pos) /*!< SCT EV8_CTRL: OUTSEL Mask */ #define SCT_EV8_CTRL_IOSEL_Pos 6 /*!< SCT EV8_CTRL: IOSEL Position */ #define SCT_EV8_CTRL_IOSEL_Msk (0x0fUL << SCT_EV8_CTRL_IOSEL_Pos) /*!< SCT EV8_CTRL: IOSEL Mask */ #define SCT_EV8_CTRL_IOCOND_Pos 10 /*!< SCT EV8_CTRL: IOCOND Position */ #define SCT_EV8_CTRL_IOCOND_Msk (0x03UL << SCT_EV8_CTRL_IOCOND_Pos) /*!< SCT EV8_CTRL: IOCOND Mask */ #define SCT_EV8_CTRL_COMBMODE_Pos 12 /*!< SCT EV8_CTRL: COMBMODE Position */ #define SCT_EV8_CTRL_COMBMODE_Msk (0x03UL << SCT_EV8_CTRL_COMBMODE_Pos) /*!< SCT EV8_CTRL: COMBMODE Mask */ #define SCT_EV8_CTRL_STATELD_Pos 14 /*!< SCT EV8_CTRL: STATELD Position */ #define SCT_EV8_CTRL_STATELD_Msk (0x01UL << SCT_EV8_CTRL_STATELD_Pos) /*!< SCT EV8_CTRL: STATELD Mask */ #define SCT_EV8_CTRL_STATEV_Pos 15 /*!< SCT EV8_CTRL: STATEV Position */ #define SCT_EV8_CTRL_STATEV_Msk (0x1fUL << SCT_EV8_CTRL_STATEV_Pos) /*!< SCT EV8_CTRL: STATEV Mask */ #define SCT_EV8_CTRL_MATCHMEM_Pos 20 /*!< SCT EV8_CTRL: MATCHMEM Position */ #define SCT_EV8_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV8_CTRL_MATCHMEM_Pos) /*!< SCT EV8_CTRL: MATCHMEM Mask */ #define SCT_EV8_CTRL_DIRECTION_Pos 21 /*!< SCT EV8_CTRL: DIRECTION Position */ #define SCT_EV8_CTRL_DIRECTION_Msk (0x03UL << SCT_EV8_CTRL_DIRECTION_Pos) /*!< SCT EV8_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_EV9_STATE ------------------------------- */ #define SCT_EV9_STATE_STATEMSK0_Pos 0 /*!< SCT EV9_STATE: STATEMSK0 Position */ #define SCT_EV9_STATE_STATEMSK0_Msk (0x01UL << SCT_EV9_STATE_STATEMSK0_Pos) /*!< SCT EV9_STATE: STATEMSK0 Mask */ #define SCT_EV9_STATE_STATEMSK1_Pos 1 /*!< SCT EV9_STATE: STATEMSK1 Position */ #define SCT_EV9_STATE_STATEMSK1_Msk (0x01UL << SCT_EV9_STATE_STATEMSK1_Pos) /*!< SCT EV9_STATE: STATEMSK1 Mask */ #define SCT_EV9_STATE_STATEMSK2_Pos 2 /*!< SCT EV9_STATE: STATEMSK2 Position */ #define SCT_EV9_STATE_STATEMSK2_Msk (0x01UL << SCT_EV9_STATE_STATEMSK2_Pos) /*!< SCT EV9_STATE: STATEMSK2 Mask */ #define SCT_EV9_STATE_STATEMSK3_Pos 3 /*!< SCT EV9_STATE: STATEMSK3 Position */ #define SCT_EV9_STATE_STATEMSK3_Msk (0x01UL << SCT_EV9_STATE_STATEMSK3_Pos) /*!< SCT EV9_STATE: STATEMSK3 Mask */ #define SCT_EV9_STATE_STATEMSK4_Pos 4 /*!< SCT EV9_STATE: STATEMSK4 Position */ #define SCT_EV9_STATE_STATEMSK4_Msk (0x01UL << SCT_EV9_STATE_STATEMSK4_Pos) /*!< SCT EV9_STATE: STATEMSK4 Mask */ #define SCT_EV9_STATE_STATEMSK5_Pos 5 /*!< SCT EV9_STATE: STATEMSK5 Position */ #define SCT_EV9_STATE_STATEMSK5_Msk (0x01UL << SCT_EV9_STATE_STATEMSK5_Pos) /*!< SCT EV9_STATE: STATEMSK5 Mask */ #define SCT_EV9_STATE_STATEMSK6_Pos 6 /*!< SCT EV9_STATE: STATEMSK6 Position */ #define SCT_EV9_STATE_STATEMSK6_Msk (0x01UL << SCT_EV9_STATE_STATEMSK6_Pos) /*!< SCT EV9_STATE: STATEMSK6 Mask */ #define SCT_EV9_STATE_STATEMSK7_Pos 7 /*!< SCT EV9_STATE: STATEMSK7 Position */ #define SCT_EV9_STATE_STATEMSK7_Msk (0x01UL << SCT_EV9_STATE_STATEMSK7_Pos) /*!< SCT EV9_STATE: STATEMSK7 Mask */ #define SCT_EV9_STATE_STATEMSK8_Pos 8 /*!< SCT EV9_STATE: STATEMSK8 Position */ #define SCT_EV9_STATE_STATEMSK8_Msk (0x01UL << SCT_EV9_STATE_STATEMSK8_Pos) /*!< SCT EV9_STATE: STATEMSK8 Mask */ #define SCT_EV9_STATE_STATEMSK9_Pos 9 /*!< SCT EV9_STATE: STATEMSK9 Position */ #define SCT_EV9_STATE_STATEMSK9_Msk (0x01UL << SCT_EV9_STATE_STATEMSK9_Pos) /*!< SCT EV9_STATE: STATEMSK9 Mask */ #define SCT_EV9_STATE_STATEMSK10_Pos 10 /*!< SCT EV9_STATE: STATEMSK10 Position */ #define SCT_EV9_STATE_STATEMSK10_Msk (0x01UL << SCT_EV9_STATE_STATEMSK10_Pos) /*!< SCT EV9_STATE: STATEMSK10 Mask */ #define SCT_EV9_STATE_STATEMSK11_Pos 11 /*!< SCT EV9_STATE: STATEMSK11 Position */ #define SCT_EV9_STATE_STATEMSK11_Msk (0x01UL << SCT_EV9_STATE_STATEMSK11_Pos) /*!< SCT EV9_STATE: STATEMSK11 Mask */ #define SCT_EV9_STATE_STATEMSK12_Pos 12 /*!< SCT EV9_STATE: STATEMSK12 Position */ #define SCT_EV9_STATE_STATEMSK12_Msk (0x01UL << SCT_EV9_STATE_STATEMSK12_Pos) /*!< SCT EV9_STATE: STATEMSK12 Mask */ #define SCT_EV9_STATE_STATEMSK13_Pos 13 /*!< SCT EV9_STATE: STATEMSK13 Position */ #define SCT_EV9_STATE_STATEMSK13_Msk (0x01UL << SCT_EV9_STATE_STATEMSK13_Pos) /*!< SCT EV9_STATE: STATEMSK13 Mask */ #define SCT_EV9_STATE_STATEMSK14_Pos 14 /*!< SCT EV9_STATE: STATEMSK14 Position */ #define SCT_EV9_STATE_STATEMSK14_Msk (0x01UL << SCT_EV9_STATE_STATEMSK14_Pos) /*!< SCT EV9_STATE: STATEMSK14 Mask */ #define SCT_EV9_STATE_STATEMSK15_Pos 15 /*!< SCT EV9_STATE: STATEMSK15 Position */ #define SCT_EV9_STATE_STATEMSK15_Msk (0x01UL << SCT_EV9_STATE_STATEMSK15_Pos) /*!< SCT EV9_STATE: STATEMSK15 Mask */ #define SCT_EV9_STATE_STATEMSK16_Pos 16 /*!< SCT EV9_STATE: STATEMSK16 Position */ #define SCT_EV9_STATE_STATEMSK16_Msk (0x01UL << SCT_EV9_STATE_STATEMSK16_Pos) /*!< SCT EV9_STATE: STATEMSK16 Mask */ #define SCT_EV9_STATE_STATEMSK17_Pos 17 /*!< SCT EV9_STATE: STATEMSK17 Position */ #define SCT_EV9_STATE_STATEMSK17_Msk (0x01UL << SCT_EV9_STATE_STATEMSK17_Pos) /*!< SCT EV9_STATE: STATEMSK17 Mask */ #define SCT_EV9_STATE_STATEMSK18_Pos 18 /*!< SCT EV9_STATE: STATEMSK18 Position */ #define SCT_EV9_STATE_STATEMSK18_Msk (0x01UL << SCT_EV9_STATE_STATEMSK18_Pos) /*!< SCT EV9_STATE: STATEMSK18 Mask */ #define SCT_EV9_STATE_STATEMSK19_Pos 19 /*!< SCT EV9_STATE: STATEMSK19 Position */ #define SCT_EV9_STATE_STATEMSK19_Msk (0x01UL << SCT_EV9_STATE_STATEMSK19_Pos) /*!< SCT EV9_STATE: STATEMSK19 Mask */ #define SCT_EV9_STATE_STATEMSK20_Pos 20 /*!< SCT EV9_STATE: STATEMSK20 Position */ #define SCT_EV9_STATE_STATEMSK20_Msk (0x01UL << SCT_EV9_STATE_STATEMSK20_Pos) /*!< SCT EV9_STATE: STATEMSK20 Mask */ #define SCT_EV9_STATE_STATEMSK21_Pos 21 /*!< SCT EV9_STATE: STATEMSK21 Position */ #define SCT_EV9_STATE_STATEMSK21_Msk (0x01UL << SCT_EV9_STATE_STATEMSK21_Pos) /*!< SCT EV9_STATE: STATEMSK21 Mask */ #define SCT_EV9_STATE_STATEMSK22_Pos 22 /*!< SCT EV9_STATE: STATEMSK22 Position */ #define SCT_EV9_STATE_STATEMSK22_Msk (0x01UL << SCT_EV9_STATE_STATEMSK22_Pos) /*!< SCT EV9_STATE: STATEMSK22 Mask */ #define SCT_EV9_STATE_STATEMSK23_Pos 23 /*!< SCT EV9_STATE: STATEMSK23 Position */ #define SCT_EV9_STATE_STATEMSK23_Msk (0x01UL << SCT_EV9_STATE_STATEMSK23_Pos) /*!< SCT EV9_STATE: STATEMSK23 Mask */ #define SCT_EV9_STATE_STATEMSK24_Pos 24 /*!< SCT EV9_STATE: STATEMSK24 Position */ #define SCT_EV9_STATE_STATEMSK24_Msk (0x01UL << SCT_EV9_STATE_STATEMSK24_Pos) /*!< SCT EV9_STATE: STATEMSK24 Mask */ #define SCT_EV9_STATE_STATEMSK25_Pos 25 /*!< SCT EV9_STATE: STATEMSK25 Position */ #define SCT_EV9_STATE_STATEMSK25_Msk (0x01UL << SCT_EV9_STATE_STATEMSK25_Pos) /*!< SCT EV9_STATE: STATEMSK25 Mask */ #define SCT_EV9_STATE_STATEMSK26_Pos 26 /*!< SCT EV9_STATE: STATEMSK26 Position */ #define SCT_EV9_STATE_STATEMSK26_Msk (0x01UL << SCT_EV9_STATE_STATEMSK26_Pos) /*!< SCT EV9_STATE: STATEMSK26 Mask */ #define SCT_EV9_STATE_STATEMSK27_Pos 27 /*!< SCT EV9_STATE: STATEMSK27 Position */ #define SCT_EV9_STATE_STATEMSK27_Msk (0x01UL << SCT_EV9_STATE_STATEMSK27_Pos) /*!< SCT EV9_STATE: STATEMSK27 Mask */ #define SCT_EV9_STATE_STATEMSK28_Pos 28 /*!< SCT EV9_STATE: STATEMSK28 Position */ #define SCT_EV9_STATE_STATEMSK28_Msk (0x01UL << SCT_EV9_STATE_STATEMSK28_Pos) /*!< SCT EV9_STATE: STATEMSK28 Mask */ #define SCT_EV9_STATE_STATEMSK29_Pos 29 /*!< SCT EV9_STATE: STATEMSK29 Position */ #define SCT_EV9_STATE_STATEMSK29_Msk (0x01UL << SCT_EV9_STATE_STATEMSK29_Pos) /*!< SCT EV9_STATE: STATEMSK29 Mask */ #define SCT_EV9_STATE_STATEMSK30_Pos 30 /*!< SCT EV9_STATE: STATEMSK30 Position */ #define SCT_EV9_STATE_STATEMSK30_Msk (0x01UL << SCT_EV9_STATE_STATEMSK30_Pos) /*!< SCT EV9_STATE: STATEMSK30 Mask */ #define SCT_EV9_STATE_STATEMSK31_Pos 31 /*!< SCT EV9_STATE: STATEMSK31 Position */ #define SCT_EV9_STATE_STATEMSK31_Msk (0x01UL << SCT_EV9_STATE_STATEMSK31_Pos) /*!< SCT EV9_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV9_CTRL -------------------------------- */ #define SCT_EV9_CTRL_MATCHSEL_Pos 0 /*!< SCT EV9_CTRL: MATCHSEL Position */ #define SCT_EV9_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV9_CTRL_MATCHSEL_Pos) /*!< SCT EV9_CTRL: MATCHSEL Mask */ #define SCT_EV9_CTRL_HEVENT_Pos 4 /*!< SCT EV9_CTRL: HEVENT Position */ #define SCT_EV9_CTRL_HEVENT_Msk (0x01UL << SCT_EV9_CTRL_HEVENT_Pos) /*!< SCT EV9_CTRL: HEVENT Mask */ #define SCT_EV9_CTRL_OUTSEL_Pos 5 /*!< SCT EV9_CTRL: OUTSEL Position */ #define SCT_EV9_CTRL_OUTSEL_Msk (0x01UL << SCT_EV9_CTRL_OUTSEL_Pos) /*!< SCT EV9_CTRL: OUTSEL Mask */ #define SCT_EV9_CTRL_IOSEL_Pos 6 /*!< SCT EV9_CTRL: IOSEL Position */ #define SCT_EV9_CTRL_IOSEL_Msk (0x0fUL << SCT_EV9_CTRL_IOSEL_Pos) /*!< SCT EV9_CTRL: IOSEL Mask */ #define SCT_EV9_CTRL_IOCOND_Pos 10 /*!< SCT EV9_CTRL: IOCOND Position */ #define SCT_EV9_CTRL_IOCOND_Msk (0x03UL << SCT_EV9_CTRL_IOCOND_Pos) /*!< SCT EV9_CTRL: IOCOND Mask */ #define SCT_EV9_CTRL_COMBMODE_Pos 12 /*!< SCT EV9_CTRL: COMBMODE Position */ #define SCT_EV9_CTRL_COMBMODE_Msk (0x03UL << SCT_EV9_CTRL_COMBMODE_Pos) /*!< SCT EV9_CTRL: COMBMODE Mask */ #define SCT_EV9_CTRL_STATELD_Pos 14 /*!< SCT EV9_CTRL: STATELD Position */ #define SCT_EV9_CTRL_STATELD_Msk (0x01UL << SCT_EV9_CTRL_STATELD_Pos) /*!< SCT EV9_CTRL: STATELD Mask */ #define SCT_EV9_CTRL_STATEV_Pos 15 /*!< SCT EV9_CTRL: STATEV Position */ #define SCT_EV9_CTRL_STATEV_Msk (0x1fUL << SCT_EV9_CTRL_STATEV_Pos) /*!< SCT EV9_CTRL: STATEV Mask */ #define SCT_EV9_CTRL_MATCHMEM_Pos 20 /*!< SCT EV9_CTRL: MATCHMEM Position */ #define SCT_EV9_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV9_CTRL_MATCHMEM_Pos) /*!< SCT EV9_CTRL: MATCHMEM Mask */ #define SCT_EV9_CTRL_DIRECTION_Pos 21 /*!< SCT EV9_CTRL: DIRECTION Position */ #define SCT_EV9_CTRL_DIRECTION_Msk (0x03UL << SCT_EV9_CTRL_DIRECTION_Pos) /*!< SCT EV9_CTRL: DIRECTION Mask */ /* ------------------------------- SCT_EV10_STATE ------------------------------- */ #define SCT_EV10_STATE_STATEMSK0_Pos 0 /*!< SCT EV10_STATE: STATEMSK0 Position */ #define SCT_EV10_STATE_STATEMSK0_Msk (0x01UL << SCT_EV10_STATE_STATEMSK0_Pos) /*!< SCT EV10_STATE: STATEMSK0 Mask */ #define SCT_EV10_STATE_STATEMSK1_Pos 1 /*!< SCT EV10_STATE: STATEMSK1 Position */ #define SCT_EV10_STATE_STATEMSK1_Msk (0x01UL << SCT_EV10_STATE_STATEMSK1_Pos) /*!< SCT EV10_STATE: STATEMSK1 Mask */ #define SCT_EV10_STATE_STATEMSK2_Pos 2 /*!< SCT EV10_STATE: STATEMSK2 Position */ #define SCT_EV10_STATE_STATEMSK2_Msk (0x01UL << SCT_EV10_STATE_STATEMSK2_Pos) /*!< SCT EV10_STATE: STATEMSK2 Mask */ #define SCT_EV10_STATE_STATEMSK3_Pos 3 /*!< SCT EV10_STATE: STATEMSK3 Position */ #define SCT_EV10_STATE_STATEMSK3_Msk (0x01UL << SCT_EV10_STATE_STATEMSK3_Pos) /*!< SCT EV10_STATE: STATEMSK3 Mask */ #define SCT_EV10_STATE_STATEMSK4_Pos 4 /*!< SCT EV10_STATE: STATEMSK4 Position */ #define SCT_EV10_STATE_STATEMSK4_Msk (0x01UL << SCT_EV10_STATE_STATEMSK4_Pos) /*!< SCT EV10_STATE: STATEMSK4 Mask */ #define SCT_EV10_STATE_STATEMSK5_Pos 5 /*!< SCT EV10_STATE: STATEMSK5 Position */ #define SCT_EV10_STATE_STATEMSK5_Msk (0x01UL << SCT_EV10_STATE_STATEMSK5_Pos) /*!< SCT EV10_STATE: STATEMSK5 Mask */ #define SCT_EV10_STATE_STATEMSK6_Pos 6 /*!< SCT EV10_STATE: STATEMSK6 Position */ #define SCT_EV10_STATE_STATEMSK6_Msk (0x01UL << SCT_EV10_STATE_STATEMSK6_Pos) /*!< SCT EV10_STATE: STATEMSK6 Mask */ #define SCT_EV10_STATE_STATEMSK7_Pos 7 /*!< SCT EV10_STATE: STATEMSK7 Position */ #define SCT_EV10_STATE_STATEMSK7_Msk (0x01UL << SCT_EV10_STATE_STATEMSK7_Pos) /*!< SCT EV10_STATE: STATEMSK7 Mask */ #define SCT_EV10_STATE_STATEMSK8_Pos 8 /*!< SCT EV10_STATE: STATEMSK8 Position */ #define SCT_EV10_STATE_STATEMSK8_Msk (0x01UL << SCT_EV10_STATE_STATEMSK8_Pos) /*!< SCT EV10_STATE: STATEMSK8 Mask */ #define SCT_EV10_STATE_STATEMSK9_Pos 9 /*!< SCT EV10_STATE: STATEMSK9 Position */ #define SCT_EV10_STATE_STATEMSK9_Msk (0x01UL << SCT_EV10_STATE_STATEMSK9_Pos) /*!< SCT EV10_STATE: STATEMSK9 Mask */ #define SCT_EV10_STATE_STATEMSK10_Pos 10 /*!< SCT EV10_STATE: STATEMSK10 Position */ #define SCT_EV10_STATE_STATEMSK10_Msk (0x01UL << SCT_EV10_STATE_STATEMSK10_Pos) /*!< SCT EV10_STATE: STATEMSK10 Mask */ #define SCT_EV10_STATE_STATEMSK11_Pos 11 /*!< SCT EV10_STATE: STATEMSK11 Position */ #define SCT_EV10_STATE_STATEMSK11_Msk (0x01UL << SCT_EV10_STATE_STATEMSK11_Pos) /*!< SCT EV10_STATE: STATEMSK11 Mask */ #define SCT_EV10_STATE_STATEMSK12_Pos 12 /*!< SCT EV10_STATE: STATEMSK12 Position */ #define SCT_EV10_STATE_STATEMSK12_Msk (0x01UL << SCT_EV10_STATE_STATEMSK12_Pos) /*!< SCT EV10_STATE: STATEMSK12 Mask */ #define SCT_EV10_STATE_STATEMSK13_Pos 13 /*!< SCT EV10_STATE: STATEMSK13 Position */ #define SCT_EV10_STATE_STATEMSK13_Msk (0x01UL << SCT_EV10_STATE_STATEMSK13_Pos) /*!< SCT EV10_STATE: STATEMSK13 Mask */ #define SCT_EV10_STATE_STATEMSK14_Pos 14 /*!< SCT EV10_STATE: STATEMSK14 Position */ #define SCT_EV10_STATE_STATEMSK14_Msk (0x01UL << SCT_EV10_STATE_STATEMSK14_Pos) /*!< SCT EV10_STATE: STATEMSK14 Mask */ #define SCT_EV10_STATE_STATEMSK15_Pos 15 /*!< SCT EV10_STATE: STATEMSK15 Position */ #define SCT_EV10_STATE_STATEMSK15_Msk (0x01UL << SCT_EV10_STATE_STATEMSK15_Pos) /*!< SCT EV10_STATE: STATEMSK15 Mask */ #define SCT_EV10_STATE_STATEMSK16_Pos 16 /*!< SCT EV10_STATE: STATEMSK16 Position */ #define SCT_EV10_STATE_STATEMSK16_Msk (0x01UL << SCT_EV10_STATE_STATEMSK16_Pos) /*!< SCT EV10_STATE: STATEMSK16 Mask */ #define SCT_EV10_STATE_STATEMSK17_Pos 17 /*!< SCT EV10_STATE: STATEMSK17 Position */ #define SCT_EV10_STATE_STATEMSK17_Msk (0x01UL << SCT_EV10_STATE_STATEMSK17_Pos) /*!< SCT EV10_STATE: STATEMSK17 Mask */ #define SCT_EV10_STATE_STATEMSK18_Pos 18 /*!< SCT EV10_STATE: STATEMSK18 Position */ #define SCT_EV10_STATE_STATEMSK18_Msk (0x01UL << SCT_EV10_STATE_STATEMSK18_Pos) /*!< SCT EV10_STATE: STATEMSK18 Mask */ #define SCT_EV10_STATE_STATEMSK19_Pos 19 /*!< SCT EV10_STATE: STATEMSK19 Position */ #define SCT_EV10_STATE_STATEMSK19_Msk (0x01UL << SCT_EV10_STATE_STATEMSK19_Pos) /*!< SCT EV10_STATE: STATEMSK19 Mask */ #define SCT_EV10_STATE_STATEMSK20_Pos 20 /*!< SCT EV10_STATE: STATEMSK20 Position */ #define SCT_EV10_STATE_STATEMSK20_Msk (0x01UL << SCT_EV10_STATE_STATEMSK20_Pos) /*!< SCT EV10_STATE: STATEMSK20 Mask */ #define SCT_EV10_STATE_STATEMSK21_Pos 21 /*!< SCT EV10_STATE: STATEMSK21 Position */ #define SCT_EV10_STATE_STATEMSK21_Msk (0x01UL << SCT_EV10_STATE_STATEMSK21_Pos) /*!< SCT EV10_STATE: STATEMSK21 Mask */ #define SCT_EV10_STATE_STATEMSK22_Pos 22 /*!< SCT EV10_STATE: STATEMSK22 Position */ #define SCT_EV10_STATE_STATEMSK22_Msk (0x01UL << SCT_EV10_STATE_STATEMSK22_Pos) /*!< SCT EV10_STATE: STATEMSK22 Mask */ #define SCT_EV10_STATE_STATEMSK23_Pos 23 /*!< SCT EV10_STATE: STATEMSK23 Position */ #define SCT_EV10_STATE_STATEMSK23_Msk (0x01UL << SCT_EV10_STATE_STATEMSK23_Pos) /*!< SCT EV10_STATE: STATEMSK23 Mask */ #define SCT_EV10_STATE_STATEMSK24_Pos 24 /*!< SCT EV10_STATE: STATEMSK24 Position */ #define SCT_EV10_STATE_STATEMSK24_Msk (0x01UL << SCT_EV10_STATE_STATEMSK24_Pos) /*!< SCT EV10_STATE: STATEMSK24 Mask */ #define SCT_EV10_STATE_STATEMSK25_Pos 25 /*!< SCT EV10_STATE: STATEMSK25 Position */ #define SCT_EV10_STATE_STATEMSK25_Msk (0x01UL << SCT_EV10_STATE_STATEMSK25_Pos) /*!< SCT EV10_STATE: STATEMSK25 Mask */ #define SCT_EV10_STATE_STATEMSK26_Pos 26 /*!< SCT EV10_STATE: STATEMSK26 Position */ #define SCT_EV10_STATE_STATEMSK26_Msk (0x01UL << SCT_EV10_STATE_STATEMSK26_Pos) /*!< SCT EV10_STATE: STATEMSK26 Mask */ #define SCT_EV10_STATE_STATEMSK27_Pos 27 /*!< SCT EV10_STATE: STATEMSK27 Position */ #define SCT_EV10_STATE_STATEMSK27_Msk (0x01UL << SCT_EV10_STATE_STATEMSK27_Pos) /*!< SCT EV10_STATE: STATEMSK27 Mask */ #define SCT_EV10_STATE_STATEMSK28_Pos 28 /*!< SCT EV10_STATE: STATEMSK28 Position */ #define SCT_EV10_STATE_STATEMSK28_Msk (0x01UL << SCT_EV10_STATE_STATEMSK28_Pos) /*!< SCT EV10_STATE: STATEMSK28 Mask */ #define SCT_EV10_STATE_STATEMSK29_Pos 29 /*!< SCT EV10_STATE: STATEMSK29 Position */ #define SCT_EV10_STATE_STATEMSK29_Msk (0x01UL << SCT_EV10_STATE_STATEMSK29_Pos) /*!< SCT EV10_STATE: STATEMSK29 Mask */ #define SCT_EV10_STATE_STATEMSK30_Pos 30 /*!< SCT EV10_STATE: STATEMSK30 Position */ #define SCT_EV10_STATE_STATEMSK30_Msk (0x01UL << SCT_EV10_STATE_STATEMSK30_Pos) /*!< SCT EV10_STATE: STATEMSK30 Mask */ #define SCT_EV10_STATE_STATEMSK31_Pos 31 /*!< SCT EV10_STATE: STATEMSK31 Position */ #define SCT_EV10_STATE_STATEMSK31_Msk (0x01UL << SCT_EV10_STATE_STATEMSK31_Pos) /*!< SCT EV10_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV10_CTRL ------------------------------- */ #define SCT_EV10_CTRL_MATCHSEL_Pos 0 /*!< SCT EV10_CTRL: MATCHSEL Position */ #define SCT_EV10_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV10_CTRL_MATCHSEL_Pos) /*!< SCT EV10_CTRL: MATCHSEL Mask */ #define SCT_EV10_CTRL_HEVENT_Pos 4 /*!< SCT EV10_CTRL: HEVENT Position */ #define SCT_EV10_CTRL_HEVENT_Msk (0x01UL << SCT_EV10_CTRL_HEVENT_Pos) /*!< SCT EV10_CTRL: HEVENT Mask */ #define SCT_EV10_CTRL_OUTSEL_Pos 5 /*!< SCT EV10_CTRL: OUTSEL Position */ #define SCT_EV10_CTRL_OUTSEL_Msk (0x01UL << SCT_EV10_CTRL_OUTSEL_Pos) /*!< SCT EV10_CTRL: OUTSEL Mask */ #define SCT_EV10_CTRL_IOSEL_Pos 6 /*!< SCT EV10_CTRL: IOSEL Position */ #define SCT_EV10_CTRL_IOSEL_Msk (0x0fUL << SCT_EV10_CTRL_IOSEL_Pos) /*!< SCT EV10_CTRL: IOSEL Mask */ #define SCT_EV10_CTRL_IOCOND_Pos 10 /*!< SCT EV10_CTRL: IOCOND Position */ #define SCT_EV10_CTRL_IOCOND_Msk (0x03UL << SCT_EV10_CTRL_IOCOND_Pos) /*!< SCT EV10_CTRL: IOCOND Mask */ #define SCT_EV10_CTRL_COMBMODE_Pos 12 /*!< SCT EV10_CTRL: COMBMODE Position */ #define SCT_EV10_CTRL_COMBMODE_Msk (0x03UL << SCT_EV10_CTRL_COMBMODE_Pos) /*!< SCT EV10_CTRL: COMBMODE Mask */ #define SCT_EV10_CTRL_STATELD_Pos 14 /*!< SCT EV10_CTRL: STATELD Position */ #define SCT_EV10_CTRL_STATELD_Msk (0x01UL << SCT_EV10_CTRL_STATELD_Pos) /*!< SCT EV10_CTRL: STATELD Mask */ #define SCT_EV10_CTRL_STATEV_Pos 15 /*!< SCT EV10_CTRL: STATEV Position */ #define SCT_EV10_CTRL_STATEV_Msk (0x1fUL << SCT_EV10_CTRL_STATEV_Pos) /*!< SCT EV10_CTRL: STATEV Mask */ #define SCT_EV10_CTRL_MATCHMEM_Pos 20 /*!< SCT EV10_CTRL: MATCHMEM Position */ #define SCT_EV10_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV10_CTRL_MATCHMEM_Pos) /*!< SCT EV10_CTRL: MATCHMEM Mask */ #define SCT_EV10_CTRL_DIRECTION_Pos 21 /*!< SCT EV10_CTRL: DIRECTION Position */ #define SCT_EV10_CTRL_DIRECTION_Msk (0x03UL << SCT_EV10_CTRL_DIRECTION_Pos) /*!< SCT EV10_CTRL: DIRECTION Mask */ /* ------------------------------- SCT_EV11_STATE ------------------------------- */ #define SCT_EV11_STATE_STATEMSK0_Pos 0 /*!< SCT EV11_STATE: STATEMSK0 Position */ #define SCT_EV11_STATE_STATEMSK0_Msk (0x01UL << SCT_EV11_STATE_STATEMSK0_Pos) /*!< SCT EV11_STATE: STATEMSK0 Mask */ #define SCT_EV11_STATE_STATEMSK1_Pos 1 /*!< SCT EV11_STATE: STATEMSK1 Position */ #define SCT_EV11_STATE_STATEMSK1_Msk (0x01UL << SCT_EV11_STATE_STATEMSK1_Pos) /*!< SCT EV11_STATE: STATEMSK1 Mask */ #define SCT_EV11_STATE_STATEMSK2_Pos 2 /*!< SCT EV11_STATE: STATEMSK2 Position */ #define SCT_EV11_STATE_STATEMSK2_Msk (0x01UL << SCT_EV11_STATE_STATEMSK2_Pos) /*!< SCT EV11_STATE: STATEMSK2 Mask */ #define SCT_EV11_STATE_STATEMSK3_Pos 3 /*!< SCT EV11_STATE: STATEMSK3 Position */ #define SCT_EV11_STATE_STATEMSK3_Msk (0x01UL << SCT_EV11_STATE_STATEMSK3_Pos) /*!< SCT EV11_STATE: STATEMSK3 Mask */ #define SCT_EV11_STATE_STATEMSK4_Pos 4 /*!< SCT EV11_STATE: STATEMSK4 Position */ #define SCT_EV11_STATE_STATEMSK4_Msk (0x01UL << SCT_EV11_STATE_STATEMSK4_Pos) /*!< SCT EV11_STATE: STATEMSK4 Mask */ #define SCT_EV11_STATE_STATEMSK5_Pos 5 /*!< SCT EV11_STATE: STATEMSK5 Position */ #define SCT_EV11_STATE_STATEMSK5_Msk (0x01UL << SCT_EV11_STATE_STATEMSK5_Pos) /*!< SCT EV11_STATE: STATEMSK5 Mask */ #define SCT_EV11_STATE_STATEMSK6_Pos 6 /*!< SCT EV11_STATE: STATEMSK6 Position */ #define SCT_EV11_STATE_STATEMSK6_Msk (0x01UL << SCT_EV11_STATE_STATEMSK6_Pos) /*!< SCT EV11_STATE: STATEMSK6 Mask */ #define SCT_EV11_STATE_STATEMSK7_Pos 7 /*!< SCT EV11_STATE: STATEMSK7 Position */ #define SCT_EV11_STATE_STATEMSK7_Msk (0x01UL << SCT_EV11_STATE_STATEMSK7_Pos) /*!< SCT EV11_STATE: STATEMSK7 Mask */ #define SCT_EV11_STATE_STATEMSK8_Pos 8 /*!< SCT EV11_STATE: STATEMSK8 Position */ #define SCT_EV11_STATE_STATEMSK8_Msk (0x01UL << SCT_EV11_STATE_STATEMSK8_Pos) /*!< SCT EV11_STATE: STATEMSK8 Mask */ #define SCT_EV11_STATE_STATEMSK9_Pos 9 /*!< SCT EV11_STATE: STATEMSK9 Position */ #define SCT_EV11_STATE_STATEMSK9_Msk (0x01UL << SCT_EV11_STATE_STATEMSK9_Pos) /*!< SCT EV11_STATE: STATEMSK9 Mask */ #define SCT_EV11_STATE_STATEMSK10_Pos 10 /*!< SCT EV11_STATE: STATEMSK10 Position */ #define SCT_EV11_STATE_STATEMSK10_Msk (0x01UL << SCT_EV11_STATE_STATEMSK10_Pos) /*!< SCT EV11_STATE: STATEMSK10 Mask */ #define SCT_EV11_STATE_STATEMSK11_Pos 11 /*!< SCT EV11_STATE: STATEMSK11 Position */ #define SCT_EV11_STATE_STATEMSK11_Msk (0x01UL << SCT_EV11_STATE_STATEMSK11_Pos) /*!< SCT EV11_STATE: STATEMSK11 Mask */ #define SCT_EV11_STATE_STATEMSK12_Pos 12 /*!< SCT EV11_STATE: STATEMSK12 Position */ #define SCT_EV11_STATE_STATEMSK12_Msk (0x01UL << SCT_EV11_STATE_STATEMSK12_Pos) /*!< SCT EV11_STATE: STATEMSK12 Mask */ #define SCT_EV11_STATE_STATEMSK13_Pos 13 /*!< SCT EV11_STATE: STATEMSK13 Position */ #define SCT_EV11_STATE_STATEMSK13_Msk (0x01UL << SCT_EV11_STATE_STATEMSK13_Pos) /*!< SCT EV11_STATE: STATEMSK13 Mask */ #define SCT_EV11_STATE_STATEMSK14_Pos 14 /*!< SCT EV11_STATE: STATEMSK14 Position */ #define SCT_EV11_STATE_STATEMSK14_Msk (0x01UL << SCT_EV11_STATE_STATEMSK14_Pos) /*!< SCT EV11_STATE: STATEMSK14 Mask */ #define SCT_EV11_STATE_STATEMSK15_Pos 15 /*!< SCT EV11_STATE: STATEMSK15 Position */ #define SCT_EV11_STATE_STATEMSK15_Msk (0x01UL << SCT_EV11_STATE_STATEMSK15_Pos) /*!< SCT EV11_STATE: STATEMSK15 Mask */ #define SCT_EV11_STATE_STATEMSK16_Pos 16 /*!< SCT EV11_STATE: STATEMSK16 Position */ #define SCT_EV11_STATE_STATEMSK16_Msk (0x01UL << SCT_EV11_STATE_STATEMSK16_Pos) /*!< SCT EV11_STATE: STATEMSK16 Mask */ #define SCT_EV11_STATE_STATEMSK17_Pos 17 /*!< SCT EV11_STATE: STATEMSK17 Position */ #define SCT_EV11_STATE_STATEMSK17_Msk (0x01UL << SCT_EV11_STATE_STATEMSK17_Pos) /*!< SCT EV11_STATE: STATEMSK17 Mask */ #define SCT_EV11_STATE_STATEMSK18_Pos 18 /*!< SCT EV11_STATE: STATEMSK18 Position */ #define SCT_EV11_STATE_STATEMSK18_Msk (0x01UL << SCT_EV11_STATE_STATEMSK18_Pos) /*!< SCT EV11_STATE: STATEMSK18 Mask */ #define SCT_EV11_STATE_STATEMSK19_Pos 19 /*!< SCT EV11_STATE: STATEMSK19 Position */ #define SCT_EV11_STATE_STATEMSK19_Msk (0x01UL << SCT_EV11_STATE_STATEMSK19_Pos) /*!< SCT EV11_STATE: STATEMSK19 Mask */ #define SCT_EV11_STATE_STATEMSK20_Pos 20 /*!< SCT EV11_STATE: STATEMSK20 Position */ #define SCT_EV11_STATE_STATEMSK20_Msk (0x01UL << SCT_EV11_STATE_STATEMSK20_Pos) /*!< SCT EV11_STATE: STATEMSK20 Mask */ #define SCT_EV11_STATE_STATEMSK21_Pos 21 /*!< SCT EV11_STATE: STATEMSK21 Position */ #define SCT_EV11_STATE_STATEMSK21_Msk (0x01UL << SCT_EV11_STATE_STATEMSK21_Pos) /*!< SCT EV11_STATE: STATEMSK21 Mask */ #define SCT_EV11_STATE_STATEMSK22_Pos 22 /*!< SCT EV11_STATE: STATEMSK22 Position */ #define SCT_EV11_STATE_STATEMSK22_Msk (0x01UL << SCT_EV11_STATE_STATEMSK22_Pos) /*!< SCT EV11_STATE: STATEMSK22 Mask */ #define SCT_EV11_STATE_STATEMSK23_Pos 23 /*!< SCT EV11_STATE: STATEMSK23 Position */ #define SCT_EV11_STATE_STATEMSK23_Msk (0x01UL << SCT_EV11_STATE_STATEMSK23_Pos) /*!< SCT EV11_STATE: STATEMSK23 Mask */ #define SCT_EV11_STATE_STATEMSK24_Pos 24 /*!< SCT EV11_STATE: STATEMSK24 Position */ #define SCT_EV11_STATE_STATEMSK24_Msk (0x01UL << SCT_EV11_STATE_STATEMSK24_Pos) /*!< SCT EV11_STATE: STATEMSK24 Mask */ #define SCT_EV11_STATE_STATEMSK25_Pos 25 /*!< SCT EV11_STATE: STATEMSK25 Position */ #define SCT_EV11_STATE_STATEMSK25_Msk (0x01UL << SCT_EV11_STATE_STATEMSK25_Pos) /*!< SCT EV11_STATE: STATEMSK25 Mask */ #define SCT_EV11_STATE_STATEMSK26_Pos 26 /*!< SCT EV11_STATE: STATEMSK26 Position */ #define SCT_EV11_STATE_STATEMSK26_Msk (0x01UL << SCT_EV11_STATE_STATEMSK26_Pos) /*!< SCT EV11_STATE: STATEMSK26 Mask */ #define SCT_EV11_STATE_STATEMSK27_Pos 27 /*!< SCT EV11_STATE: STATEMSK27 Position */ #define SCT_EV11_STATE_STATEMSK27_Msk (0x01UL << SCT_EV11_STATE_STATEMSK27_Pos) /*!< SCT EV11_STATE: STATEMSK27 Mask */ #define SCT_EV11_STATE_STATEMSK28_Pos 28 /*!< SCT EV11_STATE: STATEMSK28 Position */ #define SCT_EV11_STATE_STATEMSK28_Msk (0x01UL << SCT_EV11_STATE_STATEMSK28_Pos) /*!< SCT EV11_STATE: STATEMSK28 Mask */ #define SCT_EV11_STATE_STATEMSK29_Pos 29 /*!< SCT EV11_STATE: STATEMSK29 Position */ #define SCT_EV11_STATE_STATEMSK29_Msk (0x01UL << SCT_EV11_STATE_STATEMSK29_Pos) /*!< SCT EV11_STATE: STATEMSK29 Mask */ #define SCT_EV11_STATE_STATEMSK30_Pos 30 /*!< SCT EV11_STATE: STATEMSK30 Position */ #define SCT_EV11_STATE_STATEMSK30_Msk (0x01UL << SCT_EV11_STATE_STATEMSK30_Pos) /*!< SCT EV11_STATE: STATEMSK30 Mask */ #define SCT_EV11_STATE_STATEMSK31_Pos 31 /*!< SCT EV11_STATE: STATEMSK31 Position */ #define SCT_EV11_STATE_STATEMSK31_Msk (0x01UL << SCT_EV11_STATE_STATEMSK31_Pos) /*!< SCT EV11_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV11_CTRL ------------------------------- */ #define SCT_EV11_CTRL_MATCHSEL_Pos 0 /*!< SCT EV11_CTRL: MATCHSEL Position */ #define SCT_EV11_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV11_CTRL_MATCHSEL_Pos) /*!< SCT EV11_CTRL: MATCHSEL Mask */ #define SCT_EV11_CTRL_HEVENT_Pos 4 /*!< SCT EV11_CTRL: HEVENT Position */ #define SCT_EV11_CTRL_HEVENT_Msk (0x01UL << SCT_EV11_CTRL_HEVENT_Pos) /*!< SCT EV11_CTRL: HEVENT Mask */ #define SCT_EV11_CTRL_OUTSEL_Pos 5 /*!< SCT EV11_CTRL: OUTSEL Position */ #define SCT_EV11_CTRL_OUTSEL_Msk (0x01UL << SCT_EV11_CTRL_OUTSEL_Pos) /*!< SCT EV11_CTRL: OUTSEL Mask */ #define SCT_EV11_CTRL_IOSEL_Pos 6 /*!< SCT EV11_CTRL: IOSEL Position */ #define SCT_EV11_CTRL_IOSEL_Msk (0x0fUL << SCT_EV11_CTRL_IOSEL_Pos) /*!< SCT EV11_CTRL: IOSEL Mask */ #define SCT_EV11_CTRL_IOCOND_Pos 10 /*!< SCT EV11_CTRL: IOCOND Position */ #define SCT_EV11_CTRL_IOCOND_Msk (0x03UL << SCT_EV11_CTRL_IOCOND_Pos) /*!< SCT EV11_CTRL: IOCOND Mask */ #define SCT_EV11_CTRL_COMBMODE_Pos 12 /*!< SCT EV11_CTRL: COMBMODE Position */ #define SCT_EV11_CTRL_COMBMODE_Msk (0x03UL << SCT_EV11_CTRL_COMBMODE_Pos) /*!< SCT EV11_CTRL: COMBMODE Mask */ #define SCT_EV11_CTRL_STATELD_Pos 14 /*!< SCT EV11_CTRL: STATELD Position */ #define SCT_EV11_CTRL_STATELD_Msk (0x01UL << SCT_EV11_CTRL_STATELD_Pos) /*!< SCT EV11_CTRL: STATELD Mask */ #define SCT_EV11_CTRL_STATEV_Pos 15 /*!< SCT EV11_CTRL: STATEV Position */ #define SCT_EV11_CTRL_STATEV_Msk (0x1fUL << SCT_EV11_CTRL_STATEV_Pos) /*!< SCT EV11_CTRL: STATEV Mask */ #define SCT_EV11_CTRL_MATCHMEM_Pos 20 /*!< SCT EV11_CTRL: MATCHMEM Position */ #define SCT_EV11_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV11_CTRL_MATCHMEM_Pos) /*!< SCT EV11_CTRL: MATCHMEM Mask */ #define SCT_EV11_CTRL_DIRECTION_Pos 21 /*!< SCT EV11_CTRL: DIRECTION Position */ #define SCT_EV11_CTRL_DIRECTION_Msk (0x03UL << SCT_EV11_CTRL_DIRECTION_Pos) /*!< SCT EV11_CTRL: DIRECTION Mask */ /* ------------------------------- SCT_EV12_STATE ------------------------------- */ #define SCT_EV12_STATE_STATEMSK0_Pos 0 /*!< SCT EV12_STATE: STATEMSK0 Position */ #define SCT_EV12_STATE_STATEMSK0_Msk (0x01UL << SCT_EV12_STATE_STATEMSK0_Pos) /*!< SCT EV12_STATE: STATEMSK0 Mask */ #define SCT_EV12_STATE_STATEMSK1_Pos 1 /*!< SCT EV12_STATE: STATEMSK1 Position */ #define SCT_EV12_STATE_STATEMSK1_Msk (0x01UL << SCT_EV12_STATE_STATEMSK1_Pos) /*!< SCT EV12_STATE: STATEMSK1 Mask */ #define SCT_EV12_STATE_STATEMSK2_Pos 2 /*!< SCT EV12_STATE: STATEMSK2 Position */ #define SCT_EV12_STATE_STATEMSK2_Msk (0x01UL << SCT_EV12_STATE_STATEMSK2_Pos) /*!< SCT EV12_STATE: STATEMSK2 Mask */ #define SCT_EV12_STATE_STATEMSK3_Pos 3 /*!< SCT EV12_STATE: STATEMSK3 Position */ #define SCT_EV12_STATE_STATEMSK3_Msk (0x01UL << SCT_EV12_STATE_STATEMSK3_Pos) /*!< SCT EV12_STATE: STATEMSK3 Mask */ #define SCT_EV12_STATE_STATEMSK4_Pos 4 /*!< SCT EV12_STATE: STATEMSK4 Position */ #define SCT_EV12_STATE_STATEMSK4_Msk (0x01UL << SCT_EV12_STATE_STATEMSK4_Pos) /*!< SCT EV12_STATE: STATEMSK4 Mask */ #define SCT_EV12_STATE_STATEMSK5_Pos 5 /*!< SCT EV12_STATE: STATEMSK5 Position */ #define SCT_EV12_STATE_STATEMSK5_Msk (0x01UL << SCT_EV12_STATE_STATEMSK5_Pos) /*!< SCT EV12_STATE: STATEMSK5 Mask */ #define SCT_EV12_STATE_STATEMSK6_Pos 6 /*!< SCT EV12_STATE: STATEMSK6 Position */ #define SCT_EV12_STATE_STATEMSK6_Msk (0x01UL << SCT_EV12_STATE_STATEMSK6_Pos) /*!< SCT EV12_STATE: STATEMSK6 Mask */ #define SCT_EV12_STATE_STATEMSK7_Pos 7 /*!< SCT EV12_STATE: STATEMSK7 Position */ #define SCT_EV12_STATE_STATEMSK7_Msk (0x01UL << SCT_EV12_STATE_STATEMSK7_Pos) /*!< SCT EV12_STATE: STATEMSK7 Mask */ #define SCT_EV12_STATE_STATEMSK8_Pos 8 /*!< SCT EV12_STATE: STATEMSK8 Position */ #define SCT_EV12_STATE_STATEMSK8_Msk (0x01UL << SCT_EV12_STATE_STATEMSK8_Pos) /*!< SCT EV12_STATE: STATEMSK8 Mask */ #define SCT_EV12_STATE_STATEMSK9_Pos 9 /*!< SCT EV12_STATE: STATEMSK9 Position */ #define SCT_EV12_STATE_STATEMSK9_Msk (0x01UL << SCT_EV12_STATE_STATEMSK9_Pos) /*!< SCT EV12_STATE: STATEMSK9 Mask */ #define SCT_EV12_STATE_STATEMSK10_Pos 10 /*!< SCT EV12_STATE: STATEMSK10 Position */ #define SCT_EV12_STATE_STATEMSK10_Msk (0x01UL << SCT_EV12_STATE_STATEMSK10_Pos) /*!< SCT EV12_STATE: STATEMSK10 Mask */ #define SCT_EV12_STATE_STATEMSK11_Pos 11 /*!< SCT EV12_STATE: STATEMSK11 Position */ #define SCT_EV12_STATE_STATEMSK11_Msk (0x01UL << SCT_EV12_STATE_STATEMSK11_Pos) /*!< SCT EV12_STATE: STATEMSK11 Mask */ #define SCT_EV12_STATE_STATEMSK12_Pos 12 /*!< SCT EV12_STATE: STATEMSK12 Position */ #define SCT_EV12_STATE_STATEMSK12_Msk (0x01UL << SCT_EV12_STATE_STATEMSK12_Pos) /*!< SCT EV12_STATE: STATEMSK12 Mask */ #define SCT_EV12_STATE_STATEMSK13_Pos 13 /*!< SCT EV12_STATE: STATEMSK13 Position */ #define SCT_EV12_STATE_STATEMSK13_Msk (0x01UL << SCT_EV12_STATE_STATEMSK13_Pos) /*!< SCT EV12_STATE: STATEMSK13 Mask */ #define SCT_EV12_STATE_STATEMSK14_Pos 14 /*!< SCT EV12_STATE: STATEMSK14 Position */ #define SCT_EV12_STATE_STATEMSK14_Msk (0x01UL << SCT_EV12_STATE_STATEMSK14_Pos) /*!< SCT EV12_STATE: STATEMSK14 Mask */ #define SCT_EV12_STATE_STATEMSK15_Pos 15 /*!< SCT EV12_STATE: STATEMSK15 Position */ #define SCT_EV12_STATE_STATEMSK15_Msk (0x01UL << SCT_EV12_STATE_STATEMSK15_Pos) /*!< SCT EV12_STATE: STATEMSK15 Mask */ #define SCT_EV12_STATE_STATEMSK16_Pos 16 /*!< SCT EV12_STATE: STATEMSK16 Position */ #define SCT_EV12_STATE_STATEMSK16_Msk (0x01UL << SCT_EV12_STATE_STATEMSK16_Pos) /*!< SCT EV12_STATE: STATEMSK16 Mask */ #define SCT_EV12_STATE_STATEMSK17_Pos 17 /*!< SCT EV12_STATE: STATEMSK17 Position */ #define SCT_EV12_STATE_STATEMSK17_Msk (0x01UL << SCT_EV12_STATE_STATEMSK17_Pos) /*!< SCT EV12_STATE: STATEMSK17 Mask */ #define SCT_EV12_STATE_STATEMSK18_Pos 18 /*!< SCT EV12_STATE: STATEMSK18 Position */ #define SCT_EV12_STATE_STATEMSK18_Msk (0x01UL << SCT_EV12_STATE_STATEMSK18_Pos) /*!< SCT EV12_STATE: STATEMSK18 Mask */ #define SCT_EV12_STATE_STATEMSK19_Pos 19 /*!< SCT EV12_STATE: STATEMSK19 Position */ #define SCT_EV12_STATE_STATEMSK19_Msk (0x01UL << SCT_EV12_STATE_STATEMSK19_Pos) /*!< SCT EV12_STATE: STATEMSK19 Mask */ #define SCT_EV12_STATE_STATEMSK20_Pos 20 /*!< SCT EV12_STATE: STATEMSK20 Position */ #define SCT_EV12_STATE_STATEMSK20_Msk (0x01UL << SCT_EV12_STATE_STATEMSK20_Pos) /*!< SCT EV12_STATE: STATEMSK20 Mask */ #define SCT_EV12_STATE_STATEMSK21_Pos 21 /*!< SCT EV12_STATE: STATEMSK21 Position */ #define SCT_EV12_STATE_STATEMSK21_Msk (0x01UL << SCT_EV12_STATE_STATEMSK21_Pos) /*!< SCT EV12_STATE: STATEMSK21 Mask */ #define SCT_EV12_STATE_STATEMSK22_Pos 22 /*!< SCT EV12_STATE: STATEMSK22 Position */ #define SCT_EV12_STATE_STATEMSK22_Msk (0x01UL << SCT_EV12_STATE_STATEMSK22_Pos) /*!< SCT EV12_STATE: STATEMSK22 Mask */ #define SCT_EV12_STATE_STATEMSK23_Pos 23 /*!< SCT EV12_STATE: STATEMSK23 Position */ #define SCT_EV12_STATE_STATEMSK23_Msk (0x01UL << SCT_EV12_STATE_STATEMSK23_Pos) /*!< SCT EV12_STATE: STATEMSK23 Mask */ #define SCT_EV12_STATE_STATEMSK24_Pos 24 /*!< SCT EV12_STATE: STATEMSK24 Position */ #define SCT_EV12_STATE_STATEMSK24_Msk (0x01UL << SCT_EV12_STATE_STATEMSK24_Pos) /*!< SCT EV12_STATE: STATEMSK24 Mask */ #define SCT_EV12_STATE_STATEMSK25_Pos 25 /*!< SCT EV12_STATE: STATEMSK25 Position */ #define SCT_EV12_STATE_STATEMSK25_Msk (0x01UL << SCT_EV12_STATE_STATEMSK25_Pos) /*!< SCT EV12_STATE: STATEMSK25 Mask */ #define SCT_EV12_STATE_STATEMSK26_Pos 26 /*!< SCT EV12_STATE: STATEMSK26 Position */ #define SCT_EV12_STATE_STATEMSK26_Msk (0x01UL << SCT_EV12_STATE_STATEMSK26_Pos) /*!< SCT EV12_STATE: STATEMSK26 Mask */ #define SCT_EV12_STATE_STATEMSK27_Pos 27 /*!< SCT EV12_STATE: STATEMSK27 Position */ #define SCT_EV12_STATE_STATEMSK27_Msk (0x01UL << SCT_EV12_STATE_STATEMSK27_Pos) /*!< SCT EV12_STATE: STATEMSK27 Mask */ #define SCT_EV12_STATE_STATEMSK28_Pos 28 /*!< SCT EV12_STATE: STATEMSK28 Position */ #define SCT_EV12_STATE_STATEMSK28_Msk (0x01UL << SCT_EV12_STATE_STATEMSK28_Pos) /*!< SCT EV12_STATE: STATEMSK28 Mask */ #define SCT_EV12_STATE_STATEMSK29_Pos 29 /*!< SCT EV12_STATE: STATEMSK29 Position */ #define SCT_EV12_STATE_STATEMSK29_Msk (0x01UL << SCT_EV12_STATE_STATEMSK29_Pos) /*!< SCT EV12_STATE: STATEMSK29 Mask */ #define SCT_EV12_STATE_STATEMSK30_Pos 30 /*!< SCT EV12_STATE: STATEMSK30 Position */ #define SCT_EV12_STATE_STATEMSK30_Msk (0x01UL << SCT_EV12_STATE_STATEMSK30_Pos) /*!< SCT EV12_STATE: STATEMSK30 Mask */ #define SCT_EV12_STATE_STATEMSK31_Pos 31 /*!< SCT EV12_STATE: STATEMSK31 Position */ #define SCT_EV12_STATE_STATEMSK31_Msk (0x01UL << SCT_EV12_STATE_STATEMSK31_Pos) /*!< SCT EV12_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV12_CTRL ------------------------------- */ #define SCT_EV12_CTRL_MATCHSEL_Pos 0 /*!< SCT EV12_CTRL: MATCHSEL Position */ #define SCT_EV12_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV12_CTRL_MATCHSEL_Pos) /*!< SCT EV12_CTRL: MATCHSEL Mask */ #define SCT_EV12_CTRL_HEVENT_Pos 4 /*!< SCT EV12_CTRL: HEVENT Position */ #define SCT_EV12_CTRL_HEVENT_Msk (0x01UL << SCT_EV12_CTRL_HEVENT_Pos) /*!< SCT EV12_CTRL: HEVENT Mask */ #define SCT_EV12_CTRL_OUTSEL_Pos 5 /*!< SCT EV12_CTRL: OUTSEL Position */ #define SCT_EV12_CTRL_OUTSEL_Msk (0x01UL << SCT_EV12_CTRL_OUTSEL_Pos) /*!< SCT EV12_CTRL: OUTSEL Mask */ #define SCT_EV12_CTRL_IOSEL_Pos 6 /*!< SCT EV12_CTRL: IOSEL Position */ #define SCT_EV12_CTRL_IOSEL_Msk (0x0fUL << SCT_EV12_CTRL_IOSEL_Pos) /*!< SCT EV12_CTRL: IOSEL Mask */ #define SCT_EV12_CTRL_IOCOND_Pos 10 /*!< SCT EV12_CTRL: IOCOND Position */ #define SCT_EV12_CTRL_IOCOND_Msk (0x03UL << SCT_EV12_CTRL_IOCOND_Pos) /*!< SCT EV12_CTRL: IOCOND Mask */ #define SCT_EV12_CTRL_COMBMODE_Pos 12 /*!< SCT EV12_CTRL: COMBMODE Position */ #define SCT_EV12_CTRL_COMBMODE_Msk (0x03UL << SCT_EV12_CTRL_COMBMODE_Pos) /*!< SCT EV12_CTRL: COMBMODE Mask */ #define SCT_EV12_CTRL_STATELD_Pos 14 /*!< SCT EV12_CTRL: STATELD Position */ #define SCT_EV12_CTRL_STATELD_Msk (0x01UL << SCT_EV12_CTRL_STATELD_Pos) /*!< SCT EV12_CTRL: STATELD Mask */ #define SCT_EV12_CTRL_STATEV_Pos 15 /*!< SCT EV12_CTRL: STATEV Position */ #define SCT_EV12_CTRL_STATEV_Msk (0x1fUL << SCT_EV12_CTRL_STATEV_Pos) /*!< SCT EV12_CTRL: STATEV Mask */ #define SCT_EV12_CTRL_MATCHMEM_Pos 20 /*!< SCT EV12_CTRL: MATCHMEM Position */ #define SCT_EV12_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV12_CTRL_MATCHMEM_Pos) /*!< SCT EV12_CTRL: MATCHMEM Mask */ #define SCT_EV12_CTRL_DIRECTION_Pos 21 /*!< SCT EV12_CTRL: DIRECTION Position */ #define SCT_EV12_CTRL_DIRECTION_Msk (0x03UL << SCT_EV12_CTRL_DIRECTION_Pos) /*!< SCT EV12_CTRL: DIRECTION Mask */ /* ------------------------------- SCT_EV13_STATE ------------------------------- */ #define SCT_EV13_STATE_STATEMSK0_Pos 0 /*!< SCT EV13_STATE: STATEMSK0 Position */ #define SCT_EV13_STATE_STATEMSK0_Msk (0x01UL << SCT_EV13_STATE_STATEMSK0_Pos) /*!< SCT EV13_STATE: STATEMSK0 Mask */ #define SCT_EV13_STATE_STATEMSK1_Pos 1 /*!< SCT EV13_STATE: STATEMSK1 Position */ #define SCT_EV13_STATE_STATEMSK1_Msk (0x01UL << SCT_EV13_STATE_STATEMSK1_Pos) /*!< SCT EV13_STATE: STATEMSK1 Mask */ #define SCT_EV13_STATE_STATEMSK2_Pos 2 /*!< SCT EV13_STATE: STATEMSK2 Position */ #define SCT_EV13_STATE_STATEMSK2_Msk (0x01UL << SCT_EV13_STATE_STATEMSK2_Pos) /*!< SCT EV13_STATE: STATEMSK2 Mask */ #define SCT_EV13_STATE_STATEMSK3_Pos 3 /*!< SCT EV13_STATE: STATEMSK3 Position */ #define SCT_EV13_STATE_STATEMSK3_Msk (0x01UL << SCT_EV13_STATE_STATEMSK3_Pos) /*!< SCT EV13_STATE: STATEMSK3 Mask */ #define SCT_EV13_STATE_STATEMSK4_Pos 4 /*!< SCT EV13_STATE: STATEMSK4 Position */ #define SCT_EV13_STATE_STATEMSK4_Msk (0x01UL << SCT_EV13_STATE_STATEMSK4_Pos) /*!< SCT EV13_STATE: STATEMSK4 Mask */ #define SCT_EV13_STATE_STATEMSK5_Pos 5 /*!< SCT EV13_STATE: STATEMSK5 Position */ #define SCT_EV13_STATE_STATEMSK5_Msk (0x01UL << SCT_EV13_STATE_STATEMSK5_Pos) /*!< SCT EV13_STATE: STATEMSK5 Mask */ #define SCT_EV13_STATE_STATEMSK6_Pos 6 /*!< SCT EV13_STATE: STATEMSK6 Position */ #define SCT_EV13_STATE_STATEMSK6_Msk (0x01UL << SCT_EV13_STATE_STATEMSK6_Pos) /*!< SCT EV13_STATE: STATEMSK6 Mask */ #define SCT_EV13_STATE_STATEMSK7_Pos 7 /*!< SCT EV13_STATE: STATEMSK7 Position */ #define SCT_EV13_STATE_STATEMSK7_Msk (0x01UL << SCT_EV13_STATE_STATEMSK7_Pos) /*!< SCT EV13_STATE: STATEMSK7 Mask */ #define SCT_EV13_STATE_STATEMSK8_Pos 8 /*!< SCT EV13_STATE: STATEMSK8 Position */ #define SCT_EV13_STATE_STATEMSK8_Msk (0x01UL << SCT_EV13_STATE_STATEMSK8_Pos) /*!< SCT EV13_STATE: STATEMSK8 Mask */ #define SCT_EV13_STATE_STATEMSK9_Pos 9 /*!< SCT EV13_STATE: STATEMSK9 Position */ #define SCT_EV13_STATE_STATEMSK9_Msk (0x01UL << SCT_EV13_STATE_STATEMSK9_Pos) /*!< SCT EV13_STATE: STATEMSK9 Mask */ #define SCT_EV13_STATE_STATEMSK10_Pos 10 /*!< SCT EV13_STATE: STATEMSK10 Position */ #define SCT_EV13_STATE_STATEMSK10_Msk (0x01UL << SCT_EV13_STATE_STATEMSK10_Pos) /*!< SCT EV13_STATE: STATEMSK10 Mask */ #define SCT_EV13_STATE_STATEMSK11_Pos 11 /*!< SCT EV13_STATE: STATEMSK11 Position */ #define SCT_EV13_STATE_STATEMSK11_Msk (0x01UL << SCT_EV13_STATE_STATEMSK11_Pos) /*!< SCT EV13_STATE: STATEMSK11 Mask */ #define SCT_EV13_STATE_STATEMSK12_Pos 12 /*!< SCT EV13_STATE: STATEMSK12 Position */ #define SCT_EV13_STATE_STATEMSK12_Msk (0x01UL << SCT_EV13_STATE_STATEMSK12_Pos) /*!< SCT EV13_STATE: STATEMSK12 Mask */ #define SCT_EV13_STATE_STATEMSK13_Pos 13 /*!< SCT EV13_STATE: STATEMSK13 Position */ #define SCT_EV13_STATE_STATEMSK13_Msk (0x01UL << SCT_EV13_STATE_STATEMSK13_Pos) /*!< SCT EV13_STATE: STATEMSK13 Mask */ #define SCT_EV13_STATE_STATEMSK14_Pos 14 /*!< SCT EV13_STATE: STATEMSK14 Position */ #define SCT_EV13_STATE_STATEMSK14_Msk (0x01UL << SCT_EV13_STATE_STATEMSK14_Pos) /*!< SCT EV13_STATE: STATEMSK14 Mask */ #define SCT_EV13_STATE_STATEMSK15_Pos 15 /*!< SCT EV13_STATE: STATEMSK15 Position */ #define SCT_EV13_STATE_STATEMSK15_Msk (0x01UL << SCT_EV13_STATE_STATEMSK15_Pos) /*!< SCT EV13_STATE: STATEMSK15 Mask */ #define SCT_EV13_STATE_STATEMSK16_Pos 16 /*!< SCT EV13_STATE: STATEMSK16 Position */ #define SCT_EV13_STATE_STATEMSK16_Msk (0x01UL << SCT_EV13_STATE_STATEMSK16_Pos) /*!< SCT EV13_STATE: STATEMSK16 Mask */ #define SCT_EV13_STATE_STATEMSK17_Pos 17 /*!< SCT EV13_STATE: STATEMSK17 Position */ #define SCT_EV13_STATE_STATEMSK17_Msk (0x01UL << SCT_EV13_STATE_STATEMSK17_Pos) /*!< SCT EV13_STATE: STATEMSK17 Mask */ #define SCT_EV13_STATE_STATEMSK18_Pos 18 /*!< SCT EV13_STATE: STATEMSK18 Position */ #define SCT_EV13_STATE_STATEMSK18_Msk (0x01UL << SCT_EV13_STATE_STATEMSK18_Pos) /*!< SCT EV13_STATE: STATEMSK18 Mask */ #define SCT_EV13_STATE_STATEMSK19_Pos 19 /*!< SCT EV13_STATE: STATEMSK19 Position */ #define SCT_EV13_STATE_STATEMSK19_Msk (0x01UL << SCT_EV13_STATE_STATEMSK19_Pos) /*!< SCT EV13_STATE: STATEMSK19 Mask */ #define SCT_EV13_STATE_STATEMSK20_Pos 20 /*!< SCT EV13_STATE: STATEMSK20 Position */ #define SCT_EV13_STATE_STATEMSK20_Msk (0x01UL << SCT_EV13_STATE_STATEMSK20_Pos) /*!< SCT EV13_STATE: STATEMSK20 Mask */ #define SCT_EV13_STATE_STATEMSK21_Pos 21 /*!< SCT EV13_STATE: STATEMSK21 Position */ #define SCT_EV13_STATE_STATEMSK21_Msk (0x01UL << SCT_EV13_STATE_STATEMSK21_Pos) /*!< SCT EV13_STATE: STATEMSK21 Mask */ #define SCT_EV13_STATE_STATEMSK22_Pos 22 /*!< SCT EV13_STATE: STATEMSK22 Position */ #define SCT_EV13_STATE_STATEMSK22_Msk (0x01UL << SCT_EV13_STATE_STATEMSK22_Pos) /*!< SCT EV13_STATE: STATEMSK22 Mask */ #define SCT_EV13_STATE_STATEMSK23_Pos 23 /*!< SCT EV13_STATE: STATEMSK23 Position */ #define SCT_EV13_STATE_STATEMSK23_Msk (0x01UL << SCT_EV13_STATE_STATEMSK23_Pos) /*!< SCT EV13_STATE: STATEMSK23 Mask */ #define SCT_EV13_STATE_STATEMSK24_Pos 24 /*!< SCT EV13_STATE: STATEMSK24 Position */ #define SCT_EV13_STATE_STATEMSK24_Msk (0x01UL << SCT_EV13_STATE_STATEMSK24_Pos) /*!< SCT EV13_STATE: STATEMSK24 Mask */ #define SCT_EV13_STATE_STATEMSK25_Pos 25 /*!< SCT EV13_STATE: STATEMSK25 Position */ #define SCT_EV13_STATE_STATEMSK25_Msk (0x01UL << SCT_EV13_STATE_STATEMSK25_Pos) /*!< SCT EV13_STATE: STATEMSK25 Mask */ #define SCT_EV13_STATE_STATEMSK26_Pos 26 /*!< SCT EV13_STATE: STATEMSK26 Position */ #define SCT_EV13_STATE_STATEMSK26_Msk (0x01UL << SCT_EV13_STATE_STATEMSK26_Pos) /*!< SCT EV13_STATE: STATEMSK26 Mask */ #define SCT_EV13_STATE_STATEMSK27_Pos 27 /*!< SCT EV13_STATE: STATEMSK27 Position */ #define SCT_EV13_STATE_STATEMSK27_Msk (0x01UL << SCT_EV13_STATE_STATEMSK27_Pos) /*!< SCT EV13_STATE: STATEMSK27 Mask */ #define SCT_EV13_STATE_STATEMSK28_Pos 28 /*!< SCT EV13_STATE: STATEMSK28 Position */ #define SCT_EV13_STATE_STATEMSK28_Msk (0x01UL << SCT_EV13_STATE_STATEMSK28_Pos) /*!< SCT EV13_STATE: STATEMSK28 Mask */ #define SCT_EV13_STATE_STATEMSK29_Pos 29 /*!< SCT EV13_STATE: STATEMSK29 Position */ #define SCT_EV13_STATE_STATEMSK29_Msk (0x01UL << SCT_EV13_STATE_STATEMSK29_Pos) /*!< SCT EV13_STATE: STATEMSK29 Mask */ #define SCT_EV13_STATE_STATEMSK30_Pos 30 /*!< SCT EV13_STATE: STATEMSK30 Position */ #define SCT_EV13_STATE_STATEMSK30_Msk (0x01UL << SCT_EV13_STATE_STATEMSK30_Pos) /*!< SCT EV13_STATE: STATEMSK30 Mask */ #define SCT_EV13_STATE_STATEMSK31_Pos 31 /*!< SCT EV13_STATE: STATEMSK31 Position */ #define SCT_EV13_STATE_STATEMSK31_Msk (0x01UL << SCT_EV13_STATE_STATEMSK31_Pos) /*!< SCT EV13_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV13_CTRL ------------------------------- */ #define SCT_EV13_CTRL_MATCHSEL_Pos 0 /*!< SCT EV13_CTRL: MATCHSEL Position */ #define SCT_EV13_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV13_CTRL_MATCHSEL_Pos) /*!< SCT EV13_CTRL: MATCHSEL Mask */ #define SCT_EV13_CTRL_HEVENT_Pos 4 /*!< SCT EV13_CTRL: HEVENT Position */ #define SCT_EV13_CTRL_HEVENT_Msk (0x01UL << SCT_EV13_CTRL_HEVENT_Pos) /*!< SCT EV13_CTRL: HEVENT Mask */ #define SCT_EV13_CTRL_OUTSEL_Pos 5 /*!< SCT EV13_CTRL: OUTSEL Position */ #define SCT_EV13_CTRL_OUTSEL_Msk (0x01UL << SCT_EV13_CTRL_OUTSEL_Pos) /*!< SCT EV13_CTRL: OUTSEL Mask */ #define SCT_EV13_CTRL_IOSEL_Pos 6 /*!< SCT EV13_CTRL: IOSEL Position */ #define SCT_EV13_CTRL_IOSEL_Msk (0x0fUL << SCT_EV13_CTRL_IOSEL_Pos) /*!< SCT EV13_CTRL: IOSEL Mask */ #define SCT_EV13_CTRL_IOCOND_Pos 10 /*!< SCT EV13_CTRL: IOCOND Position */ #define SCT_EV13_CTRL_IOCOND_Msk (0x03UL << SCT_EV13_CTRL_IOCOND_Pos) /*!< SCT EV13_CTRL: IOCOND Mask */ #define SCT_EV13_CTRL_COMBMODE_Pos 12 /*!< SCT EV13_CTRL: COMBMODE Position */ #define SCT_EV13_CTRL_COMBMODE_Msk (0x03UL << SCT_EV13_CTRL_COMBMODE_Pos) /*!< SCT EV13_CTRL: COMBMODE Mask */ #define SCT_EV13_CTRL_STATELD_Pos 14 /*!< SCT EV13_CTRL: STATELD Position */ #define SCT_EV13_CTRL_STATELD_Msk (0x01UL << SCT_EV13_CTRL_STATELD_Pos) /*!< SCT EV13_CTRL: STATELD Mask */ #define SCT_EV13_CTRL_STATEV_Pos 15 /*!< SCT EV13_CTRL: STATEV Position */ #define SCT_EV13_CTRL_STATEV_Msk (0x1fUL << SCT_EV13_CTRL_STATEV_Pos) /*!< SCT EV13_CTRL: STATEV Mask */ #define SCT_EV13_CTRL_MATCHMEM_Pos 20 /*!< SCT EV13_CTRL: MATCHMEM Position */ #define SCT_EV13_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV13_CTRL_MATCHMEM_Pos) /*!< SCT EV13_CTRL: MATCHMEM Mask */ #define SCT_EV13_CTRL_DIRECTION_Pos 21 /*!< SCT EV13_CTRL: DIRECTION Position */ #define SCT_EV13_CTRL_DIRECTION_Msk (0x03UL << SCT_EV13_CTRL_DIRECTION_Pos) /*!< SCT EV13_CTRL: DIRECTION Mask */ /* ------------------------------- SCT_EV14_STATE ------------------------------- */ #define SCT_EV14_STATE_STATEMSK0_Pos 0 /*!< SCT EV14_STATE: STATEMSK0 Position */ #define SCT_EV14_STATE_STATEMSK0_Msk (0x01UL << SCT_EV14_STATE_STATEMSK0_Pos) /*!< SCT EV14_STATE: STATEMSK0 Mask */ #define SCT_EV14_STATE_STATEMSK1_Pos 1 /*!< SCT EV14_STATE: STATEMSK1 Position */ #define SCT_EV14_STATE_STATEMSK1_Msk (0x01UL << SCT_EV14_STATE_STATEMSK1_Pos) /*!< SCT EV14_STATE: STATEMSK1 Mask */ #define SCT_EV14_STATE_STATEMSK2_Pos 2 /*!< SCT EV14_STATE: STATEMSK2 Position */ #define SCT_EV14_STATE_STATEMSK2_Msk (0x01UL << SCT_EV14_STATE_STATEMSK2_Pos) /*!< SCT EV14_STATE: STATEMSK2 Mask */ #define SCT_EV14_STATE_STATEMSK3_Pos 3 /*!< SCT EV14_STATE: STATEMSK3 Position */ #define SCT_EV14_STATE_STATEMSK3_Msk (0x01UL << SCT_EV14_STATE_STATEMSK3_Pos) /*!< SCT EV14_STATE: STATEMSK3 Mask */ #define SCT_EV14_STATE_STATEMSK4_Pos 4 /*!< SCT EV14_STATE: STATEMSK4 Position */ #define SCT_EV14_STATE_STATEMSK4_Msk (0x01UL << SCT_EV14_STATE_STATEMSK4_Pos) /*!< SCT EV14_STATE: STATEMSK4 Mask */ #define SCT_EV14_STATE_STATEMSK5_Pos 5 /*!< SCT EV14_STATE: STATEMSK5 Position */ #define SCT_EV14_STATE_STATEMSK5_Msk (0x01UL << SCT_EV14_STATE_STATEMSK5_Pos) /*!< SCT EV14_STATE: STATEMSK5 Mask */ #define SCT_EV14_STATE_STATEMSK6_Pos 6 /*!< SCT EV14_STATE: STATEMSK6 Position */ #define SCT_EV14_STATE_STATEMSK6_Msk (0x01UL << SCT_EV14_STATE_STATEMSK6_Pos) /*!< SCT EV14_STATE: STATEMSK6 Mask */ #define SCT_EV14_STATE_STATEMSK7_Pos 7 /*!< SCT EV14_STATE: STATEMSK7 Position */ #define SCT_EV14_STATE_STATEMSK7_Msk (0x01UL << SCT_EV14_STATE_STATEMSK7_Pos) /*!< SCT EV14_STATE: STATEMSK7 Mask */ #define SCT_EV14_STATE_STATEMSK8_Pos 8 /*!< SCT EV14_STATE: STATEMSK8 Position */ #define SCT_EV14_STATE_STATEMSK8_Msk (0x01UL << SCT_EV14_STATE_STATEMSK8_Pos) /*!< SCT EV14_STATE: STATEMSK8 Mask */ #define SCT_EV14_STATE_STATEMSK9_Pos 9 /*!< SCT EV14_STATE: STATEMSK9 Position */ #define SCT_EV14_STATE_STATEMSK9_Msk (0x01UL << SCT_EV14_STATE_STATEMSK9_Pos) /*!< SCT EV14_STATE: STATEMSK9 Mask */ #define SCT_EV14_STATE_STATEMSK10_Pos 10 /*!< SCT EV14_STATE: STATEMSK10 Position */ #define SCT_EV14_STATE_STATEMSK10_Msk (0x01UL << SCT_EV14_STATE_STATEMSK10_Pos) /*!< SCT EV14_STATE: STATEMSK10 Mask */ #define SCT_EV14_STATE_STATEMSK11_Pos 11 /*!< SCT EV14_STATE: STATEMSK11 Position */ #define SCT_EV14_STATE_STATEMSK11_Msk (0x01UL << SCT_EV14_STATE_STATEMSK11_Pos) /*!< SCT EV14_STATE: STATEMSK11 Mask */ #define SCT_EV14_STATE_STATEMSK12_Pos 12 /*!< SCT EV14_STATE: STATEMSK12 Position */ #define SCT_EV14_STATE_STATEMSK12_Msk (0x01UL << SCT_EV14_STATE_STATEMSK12_Pos) /*!< SCT EV14_STATE: STATEMSK12 Mask */ #define SCT_EV14_STATE_STATEMSK13_Pos 13 /*!< SCT EV14_STATE: STATEMSK13 Position */ #define SCT_EV14_STATE_STATEMSK13_Msk (0x01UL << SCT_EV14_STATE_STATEMSK13_Pos) /*!< SCT EV14_STATE: STATEMSK13 Mask */ #define SCT_EV14_STATE_STATEMSK14_Pos 14 /*!< SCT EV14_STATE: STATEMSK14 Position */ #define SCT_EV14_STATE_STATEMSK14_Msk (0x01UL << SCT_EV14_STATE_STATEMSK14_Pos) /*!< SCT EV14_STATE: STATEMSK14 Mask */ #define SCT_EV14_STATE_STATEMSK15_Pos 15 /*!< SCT EV14_STATE: STATEMSK15 Position */ #define SCT_EV14_STATE_STATEMSK15_Msk (0x01UL << SCT_EV14_STATE_STATEMSK15_Pos) /*!< SCT EV14_STATE: STATEMSK15 Mask */ #define SCT_EV14_STATE_STATEMSK16_Pos 16 /*!< SCT EV14_STATE: STATEMSK16 Position */ #define SCT_EV14_STATE_STATEMSK16_Msk (0x01UL << SCT_EV14_STATE_STATEMSK16_Pos) /*!< SCT EV14_STATE: STATEMSK16 Mask */ #define SCT_EV14_STATE_STATEMSK17_Pos 17 /*!< SCT EV14_STATE: STATEMSK17 Position */ #define SCT_EV14_STATE_STATEMSK17_Msk (0x01UL << SCT_EV14_STATE_STATEMSK17_Pos) /*!< SCT EV14_STATE: STATEMSK17 Mask */ #define SCT_EV14_STATE_STATEMSK18_Pos 18 /*!< SCT EV14_STATE: STATEMSK18 Position */ #define SCT_EV14_STATE_STATEMSK18_Msk (0x01UL << SCT_EV14_STATE_STATEMSK18_Pos) /*!< SCT EV14_STATE: STATEMSK18 Mask */ #define SCT_EV14_STATE_STATEMSK19_Pos 19 /*!< SCT EV14_STATE: STATEMSK19 Position */ #define SCT_EV14_STATE_STATEMSK19_Msk (0x01UL << SCT_EV14_STATE_STATEMSK19_Pos) /*!< SCT EV14_STATE: STATEMSK19 Mask */ #define SCT_EV14_STATE_STATEMSK20_Pos 20 /*!< SCT EV14_STATE: STATEMSK20 Position */ #define SCT_EV14_STATE_STATEMSK20_Msk (0x01UL << SCT_EV14_STATE_STATEMSK20_Pos) /*!< SCT EV14_STATE: STATEMSK20 Mask */ #define SCT_EV14_STATE_STATEMSK21_Pos 21 /*!< SCT EV14_STATE: STATEMSK21 Position */ #define SCT_EV14_STATE_STATEMSK21_Msk (0x01UL << SCT_EV14_STATE_STATEMSK21_Pos) /*!< SCT EV14_STATE: STATEMSK21 Mask */ #define SCT_EV14_STATE_STATEMSK22_Pos 22 /*!< SCT EV14_STATE: STATEMSK22 Position */ #define SCT_EV14_STATE_STATEMSK22_Msk (0x01UL << SCT_EV14_STATE_STATEMSK22_Pos) /*!< SCT EV14_STATE: STATEMSK22 Mask */ #define SCT_EV14_STATE_STATEMSK23_Pos 23 /*!< SCT EV14_STATE: STATEMSK23 Position */ #define SCT_EV14_STATE_STATEMSK23_Msk (0x01UL << SCT_EV14_STATE_STATEMSK23_Pos) /*!< SCT EV14_STATE: STATEMSK23 Mask */ #define SCT_EV14_STATE_STATEMSK24_Pos 24 /*!< SCT EV14_STATE: STATEMSK24 Position */ #define SCT_EV14_STATE_STATEMSK24_Msk (0x01UL << SCT_EV14_STATE_STATEMSK24_Pos) /*!< SCT EV14_STATE: STATEMSK24 Mask */ #define SCT_EV14_STATE_STATEMSK25_Pos 25 /*!< SCT EV14_STATE: STATEMSK25 Position */ #define SCT_EV14_STATE_STATEMSK25_Msk (0x01UL << SCT_EV14_STATE_STATEMSK25_Pos) /*!< SCT EV14_STATE: STATEMSK25 Mask */ #define SCT_EV14_STATE_STATEMSK26_Pos 26 /*!< SCT EV14_STATE: STATEMSK26 Position */ #define SCT_EV14_STATE_STATEMSK26_Msk (0x01UL << SCT_EV14_STATE_STATEMSK26_Pos) /*!< SCT EV14_STATE: STATEMSK26 Mask */ #define SCT_EV14_STATE_STATEMSK27_Pos 27 /*!< SCT EV14_STATE: STATEMSK27 Position */ #define SCT_EV14_STATE_STATEMSK27_Msk (0x01UL << SCT_EV14_STATE_STATEMSK27_Pos) /*!< SCT EV14_STATE: STATEMSK27 Mask */ #define SCT_EV14_STATE_STATEMSK28_Pos 28 /*!< SCT EV14_STATE: STATEMSK28 Position */ #define SCT_EV14_STATE_STATEMSK28_Msk (0x01UL << SCT_EV14_STATE_STATEMSK28_Pos) /*!< SCT EV14_STATE: STATEMSK28 Mask */ #define SCT_EV14_STATE_STATEMSK29_Pos 29 /*!< SCT EV14_STATE: STATEMSK29 Position */ #define SCT_EV14_STATE_STATEMSK29_Msk (0x01UL << SCT_EV14_STATE_STATEMSK29_Pos) /*!< SCT EV14_STATE: STATEMSK29 Mask */ #define SCT_EV14_STATE_STATEMSK30_Pos 30 /*!< SCT EV14_STATE: STATEMSK30 Position */ #define SCT_EV14_STATE_STATEMSK30_Msk (0x01UL << SCT_EV14_STATE_STATEMSK30_Pos) /*!< SCT EV14_STATE: STATEMSK30 Mask */ #define SCT_EV14_STATE_STATEMSK31_Pos 31 /*!< SCT EV14_STATE: STATEMSK31 Position */ #define SCT_EV14_STATE_STATEMSK31_Msk (0x01UL << SCT_EV14_STATE_STATEMSK31_Pos) /*!< SCT EV14_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV14_CTRL ------------------------------- */ #define SCT_EV14_CTRL_MATCHSEL_Pos 0 /*!< SCT EV14_CTRL: MATCHSEL Position */ #define SCT_EV14_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV14_CTRL_MATCHSEL_Pos) /*!< SCT EV14_CTRL: MATCHSEL Mask */ #define SCT_EV14_CTRL_HEVENT_Pos 4 /*!< SCT EV14_CTRL: HEVENT Position */ #define SCT_EV14_CTRL_HEVENT_Msk (0x01UL << SCT_EV14_CTRL_HEVENT_Pos) /*!< SCT EV14_CTRL: HEVENT Mask */ #define SCT_EV14_CTRL_OUTSEL_Pos 5 /*!< SCT EV14_CTRL: OUTSEL Position */ #define SCT_EV14_CTRL_OUTSEL_Msk (0x01UL << SCT_EV14_CTRL_OUTSEL_Pos) /*!< SCT EV14_CTRL: OUTSEL Mask */ #define SCT_EV14_CTRL_IOSEL_Pos 6 /*!< SCT EV14_CTRL: IOSEL Position */ #define SCT_EV14_CTRL_IOSEL_Msk (0x0fUL << SCT_EV14_CTRL_IOSEL_Pos) /*!< SCT EV14_CTRL: IOSEL Mask */ #define SCT_EV14_CTRL_IOCOND_Pos 10 /*!< SCT EV14_CTRL: IOCOND Position */ #define SCT_EV14_CTRL_IOCOND_Msk (0x03UL << SCT_EV14_CTRL_IOCOND_Pos) /*!< SCT EV14_CTRL: IOCOND Mask */ #define SCT_EV14_CTRL_COMBMODE_Pos 12 /*!< SCT EV14_CTRL: COMBMODE Position */ #define SCT_EV14_CTRL_COMBMODE_Msk (0x03UL << SCT_EV14_CTRL_COMBMODE_Pos) /*!< SCT EV14_CTRL: COMBMODE Mask */ #define SCT_EV14_CTRL_STATELD_Pos 14 /*!< SCT EV14_CTRL: STATELD Position */ #define SCT_EV14_CTRL_STATELD_Msk (0x01UL << SCT_EV14_CTRL_STATELD_Pos) /*!< SCT EV14_CTRL: STATELD Mask */ #define SCT_EV14_CTRL_STATEV_Pos 15 /*!< SCT EV14_CTRL: STATEV Position */ #define SCT_EV14_CTRL_STATEV_Msk (0x1fUL << SCT_EV14_CTRL_STATEV_Pos) /*!< SCT EV14_CTRL: STATEV Mask */ #define SCT_EV14_CTRL_MATCHMEM_Pos 20 /*!< SCT EV14_CTRL: MATCHMEM Position */ #define SCT_EV14_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV14_CTRL_MATCHMEM_Pos) /*!< SCT EV14_CTRL: MATCHMEM Mask */ #define SCT_EV14_CTRL_DIRECTION_Pos 21 /*!< SCT EV14_CTRL: DIRECTION Position */ #define SCT_EV14_CTRL_DIRECTION_Msk (0x03UL << SCT_EV14_CTRL_DIRECTION_Pos) /*!< SCT EV14_CTRL: DIRECTION Mask */ /* ------------------------------- SCT_EV15_STATE ------------------------------- */ #define SCT_EV15_STATE_STATEMSK0_Pos 0 /*!< SCT EV15_STATE: STATEMSK0 Position */ #define SCT_EV15_STATE_STATEMSK0_Msk (0x01UL << SCT_EV15_STATE_STATEMSK0_Pos) /*!< SCT EV15_STATE: STATEMSK0 Mask */ #define SCT_EV15_STATE_STATEMSK1_Pos 1 /*!< SCT EV15_STATE: STATEMSK1 Position */ #define SCT_EV15_STATE_STATEMSK1_Msk (0x01UL << SCT_EV15_STATE_STATEMSK1_Pos) /*!< SCT EV15_STATE: STATEMSK1 Mask */ #define SCT_EV15_STATE_STATEMSK2_Pos 2 /*!< SCT EV15_STATE: STATEMSK2 Position */ #define SCT_EV15_STATE_STATEMSK2_Msk (0x01UL << SCT_EV15_STATE_STATEMSK2_Pos) /*!< SCT EV15_STATE: STATEMSK2 Mask */ #define SCT_EV15_STATE_STATEMSK3_Pos 3 /*!< SCT EV15_STATE: STATEMSK3 Position */ #define SCT_EV15_STATE_STATEMSK3_Msk (0x01UL << SCT_EV15_STATE_STATEMSK3_Pos) /*!< SCT EV15_STATE: STATEMSK3 Mask */ #define SCT_EV15_STATE_STATEMSK4_Pos 4 /*!< SCT EV15_STATE: STATEMSK4 Position */ #define SCT_EV15_STATE_STATEMSK4_Msk (0x01UL << SCT_EV15_STATE_STATEMSK4_Pos) /*!< SCT EV15_STATE: STATEMSK4 Mask */ #define SCT_EV15_STATE_STATEMSK5_Pos 5 /*!< SCT EV15_STATE: STATEMSK5 Position */ #define SCT_EV15_STATE_STATEMSK5_Msk (0x01UL << SCT_EV15_STATE_STATEMSK5_Pos) /*!< SCT EV15_STATE: STATEMSK5 Mask */ #define SCT_EV15_STATE_STATEMSK6_Pos 6 /*!< SCT EV15_STATE: STATEMSK6 Position */ #define SCT_EV15_STATE_STATEMSK6_Msk (0x01UL << SCT_EV15_STATE_STATEMSK6_Pos) /*!< SCT EV15_STATE: STATEMSK6 Mask */ #define SCT_EV15_STATE_STATEMSK7_Pos 7 /*!< SCT EV15_STATE: STATEMSK7 Position */ #define SCT_EV15_STATE_STATEMSK7_Msk (0x01UL << SCT_EV15_STATE_STATEMSK7_Pos) /*!< SCT EV15_STATE: STATEMSK7 Mask */ #define SCT_EV15_STATE_STATEMSK8_Pos 8 /*!< SCT EV15_STATE: STATEMSK8 Position */ #define SCT_EV15_STATE_STATEMSK8_Msk (0x01UL << SCT_EV15_STATE_STATEMSK8_Pos) /*!< SCT EV15_STATE: STATEMSK8 Mask */ #define SCT_EV15_STATE_STATEMSK9_Pos 9 /*!< SCT EV15_STATE: STATEMSK9 Position */ #define SCT_EV15_STATE_STATEMSK9_Msk (0x01UL << SCT_EV15_STATE_STATEMSK9_Pos) /*!< SCT EV15_STATE: STATEMSK9 Mask */ #define SCT_EV15_STATE_STATEMSK10_Pos 10 /*!< SCT EV15_STATE: STATEMSK10 Position */ #define SCT_EV15_STATE_STATEMSK10_Msk (0x01UL << SCT_EV15_STATE_STATEMSK10_Pos) /*!< SCT EV15_STATE: STATEMSK10 Mask */ #define SCT_EV15_STATE_STATEMSK11_Pos 11 /*!< SCT EV15_STATE: STATEMSK11 Position */ #define SCT_EV15_STATE_STATEMSK11_Msk (0x01UL << SCT_EV15_STATE_STATEMSK11_Pos) /*!< SCT EV15_STATE: STATEMSK11 Mask */ #define SCT_EV15_STATE_STATEMSK12_Pos 12 /*!< SCT EV15_STATE: STATEMSK12 Position */ #define SCT_EV15_STATE_STATEMSK12_Msk (0x01UL << SCT_EV15_STATE_STATEMSK12_Pos) /*!< SCT EV15_STATE: STATEMSK12 Mask */ #define SCT_EV15_STATE_STATEMSK13_Pos 13 /*!< SCT EV15_STATE: STATEMSK13 Position */ #define SCT_EV15_STATE_STATEMSK13_Msk (0x01UL << SCT_EV15_STATE_STATEMSK13_Pos) /*!< SCT EV15_STATE: STATEMSK13 Mask */ #define SCT_EV15_STATE_STATEMSK14_Pos 14 /*!< SCT EV15_STATE: STATEMSK14 Position */ #define SCT_EV15_STATE_STATEMSK14_Msk (0x01UL << SCT_EV15_STATE_STATEMSK14_Pos) /*!< SCT EV15_STATE: STATEMSK14 Mask */ #define SCT_EV15_STATE_STATEMSK15_Pos 15 /*!< SCT EV15_STATE: STATEMSK15 Position */ #define SCT_EV15_STATE_STATEMSK15_Msk (0x01UL << SCT_EV15_STATE_STATEMSK15_Pos) /*!< SCT EV15_STATE: STATEMSK15 Mask */ #define SCT_EV15_STATE_STATEMSK16_Pos 16 /*!< SCT EV15_STATE: STATEMSK16 Position */ #define SCT_EV15_STATE_STATEMSK16_Msk (0x01UL << SCT_EV15_STATE_STATEMSK16_Pos) /*!< SCT EV15_STATE: STATEMSK16 Mask */ #define SCT_EV15_STATE_STATEMSK17_Pos 17 /*!< SCT EV15_STATE: STATEMSK17 Position */ #define SCT_EV15_STATE_STATEMSK17_Msk (0x01UL << SCT_EV15_STATE_STATEMSK17_Pos) /*!< SCT EV15_STATE: STATEMSK17 Mask */ #define SCT_EV15_STATE_STATEMSK18_Pos 18 /*!< SCT EV15_STATE: STATEMSK18 Position */ #define SCT_EV15_STATE_STATEMSK18_Msk (0x01UL << SCT_EV15_STATE_STATEMSK18_Pos) /*!< SCT EV15_STATE: STATEMSK18 Mask */ #define SCT_EV15_STATE_STATEMSK19_Pos 19 /*!< SCT EV15_STATE: STATEMSK19 Position */ #define SCT_EV15_STATE_STATEMSK19_Msk (0x01UL << SCT_EV15_STATE_STATEMSK19_Pos) /*!< SCT EV15_STATE: STATEMSK19 Mask */ #define SCT_EV15_STATE_STATEMSK20_Pos 20 /*!< SCT EV15_STATE: STATEMSK20 Position */ #define SCT_EV15_STATE_STATEMSK20_Msk (0x01UL << SCT_EV15_STATE_STATEMSK20_Pos) /*!< SCT EV15_STATE: STATEMSK20 Mask */ #define SCT_EV15_STATE_STATEMSK21_Pos 21 /*!< SCT EV15_STATE: STATEMSK21 Position */ #define SCT_EV15_STATE_STATEMSK21_Msk (0x01UL << SCT_EV15_STATE_STATEMSK21_Pos) /*!< SCT EV15_STATE: STATEMSK21 Mask */ #define SCT_EV15_STATE_STATEMSK22_Pos 22 /*!< SCT EV15_STATE: STATEMSK22 Position */ #define SCT_EV15_STATE_STATEMSK22_Msk (0x01UL << SCT_EV15_STATE_STATEMSK22_Pos) /*!< SCT EV15_STATE: STATEMSK22 Mask */ #define SCT_EV15_STATE_STATEMSK23_Pos 23 /*!< SCT EV15_STATE: STATEMSK23 Position */ #define SCT_EV15_STATE_STATEMSK23_Msk (0x01UL << SCT_EV15_STATE_STATEMSK23_Pos) /*!< SCT EV15_STATE: STATEMSK23 Mask */ #define SCT_EV15_STATE_STATEMSK24_Pos 24 /*!< SCT EV15_STATE: STATEMSK24 Position */ #define SCT_EV15_STATE_STATEMSK24_Msk (0x01UL << SCT_EV15_STATE_STATEMSK24_Pos) /*!< SCT EV15_STATE: STATEMSK24 Mask */ #define SCT_EV15_STATE_STATEMSK25_Pos 25 /*!< SCT EV15_STATE: STATEMSK25 Position */ #define SCT_EV15_STATE_STATEMSK25_Msk (0x01UL << SCT_EV15_STATE_STATEMSK25_Pos) /*!< SCT EV15_STATE: STATEMSK25 Mask */ #define SCT_EV15_STATE_STATEMSK26_Pos 26 /*!< SCT EV15_STATE: STATEMSK26 Position */ #define SCT_EV15_STATE_STATEMSK26_Msk (0x01UL << SCT_EV15_STATE_STATEMSK26_Pos) /*!< SCT EV15_STATE: STATEMSK26 Mask */ #define SCT_EV15_STATE_STATEMSK27_Pos 27 /*!< SCT EV15_STATE: STATEMSK27 Position */ #define SCT_EV15_STATE_STATEMSK27_Msk (0x01UL << SCT_EV15_STATE_STATEMSK27_Pos) /*!< SCT EV15_STATE: STATEMSK27 Mask */ #define SCT_EV15_STATE_STATEMSK28_Pos 28 /*!< SCT EV15_STATE: STATEMSK28 Position */ #define SCT_EV15_STATE_STATEMSK28_Msk (0x01UL << SCT_EV15_STATE_STATEMSK28_Pos) /*!< SCT EV15_STATE: STATEMSK28 Mask */ #define SCT_EV15_STATE_STATEMSK29_Pos 29 /*!< SCT EV15_STATE: STATEMSK29 Position */ #define SCT_EV15_STATE_STATEMSK29_Msk (0x01UL << SCT_EV15_STATE_STATEMSK29_Pos) /*!< SCT EV15_STATE: STATEMSK29 Mask */ #define SCT_EV15_STATE_STATEMSK30_Pos 30 /*!< SCT EV15_STATE: STATEMSK30 Position */ #define SCT_EV15_STATE_STATEMSK30_Msk (0x01UL << SCT_EV15_STATE_STATEMSK30_Pos) /*!< SCT EV15_STATE: STATEMSK30 Mask */ #define SCT_EV15_STATE_STATEMSK31_Pos 31 /*!< SCT EV15_STATE: STATEMSK31 Position */ #define SCT_EV15_STATE_STATEMSK31_Msk (0x01UL << SCT_EV15_STATE_STATEMSK31_Pos) /*!< SCT EV15_STATE: STATEMSK31 Mask */ /* -------------------------------- SCT_EV15_CTRL ------------------------------- */ #define SCT_EV15_CTRL_MATCHSEL_Pos 0 /*!< SCT EV15_CTRL: MATCHSEL Position */ #define SCT_EV15_CTRL_MATCHSEL_Msk (0x0fUL << SCT_EV15_CTRL_MATCHSEL_Pos) /*!< SCT EV15_CTRL: MATCHSEL Mask */ #define SCT_EV15_CTRL_HEVENT_Pos 4 /*!< SCT EV15_CTRL: HEVENT Position */ #define SCT_EV15_CTRL_HEVENT_Msk (0x01UL << SCT_EV15_CTRL_HEVENT_Pos) /*!< SCT EV15_CTRL: HEVENT Mask */ #define SCT_EV15_CTRL_OUTSEL_Pos 5 /*!< SCT EV15_CTRL: OUTSEL Position */ #define SCT_EV15_CTRL_OUTSEL_Msk (0x01UL << SCT_EV15_CTRL_OUTSEL_Pos) /*!< SCT EV15_CTRL: OUTSEL Mask */ #define SCT_EV15_CTRL_IOSEL_Pos 6 /*!< SCT EV15_CTRL: IOSEL Position */ #define SCT_EV15_CTRL_IOSEL_Msk (0x0fUL << SCT_EV15_CTRL_IOSEL_Pos) /*!< SCT EV15_CTRL: IOSEL Mask */ #define SCT_EV15_CTRL_IOCOND_Pos 10 /*!< SCT EV15_CTRL: IOCOND Position */ #define SCT_EV15_CTRL_IOCOND_Msk (0x03UL << SCT_EV15_CTRL_IOCOND_Pos) /*!< SCT EV15_CTRL: IOCOND Mask */ #define SCT_EV15_CTRL_COMBMODE_Pos 12 /*!< SCT EV15_CTRL: COMBMODE Position */ #define SCT_EV15_CTRL_COMBMODE_Msk (0x03UL << SCT_EV15_CTRL_COMBMODE_Pos) /*!< SCT EV15_CTRL: COMBMODE Mask */ #define SCT_EV15_CTRL_STATELD_Pos 14 /*!< SCT EV15_CTRL: STATELD Position */ #define SCT_EV15_CTRL_STATELD_Msk (0x01UL << SCT_EV15_CTRL_STATELD_Pos) /*!< SCT EV15_CTRL: STATELD Mask */ #define SCT_EV15_CTRL_STATEV_Pos 15 /*!< SCT EV15_CTRL: STATEV Position */ #define SCT_EV15_CTRL_STATEV_Msk (0x1fUL << SCT_EV15_CTRL_STATEV_Pos) /*!< SCT EV15_CTRL: STATEV Mask */ #define SCT_EV15_CTRL_MATCHMEM_Pos 20 /*!< SCT EV15_CTRL: MATCHMEM Position */ #define SCT_EV15_CTRL_MATCHMEM_Msk (0x01UL << SCT_EV15_CTRL_MATCHMEM_Pos) /*!< SCT EV15_CTRL: MATCHMEM Mask */ #define SCT_EV15_CTRL_DIRECTION_Pos 21 /*!< SCT EV15_CTRL: DIRECTION Position */ #define SCT_EV15_CTRL_DIRECTION_Msk (0x03UL << SCT_EV15_CTRL_DIRECTION_Pos) /*!< SCT EV15_CTRL: DIRECTION Mask */ /* -------------------------------- SCT_OUT0_SET -------------------------------- */ #define SCT_OUT0_SET_SET0_Pos 0 /*!< SCT OUT0_SET: SET0 Position */ #define SCT_OUT0_SET_SET0_Msk (0x01UL << SCT_OUT0_SET_SET0_Pos) /*!< SCT OUT0_SET: SET0 Mask */ #define SCT_OUT0_SET_SET1_Pos 1 /*!< SCT OUT0_SET: SET1 Position */ #define SCT_OUT0_SET_SET1_Msk (0x01UL << SCT_OUT0_SET_SET1_Pos) /*!< SCT OUT0_SET: SET1 Mask */ #define SCT_OUT0_SET_SET2_Pos 2 /*!< SCT OUT0_SET: SET2 Position */ #define SCT_OUT0_SET_SET2_Msk (0x01UL << SCT_OUT0_SET_SET2_Pos) /*!< SCT OUT0_SET: SET2 Mask */ #define SCT_OUT0_SET_SET3_Pos 3 /*!< SCT OUT0_SET: SET3 Position */ #define SCT_OUT0_SET_SET3_Msk (0x01UL << SCT_OUT0_SET_SET3_Pos) /*!< SCT OUT0_SET: SET3 Mask */ #define SCT_OUT0_SET_SET4_Pos 4 /*!< SCT OUT0_SET: SET4 Position */ #define SCT_OUT0_SET_SET4_Msk (0x01UL << SCT_OUT0_SET_SET4_Pos) /*!< SCT OUT0_SET: SET4 Mask */ #define SCT_OUT0_SET_SET5_Pos 5 /*!< SCT OUT0_SET: SET5 Position */ #define SCT_OUT0_SET_SET5_Msk (0x01UL << SCT_OUT0_SET_SET5_Pos) /*!< SCT OUT0_SET: SET5 Mask */ #define SCT_OUT0_SET_SET6_Pos 6 /*!< SCT OUT0_SET: SET6 Position */ #define SCT_OUT0_SET_SET6_Msk (0x01UL << SCT_OUT0_SET_SET6_Pos) /*!< SCT OUT0_SET: SET6 Mask */ #define SCT_OUT0_SET_SET7_Pos 7 /*!< SCT OUT0_SET: SET7 Position */ #define SCT_OUT0_SET_SET7_Msk (0x01UL << SCT_OUT0_SET_SET7_Pos) /*!< SCT OUT0_SET: SET7 Mask */ #define SCT_OUT0_SET_SET8_Pos 8 /*!< SCT OUT0_SET: SET8 Position */ #define SCT_OUT0_SET_SET8_Msk (0x01UL << SCT_OUT0_SET_SET8_Pos) /*!< SCT OUT0_SET: SET8 Mask */ #define SCT_OUT0_SET_SET9_Pos 9 /*!< SCT OUT0_SET: SET9 Position */ #define SCT_OUT0_SET_SET9_Msk (0x01UL << SCT_OUT0_SET_SET9_Pos) /*!< SCT OUT0_SET: SET9 Mask */ #define SCT_OUT0_SET_SET10_Pos 10 /*!< SCT OUT0_SET: SET10 Position */ #define SCT_OUT0_SET_SET10_Msk (0x01UL << SCT_OUT0_SET_SET10_Pos) /*!< SCT OUT0_SET: SET10 Mask */ #define SCT_OUT0_SET_SET11_Pos 11 /*!< SCT OUT0_SET: SET11 Position */ #define SCT_OUT0_SET_SET11_Msk (0x01UL << SCT_OUT0_SET_SET11_Pos) /*!< SCT OUT0_SET: SET11 Mask */ #define SCT_OUT0_SET_SET12_Pos 12 /*!< SCT OUT0_SET: SET12 Position */ #define SCT_OUT0_SET_SET12_Msk (0x01UL << SCT_OUT0_SET_SET12_Pos) /*!< SCT OUT0_SET: SET12 Mask */ #define SCT_OUT0_SET_SET13_Pos 13 /*!< SCT OUT0_SET: SET13 Position */ #define SCT_OUT0_SET_SET13_Msk (0x01UL << SCT_OUT0_SET_SET13_Pos) /*!< SCT OUT0_SET: SET13 Mask */ #define SCT_OUT0_SET_SET14_Pos 14 /*!< SCT OUT0_SET: SET14 Position */ #define SCT_OUT0_SET_SET14_Msk (0x01UL << SCT_OUT0_SET_SET14_Pos) /*!< SCT OUT0_SET: SET14 Mask */ #define SCT_OUT0_SET_SET15_Pos 15 /*!< SCT OUT0_SET: SET15 Position */ #define SCT_OUT0_SET_SET15_Msk (0x01UL << SCT_OUT0_SET_SET15_Pos) /*!< SCT OUT0_SET: SET15 Mask */ /* -------------------------------- SCT_OUT0_CLR -------------------------------- */ #define SCT_OUT0_CLR_CLR0_Pos 0 /*!< SCT OUT0_CLR: CLR0 Position */ #define SCT_OUT0_CLR_CLR0_Msk (0x01UL << SCT_OUT0_CLR_CLR0_Pos) /*!< SCT OUT0_CLR: CLR0 Mask */ #define SCT_OUT0_CLR_CLR1_Pos 1 /*!< SCT OUT0_CLR: CLR1 Position */ #define SCT_OUT0_CLR_CLR1_Msk (0x01UL << SCT_OUT0_CLR_CLR1_Pos) /*!< SCT OUT0_CLR: CLR1 Mask */ #define SCT_OUT0_CLR_CLR2_Pos 2 /*!< SCT OUT0_CLR: CLR2 Position */ #define SCT_OUT0_CLR_CLR2_Msk (0x01UL << SCT_OUT0_CLR_CLR2_Pos) /*!< SCT OUT0_CLR: CLR2 Mask */ #define SCT_OUT0_CLR_CLR3_Pos 3 /*!< SCT OUT0_CLR: CLR3 Position */ #define SCT_OUT0_CLR_CLR3_Msk (0x01UL << SCT_OUT0_CLR_CLR3_Pos) /*!< SCT OUT0_CLR: CLR3 Mask */ #define SCT_OUT0_CLR_CLR4_Pos 4 /*!< SCT OUT0_CLR: CLR4 Position */ #define SCT_OUT0_CLR_CLR4_Msk (0x01UL << SCT_OUT0_CLR_CLR4_Pos) /*!< SCT OUT0_CLR: CLR4 Mask */ #define SCT_OUT0_CLR_CLR5_Pos 5 /*!< SCT OUT0_CLR: CLR5 Position */ #define SCT_OUT0_CLR_CLR5_Msk (0x01UL << SCT_OUT0_CLR_CLR5_Pos) /*!< SCT OUT0_CLR: CLR5 Mask */ #define SCT_OUT0_CLR_CLR6_Pos 6 /*!< SCT OUT0_CLR: CLR6 Position */ #define SCT_OUT0_CLR_CLR6_Msk (0x01UL << SCT_OUT0_CLR_CLR6_Pos) /*!< SCT OUT0_CLR: CLR6 Mask */ #define SCT_OUT0_CLR_CLR7_Pos 7 /*!< SCT OUT0_CLR: CLR7 Position */ #define SCT_OUT0_CLR_CLR7_Msk (0x01UL << SCT_OUT0_CLR_CLR7_Pos) /*!< SCT OUT0_CLR: CLR7 Mask */ #define SCT_OUT0_CLR_CLR8_Pos 8 /*!< SCT OUT0_CLR: CLR8 Position */ #define SCT_OUT0_CLR_CLR8_Msk (0x01UL << SCT_OUT0_CLR_CLR8_Pos) /*!< SCT OUT0_CLR: CLR8 Mask */ #define SCT_OUT0_CLR_CLR9_Pos 9 /*!< SCT OUT0_CLR: CLR9 Position */ #define SCT_OUT0_CLR_CLR9_Msk (0x01UL << SCT_OUT0_CLR_CLR9_Pos) /*!< SCT OUT0_CLR: CLR9 Mask */ #define SCT_OUT0_CLR_CLR10_Pos 10 /*!< SCT OUT0_CLR: CLR10 Position */ #define SCT_OUT0_CLR_CLR10_Msk (0x01UL << SCT_OUT0_CLR_CLR10_Pos) /*!< SCT OUT0_CLR: CLR10 Mask */ #define SCT_OUT0_CLR_CLR11_Pos 11 /*!< SCT OUT0_CLR: CLR11 Position */ #define SCT_OUT0_CLR_CLR11_Msk (0x01UL << SCT_OUT0_CLR_CLR11_Pos) /*!< SCT OUT0_CLR: CLR11 Mask */ #define SCT_OUT0_CLR_CLR12_Pos 12 /*!< SCT OUT0_CLR: CLR12 Position */ #define SCT_OUT0_CLR_CLR12_Msk (0x01UL << SCT_OUT0_CLR_CLR12_Pos) /*!< SCT OUT0_CLR: CLR12 Mask */ #define SCT_OUT0_CLR_CLR13_Pos 13 /*!< SCT OUT0_CLR: CLR13 Position */ #define SCT_OUT0_CLR_CLR13_Msk (0x01UL << SCT_OUT0_CLR_CLR13_Pos) /*!< SCT OUT0_CLR: CLR13 Mask */ #define SCT_OUT0_CLR_CLR14_Pos 14 /*!< SCT OUT0_CLR: CLR14 Position */ #define SCT_OUT0_CLR_CLR14_Msk (0x01UL << SCT_OUT0_CLR_CLR14_Pos) /*!< SCT OUT0_CLR: CLR14 Mask */ #define SCT_OUT0_CLR_CLR15_Pos 15 /*!< SCT OUT0_CLR: CLR15 Position */ #define SCT_OUT0_CLR_CLR15_Msk (0x01UL << SCT_OUT0_CLR_CLR15_Pos) /*!< SCT OUT0_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT1_SET -------------------------------- */ #define SCT_OUT1_SET_SET0_Pos 0 /*!< SCT OUT1_SET: SET0 Position */ #define SCT_OUT1_SET_SET0_Msk (0x01UL << SCT_OUT1_SET_SET0_Pos) /*!< SCT OUT1_SET: SET0 Mask */ #define SCT_OUT1_SET_SET1_Pos 1 /*!< SCT OUT1_SET: SET1 Position */ #define SCT_OUT1_SET_SET1_Msk (0x01UL << SCT_OUT1_SET_SET1_Pos) /*!< SCT OUT1_SET: SET1 Mask */ #define SCT_OUT1_SET_SET2_Pos 2 /*!< SCT OUT1_SET: SET2 Position */ #define SCT_OUT1_SET_SET2_Msk (0x01UL << SCT_OUT1_SET_SET2_Pos) /*!< SCT OUT1_SET: SET2 Mask */ #define SCT_OUT1_SET_SET3_Pos 3 /*!< SCT OUT1_SET: SET3 Position */ #define SCT_OUT1_SET_SET3_Msk (0x01UL << SCT_OUT1_SET_SET3_Pos) /*!< SCT OUT1_SET: SET3 Mask */ #define SCT_OUT1_SET_SET4_Pos 4 /*!< SCT OUT1_SET: SET4 Position */ #define SCT_OUT1_SET_SET4_Msk (0x01UL << SCT_OUT1_SET_SET4_Pos) /*!< SCT OUT1_SET: SET4 Mask */ #define SCT_OUT1_SET_SET5_Pos 5 /*!< SCT OUT1_SET: SET5 Position */ #define SCT_OUT1_SET_SET5_Msk (0x01UL << SCT_OUT1_SET_SET5_Pos) /*!< SCT OUT1_SET: SET5 Mask */ #define SCT_OUT1_SET_SET6_Pos 6 /*!< SCT OUT1_SET: SET6 Position */ #define SCT_OUT1_SET_SET6_Msk (0x01UL << SCT_OUT1_SET_SET6_Pos) /*!< SCT OUT1_SET: SET6 Mask */ #define SCT_OUT1_SET_SET7_Pos 7 /*!< SCT OUT1_SET: SET7 Position */ #define SCT_OUT1_SET_SET7_Msk (0x01UL << SCT_OUT1_SET_SET7_Pos) /*!< SCT OUT1_SET: SET7 Mask */ #define SCT_OUT1_SET_SET8_Pos 8 /*!< SCT OUT1_SET: SET8 Position */ #define SCT_OUT1_SET_SET8_Msk (0x01UL << SCT_OUT1_SET_SET8_Pos) /*!< SCT OUT1_SET: SET8 Mask */ #define SCT_OUT1_SET_SET9_Pos 9 /*!< SCT OUT1_SET: SET9 Position */ #define SCT_OUT1_SET_SET9_Msk (0x01UL << SCT_OUT1_SET_SET9_Pos) /*!< SCT OUT1_SET: SET9 Mask */ #define SCT_OUT1_SET_SET10_Pos 10 /*!< SCT OUT1_SET: SET10 Position */ #define SCT_OUT1_SET_SET10_Msk (0x01UL << SCT_OUT1_SET_SET10_Pos) /*!< SCT OUT1_SET: SET10 Mask */ #define SCT_OUT1_SET_SET11_Pos 11 /*!< SCT OUT1_SET: SET11 Position */ #define SCT_OUT1_SET_SET11_Msk (0x01UL << SCT_OUT1_SET_SET11_Pos) /*!< SCT OUT1_SET: SET11 Mask */ #define SCT_OUT1_SET_SET12_Pos 12 /*!< SCT OUT1_SET: SET12 Position */ #define SCT_OUT1_SET_SET12_Msk (0x01UL << SCT_OUT1_SET_SET12_Pos) /*!< SCT OUT1_SET: SET12 Mask */ #define SCT_OUT1_SET_SET13_Pos 13 /*!< SCT OUT1_SET: SET13 Position */ #define SCT_OUT1_SET_SET13_Msk (0x01UL << SCT_OUT1_SET_SET13_Pos) /*!< SCT OUT1_SET: SET13 Mask */ #define SCT_OUT1_SET_SET14_Pos 14 /*!< SCT OUT1_SET: SET14 Position */ #define SCT_OUT1_SET_SET14_Msk (0x01UL << SCT_OUT1_SET_SET14_Pos) /*!< SCT OUT1_SET: SET14 Mask */ #define SCT_OUT1_SET_SET15_Pos 15 /*!< SCT OUT1_SET: SET15 Position */ #define SCT_OUT1_SET_SET15_Msk (0x01UL << SCT_OUT1_SET_SET15_Pos) /*!< SCT OUT1_SET: SET15 Mask */ /* -------------------------------- SCT_OUT1_CLR -------------------------------- */ #define SCT_OUT1_CLR_CLR0_Pos 0 /*!< SCT OUT1_CLR: CLR0 Position */ #define SCT_OUT1_CLR_CLR0_Msk (0x01UL << SCT_OUT1_CLR_CLR0_Pos) /*!< SCT OUT1_CLR: CLR0 Mask */ #define SCT_OUT1_CLR_CLR1_Pos 1 /*!< SCT OUT1_CLR: CLR1 Position */ #define SCT_OUT1_CLR_CLR1_Msk (0x01UL << SCT_OUT1_CLR_CLR1_Pos) /*!< SCT OUT1_CLR: CLR1 Mask */ #define SCT_OUT1_CLR_CLR2_Pos 2 /*!< SCT OUT1_CLR: CLR2 Position */ #define SCT_OUT1_CLR_CLR2_Msk (0x01UL << SCT_OUT1_CLR_CLR2_Pos) /*!< SCT OUT1_CLR: CLR2 Mask */ #define SCT_OUT1_CLR_CLR3_Pos 3 /*!< SCT OUT1_CLR: CLR3 Position */ #define SCT_OUT1_CLR_CLR3_Msk (0x01UL << SCT_OUT1_CLR_CLR3_Pos) /*!< SCT OUT1_CLR: CLR3 Mask */ #define SCT_OUT1_CLR_CLR4_Pos 4 /*!< SCT OUT1_CLR: CLR4 Position */ #define SCT_OUT1_CLR_CLR4_Msk (0x01UL << SCT_OUT1_CLR_CLR4_Pos) /*!< SCT OUT1_CLR: CLR4 Mask */ #define SCT_OUT1_CLR_CLR5_Pos 5 /*!< SCT OUT1_CLR: CLR5 Position */ #define SCT_OUT1_CLR_CLR5_Msk (0x01UL << SCT_OUT1_CLR_CLR5_Pos) /*!< SCT OUT1_CLR: CLR5 Mask */ #define SCT_OUT1_CLR_CLR6_Pos 6 /*!< SCT OUT1_CLR: CLR6 Position */ #define SCT_OUT1_CLR_CLR6_Msk (0x01UL << SCT_OUT1_CLR_CLR6_Pos) /*!< SCT OUT1_CLR: CLR6 Mask */ #define SCT_OUT1_CLR_CLR7_Pos 7 /*!< SCT OUT1_CLR: CLR7 Position */ #define SCT_OUT1_CLR_CLR7_Msk (0x01UL << SCT_OUT1_CLR_CLR7_Pos) /*!< SCT OUT1_CLR: CLR7 Mask */ #define SCT_OUT1_CLR_CLR8_Pos 8 /*!< SCT OUT1_CLR: CLR8 Position */ #define SCT_OUT1_CLR_CLR8_Msk (0x01UL << SCT_OUT1_CLR_CLR8_Pos) /*!< SCT OUT1_CLR: CLR8 Mask */ #define SCT_OUT1_CLR_CLR9_Pos 9 /*!< SCT OUT1_CLR: CLR9 Position */ #define SCT_OUT1_CLR_CLR9_Msk (0x01UL << SCT_OUT1_CLR_CLR9_Pos) /*!< SCT OUT1_CLR: CLR9 Mask */ #define SCT_OUT1_CLR_CLR10_Pos 10 /*!< SCT OUT1_CLR: CLR10 Position */ #define SCT_OUT1_CLR_CLR10_Msk (0x01UL << SCT_OUT1_CLR_CLR10_Pos) /*!< SCT OUT1_CLR: CLR10 Mask */ #define SCT_OUT1_CLR_CLR11_Pos 11 /*!< SCT OUT1_CLR: CLR11 Position */ #define SCT_OUT1_CLR_CLR11_Msk (0x01UL << SCT_OUT1_CLR_CLR11_Pos) /*!< SCT OUT1_CLR: CLR11 Mask */ #define SCT_OUT1_CLR_CLR12_Pos 12 /*!< SCT OUT1_CLR: CLR12 Position */ #define SCT_OUT1_CLR_CLR12_Msk (0x01UL << SCT_OUT1_CLR_CLR12_Pos) /*!< SCT OUT1_CLR: CLR12 Mask */ #define SCT_OUT1_CLR_CLR13_Pos 13 /*!< SCT OUT1_CLR: CLR13 Position */ #define SCT_OUT1_CLR_CLR13_Msk (0x01UL << SCT_OUT1_CLR_CLR13_Pos) /*!< SCT OUT1_CLR: CLR13 Mask */ #define SCT_OUT1_CLR_CLR14_Pos 14 /*!< SCT OUT1_CLR: CLR14 Position */ #define SCT_OUT1_CLR_CLR14_Msk (0x01UL << SCT_OUT1_CLR_CLR14_Pos) /*!< SCT OUT1_CLR: CLR14 Mask */ #define SCT_OUT1_CLR_CLR15_Pos 15 /*!< SCT OUT1_CLR: CLR15 Position */ #define SCT_OUT1_CLR_CLR15_Msk (0x01UL << SCT_OUT1_CLR_CLR15_Pos) /*!< SCT OUT1_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT2_SET -------------------------------- */ #define SCT_OUT2_SET_SET0_Pos 0 /*!< SCT OUT2_SET: SET0 Position */ #define SCT_OUT2_SET_SET0_Msk (0x01UL << SCT_OUT2_SET_SET0_Pos) /*!< SCT OUT2_SET: SET0 Mask */ #define SCT_OUT2_SET_SET1_Pos 1 /*!< SCT OUT2_SET: SET1 Position */ #define SCT_OUT2_SET_SET1_Msk (0x01UL << SCT_OUT2_SET_SET1_Pos) /*!< SCT OUT2_SET: SET1 Mask */ #define SCT_OUT2_SET_SET2_Pos 2 /*!< SCT OUT2_SET: SET2 Position */ #define SCT_OUT2_SET_SET2_Msk (0x01UL << SCT_OUT2_SET_SET2_Pos) /*!< SCT OUT2_SET: SET2 Mask */ #define SCT_OUT2_SET_SET3_Pos 3 /*!< SCT OUT2_SET: SET3 Position */ #define SCT_OUT2_SET_SET3_Msk (0x01UL << SCT_OUT2_SET_SET3_Pos) /*!< SCT OUT2_SET: SET3 Mask */ #define SCT_OUT2_SET_SET4_Pos 4 /*!< SCT OUT2_SET: SET4 Position */ #define SCT_OUT2_SET_SET4_Msk (0x01UL << SCT_OUT2_SET_SET4_Pos) /*!< SCT OUT2_SET: SET4 Mask */ #define SCT_OUT2_SET_SET5_Pos 5 /*!< SCT OUT2_SET: SET5 Position */ #define SCT_OUT2_SET_SET5_Msk (0x01UL << SCT_OUT2_SET_SET5_Pos) /*!< SCT OUT2_SET: SET5 Mask */ #define SCT_OUT2_SET_SET6_Pos 6 /*!< SCT OUT2_SET: SET6 Position */ #define SCT_OUT2_SET_SET6_Msk (0x01UL << SCT_OUT2_SET_SET6_Pos) /*!< SCT OUT2_SET: SET6 Mask */ #define SCT_OUT2_SET_SET7_Pos 7 /*!< SCT OUT2_SET: SET7 Position */ #define SCT_OUT2_SET_SET7_Msk (0x01UL << SCT_OUT2_SET_SET7_Pos) /*!< SCT OUT2_SET: SET7 Mask */ #define SCT_OUT2_SET_SET8_Pos 8 /*!< SCT OUT2_SET: SET8 Position */ #define SCT_OUT2_SET_SET8_Msk (0x01UL << SCT_OUT2_SET_SET8_Pos) /*!< SCT OUT2_SET: SET8 Mask */ #define SCT_OUT2_SET_SET9_Pos 9 /*!< SCT OUT2_SET: SET9 Position */ #define SCT_OUT2_SET_SET9_Msk (0x01UL << SCT_OUT2_SET_SET9_Pos) /*!< SCT OUT2_SET: SET9 Mask */ #define SCT_OUT2_SET_SET10_Pos 10 /*!< SCT OUT2_SET: SET10 Position */ #define SCT_OUT2_SET_SET10_Msk (0x01UL << SCT_OUT2_SET_SET10_Pos) /*!< SCT OUT2_SET: SET10 Mask */ #define SCT_OUT2_SET_SET11_Pos 11 /*!< SCT OUT2_SET: SET11 Position */ #define SCT_OUT2_SET_SET11_Msk (0x01UL << SCT_OUT2_SET_SET11_Pos) /*!< SCT OUT2_SET: SET11 Mask */ #define SCT_OUT2_SET_SET12_Pos 12 /*!< SCT OUT2_SET: SET12 Position */ #define SCT_OUT2_SET_SET12_Msk (0x01UL << SCT_OUT2_SET_SET12_Pos) /*!< SCT OUT2_SET: SET12 Mask */ #define SCT_OUT2_SET_SET13_Pos 13 /*!< SCT OUT2_SET: SET13 Position */ #define SCT_OUT2_SET_SET13_Msk (0x01UL << SCT_OUT2_SET_SET13_Pos) /*!< SCT OUT2_SET: SET13 Mask */ #define SCT_OUT2_SET_SET14_Pos 14 /*!< SCT OUT2_SET: SET14 Position */ #define SCT_OUT2_SET_SET14_Msk (0x01UL << SCT_OUT2_SET_SET14_Pos) /*!< SCT OUT2_SET: SET14 Mask */ #define SCT_OUT2_SET_SET15_Pos 15 /*!< SCT OUT2_SET: SET15 Position */ #define SCT_OUT2_SET_SET15_Msk (0x01UL << SCT_OUT2_SET_SET15_Pos) /*!< SCT OUT2_SET: SET15 Mask */ /* -------------------------------- SCT_OUT2_CLR -------------------------------- */ #define SCT_OUT2_CLR_CLR0_Pos 0 /*!< SCT OUT2_CLR: CLR0 Position */ #define SCT_OUT2_CLR_CLR0_Msk (0x01UL << SCT_OUT2_CLR_CLR0_Pos) /*!< SCT OUT2_CLR: CLR0 Mask */ #define SCT_OUT2_CLR_CLR1_Pos 1 /*!< SCT OUT2_CLR: CLR1 Position */ #define SCT_OUT2_CLR_CLR1_Msk (0x01UL << SCT_OUT2_CLR_CLR1_Pos) /*!< SCT OUT2_CLR: CLR1 Mask */ #define SCT_OUT2_CLR_CLR2_Pos 2 /*!< SCT OUT2_CLR: CLR2 Position */ #define SCT_OUT2_CLR_CLR2_Msk (0x01UL << SCT_OUT2_CLR_CLR2_Pos) /*!< SCT OUT2_CLR: CLR2 Mask */ #define SCT_OUT2_CLR_CLR3_Pos 3 /*!< SCT OUT2_CLR: CLR3 Position */ #define SCT_OUT2_CLR_CLR3_Msk (0x01UL << SCT_OUT2_CLR_CLR3_Pos) /*!< SCT OUT2_CLR: CLR3 Mask */ #define SCT_OUT2_CLR_CLR4_Pos 4 /*!< SCT OUT2_CLR: CLR4 Position */ #define SCT_OUT2_CLR_CLR4_Msk (0x01UL << SCT_OUT2_CLR_CLR4_Pos) /*!< SCT OUT2_CLR: CLR4 Mask */ #define SCT_OUT2_CLR_CLR5_Pos 5 /*!< SCT OUT2_CLR: CLR5 Position */ #define SCT_OUT2_CLR_CLR5_Msk (0x01UL << SCT_OUT2_CLR_CLR5_Pos) /*!< SCT OUT2_CLR: CLR5 Mask */ #define SCT_OUT2_CLR_CLR6_Pos 6 /*!< SCT OUT2_CLR: CLR6 Position */ #define SCT_OUT2_CLR_CLR6_Msk (0x01UL << SCT_OUT2_CLR_CLR6_Pos) /*!< SCT OUT2_CLR: CLR6 Mask */ #define SCT_OUT2_CLR_CLR7_Pos 7 /*!< SCT OUT2_CLR: CLR7 Position */ #define SCT_OUT2_CLR_CLR7_Msk (0x01UL << SCT_OUT2_CLR_CLR7_Pos) /*!< SCT OUT2_CLR: CLR7 Mask */ #define SCT_OUT2_CLR_CLR8_Pos 8 /*!< SCT OUT2_CLR: CLR8 Position */ #define SCT_OUT2_CLR_CLR8_Msk (0x01UL << SCT_OUT2_CLR_CLR8_Pos) /*!< SCT OUT2_CLR: CLR8 Mask */ #define SCT_OUT2_CLR_CLR9_Pos 9 /*!< SCT OUT2_CLR: CLR9 Position */ #define SCT_OUT2_CLR_CLR9_Msk (0x01UL << SCT_OUT2_CLR_CLR9_Pos) /*!< SCT OUT2_CLR: CLR9 Mask */ #define SCT_OUT2_CLR_CLR10_Pos 10 /*!< SCT OUT2_CLR: CLR10 Position */ #define SCT_OUT2_CLR_CLR10_Msk (0x01UL << SCT_OUT2_CLR_CLR10_Pos) /*!< SCT OUT2_CLR: CLR10 Mask */ #define SCT_OUT2_CLR_CLR11_Pos 11 /*!< SCT OUT2_CLR: CLR11 Position */ #define SCT_OUT2_CLR_CLR11_Msk (0x01UL << SCT_OUT2_CLR_CLR11_Pos) /*!< SCT OUT2_CLR: CLR11 Mask */ #define SCT_OUT2_CLR_CLR12_Pos 12 /*!< SCT OUT2_CLR: CLR12 Position */ #define SCT_OUT2_CLR_CLR12_Msk (0x01UL << SCT_OUT2_CLR_CLR12_Pos) /*!< SCT OUT2_CLR: CLR12 Mask */ #define SCT_OUT2_CLR_CLR13_Pos 13 /*!< SCT OUT2_CLR: CLR13 Position */ #define SCT_OUT2_CLR_CLR13_Msk (0x01UL << SCT_OUT2_CLR_CLR13_Pos) /*!< SCT OUT2_CLR: CLR13 Mask */ #define SCT_OUT2_CLR_CLR14_Pos 14 /*!< SCT OUT2_CLR: CLR14 Position */ #define SCT_OUT2_CLR_CLR14_Msk (0x01UL << SCT_OUT2_CLR_CLR14_Pos) /*!< SCT OUT2_CLR: CLR14 Mask */ #define SCT_OUT2_CLR_CLR15_Pos 15 /*!< SCT OUT2_CLR: CLR15 Position */ #define SCT_OUT2_CLR_CLR15_Msk (0x01UL << SCT_OUT2_CLR_CLR15_Pos) /*!< SCT OUT2_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT3_SET -------------------------------- */ #define SCT_OUT3_SET_SET0_Pos 0 /*!< SCT OUT3_SET: SET0 Position */ #define SCT_OUT3_SET_SET0_Msk (0x01UL << SCT_OUT3_SET_SET0_Pos) /*!< SCT OUT3_SET: SET0 Mask */ #define SCT_OUT3_SET_SET1_Pos 1 /*!< SCT OUT3_SET: SET1 Position */ #define SCT_OUT3_SET_SET1_Msk (0x01UL << SCT_OUT3_SET_SET1_Pos) /*!< SCT OUT3_SET: SET1 Mask */ #define SCT_OUT3_SET_SET2_Pos 2 /*!< SCT OUT3_SET: SET2 Position */ #define SCT_OUT3_SET_SET2_Msk (0x01UL << SCT_OUT3_SET_SET2_Pos) /*!< SCT OUT3_SET: SET2 Mask */ #define SCT_OUT3_SET_SET3_Pos 3 /*!< SCT OUT3_SET: SET3 Position */ #define SCT_OUT3_SET_SET3_Msk (0x01UL << SCT_OUT3_SET_SET3_Pos) /*!< SCT OUT3_SET: SET3 Mask */ #define SCT_OUT3_SET_SET4_Pos 4 /*!< SCT OUT3_SET: SET4 Position */ #define SCT_OUT3_SET_SET4_Msk (0x01UL << SCT_OUT3_SET_SET4_Pos) /*!< SCT OUT3_SET: SET4 Mask */ #define SCT_OUT3_SET_SET5_Pos 5 /*!< SCT OUT3_SET: SET5 Position */ #define SCT_OUT3_SET_SET5_Msk (0x01UL << SCT_OUT3_SET_SET5_Pos) /*!< SCT OUT3_SET: SET5 Mask */ #define SCT_OUT3_SET_SET6_Pos 6 /*!< SCT OUT3_SET: SET6 Position */ #define SCT_OUT3_SET_SET6_Msk (0x01UL << SCT_OUT3_SET_SET6_Pos) /*!< SCT OUT3_SET: SET6 Mask */ #define SCT_OUT3_SET_SET7_Pos 7 /*!< SCT OUT3_SET: SET7 Position */ #define SCT_OUT3_SET_SET7_Msk (0x01UL << SCT_OUT3_SET_SET7_Pos) /*!< SCT OUT3_SET: SET7 Mask */ #define SCT_OUT3_SET_SET8_Pos 8 /*!< SCT OUT3_SET: SET8 Position */ #define SCT_OUT3_SET_SET8_Msk (0x01UL << SCT_OUT3_SET_SET8_Pos) /*!< SCT OUT3_SET: SET8 Mask */ #define SCT_OUT3_SET_SET9_Pos 9 /*!< SCT OUT3_SET: SET9 Position */ #define SCT_OUT3_SET_SET9_Msk (0x01UL << SCT_OUT3_SET_SET9_Pos) /*!< SCT OUT3_SET: SET9 Mask */ #define SCT_OUT3_SET_SET10_Pos 10 /*!< SCT OUT3_SET: SET10 Position */ #define SCT_OUT3_SET_SET10_Msk (0x01UL << SCT_OUT3_SET_SET10_Pos) /*!< SCT OUT3_SET: SET10 Mask */ #define SCT_OUT3_SET_SET11_Pos 11 /*!< SCT OUT3_SET: SET11 Position */ #define SCT_OUT3_SET_SET11_Msk (0x01UL << SCT_OUT3_SET_SET11_Pos) /*!< SCT OUT3_SET: SET11 Mask */ #define SCT_OUT3_SET_SET12_Pos 12 /*!< SCT OUT3_SET: SET12 Position */ #define SCT_OUT3_SET_SET12_Msk (0x01UL << SCT_OUT3_SET_SET12_Pos) /*!< SCT OUT3_SET: SET12 Mask */ #define SCT_OUT3_SET_SET13_Pos 13 /*!< SCT OUT3_SET: SET13 Position */ #define SCT_OUT3_SET_SET13_Msk (0x01UL << SCT_OUT3_SET_SET13_Pos) /*!< SCT OUT3_SET: SET13 Mask */ #define SCT_OUT3_SET_SET14_Pos 14 /*!< SCT OUT3_SET: SET14 Position */ #define SCT_OUT3_SET_SET14_Msk (0x01UL << SCT_OUT3_SET_SET14_Pos) /*!< SCT OUT3_SET: SET14 Mask */ #define SCT_OUT3_SET_SET15_Pos 15 /*!< SCT OUT3_SET: SET15 Position */ #define SCT_OUT3_SET_SET15_Msk (0x01UL << SCT_OUT3_SET_SET15_Pos) /*!< SCT OUT3_SET: SET15 Mask */ /* -------------------------------- SCT_OUT3_CLR -------------------------------- */ #define SCT_OUT3_CLR_CLR0_Pos 0 /*!< SCT OUT3_CLR: CLR0 Position */ #define SCT_OUT3_CLR_CLR0_Msk (0x01UL << SCT_OUT3_CLR_CLR0_Pos) /*!< SCT OUT3_CLR: CLR0 Mask */ #define SCT_OUT3_CLR_CLR1_Pos 1 /*!< SCT OUT3_CLR: CLR1 Position */ #define SCT_OUT3_CLR_CLR1_Msk (0x01UL << SCT_OUT3_CLR_CLR1_Pos) /*!< SCT OUT3_CLR: CLR1 Mask */ #define SCT_OUT3_CLR_CLR2_Pos 2 /*!< SCT OUT3_CLR: CLR2 Position */ #define SCT_OUT3_CLR_CLR2_Msk (0x01UL << SCT_OUT3_CLR_CLR2_Pos) /*!< SCT OUT3_CLR: CLR2 Mask */ #define SCT_OUT3_CLR_CLR3_Pos 3 /*!< SCT OUT3_CLR: CLR3 Position */ #define SCT_OUT3_CLR_CLR3_Msk (0x01UL << SCT_OUT3_CLR_CLR3_Pos) /*!< SCT OUT3_CLR: CLR3 Mask */ #define SCT_OUT3_CLR_CLR4_Pos 4 /*!< SCT OUT3_CLR: CLR4 Position */ #define SCT_OUT3_CLR_CLR4_Msk (0x01UL << SCT_OUT3_CLR_CLR4_Pos) /*!< SCT OUT3_CLR: CLR4 Mask */ #define SCT_OUT3_CLR_CLR5_Pos 5 /*!< SCT OUT3_CLR: CLR5 Position */ #define SCT_OUT3_CLR_CLR5_Msk (0x01UL << SCT_OUT3_CLR_CLR5_Pos) /*!< SCT OUT3_CLR: CLR5 Mask */ #define SCT_OUT3_CLR_CLR6_Pos 6 /*!< SCT OUT3_CLR: CLR6 Position */ #define SCT_OUT3_CLR_CLR6_Msk (0x01UL << SCT_OUT3_CLR_CLR6_Pos) /*!< SCT OUT3_CLR: CLR6 Mask */ #define SCT_OUT3_CLR_CLR7_Pos 7 /*!< SCT OUT3_CLR: CLR7 Position */ #define SCT_OUT3_CLR_CLR7_Msk (0x01UL << SCT_OUT3_CLR_CLR7_Pos) /*!< SCT OUT3_CLR: CLR7 Mask */ #define SCT_OUT3_CLR_CLR8_Pos 8 /*!< SCT OUT3_CLR: CLR8 Position */ #define SCT_OUT3_CLR_CLR8_Msk (0x01UL << SCT_OUT3_CLR_CLR8_Pos) /*!< SCT OUT3_CLR: CLR8 Mask */ #define SCT_OUT3_CLR_CLR9_Pos 9 /*!< SCT OUT3_CLR: CLR9 Position */ #define SCT_OUT3_CLR_CLR9_Msk (0x01UL << SCT_OUT3_CLR_CLR9_Pos) /*!< SCT OUT3_CLR: CLR9 Mask */ #define SCT_OUT3_CLR_CLR10_Pos 10 /*!< SCT OUT3_CLR: CLR10 Position */ #define SCT_OUT3_CLR_CLR10_Msk (0x01UL << SCT_OUT3_CLR_CLR10_Pos) /*!< SCT OUT3_CLR: CLR10 Mask */ #define SCT_OUT3_CLR_CLR11_Pos 11 /*!< SCT OUT3_CLR: CLR11 Position */ #define SCT_OUT3_CLR_CLR11_Msk (0x01UL << SCT_OUT3_CLR_CLR11_Pos) /*!< SCT OUT3_CLR: CLR11 Mask */ #define SCT_OUT3_CLR_CLR12_Pos 12 /*!< SCT OUT3_CLR: CLR12 Position */ #define SCT_OUT3_CLR_CLR12_Msk (0x01UL << SCT_OUT3_CLR_CLR12_Pos) /*!< SCT OUT3_CLR: CLR12 Mask */ #define SCT_OUT3_CLR_CLR13_Pos 13 /*!< SCT OUT3_CLR: CLR13 Position */ #define SCT_OUT3_CLR_CLR13_Msk (0x01UL << SCT_OUT3_CLR_CLR13_Pos) /*!< SCT OUT3_CLR: CLR13 Mask */ #define SCT_OUT3_CLR_CLR14_Pos 14 /*!< SCT OUT3_CLR: CLR14 Position */ #define SCT_OUT3_CLR_CLR14_Msk (0x01UL << SCT_OUT3_CLR_CLR14_Pos) /*!< SCT OUT3_CLR: CLR14 Mask */ #define SCT_OUT3_CLR_CLR15_Pos 15 /*!< SCT OUT3_CLR: CLR15 Position */ #define SCT_OUT3_CLR_CLR15_Msk (0x01UL << SCT_OUT3_CLR_CLR15_Pos) /*!< SCT OUT3_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT4_SET -------------------------------- */ #define SCT_OUT4_SET_SET0_Pos 0 /*!< SCT OUT4_SET: SET0 Position */ #define SCT_OUT4_SET_SET0_Msk (0x01UL << SCT_OUT4_SET_SET0_Pos) /*!< SCT OUT4_SET: SET0 Mask */ #define SCT_OUT4_SET_SET1_Pos 1 /*!< SCT OUT4_SET: SET1 Position */ #define SCT_OUT4_SET_SET1_Msk (0x01UL << SCT_OUT4_SET_SET1_Pos) /*!< SCT OUT4_SET: SET1 Mask */ #define SCT_OUT4_SET_SET2_Pos 2 /*!< SCT OUT4_SET: SET2 Position */ #define SCT_OUT4_SET_SET2_Msk (0x01UL << SCT_OUT4_SET_SET2_Pos) /*!< SCT OUT4_SET: SET2 Mask */ #define SCT_OUT4_SET_SET3_Pos 3 /*!< SCT OUT4_SET: SET3 Position */ #define SCT_OUT4_SET_SET3_Msk (0x01UL << SCT_OUT4_SET_SET3_Pos) /*!< SCT OUT4_SET: SET3 Mask */ #define SCT_OUT4_SET_SET4_Pos 4 /*!< SCT OUT4_SET: SET4 Position */ #define SCT_OUT4_SET_SET4_Msk (0x01UL << SCT_OUT4_SET_SET4_Pos) /*!< SCT OUT4_SET: SET4 Mask */ #define SCT_OUT4_SET_SET5_Pos 5 /*!< SCT OUT4_SET: SET5 Position */ #define SCT_OUT4_SET_SET5_Msk (0x01UL << SCT_OUT4_SET_SET5_Pos) /*!< SCT OUT4_SET: SET5 Mask */ #define SCT_OUT4_SET_SET6_Pos 6 /*!< SCT OUT4_SET: SET6 Position */ #define SCT_OUT4_SET_SET6_Msk (0x01UL << SCT_OUT4_SET_SET6_Pos) /*!< SCT OUT4_SET: SET6 Mask */ #define SCT_OUT4_SET_SET7_Pos 7 /*!< SCT OUT4_SET: SET7 Position */ #define SCT_OUT4_SET_SET7_Msk (0x01UL << SCT_OUT4_SET_SET7_Pos) /*!< SCT OUT4_SET: SET7 Mask */ #define SCT_OUT4_SET_SET8_Pos 8 /*!< SCT OUT4_SET: SET8 Position */ #define SCT_OUT4_SET_SET8_Msk (0x01UL << SCT_OUT4_SET_SET8_Pos) /*!< SCT OUT4_SET: SET8 Mask */ #define SCT_OUT4_SET_SET9_Pos 9 /*!< SCT OUT4_SET: SET9 Position */ #define SCT_OUT4_SET_SET9_Msk (0x01UL << SCT_OUT4_SET_SET9_Pos) /*!< SCT OUT4_SET: SET9 Mask */ #define SCT_OUT4_SET_SET10_Pos 10 /*!< SCT OUT4_SET: SET10 Position */ #define SCT_OUT4_SET_SET10_Msk (0x01UL << SCT_OUT4_SET_SET10_Pos) /*!< SCT OUT4_SET: SET10 Mask */ #define SCT_OUT4_SET_SET11_Pos 11 /*!< SCT OUT4_SET: SET11 Position */ #define SCT_OUT4_SET_SET11_Msk (0x01UL << SCT_OUT4_SET_SET11_Pos) /*!< SCT OUT4_SET: SET11 Mask */ #define SCT_OUT4_SET_SET12_Pos 12 /*!< SCT OUT4_SET: SET12 Position */ #define SCT_OUT4_SET_SET12_Msk (0x01UL << SCT_OUT4_SET_SET12_Pos) /*!< SCT OUT4_SET: SET12 Mask */ #define SCT_OUT4_SET_SET13_Pos 13 /*!< SCT OUT4_SET: SET13 Position */ #define SCT_OUT4_SET_SET13_Msk (0x01UL << SCT_OUT4_SET_SET13_Pos) /*!< SCT OUT4_SET: SET13 Mask */ #define SCT_OUT4_SET_SET14_Pos 14 /*!< SCT OUT4_SET: SET14 Position */ #define SCT_OUT4_SET_SET14_Msk (0x01UL << SCT_OUT4_SET_SET14_Pos) /*!< SCT OUT4_SET: SET14 Mask */ #define SCT_OUT4_SET_SET15_Pos 15 /*!< SCT OUT4_SET: SET15 Position */ #define SCT_OUT4_SET_SET15_Msk (0x01UL << SCT_OUT4_SET_SET15_Pos) /*!< SCT OUT4_SET: SET15 Mask */ /* -------------------------------- SCT_OUT4_CLR -------------------------------- */ #define SCT_OUT4_CLR_CLR0_Pos 0 /*!< SCT OUT4_CLR: CLR0 Position */ #define SCT_OUT4_CLR_CLR0_Msk (0x01UL << SCT_OUT4_CLR_CLR0_Pos) /*!< SCT OUT4_CLR: CLR0 Mask */ #define SCT_OUT4_CLR_CLR1_Pos 1 /*!< SCT OUT4_CLR: CLR1 Position */ #define SCT_OUT4_CLR_CLR1_Msk (0x01UL << SCT_OUT4_CLR_CLR1_Pos) /*!< SCT OUT4_CLR: CLR1 Mask */ #define SCT_OUT4_CLR_CLR2_Pos 2 /*!< SCT OUT4_CLR: CLR2 Position */ #define SCT_OUT4_CLR_CLR2_Msk (0x01UL << SCT_OUT4_CLR_CLR2_Pos) /*!< SCT OUT4_CLR: CLR2 Mask */ #define SCT_OUT4_CLR_CLR3_Pos 3 /*!< SCT OUT4_CLR: CLR3 Position */ #define SCT_OUT4_CLR_CLR3_Msk (0x01UL << SCT_OUT4_CLR_CLR3_Pos) /*!< SCT OUT4_CLR: CLR3 Mask */ #define SCT_OUT4_CLR_CLR4_Pos 4 /*!< SCT OUT4_CLR: CLR4 Position */ #define SCT_OUT4_CLR_CLR4_Msk (0x01UL << SCT_OUT4_CLR_CLR4_Pos) /*!< SCT OUT4_CLR: CLR4 Mask */ #define SCT_OUT4_CLR_CLR5_Pos 5 /*!< SCT OUT4_CLR: CLR5 Position */ #define SCT_OUT4_CLR_CLR5_Msk (0x01UL << SCT_OUT4_CLR_CLR5_Pos) /*!< SCT OUT4_CLR: CLR5 Mask */ #define SCT_OUT4_CLR_CLR6_Pos 6 /*!< SCT OUT4_CLR: CLR6 Position */ #define SCT_OUT4_CLR_CLR6_Msk (0x01UL << SCT_OUT4_CLR_CLR6_Pos) /*!< SCT OUT4_CLR: CLR6 Mask */ #define SCT_OUT4_CLR_CLR7_Pos 7 /*!< SCT OUT4_CLR: CLR7 Position */ #define SCT_OUT4_CLR_CLR7_Msk (0x01UL << SCT_OUT4_CLR_CLR7_Pos) /*!< SCT OUT4_CLR: CLR7 Mask */ #define SCT_OUT4_CLR_CLR8_Pos 8 /*!< SCT OUT4_CLR: CLR8 Position */ #define SCT_OUT4_CLR_CLR8_Msk (0x01UL << SCT_OUT4_CLR_CLR8_Pos) /*!< SCT OUT4_CLR: CLR8 Mask */ #define SCT_OUT4_CLR_CLR9_Pos 9 /*!< SCT OUT4_CLR: CLR9 Position */ #define SCT_OUT4_CLR_CLR9_Msk (0x01UL << SCT_OUT4_CLR_CLR9_Pos) /*!< SCT OUT4_CLR: CLR9 Mask */ #define SCT_OUT4_CLR_CLR10_Pos 10 /*!< SCT OUT4_CLR: CLR10 Position */ #define SCT_OUT4_CLR_CLR10_Msk (0x01UL << SCT_OUT4_CLR_CLR10_Pos) /*!< SCT OUT4_CLR: CLR10 Mask */ #define SCT_OUT4_CLR_CLR11_Pos 11 /*!< SCT OUT4_CLR: CLR11 Position */ #define SCT_OUT4_CLR_CLR11_Msk (0x01UL << SCT_OUT4_CLR_CLR11_Pos) /*!< SCT OUT4_CLR: CLR11 Mask */ #define SCT_OUT4_CLR_CLR12_Pos 12 /*!< SCT OUT4_CLR: CLR12 Position */ #define SCT_OUT4_CLR_CLR12_Msk (0x01UL << SCT_OUT4_CLR_CLR12_Pos) /*!< SCT OUT4_CLR: CLR12 Mask */ #define SCT_OUT4_CLR_CLR13_Pos 13 /*!< SCT OUT4_CLR: CLR13 Position */ #define SCT_OUT4_CLR_CLR13_Msk (0x01UL << SCT_OUT4_CLR_CLR13_Pos) /*!< SCT OUT4_CLR: CLR13 Mask */ #define SCT_OUT4_CLR_CLR14_Pos 14 /*!< SCT OUT4_CLR: CLR14 Position */ #define SCT_OUT4_CLR_CLR14_Msk (0x01UL << SCT_OUT4_CLR_CLR14_Pos) /*!< SCT OUT4_CLR: CLR14 Mask */ #define SCT_OUT4_CLR_CLR15_Pos 15 /*!< SCT OUT4_CLR: CLR15 Position */ #define SCT_OUT4_CLR_CLR15_Msk (0x01UL << SCT_OUT4_CLR_CLR15_Pos) /*!< SCT OUT4_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT5_SET -------------------------------- */ #define SCT_OUT5_SET_SET0_Pos 0 /*!< SCT OUT5_SET: SET0 Position */ #define SCT_OUT5_SET_SET0_Msk (0x01UL << SCT_OUT5_SET_SET0_Pos) /*!< SCT OUT5_SET: SET0 Mask */ #define SCT_OUT5_SET_SET1_Pos 1 /*!< SCT OUT5_SET: SET1 Position */ #define SCT_OUT5_SET_SET1_Msk (0x01UL << SCT_OUT5_SET_SET1_Pos) /*!< SCT OUT5_SET: SET1 Mask */ #define SCT_OUT5_SET_SET2_Pos 2 /*!< SCT OUT5_SET: SET2 Position */ #define SCT_OUT5_SET_SET2_Msk (0x01UL << SCT_OUT5_SET_SET2_Pos) /*!< SCT OUT5_SET: SET2 Mask */ #define SCT_OUT5_SET_SET3_Pos 3 /*!< SCT OUT5_SET: SET3 Position */ #define SCT_OUT5_SET_SET3_Msk (0x01UL << SCT_OUT5_SET_SET3_Pos) /*!< SCT OUT5_SET: SET3 Mask */ #define SCT_OUT5_SET_SET4_Pos 4 /*!< SCT OUT5_SET: SET4 Position */ #define SCT_OUT5_SET_SET4_Msk (0x01UL << SCT_OUT5_SET_SET4_Pos) /*!< SCT OUT5_SET: SET4 Mask */ #define SCT_OUT5_SET_SET5_Pos 5 /*!< SCT OUT5_SET: SET5 Position */ #define SCT_OUT5_SET_SET5_Msk (0x01UL << SCT_OUT5_SET_SET5_Pos) /*!< SCT OUT5_SET: SET5 Mask */ #define SCT_OUT5_SET_SET6_Pos 6 /*!< SCT OUT5_SET: SET6 Position */ #define SCT_OUT5_SET_SET6_Msk (0x01UL << SCT_OUT5_SET_SET6_Pos) /*!< SCT OUT5_SET: SET6 Mask */ #define SCT_OUT5_SET_SET7_Pos 7 /*!< SCT OUT5_SET: SET7 Position */ #define SCT_OUT5_SET_SET7_Msk (0x01UL << SCT_OUT5_SET_SET7_Pos) /*!< SCT OUT5_SET: SET7 Mask */ #define SCT_OUT5_SET_SET8_Pos 8 /*!< SCT OUT5_SET: SET8 Position */ #define SCT_OUT5_SET_SET8_Msk (0x01UL << SCT_OUT5_SET_SET8_Pos) /*!< SCT OUT5_SET: SET8 Mask */ #define SCT_OUT5_SET_SET9_Pos 9 /*!< SCT OUT5_SET: SET9 Position */ #define SCT_OUT5_SET_SET9_Msk (0x01UL << SCT_OUT5_SET_SET9_Pos) /*!< SCT OUT5_SET: SET9 Mask */ #define SCT_OUT5_SET_SET10_Pos 10 /*!< SCT OUT5_SET: SET10 Position */ #define SCT_OUT5_SET_SET10_Msk (0x01UL << SCT_OUT5_SET_SET10_Pos) /*!< SCT OUT5_SET: SET10 Mask */ #define SCT_OUT5_SET_SET11_Pos 11 /*!< SCT OUT5_SET: SET11 Position */ #define SCT_OUT5_SET_SET11_Msk (0x01UL << SCT_OUT5_SET_SET11_Pos) /*!< SCT OUT5_SET: SET11 Mask */ #define SCT_OUT5_SET_SET12_Pos 12 /*!< SCT OUT5_SET: SET12 Position */ #define SCT_OUT5_SET_SET12_Msk (0x01UL << SCT_OUT5_SET_SET12_Pos) /*!< SCT OUT5_SET: SET12 Mask */ #define SCT_OUT5_SET_SET13_Pos 13 /*!< SCT OUT5_SET: SET13 Position */ #define SCT_OUT5_SET_SET13_Msk (0x01UL << SCT_OUT5_SET_SET13_Pos) /*!< SCT OUT5_SET: SET13 Mask */ #define SCT_OUT5_SET_SET14_Pos 14 /*!< SCT OUT5_SET: SET14 Position */ #define SCT_OUT5_SET_SET14_Msk (0x01UL << SCT_OUT5_SET_SET14_Pos) /*!< SCT OUT5_SET: SET14 Mask */ #define SCT_OUT5_SET_SET15_Pos 15 /*!< SCT OUT5_SET: SET15 Position */ #define SCT_OUT5_SET_SET15_Msk (0x01UL << SCT_OUT5_SET_SET15_Pos) /*!< SCT OUT5_SET: SET15 Mask */ /* -------------------------------- SCT_OUT5_CLR -------------------------------- */ #define SCT_OUT5_CLR_CLR0_Pos 0 /*!< SCT OUT5_CLR: CLR0 Position */ #define SCT_OUT5_CLR_CLR0_Msk (0x01UL << SCT_OUT5_CLR_CLR0_Pos) /*!< SCT OUT5_CLR: CLR0 Mask */ #define SCT_OUT5_CLR_CLR1_Pos 1 /*!< SCT OUT5_CLR: CLR1 Position */ #define SCT_OUT5_CLR_CLR1_Msk (0x01UL << SCT_OUT5_CLR_CLR1_Pos) /*!< SCT OUT5_CLR: CLR1 Mask */ #define SCT_OUT5_CLR_CLR2_Pos 2 /*!< SCT OUT5_CLR: CLR2 Position */ #define SCT_OUT5_CLR_CLR2_Msk (0x01UL << SCT_OUT5_CLR_CLR2_Pos) /*!< SCT OUT5_CLR: CLR2 Mask */ #define SCT_OUT5_CLR_CLR3_Pos 3 /*!< SCT OUT5_CLR: CLR3 Position */ #define SCT_OUT5_CLR_CLR3_Msk (0x01UL << SCT_OUT5_CLR_CLR3_Pos) /*!< SCT OUT5_CLR: CLR3 Mask */ #define SCT_OUT5_CLR_CLR4_Pos 4 /*!< SCT OUT5_CLR: CLR4 Position */ #define SCT_OUT5_CLR_CLR4_Msk (0x01UL << SCT_OUT5_CLR_CLR4_Pos) /*!< SCT OUT5_CLR: CLR4 Mask */ #define SCT_OUT5_CLR_CLR5_Pos 5 /*!< SCT OUT5_CLR: CLR5 Position */ #define SCT_OUT5_CLR_CLR5_Msk (0x01UL << SCT_OUT5_CLR_CLR5_Pos) /*!< SCT OUT5_CLR: CLR5 Mask */ #define SCT_OUT5_CLR_CLR6_Pos 6 /*!< SCT OUT5_CLR: CLR6 Position */ #define SCT_OUT5_CLR_CLR6_Msk (0x01UL << SCT_OUT5_CLR_CLR6_Pos) /*!< SCT OUT5_CLR: CLR6 Mask */ #define SCT_OUT5_CLR_CLR7_Pos 7 /*!< SCT OUT5_CLR: CLR7 Position */ #define SCT_OUT5_CLR_CLR7_Msk (0x01UL << SCT_OUT5_CLR_CLR7_Pos) /*!< SCT OUT5_CLR: CLR7 Mask */ #define SCT_OUT5_CLR_CLR8_Pos 8 /*!< SCT OUT5_CLR: CLR8 Position */ #define SCT_OUT5_CLR_CLR8_Msk (0x01UL << SCT_OUT5_CLR_CLR8_Pos) /*!< SCT OUT5_CLR: CLR8 Mask */ #define SCT_OUT5_CLR_CLR9_Pos 9 /*!< SCT OUT5_CLR: CLR9 Position */ #define SCT_OUT5_CLR_CLR9_Msk (0x01UL << SCT_OUT5_CLR_CLR9_Pos) /*!< SCT OUT5_CLR: CLR9 Mask */ #define SCT_OUT5_CLR_CLR10_Pos 10 /*!< SCT OUT5_CLR: CLR10 Position */ #define SCT_OUT5_CLR_CLR10_Msk (0x01UL << SCT_OUT5_CLR_CLR10_Pos) /*!< SCT OUT5_CLR: CLR10 Mask */ #define SCT_OUT5_CLR_CLR11_Pos 11 /*!< SCT OUT5_CLR: CLR11 Position */ #define SCT_OUT5_CLR_CLR11_Msk (0x01UL << SCT_OUT5_CLR_CLR11_Pos) /*!< SCT OUT5_CLR: CLR11 Mask */ #define SCT_OUT5_CLR_CLR12_Pos 12 /*!< SCT OUT5_CLR: CLR12 Position */ #define SCT_OUT5_CLR_CLR12_Msk (0x01UL << SCT_OUT5_CLR_CLR12_Pos) /*!< SCT OUT5_CLR: CLR12 Mask */ #define SCT_OUT5_CLR_CLR13_Pos 13 /*!< SCT OUT5_CLR: CLR13 Position */ #define SCT_OUT5_CLR_CLR13_Msk (0x01UL << SCT_OUT5_CLR_CLR13_Pos) /*!< SCT OUT5_CLR: CLR13 Mask */ #define SCT_OUT5_CLR_CLR14_Pos 14 /*!< SCT OUT5_CLR: CLR14 Position */ #define SCT_OUT5_CLR_CLR14_Msk (0x01UL << SCT_OUT5_CLR_CLR14_Pos) /*!< SCT OUT5_CLR: CLR14 Mask */ #define SCT_OUT5_CLR_CLR15_Pos 15 /*!< SCT OUT5_CLR: CLR15 Position */ #define SCT_OUT5_CLR_CLR15_Msk (0x01UL << SCT_OUT5_CLR_CLR15_Pos) /*!< SCT OUT5_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT6_SET -------------------------------- */ #define SCT_OUT6_SET_SET0_Pos 0 /*!< SCT OUT6_SET: SET0 Position */ #define SCT_OUT6_SET_SET0_Msk (0x01UL << SCT_OUT6_SET_SET0_Pos) /*!< SCT OUT6_SET: SET0 Mask */ #define SCT_OUT6_SET_SET1_Pos 1 /*!< SCT OUT6_SET: SET1 Position */ #define SCT_OUT6_SET_SET1_Msk (0x01UL << SCT_OUT6_SET_SET1_Pos) /*!< SCT OUT6_SET: SET1 Mask */ #define SCT_OUT6_SET_SET2_Pos 2 /*!< SCT OUT6_SET: SET2 Position */ #define SCT_OUT6_SET_SET2_Msk (0x01UL << SCT_OUT6_SET_SET2_Pos) /*!< SCT OUT6_SET: SET2 Mask */ #define SCT_OUT6_SET_SET3_Pos 3 /*!< SCT OUT6_SET: SET3 Position */ #define SCT_OUT6_SET_SET3_Msk (0x01UL << SCT_OUT6_SET_SET3_Pos) /*!< SCT OUT6_SET: SET3 Mask */ #define SCT_OUT6_SET_SET4_Pos 4 /*!< SCT OUT6_SET: SET4 Position */ #define SCT_OUT6_SET_SET4_Msk (0x01UL << SCT_OUT6_SET_SET4_Pos) /*!< SCT OUT6_SET: SET4 Mask */ #define SCT_OUT6_SET_SET5_Pos 5 /*!< SCT OUT6_SET: SET5 Position */ #define SCT_OUT6_SET_SET5_Msk (0x01UL << SCT_OUT6_SET_SET5_Pos) /*!< SCT OUT6_SET: SET5 Mask */ #define SCT_OUT6_SET_SET6_Pos 6 /*!< SCT OUT6_SET: SET6 Position */ #define SCT_OUT6_SET_SET6_Msk (0x01UL << SCT_OUT6_SET_SET6_Pos) /*!< SCT OUT6_SET: SET6 Mask */ #define SCT_OUT6_SET_SET7_Pos 7 /*!< SCT OUT6_SET: SET7 Position */ #define SCT_OUT6_SET_SET7_Msk (0x01UL << SCT_OUT6_SET_SET7_Pos) /*!< SCT OUT6_SET: SET7 Mask */ #define SCT_OUT6_SET_SET8_Pos 8 /*!< SCT OUT6_SET: SET8 Position */ #define SCT_OUT6_SET_SET8_Msk (0x01UL << SCT_OUT6_SET_SET8_Pos) /*!< SCT OUT6_SET: SET8 Mask */ #define SCT_OUT6_SET_SET9_Pos 9 /*!< SCT OUT6_SET: SET9 Position */ #define SCT_OUT6_SET_SET9_Msk (0x01UL << SCT_OUT6_SET_SET9_Pos) /*!< SCT OUT6_SET: SET9 Mask */ #define SCT_OUT6_SET_SET10_Pos 10 /*!< SCT OUT6_SET: SET10 Position */ #define SCT_OUT6_SET_SET10_Msk (0x01UL << SCT_OUT6_SET_SET10_Pos) /*!< SCT OUT6_SET: SET10 Mask */ #define SCT_OUT6_SET_SET11_Pos 11 /*!< SCT OUT6_SET: SET11 Position */ #define SCT_OUT6_SET_SET11_Msk (0x01UL << SCT_OUT6_SET_SET11_Pos) /*!< SCT OUT6_SET: SET11 Mask */ #define SCT_OUT6_SET_SET12_Pos 12 /*!< SCT OUT6_SET: SET12 Position */ #define SCT_OUT6_SET_SET12_Msk (0x01UL << SCT_OUT6_SET_SET12_Pos) /*!< SCT OUT6_SET: SET12 Mask */ #define SCT_OUT6_SET_SET13_Pos 13 /*!< SCT OUT6_SET: SET13 Position */ #define SCT_OUT6_SET_SET13_Msk (0x01UL << SCT_OUT6_SET_SET13_Pos) /*!< SCT OUT6_SET: SET13 Mask */ #define SCT_OUT6_SET_SET14_Pos 14 /*!< SCT OUT6_SET: SET14 Position */ #define SCT_OUT6_SET_SET14_Msk (0x01UL << SCT_OUT6_SET_SET14_Pos) /*!< SCT OUT6_SET: SET14 Mask */ #define SCT_OUT6_SET_SET15_Pos 15 /*!< SCT OUT6_SET: SET15 Position */ #define SCT_OUT6_SET_SET15_Msk (0x01UL << SCT_OUT6_SET_SET15_Pos) /*!< SCT OUT6_SET: SET15 Mask */ /* -------------------------------- SCT_OUT6_CLR -------------------------------- */ #define SCT_OUT6_CLR_CLR0_Pos 0 /*!< SCT OUT6_CLR: CLR0 Position */ #define SCT_OUT6_CLR_CLR0_Msk (0x01UL << SCT_OUT6_CLR_CLR0_Pos) /*!< SCT OUT6_CLR: CLR0 Mask */ #define SCT_OUT6_CLR_CLR1_Pos 1 /*!< SCT OUT6_CLR: CLR1 Position */ #define SCT_OUT6_CLR_CLR1_Msk (0x01UL << SCT_OUT6_CLR_CLR1_Pos) /*!< SCT OUT6_CLR: CLR1 Mask */ #define SCT_OUT6_CLR_CLR2_Pos 2 /*!< SCT OUT6_CLR: CLR2 Position */ #define SCT_OUT6_CLR_CLR2_Msk (0x01UL << SCT_OUT6_CLR_CLR2_Pos) /*!< SCT OUT6_CLR: CLR2 Mask */ #define SCT_OUT6_CLR_CLR3_Pos 3 /*!< SCT OUT6_CLR: CLR3 Position */ #define SCT_OUT6_CLR_CLR3_Msk (0x01UL << SCT_OUT6_CLR_CLR3_Pos) /*!< SCT OUT6_CLR: CLR3 Mask */ #define SCT_OUT6_CLR_CLR4_Pos 4 /*!< SCT OUT6_CLR: CLR4 Position */ #define SCT_OUT6_CLR_CLR4_Msk (0x01UL << SCT_OUT6_CLR_CLR4_Pos) /*!< SCT OUT6_CLR: CLR4 Mask */ #define SCT_OUT6_CLR_CLR5_Pos 5 /*!< SCT OUT6_CLR: CLR5 Position */ #define SCT_OUT6_CLR_CLR5_Msk (0x01UL << SCT_OUT6_CLR_CLR5_Pos) /*!< SCT OUT6_CLR: CLR5 Mask */ #define SCT_OUT6_CLR_CLR6_Pos 6 /*!< SCT OUT6_CLR: CLR6 Position */ #define SCT_OUT6_CLR_CLR6_Msk (0x01UL << SCT_OUT6_CLR_CLR6_Pos) /*!< SCT OUT6_CLR: CLR6 Mask */ #define SCT_OUT6_CLR_CLR7_Pos 7 /*!< SCT OUT6_CLR: CLR7 Position */ #define SCT_OUT6_CLR_CLR7_Msk (0x01UL << SCT_OUT6_CLR_CLR7_Pos) /*!< SCT OUT6_CLR: CLR7 Mask */ #define SCT_OUT6_CLR_CLR8_Pos 8 /*!< SCT OUT6_CLR: CLR8 Position */ #define SCT_OUT6_CLR_CLR8_Msk (0x01UL << SCT_OUT6_CLR_CLR8_Pos) /*!< SCT OUT6_CLR: CLR8 Mask */ #define SCT_OUT6_CLR_CLR9_Pos 9 /*!< SCT OUT6_CLR: CLR9 Position */ #define SCT_OUT6_CLR_CLR9_Msk (0x01UL << SCT_OUT6_CLR_CLR9_Pos) /*!< SCT OUT6_CLR: CLR9 Mask */ #define SCT_OUT6_CLR_CLR10_Pos 10 /*!< SCT OUT6_CLR: CLR10 Position */ #define SCT_OUT6_CLR_CLR10_Msk (0x01UL << SCT_OUT6_CLR_CLR10_Pos) /*!< SCT OUT6_CLR: CLR10 Mask */ #define SCT_OUT6_CLR_CLR11_Pos 11 /*!< SCT OUT6_CLR: CLR11 Position */ #define SCT_OUT6_CLR_CLR11_Msk (0x01UL << SCT_OUT6_CLR_CLR11_Pos) /*!< SCT OUT6_CLR: CLR11 Mask */ #define SCT_OUT6_CLR_CLR12_Pos 12 /*!< SCT OUT6_CLR: CLR12 Position */ #define SCT_OUT6_CLR_CLR12_Msk (0x01UL << SCT_OUT6_CLR_CLR12_Pos) /*!< SCT OUT6_CLR: CLR12 Mask */ #define SCT_OUT6_CLR_CLR13_Pos 13 /*!< SCT OUT6_CLR: CLR13 Position */ #define SCT_OUT6_CLR_CLR13_Msk (0x01UL << SCT_OUT6_CLR_CLR13_Pos) /*!< SCT OUT6_CLR: CLR13 Mask */ #define SCT_OUT6_CLR_CLR14_Pos 14 /*!< SCT OUT6_CLR: CLR14 Position */ #define SCT_OUT6_CLR_CLR14_Msk (0x01UL << SCT_OUT6_CLR_CLR14_Pos) /*!< SCT OUT6_CLR: CLR14 Mask */ #define SCT_OUT6_CLR_CLR15_Pos 15 /*!< SCT OUT6_CLR: CLR15 Position */ #define SCT_OUT6_CLR_CLR15_Msk (0x01UL << SCT_OUT6_CLR_CLR15_Pos) /*!< SCT OUT6_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT7_SET -------------------------------- */ #define SCT_OUT7_SET_SET0_Pos 0 /*!< SCT OUT7_SET: SET0 Position */ #define SCT_OUT7_SET_SET0_Msk (0x01UL << SCT_OUT7_SET_SET0_Pos) /*!< SCT OUT7_SET: SET0 Mask */ #define SCT_OUT7_SET_SET1_Pos 1 /*!< SCT OUT7_SET: SET1 Position */ #define SCT_OUT7_SET_SET1_Msk (0x01UL << SCT_OUT7_SET_SET1_Pos) /*!< SCT OUT7_SET: SET1 Mask */ #define SCT_OUT7_SET_SET2_Pos 2 /*!< SCT OUT7_SET: SET2 Position */ #define SCT_OUT7_SET_SET2_Msk (0x01UL << SCT_OUT7_SET_SET2_Pos) /*!< SCT OUT7_SET: SET2 Mask */ #define SCT_OUT7_SET_SET3_Pos 3 /*!< SCT OUT7_SET: SET3 Position */ #define SCT_OUT7_SET_SET3_Msk (0x01UL << SCT_OUT7_SET_SET3_Pos) /*!< SCT OUT7_SET: SET3 Mask */ #define SCT_OUT7_SET_SET4_Pos 4 /*!< SCT OUT7_SET: SET4 Position */ #define SCT_OUT7_SET_SET4_Msk (0x01UL << SCT_OUT7_SET_SET4_Pos) /*!< SCT OUT7_SET: SET4 Mask */ #define SCT_OUT7_SET_SET5_Pos 5 /*!< SCT OUT7_SET: SET5 Position */ #define SCT_OUT7_SET_SET5_Msk (0x01UL << SCT_OUT7_SET_SET5_Pos) /*!< SCT OUT7_SET: SET5 Mask */ #define SCT_OUT7_SET_SET6_Pos 6 /*!< SCT OUT7_SET: SET6 Position */ #define SCT_OUT7_SET_SET6_Msk (0x01UL << SCT_OUT7_SET_SET6_Pos) /*!< SCT OUT7_SET: SET6 Mask */ #define SCT_OUT7_SET_SET7_Pos 7 /*!< SCT OUT7_SET: SET7 Position */ #define SCT_OUT7_SET_SET7_Msk (0x01UL << SCT_OUT7_SET_SET7_Pos) /*!< SCT OUT7_SET: SET7 Mask */ #define SCT_OUT7_SET_SET8_Pos 8 /*!< SCT OUT7_SET: SET8 Position */ #define SCT_OUT7_SET_SET8_Msk (0x01UL << SCT_OUT7_SET_SET8_Pos) /*!< SCT OUT7_SET: SET8 Mask */ #define SCT_OUT7_SET_SET9_Pos 9 /*!< SCT OUT7_SET: SET9 Position */ #define SCT_OUT7_SET_SET9_Msk (0x01UL << SCT_OUT7_SET_SET9_Pos) /*!< SCT OUT7_SET: SET9 Mask */ #define SCT_OUT7_SET_SET10_Pos 10 /*!< SCT OUT7_SET: SET10 Position */ #define SCT_OUT7_SET_SET10_Msk (0x01UL << SCT_OUT7_SET_SET10_Pos) /*!< SCT OUT7_SET: SET10 Mask */ #define SCT_OUT7_SET_SET11_Pos 11 /*!< SCT OUT7_SET: SET11 Position */ #define SCT_OUT7_SET_SET11_Msk (0x01UL << SCT_OUT7_SET_SET11_Pos) /*!< SCT OUT7_SET: SET11 Mask */ #define SCT_OUT7_SET_SET12_Pos 12 /*!< SCT OUT7_SET: SET12 Position */ #define SCT_OUT7_SET_SET12_Msk (0x01UL << SCT_OUT7_SET_SET12_Pos) /*!< SCT OUT7_SET: SET12 Mask */ #define SCT_OUT7_SET_SET13_Pos 13 /*!< SCT OUT7_SET: SET13 Position */ #define SCT_OUT7_SET_SET13_Msk (0x01UL << SCT_OUT7_SET_SET13_Pos) /*!< SCT OUT7_SET: SET13 Mask */ #define SCT_OUT7_SET_SET14_Pos 14 /*!< SCT OUT7_SET: SET14 Position */ #define SCT_OUT7_SET_SET14_Msk (0x01UL << SCT_OUT7_SET_SET14_Pos) /*!< SCT OUT7_SET: SET14 Mask */ #define SCT_OUT7_SET_SET15_Pos 15 /*!< SCT OUT7_SET: SET15 Position */ #define SCT_OUT7_SET_SET15_Msk (0x01UL << SCT_OUT7_SET_SET15_Pos) /*!< SCT OUT7_SET: SET15 Mask */ /* -------------------------------- SCT_OUT7_CLR -------------------------------- */ #define SCT_OUT7_CLR_CLR0_Pos 0 /*!< SCT OUT7_CLR: CLR0 Position */ #define SCT_OUT7_CLR_CLR0_Msk (0x01UL << SCT_OUT7_CLR_CLR0_Pos) /*!< SCT OUT7_CLR: CLR0 Mask */ #define SCT_OUT7_CLR_CLR1_Pos 1 /*!< SCT OUT7_CLR: CLR1 Position */ #define SCT_OUT7_CLR_CLR1_Msk (0x01UL << SCT_OUT7_CLR_CLR1_Pos) /*!< SCT OUT7_CLR: CLR1 Mask */ #define SCT_OUT7_CLR_CLR2_Pos 2 /*!< SCT OUT7_CLR: CLR2 Position */ #define SCT_OUT7_CLR_CLR2_Msk (0x01UL << SCT_OUT7_CLR_CLR2_Pos) /*!< SCT OUT7_CLR: CLR2 Mask */ #define SCT_OUT7_CLR_CLR3_Pos 3 /*!< SCT OUT7_CLR: CLR3 Position */ #define SCT_OUT7_CLR_CLR3_Msk (0x01UL << SCT_OUT7_CLR_CLR3_Pos) /*!< SCT OUT7_CLR: CLR3 Mask */ #define SCT_OUT7_CLR_CLR4_Pos 4 /*!< SCT OUT7_CLR: CLR4 Position */ #define SCT_OUT7_CLR_CLR4_Msk (0x01UL << SCT_OUT7_CLR_CLR4_Pos) /*!< SCT OUT7_CLR: CLR4 Mask */ #define SCT_OUT7_CLR_CLR5_Pos 5 /*!< SCT OUT7_CLR: CLR5 Position */ #define SCT_OUT7_CLR_CLR5_Msk (0x01UL << SCT_OUT7_CLR_CLR5_Pos) /*!< SCT OUT7_CLR: CLR5 Mask */ #define SCT_OUT7_CLR_CLR6_Pos 6 /*!< SCT OUT7_CLR: CLR6 Position */ #define SCT_OUT7_CLR_CLR6_Msk (0x01UL << SCT_OUT7_CLR_CLR6_Pos) /*!< SCT OUT7_CLR: CLR6 Mask */ #define SCT_OUT7_CLR_CLR7_Pos 7 /*!< SCT OUT7_CLR: CLR7 Position */ #define SCT_OUT7_CLR_CLR7_Msk (0x01UL << SCT_OUT7_CLR_CLR7_Pos) /*!< SCT OUT7_CLR: CLR7 Mask */ #define SCT_OUT7_CLR_CLR8_Pos 8 /*!< SCT OUT7_CLR: CLR8 Position */ #define SCT_OUT7_CLR_CLR8_Msk (0x01UL << SCT_OUT7_CLR_CLR8_Pos) /*!< SCT OUT7_CLR: CLR8 Mask */ #define SCT_OUT7_CLR_CLR9_Pos 9 /*!< SCT OUT7_CLR: CLR9 Position */ #define SCT_OUT7_CLR_CLR9_Msk (0x01UL << SCT_OUT7_CLR_CLR9_Pos) /*!< SCT OUT7_CLR: CLR9 Mask */ #define SCT_OUT7_CLR_CLR10_Pos 10 /*!< SCT OUT7_CLR: CLR10 Position */ #define SCT_OUT7_CLR_CLR10_Msk (0x01UL << SCT_OUT7_CLR_CLR10_Pos) /*!< SCT OUT7_CLR: CLR10 Mask */ #define SCT_OUT7_CLR_CLR11_Pos 11 /*!< SCT OUT7_CLR: CLR11 Position */ #define SCT_OUT7_CLR_CLR11_Msk (0x01UL << SCT_OUT7_CLR_CLR11_Pos) /*!< SCT OUT7_CLR: CLR11 Mask */ #define SCT_OUT7_CLR_CLR12_Pos 12 /*!< SCT OUT7_CLR: CLR12 Position */ #define SCT_OUT7_CLR_CLR12_Msk (0x01UL << SCT_OUT7_CLR_CLR12_Pos) /*!< SCT OUT7_CLR: CLR12 Mask */ #define SCT_OUT7_CLR_CLR13_Pos 13 /*!< SCT OUT7_CLR: CLR13 Position */ #define SCT_OUT7_CLR_CLR13_Msk (0x01UL << SCT_OUT7_CLR_CLR13_Pos) /*!< SCT OUT7_CLR: CLR13 Mask */ #define SCT_OUT7_CLR_CLR14_Pos 14 /*!< SCT OUT7_CLR: CLR14 Position */ #define SCT_OUT7_CLR_CLR14_Msk (0x01UL << SCT_OUT7_CLR_CLR14_Pos) /*!< SCT OUT7_CLR: CLR14 Mask */ #define SCT_OUT7_CLR_CLR15_Pos 15 /*!< SCT OUT7_CLR: CLR15 Position */ #define SCT_OUT7_CLR_CLR15_Msk (0x01UL << SCT_OUT7_CLR_CLR15_Pos) /*!< SCT OUT7_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT8_SET -------------------------------- */ #define SCT_OUT8_SET_SET0_Pos 0 /*!< SCT OUT8_SET: SET0 Position */ #define SCT_OUT8_SET_SET0_Msk (0x01UL << SCT_OUT8_SET_SET0_Pos) /*!< SCT OUT8_SET: SET0 Mask */ #define SCT_OUT8_SET_SET1_Pos 1 /*!< SCT OUT8_SET: SET1 Position */ #define SCT_OUT8_SET_SET1_Msk (0x01UL << SCT_OUT8_SET_SET1_Pos) /*!< SCT OUT8_SET: SET1 Mask */ #define SCT_OUT8_SET_SET2_Pos 2 /*!< SCT OUT8_SET: SET2 Position */ #define SCT_OUT8_SET_SET2_Msk (0x01UL << SCT_OUT8_SET_SET2_Pos) /*!< SCT OUT8_SET: SET2 Mask */ #define SCT_OUT8_SET_SET3_Pos 3 /*!< SCT OUT8_SET: SET3 Position */ #define SCT_OUT8_SET_SET3_Msk (0x01UL << SCT_OUT8_SET_SET3_Pos) /*!< SCT OUT8_SET: SET3 Mask */ #define SCT_OUT8_SET_SET4_Pos 4 /*!< SCT OUT8_SET: SET4 Position */ #define SCT_OUT8_SET_SET4_Msk (0x01UL << SCT_OUT8_SET_SET4_Pos) /*!< SCT OUT8_SET: SET4 Mask */ #define SCT_OUT8_SET_SET5_Pos 5 /*!< SCT OUT8_SET: SET5 Position */ #define SCT_OUT8_SET_SET5_Msk (0x01UL << SCT_OUT8_SET_SET5_Pos) /*!< SCT OUT8_SET: SET5 Mask */ #define SCT_OUT8_SET_SET6_Pos 6 /*!< SCT OUT8_SET: SET6 Position */ #define SCT_OUT8_SET_SET6_Msk (0x01UL << SCT_OUT8_SET_SET6_Pos) /*!< SCT OUT8_SET: SET6 Mask */ #define SCT_OUT8_SET_SET7_Pos 7 /*!< SCT OUT8_SET: SET7 Position */ #define SCT_OUT8_SET_SET7_Msk (0x01UL << SCT_OUT8_SET_SET7_Pos) /*!< SCT OUT8_SET: SET7 Mask */ #define SCT_OUT8_SET_SET8_Pos 8 /*!< SCT OUT8_SET: SET8 Position */ #define SCT_OUT8_SET_SET8_Msk (0x01UL << SCT_OUT8_SET_SET8_Pos) /*!< SCT OUT8_SET: SET8 Mask */ #define SCT_OUT8_SET_SET9_Pos 9 /*!< SCT OUT8_SET: SET9 Position */ #define SCT_OUT8_SET_SET9_Msk (0x01UL << SCT_OUT8_SET_SET9_Pos) /*!< SCT OUT8_SET: SET9 Mask */ #define SCT_OUT8_SET_SET10_Pos 10 /*!< SCT OUT8_SET: SET10 Position */ #define SCT_OUT8_SET_SET10_Msk (0x01UL << SCT_OUT8_SET_SET10_Pos) /*!< SCT OUT8_SET: SET10 Mask */ #define SCT_OUT8_SET_SET11_Pos 11 /*!< SCT OUT8_SET: SET11 Position */ #define SCT_OUT8_SET_SET11_Msk (0x01UL << SCT_OUT8_SET_SET11_Pos) /*!< SCT OUT8_SET: SET11 Mask */ #define SCT_OUT8_SET_SET12_Pos 12 /*!< SCT OUT8_SET: SET12 Position */ #define SCT_OUT8_SET_SET12_Msk (0x01UL << SCT_OUT8_SET_SET12_Pos) /*!< SCT OUT8_SET: SET12 Mask */ #define SCT_OUT8_SET_SET13_Pos 13 /*!< SCT OUT8_SET: SET13 Position */ #define SCT_OUT8_SET_SET13_Msk (0x01UL << SCT_OUT8_SET_SET13_Pos) /*!< SCT OUT8_SET: SET13 Mask */ #define SCT_OUT8_SET_SET14_Pos 14 /*!< SCT OUT8_SET: SET14 Position */ #define SCT_OUT8_SET_SET14_Msk (0x01UL << SCT_OUT8_SET_SET14_Pos) /*!< SCT OUT8_SET: SET14 Mask */ #define SCT_OUT8_SET_SET15_Pos 15 /*!< SCT OUT8_SET: SET15 Position */ #define SCT_OUT8_SET_SET15_Msk (0x01UL << SCT_OUT8_SET_SET15_Pos) /*!< SCT OUT8_SET: SET15 Mask */ /* -------------------------------- SCT_OUT8_CLR -------------------------------- */ #define SCT_OUT8_CLR_CLR0_Pos 0 /*!< SCT OUT8_CLR: CLR0 Position */ #define SCT_OUT8_CLR_CLR0_Msk (0x01UL << SCT_OUT8_CLR_CLR0_Pos) /*!< SCT OUT8_CLR: CLR0 Mask */ #define SCT_OUT8_CLR_CLR1_Pos 1 /*!< SCT OUT8_CLR: CLR1 Position */ #define SCT_OUT8_CLR_CLR1_Msk (0x01UL << SCT_OUT8_CLR_CLR1_Pos) /*!< SCT OUT8_CLR: CLR1 Mask */ #define SCT_OUT8_CLR_CLR2_Pos 2 /*!< SCT OUT8_CLR: CLR2 Position */ #define SCT_OUT8_CLR_CLR2_Msk (0x01UL << SCT_OUT8_CLR_CLR2_Pos) /*!< SCT OUT8_CLR: CLR2 Mask */ #define SCT_OUT8_CLR_CLR3_Pos 3 /*!< SCT OUT8_CLR: CLR3 Position */ #define SCT_OUT8_CLR_CLR3_Msk (0x01UL << SCT_OUT8_CLR_CLR3_Pos) /*!< SCT OUT8_CLR: CLR3 Mask */ #define SCT_OUT8_CLR_CLR4_Pos 4 /*!< SCT OUT8_CLR: CLR4 Position */ #define SCT_OUT8_CLR_CLR4_Msk (0x01UL << SCT_OUT8_CLR_CLR4_Pos) /*!< SCT OUT8_CLR: CLR4 Mask */ #define SCT_OUT8_CLR_CLR5_Pos 5 /*!< SCT OUT8_CLR: CLR5 Position */ #define SCT_OUT8_CLR_CLR5_Msk (0x01UL << SCT_OUT8_CLR_CLR5_Pos) /*!< SCT OUT8_CLR: CLR5 Mask */ #define SCT_OUT8_CLR_CLR6_Pos 6 /*!< SCT OUT8_CLR: CLR6 Position */ #define SCT_OUT8_CLR_CLR6_Msk (0x01UL << SCT_OUT8_CLR_CLR6_Pos) /*!< SCT OUT8_CLR: CLR6 Mask */ #define SCT_OUT8_CLR_CLR7_Pos 7 /*!< SCT OUT8_CLR: CLR7 Position */ #define SCT_OUT8_CLR_CLR7_Msk (0x01UL << SCT_OUT8_CLR_CLR7_Pos) /*!< SCT OUT8_CLR: CLR7 Mask */ #define SCT_OUT8_CLR_CLR8_Pos 8 /*!< SCT OUT8_CLR: CLR8 Position */ #define SCT_OUT8_CLR_CLR8_Msk (0x01UL << SCT_OUT8_CLR_CLR8_Pos) /*!< SCT OUT8_CLR: CLR8 Mask */ #define SCT_OUT8_CLR_CLR9_Pos 9 /*!< SCT OUT8_CLR: CLR9 Position */ #define SCT_OUT8_CLR_CLR9_Msk (0x01UL << SCT_OUT8_CLR_CLR9_Pos) /*!< SCT OUT8_CLR: CLR9 Mask */ #define SCT_OUT8_CLR_CLR10_Pos 10 /*!< SCT OUT8_CLR: CLR10 Position */ #define SCT_OUT8_CLR_CLR10_Msk (0x01UL << SCT_OUT8_CLR_CLR10_Pos) /*!< SCT OUT8_CLR: CLR10 Mask */ #define SCT_OUT8_CLR_CLR11_Pos 11 /*!< SCT OUT8_CLR: CLR11 Position */ #define SCT_OUT8_CLR_CLR11_Msk (0x01UL << SCT_OUT8_CLR_CLR11_Pos) /*!< SCT OUT8_CLR: CLR11 Mask */ #define SCT_OUT8_CLR_CLR12_Pos 12 /*!< SCT OUT8_CLR: CLR12 Position */ #define SCT_OUT8_CLR_CLR12_Msk (0x01UL << SCT_OUT8_CLR_CLR12_Pos) /*!< SCT OUT8_CLR: CLR12 Mask */ #define SCT_OUT8_CLR_CLR13_Pos 13 /*!< SCT OUT8_CLR: CLR13 Position */ #define SCT_OUT8_CLR_CLR13_Msk (0x01UL << SCT_OUT8_CLR_CLR13_Pos) /*!< SCT OUT8_CLR: CLR13 Mask */ #define SCT_OUT8_CLR_CLR14_Pos 14 /*!< SCT OUT8_CLR: CLR14 Position */ #define SCT_OUT8_CLR_CLR14_Msk (0x01UL << SCT_OUT8_CLR_CLR14_Pos) /*!< SCT OUT8_CLR: CLR14 Mask */ #define SCT_OUT8_CLR_CLR15_Pos 15 /*!< SCT OUT8_CLR: CLR15 Position */ #define SCT_OUT8_CLR_CLR15_Msk (0x01UL << SCT_OUT8_CLR_CLR15_Pos) /*!< SCT OUT8_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT9_SET -------------------------------- */ #define SCT_OUT9_SET_SET0_Pos 0 /*!< SCT OUT9_SET: SET0 Position */ #define SCT_OUT9_SET_SET0_Msk (0x01UL << SCT_OUT9_SET_SET0_Pos) /*!< SCT OUT9_SET: SET0 Mask */ #define SCT_OUT9_SET_SET1_Pos 1 /*!< SCT OUT9_SET: SET1 Position */ #define SCT_OUT9_SET_SET1_Msk (0x01UL << SCT_OUT9_SET_SET1_Pos) /*!< SCT OUT9_SET: SET1 Mask */ #define SCT_OUT9_SET_SET2_Pos 2 /*!< SCT OUT9_SET: SET2 Position */ #define SCT_OUT9_SET_SET2_Msk (0x01UL << SCT_OUT9_SET_SET2_Pos) /*!< SCT OUT9_SET: SET2 Mask */ #define SCT_OUT9_SET_SET3_Pos 3 /*!< SCT OUT9_SET: SET3 Position */ #define SCT_OUT9_SET_SET3_Msk (0x01UL << SCT_OUT9_SET_SET3_Pos) /*!< SCT OUT9_SET: SET3 Mask */ #define SCT_OUT9_SET_SET4_Pos 4 /*!< SCT OUT9_SET: SET4 Position */ #define SCT_OUT9_SET_SET4_Msk (0x01UL << SCT_OUT9_SET_SET4_Pos) /*!< SCT OUT9_SET: SET4 Mask */ #define SCT_OUT9_SET_SET5_Pos 5 /*!< SCT OUT9_SET: SET5 Position */ #define SCT_OUT9_SET_SET5_Msk (0x01UL << SCT_OUT9_SET_SET5_Pos) /*!< SCT OUT9_SET: SET5 Mask */ #define SCT_OUT9_SET_SET6_Pos 6 /*!< SCT OUT9_SET: SET6 Position */ #define SCT_OUT9_SET_SET6_Msk (0x01UL << SCT_OUT9_SET_SET6_Pos) /*!< SCT OUT9_SET: SET6 Mask */ #define SCT_OUT9_SET_SET7_Pos 7 /*!< SCT OUT9_SET: SET7 Position */ #define SCT_OUT9_SET_SET7_Msk (0x01UL << SCT_OUT9_SET_SET7_Pos) /*!< SCT OUT9_SET: SET7 Mask */ #define SCT_OUT9_SET_SET8_Pos 8 /*!< SCT OUT9_SET: SET8 Position */ #define SCT_OUT9_SET_SET8_Msk (0x01UL << SCT_OUT9_SET_SET8_Pos) /*!< SCT OUT9_SET: SET8 Mask */ #define SCT_OUT9_SET_SET9_Pos 9 /*!< SCT OUT9_SET: SET9 Position */ #define SCT_OUT9_SET_SET9_Msk (0x01UL << SCT_OUT9_SET_SET9_Pos) /*!< SCT OUT9_SET: SET9 Mask */ #define SCT_OUT9_SET_SET10_Pos 10 /*!< SCT OUT9_SET: SET10 Position */ #define SCT_OUT9_SET_SET10_Msk (0x01UL << SCT_OUT9_SET_SET10_Pos) /*!< SCT OUT9_SET: SET10 Mask */ #define SCT_OUT9_SET_SET11_Pos 11 /*!< SCT OUT9_SET: SET11 Position */ #define SCT_OUT9_SET_SET11_Msk (0x01UL << SCT_OUT9_SET_SET11_Pos) /*!< SCT OUT9_SET: SET11 Mask */ #define SCT_OUT9_SET_SET12_Pos 12 /*!< SCT OUT9_SET: SET12 Position */ #define SCT_OUT9_SET_SET12_Msk (0x01UL << SCT_OUT9_SET_SET12_Pos) /*!< SCT OUT9_SET: SET12 Mask */ #define SCT_OUT9_SET_SET13_Pos 13 /*!< SCT OUT9_SET: SET13 Position */ #define SCT_OUT9_SET_SET13_Msk (0x01UL << SCT_OUT9_SET_SET13_Pos) /*!< SCT OUT9_SET: SET13 Mask */ #define SCT_OUT9_SET_SET14_Pos 14 /*!< SCT OUT9_SET: SET14 Position */ #define SCT_OUT9_SET_SET14_Msk (0x01UL << SCT_OUT9_SET_SET14_Pos) /*!< SCT OUT9_SET: SET14 Mask */ #define SCT_OUT9_SET_SET15_Pos 15 /*!< SCT OUT9_SET: SET15 Position */ #define SCT_OUT9_SET_SET15_Msk (0x01UL << SCT_OUT9_SET_SET15_Pos) /*!< SCT OUT9_SET: SET15 Mask */ /* -------------------------------- SCT_OUT9_CLR -------------------------------- */ #define SCT_OUT9_CLR_CLR0_Pos 0 /*!< SCT OUT9_CLR: CLR0 Position */ #define SCT_OUT9_CLR_CLR0_Msk (0x01UL << SCT_OUT9_CLR_CLR0_Pos) /*!< SCT OUT9_CLR: CLR0 Mask */ #define SCT_OUT9_CLR_CLR1_Pos 1 /*!< SCT OUT9_CLR: CLR1 Position */ #define SCT_OUT9_CLR_CLR1_Msk (0x01UL << SCT_OUT9_CLR_CLR1_Pos) /*!< SCT OUT9_CLR: CLR1 Mask */ #define SCT_OUT9_CLR_CLR2_Pos 2 /*!< SCT OUT9_CLR: CLR2 Position */ #define SCT_OUT9_CLR_CLR2_Msk (0x01UL << SCT_OUT9_CLR_CLR2_Pos) /*!< SCT OUT9_CLR: CLR2 Mask */ #define SCT_OUT9_CLR_CLR3_Pos 3 /*!< SCT OUT9_CLR: CLR3 Position */ #define SCT_OUT9_CLR_CLR3_Msk (0x01UL << SCT_OUT9_CLR_CLR3_Pos) /*!< SCT OUT9_CLR: CLR3 Mask */ #define SCT_OUT9_CLR_CLR4_Pos 4 /*!< SCT OUT9_CLR: CLR4 Position */ #define SCT_OUT9_CLR_CLR4_Msk (0x01UL << SCT_OUT9_CLR_CLR4_Pos) /*!< SCT OUT9_CLR: CLR4 Mask */ #define SCT_OUT9_CLR_CLR5_Pos 5 /*!< SCT OUT9_CLR: CLR5 Position */ #define SCT_OUT9_CLR_CLR5_Msk (0x01UL << SCT_OUT9_CLR_CLR5_Pos) /*!< SCT OUT9_CLR: CLR5 Mask */ #define SCT_OUT9_CLR_CLR6_Pos 6 /*!< SCT OUT9_CLR: CLR6 Position */ #define SCT_OUT9_CLR_CLR6_Msk (0x01UL << SCT_OUT9_CLR_CLR6_Pos) /*!< SCT OUT9_CLR: CLR6 Mask */ #define SCT_OUT9_CLR_CLR7_Pos 7 /*!< SCT OUT9_CLR: CLR7 Position */ #define SCT_OUT9_CLR_CLR7_Msk (0x01UL << SCT_OUT9_CLR_CLR7_Pos) /*!< SCT OUT9_CLR: CLR7 Mask */ #define SCT_OUT9_CLR_CLR8_Pos 8 /*!< SCT OUT9_CLR: CLR8 Position */ #define SCT_OUT9_CLR_CLR8_Msk (0x01UL << SCT_OUT9_CLR_CLR8_Pos) /*!< SCT OUT9_CLR: CLR8 Mask */ #define SCT_OUT9_CLR_CLR9_Pos 9 /*!< SCT OUT9_CLR: CLR9 Position */ #define SCT_OUT9_CLR_CLR9_Msk (0x01UL << SCT_OUT9_CLR_CLR9_Pos) /*!< SCT OUT9_CLR: CLR9 Mask */ #define SCT_OUT9_CLR_CLR10_Pos 10 /*!< SCT OUT9_CLR: CLR10 Position */ #define SCT_OUT9_CLR_CLR10_Msk (0x01UL << SCT_OUT9_CLR_CLR10_Pos) /*!< SCT OUT9_CLR: CLR10 Mask */ #define SCT_OUT9_CLR_CLR11_Pos 11 /*!< SCT OUT9_CLR: CLR11 Position */ #define SCT_OUT9_CLR_CLR11_Msk (0x01UL << SCT_OUT9_CLR_CLR11_Pos) /*!< SCT OUT9_CLR: CLR11 Mask */ #define SCT_OUT9_CLR_CLR12_Pos 12 /*!< SCT OUT9_CLR: CLR12 Position */ #define SCT_OUT9_CLR_CLR12_Msk (0x01UL << SCT_OUT9_CLR_CLR12_Pos) /*!< SCT OUT9_CLR: CLR12 Mask */ #define SCT_OUT9_CLR_CLR13_Pos 13 /*!< SCT OUT9_CLR: CLR13 Position */ #define SCT_OUT9_CLR_CLR13_Msk (0x01UL << SCT_OUT9_CLR_CLR13_Pos) /*!< SCT OUT9_CLR: CLR13 Mask */ #define SCT_OUT9_CLR_CLR14_Pos 14 /*!< SCT OUT9_CLR: CLR14 Position */ #define SCT_OUT9_CLR_CLR14_Msk (0x01UL << SCT_OUT9_CLR_CLR14_Pos) /*!< SCT OUT9_CLR: CLR14 Mask */ #define SCT_OUT9_CLR_CLR15_Pos 15 /*!< SCT OUT9_CLR: CLR15 Position */ #define SCT_OUT9_CLR_CLR15_Msk (0x01UL << SCT_OUT9_CLR_CLR15_Pos) /*!< SCT OUT9_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT10_SET ------------------------------- */ #define SCT_OUT10_SET_SET0_Pos 0 /*!< SCT OUT10_SET: SET0 Position */ #define SCT_OUT10_SET_SET0_Msk (0x01UL << SCT_OUT10_SET_SET0_Pos) /*!< SCT OUT10_SET: SET0 Mask */ #define SCT_OUT10_SET_SET1_Pos 1 /*!< SCT OUT10_SET: SET1 Position */ #define SCT_OUT10_SET_SET1_Msk (0x01UL << SCT_OUT10_SET_SET1_Pos) /*!< SCT OUT10_SET: SET1 Mask */ #define SCT_OUT10_SET_SET2_Pos 2 /*!< SCT OUT10_SET: SET2 Position */ #define SCT_OUT10_SET_SET2_Msk (0x01UL << SCT_OUT10_SET_SET2_Pos) /*!< SCT OUT10_SET: SET2 Mask */ #define SCT_OUT10_SET_SET3_Pos 3 /*!< SCT OUT10_SET: SET3 Position */ #define SCT_OUT10_SET_SET3_Msk (0x01UL << SCT_OUT10_SET_SET3_Pos) /*!< SCT OUT10_SET: SET3 Mask */ #define SCT_OUT10_SET_SET4_Pos 4 /*!< SCT OUT10_SET: SET4 Position */ #define SCT_OUT10_SET_SET4_Msk (0x01UL << SCT_OUT10_SET_SET4_Pos) /*!< SCT OUT10_SET: SET4 Mask */ #define SCT_OUT10_SET_SET5_Pos 5 /*!< SCT OUT10_SET: SET5 Position */ #define SCT_OUT10_SET_SET5_Msk (0x01UL << SCT_OUT10_SET_SET5_Pos) /*!< SCT OUT10_SET: SET5 Mask */ #define SCT_OUT10_SET_SET6_Pos 6 /*!< SCT OUT10_SET: SET6 Position */ #define SCT_OUT10_SET_SET6_Msk (0x01UL << SCT_OUT10_SET_SET6_Pos) /*!< SCT OUT10_SET: SET6 Mask */ #define SCT_OUT10_SET_SET7_Pos 7 /*!< SCT OUT10_SET: SET7 Position */ #define SCT_OUT10_SET_SET7_Msk (0x01UL << SCT_OUT10_SET_SET7_Pos) /*!< SCT OUT10_SET: SET7 Mask */ #define SCT_OUT10_SET_SET8_Pos 8 /*!< SCT OUT10_SET: SET8 Position */ #define SCT_OUT10_SET_SET8_Msk (0x01UL << SCT_OUT10_SET_SET8_Pos) /*!< SCT OUT10_SET: SET8 Mask */ #define SCT_OUT10_SET_SET9_Pos 9 /*!< SCT OUT10_SET: SET9 Position */ #define SCT_OUT10_SET_SET9_Msk (0x01UL << SCT_OUT10_SET_SET9_Pos) /*!< SCT OUT10_SET: SET9 Mask */ #define SCT_OUT10_SET_SET10_Pos 10 /*!< SCT OUT10_SET: SET10 Position */ #define SCT_OUT10_SET_SET10_Msk (0x01UL << SCT_OUT10_SET_SET10_Pos) /*!< SCT OUT10_SET: SET10 Mask */ #define SCT_OUT10_SET_SET11_Pos 11 /*!< SCT OUT10_SET: SET11 Position */ #define SCT_OUT10_SET_SET11_Msk (0x01UL << SCT_OUT10_SET_SET11_Pos) /*!< SCT OUT10_SET: SET11 Mask */ #define SCT_OUT10_SET_SET12_Pos 12 /*!< SCT OUT10_SET: SET12 Position */ #define SCT_OUT10_SET_SET12_Msk (0x01UL << SCT_OUT10_SET_SET12_Pos) /*!< SCT OUT10_SET: SET12 Mask */ #define SCT_OUT10_SET_SET13_Pos 13 /*!< SCT OUT10_SET: SET13 Position */ #define SCT_OUT10_SET_SET13_Msk (0x01UL << SCT_OUT10_SET_SET13_Pos) /*!< SCT OUT10_SET: SET13 Mask */ #define SCT_OUT10_SET_SET14_Pos 14 /*!< SCT OUT10_SET: SET14 Position */ #define SCT_OUT10_SET_SET14_Msk (0x01UL << SCT_OUT10_SET_SET14_Pos) /*!< SCT OUT10_SET: SET14 Mask */ #define SCT_OUT10_SET_SET15_Pos 15 /*!< SCT OUT10_SET: SET15 Position */ #define SCT_OUT10_SET_SET15_Msk (0x01UL << SCT_OUT10_SET_SET15_Pos) /*!< SCT OUT10_SET: SET15 Mask */ /* -------------------------------- SCT_OUT10_CLR ------------------------------- */ #define SCT_OUT10_CLR_CLR0_Pos 0 /*!< SCT OUT10_CLR: CLR0 Position */ #define SCT_OUT10_CLR_CLR0_Msk (0x01UL << SCT_OUT10_CLR_CLR0_Pos) /*!< SCT OUT10_CLR: CLR0 Mask */ #define SCT_OUT10_CLR_CLR1_Pos 1 /*!< SCT OUT10_CLR: CLR1 Position */ #define SCT_OUT10_CLR_CLR1_Msk (0x01UL << SCT_OUT10_CLR_CLR1_Pos) /*!< SCT OUT10_CLR: CLR1 Mask */ #define SCT_OUT10_CLR_CLR2_Pos 2 /*!< SCT OUT10_CLR: CLR2 Position */ #define SCT_OUT10_CLR_CLR2_Msk (0x01UL << SCT_OUT10_CLR_CLR2_Pos) /*!< SCT OUT10_CLR: CLR2 Mask */ #define SCT_OUT10_CLR_CLR3_Pos 3 /*!< SCT OUT10_CLR: CLR3 Position */ #define SCT_OUT10_CLR_CLR3_Msk (0x01UL << SCT_OUT10_CLR_CLR3_Pos) /*!< SCT OUT10_CLR: CLR3 Mask */ #define SCT_OUT10_CLR_CLR4_Pos 4 /*!< SCT OUT10_CLR: CLR4 Position */ #define SCT_OUT10_CLR_CLR4_Msk (0x01UL << SCT_OUT10_CLR_CLR4_Pos) /*!< SCT OUT10_CLR: CLR4 Mask */ #define SCT_OUT10_CLR_CLR5_Pos 5 /*!< SCT OUT10_CLR: CLR5 Position */ #define SCT_OUT10_CLR_CLR5_Msk (0x01UL << SCT_OUT10_CLR_CLR5_Pos) /*!< SCT OUT10_CLR: CLR5 Mask */ #define SCT_OUT10_CLR_CLR6_Pos 6 /*!< SCT OUT10_CLR: CLR6 Position */ #define SCT_OUT10_CLR_CLR6_Msk (0x01UL << SCT_OUT10_CLR_CLR6_Pos) /*!< SCT OUT10_CLR: CLR6 Mask */ #define SCT_OUT10_CLR_CLR7_Pos 7 /*!< SCT OUT10_CLR: CLR7 Position */ #define SCT_OUT10_CLR_CLR7_Msk (0x01UL << SCT_OUT10_CLR_CLR7_Pos) /*!< SCT OUT10_CLR: CLR7 Mask */ #define SCT_OUT10_CLR_CLR8_Pos 8 /*!< SCT OUT10_CLR: CLR8 Position */ #define SCT_OUT10_CLR_CLR8_Msk (0x01UL << SCT_OUT10_CLR_CLR8_Pos) /*!< SCT OUT10_CLR: CLR8 Mask */ #define SCT_OUT10_CLR_CLR9_Pos 9 /*!< SCT OUT10_CLR: CLR9 Position */ #define SCT_OUT10_CLR_CLR9_Msk (0x01UL << SCT_OUT10_CLR_CLR9_Pos) /*!< SCT OUT10_CLR: CLR9 Mask */ #define SCT_OUT10_CLR_CLR10_Pos 10 /*!< SCT OUT10_CLR: CLR10 Position */ #define SCT_OUT10_CLR_CLR10_Msk (0x01UL << SCT_OUT10_CLR_CLR10_Pos) /*!< SCT OUT10_CLR: CLR10 Mask */ #define SCT_OUT10_CLR_CLR11_Pos 11 /*!< SCT OUT10_CLR: CLR11 Position */ #define SCT_OUT10_CLR_CLR11_Msk (0x01UL << SCT_OUT10_CLR_CLR11_Pos) /*!< SCT OUT10_CLR: CLR11 Mask */ #define SCT_OUT10_CLR_CLR12_Pos 12 /*!< SCT OUT10_CLR: CLR12 Position */ #define SCT_OUT10_CLR_CLR12_Msk (0x01UL << SCT_OUT10_CLR_CLR12_Pos) /*!< SCT OUT10_CLR: CLR12 Mask */ #define SCT_OUT10_CLR_CLR13_Pos 13 /*!< SCT OUT10_CLR: CLR13 Position */ #define SCT_OUT10_CLR_CLR13_Msk (0x01UL << SCT_OUT10_CLR_CLR13_Pos) /*!< SCT OUT10_CLR: CLR13 Mask */ #define SCT_OUT10_CLR_CLR14_Pos 14 /*!< SCT OUT10_CLR: CLR14 Position */ #define SCT_OUT10_CLR_CLR14_Msk (0x01UL << SCT_OUT10_CLR_CLR14_Pos) /*!< SCT OUT10_CLR: CLR14 Mask */ #define SCT_OUT10_CLR_CLR15_Pos 15 /*!< SCT OUT10_CLR: CLR15 Position */ #define SCT_OUT10_CLR_CLR15_Msk (0x01UL << SCT_OUT10_CLR_CLR15_Pos) /*!< SCT OUT10_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT11_SET ------------------------------- */ #define SCT_OUT11_SET_SET0_Pos 0 /*!< SCT OUT11_SET: SET0 Position */ #define SCT_OUT11_SET_SET0_Msk (0x01UL << SCT_OUT11_SET_SET0_Pos) /*!< SCT OUT11_SET: SET0 Mask */ #define SCT_OUT11_SET_SET1_Pos 1 /*!< SCT OUT11_SET: SET1 Position */ #define SCT_OUT11_SET_SET1_Msk (0x01UL << SCT_OUT11_SET_SET1_Pos) /*!< SCT OUT11_SET: SET1 Mask */ #define SCT_OUT11_SET_SET2_Pos 2 /*!< SCT OUT11_SET: SET2 Position */ #define SCT_OUT11_SET_SET2_Msk (0x01UL << SCT_OUT11_SET_SET2_Pos) /*!< SCT OUT11_SET: SET2 Mask */ #define SCT_OUT11_SET_SET3_Pos 3 /*!< SCT OUT11_SET: SET3 Position */ #define SCT_OUT11_SET_SET3_Msk (0x01UL << SCT_OUT11_SET_SET3_Pos) /*!< SCT OUT11_SET: SET3 Mask */ #define SCT_OUT11_SET_SET4_Pos 4 /*!< SCT OUT11_SET: SET4 Position */ #define SCT_OUT11_SET_SET4_Msk (0x01UL << SCT_OUT11_SET_SET4_Pos) /*!< SCT OUT11_SET: SET4 Mask */ #define SCT_OUT11_SET_SET5_Pos 5 /*!< SCT OUT11_SET: SET5 Position */ #define SCT_OUT11_SET_SET5_Msk (0x01UL << SCT_OUT11_SET_SET5_Pos) /*!< SCT OUT11_SET: SET5 Mask */ #define SCT_OUT11_SET_SET6_Pos 6 /*!< SCT OUT11_SET: SET6 Position */ #define SCT_OUT11_SET_SET6_Msk (0x01UL << SCT_OUT11_SET_SET6_Pos) /*!< SCT OUT11_SET: SET6 Mask */ #define SCT_OUT11_SET_SET7_Pos 7 /*!< SCT OUT11_SET: SET7 Position */ #define SCT_OUT11_SET_SET7_Msk (0x01UL << SCT_OUT11_SET_SET7_Pos) /*!< SCT OUT11_SET: SET7 Mask */ #define SCT_OUT11_SET_SET8_Pos 8 /*!< SCT OUT11_SET: SET8 Position */ #define SCT_OUT11_SET_SET8_Msk (0x01UL << SCT_OUT11_SET_SET8_Pos) /*!< SCT OUT11_SET: SET8 Mask */ #define SCT_OUT11_SET_SET9_Pos 9 /*!< SCT OUT11_SET: SET9 Position */ #define SCT_OUT11_SET_SET9_Msk (0x01UL << SCT_OUT11_SET_SET9_Pos) /*!< SCT OUT11_SET: SET9 Mask */ #define SCT_OUT11_SET_SET10_Pos 10 /*!< SCT OUT11_SET: SET10 Position */ #define SCT_OUT11_SET_SET10_Msk (0x01UL << SCT_OUT11_SET_SET10_Pos) /*!< SCT OUT11_SET: SET10 Mask */ #define SCT_OUT11_SET_SET11_Pos 11 /*!< SCT OUT11_SET: SET11 Position */ #define SCT_OUT11_SET_SET11_Msk (0x01UL << SCT_OUT11_SET_SET11_Pos) /*!< SCT OUT11_SET: SET11 Mask */ #define SCT_OUT11_SET_SET12_Pos 12 /*!< SCT OUT11_SET: SET12 Position */ #define SCT_OUT11_SET_SET12_Msk (0x01UL << SCT_OUT11_SET_SET12_Pos) /*!< SCT OUT11_SET: SET12 Mask */ #define SCT_OUT11_SET_SET13_Pos 13 /*!< SCT OUT11_SET: SET13 Position */ #define SCT_OUT11_SET_SET13_Msk (0x01UL << SCT_OUT11_SET_SET13_Pos) /*!< SCT OUT11_SET: SET13 Mask */ #define SCT_OUT11_SET_SET14_Pos 14 /*!< SCT OUT11_SET: SET14 Position */ #define SCT_OUT11_SET_SET14_Msk (0x01UL << SCT_OUT11_SET_SET14_Pos) /*!< SCT OUT11_SET: SET14 Mask */ #define SCT_OUT11_SET_SET15_Pos 15 /*!< SCT OUT11_SET: SET15 Position */ #define SCT_OUT11_SET_SET15_Msk (0x01UL << SCT_OUT11_SET_SET15_Pos) /*!< SCT OUT11_SET: SET15 Mask */ /* -------------------------------- SCT_OUT11_CLR ------------------------------- */ #define SCT_OUT11_CLR_CLR0_Pos 0 /*!< SCT OUT11_CLR: CLR0 Position */ #define SCT_OUT11_CLR_CLR0_Msk (0x01UL << SCT_OUT11_CLR_CLR0_Pos) /*!< SCT OUT11_CLR: CLR0 Mask */ #define SCT_OUT11_CLR_CLR1_Pos 1 /*!< SCT OUT11_CLR: CLR1 Position */ #define SCT_OUT11_CLR_CLR1_Msk (0x01UL << SCT_OUT11_CLR_CLR1_Pos) /*!< SCT OUT11_CLR: CLR1 Mask */ #define SCT_OUT11_CLR_CLR2_Pos 2 /*!< SCT OUT11_CLR: CLR2 Position */ #define SCT_OUT11_CLR_CLR2_Msk (0x01UL << SCT_OUT11_CLR_CLR2_Pos) /*!< SCT OUT11_CLR: CLR2 Mask */ #define SCT_OUT11_CLR_CLR3_Pos 3 /*!< SCT OUT11_CLR: CLR3 Position */ #define SCT_OUT11_CLR_CLR3_Msk (0x01UL << SCT_OUT11_CLR_CLR3_Pos) /*!< SCT OUT11_CLR: CLR3 Mask */ #define SCT_OUT11_CLR_CLR4_Pos 4 /*!< SCT OUT11_CLR: CLR4 Position */ #define SCT_OUT11_CLR_CLR4_Msk (0x01UL << SCT_OUT11_CLR_CLR4_Pos) /*!< SCT OUT11_CLR: CLR4 Mask */ #define SCT_OUT11_CLR_CLR5_Pos 5 /*!< SCT OUT11_CLR: CLR5 Position */ #define SCT_OUT11_CLR_CLR5_Msk (0x01UL << SCT_OUT11_CLR_CLR5_Pos) /*!< SCT OUT11_CLR: CLR5 Mask */ #define SCT_OUT11_CLR_CLR6_Pos 6 /*!< SCT OUT11_CLR: CLR6 Position */ #define SCT_OUT11_CLR_CLR6_Msk (0x01UL << SCT_OUT11_CLR_CLR6_Pos) /*!< SCT OUT11_CLR: CLR6 Mask */ #define SCT_OUT11_CLR_CLR7_Pos 7 /*!< SCT OUT11_CLR: CLR7 Position */ #define SCT_OUT11_CLR_CLR7_Msk (0x01UL << SCT_OUT11_CLR_CLR7_Pos) /*!< SCT OUT11_CLR: CLR7 Mask */ #define SCT_OUT11_CLR_CLR8_Pos 8 /*!< SCT OUT11_CLR: CLR8 Position */ #define SCT_OUT11_CLR_CLR8_Msk (0x01UL << SCT_OUT11_CLR_CLR8_Pos) /*!< SCT OUT11_CLR: CLR8 Mask */ #define SCT_OUT11_CLR_CLR9_Pos 9 /*!< SCT OUT11_CLR: CLR9 Position */ #define SCT_OUT11_CLR_CLR9_Msk (0x01UL << SCT_OUT11_CLR_CLR9_Pos) /*!< SCT OUT11_CLR: CLR9 Mask */ #define SCT_OUT11_CLR_CLR10_Pos 10 /*!< SCT OUT11_CLR: CLR10 Position */ #define SCT_OUT11_CLR_CLR10_Msk (0x01UL << SCT_OUT11_CLR_CLR10_Pos) /*!< SCT OUT11_CLR: CLR10 Mask */ #define SCT_OUT11_CLR_CLR11_Pos 11 /*!< SCT OUT11_CLR: CLR11 Position */ #define SCT_OUT11_CLR_CLR11_Msk (0x01UL << SCT_OUT11_CLR_CLR11_Pos) /*!< SCT OUT11_CLR: CLR11 Mask */ #define SCT_OUT11_CLR_CLR12_Pos 12 /*!< SCT OUT11_CLR: CLR12 Position */ #define SCT_OUT11_CLR_CLR12_Msk (0x01UL << SCT_OUT11_CLR_CLR12_Pos) /*!< SCT OUT11_CLR: CLR12 Mask */ #define SCT_OUT11_CLR_CLR13_Pos 13 /*!< SCT OUT11_CLR: CLR13 Position */ #define SCT_OUT11_CLR_CLR13_Msk (0x01UL << SCT_OUT11_CLR_CLR13_Pos) /*!< SCT OUT11_CLR: CLR13 Mask */ #define SCT_OUT11_CLR_CLR14_Pos 14 /*!< SCT OUT11_CLR: CLR14 Position */ #define SCT_OUT11_CLR_CLR14_Msk (0x01UL << SCT_OUT11_CLR_CLR14_Pos) /*!< SCT OUT11_CLR: CLR14 Mask */ #define SCT_OUT11_CLR_CLR15_Pos 15 /*!< SCT OUT11_CLR: CLR15 Position */ #define SCT_OUT11_CLR_CLR15_Msk (0x01UL << SCT_OUT11_CLR_CLR15_Pos) /*!< SCT OUT11_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT12_SET ------------------------------- */ #define SCT_OUT12_SET_SET0_Pos 0 /*!< SCT OUT12_SET: SET0 Position */ #define SCT_OUT12_SET_SET0_Msk (0x01UL << SCT_OUT12_SET_SET0_Pos) /*!< SCT OUT12_SET: SET0 Mask */ #define SCT_OUT12_SET_SET1_Pos 1 /*!< SCT OUT12_SET: SET1 Position */ #define SCT_OUT12_SET_SET1_Msk (0x01UL << SCT_OUT12_SET_SET1_Pos) /*!< SCT OUT12_SET: SET1 Mask */ #define SCT_OUT12_SET_SET2_Pos 2 /*!< SCT OUT12_SET: SET2 Position */ #define SCT_OUT12_SET_SET2_Msk (0x01UL << SCT_OUT12_SET_SET2_Pos) /*!< SCT OUT12_SET: SET2 Mask */ #define SCT_OUT12_SET_SET3_Pos 3 /*!< SCT OUT12_SET: SET3 Position */ #define SCT_OUT12_SET_SET3_Msk (0x01UL << SCT_OUT12_SET_SET3_Pos) /*!< SCT OUT12_SET: SET3 Mask */ #define SCT_OUT12_SET_SET4_Pos 4 /*!< SCT OUT12_SET: SET4 Position */ #define SCT_OUT12_SET_SET4_Msk (0x01UL << SCT_OUT12_SET_SET4_Pos) /*!< SCT OUT12_SET: SET4 Mask */ #define SCT_OUT12_SET_SET5_Pos 5 /*!< SCT OUT12_SET: SET5 Position */ #define SCT_OUT12_SET_SET5_Msk (0x01UL << SCT_OUT12_SET_SET5_Pos) /*!< SCT OUT12_SET: SET5 Mask */ #define SCT_OUT12_SET_SET6_Pos 6 /*!< SCT OUT12_SET: SET6 Position */ #define SCT_OUT12_SET_SET6_Msk (0x01UL << SCT_OUT12_SET_SET6_Pos) /*!< SCT OUT12_SET: SET6 Mask */ #define SCT_OUT12_SET_SET7_Pos 7 /*!< SCT OUT12_SET: SET7 Position */ #define SCT_OUT12_SET_SET7_Msk (0x01UL << SCT_OUT12_SET_SET7_Pos) /*!< SCT OUT12_SET: SET7 Mask */ #define SCT_OUT12_SET_SET8_Pos 8 /*!< SCT OUT12_SET: SET8 Position */ #define SCT_OUT12_SET_SET8_Msk (0x01UL << SCT_OUT12_SET_SET8_Pos) /*!< SCT OUT12_SET: SET8 Mask */ #define SCT_OUT12_SET_SET9_Pos 9 /*!< SCT OUT12_SET: SET9 Position */ #define SCT_OUT12_SET_SET9_Msk (0x01UL << SCT_OUT12_SET_SET9_Pos) /*!< SCT OUT12_SET: SET9 Mask */ #define SCT_OUT12_SET_SET10_Pos 10 /*!< SCT OUT12_SET: SET10 Position */ #define SCT_OUT12_SET_SET10_Msk (0x01UL << SCT_OUT12_SET_SET10_Pos) /*!< SCT OUT12_SET: SET10 Mask */ #define SCT_OUT12_SET_SET11_Pos 11 /*!< SCT OUT12_SET: SET11 Position */ #define SCT_OUT12_SET_SET11_Msk (0x01UL << SCT_OUT12_SET_SET11_Pos) /*!< SCT OUT12_SET: SET11 Mask */ #define SCT_OUT12_SET_SET12_Pos 12 /*!< SCT OUT12_SET: SET12 Position */ #define SCT_OUT12_SET_SET12_Msk (0x01UL << SCT_OUT12_SET_SET12_Pos) /*!< SCT OUT12_SET: SET12 Mask */ #define SCT_OUT12_SET_SET13_Pos 13 /*!< SCT OUT12_SET: SET13 Position */ #define SCT_OUT12_SET_SET13_Msk (0x01UL << SCT_OUT12_SET_SET13_Pos) /*!< SCT OUT12_SET: SET13 Mask */ #define SCT_OUT12_SET_SET14_Pos 14 /*!< SCT OUT12_SET: SET14 Position */ #define SCT_OUT12_SET_SET14_Msk (0x01UL << SCT_OUT12_SET_SET14_Pos) /*!< SCT OUT12_SET: SET14 Mask */ #define SCT_OUT12_SET_SET15_Pos 15 /*!< SCT OUT12_SET: SET15 Position */ #define SCT_OUT12_SET_SET15_Msk (0x01UL << SCT_OUT12_SET_SET15_Pos) /*!< SCT OUT12_SET: SET15 Mask */ /* -------------------------------- SCT_OUT12_CLR ------------------------------- */ #define SCT_OUT12_CLR_CLR0_Pos 0 /*!< SCT OUT12_CLR: CLR0 Position */ #define SCT_OUT12_CLR_CLR0_Msk (0x01UL << SCT_OUT12_CLR_CLR0_Pos) /*!< SCT OUT12_CLR: CLR0 Mask */ #define SCT_OUT12_CLR_CLR1_Pos 1 /*!< SCT OUT12_CLR: CLR1 Position */ #define SCT_OUT12_CLR_CLR1_Msk (0x01UL << SCT_OUT12_CLR_CLR1_Pos) /*!< SCT OUT12_CLR: CLR1 Mask */ #define SCT_OUT12_CLR_CLR2_Pos 2 /*!< SCT OUT12_CLR: CLR2 Position */ #define SCT_OUT12_CLR_CLR2_Msk (0x01UL << SCT_OUT12_CLR_CLR2_Pos) /*!< SCT OUT12_CLR: CLR2 Mask */ #define SCT_OUT12_CLR_CLR3_Pos 3 /*!< SCT OUT12_CLR: CLR3 Position */ #define SCT_OUT12_CLR_CLR3_Msk (0x01UL << SCT_OUT12_CLR_CLR3_Pos) /*!< SCT OUT12_CLR: CLR3 Mask */ #define SCT_OUT12_CLR_CLR4_Pos 4 /*!< SCT OUT12_CLR: CLR4 Position */ #define SCT_OUT12_CLR_CLR4_Msk (0x01UL << SCT_OUT12_CLR_CLR4_Pos) /*!< SCT OUT12_CLR: CLR4 Mask */ #define SCT_OUT12_CLR_CLR5_Pos 5 /*!< SCT OUT12_CLR: CLR5 Position */ #define SCT_OUT12_CLR_CLR5_Msk (0x01UL << SCT_OUT12_CLR_CLR5_Pos) /*!< SCT OUT12_CLR: CLR5 Mask */ #define SCT_OUT12_CLR_CLR6_Pos 6 /*!< SCT OUT12_CLR: CLR6 Position */ #define SCT_OUT12_CLR_CLR6_Msk (0x01UL << SCT_OUT12_CLR_CLR6_Pos) /*!< SCT OUT12_CLR: CLR6 Mask */ #define SCT_OUT12_CLR_CLR7_Pos 7 /*!< SCT OUT12_CLR: CLR7 Position */ #define SCT_OUT12_CLR_CLR7_Msk (0x01UL << SCT_OUT12_CLR_CLR7_Pos) /*!< SCT OUT12_CLR: CLR7 Mask */ #define SCT_OUT12_CLR_CLR8_Pos 8 /*!< SCT OUT12_CLR: CLR8 Position */ #define SCT_OUT12_CLR_CLR8_Msk (0x01UL << SCT_OUT12_CLR_CLR8_Pos) /*!< SCT OUT12_CLR: CLR8 Mask */ #define SCT_OUT12_CLR_CLR9_Pos 9 /*!< SCT OUT12_CLR: CLR9 Position */ #define SCT_OUT12_CLR_CLR9_Msk (0x01UL << SCT_OUT12_CLR_CLR9_Pos) /*!< SCT OUT12_CLR: CLR9 Mask */ #define SCT_OUT12_CLR_CLR10_Pos 10 /*!< SCT OUT12_CLR: CLR10 Position */ #define SCT_OUT12_CLR_CLR10_Msk (0x01UL << SCT_OUT12_CLR_CLR10_Pos) /*!< SCT OUT12_CLR: CLR10 Mask */ #define SCT_OUT12_CLR_CLR11_Pos 11 /*!< SCT OUT12_CLR: CLR11 Position */ #define SCT_OUT12_CLR_CLR11_Msk (0x01UL << SCT_OUT12_CLR_CLR11_Pos) /*!< SCT OUT12_CLR: CLR11 Mask */ #define SCT_OUT12_CLR_CLR12_Pos 12 /*!< SCT OUT12_CLR: CLR12 Position */ #define SCT_OUT12_CLR_CLR12_Msk (0x01UL << SCT_OUT12_CLR_CLR12_Pos) /*!< SCT OUT12_CLR: CLR12 Mask */ #define SCT_OUT12_CLR_CLR13_Pos 13 /*!< SCT OUT12_CLR: CLR13 Position */ #define SCT_OUT12_CLR_CLR13_Msk (0x01UL << SCT_OUT12_CLR_CLR13_Pos) /*!< SCT OUT12_CLR: CLR13 Mask */ #define SCT_OUT12_CLR_CLR14_Pos 14 /*!< SCT OUT12_CLR: CLR14 Position */ #define SCT_OUT12_CLR_CLR14_Msk (0x01UL << SCT_OUT12_CLR_CLR14_Pos) /*!< SCT OUT12_CLR: CLR14 Mask */ #define SCT_OUT12_CLR_CLR15_Pos 15 /*!< SCT OUT12_CLR: CLR15 Position */ #define SCT_OUT12_CLR_CLR15_Msk (0x01UL << SCT_OUT12_CLR_CLR15_Pos) /*!< SCT OUT12_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT13_SET ------------------------------- */ #define SCT_OUT13_SET_SET0_Pos 0 /*!< SCT OUT13_SET: SET0 Position */ #define SCT_OUT13_SET_SET0_Msk (0x01UL << SCT_OUT13_SET_SET0_Pos) /*!< SCT OUT13_SET: SET0 Mask */ #define SCT_OUT13_SET_SET1_Pos 1 /*!< SCT OUT13_SET: SET1 Position */ #define SCT_OUT13_SET_SET1_Msk (0x01UL << SCT_OUT13_SET_SET1_Pos) /*!< SCT OUT13_SET: SET1 Mask */ #define SCT_OUT13_SET_SET2_Pos 2 /*!< SCT OUT13_SET: SET2 Position */ #define SCT_OUT13_SET_SET2_Msk (0x01UL << SCT_OUT13_SET_SET2_Pos) /*!< SCT OUT13_SET: SET2 Mask */ #define SCT_OUT13_SET_SET3_Pos 3 /*!< SCT OUT13_SET: SET3 Position */ #define SCT_OUT13_SET_SET3_Msk (0x01UL << SCT_OUT13_SET_SET3_Pos) /*!< SCT OUT13_SET: SET3 Mask */ #define SCT_OUT13_SET_SET4_Pos 4 /*!< SCT OUT13_SET: SET4 Position */ #define SCT_OUT13_SET_SET4_Msk (0x01UL << SCT_OUT13_SET_SET4_Pos) /*!< SCT OUT13_SET: SET4 Mask */ #define SCT_OUT13_SET_SET5_Pos 5 /*!< SCT OUT13_SET: SET5 Position */ #define SCT_OUT13_SET_SET5_Msk (0x01UL << SCT_OUT13_SET_SET5_Pos) /*!< SCT OUT13_SET: SET5 Mask */ #define SCT_OUT13_SET_SET6_Pos 6 /*!< SCT OUT13_SET: SET6 Position */ #define SCT_OUT13_SET_SET6_Msk (0x01UL << SCT_OUT13_SET_SET6_Pos) /*!< SCT OUT13_SET: SET6 Mask */ #define SCT_OUT13_SET_SET7_Pos 7 /*!< SCT OUT13_SET: SET7 Position */ #define SCT_OUT13_SET_SET7_Msk (0x01UL << SCT_OUT13_SET_SET7_Pos) /*!< SCT OUT13_SET: SET7 Mask */ #define SCT_OUT13_SET_SET8_Pos 8 /*!< SCT OUT13_SET: SET8 Position */ #define SCT_OUT13_SET_SET8_Msk (0x01UL << SCT_OUT13_SET_SET8_Pos) /*!< SCT OUT13_SET: SET8 Mask */ #define SCT_OUT13_SET_SET9_Pos 9 /*!< SCT OUT13_SET: SET9 Position */ #define SCT_OUT13_SET_SET9_Msk (0x01UL << SCT_OUT13_SET_SET9_Pos) /*!< SCT OUT13_SET: SET9 Mask */ #define SCT_OUT13_SET_SET10_Pos 10 /*!< SCT OUT13_SET: SET10 Position */ #define SCT_OUT13_SET_SET10_Msk (0x01UL << SCT_OUT13_SET_SET10_Pos) /*!< SCT OUT13_SET: SET10 Mask */ #define SCT_OUT13_SET_SET11_Pos 11 /*!< SCT OUT13_SET: SET11 Position */ #define SCT_OUT13_SET_SET11_Msk (0x01UL << SCT_OUT13_SET_SET11_Pos) /*!< SCT OUT13_SET: SET11 Mask */ #define SCT_OUT13_SET_SET12_Pos 12 /*!< SCT OUT13_SET: SET12 Position */ #define SCT_OUT13_SET_SET12_Msk (0x01UL << SCT_OUT13_SET_SET12_Pos) /*!< SCT OUT13_SET: SET12 Mask */ #define SCT_OUT13_SET_SET13_Pos 13 /*!< SCT OUT13_SET: SET13 Position */ #define SCT_OUT13_SET_SET13_Msk (0x01UL << SCT_OUT13_SET_SET13_Pos) /*!< SCT OUT13_SET: SET13 Mask */ #define SCT_OUT13_SET_SET14_Pos 14 /*!< SCT OUT13_SET: SET14 Position */ #define SCT_OUT13_SET_SET14_Msk (0x01UL << SCT_OUT13_SET_SET14_Pos) /*!< SCT OUT13_SET: SET14 Mask */ #define SCT_OUT13_SET_SET15_Pos 15 /*!< SCT OUT13_SET: SET15 Position */ #define SCT_OUT13_SET_SET15_Msk (0x01UL << SCT_OUT13_SET_SET15_Pos) /*!< SCT OUT13_SET: SET15 Mask */ /* -------------------------------- SCT_OUT13_CLR ------------------------------- */ #define SCT_OUT13_CLR_CLR0_Pos 0 /*!< SCT OUT13_CLR: CLR0 Position */ #define SCT_OUT13_CLR_CLR0_Msk (0x01UL << SCT_OUT13_CLR_CLR0_Pos) /*!< SCT OUT13_CLR: CLR0 Mask */ #define SCT_OUT13_CLR_CLR1_Pos 1 /*!< SCT OUT13_CLR: CLR1 Position */ #define SCT_OUT13_CLR_CLR1_Msk (0x01UL << SCT_OUT13_CLR_CLR1_Pos) /*!< SCT OUT13_CLR: CLR1 Mask */ #define SCT_OUT13_CLR_CLR2_Pos 2 /*!< SCT OUT13_CLR: CLR2 Position */ #define SCT_OUT13_CLR_CLR2_Msk (0x01UL << SCT_OUT13_CLR_CLR2_Pos) /*!< SCT OUT13_CLR: CLR2 Mask */ #define SCT_OUT13_CLR_CLR3_Pos 3 /*!< SCT OUT13_CLR: CLR3 Position */ #define SCT_OUT13_CLR_CLR3_Msk (0x01UL << SCT_OUT13_CLR_CLR3_Pos) /*!< SCT OUT13_CLR: CLR3 Mask */ #define SCT_OUT13_CLR_CLR4_Pos 4 /*!< SCT OUT13_CLR: CLR4 Position */ #define SCT_OUT13_CLR_CLR4_Msk (0x01UL << SCT_OUT13_CLR_CLR4_Pos) /*!< SCT OUT13_CLR: CLR4 Mask */ #define SCT_OUT13_CLR_CLR5_Pos 5 /*!< SCT OUT13_CLR: CLR5 Position */ #define SCT_OUT13_CLR_CLR5_Msk (0x01UL << SCT_OUT13_CLR_CLR5_Pos) /*!< SCT OUT13_CLR: CLR5 Mask */ #define SCT_OUT13_CLR_CLR6_Pos 6 /*!< SCT OUT13_CLR: CLR6 Position */ #define SCT_OUT13_CLR_CLR6_Msk (0x01UL << SCT_OUT13_CLR_CLR6_Pos) /*!< SCT OUT13_CLR: CLR6 Mask */ #define SCT_OUT13_CLR_CLR7_Pos 7 /*!< SCT OUT13_CLR: CLR7 Position */ #define SCT_OUT13_CLR_CLR7_Msk (0x01UL << SCT_OUT13_CLR_CLR7_Pos) /*!< SCT OUT13_CLR: CLR7 Mask */ #define SCT_OUT13_CLR_CLR8_Pos 8 /*!< SCT OUT13_CLR: CLR8 Position */ #define SCT_OUT13_CLR_CLR8_Msk (0x01UL << SCT_OUT13_CLR_CLR8_Pos) /*!< SCT OUT13_CLR: CLR8 Mask */ #define SCT_OUT13_CLR_CLR9_Pos 9 /*!< SCT OUT13_CLR: CLR9 Position */ #define SCT_OUT13_CLR_CLR9_Msk (0x01UL << SCT_OUT13_CLR_CLR9_Pos) /*!< SCT OUT13_CLR: CLR9 Mask */ #define SCT_OUT13_CLR_CLR10_Pos 10 /*!< SCT OUT13_CLR: CLR10 Position */ #define SCT_OUT13_CLR_CLR10_Msk (0x01UL << SCT_OUT13_CLR_CLR10_Pos) /*!< SCT OUT13_CLR: CLR10 Mask */ #define SCT_OUT13_CLR_CLR11_Pos 11 /*!< SCT OUT13_CLR: CLR11 Position */ #define SCT_OUT13_CLR_CLR11_Msk (0x01UL << SCT_OUT13_CLR_CLR11_Pos) /*!< SCT OUT13_CLR: CLR11 Mask */ #define SCT_OUT13_CLR_CLR12_Pos 12 /*!< SCT OUT13_CLR: CLR12 Position */ #define SCT_OUT13_CLR_CLR12_Msk (0x01UL << SCT_OUT13_CLR_CLR12_Pos) /*!< SCT OUT13_CLR: CLR12 Mask */ #define SCT_OUT13_CLR_CLR13_Pos 13 /*!< SCT OUT13_CLR: CLR13 Position */ #define SCT_OUT13_CLR_CLR13_Msk (0x01UL << SCT_OUT13_CLR_CLR13_Pos) /*!< SCT OUT13_CLR: CLR13 Mask */ #define SCT_OUT13_CLR_CLR14_Pos 14 /*!< SCT OUT13_CLR: CLR14 Position */ #define SCT_OUT13_CLR_CLR14_Msk (0x01UL << SCT_OUT13_CLR_CLR14_Pos) /*!< SCT OUT13_CLR: CLR14 Mask */ #define SCT_OUT13_CLR_CLR15_Pos 15 /*!< SCT OUT13_CLR: CLR15 Position */ #define SCT_OUT13_CLR_CLR15_Msk (0x01UL << SCT_OUT13_CLR_CLR15_Pos) /*!< SCT OUT13_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT14_SET ------------------------------- */ #define SCT_OUT14_SET_SET0_Pos 0 /*!< SCT OUT14_SET: SET0 Position */ #define SCT_OUT14_SET_SET0_Msk (0x01UL << SCT_OUT14_SET_SET0_Pos) /*!< SCT OUT14_SET: SET0 Mask */ #define SCT_OUT14_SET_SET1_Pos 1 /*!< SCT OUT14_SET: SET1 Position */ #define SCT_OUT14_SET_SET1_Msk (0x01UL << SCT_OUT14_SET_SET1_Pos) /*!< SCT OUT14_SET: SET1 Mask */ #define SCT_OUT14_SET_SET2_Pos 2 /*!< SCT OUT14_SET: SET2 Position */ #define SCT_OUT14_SET_SET2_Msk (0x01UL << SCT_OUT14_SET_SET2_Pos) /*!< SCT OUT14_SET: SET2 Mask */ #define SCT_OUT14_SET_SET3_Pos 3 /*!< SCT OUT14_SET: SET3 Position */ #define SCT_OUT14_SET_SET3_Msk (0x01UL << SCT_OUT14_SET_SET3_Pos) /*!< SCT OUT14_SET: SET3 Mask */ #define SCT_OUT14_SET_SET4_Pos 4 /*!< SCT OUT14_SET: SET4 Position */ #define SCT_OUT14_SET_SET4_Msk (0x01UL << SCT_OUT14_SET_SET4_Pos) /*!< SCT OUT14_SET: SET4 Mask */ #define SCT_OUT14_SET_SET5_Pos 5 /*!< SCT OUT14_SET: SET5 Position */ #define SCT_OUT14_SET_SET5_Msk (0x01UL << SCT_OUT14_SET_SET5_Pos) /*!< SCT OUT14_SET: SET5 Mask */ #define SCT_OUT14_SET_SET6_Pos 6 /*!< SCT OUT14_SET: SET6 Position */ #define SCT_OUT14_SET_SET6_Msk (0x01UL << SCT_OUT14_SET_SET6_Pos) /*!< SCT OUT14_SET: SET6 Mask */ #define SCT_OUT14_SET_SET7_Pos 7 /*!< SCT OUT14_SET: SET7 Position */ #define SCT_OUT14_SET_SET7_Msk (0x01UL << SCT_OUT14_SET_SET7_Pos) /*!< SCT OUT14_SET: SET7 Mask */ #define SCT_OUT14_SET_SET8_Pos 8 /*!< SCT OUT14_SET: SET8 Position */ #define SCT_OUT14_SET_SET8_Msk (0x01UL << SCT_OUT14_SET_SET8_Pos) /*!< SCT OUT14_SET: SET8 Mask */ #define SCT_OUT14_SET_SET9_Pos 9 /*!< SCT OUT14_SET: SET9 Position */ #define SCT_OUT14_SET_SET9_Msk (0x01UL << SCT_OUT14_SET_SET9_Pos) /*!< SCT OUT14_SET: SET9 Mask */ #define SCT_OUT14_SET_SET10_Pos 10 /*!< SCT OUT14_SET: SET10 Position */ #define SCT_OUT14_SET_SET10_Msk (0x01UL << SCT_OUT14_SET_SET10_Pos) /*!< SCT OUT14_SET: SET10 Mask */ #define SCT_OUT14_SET_SET11_Pos 11 /*!< SCT OUT14_SET: SET11 Position */ #define SCT_OUT14_SET_SET11_Msk (0x01UL << SCT_OUT14_SET_SET11_Pos) /*!< SCT OUT14_SET: SET11 Mask */ #define SCT_OUT14_SET_SET12_Pos 12 /*!< SCT OUT14_SET: SET12 Position */ #define SCT_OUT14_SET_SET12_Msk (0x01UL << SCT_OUT14_SET_SET12_Pos) /*!< SCT OUT14_SET: SET12 Mask */ #define SCT_OUT14_SET_SET13_Pos 13 /*!< SCT OUT14_SET: SET13 Position */ #define SCT_OUT14_SET_SET13_Msk (0x01UL << SCT_OUT14_SET_SET13_Pos) /*!< SCT OUT14_SET: SET13 Mask */ #define SCT_OUT14_SET_SET14_Pos 14 /*!< SCT OUT14_SET: SET14 Position */ #define SCT_OUT14_SET_SET14_Msk (0x01UL << SCT_OUT14_SET_SET14_Pos) /*!< SCT OUT14_SET: SET14 Mask */ #define SCT_OUT14_SET_SET15_Pos 15 /*!< SCT OUT14_SET: SET15 Position */ #define SCT_OUT14_SET_SET15_Msk (0x01UL << SCT_OUT14_SET_SET15_Pos) /*!< SCT OUT14_SET: SET15 Mask */ /* -------------------------------- SCT_OUT14_CLR ------------------------------- */ #define SCT_OUT14_CLR_CLR0_Pos 0 /*!< SCT OUT14_CLR: CLR0 Position */ #define SCT_OUT14_CLR_CLR0_Msk (0x01UL << SCT_OUT14_CLR_CLR0_Pos) /*!< SCT OUT14_CLR: CLR0 Mask */ #define SCT_OUT14_CLR_CLR1_Pos 1 /*!< SCT OUT14_CLR: CLR1 Position */ #define SCT_OUT14_CLR_CLR1_Msk (0x01UL << SCT_OUT14_CLR_CLR1_Pos) /*!< SCT OUT14_CLR: CLR1 Mask */ #define SCT_OUT14_CLR_CLR2_Pos 2 /*!< SCT OUT14_CLR: CLR2 Position */ #define SCT_OUT14_CLR_CLR2_Msk (0x01UL << SCT_OUT14_CLR_CLR2_Pos) /*!< SCT OUT14_CLR: CLR2 Mask */ #define SCT_OUT14_CLR_CLR3_Pos 3 /*!< SCT OUT14_CLR: CLR3 Position */ #define SCT_OUT14_CLR_CLR3_Msk (0x01UL << SCT_OUT14_CLR_CLR3_Pos) /*!< SCT OUT14_CLR: CLR3 Mask */ #define SCT_OUT14_CLR_CLR4_Pos 4 /*!< SCT OUT14_CLR: CLR4 Position */ #define SCT_OUT14_CLR_CLR4_Msk (0x01UL << SCT_OUT14_CLR_CLR4_Pos) /*!< SCT OUT14_CLR: CLR4 Mask */ #define SCT_OUT14_CLR_CLR5_Pos 5 /*!< SCT OUT14_CLR: CLR5 Position */ #define SCT_OUT14_CLR_CLR5_Msk (0x01UL << SCT_OUT14_CLR_CLR5_Pos) /*!< SCT OUT14_CLR: CLR5 Mask */ #define SCT_OUT14_CLR_CLR6_Pos 6 /*!< SCT OUT14_CLR: CLR6 Position */ #define SCT_OUT14_CLR_CLR6_Msk (0x01UL << SCT_OUT14_CLR_CLR6_Pos) /*!< SCT OUT14_CLR: CLR6 Mask */ #define SCT_OUT14_CLR_CLR7_Pos 7 /*!< SCT OUT14_CLR: CLR7 Position */ #define SCT_OUT14_CLR_CLR7_Msk (0x01UL << SCT_OUT14_CLR_CLR7_Pos) /*!< SCT OUT14_CLR: CLR7 Mask */ #define SCT_OUT14_CLR_CLR8_Pos 8 /*!< SCT OUT14_CLR: CLR8 Position */ #define SCT_OUT14_CLR_CLR8_Msk (0x01UL << SCT_OUT14_CLR_CLR8_Pos) /*!< SCT OUT14_CLR: CLR8 Mask */ #define SCT_OUT14_CLR_CLR9_Pos 9 /*!< SCT OUT14_CLR: CLR9 Position */ #define SCT_OUT14_CLR_CLR9_Msk (0x01UL << SCT_OUT14_CLR_CLR9_Pos) /*!< SCT OUT14_CLR: CLR9 Mask */ #define SCT_OUT14_CLR_CLR10_Pos 10 /*!< SCT OUT14_CLR: CLR10 Position */ #define SCT_OUT14_CLR_CLR10_Msk (0x01UL << SCT_OUT14_CLR_CLR10_Pos) /*!< SCT OUT14_CLR: CLR10 Mask */ #define SCT_OUT14_CLR_CLR11_Pos 11 /*!< SCT OUT14_CLR: CLR11 Position */ #define SCT_OUT14_CLR_CLR11_Msk (0x01UL << SCT_OUT14_CLR_CLR11_Pos) /*!< SCT OUT14_CLR: CLR11 Mask */ #define SCT_OUT14_CLR_CLR12_Pos 12 /*!< SCT OUT14_CLR: CLR12 Position */ #define SCT_OUT14_CLR_CLR12_Msk (0x01UL << SCT_OUT14_CLR_CLR12_Pos) /*!< SCT OUT14_CLR: CLR12 Mask */ #define SCT_OUT14_CLR_CLR13_Pos 13 /*!< SCT OUT14_CLR: CLR13 Position */ #define SCT_OUT14_CLR_CLR13_Msk (0x01UL << SCT_OUT14_CLR_CLR13_Pos) /*!< SCT OUT14_CLR: CLR13 Mask */ #define SCT_OUT14_CLR_CLR14_Pos 14 /*!< SCT OUT14_CLR: CLR14 Position */ #define SCT_OUT14_CLR_CLR14_Msk (0x01UL << SCT_OUT14_CLR_CLR14_Pos) /*!< SCT OUT14_CLR: CLR14 Mask */ #define SCT_OUT14_CLR_CLR15_Pos 15 /*!< SCT OUT14_CLR: CLR15 Position */ #define SCT_OUT14_CLR_CLR15_Msk (0x01UL << SCT_OUT14_CLR_CLR15_Pos) /*!< SCT OUT14_CLR: CLR15 Mask */ /* -------------------------------- SCT_OUT15_SET ------------------------------- */ #define SCT_OUT15_SET_SET0_Pos 0 /*!< SCT OUT15_SET: SET0 Position */ #define SCT_OUT15_SET_SET0_Msk (0x01UL << SCT_OUT15_SET_SET0_Pos) /*!< SCT OUT15_SET: SET0 Mask */ #define SCT_OUT15_SET_SET1_Pos 1 /*!< SCT OUT15_SET: SET1 Position */ #define SCT_OUT15_SET_SET1_Msk (0x01UL << SCT_OUT15_SET_SET1_Pos) /*!< SCT OUT15_SET: SET1 Mask */ #define SCT_OUT15_SET_SET2_Pos 2 /*!< SCT OUT15_SET: SET2 Position */ #define SCT_OUT15_SET_SET2_Msk (0x01UL << SCT_OUT15_SET_SET2_Pos) /*!< SCT OUT15_SET: SET2 Mask */ #define SCT_OUT15_SET_SET3_Pos 3 /*!< SCT OUT15_SET: SET3 Position */ #define SCT_OUT15_SET_SET3_Msk (0x01UL << SCT_OUT15_SET_SET3_Pos) /*!< SCT OUT15_SET: SET3 Mask */ #define SCT_OUT15_SET_SET4_Pos 4 /*!< SCT OUT15_SET: SET4 Position */ #define SCT_OUT15_SET_SET4_Msk (0x01UL << SCT_OUT15_SET_SET4_Pos) /*!< SCT OUT15_SET: SET4 Mask */ #define SCT_OUT15_SET_SET5_Pos 5 /*!< SCT OUT15_SET: SET5 Position */ #define SCT_OUT15_SET_SET5_Msk (0x01UL << SCT_OUT15_SET_SET5_Pos) /*!< SCT OUT15_SET: SET5 Mask */ #define SCT_OUT15_SET_SET6_Pos 6 /*!< SCT OUT15_SET: SET6 Position */ #define SCT_OUT15_SET_SET6_Msk (0x01UL << SCT_OUT15_SET_SET6_Pos) /*!< SCT OUT15_SET: SET6 Mask */ #define SCT_OUT15_SET_SET7_Pos 7 /*!< SCT OUT15_SET: SET7 Position */ #define SCT_OUT15_SET_SET7_Msk (0x01UL << SCT_OUT15_SET_SET7_Pos) /*!< SCT OUT15_SET: SET7 Mask */ #define SCT_OUT15_SET_SET8_Pos 8 /*!< SCT OUT15_SET: SET8 Position */ #define SCT_OUT15_SET_SET8_Msk (0x01UL << SCT_OUT15_SET_SET8_Pos) /*!< SCT OUT15_SET: SET8 Mask */ #define SCT_OUT15_SET_SET9_Pos 9 /*!< SCT OUT15_SET: SET9 Position */ #define SCT_OUT15_SET_SET9_Msk (0x01UL << SCT_OUT15_SET_SET9_Pos) /*!< SCT OUT15_SET: SET9 Mask */ #define SCT_OUT15_SET_SET10_Pos 10 /*!< SCT OUT15_SET: SET10 Position */ #define SCT_OUT15_SET_SET10_Msk (0x01UL << SCT_OUT15_SET_SET10_Pos) /*!< SCT OUT15_SET: SET10 Mask */ #define SCT_OUT15_SET_SET11_Pos 11 /*!< SCT OUT15_SET: SET11 Position */ #define SCT_OUT15_SET_SET11_Msk (0x01UL << SCT_OUT15_SET_SET11_Pos) /*!< SCT OUT15_SET: SET11 Mask */ #define SCT_OUT15_SET_SET12_Pos 12 /*!< SCT OUT15_SET: SET12 Position */ #define SCT_OUT15_SET_SET12_Msk (0x01UL << SCT_OUT15_SET_SET12_Pos) /*!< SCT OUT15_SET: SET12 Mask */ #define SCT_OUT15_SET_SET13_Pos 13 /*!< SCT OUT15_SET: SET13 Position */ #define SCT_OUT15_SET_SET13_Msk (0x01UL << SCT_OUT15_SET_SET13_Pos) /*!< SCT OUT15_SET: SET13 Mask */ #define SCT_OUT15_SET_SET14_Pos 14 /*!< SCT OUT15_SET: SET14 Position */ #define SCT_OUT15_SET_SET14_Msk (0x01UL << SCT_OUT15_SET_SET14_Pos) /*!< SCT OUT15_SET: SET14 Mask */ #define SCT_OUT15_SET_SET15_Pos 15 /*!< SCT OUT15_SET: SET15 Position */ #define SCT_OUT15_SET_SET15_Msk (0x01UL << SCT_OUT15_SET_SET15_Pos) /*!< SCT OUT15_SET: SET15 Mask */ /* -------------------------------- SCT_OUT15_CLR ------------------------------- */ #define SCT_OUT15_CLR_CLR0_Pos 0 /*!< SCT OUT15_CLR: CLR0 Position */ #define SCT_OUT15_CLR_CLR0_Msk (0x01UL << SCT_OUT15_CLR_CLR0_Pos) /*!< SCT OUT15_CLR: CLR0 Mask */ #define SCT_OUT15_CLR_CLR1_Pos 1 /*!< SCT OUT15_CLR: CLR1 Position */ #define SCT_OUT15_CLR_CLR1_Msk (0x01UL << SCT_OUT15_CLR_CLR1_Pos) /*!< SCT OUT15_CLR: CLR1 Mask */ #define SCT_OUT15_CLR_CLR2_Pos 2 /*!< SCT OUT15_CLR: CLR2 Position */ #define SCT_OUT15_CLR_CLR2_Msk (0x01UL << SCT_OUT15_CLR_CLR2_Pos) /*!< SCT OUT15_CLR: CLR2 Mask */ #define SCT_OUT15_CLR_CLR3_Pos 3 /*!< SCT OUT15_CLR: CLR3 Position */ #define SCT_OUT15_CLR_CLR3_Msk (0x01UL << SCT_OUT15_CLR_CLR3_Pos) /*!< SCT OUT15_CLR: CLR3 Mask */ #define SCT_OUT15_CLR_CLR4_Pos 4 /*!< SCT OUT15_CLR: CLR4 Position */ #define SCT_OUT15_CLR_CLR4_Msk (0x01UL << SCT_OUT15_CLR_CLR4_Pos) /*!< SCT OUT15_CLR: CLR4 Mask */ #define SCT_OUT15_CLR_CLR5_Pos 5 /*!< SCT OUT15_CLR: CLR5 Position */ #define SCT_OUT15_CLR_CLR5_Msk (0x01UL << SCT_OUT15_CLR_CLR5_Pos) /*!< SCT OUT15_CLR: CLR5 Mask */ #define SCT_OUT15_CLR_CLR6_Pos 6 /*!< SCT OUT15_CLR: CLR6 Position */ #define SCT_OUT15_CLR_CLR6_Msk (0x01UL << SCT_OUT15_CLR_CLR6_Pos) /*!< SCT OUT15_CLR: CLR6 Mask */ #define SCT_OUT15_CLR_CLR7_Pos 7 /*!< SCT OUT15_CLR: CLR7 Position */ #define SCT_OUT15_CLR_CLR7_Msk (0x01UL << SCT_OUT15_CLR_CLR7_Pos) /*!< SCT OUT15_CLR: CLR7 Mask */ #define SCT_OUT15_CLR_CLR8_Pos 8 /*!< SCT OUT15_CLR: CLR8 Position */ #define SCT_OUT15_CLR_CLR8_Msk (0x01UL << SCT_OUT15_CLR_CLR8_Pos) /*!< SCT OUT15_CLR: CLR8 Mask */ #define SCT_OUT15_CLR_CLR9_Pos 9 /*!< SCT OUT15_CLR: CLR9 Position */ #define SCT_OUT15_CLR_CLR9_Msk (0x01UL << SCT_OUT15_CLR_CLR9_Pos) /*!< SCT OUT15_CLR: CLR9 Mask */ #define SCT_OUT15_CLR_CLR10_Pos 10 /*!< SCT OUT15_CLR: CLR10 Position */ #define SCT_OUT15_CLR_CLR10_Msk (0x01UL << SCT_OUT15_CLR_CLR10_Pos) /*!< SCT OUT15_CLR: CLR10 Mask */ #define SCT_OUT15_CLR_CLR11_Pos 11 /*!< SCT OUT15_CLR: CLR11 Position */ #define SCT_OUT15_CLR_CLR11_Msk (0x01UL << SCT_OUT15_CLR_CLR11_Pos) /*!< SCT OUT15_CLR: CLR11 Mask */ #define SCT_OUT15_CLR_CLR12_Pos 12 /*!< SCT OUT15_CLR: CLR12 Position */ #define SCT_OUT15_CLR_CLR12_Msk (0x01UL << SCT_OUT15_CLR_CLR12_Pos) /*!< SCT OUT15_CLR: CLR12 Mask */ #define SCT_OUT15_CLR_CLR13_Pos 13 /*!< SCT OUT15_CLR: CLR13 Position */ #define SCT_OUT15_CLR_CLR13_Msk (0x01UL << SCT_OUT15_CLR_CLR13_Pos) /*!< SCT OUT15_CLR: CLR13 Mask */ #define SCT_OUT15_CLR_CLR14_Pos 14 /*!< SCT OUT15_CLR: CLR14 Position */ #define SCT_OUT15_CLR_CLR14_Msk (0x01UL << SCT_OUT15_CLR_CLR14_Pos) /*!< SCT OUT15_CLR: CLR14 Mask */ #define SCT_OUT15_CLR_CLR15_Pos 15 /*!< SCT OUT15_CLR: CLR15 Position */ #define SCT_OUT15_CLR_CLR15_Msk (0x01UL << SCT_OUT15_CLR_CLR15_Pos) /*!< SCT OUT15_CLR: CLR15 Mask */ /* ================================================================================ */ /* ================ struct 'GPDMA' Position & Mask ================ */ /* ================================================================================ */ /* -------------------------------- GPDMA_INTSTAT ------------------------------- */ #define GPDMA_INTSTAT_INTSTAT0_Pos 0 /*!< GPDMA INTSTAT: INTSTAT0 Position */ #define GPDMA_INTSTAT_INTSTAT0_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT0_Pos) /*!< GPDMA INTSTAT: INTSTAT0 Mask */ #define GPDMA_INTSTAT_INTSTAT1_Pos 1 /*!< GPDMA INTSTAT: INTSTAT1 Position */ #define GPDMA_INTSTAT_INTSTAT1_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT1_Pos) /*!< GPDMA INTSTAT: INTSTAT1 Mask */ #define GPDMA_INTSTAT_INTSTAT2_Pos 2 /*!< GPDMA INTSTAT: INTSTAT2 Position */ #define GPDMA_INTSTAT_INTSTAT2_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT2_Pos) /*!< GPDMA INTSTAT: INTSTAT2 Mask */ #define GPDMA_INTSTAT_INTSTAT3_Pos 3 /*!< GPDMA INTSTAT: INTSTAT3 Position */ #define GPDMA_INTSTAT_INTSTAT3_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT3_Pos) /*!< GPDMA INTSTAT: INTSTAT3 Mask */ #define GPDMA_INTSTAT_INTSTAT4_Pos 4 /*!< GPDMA INTSTAT: INTSTAT4 Position */ #define GPDMA_INTSTAT_INTSTAT4_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT4_Pos) /*!< GPDMA INTSTAT: INTSTAT4 Mask */ #define GPDMA_INTSTAT_INTSTAT5_Pos 5 /*!< GPDMA INTSTAT: INTSTAT5 Position */ #define GPDMA_INTSTAT_INTSTAT5_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT5_Pos) /*!< GPDMA INTSTAT: INTSTAT5 Mask */ #define GPDMA_INTSTAT_INTSTAT6_Pos 6 /*!< GPDMA INTSTAT: INTSTAT6 Position */ #define GPDMA_INTSTAT_INTSTAT6_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT6_Pos) /*!< GPDMA INTSTAT: INTSTAT6 Mask */ #define GPDMA_INTSTAT_INTSTAT7_Pos 7 /*!< GPDMA INTSTAT: INTSTAT7 Position */ #define GPDMA_INTSTAT_INTSTAT7_Msk (0x01UL << GPDMA_INTSTAT_INTSTAT7_Pos) /*!< GPDMA INTSTAT: INTSTAT7 Mask */ /* ------------------------------- GPDMA_INTTCSTAT ------------------------------ */ #define GPDMA_INTTCSTAT_INTTCSTAT0_Pos 0 /*!< GPDMA INTTCSTAT: INTTCSTAT0 Position */ #define GPDMA_INTTCSTAT_INTTCSTAT0_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT0_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT0 Mask */ #define GPDMA_INTTCSTAT_INTTCSTAT1_Pos 1 /*!< GPDMA INTTCSTAT: INTTCSTAT1 Position */ #define GPDMA_INTTCSTAT_INTTCSTAT1_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT1_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT1 Mask */ #define GPDMA_INTTCSTAT_INTTCSTAT2_Pos 2 /*!< GPDMA INTTCSTAT: INTTCSTAT2 Position */ #define GPDMA_INTTCSTAT_INTTCSTAT2_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT2_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT2 Mask */ #define GPDMA_INTTCSTAT_INTTCSTAT3_Pos 3 /*!< GPDMA INTTCSTAT: INTTCSTAT3 Position */ #define GPDMA_INTTCSTAT_INTTCSTAT3_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT3_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT3 Mask */ #define GPDMA_INTTCSTAT_INTTCSTAT4_Pos 4 /*!< GPDMA INTTCSTAT: INTTCSTAT4 Position */ #define GPDMA_INTTCSTAT_INTTCSTAT4_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT4_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT4 Mask */ #define GPDMA_INTTCSTAT_INTTCSTAT5_Pos 5 /*!< GPDMA INTTCSTAT: INTTCSTAT5 Position */ #define GPDMA_INTTCSTAT_INTTCSTAT5_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT5_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT5 Mask */ #define GPDMA_INTTCSTAT_INTTCSTAT6_Pos 6 /*!< GPDMA INTTCSTAT: INTTCSTAT6 Position */ #define GPDMA_INTTCSTAT_INTTCSTAT6_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT6_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT6 Mask */ #define GPDMA_INTTCSTAT_INTTCSTAT7_Pos 7 /*!< GPDMA INTTCSTAT: INTTCSTAT7 Position */ #define GPDMA_INTTCSTAT_INTTCSTAT7_Msk (0x01UL << GPDMA_INTTCSTAT_INTTCSTAT7_Pos) /*!< GPDMA INTTCSTAT: INTTCSTAT7 Mask */ /* ------------------------------ GPDMA_INTTCCLEAR ------------------------------ */ #define GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos 0 /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Position */ #define GPDMA_INTTCCLEAR_INTTCCLEAR0_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR0_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR0 Mask */ #define GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos 1 /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Position */ #define GPDMA_INTTCCLEAR_INTTCCLEAR1_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR1_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR1 Mask */ #define GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos 2 /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Position */ #define GPDMA_INTTCCLEAR_INTTCCLEAR2_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR2_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR2 Mask */ #define GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos 3 /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Position */ #define GPDMA_INTTCCLEAR_INTTCCLEAR3_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR3_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR3 Mask */ #define GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos 4 /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Position */ #define GPDMA_INTTCCLEAR_INTTCCLEAR4_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR4_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR4 Mask */ #define GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos 5 /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Position */ #define GPDMA_INTTCCLEAR_INTTCCLEAR5_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR5_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR5 Mask */ #define GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos 6 /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Position */ #define GPDMA_INTTCCLEAR_INTTCCLEAR6_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR6_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR6 Mask */ #define GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos 7 /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Position */ #define GPDMA_INTTCCLEAR_INTTCCLEAR7_Msk (0x01UL << GPDMA_INTTCCLEAR_INTTCCLEAR7_Pos) /*!< GPDMA INTTCCLEAR: INTTCCLEAR7 Mask */ /* ------------------------------ GPDMA_INTERRSTAT ------------------------------ */ #define GPDMA_INTERRSTAT_INTERRSTAT0_Pos 0 /*!< GPDMA INTERRSTAT: INTERRSTAT0 Position */ #define GPDMA_INTERRSTAT_INTERRSTAT0_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT0_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT0 Mask */ #define GPDMA_INTERRSTAT_INTERRSTAT1_Pos 1 /*!< GPDMA INTERRSTAT: INTERRSTAT1 Position */ #define GPDMA_INTERRSTAT_INTERRSTAT1_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT1_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT1 Mask */ #define GPDMA_INTERRSTAT_INTERRSTAT2_Pos 2 /*!< GPDMA INTERRSTAT: INTERRSTAT2 Position */ #define GPDMA_INTERRSTAT_INTERRSTAT2_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT2_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT2 Mask */ #define GPDMA_INTERRSTAT_INTERRSTAT3_Pos 3 /*!< GPDMA INTERRSTAT: INTERRSTAT3 Position */ #define GPDMA_INTERRSTAT_INTERRSTAT3_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT3_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT3 Mask */ #define GPDMA_INTERRSTAT_INTERRSTAT4_Pos 4 /*!< GPDMA INTERRSTAT: INTERRSTAT4 Position */ #define GPDMA_INTERRSTAT_INTERRSTAT4_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT4_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT4 Mask */ #define GPDMA_INTERRSTAT_INTERRSTAT5_Pos 5 /*!< GPDMA INTERRSTAT: INTERRSTAT5 Position */ #define GPDMA_INTERRSTAT_INTERRSTAT5_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT5_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT5 Mask */ #define GPDMA_INTERRSTAT_INTERRSTAT6_Pos 6 /*!< GPDMA INTERRSTAT: INTERRSTAT6 Position */ #define GPDMA_INTERRSTAT_INTERRSTAT6_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT6_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT6 Mask */ #define GPDMA_INTERRSTAT_INTERRSTAT7_Pos 7 /*!< GPDMA INTERRSTAT: INTERRSTAT7 Position */ #define GPDMA_INTERRSTAT_INTERRSTAT7_Msk (0x01UL << GPDMA_INTERRSTAT_INTERRSTAT7_Pos) /*!< GPDMA INTERRSTAT: INTERRSTAT7 Mask */ /* ------------------------------- GPDMA_INTERRCLR ------------------------------ */ #define GPDMA_INTERRCLR_INTERRCLR0_Pos 0 /*!< GPDMA INTERRCLR: INTERRCLR0 Position */ #define GPDMA_INTERRCLR_INTERRCLR0_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR0_Pos) /*!< GPDMA INTERRCLR: INTERRCLR0 Mask */ #define GPDMA_INTERRCLR_INTERRCLR1_Pos 1 /*!< GPDMA INTERRCLR: INTERRCLR1 Position */ #define GPDMA_INTERRCLR_INTERRCLR1_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR1_Pos) /*!< GPDMA INTERRCLR: INTERRCLR1 Mask */ #define GPDMA_INTERRCLR_INTERRCLR2_Pos 2 /*!< GPDMA INTERRCLR: INTERRCLR2 Position */ #define GPDMA_INTERRCLR_INTERRCLR2_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR2_Pos) /*!< GPDMA INTERRCLR: INTERRCLR2 Mask */ #define GPDMA_INTERRCLR_INTERRCLR3_Pos 3 /*!< GPDMA INTERRCLR: INTERRCLR3 Position */ #define GPDMA_INTERRCLR_INTERRCLR3_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR3_Pos) /*!< GPDMA INTERRCLR: INTERRCLR3 Mask */ #define GPDMA_INTERRCLR_INTERRCLR4_Pos 4 /*!< GPDMA INTERRCLR: INTERRCLR4 Position */ #define GPDMA_INTERRCLR_INTERRCLR4_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR4_Pos) /*!< GPDMA INTERRCLR: INTERRCLR4 Mask */ #define GPDMA_INTERRCLR_INTERRCLR5_Pos 5 /*!< GPDMA INTERRCLR: INTERRCLR5 Position */ #define GPDMA_INTERRCLR_INTERRCLR5_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR5_Pos) /*!< GPDMA INTERRCLR: INTERRCLR5 Mask */ #define GPDMA_INTERRCLR_INTERRCLR6_Pos 6 /*!< GPDMA INTERRCLR: INTERRCLR6 Position */ #define GPDMA_INTERRCLR_INTERRCLR6_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR6_Pos) /*!< GPDMA INTERRCLR: INTERRCLR6 Mask */ #define GPDMA_INTERRCLR_INTERRCLR7_Pos 7 /*!< GPDMA INTERRCLR: INTERRCLR7 Position */ #define GPDMA_INTERRCLR_INTERRCLR7_Msk (0x01UL << GPDMA_INTERRCLR_INTERRCLR7_Pos) /*!< GPDMA INTERRCLR: INTERRCLR7 Mask */ /* ----------------------------- GPDMA_RAWINTTCSTAT ----------------------------- */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos 0 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Position */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT0_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT0 Mask */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos 1 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Position */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT1_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT1 Mask */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos 2 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Position */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT2_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT2 Mask */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos 3 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Position */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT3_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT3 Mask */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos 4 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Position */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT4_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT4 Mask */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos 5 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Position */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT5_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT5 Mask */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos 6 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Position */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT6_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT6 Mask */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos 7 /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Position */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Msk (0x01UL << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT7_Pos) /*!< GPDMA RAWINTTCSTAT: RAWINTTCSTAT7 Mask */ /* ----------------------------- GPDMA_RAWINTERRSTAT ---------------------------- */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos 0 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Position */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT0_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT0 Mask */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos 1 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Position */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT1_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT1 Mask */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos 2 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Position */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT2_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT2 Mask */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos 3 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Position */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT3_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT3 Mask */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos 4 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Position */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT4_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT4 Mask */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos 5 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Position */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT5_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT5 Mask */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos 6 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Position */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT6_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT6 Mask */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos 7 /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Position */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Msk (0x01UL << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT7_Pos) /*!< GPDMA RAWINTERRSTAT: RAWINTERRSTAT7 Mask */ /* ------------------------------- GPDMA_ENBLDCHNS ------------------------------ */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos 0 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Position */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS0_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS0 Mask */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos 1 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Position */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS1_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS1 Mask */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos 2 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Position */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS2_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS2 Mask */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos 3 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Position */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS3_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS3 Mask */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos 4 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Position */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS4_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS4 Mask */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos 5 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Position */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS5_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS5 Mask */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos 6 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Position */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS6_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS6 Mask */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos 7 /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Position */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Msk (0x01UL << GPDMA_ENBLDCHNS_ENABLEDCHANNELS7_Pos) /*!< GPDMA ENBLDCHNS: ENABLEDCHANNELS7 Mask */ /* ------------------------------- GPDMA_SOFTBREQ ------------------------------- */ #define GPDMA_SOFTBREQ_SOFTBREQ0_Pos 0 /*!< GPDMA SOFTBREQ: SOFTBREQ0 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ0_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ0_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ0 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ1_Pos 1 /*!< GPDMA SOFTBREQ: SOFTBREQ1 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ1_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ1_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ1 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ2_Pos 2 /*!< GPDMA SOFTBREQ: SOFTBREQ2 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ2_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ2_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ2 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ3_Pos 3 /*!< GPDMA SOFTBREQ: SOFTBREQ3 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ3_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ3_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ3 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ4_Pos 4 /*!< GPDMA SOFTBREQ: SOFTBREQ4 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ4_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ4_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ4 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ5_Pos 5 /*!< GPDMA SOFTBREQ: SOFTBREQ5 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ5_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ5_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ5 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ6_Pos 6 /*!< GPDMA SOFTBREQ: SOFTBREQ6 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ6_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ6_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ6 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ7_Pos 7 /*!< GPDMA SOFTBREQ: SOFTBREQ7 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ7_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ7_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ7 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ8_Pos 8 /*!< GPDMA SOFTBREQ: SOFTBREQ8 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ8_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ8_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ8 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ9_Pos 9 /*!< GPDMA SOFTBREQ: SOFTBREQ9 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ9_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ9_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ9 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ10_Pos 10 /*!< GPDMA SOFTBREQ: SOFTBREQ10 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ10_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ10_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ10 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ11_Pos 11 /*!< GPDMA SOFTBREQ: SOFTBREQ11 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ11_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ11_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ11 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ12_Pos 12 /*!< GPDMA SOFTBREQ: SOFTBREQ12 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ12_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ12_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ12 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ13_Pos 13 /*!< GPDMA SOFTBREQ: SOFTBREQ13 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ13_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ13_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ13 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ14_Pos 14 /*!< GPDMA SOFTBREQ: SOFTBREQ14 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ14_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ14_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ14 Mask */ #define GPDMA_SOFTBREQ_SOFTBREQ15_Pos 15 /*!< GPDMA SOFTBREQ: SOFTBREQ15 Position */ #define GPDMA_SOFTBREQ_SOFTBREQ15_Msk (0x01UL << GPDMA_SOFTBREQ_SOFTBREQ15_Pos) /*!< GPDMA SOFTBREQ: SOFTBREQ15 Mask */ /* ------------------------------- GPDMA_SOFTSREQ ------------------------------- */ #define GPDMA_SOFTSREQ_SOFTSREQ0_Pos 0 /*!< GPDMA SOFTSREQ: SOFTSREQ0 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ0_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ0_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ0 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ1_Pos 1 /*!< GPDMA SOFTSREQ: SOFTSREQ1 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ1_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ1_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ1 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ2_Pos 2 /*!< GPDMA SOFTSREQ: SOFTSREQ2 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ2_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ2_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ2 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ3_Pos 3 /*!< GPDMA SOFTSREQ: SOFTSREQ3 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ3_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ3_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ3 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ4_Pos 4 /*!< GPDMA SOFTSREQ: SOFTSREQ4 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ4_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ4_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ4 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ5_Pos 5 /*!< GPDMA SOFTSREQ: SOFTSREQ5 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ5_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ5_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ5 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ6_Pos 6 /*!< GPDMA SOFTSREQ: SOFTSREQ6 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ6_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ6_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ6 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ7_Pos 7 /*!< GPDMA SOFTSREQ: SOFTSREQ7 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ7_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ7_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ7 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ8_Pos 8 /*!< GPDMA SOFTSREQ: SOFTSREQ8 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ8_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ8_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ8 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ9_Pos 9 /*!< GPDMA SOFTSREQ: SOFTSREQ9 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ9_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ9_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ9 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ10_Pos 10 /*!< GPDMA SOFTSREQ: SOFTSREQ10 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ10_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ10_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ10 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ11_Pos 11 /*!< GPDMA SOFTSREQ: SOFTSREQ11 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ11_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ11_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ11 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ12_Pos 12 /*!< GPDMA SOFTSREQ: SOFTSREQ12 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ12_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ12_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ12 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ13_Pos 13 /*!< GPDMA SOFTSREQ: SOFTSREQ13 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ13_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ13_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ13 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ14_Pos 14 /*!< GPDMA SOFTSREQ: SOFTSREQ14 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ14_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ14_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ14 Mask */ #define GPDMA_SOFTSREQ_SOFTSREQ15_Pos 15 /*!< GPDMA SOFTSREQ: SOFTSREQ15 Position */ #define GPDMA_SOFTSREQ_SOFTSREQ15_Msk (0x01UL << GPDMA_SOFTSREQ_SOFTSREQ15_Pos) /*!< GPDMA SOFTSREQ: SOFTSREQ15 Mask */ /* ------------------------------- GPDMA_SOFTLBREQ ------------------------------ */ #define GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos 0 /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ0_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ0_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ0 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos 1 /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ1_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ1_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ1 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos 2 /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ2_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ2_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ2 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos 3 /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ3_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ3_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ3 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos 4 /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ4_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ4_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ4 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos 5 /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ5_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ5_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ5 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos 6 /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ6_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ6_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ6 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos 7 /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ7_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ7_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ7 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos 8 /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ8_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ8_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ8 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos 9 /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ9_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ9_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ9 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos 10 /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ10_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ10_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ10 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos 11 /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ11_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ11_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ11 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos 12 /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ12_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ12_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ12 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos 13 /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ13_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ13_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ13 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos 14 /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ14_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ14_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ14 Mask */ #define GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos 15 /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Position */ #define GPDMA_SOFTLBREQ_SOFTLBREQ15_Msk (0x01UL << GPDMA_SOFTLBREQ_SOFTLBREQ15_Pos) /*!< GPDMA SOFTLBREQ: SOFTLBREQ15 Mask */ /* ------------------------------- GPDMA_SOFTLSREQ ------------------------------ */ #define GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos 0 /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ0_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ0_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ0 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos 1 /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ1_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ1_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ1 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos 2 /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ2_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ2_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ2 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos 3 /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ3_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ3_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ3 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos 4 /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ4_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ4_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ4 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos 5 /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ5_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ5_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ5 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos 6 /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ6_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ6_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ6 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos 7 /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ7_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ7_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ7 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos 8 /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ8_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ8_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ8 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos 9 /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ9_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ9_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ9 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos 10 /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ10_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ10_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ10 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos 11 /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ11_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ11_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ11 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos 12 /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ12_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ12_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ12 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos 13 /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ13_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ13_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ13 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos 14 /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ14_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ14_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ14 Mask */ #define GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos 15 /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Position */ #define GPDMA_SOFTLSREQ_SOFTLSREQ15_Msk (0x01UL << GPDMA_SOFTLSREQ_SOFTLSREQ15_Pos) /*!< GPDMA SOFTLSREQ: SOFTLSREQ15 Mask */ /* -------------------------------- GPDMA_CONFIG -------------------------------- */ #define GPDMA_CONFIG_E_Pos 0 /*!< GPDMA CONFIG: E Position */ #define GPDMA_CONFIG_E_Msk (0x01UL << GPDMA_CONFIG_E_Pos) /*!< GPDMA CONFIG: E Mask */ #define GPDMA_CONFIG_M0_Pos 1 /*!< GPDMA CONFIG: M0 Position */ #define GPDMA_CONFIG_M0_Msk (0x01UL << GPDMA_CONFIG_M0_Pos) /*!< GPDMA CONFIG: M0 Mask */ #define GPDMA_CONFIG_M1_Pos 2 /*!< GPDMA CONFIG: M1 Position */ #define GPDMA_CONFIG_M1_Msk (0x01UL << GPDMA_CONFIG_M1_Pos) /*!< GPDMA CONFIG: M1 Mask */ /* --------------------------------- GPDMA_SYNC --------------------------------- */ #define GPDMA_SYNC_DMACSYNC0_Pos 0 /*!< GPDMA SYNC: DMACSYNC0 Position */ #define GPDMA_SYNC_DMACSYNC0_Msk (0x01UL << GPDMA_SYNC_DMACSYNC0_Pos) /*!< GPDMA SYNC: DMACSYNC0 Mask */ #define GPDMA_SYNC_DMACSYNC1_Pos 1 /*!< GPDMA SYNC: DMACSYNC1 Position */ #define GPDMA_SYNC_DMACSYNC1_Msk (0x01UL << GPDMA_SYNC_DMACSYNC1_Pos) /*!< GPDMA SYNC: DMACSYNC1 Mask */ #define GPDMA_SYNC_DMACSYNC2_Pos 2 /*!< GPDMA SYNC: DMACSYNC2 Position */ #define GPDMA_SYNC_DMACSYNC2_Msk (0x01UL << GPDMA_SYNC_DMACSYNC2_Pos) /*!< GPDMA SYNC: DMACSYNC2 Mask */ #define GPDMA_SYNC_DMACSYNC3_Pos 3 /*!< GPDMA SYNC: DMACSYNC3 Position */ #define GPDMA_SYNC_DMACSYNC3_Msk (0x01UL << GPDMA_SYNC_DMACSYNC3_Pos) /*!< GPDMA SYNC: DMACSYNC3 Mask */ #define GPDMA_SYNC_DMACSYNC4_Pos 4 /*!< GPDMA SYNC: DMACSYNC4 Position */ #define GPDMA_SYNC_DMACSYNC4_Msk (0x01UL << GPDMA_SYNC_DMACSYNC4_Pos) /*!< GPDMA SYNC: DMACSYNC4 Mask */ #define GPDMA_SYNC_DMACSYNC5_Pos 5 /*!< GPDMA SYNC: DMACSYNC5 Position */ #define GPDMA_SYNC_DMACSYNC5_Msk (0x01UL << GPDMA_SYNC_DMACSYNC5_Pos) /*!< GPDMA SYNC: DMACSYNC5 Mask */ #define GPDMA_SYNC_DMACSYNC6_Pos 6 /*!< GPDMA SYNC: DMACSYNC6 Position */ #define GPDMA_SYNC_DMACSYNC6_Msk (0x01UL << GPDMA_SYNC_DMACSYNC6_Pos) /*!< GPDMA SYNC: DMACSYNC6 Mask */ #define GPDMA_SYNC_DMACSYNC7_Pos 7 /*!< GPDMA SYNC: DMACSYNC7 Position */ #define GPDMA_SYNC_DMACSYNC7_Msk (0x01UL << GPDMA_SYNC_DMACSYNC7_Pos) /*!< GPDMA SYNC: DMACSYNC7 Mask */ #define GPDMA_SYNC_DMACSYNC8_Pos 8 /*!< GPDMA SYNC: DMACSYNC8 Position */ #define GPDMA_SYNC_DMACSYNC8_Msk (0x01UL << GPDMA_SYNC_DMACSYNC8_Pos) /*!< GPDMA SYNC: DMACSYNC8 Mask */ #define GPDMA_SYNC_DMACSYNC9_Pos 9 /*!< GPDMA SYNC: DMACSYNC9 Position */ #define GPDMA_SYNC_DMACSYNC9_Msk (0x01UL << GPDMA_SYNC_DMACSYNC9_Pos) /*!< GPDMA SYNC: DMACSYNC9 Mask */ #define GPDMA_SYNC_DMACSYNC10_Pos 10 /*!< GPDMA SYNC: DMACSYNC10 Position */ #define GPDMA_SYNC_DMACSYNC10_Msk (0x01UL << GPDMA_SYNC_DMACSYNC10_Pos) /*!< GPDMA SYNC: DMACSYNC10 Mask */ #define GPDMA_SYNC_DMACSYNC11_Pos 11 /*!< GPDMA SYNC: DMACSYNC11 Position */ #define GPDMA_SYNC_DMACSYNC11_Msk (0x01UL << GPDMA_SYNC_DMACSYNC11_Pos) /*!< GPDMA SYNC: DMACSYNC11 Mask */ #define GPDMA_SYNC_DMACSYNC12_Pos 12 /*!< GPDMA SYNC: DMACSYNC12 Position */ #define GPDMA_SYNC_DMACSYNC12_Msk (0x01UL << GPDMA_SYNC_DMACSYNC12_Pos) /*!< GPDMA SYNC: DMACSYNC12 Mask */ #define GPDMA_SYNC_DMACSYNC13_Pos 13 /*!< GPDMA SYNC: DMACSYNC13 Position */ #define GPDMA_SYNC_DMACSYNC13_Msk (0x01UL << GPDMA_SYNC_DMACSYNC13_Pos) /*!< GPDMA SYNC: DMACSYNC13 Mask */ #define GPDMA_SYNC_DMACSYNC14_Pos 14 /*!< GPDMA SYNC: DMACSYNC14 Position */ #define GPDMA_SYNC_DMACSYNC14_Msk (0x01UL << GPDMA_SYNC_DMACSYNC14_Pos) /*!< GPDMA SYNC: DMACSYNC14 Mask */ #define GPDMA_SYNC_DMACSYNC15_Pos 15 /*!< GPDMA SYNC: DMACSYNC15 Position */ #define GPDMA_SYNC_DMACSYNC15_Msk (0x01UL << GPDMA_SYNC_DMACSYNC15_Pos) /*!< GPDMA SYNC: DMACSYNC15 Mask */ /* ------------------------------- GPDMA_C0SRCADDR ------------------------------ */ #define GPDMA_C0SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C0SRCADDR: SRCADDR Position */ #define GPDMA_C0SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C0SRCADDR_SRCADDR_Pos) /*!< GPDMA C0SRCADDR: SRCADDR Mask */ /* ------------------------------ GPDMA_C0DESTADDR ------------------------------ */ #define GPDMA_C0DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C0DESTADDR: DESTADDR Position */ #define GPDMA_C0DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C0DESTADDR_DESTADDR_Pos) /*!< GPDMA C0DESTADDR: DESTADDR Mask */ /* --------------------------------- GPDMA_C0LLI -------------------------------- */ #define GPDMA_C0LLI_LM_Pos 0 /*!< GPDMA C0LLI: LM Position */ #define GPDMA_C0LLI_LM_Msk (0x01UL << GPDMA_C0LLI_LM_Pos) /*!< GPDMA C0LLI: LM Mask */ #define GPDMA_C0LLI_R_Pos 1 /*!< GPDMA C0LLI: R Position */ #define GPDMA_C0LLI_R_Msk (0x01UL << GPDMA_C0LLI_R_Pos) /*!< GPDMA C0LLI: R Mask */ #define GPDMA_C0LLI_LLI_Pos 2 /*!< GPDMA C0LLI: LLI Position */ #define GPDMA_C0LLI_LLI_Msk (0x3fffffffUL << GPDMA_C0LLI_LLI_Pos) /*!< GPDMA C0LLI: LLI Mask */ /* ------------------------------- GPDMA_C0CONTROL ------------------------------ */ #define GPDMA_C0CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C0CONTROL: TRANSFERSIZE Position */ #define GPDMA_C0CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C0CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C0CONTROL: TRANSFERSIZE Mask */ #define GPDMA_C0CONTROL_SBSIZE_Pos 12 /*!< GPDMA C0CONTROL: SBSIZE Position */ #define GPDMA_C0CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_SBSIZE_Pos) /*!< GPDMA C0CONTROL: SBSIZE Mask */ #define GPDMA_C0CONTROL_DBSIZE_Pos 15 /*!< GPDMA C0CONTROL: DBSIZE Position */ #define GPDMA_C0CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C0CONTROL_DBSIZE_Pos) /*!< GPDMA C0CONTROL: DBSIZE Mask */ #define GPDMA_C0CONTROL_SWIDTH_Pos 18 /*!< GPDMA C0CONTROL: SWIDTH Position */ #define GPDMA_C0CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_SWIDTH_Pos) /*!< GPDMA C0CONTROL: SWIDTH Mask */ #define GPDMA_C0CONTROL_DWIDTH_Pos 21 /*!< GPDMA C0CONTROL: DWIDTH Position */ #define GPDMA_C0CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C0CONTROL_DWIDTH_Pos) /*!< GPDMA C0CONTROL: DWIDTH Mask */ #define GPDMA_C0CONTROL_S_Pos 24 /*!< GPDMA C0CONTROL: S Position */ #define GPDMA_C0CONTROL_S_Msk (0x01UL << GPDMA_C0CONTROL_S_Pos) /*!< GPDMA C0CONTROL: S Mask */ #define GPDMA_C0CONTROL_D_Pos 25 /*!< GPDMA C0CONTROL: D Position */ #define GPDMA_C0CONTROL_D_Msk (0x01UL << GPDMA_C0CONTROL_D_Pos) /*!< GPDMA C0CONTROL: D Mask */ #define GPDMA_C0CONTROL_SI_Pos 26 /*!< GPDMA C0CONTROL: SI Position */ #define GPDMA_C0CONTROL_SI_Msk (0x01UL << GPDMA_C0CONTROL_SI_Pos) /*!< GPDMA C0CONTROL: SI Mask */ #define GPDMA_C0CONTROL_DI_Pos 27 /*!< GPDMA C0CONTROL: DI Position */ #define GPDMA_C0CONTROL_DI_Msk (0x01UL << GPDMA_C0CONTROL_DI_Pos) /*!< GPDMA C0CONTROL: DI Mask */ #define GPDMA_C0CONTROL_PROT1_Pos 28 /*!< GPDMA C0CONTROL: PROT1 Position */ #define GPDMA_C0CONTROL_PROT1_Msk (0x01UL << GPDMA_C0CONTROL_PROT1_Pos) /*!< GPDMA C0CONTROL: PROT1 Mask */ #define GPDMA_C0CONTROL_PROT2_Pos 29 /*!< GPDMA C0CONTROL: PROT2 Position */ #define GPDMA_C0CONTROL_PROT2_Msk (0x01UL << GPDMA_C0CONTROL_PROT2_Pos) /*!< GPDMA C0CONTROL: PROT2 Mask */ #define GPDMA_C0CONTROL_PROT3_Pos 30 /*!< GPDMA C0CONTROL: PROT3 Position */ #define GPDMA_C0CONTROL_PROT3_Msk (0x01UL << GPDMA_C0CONTROL_PROT3_Pos) /*!< GPDMA C0CONTROL: PROT3 Mask */ #define GPDMA_C0CONTROL_I_Pos 31 /*!< GPDMA C0CONTROL: I Position */ #define GPDMA_C0CONTROL_I_Msk (0x01UL << GPDMA_C0CONTROL_I_Pos) /*!< GPDMA C0CONTROL: I Mask */ /* ------------------------------- GPDMA_C0CONFIG ------------------------------- */ #define GPDMA_C0CONFIG_E_Pos 0 /*!< GPDMA C0CONFIG: E Position */ #define GPDMA_C0CONFIG_E_Msk (0x01UL << GPDMA_C0CONFIG_E_Pos) /*!< GPDMA C0CONFIG: E Mask */ #define GPDMA_C0CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C0CONFIG: SRCPERIPHERAL Position */ #define GPDMA_C0CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: SRCPERIPHERAL Mask */ #define GPDMA_C0CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C0CONFIG: DESTPERIPHERAL Position */ #define GPDMA_C0CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C0CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C0CONFIG: DESTPERIPHERAL Mask */ #define GPDMA_C0CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C0CONFIG: FLOWCNTRL Position */ #define GPDMA_C0CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C0CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C0CONFIG: FLOWCNTRL Mask */ #define GPDMA_C0CONFIG_IE_Pos 14 /*!< GPDMA C0CONFIG: IE Position */ #define GPDMA_C0CONFIG_IE_Msk (0x01UL << GPDMA_C0CONFIG_IE_Pos) /*!< GPDMA C0CONFIG: IE Mask */ #define GPDMA_C0CONFIG_ITC_Pos 15 /*!< GPDMA C0CONFIG: ITC Position */ #define GPDMA_C0CONFIG_ITC_Msk (0x01UL << GPDMA_C0CONFIG_ITC_Pos) /*!< GPDMA C0CONFIG: ITC Mask */ #define GPDMA_C0CONFIG_L_Pos 16 /*!< GPDMA C0CONFIG: L Position */ #define GPDMA_C0CONFIG_L_Msk (0x01UL << GPDMA_C0CONFIG_L_Pos) /*!< GPDMA C0CONFIG: L Mask */ #define GPDMA_C0CONFIG_A_Pos 17 /*!< GPDMA C0CONFIG: A Position */ #define GPDMA_C0CONFIG_A_Msk (0x01UL << GPDMA_C0CONFIG_A_Pos) /*!< GPDMA C0CONFIG: A Mask */ #define GPDMA_C0CONFIG_H_Pos 18 /*!< GPDMA C0CONFIG: H Position */ #define GPDMA_C0CONFIG_H_Msk (0x01UL << GPDMA_C0CONFIG_H_Pos) /*!< GPDMA C0CONFIG: H Mask */ /* ------------------------------- GPDMA_C1SRCADDR ------------------------------ */ #define GPDMA_C1SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C1SRCADDR: SRCADDR Position */ #define GPDMA_C1SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C1SRCADDR_SRCADDR_Pos) /*!< GPDMA C1SRCADDR: SRCADDR Mask */ /* ------------------------------ GPDMA_C1DESTADDR ------------------------------ */ #define GPDMA_C1DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C1DESTADDR: DESTADDR Position */ #define GPDMA_C1DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C1DESTADDR_DESTADDR_Pos) /*!< GPDMA C1DESTADDR: DESTADDR Mask */ /* --------------------------------- GPDMA_C1LLI -------------------------------- */ #define GPDMA_C1LLI_LM_Pos 0 /*!< GPDMA C1LLI: LM Position */ #define GPDMA_C1LLI_LM_Msk (0x01UL << GPDMA_C1LLI_LM_Pos) /*!< GPDMA C1LLI: LM Mask */ #define GPDMA_C1LLI_R_Pos 1 /*!< GPDMA C1LLI: R Position */ #define GPDMA_C1LLI_R_Msk (0x01UL << GPDMA_C1LLI_R_Pos) /*!< GPDMA C1LLI: R Mask */ #define GPDMA_C1LLI_LLI_Pos 2 /*!< GPDMA C1LLI: LLI Position */ #define GPDMA_C1LLI_LLI_Msk (0x3fffffffUL << GPDMA_C1LLI_LLI_Pos) /*!< GPDMA C1LLI: LLI Mask */ /* ------------------------------- GPDMA_C1CONTROL ------------------------------ */ #define GPDMA_C1CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C1CONTROL: TRANSFERSIZE Position */ #define GPDMA_C1CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C1CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C1CONTROL: TRANSFERSIZE Mask */ #define GPDMA_C1CONTROL_SBSIZE_Pos 12 /*!< GPDMA C1CONTROL: SBSIZE Position */ #define GPDMA_C1CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_SBSIZE_Pos) /*!< GPDMA C1CONTROL: SBSIZE Mask */ #define GPDMA_C1CONTROL_DBSIZE_Pos 15 /*!< GPDMA C1CONTROL: DBSIZE Position */ #define GPDMA_C1CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C1CONTROL_DBSIZE_Pos) /*!< GPDMA C1CONTROL: DBSIZE Mask */ #define GPDMA_C1CONTROL_SWIDTH_Pos 18 /*!< GPDMA C1CONTROL: SWIDTH Position */ #define GPDMA_C1CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_SWIDTH_Pos) /*!< GPDMA C1CONTROL: SWIDTH Mask */ #define GPDMA_C1CONTROL_DWIDTH_Pos 21 /*!< GPDMA C1CONTROL: DWIDTH Position */ #define GPDMA_C1CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C1CONTROL_DWIDTH_Pos) /*!< GPDMA C1CONTROL: DWIDTH Mask */ #define GPDMA_C1CONTROL_S_Pos 24 /*!< GPDMA C1CONTROL: S Position */ #define GPDMA_C1CONTROL_S_Msk (0x01UL << GPDMA_C1CONTROL_S_Pos) /*!< GPDMA C1CONTROL: S Mask */ #define GPDMA_C1CONTROL_D_Pos 25 /*!< GPDMA C1CONTROL: D Position */ #define GPDMA_C1CONTROL_D_Msk (0x01UL << GPDMA_C1CONTROL_D_Pos) /*!< GPDMA C1CONTROL: D Mask */ #define GPDMA_C1CONTROL_SI_Pos 26 /*!< GPDMA C1CONTROL: SI Position */ #define GPDMA_C1CONTROL_SI_Msk (0x01UL << GPDMA_C1CONTROL_SI_Pos) /*!< GPDMA C1CONTROL: SI Mask */ #define GPDMA_C1CONTROL_DI_Pos 27 /*!< GPDMA C1CONTROL: DI Position */ #define GPDMA_C1CONTROL_DI_Msk (0x01UL << GPDMA_C1CONTROL_DI_Pos) /*!< GPDMA C1CONTROL: DI Mask */ #define GPDMA_C1CONTROL_PROT1_Pos 28 /*!< GPDMA C1CONTROL: PROT1 Position */ #define GPDMA_C1CONTROL_PROT1_Msk (0x01UL << GPDMA_C1CONTROL_PROT1_Pos) /*!< GPDMA C1CONTROL: PROT1 Mask */ #define GPDMA_C1CONTROL_PROT2_Pos 29 /*!< GPDMA C1CONTROL: PROT2 Position */ #define GPDMA_C1CONTROL_PROT2_Msk (0x01UL << GPDMA_C1CONTROL_PROT2_Pos) /*!< GPDMA C1CONTROL: PROT2 Mask */ #define GPDMA_C1CONTROL_PROT3_Pos 30 /*!< GPDMA C1CONTROL: PROT3 Position */ #define GPDMA_C1CONTROL_PROT3_Msk (0x01UL << GPDMA_C1CONTROL_PROT3_Pos) /*!< GPDMA C1CONTROL: PROT3 Mask */ #define GPDMA_C1CONTROL_I_Pos 31 /*!< GPDMA C1CONTROL: I Position */ #define GPDMA_C1CONTROL_I_Msk (0x01UL << GPDMA_C1CONTROL_I_Pos) /*!< GPDMA C1CONTROL: I Mask */ /* ------------------------------- GPDMA_C1CONFIG ------------------------------- */ #define GPDMA_C1CONFIG_E_Pos 0 /*!< GPDMA C1CONFIG: E Position */ #define GPDMA_C1CONFIG_E_Msk (0x01UL << GPDMA_C1CONFIG_E_Pos) /*!< GPDMA C1CONFIG: E Mask */ #define GPDMA_C1CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C1CONFIG: SRCPERIPHERAL Position */ #define GPDMA_C1CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: SRCPERIPHERAL Mask */ #define GPDMA_C1CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C1CONFIG: DESTPERIPHERAL Position */ #define GPDMA_C1CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C1CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C1CONFIG: DESTPERIPHERAL Mask */ #define GPDMA_C1CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C1CONFIG: FLOWCNTRL Position */ #define GPDMA_C1CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C1CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C1CONFIG: FLOWCNTRL Mask */ #define GPDMA_C1CONFIG_IE_Pos 14 /*!< GPDMA C1CONFIG: IE Position */ #define GPDMA_C1CONFIG_IE_Msk (0x01UL << GPDMA_C1CONFIG_IE_Pos) /*!< GPDMA C1CONFIG: IE Mask */ #define GPDMA_C1CONFIG_ITC_Pos 15 /*!< GPDMA C1CONFIG: ITC Position */ #define GPDMA_C1CONFIG_ITC_Msk (0x01UL << GPDMA_C1CONFIG_ITC_Pos) /*!< GPDMA C1CONFIG: ITC Mask */ #define GPDMA_C1CONFIG_L_Pos 16 /*!< GPDMA C1CONFIG: L Position */ #define GPDMA_C1CONFIG_L_Msk (0x01UL << GPDMA_C1CONFIG_L_Pos) /*!< GPDMA C1CONFIG: L Mask */ #define GPDMA_C1CONFIG_A_Pos 17 /*!< GPDMA C1CONFIG: A Position */ #define GPDMA_C1CONFIG_A_Msk (0x01UL << GPDMA_C1CONFIG_A_Pos) /*!< GPDMA C1CONFIG: A Mask */ #define GPDMA_C1CONFIG_H_Pos 18 /*!< GPDMA C1CONFIG: H Position */ #define GPDMA_C1CONFIG_H_Msk (0x01UL << GPDMA_C1CONFIG_H_Pos) /*!< GPDMA C1CONFIG: H Mask */ /* ------------------------------- GPDMA_C2SRCADDR ------------------------------ */ #define GPDMA_C2SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C2SRCADDR: SRCADDR Position */ #define GPDMA_C2SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C2SRCADDR_SRCADDR_Pos) /*!< GPDMA C2SRCADDR: SRCADDR Mask */ /* ------------------------------ GPDMA_C2DESTADDR ------------------------------ */ #define GPDMA_C2DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C2DESTADDR: DESTADDR Position */ #define GPDMA_C2DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C2DESTADDR_DESTADDR_Pos) /*!< GPDMA C2DESTADDR: DESTADDR Mask */ /* --------------------------------- GPDMA_C2LLI -------------------------------- */ #define GPDMA_C2LLI_LM_Pos 0 /*!< GPDMA C2LLI: LM Position */ #define GPDMA_C2LLI_LM_Msk (0x01UL << GPDMA_C2LLI_LM_Pos) /*!< GPDMA C2LLI: LM Mask */ #define GPDMA_C2LLI_R_Pos 1 /*!< GPDMA C2LLI: R Position */ #define GPDMA_C2LLI_R_Msk (0x01UL << GPDMA_C2LLI_R_Pos) /*!< GPDMA C2LLI: R Mask */ #define GPDMA_C2LLI_LLI_Pos 2 /*!< GPDMA C2LLI: LLI Position */ #define GPDMA_C2LLI_LLI_Msk (0x3fffffffUL << GPDMA_C2LLI_LLI_Pos) /*!< GPDMA C2LLI: LLI Mask */ /* ------------------------------- GPDMA_C2CONTROL ------------------------------ */ #define GPDMA_C2CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C2CONTROL: TRANSFERSIZE Position */ #define GPDMA_C2CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C2CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C2CONTROL: TRANSFERSIZE Mask */ #define GPDMA_C2CONTROL_SBSIZE_Pos 12 /*!< GPDMA C2CONTROL: SBSIZE Position */ #define GPDMA_C2CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_SBSIZE_Pos) /*!< GPDMA C2CONTROL: SBSIZE Mask */ #define GPDMA_C2CONTROL_DBSIZE_Pos 15 /*!< GPDMA C2CONTROL: DBSIZE Position */ #define GPDMA_C2CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C2CONTROL_DBSIZE_Pos) /*!< GPDMA C2CONTROL: DBSIZE Mask */ #define GPDMA_C2CONTROL_SWIDTH_Pos 18 /*!< GPDMA C2CONTROL: SWIDTH Position */ #define GPDMA_C2CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_SWIDTH_Pos) /*!< GPDMA C2CONTROL: SWIDTH Mask */ #define GPDMA_C2CONTROL_DWIDTH_Pos 21 /*!< GPDMA C2CONTROL: DWIDTH Position */ #define GPDMA_C2CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C2CONTROL_DWIDTH_Pos) /*!< GPDMA C2CONTROL: DWIDTH Mask */ #define GPDMA_C2CONTROL_S_Pos 24 /*!< GPDMA C2CONTROL: S Position */ #define GPDMA_C2CONTROL_S_Msk (0x01UL << GPDMA_C2CONTROL_S_Pos) /*!< GPDMA C2CONTROL: S Mask */ #define GPDMA_C2CONTROL_D_Pos 25 /*!< GPDMA C2CONTROL: D Position */ #define GPDMA_C2CONTROL_D_Msk (0x01UL << GPDMA_C2CONTROL_D_Pos) /*!< GPDMA C2CONTROL: D Mask */ #define GPDMA_C2CONTROL_SI_Pos 26 /*!< GPDMA C2CONTROL: SI Position */ #define GPDMA_C2CONTROL_SI_Msk (0x01UL << GPDMA_C2CONTROL_SI_Pos) /*!< GPDMA C2CONTROL: SI Mask */ #define GPDMA_C2CONTROL_DI_Pos 27 /*!< GPDMA C2CONTROL: DI Position */ #define GPDMA_C2CONTROL_DI_Msk (0x01UL << GPDMA_C2CONTROL_DI_Pos) /*!< GPDMA C2CONTROL: DI Mask */ #define GPDMA_C2CONTROL_PROT1_Pos 28 /*!< GPDMA C2CONTROL: PROT1 Position */ #define GPDMA_C2CONTROL_PROT1_Msk (0x01UL << GPDMA_C2CONTROL_PROT1_Pos) /*!< GPDMA C2CONTROL: PROT1 Mask */ #define GPDMA_C2CONTROL_PROT2_Pos 29 /*!< GPDMA C2CONTROL: PROT2 Position */ #define GPDMA_C2CONTROL_PROT2_Msk (0x01UL << GPDMA_C2CONTROL_PROT2_Pos) /*!< GPDMA C2CONTROL: PROT2 Mask */ #define GPDMA_C2CONTROL_PROT3_Pos 30 /*!< GPDMA C2CONTROL: PROT3 Position */ #define GPDMA_C2CONTROL_PROT3_Msk (0x01UL << GPDMA_C2CONTROL_PROT3_Pos) /*!< GPDMA C2CONTROL: PROT3 Mask */ #define GPDMA_C2CONTROL_I_Pos 31 /*!< GPDMA C2CONTROL: I Position */ #define GPDMA_C2CONTROL_I_Msk (0x01UL << GPDMA_C2CONTROL_I_Pos) /*!< GPDMA C2CONTROL: I Mask */ /* ------------------------------- GPDMA_C2CONFIG ------------------------------- */ #define GPDMA_C2CONFIG_E_Pos 0 /*!< GPDMA C2CONFIG: E Position */ #define GPDMA_C2CONFIG_E_Msk (0x01UL << GPDMA_C2CONFIG_E_Pos) /*!< GPDMA C2CONFIG: E Mask */ #define GPDMA_C2CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C2CONFIG: SRCPERIPHERAL Position */ #define GPDMA_C2CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: SRCPERIPHERAL Mask */ #define GPDMA_C2CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C2CONFIG: DESTPERIPHERAL Position */ #define GPDMA_C2CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C2CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C2CONFIG: DESTPERIPHERAL Mask */ #define GPDMA_C2CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C2CONFIG: FLOWCNTRL Position */ #define GPDMA_C2CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C2CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C2CONFIG: FLOWCNTRL Mask */ #define GPDMA_C2CONFIG_IE_Pos 14 /*!< GPDMA C2CONFIG: IE Position */ #define GPDMA_C2CONFIG_IE_Msk (0x01UL << GPDMA_C2CONFIG_IE_Pos) /*!< GPDMA C2CONFIG: IE Mask */ #define GPDMA_C2CONFIG_ITC_Pos 15 /*!< GPDMA C2CONFIG: ITC Position */ #define GPDMA_C2CONFIG_ITC_Msk (0x01UL << GPDMA_C2CONFIG_ITC_Pos) /*!< GPDMA C2CONFIG: ITC Mask */ #define GPDMA_C2CONFIG_L_Pos 16 /*!< GPDMA C2CONFIG: L Position */ #define GPDMA_C2CONFIG_L_Msk (0x01UL << GPDMA_C2CONFIG_L_Pos) /*!< GPDMA C2CONFIG: L Mask */ #define GPDMA_C2CONFIG_A_Pos 17 /*!< GPDMA C2CONFIG: A Position */ #define GPDMA_C2CONFIG_A_Msk (0x01UL << GPDMA_C2CONFIG_A_Pos) /*!< GPDMA C2CONFIG: A Mask */ #define GPDMA_C2CONFIG_H_Pos 18 /*!< GPDMA C2CONFIG: H Position */ #define GPDMA_C2CONFIG_H_Msk (0x01UL << GPDMA_C2CONFIG_H_Pos) /*!< GPDMA C2CONFIG: H Mask */ /* ------------------------------- GPDMA_C3SRCADDR ------------------------------ */ #define GPDMA_C3SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C3SRCADDR: SRCADDR Position */ #define GPDMA_C3SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C3SRCADDR_SRCADDR_Pos) /*!< GPDMA C3SRCADDR: SRCADDR Mask */ /* ------------------------------ GPDMA_C3DESTADDR ------------------------------ */ #define GPDMA_C3DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C3DESTADDR: DESTADDR Position */ #define GPDMA_C3DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C3DESTADDR_DESTADDR_Pos) /*!< GPDMA C3DESTADDR: DESTADDR Mask */ /* --------------------------------- GPDMA_C3LLI -------------------------------- */ #define GPDMA_C3LLI_LM_Pos 0 /*!< GPDMA C3LLI: LM Position */ #define GPDMA_C3LLI_LM_Msk (0x01UL << GPDMA_C3LLI_LM_Pos) /*!< GPDMA C3LLI: LM Mask */ #define GPDMA_C3LLI_R_Pos 1 /*!< GPDMA C3LLI: R Position */ #define GPDMA_C3LLI_R_Msk (0x01UL << GPDMA_C3LLI_R_Pos) /*!< GPDMA C3LLI: R Mask */ #define GPDMA_C3LLI_LLI_Pos 2 /*!< GPDMA C3LLI: LLI Position */ #define GPDMA_C3LLI_LLI_Msk (0x3fffffffUL << GPDMA_C3LLI_LLI_Pos) /*!< GPDMA C3LLI: LLI Mask */ /* ------------------------------- GPDMA_C3CONTROL ------------------------------ */ #define GPDMA_C3CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C3CONTROL: TRANSFERSIZE Position */ #define GPDMA_C3CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C3CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C3CONTROL: TRANSFERSIZE Mask */ #define GPDMA_C3CONTROL_SBSIZE_Pos 12 /*!< GPDMA C3CONTROL: SBSIZE Position */ #define GPDMA_C3CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_SBSIZE_Pos) /*!< GPDMA C3CONTROL: SBSIZE Mask */ #define GPDMA_C3CONTROL_DBSIZE_Pos 15 /*!< GPDMA C3CONTROL: DBSIZE Position */ #define GPDMA_C3CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C3CONTROL_DBSIZE_Pos) /*!< GPDMA C3CONTROL: DBSIZE Mask */ #define GPDMA_C3CONTROL_SWIDTH_Pos 18 /*!< GPDMA C3CONTROL: SWIDTH Position */ #define GPDMA_C3CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_SWIDTH_Pos) /*!< GPDMA C3CONTROL: SWIDTH Mask */ #define GPDMA_C3CONTROL_DWIDTH_Pos 21 /*!< GPDMA C3CONTROL: DWIDTH Position */ #define GPDMA_C3CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C3CONTROL_DWIDTH_Pos) /*!< GPDMA C3CONTROL: DWIDTH Mask */ #define GPDMA_C3CONTROL_S_Pos 24 /*!< GPDMA C3CONTROL: S Position */ #define GPDMA_C3CONTROL_S_Msk (0x01UL << GPDMA_C3CONTROL_S_Pos) /*!< GPDMA C3CONTROL: S Mask */ #define GPDMA_C3CONTROL_D_Pos 25 /*!< GPDMA C3CONTROL: D Position */ #define GPDMA_C3CONTROL_D_Msk (0x01UL << GPDMA_C3CONTROL_D_Pos) /*!< GPDMA C3CONTROL: D Mask */ #define GPDMA_C3CONTROL_SI_Pos 26 /*!< GPDMA C3CONTROL: SI Position */ #define GPDMA_C3CONTROL_SI_Msk (0x01UL << GPDMA_C3CONTROL_SI_Pos) /*!< GPDMA C3CONTROL: SI Mask */ #define GPDMA_C3CONTROL_DI_Pos 27 /*!< GPDMA C3CONTROL: DI Position */ #define GPDMA_C3CONTROL_DI_Msk (0x01UL << GPDMA_C3CONTROL_DI_Pos) /*!< GPDMA C3CONTROL: DI Mask */ #define GPDMA_C3CONTROL_PROT1_Pos 28 /*!< GPDMA C3CONTROL: PROT1 Position */ #define GPDMA_C3CONTROL_PROT1_Msk (0x01UL << GPDMA_C3CONTROL_PROT1_Pos) /*!< GPDMA C3CONTROL: PROT1 Mask */ #define GPDMA_C3CONTROL_PROT2_Pos 29 /*!< GPDMA C3CONTROL: PROT2 Position */ #define GPDMA_C3CONTROL_PROT2_Msk (0x01UL << GPDMA_C3CONTROL_PROT2_Pos) /*!< GPDMA C3CONTROL: PROT2 Mask */ #define GPDMA_C3CONTROL_PROT3_Pos 30 /*!< GPDMA C3CONTROL: PROT3 Position */ #define GPDMA_C3CONTROL_PROT3_Msk (0x01UL << GPDMA_C3CONTROL_PROT3_Pos) /*!< GPDMA C3CONTROL: PROT3 Mask */ #define GPDMA_C3CONTROL_I_Pos 31 /*!< GPDMA C3CONTROL: I Position */ #define GPDMA_C3CONTROL_I_Msk (0x01UL << GPDMA_C3CONTROL_I_Pos) /*!< GPDMA C3CONTROL: I Mask */ /* ------------------------------- GPDMA_C3CONFIG ------------------------------- */ #define GPDMA_C3CONFIG_E_Pos 0 /*!< GPDMA C3CONFIG: E Position */ #define GPDMA_C3CONFIG_E_Msk (0x01UL << GPDMA_C3CONFIG_E_Pos) /*!< GPDMA C3CONFIG: E Mask */ #define GPDMA_C3CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C3CONFIG: SRCPERIPHERAL Position */ #define GPDMA_C3CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: SRCPERIPHERAL Mask */ #define GPDMA_C3CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C3CONFIG: DESTPERIPHERAL Position */ #define GPDMA_C3CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C3CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C3CONFIG: DESTPERIPHERAL Mask */ #define GPDMA_C3CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C3CONFIG: FLOWCNTRL Position */ #define GPDMA_C3CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C3CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C3CONFIG: FLOWCNTRL Mask */ #define GPDMA_C3CONFIG_IE_Pos 14 /*!< GPDMA C3CONFIG: IE Position */ #define GPDMA_C3CONFIG_IE_Msk (0x01UL << GPDMA_C3CONFIG_IE_Pos) /*!< GPDMA C3CONFIG: IE Mask */ #define GPDMA_C3CONFIG_ITC_Pos 15 /*!< GPDMA C3CONFIG: ITC Position */ #define GPDMA_C3CONFIG_ITC_Msk (0x01UL << GPDMA_C3CONFIG_ITC_Pos) /*!< GPDMA C3CONFIG: ITC Mask */ #define GPDMA_C3CONFIG_L_Pos 16 /*!< GPDMA C3CONFIG: L Position */ #define GPDMA_C3CONFIG_L_Msk (0x01UL << GPDMA_C3CONFIG_L_Pos) /*!< GPDMA C3CONFIG: L Mask */ #define GPDMA_C3CONFIG_A_Pos 17 /*!< GPDMA C3CONFIG: A Position */ #define GPDMA_C3CONFIG_A_Msk (0x01UL << GPDMA_C3CONFIG_A_Pos) /*!< GPDMA C3CONFIG: A Mask */ #define GPDMA_C3CONFIG_H_Pos 18 /*!< GPDMA C3CONFIG: H Position */ #define GPDMA_C3CONFIG_H_Msk (0x01UL << GPDMA_C3CONFIG_H_Pos) /*!< GPDMA C3CONFIG: H Mask */ /* ------------------------------- GPDMA_C4SRCADDR ------------------------------ */ #define GPDMA_C4SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C4SRCADDR: SRCADDR Position */ #define GPDMA_C4SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C4SRCADDR_SRCADDR_Pos) /*!< GPDMA C4SRCADDR: SRCADDR Mask */ /* ------------------------------ GPDMA_C4DESTADDR ------------------------------ */ #define GPDMA_C4DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C4DESTADDR: DESTADDR Position */ #define GPDMA_C4DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C4DESTADDR_DESTADDR_Pos) /*!< GPDMA C4DESTADDR: DESTADDR Mask */ /* --------------------------------- GPDMA_C4LLI -------------------------------- */ #define GPDMA_C4LLI_LM_Pos 0 /*!< GPDMA C4LLI: LM Position */ #define GPDMA_C4LLI_LM_Msk (0x01UL << GPDMA_C4LLI_LM_Pos) /*!< GPDMA C4LLI: LM Mask */ #define GPDMA_C4LLI_R_Pos 1 /*!< GPDMA C4LLI: R Position */ #define GPDMA_C4LLI_R_Msk (0x01UL << GPDMA_C4LLI_R_Pos) /*!< GPDMA C4LLI: R Mask */ #define GPDMA_C4LLI_LLI_Pos 2 /*!< GPDMA C4LLI: LLI Position */ #define GPDMA_C4LLI_LLI_Msk (0x3fffffffUL << GPDMA_C4LLI_LLI_Pos) /*!< GPDMA C4LLI: LLI Mask */ /* ------------------------------- GPDMA_C4CONTROL ------------------------------ */ #define GPDMA_C4CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C4CONTROL: TRANSFERSIZE Position */ #define GPDMA_C4CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C4CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C4CONTROL: TRANSFERSIZE Mask */ #define GPDMA_C4CONTROL_SBSIZE_Pos 12 /*!< GPDMA C4CONTROL: SBSIZE Position */ #define GPDMA_C4CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_SBSIZE_Pos) /*!< GPDMA C4CONTROL: SBSIZE Mask */ #define GPDMA_C4CONTROL_DBSIZE_Pos 15 /*!< GPDMA C4CONTROL: DBSIZE Position */ #define GPDMA_C4CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C4CONTROL_DBSIZE_Pos) /*!< GPDMA C4CONTROL: DBSIZE Mask */ #define GPDMA_C4CONTROL_SWIDTH_Pos 18 /*!< GPDMA C4CONTROL: SWIDTH Position */ #define GPDMA_C4CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_SWIDTH_Pos) /*!< GPDMA C4CONTROL: SWIDTH Mask */ #define GPDMA_C4CONTROL_DWIDTH_Pos 21 /*!< GPDMA C4CONTROL: DWIDTH Position */ #define GPDMA_C4CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C4CONTROL_DWIDTH_Pos) /*!< GPDMA C4CONTROL: DWIDTH Mask */ #define GPDMA_C4CONTROL_S_Pos 24 /*!< GPDMA C4CONTROL: S Position */ #define GPDMA_C4CONTROL_S_Msk (0x01UL << GPDMA_C4CONTROL_S_Pos) /*!< GPDMA C4CONTROL: S Mask */ #define GPDMA_C4CONTROL_D_Pos 25 /*!< GPDMA C4CONTROL: D Position */ #define GPDMA_C4CONTROL_D_Msk (0x01UL << GPDMA_C4CONTROL_D_Pos) /*!< GPDMA C4CONTROL: D Mask */ #define GPDMA_C4CONTROL_SI_Pos 26 /*!< GPDMA C4CONTROL: SI Position */ #define GPDMA_C4CONTROL_SI_Msk (0x01UL << GPDMA_C4CONTROL_SI_Pos) /*!< GPDMA C4CONTROL: SI Mask */ #define GPDMA_C4CONTROL_DI_Pos 27 /*!< GPDMA C4CONTROL: DI Position */ #define GPDMA_C4CONTROL_DI_Msk (0x01UL << GPDMA_C4CONTROL_DI_Pos) /*!< GPDMA C4CONTROL: DI Mask */ #define GPDMA_C4CONTROL_PROT1_Pos 28 /*!< GPDMA C4CONTROL: PROT1 Position */ #define GPDMA_C4CONTROL_PROT1_Msk (0x01UL << GPDMA_C4CONTROL_PROT1_Pos) /*!< GPDMA C4CONTROL: PROT1 Mask */ #define GPDMA_C4CONTROL_PROT2_Pos 29 /*!< GPDMA C4CONTROL: PROT2 Position */ #define GPDMA_C4CONTROL_PROT2_Msk (0x01UL << GPDMA_C4CONTROL_PROT2_Pos) /*!< GPDMA C4CONTROL: PROT2 Mask */ #define GPDMA_C4CONTROL_PROT3_Pos 30 /*!< GPDMA C4CONTROL: PROT3 Position */ #define GPDMA_C4CONTROL_PROT3_Msk (0x01UL << GPDMA_C4CONTROL_PROT3_Pos) /*!< GPDMA C4CONTROL: PROT3 Mask */ #define GPDMA_C4CONTROL_I_Pos 31 /*!< GPDMA C4CONTROL: I Position */ #define GPDMA_C4CONTROL_I_Msk (0x01UL << GPDMA_C4CONTROL_I_Pos) /*!< GPDMA C4CONTROL: I Mask */ /* ------------------------------- GPDMA_C4CONFIG ------------------------------- */ #define GPDMA_C4CONFIG_E_Pos 0 /*!< GPDMA C4CONFIG: E Position */ #define GPDMA_C4CONFIG_E_Msk (0x01UL << GPDMA_C4CONFIG_E_Pos) /*!< GPDMA C4CONFIG: E Mask */ #define GPDMA_C4CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C4CONFIG: SRCPERIPHERAL Position */ #define GPDMA_C4CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: SRCPERIPHERAL Mask */ #define GPDMA_C4CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C4CONFIG: DESTPERIPHERAL Position */ #define GPDMA_C4CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C4CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C4CONFIG: DESTPERIPHERAL Mask */ #define GPDMA_C4CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C4CONFIG: FLOWCNTRL Position */ #define GPDMA_C4CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C4CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C4CONFIG: FLOWCNTRL Mask */ #define GPDMA_C4CONFIG_IE_Pos 14 /*!< GPDMA C4CONFIG: IE Position */ #define GPDMA_C4CONFIG_IE_Msk (0x01UL << GPDMA_C4CONFIG_IE_Pos) /*!< GPDMA C4CONFIG: IE Mask */ #define GPDMA_C4CONFIG_ITC_Pos 15 /*!< GPDMA C4CONFIG: ITC Position */ #define GPDMA_C4CONFIG_ITC_Msk (0x01UL << GPDMA_C4CONFIG_ITC_Pos) /*!< GPDMA C4CONFIG: ITC Mask */ #define GPDMA_C4CONFIG_L_Pos 16 /*!< GPDMA C4CONFIG: L Position */ #define GPDMA_C4CONFIG_L_Msk (0x01UL << GPDMA_C4CONFIG_L_Pos) /*!< GPDMA C4CONFIG: L Mask */ #define GPDMA_C4CONFIG_A_Pos 17 /*!< GPDMA C4CONFIG: A Position */ #define GPDMA_C4CONFIG_A_Msk (0x01UL << GPDMA_C4CONFIG_A_Pos) /*!< GPDMA C4CONFIG: A Mask */ #define GPDMA_C4CONFIG_H_Pos 18 /*!< GPDMA C4CONFIG: H Position */ #define GPDMA_C4CONFIG_H_Msk (0x01UL << GPDMA_C4CONFIG_H_Pos) /*!< GPDMA C4CONFIG: H Mask */ /* ------------------------------- GPDMA_C5SRCADDR ------------------------------ */ #define GPDMA_C5SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C5SRCADDR: SRCADDR Position */ #define GPDMA_C5SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C5SRCADDR_SRCADDR_Pos) /*!< GPDMA C5SRCADDR: SRCADDR Mask */ /* ------------------------------ GPDMA_C5DESTADDR ------------------------------ */ #define GPDMA_C5DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C5DESTADDR: DESTADDR Position */ #define GPDMA_C5DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C5DESTADDR_DESTADDR_Pos) /*!< GPDMA C5DESTADDR: DESTADDR Mask */ /* --------------------------------- GPDMA_C5LLI -------------------------------- */ #define GPDMA_C5LLI_LM_Pos 0 /*!< GPDMA C5LLI: LM Position */ #define GPDMA_C5LLI_LM_Msk (0x01UL << GPDMA_C5LLI_LM_Pos) /*!< GPDMA C5LLI: LM Mask */ #define GPDMA_C5LLI_R_Pos 1 /*!< GPDMA C5LLI: R Position */ #define GPDMA_C5LLI_R_Msk (0x01UL << GPDMA_C5LLI_R_Pos) /*!< GPDMA C5LLI: R Mask */ #define GPDMA_C5LLI_LLI_Pos 2 /*!< GPDMA C5LLI: LLI Position */ #define GPDMA_C5LLI_LLI_Msk (0x3fffffffUL << GPDMA_C5LLI_LLI_Pos) /*!< GPDMA C5LLI: LLI Mask */ /* ------------------------------- GPDMA_C5CONTROL ------------------------------ */ #define GPDMA_C5CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C5CONTROL: TRANSFERSIZE Position */ #define GPDMA_C5CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C5CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C5CONTROL: TRANSFERSIZE Mask */ #define GPDMA_C5CONTROL_SBSIZE_Pos 12 /*!< GPDMA C5CONTROL: SBSIZE Position */ #define GPDMA_C5CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_SBSIZE_Pos) /*!< GPDMA C5CONTROL: SBSIZE Mask */ #define GPDMA_C5CONTROL_DBSIZE_Pos 15 /*!< GPDMA C5CONTROL: DBSIZE Position */ #define GPDMA_C5CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C5CONTROL_DBSIZE_Pos) /*!< GPDMA C5CONTROL: DBSIZE Mask */ #define GPDMA_C5CONTROL_SWIDTH_Pos 18 /*!< GPDMA C5CONTROL: SWIDTH Position */ #define GPDMA_C5CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_SWIDTH_Pos) /*!< GPDMA C5CONTROL: SWIDTH Mask */ #define GPDMA_C5CONTROL_DWIDTH_Pos 21 /*!< GPDMA C5CONTROL: DWIDTH Position */ #define GPDMA_C5CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C5CONTROL_DWIDTH_Pos) /*!< GPDMA C5CONTROL: DWIDTH Mask */ #define GPDMA_C5CONTROL_S_Pos 24 /*!< GPDMA C5CONTROL: S Position */ #define GPDMA_C5CONTROL_S_Msk (0x01UL << GPDMA_C5CONTROL_S_Pos) /*!< GPDMA C5CONTROL: S Mask */ #define GPDMA_C5CONTROL_D_Pos 25 /*!< GPDMA C5CONTROL: D Position */ #define GPDMA_C5CONTROL_D_Msk (0x01UL << GPDMA_C5CONTROL_D_Pos) /*!< GPDMA C5CONTROL: D Mask */ #define GPDMA_C5CONTROL_SI_Pos 26 /*!< GPDMA C5CONTROL: SI Position */ #define GPDMA_C5CONTROL_SI_Msk (0x01UL << GPDMA_C5CONTROL_SI_Pos) /*!< GPDMA C5CONTROL: SI Mask */ #define GPDMA_C5CONTROL_DI_Pos 27 /*!< GPDMA C5CONTROL: DI Position */ #define GPDMA_C5CONTROL_DI_Msk (0x01UL << GPDMA_C5CONTROL_DI_Pos) /*!< GPDMA C5CONTROL: DI Mask */ #define GPDMA_C5CONTROL_PROT1_Pos 28 /*!< GPDMA C5CONTROL: PROT1 Position */ #define GPDMA_C5CONTROL_PROT1_Msk (0x01UL << GPDMA_C5CONTROL_PROT1_Pos) /*!< GPDMA C5CONTROL: PROT1 Mask */ #define GPDMA_C5CONTROL_PROT2_Pos 29 /*!< GPDMA C5CONTROL: PROT2 Position */ #define GPDMA_C5CONTROL_PROT2_Msk (0x01UL << GPDMA_C5CONTROL_PROT2_Pos) /*!< GPDMA C5CONTROL: PROT2 Mask */ #define GPDMA_C5CONTROL_PROT3_Pos 30 /*!< GPDMA C5CONTROL: PROT3 Position */ #define GPDMA_C5CONTROL_PROT3_Msk (0x01UL << GPDMA_C5CONTROL_PROT3_Pos) /*!< GPDMA C5CONTROL: PROT3 Mask */ #define GPDMA_C5CONTROL_I_Pos 31 /*!< GPDMA C5CONTROL: I Position */ #define GPDMA_C5CONTROL_I_Msk (0x01UL << GPDMA_C5CONTROL_I_Pos) /*!< GPDMA C5CONTROL: I Mask */ /* ------------------------------- GPDMA_C5CONFIG ------------------------------- */ #define GPDMA_C5CONFIG_E_Pos 0 /*!< GPDMA C5CONFIG: E Position */ #define GPDMA_C5CONFIG_E_Msk (0x01UL << GPDMA_C5CONFIG_E_Pos) /*!< GPDMA C5CONFIG: E Mask */ #define GPDMA_C5CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C5CONFIG: SRCPERIPHERAL Position */ #define GPDMA_C5CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: SRCPERIPHERAL Mask */ #define GPDMA_C5CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C5CONFIG: DESTPERIPHERAL Position */ #define GPDMA_C5CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C5CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C5CONFIG: DESTPERIPHERAL Mask */ #define GPDMA_C5CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C5CONFIG: FLOWCNTRL Position */ #define GPDMA_C5CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C5CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C5CONFIG: FLOWCNTRL Mask */ #define GPDMA_C5CONFIG_IE_Pos 14 /*!< GPDMA C5CONFIG: IE Position */ #define GPDMA_C5CONFIG_IE_Msk (0x01UL << GPDMA_C5CONFIG_IE_Pos) /*!< GPDMA C5CONFIG: IE Mask */ #define GPDMA_C5CONFIG_ITC_Pos 15 /*!< GPDMA C5CONFIG: ITC Position */ #define GPDMA_C5CONFIG_ITC_Msk (0x01UL << GPDMA_C5CONFIG_ITC_Pos) /*!< GPDMA C5CONFIG: ITC Mask */ #define GPDMA_C5CONFIG_L_Pos 16 /*!< GPDMA C5CONFIG: L Position */ #define GPDMA_C5CONFIG_L_Msk (0x01UL << GPDMA_C5CONFIG_L_Pos) /*!< GPDMA C5CONFIG: L Mask */ #define GPDMA_C5CONFIG_A_Pos 17 /*!< GPDMA C5CONFIG: A Position */ #define GPDMA_C5CONFIG_A_Msk (0x01UL << GPDMA_C5CONFIG_A_Pos) /*!< GPDMA C5CONFIG: A Mask */ #define GPDMA_C5CONFIG_H_Pos 18 /*!< GPDMA C5CONFIG: H Position */ #define GPDMA_C5CONFIG_H_Msk (0x01UL << GPDMA_C5CONFIG_H_Pos) /*!< GPDMA C5CONFIG: H Mask */ /* ------------------------------- GPDMA_C6SRCADDR ------------------------------ */ #define GPDMA_C6SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C6SRCADDR: SRCADDR Position */ #define GPDMA_C6SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C6SRCADDR_SRCADDR_Pos) /*!< GPDMA C6SRCADDR: SRCADDR Mask */ /* ------------------------------ GPDMA_C6DESTADDR ------------------------------ */ #define GPDMA_C6DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C6DESTADDR: DESTADDR Position */ #define GPDMA_C6DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C6DESTADDR_DESTADDR_Pos) /*!< GPDMA C6DESTADDR: DESTADDR Mask */ /* --------------------------------- GPDMA_C6LLI -------------------------------- */ #define GPDMA_C6LLI_LM_Pos 0 /*!< GPDMA C6LLI: LM Position */ #define GPDMA_C6LLI_LM_Msk (0x01UL << GPDMA_C6LLI_LM_Pos) /*!< GPDMA C6LLI: LM Mask */ #define GPDMA_C6LLI_R_Pos 1 /*!< GPDMA C6LLI: R Position */ #define GPDMA_C6LLI_R_Msk (0x01UL << GPDMA_C6LLI_R_Pos) /*!< GPDMA C6LLI: R Mask */ #define GPDMA_C6LLI_LLI_Pos 2 /*!< GPDMA C6LLI: LLI Position */ #define GPDMA_C6LLI_LLI_Msk (0x3fffffffUL << GPDMA_C6LLI_LLI_Pos) /*!< GPDMA C6LLI: LLI Mask */ /* ------------------------------- GPDMA_C6CONTROL ------------------------------ */ #define GPDMA_C6CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C6CONTROL: TRANSFERSIZE Position */ #define GPDMA_C6CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C6CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C6CONTROL: TRANSFERSIZE Mask */ #define GPDMA_C6CONTROL_SBSIZE_Pos 12 /*!< GPDMA C6CONTROL: SBSIZE Position */ #define GPDMA_C6CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_SBSIZE_Pos) /*!< GPDMA C6CONTROL: SBSIZE Mask */ #define GPDMA_C6CONTROL_DBSIZE_Pos 15 /*!< GPDMA C6CONTROL: DBSIZE Position */ #define GPDMA_C6CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C6CONTROL_DBSIZE_Pos) /*!< GPDMA C6CONTROL: DBSIZE Mask */ #define GPDMA_C6CONTROL_SWIDTH_Pos 18 /*!< GPDMA C6CONTROL: SWIDTH Position */ #define GPDMA_C6CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_SWIDTH_Pos) /*!< GPDMA C6CONTROL: SWIDTH Mask */ #define GPDMA_C6CONTROL_DWIDTH_Pos 21 /*!< GPDMA C6CONTROL: DWIDTH Position */ #define GPDMA_C6CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C6CONTROL_DWIDTH_Pos) /*!< GPDMA C6CONTROL: DWIDTH Mask */ #define GPDMA_C6CONTROL_S_Pos 24 /*!< GPDMA C6CONTROL: S Position */ #define GPDMA_C6CONTROL_S_Msk (0x01UL << GPDMA_C6CONTROL_S_Pos) /*!< GPDMA C6CONTROL: S Mask */ #define GPDMA_C6CONTROL_D_Pos 25 /*!< GPDMA C6CONTROL: D Position */ #define GPDMA_C6CONTROL_D_Msk (0x01UL << GPDMA_C6CONTROL_D_Pos) /*!< GPDMA C6CONTROL: D Mask */ #define GPDMA_C6CONTROL_SI_Pos 26 /*!< GPDMA C6CONTROL: SI Position */ #define GPDMA_C6CONTROL_SI_Msk (0x01UL << GPDMA_C6CONTROL_SI_Pos) /*!< GPDMA C6CONTROL: SI Mask */ #define GPDMA_C6CONTROL_DI_Pos 27 /*!< GPDMA C6CONTROL: DI Position */ #define GPDMA_C6CONTROL_DI_Msk (0x01UL << GPDMA_C6CONTROL_DI_Pos) /*!< GPDMA C6CONTROL: DI Mask */ #define GPDMA_C6CONTROL_PROT1_Pos 28 /*!< GPDMA C6CONTROL: PROT1 Position */ #define GPDMA_C6CONTROL_PROT1_Msk (0x01UL << GPDMA_C6CONTROL_PROT1_Pos) /*!< GPDMA C6CONTROL: PROT1 Mask */ #define GPDMA_C6CONTROL_PROT2_Pos 29 /*!< GPDMA C6CONTROL: PROT2 Position */ #define GPDMA_C6CONTROL_PROT2_Msk (0x01UL << GPDMA_C6CONTROL_PROT2_Pos) /*!< GPDMA C6CONTROL: PROT2 Mask */ #define GPDMA_C6CONTROL_PROT3_Pos 30 /*!< GPDMA C6CONTROL: PROT3 Position */ #define GPDMA_C6CONTROL_PROT3_Msk (0x01UL << GPDMA_C6CONTROL_PROT3_Pos) /*!< GPDMA C6CONTROL: PROT3 Mask */ #define GPDMA_C6CONTROL_I_Pos 31 /*!< GPDMA C6CONTROL: I Position */ #define GPDMA_C6CONTROL_I_Msk (0x01UL << GPDMA_C6CONTROL_I_Pos) /*!< GPDMA C6CONTROL: I Mask */ /* ------------------------------- GPDMA_C6CONFIG ------------------------------- */ #define GPDMA_C6CONFIG_E_Pos 0 /*!< GPDMA C6CONFIG: E Position */ #define GPDMA_C6CONFIG_E_Msk (0x01UL << GPDMA_C6CONFIG_E_Pos) /*!< GPDMA C6CONFIG: E Mask */ #define GPDMA_C6CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C6CONFIG: SRCPERIPHERAL Position */ #define GPDMA_C6CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: SRCPERIPHERAL Mask */ #define GPDMA_C6CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C6CONFIG: DESTPERIPHERAL Position */ #define GPDMA_C6CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C6CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C6CONFIG: DESTPERIPHERAL Mask */ #define GPDMA_C6CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C6CONFIG: FLOWCNTRL Position */ #define GPDMA_C6CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C6CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C6CONFIG: FLOWCNTRL Mask */ #define GPDMA_C6CONFIG_IE_Pos 14 /*!< GPDMA C6CONFIG: IE Position */ #define GPDMA_C6CONFIG_IE_Msk (0x01UL << GPDMA_C6CONFIG_IE_Pos) /*!< GPDMA C6CONFIG: IE Mask */ #define GPDMA_C6CONFIG_ITC_Pos 15 /*!< GPDMA C6CONFIG: ITC Position */ #define GPDMA_C6CONFIG_ITC_Msk (0x01UL << GPDMA_C6CONFIG_ITC_Pos) /*!< GPDMA C6CONFIG: ITC Mask */ #define GPDMA_C6CONFIG_L_Pos 16 /*!< GPDMA C6CONFIG: L Position */ #define GPDMA_C6CONFIG_L_Msk (0x01UL << GPDMA_C6CONFIG_L_Pos) /*!< GPDMA C6CONFIG: L Mask */ #define GPDMA_C6CONFIG_A_Pos 17 /*!< GPDMA C6CONFIG: A Position */ #define GPDMA_C6CONFIG_A_Msk (0x01UL << GPDMA_C6CONFIG_A_Pos) /*!< GPDMA C6CONFIG: A Mask */ #define GPDMA_C6CONFIG_H_Pos 18 /*!< GPDMA C6CONFIG: H Position */ #define GPDMA_C6CONFIG_H_Msk (0x01UL << GPDMA_C6CONFIG_H_Pos) /*!< GPDMA C6CONFIG: H Mask */ /* ------------------------------- GPDMA_C7SRCADDR ------------------------------ */ #define GPDMA_C7SRCADDR_SRCADDR_Pos 0 /*!< GPDMA C7SRCADDR: SRCADDR Position */ #define GPDMA_C7SRCADDR_SRCADDR_Msk (0xffffffffUL << GPDMA_C7SRCADDR_SRCADDR_Pos) /*!< GPDMA C7SRCADDR: SRCADDR Mask */ /* ------------------------------ GPDMA_C7DESTADDR ------------------------------ */ #define GPDMA_C7DESTADDR_DESTADDR_Pos 0 /*!< GPDMA C7DESTADDR: DESTADDR Position */ #define GPDMA_C7DESTADDR_DESTADDR_Msk (0xffffffffUL << GPDMA_C7DESTADDR_DESTADDR_Pos) /*!< GPDMA C7DESTADDR: DESTADDR Mask */ /* --------------------------------- GPDMA_C7LLI -------------------------------- */ #define GPDMA_C7LLI_LM_Pos 0 /*!< GPDMA C7LLI: LM Position */ #define GPDMA_C7LLI_LM_Msk (0x01UL << GPDMA_C7LLI_LM_Pos) /*!< GPDMA C7LLI: LM Mask */ #define GPDMA_C7LLI_R_Pos 1 /*!< GPDMA C7LLI: R Position */ #define GPDMA_C7LLI_R_Msk (0x01UL << GPDMA_C7LLI_R_Pos) /*!< GPDMA C7LLI: R Mask */ #define GPDMA_C7LLI_LLI_Pos 2 /*!< GPDMA C7LLI: LLI Position */ #define GPDMA_C7LLI_LLI_Msk (0x3fffffffUL << GPDMA_C7LLI_LLI_Pos) /*!< GPDMA C7LLI: LLI Mask */ /* ------------------------------- GPDMA_C7CONTROL ------------------------------ */ #define GPDMA_C7CONTROL_TRANSFERSIZE_Pos 0 /*!< GPDMA C7CONTROL: TRANSFERSIZE Position */ #define GPDMA_C7CONTROL_TRANSFERSIZE_Msk (0x00000fffUL << GPDMA_C7CONTROL_TRANSFERSIZE_Pos) /*!< GPDMA C7CONTROL: TRANSFERSIZE Mask */ #define GPDMA_C7CONTROL_SBSIZE_Pos 12 /*!< GPDMA C7CONTROL: SBSIZE Position */ #define GPDMA_C7CONTROL_SBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_SBSIZE_Pos) /*!< GPDMA C7CONTROL: SBSIZE Mask */ #define GPDMA_C7CONTROL_DBSIZE_Pos 15 /*!< GPDMA C7CONTROL: DBSIZE Position */ #define GPDMA_C7CONTROL_DBSIZE_Msk (0x07UL << GPDMA_C7CONTROL_DBSIZE_Pos) /*!< GPDMA C7CONTROL: DBSIZE Mask */ #define GPDMA_C7CONTROL_SWIDTH_Pos 18 /*!< GPDMA C7CONTROL: SWIDTH Position */ #define GPDMA_C7CONTROL_SWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_SWIDTH_Pos) /*!< GPDMA C7CONTROL: SWIDTH Mask */ #define GPDMA_C7CONTROL_DWIDTH_Pos 21 /*!< GPDMA C7CONTROL: DWIDTH Position */ #define GPDMA_C7CONTROL_DWIDTH_Msk (0x07UL << GPDMA_C7CONTROL_DWIDTH_Pos) /*!< GPDMA C7CONTROL: DWIDTH Mask */ #define GPDMA_C7CONTROL_S_Pos 24 /*!< GPDMA C7CONTROL: S Position */ #define GPDMA_C7CONTROL_S_Msk (0x01UL << GPDMA_C7CONTROL_S_Pos) /*!< GPDMA C7CONTROL: S Mask */ #define GPDMA_C7CONTROL_D_Pos 25 /*!< GPDMA C7CONTROL: D Position */ #define GPDMA_C7CONTROL_D_Msk (0x01UL << GPDMA_C7CONTROL_D_Pos) /*!< GPDMA C7CONTROL: D Mask */ #define GPDMA_C7CONTROL_SI_Pos 26 /*!< GPDMA C7CONTROL: SI Position */ #define GPDMA_C7CONTROL_SI_Msk (0x01UL << GPDMA_C7CONTROL_SI_Pos) /*!< GPDMA C7CONTROL: SI Mask */ #define GPDMA_C7CONTROL_DI_Pos 27 /*!< GPDMA C7CONTROL: DI Position */ #define GPDMA_C7CONTROL_DI_Msk (0x01UL << GPDMA_C7CONTROL_DI_Pos) /*!< GPDMA C7CONTROL: DI Mask */ #define GPDMA_C7CONTROL_PROT1_Pos 28 /*!< GPDMA C7CONTROL: PROT1 Position */ #define GPDMA_C7CONTROL_PROT1_Msk (0x01UL << GPDMA_C7CONTROL_PROT1_Pos) /*!< GPDMA C7CONTROL: PROT1 Mask */ #define GPDMA_C7CONTROL_PROT2_Pos 29 /*!< GPDMA C7CONTROL: PROT2 Position */ #define GPDMA_C7CONTROL_PROT2_Msk (0x01UL << GPDMA_C7CONTROL_PROT2_Pos) /*!< GPDMA C7CONTROL: PROT2 Mask */ #define GPDMA_C7CONTROL_PROT3_Pos 30 /*!< GPDMA C7CONTROL: PROT3 Position */ #define GPDMA_C7CONTROL_PROT3_Msk (0x01UL << GPDMA_C7CONTROL_PROT3_Pos) /*!< GPDMA C7CONTROL: PROT3 Mask */ #define GPDMA_C7CONTROL_I_Pos 31 /*!< GPDMA C7CONTROL: I Position */ #define GPDMA_C7CONTROL_I_Msk (0x01UL << GPDMA_C7CONTROL_I_Pos) /*!< GPDMA C7CONTROL: I Mask */ /* ------------------------------- GPDMA_C7CONFIG ------------------------------- */ #define GPDMA_C7CONFIG_E_Pos 0 /*!< GPDMA C7CONFIG: E Position */ #define GPDMA_C7CONFIG_E_Msk (0x01UL << GPDMA_C7CONFIG_E_Pos) /*!< GPDMA C7CONFIG: E Mask */ #define GPDMA_C7CONFIG_SRCPERIPHERAL_Pos 1 /*!< GPDMA C7CONFIG: SRCPERIPHERAL Position */ #define GPDMA_C7CONFIG_SRCPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_SRCPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: SRCPERIPHERAL Mask */ #define GPDMA_C7CONFIG_DESTPERIPHERAL_Pos 6 /*!< GPDMA C7CONFIG: DESTPERIPHERAL Position */ #define GPDMA_C7CONFIG_DESTPERIPHERAL_Msk (0x1fUL << GPDMA_C7CONFIG_DESTPERIPHERAL_Pos) /*!< GPDMA C7CONFIG: DESTPERIPHERAL Mask */ #define GPDMA_C7CONFIG_FLOWCNTRL_Pos 11 /*!< GPDMA C7CONFIG: FLOWCNTRL Position */ #define GPDMA_C7CONFIG_FLOWCNTRL_Msk (0x07UL << GPDMA_C7CONFIG_FLOWCNTRL_Pos) /*!< GPDMA C7CONFIG: FLOWCNTRL Mask */ #define GPDMA_C7CONFIG_IE_Pos 14 /*!< GPDMA C7CONFIG: IE Position */ #define GPDMA_C7CONFIG_IE_Msk (0x01UL << GPDMA_C7CONFIG_IE_Pos) /*!< GPDMA C7CONFIG: IE Mask */ #define GPDMA_C7CONFIG_ITC_Pos 15 /*!< GPDMA C7CONFIG: ITC Position */ #define GPDMA_C7CONFIG_ITC_Msk (0x01UL << GPDMA_C7CONFIG_ITC_Pos) /*!< GPDMA C7CONFIG: ITC Mask */ #define GPDMA_C7CONFIG_L_Pos 16 /*!< GPDMA C7CONFIG: L Position */ #define GPDMA_C7CONFIG_L_Msk (0x01UL << GPDMA_C7CONFIG_L_Pos) /*!< GPDMA C7CONFIG: L Mask */ #define GPDMA_C7CONFIG_A_Pos 17 /*!< GPDMA C7CONFIG: A Position */ #define GPDMA_C7CONFIG_A_Msk (0x01UL << GPDMA_C7CONFIG_A_Pos) /*!< GPDMA C7CONFIG: A Mask */ #define GPDMA_C7CONFIG_H_Pos 18 /*!< GPDMA C7CONFIG: H Position */ #define GPDMA_C7CONFIG_H_Msk (0x01UL << GPDMA_C7CONFIG_H_Pos) /*!< GPDMA C7CONFIG: H Mask */ /* ================================================================================ */ /* ================ struct 'SPIFI' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- SPIFI_CTRL --------------------------------- */ #define SPIFI_CTRL_TIMEOUT_Pos 0 /*!< SPIFI CTRL: TIMEOUT Position */ #define SPIFI_CTRL_TIMEOUT_Msk (0x0000ffffUL << SPIFI_CTRL_TIMEOUT_Pos) /*!< SPIFI CTRL: TIMEOUT Mask */ #define SPIFI_CTRL_CSHIGH_Pos 16 /*!< SPIFI CTRL: CSHIGH Position */ #define SPIFI_CTRL_CSHIGH_Msk (0x0fUL << SPIFI_CTRL_CSHIGH_Pos) /*!< SPIFI CTRL: CSHIGH Mask */ #define SPIFI_CTRL_D_PRFTCH_DIS_Pos 21 /*!< SPIFI CTRL: D_PRFTCH_DIS Position */ #define SPIFI_CTRL_D_PRFTCH_DIS_Msk (0x01UL << SPIFI_CTRL_D_PRFTCH_DIS_Pos) /*!< SPIFI CTRL: D_PRFTCH_DIS Mask */ #define SPIFI_CTRL_INTEN_Pos 22 /*!< SPIFI CTRL: INTEN Position */ #define SPIFI_CTRL_INTEN_Msk (0x01UL << SPIFI_CTRL_INTEN_Pos) /*!< SPIFI CTRL: INTEN Mask */ #define SPIFI_CTRL_MODE3_Pos 23 /*!< SPIFI CTRL: MODE3 Position */ #define SPIFI_CTRL_MODE3_Msk (0x01UL << SPIFI_CTRL_MODE3_Pos) /*!< SPIFI CTRL: MODE3 Mask */ #define SPIFI_CTRL_PRFTCH_DIS_Pos 27 /*!< SPIFI CTRL: PRFTCH_DIS Position */ #define SPIFI_CTRL_PRFTCH_DIS_Msk (0x01UL << SPIFI_CTRL_PRFTCH_DIS_Pos) /*!< SPIFI CTRL: PRFTCH_DIS Mask */ #define SPIFI_CTRL_DUAL_Pos 28 /*!< SPIFI CTRL: DUAL Position */ #define SPIFI_CTRL_DUAL_Msk (0x01UL << SPIFI_CTRL_DUAL_Pos) /*!< SPIFI CTRL: DUAL Mask */ #define SPIFI_CTRL_RFCLK_Pos 29 /*!< SPIFI CTRL: RFCLK Position */ #define SPIFI_CTRL_RFCLK_Msk (0x01UL << SPIFI_CTRL_RFCLK_Pos) /*!< SPIFI CTRL: RFCLK Mask */ #define SPIFI_CTRL_FBCLK_Pos 30 /*!< SPIFI CTRL: FBCLK Position */ #define SPIFI_CTRL_FBCLK_Msk (0x01UL << SPIFI_CTRL_FBCLK_Pos) /*!< SPIFI CTRL: FBCLK Mask */ #define SPIFI_CTRL_DMAEN_Pos 31 /*!< SPIFI CTRL: DMAEN Position */ #define SPIFI_CTRL_DMAEN_Msk (0x01UL << SPIFI_CTRL_DMAEN_Pos) /*!< SPIFI CTRL: DMAEN Mask */ /* ---------------------------------- SPIFI_CMD --------------------------------- */ #define SPIFI_CMD_DATALEN_Pos 0 /*!< SPIFI CMD: DATALEN Position */ #define SPIFI_CMD_DATALEN_Msk (0x00003fffUL << SPIFI_CMD_DATALEN_Pos) /*!< SPIFI CMD: DATALEN Mask */ #define SPIFI_CMD_POLL_Pos 14 /*!< SPIFI CMD: POLL Position */ #define SPIFI_CMD_POLL_Msk (0x01UL << SPIFI_CMD_POLL_Pos) /*!< SPIFI CMD: POLL Mask */ #define SPIFI_CMD_DOUT_Pos 15 /*!< SPIFI CMD: DOUT Position */ #define SPIFI_CMD_DOUT_Msk (0x01UL << SPIFI_CMD_DOUT_Pos) /*!< SPIFI CMD: DOUT Mask */ #define SPIFI_CMD_INTLEN_Pos 16 /*!< SPIFI CMD: INTLEN Position */ #define SPIFI_CMD_INTLEN_Msk (0x07UL << SPIFI_CMD_INTLEN_Pos) /*!< SPIFI CMD: INTLEN Mask */ #define SPIFI_CMD_FIELDFORM_Pos 19 /*!< SPIFI CMD: FIELDFORM Position */ #define SPIFI_CMD_FIELDFORM_Msk (0x03UL << SPIFI_CMD_FIELDFORM_Pos) /*!< SPIFI CMD: FIELDFORM Mask */ #define SPIFI_CMD_FRAMEFORM_Pos 21 /*!< SPIFI CMD: FRAMEFORM Position */ #define SPIFI_CMD_FRAMEFORM_Msk (0x07UL << SPIFI_CMD_FRAMEFORM_Pos) /*!< SPIFI CMD: FRAMEFORM Mask */ #define SPIFI_CMD_OPCODE_Pos 24 /*!< SPIFI CMD: OPCODE Position */ #define SPIFI_CMD_OPCODE_Msk (0x000000ffUL << SPIFI_CMD_OPCODE_Pos) /*!< SPIFI CMD: OPCODE Mask */ /* --------------------------------- SPIFI_ADDR --------------------------------- */ #define SPIFI_ADDR_ADDRESS_Pos 0 /*!< SPIFI ADDR: ADDRESS Position */ #define SPIFI_ADDR_ADDRESS_Msk (0xffffffffUL << SPIFI_ADDR_ADDRESS_Pos) /*!< SPIFI ADDR: ADDRESS Mask */ /* --------------------------------- SPIFI_IDATA -------------------------------- */ #define SPIFI_IDATA_IDATA_Pos 0 /*!< SPIFI IDATA: IDATA Position */ #define SPIFI_IDATA_IDATA_Msk (0xffffffffUL << SPIFI_IDATA_IDATA_Pos) /*!< SPIFI IDATA: IDATA Mask */ /* -------------------------------- SPIFI_CLIMIT -------------------------------- */ #define SPIFI_CLIMIT_CLIMIT_Pos 0 /*!< SPIFI CLIMIT: CLIMIT Position */ #define SPIFI_CLIMIT_CLIMIT_Msk (0xffffffffUL << SPIFI_CLIMIT_CLIMIT_Pos) /*!< SPIFI CLIMIT: CLIMIT Mask */ /* --------------------------------- SPIFI_DATA --------------------------------- */ #define SPIFI_DATA_DATA_Pos 0 /*!< SPIFI DATA: DATA Position */ #define SPIFI_DATA_DATA_Msk (0xffffffffUL << SPIFI_DATA_DATA_Pos) /*!< SPIFI DATA: DATA Mask */ /* --------------------------------- SPIFI_MCMD --------------------------------- */ #define SPIFI_MCMD_POLL_Pos 14 /*!< SPIFI MCMD: POLL Position */ #define SPIFI_MCMD_POLL_Msk (0x01UL << SPIFI_MCMD_POLL_Pos) /*!< SPIFI MCMD: POLL Mask */ #define SPIFI_MCMD_DOUT_Pos 15 /*!< SPIFI MCMD: DOUT Position */ #define SPIFI_MCMD_DOUT_Msk (0x01UL << SPIFI_MCMD_DOUT_Pos) /*!< SPIFI MCMD: DOUT Mask */ #define SPIFI_MCMD_INTLEN_Pos 16 /*!< SPIFI MCMD: INTLEN Position */ #define SPIFI_MCMD_INTLEN_Msk (0x07UL << SPIFI_MCMD_INTLEN_Pos) /*!< SPIFI MCMD: INTLEN Mask */ #define SPIFI_MCMD_FIELDFORM_Pos 19 /*!< SPIFI MCMD: FIELDFORM Position */ #define SPIFI_MCMD_FIELDFORM_Msk (0x03UL << SPIFI_MCMD_FIELDFORM_Pos) /*!< SPIFI MCMD: FIELDFORM Mask */ #define SPIFI_MCMD_FRAMEFORM_Pos 21 /*!< SPIFI MCMD: FRAMEFORM Position */ #define SPIFI_MCMD_FRAMEFORM_Msk (0x07UL << SPIFI_MCMD_FRAMEFORM_Pos) /*!< SPIFI MCMD: FRAMEFORM Mask */ #define SPIFI_MCMD_OPCODE_Pos 24 /*!< SPIFI MCMD: OPCODE Position */ #define SPIFI_MCMD_OPCODE_Msk (0x000000ffUL << SPIFI_MCMD_OPCODE_Pos) /*!< SPIFI MCMD: OPCODE Mask */ /* --------------------------------- SPIFI_STAT --------------------------------- */ #define SPIFI_STAT_MCINIT_Pos 0 /*!< SPIFI STAT: MCINIT Position */ #define SPIFI_STAT_MCINIT_Msk (0x01UL << SPIFI_STAT_MCINIT_Pos) /*!< SPIFI STAT: MCINIT Mask */ #define SPIFI_STAT_CMD_Pos 1 /*!< SPIFI STAT: CMD Position */ #define SPIFI_STAT_CMD_Msk (0x01UL << SPIFI_STAT_CMD_Pos) /*!< SPIFI STAT: CMD Mask */ #define SPIFI_STAT_RESET_Pos 4 /*!< SPIFI STAT: RESET Position */ #define SPIFI_STAT_RESET_Msk (0x01UL << SPIFI_STAT_RESET_Pos) /*!< SPIFI STAT: RESET Mask */ #define SPIFI_STAT_INTRQ_Pos 5 /*!< SPIFI STAT: INTRQ Position */ #define SPIFI_STAT_INTRQ_Msk (0x01UL << SPIFI_STAT_INTRQ_Pos) /*!< SPIFI STAT: INTRQ Mask */ #define SPIFI_STAT_VERSION_Pos 24 /*!< SPIFI STAT: VERSION Position */ #define SPIFI_STAT_VERSION_Msk (0x000000ffUL << SPIFI_STAT_VERSION_Pos) /*!< SPIFI STAT: VERSION Mask */ /* ================================================================================ */ /* ================ struct 'SDMMC' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- SDMMC_CTRL --------------------------------- */ #define SDMMC_CTRL_CONTROLLER_RESET_Pos 0 /*!< SDMMC CTRL: CONTROLLER_RESET Position */ #define SDMMC_CTRL_CONTROLLER_RESET_Msk (0x01UL << SDMMC_CTRL_CONTROLLER_RESET_Pos) /*!< SDMMC CTRL: CONTROLLER_RESET Mask */ #define SDMMC_CTRL_FIFO_RESET_Pos 1 /*!< SDMMC CTRL: FIFO_RESET Position */ #define SDMMC_CTRL_FIFO_RESET_Msk (0x01UL << SDMMC_CTRL_FIFO_RESET_Pos) /*!< SDMMC CTRL: FIFO_RESET Mask */ #define SDMMC_CTRL_DMA_RESET_Pos 2 /*!< SDMMC CTRL: DMA_RESET Position */ #define SDMMC_CTRL_DMA_RESET_Msk (0x01UL << SDMMC_CTRL_DMA_RESET_Pos) /*!< SDMMC CTRL: DMA_RESET Mask */ #define SDMMC_CTRL_INT_ENABLE_Pos 4 /*!< SDMMC CTRL: INT_ENABLE Position */ #define SDMMC_CTRL_INT_ENABLE_Msk (0x01UL << SDMMC_CTRL_INT_ENABLE_Pos) /*!< SDMMC CTRL: INT_ENABLE Mask */ #define SDMMC_CTRL_READ_WAIT_Pos 6 /*!< SDMMC CTRL: READ_WAIT Position */ #define SDMMC_CTRL_READ_WAIT_Msk (0x01UL << SDMMC_CTRL_READ_WAIT_Pos) /*!< SDMMC CTRL: READ_WAIT Mask */ #define SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos 7 /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Position */ #define SDMMC_CTRL_SEND_IRQ_RESPONSE_Msk (0x01UL << SDMMC_CTRL_SEND_IRQ_RESPONSE_Pos) /*!< SDMMC CTRL: SEND_IRQ_RESPONSE Mask */ #define SDMMC_CTRL_ABORT_READ_DATA_Pos 8 /*!< SDMMC CTRL: ABORT_READ_DATA Position */ #define SDMMC_CTRL_ABORT_READ_DATA_Msk (0x01UL << SDMMC_CTRL_ABORT_READ_DATA_Pos) /*!< SDMMC CTRL: ABORT_READ_DATA Mask */ #define SDMMC_CTRL_SEND_CCSD_Pos 9 /*!< SDMMC CTRL: SEND_CCSD Position */ #define SDMMC_CTRL_SEND_CCSD_Msk (0x01UL << SDMMC_CTRL_SEND_CCSD_Pos) /*!< SDMMC CTRL: SEND_CCSD Mask */ #define SDMMC_CTRL_SEND_AUTO_STOP_Pos 10 /*!< SDMMC CTRL: SEND_AUTO_STOP Position */ #define SDMMC_CTRL_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CTRL_SEND_AUTO_STOP_Pos) /*!< SDMMC CTRL: SEND_AUTO_STOP Mask */ #define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos 11 /*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Position */ #define SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Msk (0x01UL << SDMMC_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_Pos)/*!< SDMMC CTRL: CEATA_DEVICE_INTERRUPT_STATUS Mask */ #define SDMMC_CTRL_CARD_VOLTAGE_A0_Pos 16 /*!< SDMMC CTRL: CARD_VOLTAGE_A0 Position */ #define SDMMC_CTRL_CARD_VOLTAGE_A0_Msk (0x01UL << SDMMC_CTRL_CARD_VOLTAGE_A0_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A0 Mask */ #define SDMMC_CTRL_CARD_VOLTAGE_A1_Pos 17 /*!< SDMMC CTRL: CARD_VOLTAGE_A1 Position */ #define SDMMC_CTRL_CARD_VOLTAGE_A1_Msk (0x01UL << SDMMC_CTRL_CARD_VOLTAGE_A1_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A1 Mask */ #define SDMMC_CTRL_CARD_VOLTAGE_A2_Pos 18 /*!< SDMMC CTRL: CARD_VOLTAGE_A2 Position */ #define SDMMC_CTRL_CARD_VOLTAGE_A2_Msk (0x01UL << SDMMC_CTRL_CARD_VOLTAGE_A2_Pos) /*!< SDMMC CTRL: CARD_VOLTAGE_A2 Mask */ #define SDMMC_CTRL_USE_INTERNAL_DMAC_Pos 25 /*!< SDMMC CTRL: USE_INTERNAL_DMAC Position */ #define SDMMC_CTRL_USE_INTERNAL_DMAC_Msk (0x01UL << SDMMC_CTRL_USE_INTERNAL_DMAC_Pos) /*!< SDMMC CTRL: USE_INTERNAL_DMAC Mask */ /* --------------------------------- SDMMC_PWREN -------------------------------- */ #define SDMMC_PWREN_POWER_ENABLE_Pos 0 /*!< SDMMC PWREN: POWER_ENABLE Position */ #define SDMMC_PWREN_POWER_ENABLE_Msk (0x01UL << SDMMC_PWREN_POWER_ENABLE_Pos) /*!< SDMMC PWREN: POWER_ENABLE Mask */ /* -------------------------------- SDMMC_CLKDIV -------------------------------- */ #define SDMMC_CLKDIV_CLK_DIVIDER0_Pos 0 /*!< SDMMC CLKDIV: CLK_DIVIDER0 Position */ #define SDMMC_CLKDIV_CLK_DIVIDER0_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER0_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER0 Mask */ #define SDMMC_CLKDIV_CLK_DIVIDER1_Pos 8 /*!< SDMMC CLKDIV: CLK_DIVIDER1 Position */ #define SDMMC_CLKDIV_CLK_DIVIDER1_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER1_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER1 Mask */ #define SDMMC_CLKDIV_CLK_DIVIDER2_Pos 16 /*!< SDMMC CLKDIV: CLK_DIVIDER2 Position */ #define SDMMC_CLKDIV_CLK_DIVIDER2_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER2_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER2 Mask */ #define SDMMC_CLKDIV_CLK_DIVIDER3_Pos 24 /*!< SDMMC CLKDIV: CLK_DIVIDER3 Position */ #define SDMMC_CLKDIV_CLK_DIVIDER3_Msk (0x000000ffUL << SDMMC_CLKDIV_CLK_DIVIDER3_Pos) /*!< SDMMC CLKDIV: CLK_DIVIDER3 Mask */ /* -------------------------------- SDMMC_CLKSRC -------------------------------- */ #define SDMMC_CLKSRC_CLK_SOURCE_Pos 0 /*!< SDMMC CLKSRC: CLK_SOURCE Position */ #define SDMMC_CLKSRC_CLK_SOURCE_Msk (0x03UL << SDMMC_CLKSRC_CLK_SOURCE_Pos) /*!< SDMMC CLKSRC: CLK_SOURCE Mask */ /* -------------------------------- SDMMC_CLKENA -------------------------------- */ #define SDMMC_CLKENA_CCLK_ENABLE_Pos 0 /*!< SDMMC CLKENA: CCLK_ENABLE Position */ #define SDMMC_CLKENA_CCLK_ENABLE_Msk (0x01UL << SDMMC_CLKENA_CCLK_ENABLE_Pos) /*!< SDMMC CLKENA: CCLK_ENABLE Mask */ #define SDMMC_CLKENA_CCLK_LOW_POWER_Pos 16 /*!< SDMMC CLKENA: CCLK_LOW_POWER Position */ #define SDMMC_CLKENA_CCLK_LOW_POWER_Msk (0x01UL << SDMMC_CLKENA_CCLK_LOW_POWER_Pos) /*!< SDMMC CLKENA: CCLK_LOW_POWER Mask */ /* --------------------------------- SDMMC_TMOUT -------------------------------- */ #define SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos 0 /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Position */ #define SDMMC_TMOUT_RESPONSE_TIMEOUT_Msk (0x000000ffUL << SDMMC_TMOUT_RESPONSE_TIMEOUT_Pos) /*!< SDMMC TMOUT: RESPONSE_TIMEOUT Mask */ #define SDMMC_TMOUT_DATA_TIMEOUT_Pos 8 /*!< SDMMC TMOUT: DATA_TIMEOUT Position */ #define SDMMC_TMOUT_DATA_TIMEOUT_Msk (0x00ffffffUL << SDMMC_TMOUT_DATA_TIMEOUT_Pos) /*!< SDMMC TMOUT: DATA_TIMEOUT Mask */ /* --------------------------------- SDMMC_CTYPE -------------------------------- */ #define SDMMC_CTYPE_CARD_WIDTH0_Pos 0 /*!< SDMMC CTYPE: CARD_WIDTH0 Position */ #define SDMMC_CTYPE_CARD_WIDTH0_Msk (0x01UL << SDMMC_CTYPE_CARD_WIDTH0_Pos) /*!< SDMMC CTYPE: CARD_WIDTH0 Mask */ #define SDMMC_CTYPE_CARD_WIDTH1_Pos 16 /*!< SDMMC CTYPE: CARD_WIDTH1 Position */ #define SDMMC_CTYPE_CARD_WIDTH1_Msk (0x01UL << SDMMC_CTYPE_CARD_WIDTH1_Pos) /*!< SDMMC CTYPE: CARD_WIDTH1 Mask */ /* -------------------------------- SDMMC_BLKSIZ -------------------------------- */ #define SDMMC_BLKSIZ_BLOCK_SIZE_Pos 0 /*!< SDMMC BLKSIZ: BLOCK_SIZE Position */ #define SDMMC_BLKSIZ_BLOCK_SIZE_Msk (0x0000ffffUL << SDMMC_BLKSIZ_BLOCK_SIZE_Pos) /*!< SDMMC BLKSIZ: BLOCK_SIZE Mask */ /* -------------------------------- SDMMC_BYTCNT -------------------------------- */ #define SDMMC_BYTCNT_BYTE_COUNT_Pos 0 /*!< SDMMC BYTCNT: BYTE_COUNT Position */ #define SDMMC_BYTCNT_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_BYTCNT_BYTE_COUNT_Pos) /*!< SDMMC BYTCNT: BYTE_COUNT Mask */ /* -------------------------------- SDMMC_INTMASK ------------------------------- */ #define SDMMC_INTMASK_CDET_Pos 0 /*!< SDMMC INTMASK: CDET Position */ #define SDMMC_INTMASK_CDET_Msk (0x01UL << SDMMC_INTMASK_CDET_Pos) /*!< SDMMC INTMASK: CDET Mask */ #define SDMMC_INTMASK_RE_Pos 1 /*!< SDMMC INTMASK: RE Position */ #define SDMMC_INTMASK_RE_Msk (0x01UL << SDMMC_INTMASK_RE_Pos) /*!< SDMMC INTMASK: RE Mask */ #define SDMMC_INTMASK_CDONE_Pos 2 /*!< SDMMC INTMASK: CDONE Position */ #define SDMMC_INTMASK_CDONE_Msk (0x01UL << SDMMC_INTMASK_CDONE_Pos) /*!< SDMMC INTMASK: CDONE Mask */ #define SDMMC_INTMASK_DTO_Pos 3 /*!< SDMMC INTMASK: DTO Position */ #define SDMMC_INTMASK_DTO_Msk (0x01UL << SDMMC_INTMASK_DTO_Pos) /*!< SDMMC INTMASK: DTO Mask */ #define SDMMC_INTMASK_TXDR_Pos 4 /*!< SDMMC INTMASK: TXDR Position */ #define SDMMC_INTMASK_TXDR_Msk (0x01UL << SDMMC_INTMASK_TXDR_Pos) /*!< SDMMC INTMASK: TXDR Mask */ #define SDMMC_INTMASK_RXDR_Pos 5 /*!< SDMMC INTMASK: RXDR Position */ #define SDMMC_INTMASK_RXDR_Msk (0x01UL << SDMMC_INTMASK_RXDR_Pos) /*!< SDMMC INTMASK: RXDR Mask */ #define SDMMC_INTMASK_RCRC_Pos 6 /*!< SDMMC INTMASK: RCRC Position */ #define SDMMC_INTMASK_RCRC_Msk (0x01UL << SDMMC_INTMASK_RCRC_Pos) /*!< SDMMC INTMASK: RCRC Mask */ #define SDMMC_INTMASK_DCRC_Pos 7 /*!< SDMMC INTMASK: DCRC Position */ #define SDMMC_INTMASK_DCRC_Msk (0x01UL << SDMMC_INTMASK_DCRC_Pos) /*!< SDMMC INTMASK: DCRC Mask */ #define SDMMC_INTMASK_RTO_Pos 8 /*!< SDMMC INTMASK: RTO Position */ #define SDMMC_INTMASK_RTO_Msk (0x01UL << SDMMC_INTMASK_RTO_Pos) /*!< SDMMC INTMASK: RTO Mask */ #define SDMMC_INTMASK_DRTO_Pos 9 /*!< SDMMC INTMASK: DRTO Position */ #define SDMMC_INTMASK_DRTO_Msk (0x01UL << SDMMC_INTMASK_DRTO_Pos) /*!< SDMMC INTMASK: DRTO Mask */ #define SDMMC_INTMASK_HTO_Pos 10 /*!< SDMMC INTMASK: HTO Position */ #define SDMMC_INTMASK_HTO_Msk (0x01UL << SDMMC_INTMASK_HTO_Pos) /*!< SDMMC INTMASK: HTO Mask */ #define SDMMC_INTMASK_FRUN_Pos 11 /*!< SDMMC INTMASK: FRUN Position */ #define SDMMC_INTMASK_FRUN_Msk (0x01UL << SDMMC_INTMASK_FRUN_Pos) /*!< SDMMC INTMASK: FRUN Mask */ #define SDMMC_INTMASK_HLE_Pos 12 /*!< SDMMC INTMASK: HLE Position */ #define SDMMC_INTMASK_HLE_Msk (0x01UL << SDMMC_INTMASK_HLE_Pos) /*!< SDMMC INTMASK: HLE Mask */ #define SDMMC_INTMASK_SBE_Pos 13 /*!< SDMMC INTMASK: SBE Position */ #define SDMMC_INTMASK_SBE_Msk (0x01UL << SDMMC_INTMASK_SBE_Pos) /*!< SDMMC INTMASK: SBE Mask */ #define SDMMC_INTMASK_ACD_Pos 14 /*!< SDMMC INTMASK: ACD Position */ #define SDMMC_INTMASK_ACD_Msk (0x01UL << SDMMC_INTMASK_ACD_Pos) /*!< SDMMC INTMASK: ACD Mask */ #define SDMMC_INTMASK_EBE_Pos 15 /*!< SDMMC INTMASK: EBE Position */ #define SDMMC_INTMASK_EBE_Msk (0x01UL << SDMMC_INTMASK_EBE_Pos) /*!< SDMMC INTMASK: EBE Mask */ #define SDMMC_INTMASK_SDIO_INT_MASK_Pos 16 /*!< SDMMC INTMASK: SDIO_INT_MASK Position */ #define SDMMC_INTMASK_SDIO_INT_MASK_Msk (0x01UL << SDMMC_INTMASK_SDIO_INT_MASK_Pos) /*!< SDMMC INTMASK: SDIO_INT_MASK Mask */ /* -------------------------------- SDMMC_CMDARG -------------------------------- */ #define SDMMC_CMDARG_CMD_ARG_Pos 0 /*!< SDMMC CMDARG: CMD_ARG Position */ #define SDMMC_CMDARG_CMD_ARG_Msk (0xffffffffUL << SDMMC_CMDARG_CMD_ARG_Pos) /*!< SDMMC CMDARG: CMD_ARG Mask */ /* ---------------------------------- SDMMC_CMD --------------------------------- */ #define SDMMC_CMD_CMD_INDEX_Pos 0 /*!< SDMMC CMD: CMD_INDEX Position */ #define SDMMC_CMD_CMD_INDEX_Msk (0x3fUL << SDMMC_CMD_CMD_INDEX_Pos) /*!< SDMMC CMD: CMD_INDEX Mask */ #define SDMMC_CMD_RESPONSE_EXPECT_Pos 6 /*!< SDMMC CMD: RESPONSE_EXPECT Position */ #define SDMMC_CMD_RESPONSE_EXPECT_Msk (0x01UL << SDMMC_CMD_RESPONSE_EXPECT_Pos) /*!< SDMMC CMD: RESPONSE_EXPECT Mask */ #define SDMMC_CMD_RESPONSE_LENGTH_Pos 7 /*!< SDMMC CMD: RESPONSE_LENGTH Position */ #define SDMMC_CMD_RESPONSE_LENGTH_Msk (0x01UL << SDMMC_CMD_RESPONSE_LENGTH_Pos) /*!< SDMMC CMD: RESPONSE_LENGTH Mask */ #define SDMMC_CMD_CHECK_RESPONSE_CRC_Pos 8 /*!< SDMMC CMD: CHECK_RESPONSE_CRC Position */ #define SDMMC_CMD_CHECK_RESPONSE_CRC_Msk (0x01UL << SDMMC_CMD_CHECK_RESPONSE_CRC_Pos) /*!< SDMMC CMD: CHECK_RESPONSE_CRC Mask */ #define SDMMC_CMD_DATA_EXPECTED_Pos 9 /*!< SDMMC CMD: DATA_EXPECTED Position */ #define SDMMC_CMD_DATA_EXPECTED_Msk (0x01UL << SDMMC_CMD_DATA_EXPECTED_Pos) /*!< SDMMC CMD: DATA_EXPECTED Mask */ #define SDMMC_CMD_READ_WRITE_Pos 10 /*!< SDMMC CMD: READ_WRITE Position */ #define SDMMC_CMD_READ_WRITE_Msk (0x01UL << SDMMC_CMD_READ_WRITE_Pos) /*!< SDMMC CMD: READ_WRITE Mask */ #define SDMMC_CMD_TRANSFER_MODE_Pos 11 /*!< SDMMC CMD: TRANSFER_MODE Position */ #define SDMMC_CMD_TRANSFER_MODE_Msk (0x01UL << SDMMC_CMD_TRANSFER_MODE_Pos) /*!< SDMMC CMD: TRANSFER_MODE Mask */ #define SDMMC_CMD_SEND_AUTO_STOP_Pos 12 /*!< SDMMC CMD: SEND_AUTO_STOP Position */ #define SDMMC_CMD_SEND_AUTO_STOP_Msk (0x01UL << SDMMC_CMD_SEND_AUTO_STOP_Pos) /*!< SDMMC CMD: SEND_AUTO_STOP Mask */ #define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos 13 /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Position */ #define SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Msk (0x01UL << SDMMC_CMD_WAIT_PRVDATA_COMPLETE_Pos) /*!< SDMMC CMD: WAIT_PRVDATA_COMPLETE Mask */ #define SDMMC_CMD_STOP_ABORT_CMD_Pos 14 /*!< SDMMC CMD: STOP_ABORT_CMD Position */ #define SDMMC_CMD_STOP_ABORT_CMD_Msk (0x01UL << SDMMC_CMD_STOP_ABORT_CMD_Pos) /*!< SDMMC CMD: STOP_ABORT_CMD Mask */ #define SDMMC_CMD_SEND_INITIALIZATION_Pos 15 /*!< SDMMC CMD: SEND_INITIALIZATION Position */ #define SDMMC_CMD_SEND_INITIALIZATION_Msk (0x01UL << SDMMC_CMD_SEND_INITIALIZATION_Pos) /*!< SDMMC CMD: SEND_INITIALIZATION Mask */ #define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos 21 /*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Position */ #define SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Msk (0x01UL << SDMMC_CMD_UPDATE_CLOCK_REGISTERS_ONLY_Pos)/*!< SDMMC CMD: UPDATE_CLOCK_REGISTERS_ONLY Mask */ #define SDMMC_CMD_READ_CEATA_DEVICE_Pos 22 /*!< SDMMC CMD: READ_CEATA_DEVICE Position */ #define SDMMC_CMD_READ_CEATA_DEVICE_Msk (0x01UL << SDMMC_CMD_READ_CEATA_DEVICE_Pos) /*!< SDMMC CMD: READ_CEATA_DEVICE Mask */ #define SDMMC_CMD_CCS_EXPECTED_Pos 23 /*!< SDMMC CMD: CCS_EXPECTED Position */ #define SDMMC_CMD_CCS_EXPECTED_Msk (0x01UL << SDMMC_CMD_CCS_EXPECTED_Pos) /*!< SDMMC CMD: CCS_EXPECTED Mask */ #define SDMMC_CMD_ENABLE_BOOT_Pos 24 /*!< SDMMC CMD: ENABLE_BOOT Position */ #define SDMMC_CMD_ENABLE_BOOT_Msk (0x01UL << SDMMC_CMD_ENABLE_BOOT_Pos) /*!< SDMMC CMD: ENABLE_BOOT Mask */ #define SDMMC_CMD_EXPECT_BOOT_ACK_Pos 25 /*!< SDMMC CMD: EXPECT_BOOT_ACK Position */ #define SDMMC_CMD_EXPECT_BOOT_ACK_Msk (0x01UL << SDMMC_CMD_EXPECT_BOOT_ACK_Pos) /*!< SDMMC CMD: EXPECT_BOOT_ACK Mask */ #define SDMMC_CMD_DISABLE_BOOT_Pos 26 /*!< SDMMC CMD: DISABLE_BOOT Position */ #define SDMMC_CMD_DISABLE_BOOT_Msk (0x01UL << SDMMC_CMD_DISABLE_BOOT_Pos) /*!< SDMMC CMD: DISABLE_BOOT Mask */ #define SDMMC_CMD_BOOT_MODE_Pos 27 /*!< SDMMC CMD: BOOT_MODE Position */ #define SDMMC_CMD_BOOT_MODE_Msk (0x01UL << SDMMC_CMD_BOOT_MODE_Pos) /*!< SDMMC CMD: BOOT_MODE Mask */ #define SDMMC_CMD_VOLT_SWITCH_Pos 28 /*!< SDMMC CMD: VOLT_SWITCH Position */ #define SDMMC_CMD_VOLT_SWITCH_Msk (0x01UL << SDMMC_CMD_VOLT_SWITCH_Pos) /*!< SDMMC CMD: VOLT_SWITCH Mask */ #define SDMMC_CMD_START_CMD_Pos 31 /*!< SDMMC CMD: START_CMD Position */ #define SDMMC_CMD_START_CMD_Msk (0x01UL << SDMMC_CMD_START_CMD_Pos) /*!< SDMMC CMD: START_CMD Mask */ /* --------------------------------- SDMMC_RESP0 -------------------------------- */ #define SDMMC_RESP0_RESPONSE0_Pos 0 /*!< SDMMC RESP0: RESPONSE0 Position */ #define SDMMC_RESP0_RESPONSE0_Msk (0xffffffffUL << SDMMC_RESP0_RESPONSE0_Pos) /*!< SDMMC RESP0: RESPONSE0 Mask */ /* --------------------------------- SDMMC_RESP1 -------------------------------- */ #define SDMMC_RESP1_RESPONSE1_Pos 0 /*!< SDMMC RESP1: RESPONSE1 Position */ #define SDMMC_RESP1_RESPONSE1_Msk (0xffffffffUL << SDMMC_RESP1_RESPONSE1_Pos) /*!< SDMMC RESP1: RESPONSE1 Mask */ /* --------------------------------- SDMMC_RESP2 -------------------------------- */ #define SDMMC_RESP2_RESPONSE2_Pos 0 /*!< SDMMC RESP2: RESPONSE2 Position */ #define SDMMC_RESP2_RESPONSE2_Msk (0xffffffffUL << SDMMC_RESP2_RESPONSE2_Pos) /*!< SDMMC RESP2: RESPONSE2 Mask */ /* --------------------------------- SDMMC_RESP3 -------------------------------- */ #define SDMMC_RESP3_RESPONSE3_Pos 0 /*!< SDMMC RESP3: RESPONSE3 Position */ #define SDMMC_RESP3_RESPONSE3_Msk (0xffffffffUL << SDMMC_RESP3_RESPONSE3_Pos) /*!< SDMMC RESP3: RESPONSE3 Mask */ /* -------------------------------- SDMMC_MINTSTS ------------------------------- */ #define SDMMC_MINTSTS_CDET_Pos 0 /*!< SDMMC MINTSTS: CDET Position */ #define SDMMC_MINTSTS_CDET_Msk (0x01UL << SDMMC_MINTSTS_CDET_Pos) /*!< SDMMC MINTSTS: CDET Mask */ #define SDMMC_MINTSTS_RE_Pos 1 /*!< SDMMC MINTSTS: RE Position */ #define SDMMC_MINTSTS_RE_Msk (0x01UL << SDMMC_MINTSTS_RE_Pos) /*!< SDMMC MINTSTS: RE Mask */ #define SDMMC_MINTSTS_CDONE_Pos 2 /*!< SDMMC MINTSTS: CDONE Position */ #define SDMMC_MINTSTS_CDONE_Msk (0x01UL << SDMMC_MINTSTS_CDONE_Pos) /*!< SDMMC MINTSTS: CDONE Mask */ #define SDMMC_MINTSTS_DTO_Pos 3 /*!< SDMMC MINTSTS: DTO Position */ #define SDMMC_MINTSTS_DTO_Msk (0x01UL << SDMMC_MINTSTS_DTO_Pos) /*!< SDMMC MINTSTS: DTO Mask */ #define SDMMC_MINTSTS_TXDR_Pos 4 /*!< SDMMC MINTSTS: TXDR Position */ #define SDMMC_MINTSTS_TXDR_Msk (0x01UL << SDMMC_MINTSTS_TXDR_Pos) /*!< SDMMC MINTSTS: TXDR Mask */ #define SDMMC_MINTSTS_RXDR_Pos 5 /*!< SDMMC MINTSTS: RXDR Position */ #define SDMMC_MINTSTS_RXDR_Msk (0x01UL << SDMMC_MINTSTS_RXDR_Pos) /*!< SDMMC MINTSTS: RXDR Mask */ #define SDMMC_MINTSTS_RCRC_Pos 6 /*!< SDMMC MINTSTS: RCRC Position */ #define SDMMC_MINTSTS_RCRC_Msk (0x01UL << SDMMC_MINTSTS_RCRC_Pos) /*!< SDMMC MINTSTS: RCRC Mask */ #define SDMMC_MINTSTS_DCRC_Pos 7 /*!< SDMMC MINTSTS: DCRC Position */ #define SDMMC_MINTSTS_DCRC_Msk (0x01UL << SDMMC_MINTSTS_DCRC_Pos) /*!< SDMMC MINTSTS: DCRC Mask */ #define SDMMC_MINTSTS_RTO_Pos 8 /*!< SDMMC MINTSTS: RTO Position */ #define SDMMC_MINTSTS_RTO_Msk (0x01UL << SDMMC_MINTSTS_RTO_Pos) /*!< SDMMC MINTSTS: RTO Mask */ #define SDMMC_MINTSTS_DRTO_Pos 9 /*!< SDMMC MINTSTS: DRTO Position */ #define SDMMC_MINTSTS_DRTO_Msk (0x01UL << SDMMC_MINTSTS_DRTO_Pos) /*!< SDMMC MINTSTS: DRTO Mask */ #define SDMMC_MINTSTS_HTO_Pos 10 /*!< SDMMC MINTSTS: HTO Position */ #define SDMMC_MINTSTS_HTO_Msk (0x01UL << SDMMC_MINTSTS_HTO_Pos) /*!< SDMMC MINTSTS: HTO Mask */ #define SDMMC_MINTSTS_FRUN_Pos 11 /*!< SDMMC MINTSTS: FRUN Position */ #define SDMMC_MINTSTS_FRUN_Msk (0x01UL << SDMMC_MINTSTS_FRUN_Pos) /*!< SDMMC MINTSTS: FRUN Mask */ #define SDMMC_MINTSTS_HLE_Pos 12 /*!< SDMMC MINTSTS: HLE Position */ #define SDMMC_MINTSTS_HLE_Msk (0x01UL << SDMMC_MINTSTS_HLE_Pos) /*!< SDMMC MINTSTS: HLE Mask */ #define SDMMC_MINTSTS_SBE_Pos 13 /*!< SDMMC MINTSTS: SBE Position */ #define SDMMC_MINTSTS_SBE_Msk (0x01UL << SDMMC_MINTSTS_SBE_Pos) /*!< SDMMC MINTSTS: SBE Mask */ #define SDMMC_MINTSTS_ACD_Pos 14 /*!< SDMMC MINTSTS: ACD Position */ #define SDMMC_MINTSTS_ACD_Msk (0x01UL << SDMMC_MINTSTS_ACD_Pos) /*!< SDMMC MINTSTS: ACD Mask */ #define SDMMC_MINTSTS_EBE_Pos 15 /*!< SDMMC MINTSTS: EBE Position */ #define SDMMC_MINTSTS_EBE_Msk (0x01UL << SDMMC_MINTSTS_EBE_Pos) /*!< SDMMC MINTSTS: EBE Mask */ #define SDMMC_MINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC MINTSTS: SDIO_INTERRUPT Position */ #define SDMMC_MINTSTS_SDIO_INTERRUPT_Msk (0x01UL << SDMMC_MINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC MINTSTS: SDIO_INTERRUPT Mask */ /* -------------------------------- SDMMC_RINTSTS ------------------------------- */ #define SDMMC_RINTSTS_CDET_Pos 0 /*!< SDMMC RINTSTS: CDET Position */ #define SDMMC_RINTSTS_CDET_Msk (0x01UL << SDMMC_RINTSTS_CDET_Pos) /*!< SDMMC RINTSTS: CDET Mask */ #define SDMMC_RINTSTS_RE_Pos 1 /*!< SDMMC RINTSTS: RE Position */ #define SDMMC_RINTSTS_RE_Msk (0x01UL << SDMMC_RINTSTS_RE_Pos) /*!< SDMMC RINTSTS: RE Mask */ #define SDMMC_RINTSTS_CDONE_Pos 2 /*!< SDMMC RINTSTS: CDONE Position */ #define SDMMC_RINTSTS_CDONE_Msk (0x01UL << SDMMC_RINTSTS_CDONE_Pos) /*!< SDMMC RINTSTS: CDONE Mask */ #define SDMMC_RINTSTS_DTO_Pos 3 /*!< SDMMC RINTSTS: DTO Position */ #define SDMMC_RINTSTS_DTO_Msk (0x01UL << SDMMC_RINTSTS_DTO_Pos) /*!< SDMMC RINTSTS: DTO Mask */ #define SDMMC_RINTSTS_TXDR_Pos 4 /*!< SDMMC RINTSTS: TXDR Position */ #define SDMMC_RINTSTS_TXDR_Msk (0x01UL << SDMMC_RINTSTS_TXDR_Pos) /*!< SDMMC RINTSTS: TXDR Mask */ #define SDMMC_RINTSTS_RXDR_Pos 5 /*!< SDMMC RINTSTS: RXDR Position */ #define SDMMC_RINTSTS_RXDR_Msk (0x01UL << SDMMC_RINTSTS_RXDR_Pos) /*!< SDMMC RINTSTS: RXDR Mask */ #define SDMMC_RINTSTS_RCRC_Pos 6 /*!< SDMMC RINTSTS: RCRC Position */ #define SDMMC_RINTSTS_RCRC_Msk (0x01UL << SDMMC_RINTSTS_RCRC_Pos) /*!< SDMMC RINTSTS: RCRC Mask */ #define SDMMC_RINTSTS_DCRC_Pos 7 /*!< SDMMC RINTSTS: DCRC Position */ #define SDMMC_RINTSTS_DCRC_Msk (0x01UL << SDMMC_RINTSTS_DCRC_Pos) /*!< SDMMC RINTSTS: DCRC Mask */ #define SDMMC_RINTSTS_RTO_BAR_Pos 8 /*!< SDMMC RINTSTS: RTO_BAR Position */ #define SDMMC_RINTSTS_RTO_BAR_Msk (0x01UL << SDMMC_RINTSTS_RTO_BAR_Pos) /*!< SDMMC RINTSTS: RTO_BAR Mask */ #define SDMMC_RINTSTS_DRTO_BDS_Pos 9 /*!< SDMMC RINTSTS: DRTO_BDS Position */ #define SDMMC_RINTSTS_DRTO_BDS_Msk (0x01UL << SDMMC_RINTSTS_DRTO_BDS_Pos) /*!< SDMMC RINTSTS: DRTO_BDS Mask */ #define SDMMC_RINTSTS_HTO_Pos 10 /*!< SDMMC RINTSTS: HTO Position */ #define SDMMC_RINTSTS_HTO_Msk (0x01UL << SDMMC_RINTSTS_HTO_Pos) /*!< SDMMC RINTSTS: HTO Mask */ #define SDMMC_RINTSTS_FRUN_Pos 11 /*!< SDMMC RINTSTS: FRUN Position */ #define SDMMC_RINTSTS_FRUN_Msk (0x01UL << SDMMC_RINTSTS_FRUN_Pos) /*!< SDMMC RINTSTS: FRUN Mask */ #define SDMMC_RINTSTS_HLE_Pos 12 /*!< SDMMC RINTSTS: HLE Position */ #define SDMMC_RINTSTS_HLE_Msk (0x01UL << SDMMC_RINTSTS_HLE_Pos) /*!< SDMMC RINTSTS: HLE Mask */ #define SDMMC_RINTSTS_SBE_Pos 13 /*!< SDMMC RINTSTS: SBE Position */ #define SDMMC_RINTSTS_SBE_Msk (0x01UL << SDMMC_RINTSTS_SBE_Pos) /*!< SDMMC RINTSTS: SBE Mask */ #define SDMMC_RINTSTS_ACD_Pos 14 /*!< SDMMC RINTSTS: ACD Position */ #define SDMMC_RINTSTS_ACD_Msk (0x01UL << SDMMC_RINTSTS_ACD_Pos) /*!< SDMMC RINTSTS: ACD Mask */ #define SDMMC_RINTSTS_EBE_Pos 15 /*!< SDMMC RINTSTS: EBE Position */ #define SDMMC_RINTSTS_EBE_Msk (0x01UL << SDMMC_RINTSTS_EBE_Pos) /*!< SDMMC RINTSTS: EBE Mask */ #define SDMMC_RINTSTS_SDIO_INTERRUPT_Pos 16 /*!< SDMMC RINTSTS: SDIO_INTERRUPT Position */ #define SDMMC_RINTSTS_SDIO_INTERRUPT_Msk (0x01UL << SDMMC_RINTSTS_SDIO_INTERRUPT_Pos) /*!< SDMMC RINTSTS: SDIO_INTERRUPT Mask */ /* -------------------------------- SDMMC_STATUS -------------------------------- */ #define SDMMC_STATUS_FIFO_RX_WATERMARK_Pos 0 /*!< SDMMC STATUS: FIFO_RX_WATERMARK Position */ #define SDMMC_STATUS_FIFO_RX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_RX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_RX_WATERMARK Mask */ #define SDMMC_STATUS_FIFO_TX_WATERMARK_Pos 1 /*!< SDMMC STATUS: FIFO_TX_WATERMARK Position */ #define SDMMC_STATUS_FIFO_TX_WATERMARK_Msk (0x01UL << SDMMC_STATUS_FIFO_TX_WATERMARK_Pos) /*!< SDMMC STATUS: FIFO_TX_WATERMARK Mask */ #define SDMMC_STATUS_FIFO_EMPTY_Pos 2 /*!< SDMMC STATUS: FIFO_EMPTY Position */ #define SDMMC_STATUS_FIFO_EMPTY_Msk (0x01UL << SDMMC_STATUS_FIFO_EMPTY_Pos) /*!< SDMMC STATUS: FIFO_EMPTY Mask */ #define SDMMC_STATUS_FIFO_FULL_Pos 3 /*!< SDMMC STATUS: FIFO_FULL Position */ #define SDMMC_STATUS_FIFO_FULL_Msk (0x01UL << SDMMC_STATUS_FIFO_FULL_Pos) /*!< SDMMC STATUS: FIFO_FULL Mask */ #define SDMMC_STATUS_CMDFSMSTATES_Pos 4 /*!< SDMMC STATUS: CMDFSMSTATES Position */ #define SDMMC_STATUS_CMDFSMSTATES_Msk (0x0fUL << SDMMC_STATUS_CMDFSMSTATES_Pos) /*!< SDMMC STATUS: CMDFSMSTATES Mask */ #define SDMMC_STATUS_DATA_3_STATUS_Pos 8 /*!< SDMMC STATUS: DATA_3_STATUS Position */ #define SDMMC_STATUS_DATA_3_STATUS_Msk (0x01UL << SDMMC_STATUS_DATA_3_STATUS_Pos) /*!< SDMMC STATUS: DATA_3_STATUS Mask */ #define SDMMC_STATUS_DATA_BUSY_Pos 9 /*!< SDMMC STATUS: DATA_BUSY Position */ #define SDMMC_STATUS_DATA_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_BUSY_Pos) /*!< SDMMC STATUS: DATA_BUSY Mask */ #define SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos 10 /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Position */ #define SDMMC_STATUS_DATA_STATE_MC_BUSY_Msk (0x01UL << SDMMC_STATUS_DATA_STATE_MC_BUSY_Pos) /*!< SDMMC STATUS: DATA_STATE_MC_BUSY Mask */ #define SDMMC_STATUS_RESPONSE_INDEX_Pos 11 /*!< SDMMC STATUS: RESPONSE_INDEX Position */ #define SDMMC_STATUS_RESPONSE_INDEX_Msk (0x3fUL << SDMMC_STATUS_RESPONSE_INDEX_Pos) /*!< SDMMC STATUS: RESPONSE_INDEX Mask */ #define SDMMC_STATUS_FIFO_COUNT_Pos 17 /*!< SDMMC STATUS: FIFO_COUNT Position */ #define SDMMC_STATUS_FIFO_COUNT_Msk (0x00001fffUL << SDMMC_STATUS_FIFO_COUNT_Pos) /*!< SDMMC STATUS: FIFO_COUNT Mask */ #define SDMMC_STATUS_DMA_ACK_Pos 30 /*!< SDMMC STATUS: DMA_ACK Position */ #define SDMMC_STATUS_DMA_ACK_Msk (0x01UL << SDMMC_STATUS_DMA_ACK_Pos) /*!< SDMMC STATUS: DMA_ACK Mask */ #define SDMMC_STATUS_DMA_REQ_Pos 31 /*!< SDMMC STATUS: DMA_REQ Position */ #define SDMMC_STATUS_DMA_REQ_Msk (0x01UL << SDMMC_STATUS_DMA_REQ_Pos) /*!< SDMMC STATUS: DMA_REQ Mask */ /* -------------------------------- SDMMC_FIFOTH -------------------------------- */ #define SDMMC_FIFOTH_TX_WMARK_Pos 0 /*!< SDMMC FIFOTH: TX_WMARK Position */ #define SDMMC_FIFOTH_TX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_TX_WMARK_Pos) /*!< SDMMC FIFOTH: TX_WMARK Mask */ #define SDMMC_FIFOTH_RX_WMARK_Pos 16 /*!< SDMMC FIFOTH: RX_WMARK Position */ #define SDMMC_FIFOTH_RX_WMARK_Msk (0x00000fffUL << SDMMC_FIFOTH_RX_WMARK_Pos) /*!< SDMMC FIFOTH: RX_WMARK Mask */ #define SDMMC_FIFOTH_DMA_MTS_Pos 28 /*!< SDMMC FIFOTH: DMA_MTS Position */ #define SDMMC_FIFOTH_DMA_MTS_Msk (0x07UL << SDMMC_FIFOTH_DMA_MTS_Pos) /*!< SDMMC FIFOTH: DMA_MTS Mask */ /* -------------------------------- SDMMC_CDETECT ------------------------------- */ #define SDMMC_CDETECT_CARD_DETECT_Pos 0 /*!< SDMMC CDETECT: CARD_DETECT Position */ #define SDMMC_CDETECT_CARD_DETECT_Msk (0x01UL << SDMMC_CDETECT_CARD_DETECT_Pos) /*!< SDMMC CDETECT: CARD_DETECT Mask */ /* -------------------------------- SDMMC_WRTPRT -------------------------------- */ #define SDMMC_WRTPRT_WRITE_PROTECT_Pos 0 /*!< SDMMC WRTPRT: WRITE_PROTECT Position */ #define SDMMC_WRTPRT_WRITE_PROTECT_Msk (0x01UL << SDMMC_WRTPRT_WRITE_PROTECT_Pos) /*!< SDMMC WRTPRT: WRITE_PROTECT Mask */ /* -------------------------------- SDMMC_TCBCNT -------------------------------- */ #define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos 0 /*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Position */ #define SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_Pos)/*!< SDMMC TCBCNT: TRANS_CARD_BYTE_COUNT Mask */ /* -------------------------------- SDMMC_TBBCNT -------------------------------- */ #define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos 0 /*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Position */ #define SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Msk (0xffffffffUL << SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_Pos)/*!< SDMMC TBBCNT: TRANS_FIFO_BYTE_COUNT Mask */ /* -------------------------------- SDMMC_DEBNCE -------------------------------- */ #define SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos 0 /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Position */ #define SDMMC_DEBNCE_DEBOUNCE_COUNT_Msk (0x00ffffffUL << SDMMC_DEBNCE_DEBOUNCE_COUNT_Pos) /*!< SDMMC DEBNCE: DEBOUNCE_COUNT Mask */ /* --------------------------------- SDMMC_RST_N -------------------------------- */ #define SDMMC_RST_N_CARD_RESET_Pos 0 /*!< SDMMC RST_N: CARD_RESET Position */ #define SDMMC_RST_N_CARD_RESET_Msk (0x01UL << SDMMC_RST_N_CARD_RESET_Pos) /*!< SDMMC RST_N: CARD_RESET Mask */ /* --------------------------------- SDMMC_BMOD --------------------------------- */ #define SDMMC_BMOD_SWR_Pos 0 /*!< SDMMC BMOD: SWR Position */ #define SDMMC_BMOD_SWR_Msk (0x01UL << SDMMC_BMOD_SWR_Pos) /*!< SDMMC BMOD: SWR Mask */ #define SDMMC_BMOD_FB_Pos 1 /*!< SDMMC BMOD: FB Position */ #define SDMMC_BMOD_FB_Msk (0x01UL << SDMMC_BMOD_FB_Pos) /*!< SDMMC BMOD: FB Mask */ #define SDMMC_BMOD_DSL_Pos 2 /*!< SDMMC BMOD: DSL Position */ #define SDMMC_BMOD_DSL_Msk (0x1fUL << SDMMC_BMOD_DSL_Pos) /*!< SDMMC BMOD: DSL Mask */ #define SDMMC_BMOD_DE_Pos 7 /*!< SDMMC BMOD: DE Position */ #define SDMMC_BMOD_DE_Msk (0x01UL << SDMMC_BMOD_DE_Pos) /*!< SDMMC BMOD: DE Mask */ #define SDMMC_BMOD_PBL_Pos 8 /*!< SDMMC BMOD: PBL Position */ #define SDMMC_BMOD_PBL_Msk (0x07UL << SDMMC_BMOD_PBL_Pos) /*!< SDMMC BMOD: PBL Mask */ /* -------------------------------- SDMMC_PLDMND -------------------------------- */ #define SDMMC_PLDMND_PD_Pos 0 /*!< SDMMC PLDMND: PD Position */ #define SDMMC_PLDMND_PD_Msk (0xffffffffUL << SDMMC_PLDMND_PD_Pos) /*!< SDMMC PLDMND: PD Mask */ /* -------------------------------- SDMMC_DBADDR -------------------------------- */ #define SDMMC_DBADDR_SDL_Pos 0 /*!< SDMMC DBADDR: SDL Position */ #define SDMMC_DBADDR_SDL_Msk (0xffffffffUL << SDMMC_DBADDR_SDL_Pos) /*!< SDMMC DBADDR: SDL Mask */ /* --------------------------------- SDMMC_IDSTS -------------------------------- */ #define SDMMC_IDSTS_TI_Pos 0 /*!< SDMMC IDSTS: TI Position */ #define SDMMC_IDSTS_TI_Msk (0x01UL << SDMMC_IDSTS_TI_Pos) /*!< SDMMC IDSTS: TI Mask */ #define SDMMC_IDSTS_RI_Pos 1 /*!< SDMMC IDSTS: RI Position */ #define SDMMC_IDSTS_RI_Msk (0x01UL << SDMMC_IDSTS_RI_Pos) /*!< SDMMC IDSTS: RI Mask */ #define SDMMC_IDSTS_FBE_Pos 2 /*!< SDMMC IDSTS: FBE Position */ #define SDMMC_IDSTS_FBE_Msk (0x01UL << SDMMC_IDSTS_FBE_Pos) /*!< SDMMC IDSTS: FBE Mask */ #define SDMMC_IDSTS_DU_Pos 4 /*!< SDMMC IDSTS: DU Position */ #define SDMMC_IDSTS_DU_Msk (0x01UL << SDMMC_IDSTS_DU_Pos) /*!< SDMMC IDSTS: DU Mask */ #define SDMMC_IDSTS_CES_Pos 5 /*!< SDMMC IDSTS: CES Position */ #define SDMMC_IDSTS_CES_Msk (0x01UL << SDMMC_IDSTS_CES_Pos) /*!< SDMMC IDSTS: CES Mask */ #define SDMMC_IDSTS_NIS_Pos 8 /*!< SDMMC IDSTS: NIS Position */ #define SDMMC_IDSTS_NIS_Msk (0x01UL << SDMMC_IDSTS_NIS_Pos) /*!< SDMMC IDSTS: NIS Mask */ #define SDMMC_IDSTS_AIS_Pos 9 /*!< SDMMC IDSTS: AIS Position */ #define SDMMC_IDSTS_AIS_Msk (0x01UL << SDMMC_IDSTS_AIS_Pos) /*!< SDMMC IDSTS: AIS Mask */ #define SDMMC_IDSTS_EB_Pos 10 /*!< SDMMC IDSTS: EB Position */ #define SDMMC_IDSTS_EB_Msk (0x07UL << SDMMC_IDSTS_EB_Pos) /*!< SDMMC IDSTS: EB Mask */ #define SDMMC_IDSTS_FSM_Pos 13 /*!< SDMMC IDSTS: FSM Position */ #define SDMMC_IDSTS_FSM_Msk (0x0fUL << SDMMC_IDSTS_FSM_Pos) /*!< SDMMC IDSTS: FSM Mask */ /* -------------------------------- SDMMC_IDINTEN ------------------------------- */ #define SDMMC_IDINTEN_TI_Pos 0 /*!< SDMMC IDINTEN: TI Position */ #define SDMMC_IDINTEN_TI_Msk (0x01UL << SDMMC_IDINTEN_TI_Pos) /*!< SDMMC IDINTEN: TI Mask */ #define SDMMC_IDINTEN_RI_Pos 1 /*!< SDMMC IDINTEN: RI Position */ #define SDMMC_IDINTEN_RI_Msk (0x01UL << SDMMC_IDINTEN_RI_Pos) /*!< SDMMC IDINTEN: RI Mask */ #define SDMMC_IDINTEN_FBE_Pos 2 /*!< SDMMC IDINTEN: FBE Position */ #define SDMMC_IDINTEN_FBE_Msk (0x01UL << SDMMC_IDINTEN_FBE_Pos) /*!< SDMMC IDINTEN: FBE Mask */ #define SDMMC_IDINTEN_DU_Pos 4 /*!< SDMMC IDINTEN: DU Position */ #define SDMMC_IDINTEN_DU_Msk (0x01UL << SDMMC_IDINTEN_DU_Pos) /*!< SDMMC IDINTEN: DU Mask */ #define SDMMC_IDINTEN_CES_Pos 5 /*!< SDMMC IDINTEN: CES Position */ #define SDMMC_IDINTEN_CES_Msk (0x01UL << SDMMC_IDINTEN_CES_Pos) /*!< SDMMC IDINTEN: CES Mask */ #define SDMMC_IDINTEN_NIS_Pos 8 /*!< SDMMC IDINTEN: NIS Position */ #define SDMMC_IDINTEN_NIS_Msk (0x01UL << SDMMC_IDINTEN_NIS_Pos) /*!< SDMMC IDINTEN: NIS Mask */ #define SDMMC_IDINTEN_AIS_Pos 9 /*!< SDMMC IDINTEN: AIS Position */ #define SDMMC_IDINTEN_AIS_Msk (0x01UL << SDMMC_IDINTEN_AIS_Pos) /*!< SDMMC IDINTEN: AIS Mask */ /* -------------------------------- SDMMC_DSCADDR ------------------------------- */ #define SDMMC_DSCADDR_HDA_Pos 0 /*!< SDMMC DSCADDR: HDA Position */ #define SDMMC_DSCADDR_HDA_Msk (0xffffffffUL << SDMMC_DSCADDR_HDA_Pos) /*!< SDMMC DSCADDR: HDA Mask */ /* -------------------------------- SDMMC_BUFADDR ------------------------------- */ #define SDMMC_BUFADDR_HBA_Pos 0 /*!< SDMMC BUFADDR: HBA Position */ #define SDMMC_BUFADDR_HBA_Msk (0xffffffffUL << SDMMC_BUFADDR_HBA_Pos) /*!< SDMMC BUFADDR: HBA Mask */ /* ================================================================================ */ /* ================ struct 'EMC' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- EMC_CONTROL -------------------------------- */ #define EMC_CONTROL_E_Pos 0 /*!< EMC CONTROL: E Position */ #define EMC_CONTROL_E_Msk (0x01UL << EMC_CONTROL_E_Pos) /*!< EMC CONTROL: E Mask */ #define EMC_CONTROL_M_Pos 1 /*!< EMC CONTROL: M Position */ #define EMC_CONTROL_M_Msk (0x01UL << EMC_CONTROL_M_Pos) /*!< EMC CONTROL: M Mask */ #define EMC_CONTROL_L_Pos 2 /*!< EMC CONTROL: L Position */ #define EMC_CONTROL_L_Msk (0x01UL << EMC_CONTROL_L_Pos) /*!< EMC CONTROL: L Mask */ /* --------------------------------- EMC_STATUS --------------------------------- */ #define EMC_STATUS_B_Pos 0 /*!< EMC STATUS: B Position */ #define EMC_STATUS_B_Msk (0x01UL << EMC_STATUS_B_Pos) /*!< EMC STATUS: B Mask */ #define EMC_STATUS_S_Pos 1 /*!< EMC STATUS: S Position */ #define EMC_STATUS_S_Msk (0x01UL << EMC_STATUS_S_Pos) /*!< EMC STATUS: S Mask */ #define EMC_STATUS_SA_Pos 2 /*!< EMC STATUS: SA Position */ #define EMC_STATUS_SA_Msk (0x01UL << EMC_STATUS_SA_Pos) /*!< EMC STATUS: SA Mask */ /* --------------------------------- EMC_CONFIG --------------------------------- */ #define EMC_CONFIG_EM_Pos 0 /*!< EMC CONFIG: EM Position */ #define EMC_CONFIG_EM_Msk (0x01UL << EMC_CONFIG_EM_Pos) /*!< EMC CONFIG: EM Mask */ /* ----------------------------- EMC_DYNAMICCONTROL ----------------------------- */ #define EMC_DYNAMICCONTROL_CE_Pos 0 /*!< EMC DYNAMICCONTROL: CE Position */ #define EMC_DYNAMICCONTROL_CE_Msk (0x01UL << EMC_DYNAMICCONTROL_CE_Pos) /*!< EMC DYNAMICCONTROL: CE Mask */ #define EMC_DYNAMICCONTROL_CS_Pos 1 /*!< EMC DYNAMICCONTROL: CS Position */ #define EMC_DYNAMICCONTROL_CS_Msk (0x01UL << EMC_DYNAMICCONTROL_CS_Pos) /*!< EMC DYNAMICCONTROL: CS Mask */ #define EMC_DYNAMICCONTROL_SR_Pos 2 /*!< EMC DYNAMICCONTROL: SR Position */ #define EMC_DYNAMICCONTROL_SR_Msk (0x01UL << EMC_DYNAMICCONTROL_SR_Pos) /*!< EMC DYNAMICCONTROL: SR Mask */ #define EMC_DYNAMICCONTROL_MMC_Pos 5 /*!< EMC DYNAMICCONTROL: MMC Position */ #define EMC_DYNAMICCONTROL_MMC_Msk (0x01UL << EMC_DYNAMICCONTROL_MMC_Pos) /*!< EMC DYNAMICCONTROL: MMC Mask */ #define EMC_DYNAMICCONTROL_I_Pos 7 /*!< EMC DYNAMICCONTROL: I Position */ #define EMC_DYNAMICCONTROL_I_Msk (0x03UL << EMC_DYNAMICCONTROL_I_Pos) /*!< EMC DYNAMICCONTROL: I Mask */ /* ----------------------------- EMC_DYNAMICREFRESH ----------------------------- */ #define EMC_DYNAMICREFRESH_REFRESH_Pos 0 /*!< EMC DYNAMICREFRESH: REFRESH Position */ #define EMC_DYNAMICREFRESH_REFRESH_Msk (0x000007ffUL << EMC_DYNAMICREFRESH_REFRESH_Pos) /*!< EMC DYNAMICREFRESH: REFRESH Mask */ /* ---------------------------- EMC_DYNAMICREADCONFIG --------------------------- */ #define EMC_DYNAMICREADCONFIG_RD_Pos 0 /*!< EMC DYNAMICREADCONFIG: RD Position */ #define EMC_DYNAMICREADCONFIG_RD_Msk (0x03UL << EMC_DYNAMICREADCONFIG_RD_Pos) /*!< EMC DYNAMICREADCONFIG: RD Mask */ /* -------------------------------- EMC_DYNAMICRP ------------------------------- */ #define EMC_DYNAMICRP_TRP_Pos 0 /*!< EMC DYNAMICRP: TRP Position */ #define EMC_DYNAMICRP_TRP_Msk (0x0fUL << EMC_DYNAMICRP_TRP_Pos) /*!< EMC DYNAMICRP: TRP Mask */ /* ------------------------------- EMC_DYNAMICRAS ------------------------------- */ #define EMC_DYNAMICRAS_TRAS_Pos 0 /*!< EMC DYNAMICRAS: TRAS Position */ #define EMC_DYNAMICRAS_TRAS_Msk (0x0fUL << EMC_DYNAMICRAS_TRAS_Pos) /*!< EMC DYNAMICRAS: TRAS Mask */ /* ------------------------------- EMC_DYNAMICSREX ------------------------------ */ #define EMC_DYNAMICSREX_TSREX_Pos 0 /*!< EMC DYNAMICSREX: TSREX Position */ #define EMC_DYNAMICSREX_TSREX_Msk (0x0fUL << EMC_DYNAMICSREX_TSREX_Pos) /*!< EMC DYNAMICSREX: TSREX Mask */ /* ------------------------------- EMC_DYNAMICAPR ------------------------------- */ #define EMC_DYNAMICAPR_TAPR_Pos 0 /*!< EMC DYNAMICAPR: TAPR Position */ #define EMC_DYNAMICAPR_TAPR_Msk (0x0fUL << EMC_DYNAMICAPR_TAPR_Pos) /*!< EMC DYNAMICAPR: TAPR Mask */ /* ------------------------------- EMC_DYNAMICDAL ------------------------------- */ #define EMC_DYNAMICDAL_TDAL_Pos 0 /*!< EMC DYNAMICDAL: TDAL Position */ #define EMC_DYNAMICDAL_TDAL_Msk (0x0fUL << EMC_DYNAMICDAL_TDAL_Pos) /*!< EMC DYNAMICDAL: TDAL Mask */ /* -------------------------------- EMC_DYNAMICWR ------------------------------- */ #define EMC_DYNAMICWR_TWR_Pos 0 /*!< EMC DYNAMICWR: TWR Position */ #define EMC_DYNAMICWR_TWR_Msk (0x0fUL << EMC_DYNAMICWR_TWR_Pos) /*!< EMC DYNAMICWR: TWR Mask */ /* -------------------------------- EMC_DYNAMICRC ------------------------------- */ #define EMC_DYNAMICRC_TRC_Pos 0 /*!< EMC DYNAMICRC: TRC Position */ #define EMC_DYNAMICRC_TRC_Msk (0x1fUL << EMC_DYNAMICRC_TRC_Pos) /*!< EMC DYNAMICRC: TRC Mask */ /* ------------------------------- EMC_DYNAMICRFC ------------------------------- */ #define EMC_DYNAMICRFC_TRFC_Pos 0 /*!< EMC DYNAMICRFC: TRFC Position */ #define EMC_DYNAMICRFC_TRFC_Msk (0x1fUL << EMC_DYNAMICRFC_TRFC_Pos) /*!< EMC DYNAMICRFC: TRFC Mask */ /* ------------------------------- EMC_DYNAMICXSR ------------------------------- */ #define EMC_DYNAMICXSR_TXSR_Pos 0 /*!< EMC DYNAMICXSR: TXSR Position */ #define EMC_DYNAMICXSR_TXSR_Msk (0x1fUL << EMC_DYNAMICXSR_TXSR_Pos) /*!< EMC DYNAMICXSR: TXSR Mask */ /* ------------------------------- EMC_DYNAMICRRD ------------------------------- */ #define EMC_DYNAMICRRD_TRRD_Pos 0 /*!< EMC DYNAMICRRD: TRRD Position */ #define EMC_DYNAMICRRD_TRRD_Msk (0x0fUL << EMC_DYNAMICRRD_TRRD_Pos) /*!< EMC DYNAMICRRD: TRRD Mask */ /* ------------------------------- EMC_DYNAMICMRD ------------------------------- */ #define EMC_DYNAMICMRD_TMRD_Pos 0 /*!< EMC DYNAMICMRD: TMRD Position */ #define EMC_DYNAMICMRD_TMRD_Msk (0x0fUL << EMC_DYNAMICMRD_TMRD_Pos) /*!< EMC DYNAMICMRD: TMRD Mask */ /* --------------------------- EMC_STATICEXTENDEDWAIT --------------------------- */ #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos 0 /*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Position */ #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Msk (0x000003ffUL << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_Pos)/*!< EMC STATICEXTENDEDWAIT: EXTENDEDWAIT Mask */ /* ----------------------------- EMC_DYNAMICCONFIG0 ----------------------------- */ #define EMC_DYNAMICCONFIG0_MD_Pos 3 /*!< EMC DYNAMICCONFIG0: MD Position */ #define EMC_DYNAMICCONFIG0_MD_Msk (0x03UL << EMC_DYNAMICCONFIG0_MD_Pos) /*!< EMC DYNAMICCONFIG0: MD Mask */ #define EMC_DYNAMICCONFIG0_AM0_Pos 7 /*!< EMC DYNAMICCONFIG0: AM0 Position */ #define EMC_DYNAMICCONFIG0_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG0_AM0_Pos) /*!< EMC DYNAMICCONFIG0: AM0 Mask */ #define EMC_DYNAMICCONFIG0_AM1_Pos 14 /*!< EMC DYNAMICCONFIG0: AM1 Position */ #define EMC_DYNAMICCONFIG0_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG0_AM1_Pos) /*!< EMC DYNAMICCONFIG0: AM1 Mask */ #define EMC_DYNAMICCONFIG0_B_Pos 19 /*!< EMC DYNAMICCONFIG0: B Position */ #define EMC_DYNAMICCONFIG0_B_Msk (0x01UL << EMC_DYNAMICCONFIG0_B_Pos) /*!< EMC DYNAMICCONFIG0: B Mask */ #define EMC_DYNAMICCONFIG0_P_Pos 20 /*!< EMC DYNAMICCONFIG0: P Position */ #define EMC_DYNAMICCONFIG0_P_Msk (0x01UL << EMC_DYNAMICCONFIG0_P_Pos) /*!< EMC DYNAMICCONFIG0: P Mask */ /* ----------------------------- EMC_DYNAMICRASCAS0 ----------------------------- */ #define EMC_DYNAMICRASCAS0_RAS_Pos 0 /*!< EMC DYNAMICRASCAS0: RAS Position */ #define EMC_DYNAMICRASCAS0_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_RAS_Pos) /*!< EMC DYNAMICRASCAS0: RAS Mask */ #define EMC_DYNAMICRASCAS0_CAS_Pos 8 /*!< EMC DYNAMICRASCAS0: CAS Position */ #define EMC_DYNAMICRASCAS0_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS0_CAS_Pos) /*!< EMC DYNAMICRASCAS0: CAS Mask */ /* ----------------------------- EMC_DYNAMICCONFIG1 ----------------------------- */ #define EMC_DYNAMICCONFIG1_MD_Pos 3 /*!< EMC DYNAMICCONFIG1: MD Position */ #define EMC_DYNAMICCONFIG1_MD_Msk (0x03UL << EMC_DYNAMICCONFIG1_MD_Pos) /*!< EMC DYNAMICCONFIG1: MD Mask */ #define EMC_DYNAMICCONFIG1_AM0_Pos 7 /*!< EMC DYNAMICCONFIG1: AM0 Position */ #define EMC_DYNAMICCONFIG1_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG1_AM0_Pos) /*!< EMC DYNAMICCONFIG1: AM0 Mask */ #define EMC_DYNAMICCONFIG1_AM1_Pos 14 /*!< EMC DYNAMICCONFIG1: AM1 Position */ #define EMC_DYNAMICCONFIG1_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG1_AM1_Pos) /*!< EMC DYNAMICCONFIG1: AM1 Mask */ #define EMC_DYNAMICCONFIG1_B_Pos 19 /*!< EMC DYNAMICCONFIG1: B Position */ #define EMC_DYNAMICCONFIG1_B_Msk (0x01UL << EMC_DYNAMICCONFIG1_B_Pos) /*!< EMC DYNAMICCONFIG1: B Mask */ #define EMC_DYNAMICCONFIG1_P_Pos 20 /*!< EMC DYNAMICCONFIG1: P Position */ #define EMC_DYNAMICCONFIG1_P_Msk (0x01UL << EMC_DYNAMICCONFIG1_P_Pos) /*!< EMC DYNAMICCONFIG1: P Mask */ /* ----------------------------- EMC_DYNAMICRASCAS1 ----------------------------- */ #define EMC_DYNAMICRASCAS1_RAS_Pos 0 /*!< EMC DYNAMICRASCAS1: RAS Position */ #define EMC_DYNAMICRASCAS1_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_RAS_Pos) /*!< EMC DYNAMICRASCAS1: RAS Mask */ #define EMC_DYNAMICRASCAS1_CAS_Pos 8 /*!< EMC DYNAMICRASCAS1: CAS Position */ #define EMC_DYNAMICRASCAS1_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS1_CAS_Pos) /*!< EMC DYNAMICRASCAS1: CAS Mask */ /* ----------------------------- EMC_DYNAMICCONFIG2 ----------------------------- */ #define EMC_DYNAMICCONFIG2_MD_Pos 3 /*!< EMC DYNAMICCONFIG2: MD Position */ #define EMC_DYNAMICCONFIG2_MD_Msk (0x03UL << EMC_DYNAMICCONFIG2_MD_Pos) /*!< EMC DYNAMICCONFIG2: MD Mask */ #define EMC_DYNAMICCONFIG2_AM0_Pos 7 /*!< EMC DYNAMICCONFIG2: AM0 Position */ #define EMC_DYNAMICCONFIG2_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG2_AM0_Pos) /*!< EMC DYNAMICCONFIG2: AM0 Mask */ #define EMC_DYNAMICCONFIG2_AM1_Pos 14 /*!< EMC DYNAMICCONFIG2: AM1 Position */ #define EMC_DYNAMICCONFIG2_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG2_AM1_Pos) /*!< EMC DYNAMICCONFIG2: AM1 Mask */ #define EMC_DYNAMICCONFIG2_B_Pos 19 /*!< EMC DYNAMICCONFIG2: B Position */ #define EMC_DYNAMICCONFIG2_B_Msk (0x01UL << EMC_DYNAMICCONFIG2_B_Pos) /*!< EMC DYNAMICCONFIG2: B Mask */ #define EMC_DYNAMICCONFIG2_P_Pos 20 /*!< EMC DYNAMICCONFIG2: P Position */ #define EMC_DYNAMICCONFIG2_P_Msk (0x01UL << EMC_DYNAMICCONFIG2_P_Pos) /*!< EMC DYNAMICCONFIG2: P Mask */ /* ----------------------------- EMC_DYNAMICRASCAS2 ----------------------------- */ #define EMC_DYNAMICRASCAS2_RAS_Pos 0 /*!< EMC DYNAMICRASCAS2: RAS Position */ #define EMC_DYNAMICRASCAS2_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_RAS_Pos) /*!< EMC DYNAMICRASCAS2: RAS Mask */ #define EMC_DYNAMICRASCAS2_CAS_Pos 8 /*!< EMC DYNAMICRASCAS2: CAS Position */ #define EMC_DYNAMICRASCAS2_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS2_CAS_Pos) /*!< EMC DYNAMICRASCAS2: CAS Mask */ /* ----------------------------- EMC_DYNAMICCONFIG3 ----------------------------- */ #define EMC_DYNAMICCONFIG3_MD_Pos 3 /*!< EMC DYNAMICCONFIG3: MD Position */ #define EMC_DYNAMICCONFIG3_MD_Msk (0x03UL << EMC_DYNAMICCONFIG3_MD_Pos) /*!< EMC DYNAMICCONFIG3: MD Mask */ #define EMC_DYNAMICCONFIG3_AM0_Pos 7 /*!< EMC DYNAMICCONFIG3: AM0 Position */ #define EMC_DYNAMICCONFIG3_AM0_Msk (0x3fUL << EMC_DYNAMICCONFIG3_AM0_Pos) /*!< EMC DYNAMICCONFIG3: AM0 Mask */ #define EMC_DYNAMICCONFIG3_AM1_Pos 14 /*!< EMC DYNAMICCONFIG3: AM1 Position */ #define EMC_DYNAMICCONFIG3_AM1_Msk (0x01UL << EMC_DYNAMICCONFIG3_AM1_Pos) /*!< EMC DYNAMICCONFIG3: AM1 Mask */ #define EMC_DYNAMICCONFIG3_B_Pos 19 /*!< EMC DYNAMICCONFIG3: B Position */ #define EMC_DYNAMICCONFIG3_B_Msk (0x01UL << EMC_DYNAMICCONFIG3_B_Pos) /*!< EMC DYNAMICCONFIG3: B Mask */ #define EMC_DYNAMICCONFIG3_P_Pos 20 /*!< EMC DYNAMICCONFIG3: P Position */ #define EMC_DYNAMICCONFIG3_P_Msk (0x01UL << EMC_DYNAMICCONFIG3_P_Pos) /*!< EMC DYNAMICCONFIG3: P Mask */ /* ----------------------------- EMC_DYNAMICRASCAS3 ----------------------------- */ #define EMC_DYNAMICRASCAS3_RAS_Pos 0 /*!< EMC DYNAMICRASCAS3: RAS Position */ #define EMC_DYNAMICRASCAS3_RAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_RAS_Pos) /*!< EMC DYNAMICRASCAS3: RAS Mask */ #define EMC_DYNAMICRASCAS3_CAS_Pos 8 /*!< EMC DYNAMICRASCAS3: CAS Position */ #define EMC_DYNAMICRASCAS3_CAS_Msk (0x03UL << EMC_DYNAMICRASCAS3_CAS_Pos) /*!< EMC DYNAMICRASCAS3: CAS Mask */ /* ------------------------------ EMC_STATICCONFIG0 ----------------------------- */ #define EMC_STATICCONFIG0_MW_Pos 0 /*!< EMC STATICCONFIG0: MW Position */ #define EMC_STATICCONFIG0_MW_Msk (0x03UL << EMC_STATICCONFIG0_MW_Pos) /*!< EMC STATICCONFIG0: MW Mask */ #define EMC_STATICCONFIG0_PM_Pos 3 /*!< EMC STATICCONFIG0: PM Position */ #define EMC_STATICCONFIG0_PM_Msk (0x01UL << EMC_STATICCONFIG0_PM_Pos) /*!< EMC STATICCONFIG0: PM Mask */ #define EMC_STATICCONFIG0_PC_Pos 6 /*!< EMC STATICCONFIG0: PC Position */ #define EMC_STATICCONFIG0_PC_Msk (0x01UL << EMC_STATICCONFIG0_PC_Pos) /*!< EMC STATICCONFIG0: PC Mask */ #define EMC_STATICCONFIG0_PB_Pos 7 /*!< EMC STATICCONFIG0: PB Position */ #define EMC_STATICCONFIG0_PB_Msk (0x01UL << EMC_STATICCONFIG0_PB_Pos) /*!< EMC STATICCONFIG0: PB Mask */ #define EMC_STATICCONFIG0_EW_Pos 8 /*!< EMC STATICCONFIG0: EW Position */ #define EMC_STATICCONFIG0_EW_Msk (0x01UL << EMC_STATICCONFIG0_EW_Pos) /*!< EMC STATICCONFIG0: EW Mask */ #define EMC_STATICCONFIG0_B_Pos 19 /*!< EMC STATICCONFIG0: B Position */ #define EMC_STATICCONFIG0_B_Msk (0x01UL << EMC_STATICCONFIG0_B_Pos) /*!< EMC STATICCONFIG0: B Mask */ #define EMC_STATICCONFIG0_P_Pos 20 /*!< EMC STATICCONFIG0: P Position */ #define EMC_STATICCONFIG0_P_Msk (0x01UL << EMC_STATICCONFIG0_P_Pos) /*!< EMC STATICCONFIG0: P Mask */ /* ----------------------------- EMC_STATICWAITWEN0 ----------------------------- */ #define EMC_STATICWAITWEN0_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN0: WAITWEN Position */ #define EMC_STATICWAITWEN0_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN0_WAITWEN_Pos) /*!< EMC STATICWAITWEN0: WAITWEN Mask */ /* ----------------------------- EMC_STATICWAITOEN0 ----------------------------- */ #define EMC_STATICWAITOEN0_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN0: WAITOEN Position */ #define EMC_STATICWAITOEN0_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN0_WAITOEN_Pos) /*!< EMC STATICWAITOEN0: WAITOEN Mask */ /* ------------------------------ EMC_STATICWAITRD0 ----------------------------- */ #define EMC_STATICWAITRD0_WAITRD_Pos 0 /*!< EMC STATICWAITRD0: WAITRD Position */ #define EMC_STATICWAITRD0_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD0_WAITRD_Pos) /*!< EMC STATICWAITRD0: WAITRD Mask */ /* ----------------------------- EMC_STATICWAITPAGE0 ---------------------------- */ #define EMC_STATICWAITPAGE0_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAGE0: WAITPAGE Position */ #define EMC_STATICWAITPAGE0_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAGE0_WAITPAGE_Pos) /*!< EMC STATICWAITPAGE0: WAITPAGE Mask */ /* ------------------------------ EMC_STATICWAITWR0 ----------------------------- */ #define EMC_STATICWAITWR0_WAITWR_Pos 0 /*!< EMC STATICWAITWR0: WAITWR Position */ #define EMC_STATICWAITWR0_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR0_WAITWR_Pos) /*!< EMC STATICWAITWR0: WAITWR Mask */ /* ----------------------------- EMC_STATICWAITTURN0 ---------------------------- */ #define EMC_STATICWAITTURN0_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN0: WAITTURN Position */ #define EMC_STATICWAITTURN0_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN0_WAITTURN_Pos) /*!< EMC STATICWAITTURN0: WAITTURN Mask */ /* ------------------------------ EMC_STATICCONFIG1 ----------------------------- */ #define EMC_STATICCONFIG1_MW_Pos 0 /*!< EMC STATICCONFIG1: MW Position */ #define EMC_STATICCONFIG1_MW_Msk (0x03UL << EMC_STATICCONFIG1_MW_Pos) /*!< EMC STATICCONFIG1: MW Mask */ #define EMC_STATICCONFIG1_PM_Pos 3 /*!< EMC STATICCONFIG1: PM Position */ #define EMC_STATICCONFIG1_PM_Msk (0x01UL << EMC_STATICCONFIG1_PM_Pos) /*!< EMC STATICCONFIG1: PM Mask */ #define EMC_STATICCONFIG1_PC_Pos 6 /*!< EMC STATICCONFIG1: PC Position */ #define EMC_STATICCONFIG1_PC_Msk (0x01UL << EMC_STATICCONFIG1_PC_Pos) /*!< EMC STATICCONFIG1: PC Mask */ #define EMC_STATICCONFIG1_PB_Pos 7 /*!< EMC STATICCONFIG1: PB Position */ #define EMC_STATICCONFIG1_PB_Msk (0x01UL << EMC_STATICCONFIG1_PB_Pos) /*!< EMC STATICCONFIG1: PB Mask */ #define EMC_STATICCONFIG1_EW_Pos 8 /*!< EMC STATICCONFIG1: EW Position */ #define EMC_STATICCONFIG1_EW_Msk (0x01UL << EMC_STATICCONFIG1_EW_Pos) /*!< EMC STATICCONFIG1: EW Mask */ #define EMC_STATICCONFIG1_B_Pos 19 /*!< EMC STATICCONFIG1: B Position */ #define EMC_STATICCONFIG1_B_Msk (0x01UL << EMC_STATICCONFIG1_B_Pos) /*!< EMC STATICCONFIG1: B Mask */ #define EMC_STATICCONFIG1_P_Pos 20 /*!< EMC STATICCONFIG1: P Position */ #define EMC_STATICCONFIG1_P_Msk (0x01UL << EMC_STATICCONFIG1_P_Pos) /*!< EMC STATICCONFIG1: P Mask */ /* ----------------------------- EMC_STATICWAITWEN1 ----------------------------- */ #define EMC_STATICWAITWEN1_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN1: WAITWEN Position */ #define EMC_STATICWAITWEN1_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN1_WAITWEN_Pos) /*!< EMC STATICWAITWEN1: WAITWEN Mask */ /* ----------------------------- EMC_STATICWAITOEN1 ----------------------------- */ #define EMC_STATICWAITOEN1_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN1: WAITOEN Position */ #define EMC_STATICWAITOEN1_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN1_WAITOEN_Pos) /*!< EMC STATICWAITOEN1: WAITOEN Mask */ /* ------------------------------ EMC_STATICWAITRD1 ----------------------------- */ #define EMC_STATICWAITRD1_WAITRD_Pos 0 /*!< EMC STATICWAITRD1: WAITRD Position */ #define EMC_STATICWAITRD1_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD1_WAITRD_Pos) /*!< EMC STATICWAITRD1: WAITRD Mask */ /* ----------------------------- EMC_STATICWAITPAGE1 ---------------------------- */ #define EMC_STATICWAITPAGE1_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAGE1: WAITPAGE Position */ #define EMC_STATICWAITPAGE1_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAGE1_WAITPAGE_Pos) /*!< EMC STATICWAITPAGE1: WAITPAGE Mask */ /* ------------------------------ EMC_STATICWAITWR1 ----------------------------- */ #define EMC_STATICWAITWR1_WAITWR_Pos 0 /*!< EMC STATICWAITWR1: WAITWR Position */ #define EMC_STATICWAITWR1_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR1_WAITWR_Pos) /*!< EMC STATICWAITWR1: WAITWR Mask */ /* ----------------------------- EMC_STATICWAITTURN1 ---------------------------- */ #define EMC_STATICWAITTURN1_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN1: WAITTURN Position */ #define EMC_STATICWAITTURN1_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN1_WAITTURN_Pos) /*!< EMC STATICWAITTURN1: WAITTURN Mask */ /* ------------------------------ EMC_STATICCONFIG2 ----------------------------- */ #define EMC_STATICCONFIG2_MW_Pos 0 /*!< EMC STATICCONFIG2: MW Position */ #define EMC_STATICCONFIG2_MW_Msk (0x03UL << EMC_STATICCONFIG2_MW_Pos) /*!< EMC STATICCONFIG2: MW Mask */ #define EMC_STATICCONFIG2_PM_Pos 3 /*!< EMC STATICCONFIG2: PM Position */ #define EMC_STATICCONFIG2_PM_Msk (0x01UL << EMC_STATICCONFIG2_PM_Pos) /*!< EMC STATICCONFIG2: PM Mask */ #define EMC_STATICCONFIG2_PC_Pos 6 /*!< EMC STATICCONFIG2: PC Position */ #define EMC_STATICCONFIG2_PC_Msk (0x01UL << EMC_STATICCONFIG2_PC_Pos) /*!< EMC STATICCONFIG2: PC Mask */ #define EMC_STATICCONFIG2_PB_Pos 7 /*!< EMC STATICCONFIG2: PB Position */ #define EMC_STATICCONFIG2_PB_Msk (0x01UL << EMC_STATICCONFIG2_PB_Pos) /*!< EMC STATICCONFIG2: PB Mask */ #define EMC_STATICCONFIG2_EW_Pos 8 /*!< EMC STATICCONFIG2: EW Position */ #define EMC_STATICCONFIG2_EW_Msk (0x01UL << EMC_STATICCONFIG2_EW_Pos) /*!< EMC STATICCONFIG2: EW Mask */ #define EMC_STATICCONFIG2_B_Pos 19 /*!< EMC STATICCONFIG2: B Position */ #define EMC_STATICCONFIG2_B_Msk (0x01UL << EMC_STATICCONFIG2_B_Pos) /*!< EMC STATICCONFIG2: B Mask */ #define EMC_STATICCONFIG2_P_Pos 20 /*!< EMC STATICCONFIG2: P Position */ #define EMC_STATICCONFIG2_P_Msk (0x01UL << EMC_STATICCONFIG2_P_Pos) /*!< EMC STATICCONFIG2: P Mask */ /* ----------------------------- EMC_STATICWAITWEN2 ----------------------------- */ #define EMC_STATICWAITWEN2_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN2: WAITWEN Position */ #define EMC_STATICWAITWEN2_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN2_WAITWEN_Pos) /*!< EMC STATICWAITWEN2: WAITWEN Mask */ /* ----------------------------- EMC_STATICWAITOEN2 ----------------------------- */ #define EMC_STATICWAITOEN2_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN2: WAITOEN Position */ #define EMC_STATICWAITOEN2_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN2_WAITOEN_Pos) /*!< EMC STATICWAITOEN2: WAITOEN Mask */ /* ------------------------------ EMC_STATICWAITRD2 ----------------------------- */ #define EMC_STATICWAITRD2_WAITRD_Pos 0 /*!< EMC STATICWAITRD2: WAITRD Position */ #define EMC_STATICWAITRD2_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD2_WAITRD_Pos) /*!< EMC STATICWAITRD2: WAITRD Mask */ /* ----------------------------- EMC_STATICWAITPAGE2 ---------------------------- */ #define EMC_STATICWAITPAGE2_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAGE2: WAITPAGE Position */ #define EMC_STATICWAITPAGE2_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAGE2_WAITPAGE_Pos) /*!< EMC STATICWAITPAGE2: WAITPAGE Mask */ /* ------------------------------ EMC_STATICWAITWR2 ----------------------------- */ #define EMC_STATICWAITWR2_WAITWR_Pos 0 /*!< EMC STATICWAITWR2: WAITWR Position */ #define EMC_STATICWAITWR2_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR2_WAITWR_Pos) /*!< EMC STATICWAITWR2: WAITWR Mask */ /* ----------------------------- EMC_STATICWAITTURN2 ---------------------------- */ #define EMC_STATICWAITTURN2_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN2: WAITTURN Position */ #define EMC_STATICWAITTURN2_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN2_WAITTURN_Pos) /*!< EMC STATICWAITTURN2: WAITTURN Mask */ /* ------------------------------ EMC_STATICCONFIG3 ----------------------------- */ #define EMC_STATICCONFIG3_MW_Pos 0 /*!< EMC STATICCONFIG3: MW Position */ #define EMC_STATICCONFIG3_MW_Msk (0x03UL << EMC_STATICCONFIG3_MW_Pos) /*!< EMC STATICCONFIG3: MW Mask */ #define EMC_STATICCONFIG3_PM_Pos 3 /*!< EMC STATICCONFIG3: PM Position */ #define EMC_STATICCONFIG3_PM_Msk (0x01UL << EMC_STATICCONFIG3_PM_Pos) /*!< EMC STATICCONFIG3: PM Mask */ #define EMC_STATICCONFIG3_PC_Pos 6 /*!< EMC STATICCONFIG3: PC Position */ #define EMC_STATICCONFIG3_PC_Msk (0x01UL << EMC_STATICCONFIG3_PC_Pos) /*!< EMC STATICCONFIG3: PC Mask */ #define EMC_STATICCONFIG3_PB_Pos 7 /*!< EMC STATICCONFIG3: PB Position */ #define EMC_STATICCONFIG3_PB_Msk (0x01UL << EMC_STATICCONFIG3_PB_Pos) /*!< EMC STATICCONFIG3: PB Mask */ #define EMC_STATICCONFIG3_EW_Pos 8 /*!< EMC STATICCONFIG3: EW Position */ #define EMC_STATICCONFIG3_EW_Msk (0x01UL << EMC_STATICCONFIG3_EW_Pos) /*!< EMC STATICCONFIG3: EW Mask */ #define EMC_STATICCONFIG3_B_Pos 19 /*!< EMC STATICCONFIG3: B Position */ #define EMC_STATICCONFIG3_B_Msk (0x01UL << EMC_STATICCONFIG3_B_Pos) /*!< EMC STATICCONFIG3: B Mask */ #define EMC_STATICCONFIG3_P_Pos 20 /*!< EMC STATICCONFIG3: P Position */ #define EMC_STATICCONFIG3_P_Msk (0x01UL << EMC_STATICCONFIG3_P_Pos) /*!< EMC STATICCONFIG3: P Mask */ /* ----------------------------- EMC_STATICWAITWEN3 ----------------------------- */ #define EMC_STATICWAITWEN3_WAITWEN_Pos 0 /*!< EMC STATICWAITWEN3: WAITWEN Position */ #define EMC_STATICWAITWEN3_WAITWEN_Msk (0x0fUL << EMC_STATICWAITWEN3_WAITWEN_Pos) /*!< EMC STATICWAITWEN3: WAITWEN Mask */ /* ----------------------------- EMC_STATICWAITOEN3 ----------------------------- */ #define EMC_STATICWAITOEN3_WAITOEN_Pos 0 /*!< EMC STATICWAITOEN3: WAITOEN Position */ #define EMC_STATICWAITOEN3_WAITOEN_Msk (0x0fUL << EMC_STATICWAITOEN3_WAITOEN_Pos) /*!< EMC STATICWAITOEN3: WAITOEN Mask */ /* ------------------------------ EMC_STATICWAITRD3 ----------------------------- */ #define EMC_STATICWAITRD3_WAITRD_Pos 0 /*!< EMC STATICWAITRD3: WAITRD Position */ #define EMC_STATICWAITRD3_WAITRD_Msk (0x1fUL << EMC_STATICWAITRD3_WAITRD_Pos) /*!< EMC STATICWAITRD3: WAITRD Mask */ /* ----------------------------- EMC_STATICWAITPAGE3 ---------------------------- */ #define EMC_STATICWAITPAGE3_WAITPAGE_Pos 0 /*!< EMC STATICWAITPAGE3: WAITPAGE Position */ #define EMC_STATICWAITPAGE3_WAITPAGE_Msk (0x1fUL << EMC_STATICWAITPAGE3_WAITPAGE_Pos) /*!< EMC STATICWAITPAGE3: WAITPAGE Mask */ /* ------------------------------ EMC_STATICWAITWR3 ----------------------------- */ #define EMC_STATICWAITWR3_WAITWR_Pos 0 /*!< EMC STATICWAITWR3: WAITWR Position */ #define EMC_STATICWAITWR3_WAITWR_Msk (0x1fUL << EMC_STATICWAITWR3_WAITWR_Pos) /*!< EMC STATICWAITWR3: WAITWR Mask */ /* ----------------------------- EMC_STATICWAITTURN3 ---------------------------- */ #define EMC_STATICWAITTURN3_WAITTURN_Pos 0 /*!< EMC STATICWAITTURN3: WAITTURN Position */ #define EMC_STATICWAITTURN3_WAITTURN_Msk (0x0fUL << EMC_STATICWAITTURN3_WAITTURN_Pos) /*!< EMC STATICWAITTURN3: WAITTURN Mask */ /* ================================================================================ */ /* ================ struct 'USB0' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------- USB0_CAPLENGTH ------------------------------- */ #define USB0_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB0 CAPLENGTH: CAPLENGTH Position */ #define USB0_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB0_CAPLENGTH_CAPLENGTH_Pos) /*!< USB0 CAPLENGTH: CAPLENGTH Mask */ #define USB0_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB0 CAPLENGTH: HCIVERSION Position */ #define USB0_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB0_CAPLENGTH_HCIVERSION_Pos) /*!< USB0 CAPLENGTH: HCIVERSION Mask */ /* ------------------------------- USB0_HCSPARAMS ------------------------------- */ #define USB0_HCSPARAMS_N_PORTS_Pos 0 /*!< USB0 HCSPARAMS: N_PORTS Position */ #define USB0_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB0_HCSPARAMS_N_PORTS_Pos) /*!< USB0 HCSPARAMS: N_PORTS Mask */ #define USB0_HCSPARAMS_PPC_Pos 4 /*!< USB0 HCSPARAMS: PPC Position */ #define USB0_HCSPARAMS_PPC_Msk (0x01UL << USB0_HCSPARAMS_PPC_Pos) /*!< USB0 HCSPARAMS: PPC Mask */ #define USB0_HCSPARAMS_N_PCC_Pos 8 /*!< USB0 HCSPARAMS: N_PCC Position */ #define USB0_HCSPARAMS_N_PCC_Msk (0x0fUL << USB0_HCSPARAMS_N_PCC_Pos) /*!< USB0 HCSPARAMS: N_PCC Mask */ #define USB0_HCSPARAMS_N_CC_Pos 12 /*!< USB0 HCSPARAMS: N_CC Position */ #define USB0_HCSPARAMS_N_CC_Msk (0x0fUL << USB0_HCSPARAMS_N_CC_Pos) /*!< USB0 HCSPARAMS: N_CC Mask */ #define USB0_HCSPARAMS_PI_Pos 16 /*!< USB0 HCSPARAMS: PI Position */ #define USB0_HCSPARAMS_PI_Msk (0x01UL << USB0_HCSPARAMS_PI_Pos) /*!< USB0 HCSPARAMS: PI Mask */ #define USB0_HCSPARAMS_N_PTT_Pos 20 /*!< USB0 HCSPARAMS: N_PTT Position */ #define USB0_HCSPARAMS_N_PTT_Msk (0x0fUL << USB0_HCSPARAMS_N_PTT_Pos) /*!< USB0 HCSPARAMS: N_PTT Mask */ #define USB0_HCSPARAMS_N_TT_Pos 24 /*!< USB0 HCSPARAMS: N_TT Position */ #define USB0_HCSPARAMS_N_TT_Msk (0x0fUL << USB0_HCSPARAMS_N_TT_Pos) /*!< USB0 HCSPARAMS: N_TT Mask */ /* ------------------------------- USB0_HCCPARAMS ------------------------------- */ #define USB0_HCCPARAMS_ADC_Pos 0 /*!< USB0 HCCPARAMS: ADC Position */ #define USB0_HCCPARAMS_ADC_Msk (0x01UL << USB0_HCCPARAMS_ADC_Pos) /*!< USB0 HCCPARAMS: ADC Mask */ #define USB0_HCCPARAMS_PFL_Pos 1 /*!< USB0 HCCPARAMS: PFL Position */ #define USB0_HCCPARAMS_PFL_Msk (0x01UL << USB0_HCCPARAMS_PFL_Pos) /*!< USB0 HCCPARAMS: PFL Mask */ #define USB0_HCCPARAMS_ASP_Pos 2 /*!< USB0 HCCPARAMS: ASP Position */ #define USB0_HCCPARAMS_ASP_Msk (0x01UL << USB0_HCCPARAMS_ASP_Pos) /*!< USB0 HCCPARAMS: ASP Mask */ #define USB0_HCCPARAMS_IST_Pos 4 /*!< USB0 HCCPARAMS: IST Position */ #define USB0_HCCPARAMS_IST_Msk (0x0fUL << USB0_HCCPARAMS_IST_Pos) /*!< USB0 HCCPARAMS: IST Mask */ #define USB0_HCCPARAMS_EECP_Pos 8 /*!< USB0 HCCPARAMS: EECP Position */ #define USB0_HCCPARAMS_EECP_Msk (0x000000ffUL << USB0_HCCPARAMS_EECP_Pos) /*!< USB0 HCCPARAMS: EECP Mask */ /* ------------------------------- USB0_DCIVERSION ------------------------------ */ #define USB0_DCIVERSION_DCIVERSION_Pos 0 /*!< USB0 DCIVERSION: DCIVERSION Position */ #define USB0_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB0_DCIVERSION_DCIVERSION_Pos) /*!< USB0 DCIVERSION: DCIVERSION Mask */ /* -------------------------------- USB0_USBCMD_D ------------------------------- */ #define USB0_USBCMD_D_RS_Pos 0 /*!< USB0 USBCMD_D: RS Position */ #define USB0_USBCMD_D_RS_Msk (0x01UL << USB0_USBCMD_D_RS_Pos) /*!< USB0 USBCMD_D: RS Mask */ #define USB0_USBCMD_D_RST_Pos 1 /*!< USB0 USBCMD_D: RST Position */ #define USB0_USBCMD_D_RST_Msk (0x01UL << USB0_USBCMD_D_RST_Pos) /*!< USB0 USBCMD_D: RST Mask */ #define USB0_USBCMD_D_SUTW_Pos 13 /*!< USB0 USBCMD_D: SUTW Position */ #define USB0_USBCMD_D_SUTW_Msk (0x01UL << USB0_USBCMD_D_SUTW_Pos) /*!< USB0 USBCMD_D: SUTW Mask */ #define USB0_USBCMD_D_ATDTW_Pos 14 /*!< USB0 USBCMD_D: ATDTW Position */ #define USB0_USBCMD_D_ATDTW_Msk (0x01UL << USB0_USBCMD_D_ATDTW_Pos) /*!< USB0 USBCMD_D: ATDTW Mask */ #define USB0_USBCMD_D_ITC_Pos 16 /*!< USB0 USBCMD_D: ITC Position */ #define USB0_USBCMD_D_ITC_Msk (0x000000ffUL << USB0_USBCMD_D_ITC_Pos) /*!< USB0 USBCMD_D: ITC Mask */ /* -------------------------------- USB0_USBCMD_H ------------------------------- */ #define USB0_USBCMD_H_RS_Pos 0 /*!< USB0 USBCMD_H: RS Position */ #define USB0_USBCMD_H_RS_Msk (0x01UL << USB0_USBCMD_H_RS_Pos) /*!< USB0 USBCMD_H: RS Mask */ #define USB0_USBCMD_H_RST_Pos 1 /*!< USB0 USBCMD_H: RST Position */ #define USB0_USBCMD_H_RST_Msk (0x01UL << USB0_USBCMD_H_RST_Pos) /*!< USB0 USBCMD_H: RST Mask */ #define USB0_USBCMD_H_FS0_Pos 2 /*!< USB0 USBCMD_H: FS0 Position */ #define USB0_USBCMD_H_FS0_Msk (0x01UL << USB0_USBCMD_H_FS0_Pos) /*!< USB0 USBCMD_H: FS0 Mask */ #define USB0_USBCMD_H_FS1_Pos 3 /*!< USB0 USBCMD_H: FS1 Position */ #define USB0_USBCMD_H_FS1_Msk (0x01UL << USB0_USBCMD_H_FS1_Pos) /*!< USB0 USBCMD_H: FS1 Mask */ #define USB0_USBCMD_H_PSE_Pos 4 /*!< USB0 USBCMD_H: PSE Position */ #define USB0_USBCMD_H_PSE_Msk (0x01UL << USB0_USBCMD_H_PSE_Pos) /*!< USB0 USBCMD_H: PSE Mask */ #define USB0_USBCMD_H_ASE_Pos 5 /*!< USB0 USBCMD_H: ASE Position */ #define USB0_USBCMD_H_ASE_Msk (0x01UL << USB0_USBCMD_H_ASE_Pos) /*!< USB0 USBCMD_H: ASE Mask */ #define USB0_USBCMD_H_IAA_Pos 6 /*!< USB0 USBCMD_H: IAA Position */ #define USB0_USBCMD_H_IAA_Msk (0x01UL << USB0_USBCMD_H_IAA_Pos) /*!< USB0 USBCMD_H: IAA Mask */ #define USB0_USBCMD_H_ASP1_0_Pos 8 /*!< USB0 USBCMD_H: ASP1_0 Position */ #define USB0_USBCMD_H_ASP1_0_Msk (0x03UL << USB0_USBCMD_H_ASP1_0_Pos) /*!< USB0 USBCMD_H: ASP1_0 Mask */ #define USB0_USBCMD_H_ASPE_Pos 11 /*!< USB0 USBCMD_H: ASPE Position */ #define USB0_USBCMD_H_ASPE_Msk (0x01UL << USB0_USBCMD_H_ASPE_Pos) /*!< USB0 USBCMD_H: ASPE Mask */ #define USB0_USBCMD_H_FS2_Pos 15 /*!< USB0 USBCMD_H: FS2 Position */ #define USB0_USBCMD_H_FS2_Msk (0x01UL << USB0_USBCMD_H_FS2_Pos) /*!< USB0 USBCMD_H: FS2 Mask */ #define USB0_USBCMD_H_ITC_Pos 16 /*!< USB0 USBCMD_H: ITC Position */ #define USB0_USBCMD_H_ITC_Msk (0x000000ffUL << USB0_USBCMD_H_ITC_Pos) /*!< USB0 USBCMD_H: ITC Mask */ /* -------------------------------- USB0_USBSTS_D ------------------------------- */ #define USB0_USBSTS_D_UI_Pos 0 /*!< USB0 USBSTS_D: UI Position */ #define USB0_USBSTS_D_UI_Msk (0x01UL << USB0_USBSTS_D_UI_Pos) /*!< USB0 USBSTS_D: UI Mask */ #define USB0_USBSTS_D_UEI_Pos 1 /*!< USB0 USBSTS_D: UEI Position */ #define USB0_USBSTS_D_UEI_Msk (0x01UL << USB0_USBSTS_D_UEI_Pos) /*!< USB0 USBSTS_D: UEI Mask */ #define USB0_USBSTS_D_PCI_Pos 2 /*!< USB0 USBSTS_D: PCI Position */ #define USB0_USBSTS_D_PCI_Msk (0x01UL << USB0_USBSTS_D_PCI_Pos) /*!< USB0 USBSTS_D: PCI Mask */ #define USB0_USBSTS_D_AAI_Pos 5 /*!< USB0 USBSTS_D: AAI Position */ #define USB0_USBSTS_D_AAI_Msk (0x01UL << USB0_USBSTS_D_AAI_Pos) /*!< USB0 USBSTS_D: AAI Mask */ #define USB0_USBSTS_D_URI_Pos 6 /*!< USB0 USBSTS_D: URI Position */ #define USB0_USBSTS_D_URI_Msk (0x01UL << USB0_USBSTS_D_URI_Pos) /*!< USB0 USBSTS_D: URI Mask */ #define USB0_USBSTS_D_SRI_Pos 7 /*!< USB0 USBSTS_D: SRI Position */ #define USB0_USBSTS_D_SRI_Msk (0x01UL << USB0_USBSTS_D_SRI_Pos) /*!< USB0 USBSTS_D: SRI Mask */ #define USB0_USBSTS_D_SLI_Pos 8 /*!< USB0 USBSTS_D: SLI Position */ #define USB0_USBSTS_D_SLI_Msk (0x01UL << USB0_USBSTS_D_SLI_Pos) /*!< USB0 USBSTS_D: SLI Mask */ #define USB0_USBSTS_D_NAKI_Pos 16 /*!< USB0 USBSTS_D: NAKI Position */ #define USB0_USBSTS_D_NAKI_Msk (0x01UL << USB0_USBSTS_D_NAKI_Pos) /*!< USB0 USBSTS_D: NAKI Mask */ /* -------------------------------- USB0_USBSTS_H ------------------------------- */ #define USB0_USBSTS_H_UI_Pos 0 /*!< USB0 USBSTS_H: UI Position */ #define USB0_USBSTS_H_UI_Msk (0x01UL << USB0_USBSTS_H_UI_Pos) /*!< USB0 USBSTS_H: UI Mask */ #define USB0_USBSTS_H_UEI_Pos 1 /*!< USB0 USBSTS_H: UEI Position */ #define USB0_USBSTS_H_UEI_Msk (0x01UL << USB0_USBSTS_H_UEI_Pos) /*!< USB0 USBSTS_H: UEI Mask */ #define USB0_USBSTS_H_PCI_Pos 2 /*!< USB0 USBSTS_H: PCI Position */ #define USB0_USBSTS_H_PCI_Msk (0x01UL << USB0_USBSTS_H_PCI_Pos) /*!< USB0 USBSTS_H: PCI Mask */ #define USB0_USBSTS_H_FRI_Pos 3 /*!< USB0 USBSTS_H: FRI Position */ #define USB0_USBSTS_H_FRI_Msk (0x01UL << USB0_USBSTS_H_FRI_Pos) /*!< USB0 USBSTS_H: FRI Mask */ #define USB0_USBSTS_H_AAI_Pos 5 /*!< USB0 USBSTS_H: AAI Position */ #define USB0_USBSTS_H_AAI_Msk (0x01UL << USB0_USBSTS_H_AAI_Pos) /*!< USB0 USBSTS_H: AAI Mask */ #define USB0_USBSTS_H_SRI_Pos 7 /*!< USB0 USBSTS_H: SRI Position */ #define USB0_USBSTS_H_SRI_Msk (0x01UL << USB0_USBSTS_H_SRI_Pos) /*!< USB0 USBSTS_H: SRI Mask */ #define USB0_USBSTS_H_HCH_Pos 12 /*!< USB0 USBSTS_H: HCH Position */ #define USB0_USBSTS_H_HCH_Msk (0x01UL << USB0_USBSTS_H_HCH_Pos) /*!< USB0 USBSTS_H: HCH Mask */ #define USB0_USBSTS_H_RCL_Pos 13 /*!< USB0 USBSTS_H: RCL Position */ #define USB0_USBSTS_H_RCL_Msk (0x01UL << USB0_USBSTS_H_RCL_Pos) /*!< USB0 USBSTS_H: RCL Mask */ #define USB0_USBSTS_H_PS_Pos 14 /*!< USB0 USBSTS_H: PS Position */ #define USB0_USBSTS_H_PS_Msk (0x01UL << USB0_USBSTS_H_PS_Pos) /*!< USB0 USBSTS_H: PS Mask */ #define USB0_USBSTS_H_AS_Pos 15 /*!< USB0 USBSTS_H: AS Position */ #define USB0_USBSTS_H_AS_Msk (0x01UL << USB0_USBSTS_H_AS_Pos) /*!< USB0 USBSTS_H: AS Mask */ #define USB0_USBSTS_H_UAI_Pos 18 /*!< USB0 USBSTS_H: UAI Position */ #define USB0_USBSTS_H_UAI_Msk (0x01UL << USB0_USBSTS_H_UAI_Pos) /*!< USB0 USBSTS_H: UAI Mask */ #define USB0_USBSTS_H_UPI_Pos 19 /*!< USB0 USBSTS_H: UPI Position */ #define USB0_USBSTS_H_UPI_Msk (0x01UL << USB0_USBSTS_H_UPI_Pos) /*!< USB0 USBSTS_H: UPI Mask */ /* ------------------------------- USB0_USBINTR_D ------------------------------- */ #define USB0_USBINTR_D_UE_Pos 0 /*!< USB0 USBINTR_D: UE Position */ #define USB0_USBINTR_D_UE_Msk (0x01UL << USB0_USBINTR_D_UE_Pos) /*!< USB0 USBINTR_D: UE Mask */ #define USB0_USBINTR_D_UEE_Pos 1 /*!< USB0 USBINTR_D: UEE Position */ #define USB0_USBINTR_D_UEE_Msk (0x01UL << USB0_USBINTR_D_UEE_Pos) /*!< USB0 USBINTR_D: UEE Mask */ #define USB0_USBINTR_D_PCE_Pos 2 /*!< USB0 USBINTR_D: PCE Position */ #define USB0_USBINTR_D_PCE_Msk (0x01UL << USB0_USBINTR_D_PCE_Pos) /*!< USB0 USBINTR_D: PCE Mask */ #define USB0_USBINTR_D_URE_Pos 6 /*!< USB0 USBINTR_D: URE Position */ #define USB0_USBINTR_D_URE_Msk (0x01UL << USB0_USBINTR_D_URE_Pos) /*!< USB0 USBINTR_D: URE Mask */ #define USB0_USBINTR_D_SRE_Pos 7 /*!< USB0 USBINTR_D: SRE Position */ #define USB0_USBINTR_D_SRE_Msk (0x01UL << USB0_USBINTR_D_SRE_Pos) /*!< USB0 USBINTR_D: SRE Mask */ #define USB0_USBINTR_D_SLE_Pos 8 /*!< USB0 USBINTR_D: SLE Position */ #define USB0_USBINTR_D_SLE_Msk (0x01UL << USB0_USBINTR_D_SLE_Pos) /*!< USB0 USBINTR_D: SLE Mask */ #define USB0_USBINTR_D_NAKE_Pos 16 /*!< USB0 USBINTR_D: NAKE Position */ #define USB0_USBINTR_D_NAKE_Msk (0x01UL << USB0_USBINTR_D_NAKE_Pos) /*!< USB0 USBINTR_D: NAKE Mask */ /* ------------------------------- USB0_USBINTR_H ------------------------------- */ #define USB0_USBINTR_H_UE_Pos 0 /*!< USB0 USBINTR_H: UE Position */ #define USB0_USBINTR_H_UE_Msk (0x01UL << USB0_USBINTR_H_UE_Pos) /*!< USB0 USBINTR_H: UE Mask */ #define USB0_USBINTR_H_UEE_Pos 1 /*!< USB0 USBINTR_H: UEE Position */ #define USB0_USBINTR_H_UEE_Msk (0x01UL << USB0_USBINTR_H_UEE_Pos) /*!< USB0 USBINTR_H: UEE Mask */ #define USB0_USBINTR_H_PCE_Pos 2 /*!< USB0 USBINTR_H: PCE Position */ #define USB0_USBINTR_H_PCE_Msk (0x01UL << USB0_USBINTR_H_PCE_Pos) /*!< USB0 USBINTR_H: PCE Mask */ #define USB0_USBINTR_H_FRE_Pos 3 /*!< USB0 USBINTR_H: FRE Position */ #define USB0_USBINTR_H_FRE_Msk (0x01UL << USB0_USBINTR_H_FRE_Pos) /*!< USB0 USBINTR_H: FRE Mask */ #define USB0_USBINTR_H_AAE_Pos 5 /*!< USB0 USBINTR_H: AAE Position */ #define USB0_USBINTR_H_AAE_Msk (0x01UL << USB0_USBINTR_H_AAE_Pos) /*!< USB0 USBINTR_H: AAE Mask */ #define USB0_USBINTR_H_SRE_Pos 7 /*!< USB0 USBINTR_H: SRE Position */ #define USB0_USBINTR_H_SRE_Msk (0x01UL << USB0_USBINTR_H_SRE_Pos) /*!< USB0 USBINTR_H: SRE Mask */ #define USB0_USBINTR_H_UAIE_Pos 18 /*!< USB0 USBINTR_H: UAIE Position */ #define USB0_USBINTR_H_UAIE_Msk (0x01UL << USB0_USBINTR_H_UAIE_Pos) /*!< USB0 USBINTR_H: UAIE Mask */ #define USB0_USBINTR_H_UPIA_Pos 19 /*!< USB0 USBINTR_H: UPIA Position */ #define USB0_USBINTR_H_UPIA_Msk (0x01UL << USB0_USBINTR_H_UPIA_Pos) /*!< USB0 USBINTR_H: UPIA Mask */ /* ------------------------------- USB0_FRINDEX_D ------------------------------- */ #define USB0_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_D: FRINDEX2_0 Position */ #define USB0_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_D: FRINDEX2_0 Mask */ #define USB0_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB0 FRINDEX_D: FRINDEX13_3 Position */ #define USB0_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB0_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB0 FRINDEX_D: FRINDEX13_3 Mask */ /* ------------------------------- USB0_FRINDEX_H ------------------------------- */ #define USB0_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB0 FRINDEX_H: FRINDEX2_0 Position */ #define USB0_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB0_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB0 FRINDEX_H: FRINDEX2_0 Mask */ #define USB0_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB0 FRINDEX_H: FRINDEX12_3 Position */ #define USB0_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB0_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB0 FRINDEX_H: FRINDEX12_3 Mask */ /* ------------------------------- USB0_DEVICEADDR ------------------------------ */ #define USB0_DEVICEADDR_USBADRA_Pos 24 /*!< USB0 DEVICEADDR: USBADRA Position */ #define USB0_DEVICEADDR_USBADRA_Msk (0x01UL << USB0_DEVICEADDR_USBADRA_Pos) /*!< USB0 DEVICEADDR: USBADRA Mask */ #define USB0_DEVICEADDR_USBADR_Pos 25 /*!< USB0 DEVICEADDR: USBADR Position */ #define USB0_DEVICEADDR_USBADR_Msk (0x7fUL << USB0_DEVICEADDR_USBADR_Pos) /*!< USB0 DEVICEADDR: USBADR Mask */ /* ---------------------------- USB0_PERIODICLISTBASE --------------------------- */ #define USB0_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB0 PERIODICLISTBASE: PERBASE31_12 Position */ #define USB0_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB0_PERIODICLISTBASE_PERBASE31_12_Pos)/*!< USB0 PERIODICLISTBASE: PERBASE31_12 Mask */ /* ---------------------------- USB0_ENDPOINTLISTADDR --------------------------- */ #define USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Position */ #define USB0_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB0_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB0 ENDPOINTLISTADDR: EPBASE31_11 Mask */ /* ----------------------------- USB0_ASYNCLISTADDR ----------------------------- */ #define USB0_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Position */ #define USB0_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB0_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB0 ASYNCLISTADDR: ASYBASE31_5 Mask */ /* --------------------------------- USB0_TTCTRL -------------------------------- */ #define USB0_TTCTRL_TTHA_Pos 24 /*!< USB0 TTCTRL: TTHA Position */ #define USB0_TTCTRL_TTHA_Msk (0x7fUL << USB0_TTCTRL_TTHA_Pos) /*!< USB0 TTCTRL: TTHA Mask */ /* ------------------------------- USB0_BURSTSIZE ------------------------------- */ #define USB0_BURSTSIZE_RXPBURST_Pos 0 /*!< USB0 BURSTSIZE: RXPBURST Position */ #define USB0_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_RXPBURST_Pos) /*!< USB0 BURSTSIZE: RXPBURST Mask */ #define USB0_BURSTSIZE_TXPBURST_Pos 8 /*!< USB0 BURSTSIZE: TXPBURST Position */ #define USB0_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB0_BURSTSIZE_TXPBURST_Pos) /*!< USB0 BURSTSIZE: TXPBURST Mask */ /* ------------------------------ USB0_TXFILLTUNING ----------------------------- */ #define USB0_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB0 TXFILLTUNING: TXSCHOH Position */ #define USB0_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB0_TXFILLTUNING_TXSCHOH_Pos) /*!< USB0 TXFILLTUNING: TXSCHOH Mask */ #define USB0_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB0 TXFILLTUNING: TXSCHEATLTH Position */ #define USB0_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB0_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB0 TXFILLTUNING: TXSCHEATLTH Mask */ #define USB0_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB0 TXFILLTUNING: TXFIFOTHRES Position */ #define USB0_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB0_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB0 TXFILLTUNING: TXFIFOTHRES Mask */ /* ------------------------------- USB0_BINTERVAL ------------------------------- */ #define USB0_BINTERVAL_BINT_Pos 0 /*!< USB0 BINTERVAL: BINT Position */ #define USB0_BINTERVAL_BINT_Msk (0x0fUL << USB0_BINTERVAL_BINT_Pos) /*!< USB0 BINTERVAL: BINT Mask */ /* -------------------------------- USB0_ENDPTNAK ------------------------------- */ #define USB0_ENDPTNAK_EPRN0_Pos 0 /*!< USB0 ENDPTNAK: EPRN0 Position */ #define USB0_ENDPTNAK_EPRN0_Msk (0x01UL << USB0_ENDPTNAK_EPRN0_Pos) /*!< USB0 ENDPTNAK: EPRN0 Mask */ #define USB0_ENDPTNAK_EPRN1_Pos 1 /*!< USB0 ENDPTNAK: EPRN1 Position */ #define USB0_ENDPTNAK_EPRN1_Msk (0x01UL << USB0_ENDPTNAK_EPRN1_Pos) /*!< USB0 ENDPTNAK: EPRN1 Mask */ #define USB0_ENDPTNAK_EPRN2_Pos 2 /*!< USB0 ENDPTNAK: EPRN2 Position */ #define USB0_ENDPTNAK_EPRN2_Msk (0x01UL << USB0_ENDPTNAK_EPRN2_Pos) /*!< USB0 ENDPTNAK: EPRN2 Mask */ #define USB0_ENDPTNAK_EPRN3_Pos 3 /*!< USB0 ENDPTNAK: EPRN3 Position */ #define USB0_ENDPTNAK_EPRN3_Msk (0x01UL << USB0_ENDPTNAK_EPRN3_Pos) /*!< USB0 ENDPTNAK: EPRN3 Mask */ #define USB0_ENDPTNAK_EPRN4_Pos 4 /*!< USB0 ENDPTNAK: EPRN4 Position */ #define USB0_ENDPTNAK_EPRN4_Msk (0x01UL << USB0_ENDPTNAK_EPRN4_Pos) /*!< USB0 ENDPTNAK: EPRN4 Mask */ #define USB0_ENDPTNAK_EPRN5_Pos 5 /*!< USB0 ENDPTNAK: EPRN5 Position */ #define USB0_ENDPTNAK_EPRN5_Msk (0x01UL << USB0_ENDPTNAK_EPRN5_Pos) /*!< USB0 ENDPTNAK: EPRN5 Mask */ #define USB0_ENDPTNAK_EPTN0_Pos 16 /*!< USB0 ENDPTNAK: EPTN0 Position */ #define USB0_ENDPTNAK_EPTN0_Msk (0x01UL << USB0_ENDPTNAK_EPTN0_Pos) /*!< USB0 ENDPTNAK: EPTN0 Mask */ #define USB0_ENDPTNAK_EPTN1_Pos 17 /*!< USB0 ENDPTNAK: EPTN1 Position */ #define USB0_ENDPTNAK_EPTN1_Msk (0x01UL << USB0_ENDPTNAK_EPTN1_Pos) /*!< USB0 ENDPTNAK: EPTN1 Mask */ #define USB0_ENDPTNAK_EPTN2_Pos 18 /*!< USB0 ENDPTNAK: EPTN2 Position */ #define USB0_ENDPTNAK_EPTN2_Msk (0x01UL << USB0_ENDPTNAK_EPTN2_Pos) /*!< USB0 ENDPTNAK: EPTN2 Mask */ #define USB0_ENDPTNAK_EPTN3_Pos 19 /*!< USB0 ENDPTNAK: EPTN3 Position */ #define USB0_ENDPTNAK_EPTN3_Msk (0x01UL << USB0_ENDPTNAK_EPTN3_Pos) /*!< USB0 ENDPTNAK: EPTN3 Mask */ #define USB0_ENDPTNAK_EPTN4_Pos 20 /*!< USB0 ENDPTNAK: EPTN4 Position */ #define USB0_ENDPTNAK_EPTN4_Msk (0x01UL << USB0_ENDPTNAK_EPTN4_Pos) /*!< USB0 ENDPTNAK: EPTN4 Mask */ #define USB0_ENDPTNAK_EPTN5_Pos 21 /*!< USB0 ENDPTNAK: EPTN5 Position */ #define USB0_ENDPTNAK_EPTN5_Msk (0x01UL << USB0_ENDPTNAK_EPTN5_Pos) /*!< USB0 ENDPTNAK: EPTN5 Mask */ /* ------------------------------- USB0_ENDPTNAKEN ------------------------------ */ #define USB0_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB0 ENDPTNAKEN: EPRNE0 Position */ #define USB0_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE0_Pos) /*!< USB0 ENDPTNAKEN: EPRNE0 Mask */ #define USB0_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB0 ENDPTNAKEN: EPRNE1 Position */ #define USB0_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE1_Pos) /*!< USB0 ENDPTNAKEN: EPRNE1 Mask */ #define USB0_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB0 ENDPTNAKEN: EPRNE2 Position */ #define USB0_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE2_Pos) /*!< USB0 ENDPTNAKEN: EPRNE2 Mask */ #define USB0_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB0 ENDPTNAKEN: EPRNE3 Position */ #define USB0_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE3_Pos) /*!< USB0 ENDPTNAKEN: EPRNE3 Mask */ #define USB0_ENDPTNAKEN_EPRNE4_Pos 4 /*!< USB0 ENDPTNAKEN: EPRNE4 Position */ #define USB0_ENDPTNAKEN_EPRNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE4_Pos) /*!< USB0 ENDPTNAKEN: EPRNE4 Mask */ #define USB0_ENDPTNAKEN_EPRNE5_Pos 5 /*!< USB0 ENDPTNAKEN: EPRNE5 Position */ #define USB0_ENDPTNAKEN_EPRNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPRNE5_Pos) /*!< USB0 ENDPTNAKEN: EPRNE5 Mask */ #define USB0_ENDPTNAKEN_EPTNE0_Pos 16 /*!< USB0 ENDPTNAKEN: EPTNE0 Position */ #define USB0_ENDPTNAKEN_EPTNE0_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE0_Pos) /*!< USB0 ENDPTNAKEN: EPTNE0 Mask */ #define USB0_ENDPTNAKEN_EPTNE1_Pos 17 /*!< USB0 ENDPTNAKEN: EPTNE1 Position */ #define USB0_ENDPTNAKEN_EPTNE1_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE1_Pos) /*!< USB0 ENDPTNAKEN: EPTNE1 Mask */ #define USB0_ENDPTNAKEN_EPTNE2_Pos 18 /*!< USB0 ENDPTNAKEN: EPTNE2 Position */ #define USB0_ENDPTNAKEN_EPTNE2_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE2_Pos) /*!< USB0 ENDPTNAKEN: EPTNE2 Mask */ #define USB0_ENDPTNAKEN_EPTNE3_Pos 19 /*!< USB0 ENDPTNAKEN: EPTNE3 Position */ #define USB0_ENDPTNAKEN_EPTNE3_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE3_Pos) /*!< USB0 ENDPTNAKEN: EPTNE3 Mask */ #define USB0_ENDPTNAKEN_EPTNE4_Pos 20 /*!< USB0 ENDPTNAKEN: EPTNE4 Position */ #define USB0_ENDPTNAKEN_EPTNE4_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE4_Pos) /*!< USB0 ENDPTNAKEN: EPTNE4 Mask */ #define USB0_ENDPTNAKEN_EPTNE5_Pos 21 /*!< USB0 ENDPTNAKEN: EPTNE5 Position */ #define USB0_ENDPTNAKEN_EPTNE5_Msk (0x01UL << USB0_ENDPTNAKEN_EPTNE5_Pos) /*!< USB0 ENDPTNAKEN: EPTNE5 Mask */ /* ------------------------------- USB0_PORTSC1_D ------------------------------- */ #define USB0_PORTSC1_D_CCS_Pos 0 /*!< USB0 PORTSC1_D: CCS Position */ #define USB0_PORTSC1_D_CCS_Msk (0x01UL << USB0_PORTSC1_D_CCS_Pos) /*!< USB0 PORTSC1_D: CCS Mask */ #define USB0_PORTSC1_D_PE_Pos 2 /*!< USB0 PORTSC1_D: PE Position */ #define USB0_PORTSC1_D_PE_Msk (0x01UL << USB0_PORTSC1_D_PE_Pos) /*!< USB0 PORTSC1_D: PE Mask */ #define USB0_PORTSC1_D_PEC_Pos 3 /*!< USB0 PORTSC1_D: PEC Position */ #define USB0_PORTSC1_D_PEC_Msk (0x01UL << USB0_PORTSC1_D_PEC_Pos) /*!< USB0 PORTSC1_D: PEC Mask */ #define USB0_PORTSC1_D_FPR_Pos 6 /*!< USB0 PORTSC1_D: FPR Position */ #define USB0_PORTSC1_D_FPR_Msk (0x01UL << USB0_PORTSC1_D_FPR_Pos) /*!< USB0 PORTSC1_D: FPR Mask */ #define USB0_PORTSC1_D_SUSP_Pos 7 /*!< USB0 PORTSC1_D: SUSP Position */ #define USB0_PORTSC1_D_SUSP_Msk (0x01UL << USB0_PORTSC1_D_SUSP_Pos) /*!< USB0 PORTSC1_D: SUSP Mask */ #define USB0_PORTSC1_D_PR_Pos 8 /*!< USB0 PORTSC1_D: PR Position */ #define USB0_PORTSC1_D_PR_Msk (0x01UL << USB0_PORTSC1_D_PR_Pos) /*!< USB0 PORTSC1_D: PR Mask */ #define USB0_PORTSC1_D_HSP_Pos 9 /*!< USB0 PORTSC1_D: HSP Position */ #define USB0_PORTSC1_D_HSP_Msk (0x01UL << USB0_PORTSC1_D_HSP_Pos) /*!< USB0 PORTSC1_D: HSP Mask */ #define USB0_PORTSC1_D_PIC1_0_Pos 14 /*!< USB0 PORTSC1_D: PIC1_0 Position */ #define USB0_PORTSC1_D_PIC1_0_Msk (0x03UL << USB0_PORTSC1_D_PIC1_0_Pos) /*!< USB0 PORTSC1_D: PIC1_0 Mask */ #define USB0_PORTSC1_D_PTC3_0_Pos 16 /*!< USB0 PORTSC1_D: PTC3_0 Position */ #define USB0_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_D_PTC3_0_Pos) /*!< USB0 PORTSC1_D: PTC3_0 Mask */ #define USB0_PORTSC1_D_PHCD_Pos 23 /*!< USB0 PORTSC1_D: PHCD Position */ #define USB0_PORTSC1_D_PHCD_Msk (0x01UL << USB0_PORTSC1_D_PHCD_Pos) /*!< USB0 PORTSC1_D: PHCD Mask */ #define USB0_PORTSC1_D_PFSC_Pos 24 /*!< USB0 PORTSC1_D: PFSC Position */ #define USB0_PORTSC1_D_PFSC_Msk (0x01UL << USB0_PORTSC1_D_PFSC_Pos) /*!< USB0 PORTSC1_D: PFSC Mask */ #define USB0_PORTSC1_D_PSPD_Pos 26 /*!< USB0 PORTSC1_D: PSPD Position */ #define USB0_PORTSC1_D_PSPD_Msk (0x03UL << USB0_PORTSC1_D_PSPD_Pos) /*!< USB0 PORTSC1_D: PSPD Mask */ /* ------------------------------- USB0_PORTSC1_H ------------------------------- */ #define USB0_PORTSC1_H_CCS_Pos 0 /*!< USB0 PORTSC1_H: CCS Position */ #define USB0_PORTSC1_H_CCS_Msk (0x01UL << USB0_PORTSC1_H_CCS_Pos) /*!< USB0 PORTSC1_H: CCS Mask */ #define USB0_PORTSC1_H_CSC_Pos 1 /*!< USB0 PORTSC1_H: CSC Position */ #define USB0_PORTSC1_H_CSC_Msk (0x01UL << USB0_PORTSC1_H_CSC_Pos) /*!< USB0 PORTSC1_H: CSC Mask */ #define USB0_PORTSC1_H_PE_Pos 2 /*!< USB0 PORTSC1_H: PE Position */ #define USB0_PORTSC1_H_PE_Msk (0x01UL << USB0_PORTSC1_H_PE_Pos) /*!< USB0 PORTSC1_H: PE Mask */ #define USB0_PORTSC1_H_PEC_Pos 3 /*!< USB0 PORTSC1_H: PEC Position */ #define USB0_PORTSC1_H_PEC_Msk (0x01UL << USB0_PORTSC1_H_PEC_Pos) /*!< USB0 PORTSC1_H: PEC Mask */ #define USB0_PORTSC1_H_OCA_Pos 4 /*!< USB0 PORTSC1_H: OCA Position */ #define USB0_PORTSC1_H_OCA_Msk (0x01UL << USB0_PORTSC1_H_OCA_Pos) /*!< USB0 PORTSC1_H: OCA Mask */ #define USB0_PORTSC1_H_OCC_Pos 5 /*!< USB0 PORTSC1_H: OCC Position */ #define USB0_PORTSC1_H_OCC_Msk (0x01UL << USB0_PORTSC1_H_OCC_Pos) /*!< USB0 PORTSC1_H: OCC Mask */ #define USB0_PORTSC1_H_FPR_Pos 6 /*!< USB0 PORTSC1_H: FPR Position */ #define USB0_PORTSC1_H_FPR_Msk (0x01UL << USB0_PORTSC1_H_FPR_Pos) /*!< USB0 PORTSC1_H: FPR Mask */ #define USB0_PORTSC1_H_SUSP_Pos 7 /*!< USB0 PORTSC1_H: SUSP Position */ #define USB0_PORTSC1_H_SUSP_Msk (0x01UL << USB0_PORTSC1_H_SUSP_Pos) /*!< USB0 PORTSC1_H: SUSP Mask */ #define USB0_PORTSC1_H_PR_Pos 8 /*!< USB0 PORTSC1_H: PR Position */ #define USB0_PORTSC1_H_PR_Msk (0x01UL << USB0_PORTSC1_H_PR_Pos) /*!< USB0 PORTSC1_H: PR Mask */ #define USB0_PORTSC1_H_HSP_Pos 9 /*!< USB0 PORTSC1_H: HSP Position */ #define USB0_PORTSC1_H_HSP_Msk (0x01UL << USB0_PORTSC1_H_HSP_Pos) /*!< USB0 PORTSC1_H: HSP Mask */ #define USB0_PORTSC1_H_LS_Pos 10 /*!< USB0 PORTSC1_H: LS Position */ #define USB0_PORTSC1_H_LS_Msk (0x03UL << USB0_PORTSC1_H_LS_Pos) /*!< USB0 PORTSC1_H: LS Mask */ #define USB0_PORTSC1_H_PP_Pos 12 /*!< USB0 PORTSC1_H: PP Position */ #define USB0_PORTSC1_H_PP_Msk (0x01UL << USB0_PORTSC1_H_PP_Pos) /*!< USB0 PORTSC1_H: PP Mask */ #define USB0_PORTSC1_H_PIC1_0_Pos 14 /*!< USB0 PORTSC1_H: PIC1_0 Position */ #define USB0_PORTSC1_H_PIC1_0_Msk (0x03UL << USB0_PORTSC1_H_PIC1_0_Pos) /*!< USB0 PORTSC1_H: PIC1_0 Mask */ #define USB0_PORTSC1_H_PTC3_0_Pos 16 /*!< USB0 PORTSC1_H: PTC3_0 Position */ #define USB0_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB0_PORTSC1_H_PTC3_0_Pos) /*!< USB0 PORTSC1_H: PTC3_0 Mask */ #define USB0_PORTSC1_H_WKCN_Pos 20 /*!< USB0 PORTSC1_H: WKCN Position */ #define USB0_PORTSC1_H_WKCN_Msk (0x01UL << USB0_PORTSC1_H_WKCN_Pos) /*!< USB0 PORTSC1_H: WKCN Mask */ #define USB0_PORTSC1_H_WKDC_Pos 21 /*!< USB0 PORTSC1_H: WKDC Position */ #define USB0_PORTSC1_H_WKDC_Msk (0x01UL << USB0_PORTSC1_H_WKDC_Pos) /*!< USB0 PORTSC1_H: WKDC Mask */ #define USB0_PORTSC1_H_WKOC_Pos 22 /*!< USB0 PORTSC1_H: WKOC Position */ #define USB0_PORTSC1_H_WKOC_Msk (0x01UL << USB0_PORTSC1_H_WKOC_Pos) /*!< USB0 PORTSC1_H: WKOC Mask */ #define USB0_PORTSC1_H_PHCD_Pos 23 /*!< USB0 PORTSC1_H: PHCD Position */ #define USB0_PORTSC1_H_PHCD_Msk (0x01UL << USB0_PORTSC1_H_PHCD_Pos) /*!< USB0 PORTSC1_H: PHCD Mask */ #define USB0_PORTSC1_H_PFSC_Pos 24 /*!< USB0 PORTSC1_H: PFSC Position */ #define USB0_PORTSC1_H_PFSC_Msk (0x01UL << USB0_PORTSC1_H_PFSC_Pos) /*!< USB0 PORTSC1_H: PFSC Mask */ #define USB0_PORTSC1_H_PSPD_Pos 26 /*!< USB0 PORTSC1_H: PSPD Position */ #define USB0_PORTSC1_H_PSPD_Msk (0x03UL << USB0_PORTSC1_H_PSPD_Pos) /*!< USB0 PORTSC1_H: PSPD Mask */ /* --------------------------------- USB0_OTGSC --------------------------------- */ #define USB0_OTGSC_VD_Pos 0 /*!< USB0 OTGSC: VD Position */ #define USB0_OTGSC_VD_Msk (0x01UL << USB0_OTGSC_VD_Pos) /*!< USB0 OTGSC: VD Mask */ #define USB0_OTGSC_VC_Pos 1 /*!< USB0 OTGSC: VC Position */ #define USB0_OTGSC_VC_Msk (0x01UL << USB0_OTGSC_VC_Pos) /*!< USB0 OTGSC: VC Mask */ #define USB0_OTGSC_HAAR_Pos 2 /*!< USB0 OTGSC: HAAR Position */ #define USB0_OTGSC_HAAR_Msk (0x01UL << USB0_OTGSC_HAAR_Pos) /*!< USB0 OTGSC: HAAR Mask */ #define USB0_OTGSC_OT_Pos 3 /*!< USB0 OTGSC: OT Position */ #define USB0_OTGSC_OT_Msk (0x01UL << USB0_OTGSC_OT_Pos) /*!< USB0 OTGSC: OT Mask */ #define USB0_OTGSC_DP_Pos 4 /*!< USB0 OTGSC: DP Position */ #define USB0_OTGSC_DP_Msk (0x01UL << USB0_OTGSC_DP_Pos) /*!< USB0 OTGSC: DP Mask */ #define USB0_OTGSC_IDPU_Pos 5 /*!< USB0 OTGSC: IDPU Position */ #define USB0_OTGSC_IDPU_Msk (0x01UL << USB0_OTGSC_IDPU_Pos) /*!< USB0 OTGSC: IDPU Mask */ #define USB0_OTGSC_HADP_Pos 6 /*!< USB0 OTGSC: HADP Position */ #define USB0_OTGSC_HADP_Msk (0x01UL << USB0_OTGSC_HADP_Pos) /*!< USB0 OTGSC: HADP Mask */ #define USB0_OTGSC_HABA_Pos 7 /*!< USB0 OTGSC: HABA Position */ #define USB0_OTGSC_HABA_Msk (0x01UL << USB0_OTGSC_HABA_Pos) /*!< USB0 OTGSC: HABA Mask */ #define USB0_OTGSC_ID_Pos 8 /*!< USB0 OTGSC: ID Position */ #define USB0_OTGSC_ID_Msk (0x01UL << USB0_OTGSC_ID_Pos) /*!< USB0 OTGSC: ID Mask */ #define USB0_OTGSC_AVV_Pos 9 /*!< USB0 OTGSC: AVV Position */ #define USB0_OTGSC_AVV_Msk (0x01UL << USB0_OTGSC_AVV_Pos) /*!< USB0 OTGSC: AVV Mask */ #define USB0_OTGSC_ASV_Pos 10 /*!< USB0 OTGSC: ASV Position */ #define USB0_OTGSC_ASV_Msk (0x01UL << USB0_OTGSC_ASV_Pos) /*!< USB0 OTGSC: ASV Mask */ #define USB0_OTGSC_BSV_Pos 11 /*!< USB0 OTGSC: BSV Position */ #define USB0_OTGSC_BSV_Msk (0x01UL << USB0_OTGSC_BSV_Pos) /*!< USB0 OTGSC: BSV Mask */ #define USB0_OTGSC_BSE_Pos 12 /*!< USB0 OTGSC: BSE Position */ #define USB0_OTGSC_BSE_Msk (0x01UL << USB0_OTGSC_BSE_Pos) /*!< USB0 OTGSC: BSE Mask */ #define USB0_OTGSC_MS1T_Pos 13 /*!< USB0 OTGSC: MS1T Position */ #define USB0_OTGSC_MS1T_Msk (0x01UL << USB0_OTGSC_MS1T_Pos) /*!< USB0 OTGSC: MS1T Mask */ #define USB0_OTGSC_DPS_Pos 14 /*!< USB0 OTGSC: DPS Position */ #define USB0_OTGSC_DPS_Msk (0x01UL << USB0_OTGSC_DPS_Pos) /*!< USB0 OTGSC: DPS Mask */ #define USB0_OTGSC_IDIS_Pos 16 /*!< USB0 OTGSC: IDIS Position */ #define USB0_OTGSC_IDIS_Msk (0x01UL << USB0_OTGSC_IDIS_Pos) /*!< USB0 OTGSC: IDIS Mask */ #define USB0_OTGSC_AVVIS_Pos 17 /*!< USB0 OTGSC: AVVIS Position */ #define USB0_OTGSC_AVVIS_Msk (0x01UL << USB0_OTGSC_AVVIS_Pos) /*!< USB0 OTGSC: AVVIS Mask */ #define USB0_OTGSC_ASVIS_Pos 18 /*!< USB0 OTGSC: ASVIS Position */ #define USB0_OTGSC_ASVIS_Msk (0x01UL << USB0_OTGSC_ASVIS_Pos) /*!< USB0 OTGSC: ASVIS Mask */ #define USB0_OTGSC_BSVIS_Pos 19 /*!< USB0 OTGSC: BSVIS Position */ #define USB0_OTGSC_BSVIS_Msk (0x01UL << USB0_OTGSC_BSVIS_Pos) /*!< USB0 OTGSC: BSVIS Mask */ #define USB0_OTGSC_BSEIS_Pos 20 /*!< USB0 OTGSC: BSEIS Position */ #define USB0_OTGSC_BSEIS_Msk (0x01UL << USB0_OTGSC_BSEIS_Pos) /*!< USB0 OTGSC: BSEIS Mask */ #define USB0_OTGSC_ms1S_Pos 21 /*!< USB0 OTGSC: ms1S Position */ #define USB0_OTGSC_ms1S_Msk (0x01UL << USB0_OTGSC_ms1S_Pos) /*!< USB0 OTGSC: ms1S Mask */ #define USB0_OTGSC_DPIS_Pos 22 /*!< USB0 OTGSC: DPIS Position */ #define USB0_OTGSC_DPIS_Msk (0x01UL << USB0_OTGSC_DPIS_Pos) /*!< USB0 OTGSC: DPIS Mask */ #define USB0_OTGSC_IDIE_Pos 24 /*!< USB0 OTGSC: IDIE Position */ #define USB0_OTGSC_IDIE_Msk (0x01UL << USB0_OTGSC_IDIE_Pos) /*!< USB0 OTGSC: IDIE Mask */ #define USB0_OTGSC_AVVIE_Pos 25 /*!< USB0 OTGSC: AVVIE Position */ #define USB0_OTGSC_AVVIE_Msk (0x01UL << USB0_OTGSC_AVVIE_Pos) /*!< USB0 OTGSC: AVVIE Mask */ #define USB0_OTGSC_ASVIE_Pos 26 /*!< USB0 OTGSC: ASVIE Position */ #define USB0_OTGSC_ASVIE_Msk (0x01UL << USB0_OTGSC_ASVIE_Pos) /*!< USB0 OTGSC: ASVIE Mask */ #define USB0_OTGSC_BSVIE_Pos 27 /*!< USB0 OTGSC: BSVIE Position */ #define USB0_OTGSC_BSVIE_Msk (0x01UL << USB0_OTGSC_BSVIE_Pos) /*!< USB0 OTGSC: BSVIE Mask */ #define USB0_OTGSC_BSEIE_Pos 28 /*!< USB0 OTGSC: BSEIE Position */ #define USB0_OTGSC_BSEIE_Msk (0x01UL << USB0_OTGSC_BSEIE_Pos) /*!< USB0 OTGSC: BSEIE Mask */ #define USB0_OTGSC_MS1E_Pos 29 /*!< USB0 OTGSC: MS1E Position */ #define USB0_OTGSC_MS1E_Msk (0x01UL << USB0_OTGSC_MS1E_Pos) /*!< USB0 OTGSC: MS1E Mask */ #define USB0_OTGSC_DPIE_Pos 30 /*!< USB0 OTGSC: DPIE Position */ #define USB0_OTGSC_DPIE_Msk (0x01UL << USB0_OTGSC_DPIE_Pos) /*!< USB0 OTGSC: DPIE Mask */ /* ------------------------------- USB0_USBMODE_D ------------------------------- */ #define USB0_USBMODE_D_CM1_0_Pos 0 /*!< USB0 USBMODE_D: CM1_0 Position */ #define USB0_USBMODE_D_CM1_0_Msk (0x03UL << USB0_USBMODE_D_CM1_0_Pos) /*!< USB0 USBMODE_D: CM1_0 Mask */ #define USB0_USBMODE_D_ES_Pos 2 /*!< USB0 USBMODE_D: ES Position */ #define USB0_USBMODE_D_ES_Msk (0x01UL << USB0_USBMODE_D_ES_Pos) /*!< USB0 USBMODE_D: ES Mask */ #define USB0_USBMODE_D_SLOM_Pos 3 /*!< USB0 USBMODE_D: SLOM Position */ #define USB0_USBMODE_D_SLOM_Msk (0x01UL << USB0_USBMODE_D_SLOM_Pos) /*!< USB0 USBMODE_D: SLOM Mask */ #define USB0_USBMODE_D_SDIS_Pos 4 /*!< USB0 USBMODE_D: SDIS Position */ #define USB0_USBMODE_D_SDIS_Msk (0x01UL << USB0_USBMODE_D_SDIS_Pos) /*!< USB0 USBMODE_D: SDIS Mask */ /* ------------------------------- USB0_USBMODE_H ------------------------------- */ #define USB0_USBMODE_H_CM_Pos 0 /*!< USB0 USBMODE_H: CM Position */ #define USB0_USBMODE_H_CM_Msk (0x03UL << USB0_USBMODE_H_CM_Pos) /*!< USB0 USBMODE_H: CM Mask */ #define USB0_USBMODE_H_ES_Pos 2 /*!< USB0 USBMODE_H: ES Position */ #define USB0_USBMODE_H_ES_Msk (0x01UL << USB0_USBMODE_H_ES_Pos) /*!< USB0 USBMODE_H: ES Mask */ #define USB0_USBMODE_H_SDIS_Pos 4 /*!< USB0 USBMODE_H: SDIS Position */ #define USB0_USBMODE_H_SDIS_Msk (0x01UL << USB0_USBMODE_H_SDIS_Pos) /*!< USB0 USBMODE_H: SDIS Mask */ #define USB0_USBMODE_H_VBPS_Pos 5 /*!< USB0 USBMODE_H: VBPS Position */ #define USB0_USBMODE_H_VBPS_Msk (0x01UL << USB0_USBMODE_H_VBPS_Pos) /*!< USB0 USBMODE_H: VBPS Mask */ /* ----------------------------- USB0_ENDPTSETUPSTAT ---------------------------- */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos 4 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Position */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT4_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT4 Mask */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos 5 /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Position */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Msk (0x01UL << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT5_Pos) /*!< USB0 ENDPTSETUPSTAT: ENDPTSETUPSTAT5 Mask */ /* ------------------------------- USB0_ENDPTPRIME ------------------------------ */ #define USB0_ENDPTPRIME_PERB0_Pos 0 /*!< USB0 ENDPTPRIME: PERB0 Position */ #define USB0_ENDPTPRIME_PERB0_Msk (0x01UL << USB0_ENDPTPRIME_PERB0_Pos) /*!< USB0 ENDPTPRIME: PERB0 Mask */ #define USB0_ENDPTPRIME_PERB1_Pos 1 /*!< USB0 ENDPTPRIME: PERB1 Position */ #define USB0_ENDPTPRIME_PERB1_Msk (0x01UL << USB0_ENDPTPRIME_PERB1_Pos) /*!< USB0 ENDPTPRIME: PERB1 Mask */ #define USB0_ENDPTPRIME_PERB2_Pos 2 /*!< USB0 ENDPTPRIME: PERB2 Position */ #define USB0_ENDPTPRIME_PERB2_Msk (0x01UL << USB0_ENDPTPRIME_PERB2_Pos) /*!< USB0 ENDPTPRIME: PERB2 Mask */ #define USB0_ENDPTPRIME_PERB3_Pos 3 /*!< USB0 ENDPTPRIME: PERB3 Position */ #define USB0_ENDPTPRIME_PERB3_Msk (0x01UL << USB0_ENDPTPRIME_PERB3_Pos) /*!< USB0 ENDPTPRIME: PERB3 Mask */ #define USB0_ENDPTPRIME_PERB4_Pos 4 /*!< USB0 ENDPTPRIME: PERB4 Position */ #define USB0_ENDPTPRIME_PERB4_Msk (0x01UL << USB0_ENDPTPRIME_PERB4_Pos) /*!< USB0 ENDPTPRIME: PERB4 Mask */ #define USB0_ENDPTPRIME_PERB5_Pos 5 /*!< USB0 ENDPTPRIME: PERB5 Position */ #define USB0_ENDPTPRIME_PERB5_Msk (0x01UL << USB0_ENDPTPRIME_PERB5_Pos) /*!< USB0 ENDPTPRIME: PERB5 Mask */ #define USB0_ENDPTPRIME_PETB0_Pos 16 /*!< USB0 ENDPTPRIME: PETB0 Position */ #define USB0_ENDPTPRIME_PETB0_Msk (0x01UL << USB0_ENDPTPRIME_PETB0_Pos) /*!< USB0 ENDPTPRIME: PETB0 Mask */ #define USB0_ENDPTPRIME_PETB1_Pos 17 /*!< USB0 ENDPTPRIME: PETB1 Position */ #define USB0_ENDPTPRIME_PETB1_Msk (0x01UL << USB0_ENDPTPRIME_PETB1_Pos) /*!< USB0 ENDPTPRIME: PETB1 Mask */ #define USB0_ENDPTPRIME_PETB2_Pos 18 /*!< USB0 ENDPTPRIME: PETB2 Position */ #define USB0_ENDPTPRIME_PETB2_Msk (0x01UL << USB0_ENDPTPRIME_PETB2_Pos) /*!< USB0 ENDPTPRIME: PETB2 Mask */ #define USB0_ENDPTPRIME_PETB3_Pos 19 /*!< USB0 ENDPTPRIME: PETB3 Position */ #define USB0_ENDPTPRIME_PETB3_Msk (0x01UL << USB0_ENDPTPRIME_PETB3_Pos) /*!< USB0 ENDPTPRIME: PETB3 Mask */ #define USB0_ENDPTPRIME_PETB4_Pos 20 /*!< USB0 ENDPTPRIME: PETB4 Position */ #define USB0_ENDPTPRIME_PETB4_Msk (0x01UL << USB0_ENDPTPRIME_PETB4_Pos) /*!< USB0 ENDPTPRIME: PETB4 Mask */ #define USB0_ENDPTPRIME_PETB5_Pos 21 /*!< USB0 ENDPTPRIME: PETB5 Position */ #define USB0_ENDPTPRIME_PETB5_Msk (0x01UL << USB0_ENDPTPRIME_PETB5_Pos) /*!< USB0 ENDPTPRIME: PETB5 Mask */ /* ------------------------------- USB0_ENDPTFLUSH ------------------------------ */ #define USB0_ENDPTFLUSH_FERB0_Pos 0 /*!< USB0 ENDPTFLUSH: FERB0 Position */ #define USB0_ENDPTFLUSH_FERB0_Msk (0x01UL << USB0_ENDPTFLUSH_FERB0_Pos) /*!< USB0 ENDPTFLUSH: FERB0 Mask */ #define USB0_ENDPTFLUSH_FERB1_Pos 1 /*!< USB0 ENDPTFLUSH: FERB1 Position */ #define USB0_ENDPTFLUSH_FERB1_Msk (0x01UL << USB0_ENDPTFLUSH_FERB1_Pos) /*!< USB0 ENDPTFLUSH: FERB1 Mask */ #define USB0_ENDPTFLUSH_FERB2_Pos 2 /*!< USB0 ENDPTFLUSH: FERB2 Position */ #define USB0_ENDPTFLUSH_FERB2_Msk (0x01UL << USB0_ENDPTFLUSH_FERB2_Pos) /*!< USB0 ENDPTFLUSH: FERB2 Mask */ #define USB0_ENDPTFLUSH_FERB3_Pos 3 /*!< USB0 ENDPTFLUSH: FERB3 Position */ #define USB0_ENDPTFLUSH_FERB3_Msk (0x01UL << USB0_ENDPTFLUSH_FERB3_Pos) /*!< USB0 ENDPTFLUSH: FERB3 Mask */ #define USB0_ENDPTFLUSH_FERB4_Pos 4 /*!< USB0 ENDPTFLUSH: FERB4 Position */ #define USB0_ENDPTFLUSH_FERB4_Msk (0x01UL << USB0_ENDPTFLUSH_FERB4_Pos) /*!< USB0 ENDPTFLUSH: FERB4 Mask */ #define USB0_ENDPTFLUSH_FERB5_Pos 5 /*!< USB0 ENDPTFLUSH: FERB5 Position */ #define USB0_ENDPTFLUSH_FERB5_Msk (0x01UL << USB0_ENDPTFLUSH_FERB5_Pos) /*!< USB0 ENDPTFLUSH: FERB5 Mask */ #define USB0_ENDPTFLUSH_FETB0_Pos 16 /*!< USB0 ENDPTFLUSH: FETB0 Position */ #define USB0_ENDPTFLUSH_FETB0_Msk (0x01UL << USB0_ENDPTFLUSH_FETB0_Pos) /*!< USB0 ENDPTFLUSH: FETB0 Mask */ #define USB0_ENDPTFLUSH_FETB1_Pos 17 /*!< USB0 ENDPTFLUSH: FETB1 Position */ #define USB0_ENDPTFLUSH_FETB1_Msk (0x01UL << USB0_ENDPTFLUSH_FETB1_Pos) /*!< USB0 ENDPTFLUSH: FETB1 Mask */ #define USB0_ENDPTFLUSH_FETB2_Pos 18 /*!< USB0 ENDPTFLUSH: FETB2 Position */ #define USB0_ENDPTFLUSH_FETB2_Msk (0x01UL << USB0_ENDPTFLUSH_FETB2_Pos) /*!< USB0 ENDPTFLUSH: FETB2 Mask */ #define USB0_ENDPTFLUSH_FETB3_Pos 19 /*!< USB0 ENDPTFLUSH: FETB3 Position */ #define USB0_ENDPTFLUSH_FETB3_Msk (0x01UL << USB0_ENDPTFLUSH_FETB3_Pos) /*!< USB0 ENDPTFLUSH: FETB3 Mask */ #define USB0_ENDPTFLUSH_FETB4_Pos 20 /*!< USB0 ENDPTFLUSH: FETB4 Position */ #define USB0_ENDPTFLUSH_FETB4_Msk (0x01UL << USB0_ENDPTFLUSH_FETB4_Pos) /*!< USB0 ENDPTFLUSH: FETB4 Mask */ #define USB0_ENDPTFLUSH_FETB5_Pos 21 /*!< USB0 ENDPTFLUSH: FETB5 Position */ #define USB0_ENDPTFLUSH_FETB5_Msk (0x01UL << USB0_ENDPTFLUSH_FETB5_Pos) /*!< USB0 ENDPTFLUSH: FETB5 Mask */ /* ------------------------------- USB0_ENDPTSTAT ------------------------------- */ #define USB0_ENDPTSTAT_ERBR0_Pos 0 /*!< USB0 ENDPTSTAT: ERBR0 Position */ #define USB0_ENDPTSTAT_ERBR0_Msk (0x01UL << USB0_ENDPTSTAT_ERBR0_Pos) /*!< USB0 ENDPTSTAT: ERBR0 Mask */ #define USB0_ENDPTSTAT_ERBR1_Pos 1 /*!< USB0 ENDPTSTAT: ERBR1 Position */ #define USB0_ENDPTSTAT_ERBR1_Msk (0x01UL << USB0_ENDPTSTAT_ERBR1_Pos) /*!< USB0 ENDPTSTAT: ERBR1 Mask */ #define USB0_ENDPTSTAT_ERBR2_Pos 2 /*!< USB0 ENDPTSTAT: ERBR2 Position */ #define USB0_ENDPTSTAT_ERBR2_Msk (0x01UL << USB0_ENDPTSTAT_ERBR2_Pos) /*!< USB0 ENDPTSTAT: ERBR2 Mask */ #define USB0_ENDPTSTAT_ERBR3_Pos 3 /*!< USB0 ENDPTSTAT: ERBR3 Position */ #define USB0_ENDPTSTAT_ERBR3_Msk (0x01UL << USB0_ENDPTSTAT_ERBR3_Pos) /*!< USB0 ENDPTSTAT: ERBR3 Mask */ #define USB0_ENDPTSTAT_ERBR4_Pos 4 /*!< USB0 ENDPTSTAT: ERBR4 Position */ #define USB0_ENDPTSTAT_ERBR4_Msk (0x01UL << USB0_ENDPTSTAT_ERBR4_Pos) /*!< USB0 ENDPTSTAT: ERBR4 Mask */ #define USB0_ENDPTSTAT_ERBR5_Pos 5 /*!< USB0 ENDPTSTAT: ERBR5 Position */ #define USB0_ENDPTSTAT_ERBR5_Msk (0x01UL << USB0_ENDPTSTAT_ERBR5_Pos) /*!< USB0 ENDPTSTAT: ERBR5 Mask */ #define USB0_ENDPTSTAT_ETBR0_Pos 16 /*!< USB0 ENDPTSTAT: ETBR0 Position */ #define USB0_ENDPTSTAT_ETBR0_Msk (0x01UL << USB0_ENDPTSTAT_ETBR0_Pos) /*!< USB0 ENDPTSTAT: ETBR0 Mask */ #define USB0_ENDPTSTAT_ETBR1_Pos 17 /*!< USB0 ENDPTSTAT: ETBR1 Position */ #define USB0_ENDPTSTAT_ETBR1_Msk (0x01UL << USB0_ENDPTSTAT_ETBR1_Pos) /*!< USB0 ENDPTSTAT: ETBR1 Mask */ #define USB0_ENDPTSTAT_ETBR2_Pos 18 /*!< USB0 ENDPTSTAT: ETBR2 Position */ #define USB0_ENDPTSTAT_ETBR2_Msk (0x01UL << USB0_ENDPTSTAT_ETBR2_Pos) /*!< USB0 ENDPTSTAT: ETBR2 Mask */ #define USB0_ENDPTSTAT_ETBR3_Pos 19 /*!< USB0 ENDPTSTAT: ETBR3 Position */ #define USB0_ENDPTSTAT_ETBR3_Msk (0x01UL << USB0_ENDPTSTAT_ETBR3_Pos) /*!< USB0 ENDPTSTAT: ETBR3 Mask */ #define USB0_ENDPTSTAT_ETBR4_Pos 20 /*!< USB0 ENDPTSTAT: ETBR4 Position */ #define USB0_ENDPTSTAT_ETBR4_Msk (0x01UL << USB0_ENDPTSTAT_ETBR4_Pos) /*!< USB0 ENDPTSTAT: ETBR4 Mask */ #define USB0_ENDPTSTAT_ETBR5_Pos 21 /*!< USB0 ENDPTSTAT: ETBR5 Position */ #define USB0_ENDPTSTAT_ETBR5_Msk (0x01UL << USB0_ENDPTSTAT_ETBR5_Pos) /*!< USB0 ENDPTSTAT: ETBR5 Mask */ /* ----------------------------- USB0_ENDPTCOMPLETE ----------------------------- */ #define USB0_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB0 ENDPTCOMPLETE: ERCE0 Position */ #define USB0_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE0 Mask */ #define USB0_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB0 ENDPTCOMPLETE: ERCE1 Position */ #define USB0_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE1 Mask */ #define USB0_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB0 ENDPTCOMPLETE: ERCE2 Position */ #define USB0_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE2 Mask */ #define USB0_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB0 ENDPTCOMPLETE: ERCE3 Position */ #define USB0_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE3 Mask */ #define USB0_ENDPTCOMPLETE_ERCE4_Pos 4 /*!< USB0 ENDPTCOMPLETE: ERCE4 Position */ #define USB0_ENDPTCOMPLETE_ERCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE4 Mask */ #define USB0_ENDPTCOMPLETE_ERCE5_Pos 5 /*!< USB0 ENDPTCOMPLETE: ERCE5 Position */ #define USB0_ENDPTCOMPLETE_ERCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ERCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ERCE5 Mask */ #define USB0_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB0 ENDPTCOMPLETE: ETCE0 Position */ #define USB0_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE0 Mask */ #define USB0_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB0 ENDPTCOMPLETE: ETCE1 Position */ #define USB0_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE1 Mask */ #define USB0_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB0 ENDPTCOMPLETE: ETCE2 Position */ #define USB0_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE2 Mask */ #define USB0_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB0 ENDPTCOMPLETE: ETCE3 Position */ #define USB0_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE3 Mask */ #define USB0_ENDPTCOMPLETE_ETCE4_Pos 20 /*!< USB0 ENDPTCOMPLETE: ETCE4 Position */ #define USB0_ENDPTCOMPLETE_ETCE4_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE4_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE4 Mask */ #define USB0_ENDPTCOMPLETE_ETCE5_Pos 21 /*!< USB0 ENDPTCOMPLETE: ETCE5 Position */ #define USB0_ENDPTCOMPLETE_ETCE5_Msk (0x01UL << USB0_ENDPTCOMPLETE_ETCE5_Pos) /*!< USB0 ENDPTCOMPLETE: ETCE5 Mask */ /* ------------------------------- USB0_ENDPTCTRL0 ------------------------------ */ #define USB0_ENDPTCTRL0_RXS_Pos 0 /*!< USB0 ENDPTCTRL0: RXS Position */ #define USB0_ENDPTCTRL0_RXS_Msk (0x01UL << USB0_ENDPTCTRL0_RXS_Pos) /*!< USB0 ENDPTCTRL0: RXS Mask */ #define USB0_ENDPTCTRL0_RXT1_0_Pos 2 /*!< USB0 ENDPTCTRL0: RXT1_0 Position */ #define USB0_ENDPTCTRL0_RXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_RXT1_0_Pos) /*!< USB0 ENDPTCTRL0: RXT1_0 Mask */ #define USB0_ENDPTCTRL0_RXE_Pos 7 /*!< USB0 ENDPTCTRL0: RXE Position */ #define USB0_ENDPTCTRL0_RXE_Msk (0x01UL << USB0_ENDPTCTRL0_RXE_Pos) /*!< USB0 ENDPTCTRL0: RXE Mask */ #define USB0_ENDPTCTRL0_TXS_Pos 16 /*!< USB0 ENDPTCTRL0: TXS Position */ #define USB0_ENDPTCTRL0_TXS_Msk (0x01UL << USB0_ENDPTCTRL0_TXS_Pos) /*!< USB0 ENDPTCTRL0: TXS Mask */ #define USB0_ENDPTCTRL0_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL0: TXT1_0 Position */ #define USB0_ENDPTCTRL0_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL0_TXT1_0_Pos) /*!< USB0 ENDPTCTRL0: TXT1_0 Mask */ #define USB0_ENDPTCTRL0_TXE_Pos 23 /*!< USB0 ENDPTCTRL0: TXE Position */ #define USB0_ENDPTCTRL0_TXE_Msk (0x01UL << USB0_ENDPTCTRL0_TXE_Pos) /*!< USB0 ENDPTCTRL0: TXE Mask */ /* ------------------------------- USB0_ENDPTCTRL1 ------------------------------ */ #define USB0_ENDPTCTRL1_RXS_Pos 0 /*!< USB0 ENDPTCTRL1: RXS Position */ #define USB0_ENDPTCTRL1_RXS_Msk (0x01UL << USB0_ENDPTCTRL1_RXS_Pos) /*!< USB0 ENDPTCTRL1: RXS Mask */ #define USB0_ENDPTCTRL1_RXT_Pos 2 /*!< USB0 ENDPTCTRL1: RXT Position */ #define USB0_ENDPTCTRL1_RXT_Msk (0x03UL << USB0_ENDPTCTRL1_RXT_Pos) /*!< USB0 ENDPTCTRL1: RXT Mask */ #define USB0_ENDPTCTRL1_RXI_Pos 5 /*!< USB0 ENDPTCTRL1: RXI Position */ #define USB0_ENDPTCTRL1_RXI_Msk (0x01UL << USB0_ENDPTCTRL1_RXI_Pos) /*!< USB0 ENDPTCTRL1: RXI Mask */ #define USB0_ENDPTCTRL1_RXR_Pos 6 /*!< USB0 ENDPTCTRL1: RXR Position */ #define USB0_ENDPTCTRL1_RXR_Msk (0x01UL << USB0_ENDPTCTRL1_RXR_Pos) /*!< USB0 ENDPTCTRL1: RXR Mask */ #define USB0_ENDPTCTRL1_RXE_Pos 7 /*!< USB0 ENDPTCTRL1: RXE Position */ #define USB0_ENDPTCTRL1_RXE_Msk (0x01UL << USB0_ENDPTCTRL1_RXE_Pos) /*!< USB0 ENDPTCTRL1: RXE Mask */ #define USB0_ENDPTCTRL1_TXS_Pos 16 /*!< USB0 ENDPTCTRL1: TXS Position */ #define USB0_ENDPTCTRL1_TXS_Msk (0x01UL << USB0_ENDPTCTRL1_TXS_Pos) /*!< USB0 ENDPTCTRL1: TXS Mask */ #define USB0_ENDPTCTRL1_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL1: TXT1_0 Position */ #define USB0_ENDPTCTRL1_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL1_TXT1_0_Pos) /*!< USB0 ENDPTCTRL1: TXT1_0 Mask */ #define USB0_ENDPTCTRL1_TXI_Pos 21 /*!< USB0 ENDPTCTRL1: TXI Position */ #define USB0_ENDPTCTRL1_TXI_Msk (0x01UL << USB0_ENDPTCTRL1_TXI_Pos) /*!< USB0 ENDPTCTRL1: TXI Mask */ #define USB0_ENDPTCTRL1_TXR_Pos 22 /*!< USB0 ENDPTCTRL1: TXR Position */ #define USB0_ENDPTCTRL1_TXR_Msk (0x01UL << USB0_ENDPTCTRL1_TXR_Pos) /*!< USB0 ENDPTCTRL1: TXR Mask */ #define USB0_ENDPTCTRL1_TXE_Pos 23 /*!< USB0 ENDPTCTRL1: TXE Position */ #define USB0_ENDPTCTRL1_TXE_Msk (0x01UL << USB0_ENDPTCTRL1_TXE_Pos) /*!< USB0 ENDPTCTRL1: TXE Mask */ /* ------------------------------- USB0_ENDPTCTRL2 ------------------------------ */ #define USB0_ENDPTCTRL2_RXS_Pos 0 /*!< USB0 ENDPTCTRL2: RXS Position */ #define USB0_ENDPTCTRL2_RXS_Msk (0x01UL << USB0_ENDPTCTRL2_RXS_Pos) /*!< USB0 ENDPTCTRL2: RXS Mask */ #define USB0_ENDPTCTRL2_RXT_Pos 2 /*!< USB0 ENDPTCTRL2: RXT Position */ #define USB0_ENDPTCTRL2_RXT_Msk (0x03UL << USB0_ENDPTCTRL2_RXT_Pos) /*!< USB0 ENDPTCTRL2: RXT Mask */ #define USB0_ENDPTCTRL2_RXI_Pos 5 /*!< USB0 ENDPTCTRL2: RXI Position */ #define USB0_ENDPTCTRL2_RXI_Msk (0x01UL << USB0_ENDPTCTRL2_RXI_Pos) /*!< USB0 ENDPTCTRL2: RXI Mask */ #define USB0_ENDPTCTRL2_RXR_Pos 6 /*!< USB0 ENDPTCTRL2: RXR Position */ #define USB0_ENDPTCTRL2_RXR_Msk (0x01UL << USB0_ENDPTCTRL2_RXR_Pos) /*!< USB0 ENDPTCTRL2: RXR Mask */ #define USB0_ENDPTCTRL2_RXE_Pos 7 /*!< USB0 ENDPTCTRL2: RXE Position */ #define USB0_ENDPTCTRL2_RXE_Msk (0x01UL << USB0_ENDPTCTRL2_RXE_Pos) /*!< USB0 ENDPTCTRL2: RXE Mask */ #define USB0_ENDPTCTRL2_TXS_Pos 16 /*!< USB0 ENDPTCTRL2: TXS Position */ #define USB0_ENDPTCTRL2_TXS_Msk (0x01UL << USB0_ENDPTCTRL2_TXS_Pos) /*!< USB0 ENDPTCTRL2: TXS Mask */ #define USB0_ENDPTCTRL2_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL2: TXT1_0 Position */ #define USB0_ENDPTCTRL2_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL2_TXT1_0_Pos) /*!< USB0 ENDPTCTRL2: TXT1_0 Mask */ #define USB0_ENDPTCTRL2_TXI_Pos 21 /*!< USB0 ENDPTCTRL2: TXI Position */ #define USB0_ENDPTCTRL2_TXI_Msk (0x01UL << USB0_ENDPTCTRL2_TXI_Pos) /*!< USB0 ENDPTCTRL2: TXI Mask */ #define USB0_ENDPTCTRL2_TXR_Pos 22 /*!< USB0 ENDPTCTRL2: TXR Position */ #define USB0_ENDPTCTRL2_TXR_Msk (0x01UL << USB0_ENDPTCTRL2_TXR_Pos) /*!< USB0 ENDPTCTRL2: TXR Mask */ #define USB0_ENDPTCTRL2_TXE_Pos 23 /*!< USB0 ENDPTCTRL2: TXE Position */ #define USB0_ENDPTCTRL2_TXE_Msk (0x01UL << USB0_ENDPTCTRL2_TXE_Pos) /*!< USB0 ENDPTCTRL2: TXE Mask */ /* ------------------------------- USB0_ENDPTCTRL3 ------------------------------ */ #define USB0_ENDPTCTRL3_RXS_Pos 0 /*!< USB0 ENDPTCTRL3: RXS Position */ #define USB0_ENDPTCTRL3_RXS_Msk (0x01UL << USB0_ENDPTCTRL3_RXS_Pos) /*!< USB0 ENDPTCTRL3: RXS Mask */ #define USB0_ENDPTCTRL3_RXT_Pos 2 /*!< USB0 ENDPTCTRL3: RXT Position */ #define USB0_ENDPTCTRL3_RXT_Msk (0x03UL << USB0_ENDPTCTRL3_RXT_Pos) /*!< USB0 ENDPTCTRL3: RXT Mask */ #define USB0_ENDPTCTRL3_RXI_Pos 5 /*!< USB0 ENDPTCTRL3: RXI Position */ #define USB0_ENDPTCTRL3_RXI_Msk (0x01UL << USB0_ENDPTCTRL3_RXI_Pos) /*!< USB0 ENDPTCTRL3: RXI Mask */ #define USB0_ENDPTCTRL3_RXR_Pos 6 /*!< USB0 ENDPTCTRL3: RXR Position */ #define USB0_ENDPTCTRL3_RXR_Msk (0x01UL << USB0_ENDPTCTRL3_RXR_Pos) /*!< USB0 ENDPTCTRL3: RXR Mask */ #define USB0_ENDPTCTRL3_RXE_Pos 7 /*!< USB0 ENDPTCTRL3: RXE Position */ #define USB0_ENDPTCTRL3_RXE_Msk (0x01UL << USB0_ENDPTCTRL3_RXE_Pos) /*!< USB0 ENDPTCTRL3: RXE Mask */ #define USB0_ENDPTCTRL3_TXS_Pos 16 /*!< USB0 ENDPTCTRL3: TXS Position */ #define USB0_ENDPTCTRL3_TXS_Msk (0x01UL << USB0_ENDPTCTRL3_TXS_Pos) /*!< USB0 ENDPTCTRL3: TXS Mask */ #define USB0_ENDPTCTRL3_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL3: TXT1_0 Position */ #define USB0_ENDPTCTRL3_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL3_TXT1_0_Pos) /*!< USB0 ENDPTCTRL3: TXT1_0 Mask */ #define USB0_ENDPTCTRL3_TXI_Pos 21 /*!< USB0 ENDPTCTRL3: TXI Position */ #define USB0_ENDPTCTRL3_TXI_Msk (0x01UL << USB0_ENDPTCTRL3_TXI_Pos) /*!< USB0 ENDPTCTRL3: TXI Mask */ #define USB0_ENDPTCTRL3_TXR_Pos 22 /*!< USB0 ENDPTCTRL3: TXR Position */ #define USB0_ENDPTCTRL3_TXR_Msk (0x01UL << USB0_ENDPTCTRL3_TXR_Pos) /*!< USB0 ENDPTCTRL3: TXR Mask */ #define USB0_ENDPTCTRL3_TXE_Pos 23 /*!< USB0 ENDPTCTRL3: TXE Position */ #define USB0_ENDPTCTRL3_TXE_Msk (0x01UL << USB0_ENDPTCTRL3_TXE_Pos) /*!< USB0 ENDPTCTRL3: TXE Mask */ /* ------------------------------- USB0_ENDPTCTRL4 ------------------------------ */ #define USB0_ENDPTCTRL4_RXS_Pos 0 /*!< USB0 ENDPTCTRL4: RXS Position */ #define USB0_ENDPTCTRL4_RXS_Msk (0x01UL << USB0_ENDPTCTRL4_RXS_Pos) /*!< USB0 ENDPTCTRL4: RXS Mask */ #define USB0_ENDPTCTRL4_RXT_Pos 2 /*!< USB0 ENDPTCTRL4: RXT Position */ #define USB0_ENDPTCTRL4_RXT_Msk (0x03UL << USB0_ENDPTCTRL4_RXT_Pos) /*!< USB0 ENDPTCTRL4: RXT Mask */ #define USB0_ENDPTCTRL4_RXI_Pos 5 /*!< USB0 ENDPTCTRL4: RXI Position */ #define USB0_ENDPTCTRL4_RXI_Msk (0x01UL << USB0_ENDPTCTRL4_RXI_Pos) /*!< USB0 ENDPTCTRL4: RXI Mask */ #define USB0_ENDPTCTRL4_RXR_Pos 6 /*!< USB0 ENDPTCTRL4: RXR Position */ #define USB0_ENDPTCTRL4_RXR_Msk (0x01UL << USB0_ENDPTCTRL4_RXR_Pos) /*!< USB0 ENDPTCTRL4: RXR Mask */ #define USB0_ENDPTCTRL4_RXE_Pos 7 /*!< USB0 ENDPTCTRL4: RXE Position */ #define USB0_ENDPTCTRL4_RXE_Msk (0x01UL << USB0_ENDPTCTRL4_RXE_Pos) /*!< USB0 ENDPTCTRL4: RXE Mask */ #define USB0_ENDPTCTRL4_TXS_Pos 16 /*!< USB0 ENDPTCTRL4: TXS Position */ #define USB0_ENDPTCTRL4_TXS_Msk (0x01UL << USB0_ENDPTCTRL4_TXS_Pos) /*!< USB0 ENDPTCTRL4: TXS Mask */ #define USB0_ENDPTCTRL4_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL4: TXT1_0 Position */ #define USB0_ENDPTCTRL4_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL4_TXT1_0_Pos) /*!< USB0 ENDPTCTRL4: TXT1_0 Mask */ #define USB0_ENDPTCTRL4_TXI_Pos 21 /*!< USB0 ENDPTCTRL4: TXI Position */ #define USB0_ENDPTCTRL4_TXI_Msk (0x01UL << USB0_ENDPTCTRL4_TXI_Pos) /*!< USB0 ENDPTCTRL4: TXI Mask */ #define USB0_ENDPTCTRL4_TXR_Pos 22 /*!< USB0 ENDPTCTRL4: TXR Position */ #define USB0_ENDPTCTRL4_TXR_Msk (0x01UL << USB0_ENDPTCTRL4_TXR_Pos) /*!< USB0 ENDPTCTRL4: TXR Mask */ #define USB0_ENDPTCTRL4_TXE_Pos 23 /*!< USB0 ENDPTCTRL4: TXE Position */ #define USB0_ENDPTCTRL4_TXE_Msk (0x01UL << USB0_ENDPTCTRL4_TXE_Pos) /*!< USB0 ENDPTCTRL4: TXE Mask */ /* ------------------------------- USB0_ENDPTCTRL5 ------------------------------ */ #define USB0_ENDPTCTRL5_RXS_Pos 0 /*!< USB0 ENDPTCTRL5: RXS Position */ #define USB0_ENDPTCTRL5_RXS_Msk (0x01UL << USB0_ENDPTCTRL5_RXS_Pos) /*!< USB0 ENDPTCTRL5: RXS Mask */ #define USB0_ENDPTCTRL5_RXT_Pos 2 /*!< USB0 ENDPTCTRL5: RXT Position */ #define USB0_ENDPTCTRL5_RXT_Msk (0x03UL << USB0_ENDPTCTRL5_RXT_Pos) /*!< USB0 ENDPTCTRL5: RXT Mask */ #define USB0_ENDPTCTRL5_RXI_Pos 5 /*!< USB0 ENDPTCTRL5: RXI Position */ #define USB0_ENDPTCTRL5_RXI_Msk (0x01UL << USB0_ENDPTCTRL5_RXI_Pos) /*!< USB0 ENDPTCTRL5: RXI Mask */ #define USB0_ENDPTCTRL5_RXR_Pos 6 /*!< USB0 ENDPTCTRL5: RXR Position */ #define USB0_ENDPTCTRL5_RXR_Msk (0x01UL << USB0_ENDPTCTRL5_RXR_Pos) /*!< USB0 ENDPTCTRL5: RXR Mask */ #define USB0_ENDPTCTRL5_RXE_Pos 7 /*!< USB0 ENDPTCTRL5: RXE Position */ #define USB0_ENDPTCTRL5_RXE_Msk (0x01UL << USB0_ENDPTCTRL5_RXE_Pos) /*!< USB0 ENDPTCTRL5: RXE Mask */ #define USB0_ENDPTCTRL5_TXS_Pos 16 /*!< USB0 ENDPTCTRL5: TXS Position */ #define USB0_ENDPTCTRL5_TXS_Msk (0x01UL << USB0_ENDPTCTRL5_TXS_Pos) /*!< USB0 ENDPTCTRL5: TXS Mask */ #define USB0_ENDPTCTRL5_TXT1_0_Pos 18 /*!< USB0 ENDPTCTRL5: TXT1_0 Position */ #define USB0_ENDPTCTRL5_TXT1_0_Msk (0x03UL << USB0_ENDPTCTRL5_TXT1_0_Pos) /*!< USB0 ENDPTCTRL5: TXT1_0 Mask */ #define USB0_ENDPTCTRL5_TXI_Pos 21 /*!< USB0 ENDPTCTRL5: TXI Position */ #define USB0_ENDPTCTRL5_TXI_Msk (0x01UL << USB0_ENDPTCTRL5_TXI_Pos) /*!< USB0 ENDPTCTRL5: TXI Mask */ #define USB0_ENDPTCTRL5_TXR_Pos 22 /*!< USB0 ENDPTCTRL5: TXR Position */ #define USB0_ENDPTCTRL5_TXR_Msk (0x01UL << USB0_ENDPTCTRL5_TXR_Pos) /*!< USB0 ENDPTCTRL5: TXR Mask */ #define USB0_ENDPTCTRL5_TXE_Pos 23 /*!< USB0 ENDPTCTRL5: TXE Position */ #define USB0_ENDPTCTRL5_TXE_Msk (0x01UL << USB0_ENDPTCTRL5_TXE_Pos) /*!< USB0 ENDPTCTRL5: TXE Mask */ /* ================================================================================ */ /* ================ struct 'USB1' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------- USB1_CAPLENGTH ------------------------------- */ #define USB1_CAPLENGTH_CAPLENGTH_Pos 0 /*!< USB1 CAPLENGTH: CAPLENGTH Position */ #define USB1_CAPLENGTH_CAPLENGTH_Msk (0x000000ffUL << USB1_CAPLENGTH_CAPLENGTH_Pos) /*!< USB1 CAPLENGTH: CAPLENGTH Mask */ #define USB1_CAPLENGTH_HCIVERSION_Pos 8 /*!< USB1 CAPLENGTH: HCIVERSION Position */ #define USB1_CAPLENGTH_HCIVERSION_Msk (0x0000ffffUL << USB1_CAPLENGTH_HCIVERSION_Pos) /*!< USB1 CAPLENGTH: HCIVERSION Mask */ /* ------------------------------- USB1_HCSPARAMS ------------------------------- */ #define USB1_HCSPARAMS_N_PORTS_Pos 0 /*!< USB1 HCSPARAMS: N_PORTS Position */ #define USB1_HCSPARAMS_N_PORTS_Msk (0x0fUL << USB1_HCSPARAMS_N_PORTS_Pos) /*!< USB1 HCSPARAMS: N_PORTS Mask */ #define USB1_HCSPARAMS_PPC_Pos 4 /*!< USB1 HCSPARAMS: PPC Position */ #define USB1_HCSPARAMS_PPC_Msk (0x01UL << USB1_HCSPARAMS_PPC_Pos) /*!< USB1 HCSPARAMS: PPC Mask */ #define USB1_HCSPARAMS_N_PCC_Pos 8 /*!< USB1 HCSPARAMS: N_PCC Position */ #define USB1_HCSPARAMS_N_PCC_Msk (0x0fUL << USB1_HCSPARAMS_N_PCC_Pos) /*!< USB1 HCSPARAMS: N_PCC Mask */ #define USB1_HCSPARAMS_N_CC_Pos 12 /*!< USB1 HCSPARAMS: N_CC Position */ #define USB1_HCSPARAMS_N_CC_Msk (0x0fUL << USB1_HCSPARAMS_N_CC_Pos) /*!< USB1 HCSPARAMS: N_CC Mask */ #define USB1_HCSPARAMS_PI_Pos 16 /*!< USB1 HCSPARAMS: PI Position */ #define USB1_HCSPARAMS_PI_Msk (0x01UL << USB1_HCSPARAMS_PI_Pos) /*!< USB1 HCSPARAMS: PI Mask */ #define USB1_HCSPARAMS_N_PTT_Pos 20 /*!< USB1 HCSPARAMS: N_PTT Position */ #define USB1_HCSPARAMS_N_PTT_Msk (0x0fUL << USB1_HCSPARAMS_N_PTT_Pos) /*!< USB1 HCSPARAMS: N_PTT Mask */ #define USB1_HCSPARAMS_N_TT_Pos 24 /*!< USB1 HCSPARAMS: N_TT Position */ #define USB1_HCSPARAMS_N_TT_Msk (0x0fUL << USB1_HCSPARAMS_N_TT_Pos) /*!< USB1 HCSPARAMS: N_TT Mask */ /* ------------------------------- USB1_HCCPARAMS ------------------------------- */ #define USB1_HCCPARAMS_ADC_Pos 0 /*!< USB1 HCCPARAMS: ADC Position */ #define USB1_HCCPARAMS_ADC_Msk (0x01UL << USB1_HCCPARAMS_ADC_Pos) /*!< USB1 HCCPARAMS: ADC Mask */ #define USB1_HCCPARAMS_PFL_Pos 1 /*!< USB1 HCCPARAMS: PFL Position */ #define USB1_HCCPARAMS_PFL_Msk (0x01UL << USB1_HCCPARAMS_PFL_Pos) /*!< USB1 HCCPARAMS: PFL Mask */ #define USB1_HCCPARAMS_ASP_Pos 2 /*!< USB1 HCCPARAMS: ASP Position */ #define USB1_HCCPARAMS_ASP_Msk (0x01UL << USB1_HCCPARAMS_ASP_Pos) /*!< USB1 HCCPARAMS: ASP Mask */ #define USB1_HCCPARAMS_IST_Pos 4 /*!< USB1 HCCPARAMS: IST Position */ #define USB1_HCCPARAMS_IST_Msk (0x0fUL << USB1_HCCPARAMS_IST_Pos) /*!< USB1 HCCPARAMS: IST Mask */ #define USB1_HCCPARAMS_EECP_Pos 8 /*!< USB1 HCCPARAMS: EECP Position */ #define USB1_HCCPARAMS_EECP_Msk (0x000000ffUL << USB1_HCCPARAMS_EECP_Pos) /*!< USB1 HCCPARAMS: EECP Mask */ /* ------------------------------- USB1_DCIVERSION ------------------------------ */ #define USB1_DCIVERSION_DCIVERSION_Pos 0 /*!< USB1 DCIVERSION: DCIVERSION Position */ #define USB1_DCIVERSION_DCIVERSION_Msk (0x0000ffffUL << USB1_DCIVERSION_DCIVERSION_Pos) /*!< USB1 DCIVERSION: DCIVERSION Mask */ /* -------------------------------- USB1_USBCMD_D ------------------------------- */ #define USB1_USBCMD_D_RS_Pos 0 /*!< USB1 USBCMD_D: RS Position */ #define USB1_USBCMD_D_RS_Msk (0x01UL << USB1_USBCMD_D_RS_Pos) /*!< USB1 USBCMD_D: RS Mask */ #define USB1_USBCMD_D_RST_Pos 1 /*!< USB1 USBCMD_D: RST Position */ #define USB1_USBCMD_D_RST_Msk (0x01UL << USB1_USBCMD_D_RST_Pos) /*!< USB1 USBCMD_D: RST Mask */ #define USB1_USBCMD_D_SUTW_Pos 13 /*!< USB1 USBCMD_D: SUTW Position */ #define USB1_USBCMD_D_SUTW_Msk (0x01UL << USB1_USBCMD_D_SUTW_Pos) /*!< USB1 USBCMD_D: SUTW Mask */ #define USB1_USBCMD_D_ATDTW_Pos 14 /*!< USB1 USBCMD_D: ATDTW Position */ #define USB1_USBCMD_D_ATDTW_Msk (0x01UL << USB1_USBCMD_D_ATDTW_Pos) /*!< USB1 USBCMD_D: ATDTW Mask */ #define USB1_USBCMD_D_FS2_Pos 15 /*!< USB1 USBCMD_D: FS2 Position */ #define USB1_USBCMD_D_FS2_Msk (0x01UL << USB1_USBCMD_D_FS2_Pos) /*!< USB1 USBCMD_D: FS2 Mask */ #define USB1_USBCMD_D_ITC_Pos 16 /*!< USB1 USBCMD_D: ITC Position */ #define USB1_USBCMD_D_ITC_Msk (0x000000ffUL << USB1_USBCMD_D_ITC_Pos) /*!< USB1 USBCMD_D: ITC Mask */ /* -------------------------------- USB1_USBCMD_H ------------------------------- */ #define USB1_USBCMD_H_RS_Pos 0 /*!< USB1 USBCMD_H: RS Position */ #define USB1_USBCMD_H_RS_Msk (0x01UL << USB1_USBCMD_H_RS_Pos) /*!< USB1 USBCMD_H: RS Mask */ #define USB1_USBCMD_H_RST_Pos 1 /*!< USB1 USBCMD_H: RST Position */ #define USB1_USBCMD_H_RST_Msk (0x01UL << USB1_USBCMD_H_RST_Pos) /*!< USB1 USBCMD_H: RST Mask */ #define USB1_USBCMD_H_FS0_Pos 2 /*!< USB1 USBCMD_H: FS0 Position */ #define USB1_USBCMD_H_FS0_Msk (0x01UL << USB1_USBCMD_H_FS0_Pos) /*!< USB1 USBCMD_H: FS0 Mask */ #define USB1_USBCMD_H_FS1_Pos 3 /*!< USB1 USBCMD_H: FS1 Position */ #define USB1_USBCMD_H_FS1_Msk (0x01UL << USB1_USBCMD_H_FS1_Pos) /*!< USB1 USBCMD_H: FS1 Mask */ #define USB1_USBCMD_H_PSE_Pos 4 /*!< USB1 USBCMD_H: PSE Position */ #define USB1_USBCMD_H_PSE_Msk (0x01UL << USB1_USBCMD_H_PSE_Pos) /*!< USB1 USBCMD_H: PSE Mask */ #define USB1_USBCMD_H_ASE_Pos 5 /*!< USB1 USBCMD_H: ASE Position */ #define USB1_USBCMD_H_ASE_Msk (0x01UL << USB1_USBCMD_H_ASE_Pos) /*!< USB1 USBCMD_H: ASE Mask */ #define USB1_USBCMD_H_IAA_Pos 6 /*!< USB1 USBCMD_H: IAA Position */ #define USB1_USBCMD_H_IAA_Msk (0x01UL << USB1_USBCMD_H_IAA_Pos) /*!< USB1 USBCMD_H: IAA Mask */ #define USB1_USBCMD_H_ASP1_0_Pos 8 /*!< USB1 USBCMD_H: ASP1_0 Position */ #define USB1_USBCMD_H_ASP1_0_Msk (0x03UL << USB1_USBCMD_H_ASP1_0_Pos) /*!< USB1 USBCMD_H: ASP1_0 Mask */ #define USB1_USBCMD_H_ASPE_Pos 11 /*!< USB1 USBCMD_H: ASPE Position */ #define USB1_USBCMD_H_ASPE_Msk (0x01UL << USB1_USBCMD_H_ASPE_Pos) /*!< USB1 USBCMD_H: ASPE Mask */ #define USB1_USBCMD_H_FS2_Pos 15 /*!< USB1 USBCMD_H: FS2 Position */ #define USB1_USBCMD_H_FS2_Msk (0x01UL << USB1_USBCMD_H_FS2_Pos) /*!< USB1 USBCMD_H: FS2 Mask */ #define USB1_USBCMD_H_ITC_Pos 16 /*!< USB1 USBCMD_H: ITC Position */ #define USB1_USBCMD_H_ITC_Msk (0x000000ffUL << USB1_USBCMD_H_ITC_Pos) /*!< USB1 USBCMD_H: ITC Mask */ /* -------------------------------- USB1_USBSTS_D ------------------------------- */ #define USB1_USBSTS_D_UI_Pos 0 /*!< USB1 USBSTS_D: UI Position */ #define USB1_USBSTS_D_UI_Msk (0x01UL << USB1_USBSTS_D_UI_Pos) /*!< USB1 USBSTS_D: UI Mask */ #define USB1_USBSTS_D_UEI_Pos 1 /*!< USB1 USBSTS_D: UEI Position */ #define USB1_USBSTS_D_UEI_Msk (0x01UL << USB1_USBSTS_D_UEI_Pos) /*!< USB1 USBSTS_D: UEI Mask */ #define USB1_USBSTS_D_PCI_Pos 2 /*!< USB1 USBSTS_D: PCI Position */ #define USB1_USBSTS_D_PCI_Msk (0x01UL << USB1_USBSTS_D_PCI_Pos) /*!< USB1 USBSTS_D: PCI Mask */ #define USB1_USBSTS_D_URI_Pos 6 /*!< USB1 USBSTS_D: URI Position */ #define USB1_USBSTS_D_URI_Msk (0x01UL << USB1_USBSTS_D_URI_Pos) /*!< USB1 USBSTS_D: URI Mask */ #define USB1_USBSTS_D_SRI_Pos 7 /*!< USB1 USBSTS_D: SRI Position */ #define USB1_USBSTS_D_SRI_Msk (0x01UL << USB1_USBSTS_D_SRI_Pos) /*!< USB1 USBSTS_D: SRI Mask */ #define USB1_USBSTS_D_SLI_Pos 8 /*!< USB1 USBSTS_D: SLI Position */ #define USB1_USBSTS_D_SLI_Msk (0x01UL << USB1_USBSTS_D_SLI_Pos) /*!< USB1 USBSTS_D: SLI Mask */ #define USB1_USBSTS_D_NAKI_Pos 16 /*!< USB1 USBSTS_D: NAKI Position */ #define USB1_USBSTS_D_NAKI_Msk (0x01UL << USB1_USBSTS_D_NAKI_Pos) /*!< USB1 USBSTS_D: NAKI Mask */ /* -------------------------------- USB1_USBSTS_H ------------------------------- */ #define USB1_USBSTS_H_UI_Pos 0 /*!< USB1 USBSTS_H: UI Position */ #define USB1_USBSTS_H_UI_Msk (0x01UL << USB1_USBSTS_H_UI_Pos) /*!< USB1 USBSTS_H: UI Mask */ #define USB1_USBSTS_H_UEI_Pos 1 /*!< USB1 USBSTS_H: UEI Position */ #define USB1_USBSTS_H_UEI_Msk (0x01UL << USB1_USBSTS_H_UEI_Pos) /*!< USB1 USBSTS_H: UEI Mask */ #define USB1_USBSTS_H_PCI_Pos 2 /*!< USB1 USBSTS_H: PCI Position */ #define USB1_USBSTS_H_PCI_Msk (0x01UL << USB1_USBSTS_H_PCI_Pos) /*!< USB1 USBSTS_H: PCI Mask */ #define USB1_USBSTS_H_FRI_Pos 3 /*!< USB1 USBSTS_H: FRI Position */ #define USB1_USBSTS_H_FRI_Msk (0x01UL << USB1_USBSTS_H_FRI_Pos) /*!< USB1 USBSTS_H: FRI Mask */ #define USB1_USBSTS_H_AAI_Pos 5 /*!< USB1 USBSTS_H: AAI Position */ #define USB1_USBSTS_H_AAI_Msk (0x01UL << USB1_USBSTS_H_AAI_Pos) /*!< USB1 USBSTS_H: AAI Mask */ #define USB1_USBSTS_H_SRI_Pos 7 /*!< USB1 USBSTS_H: SRI Position */ #define USB1_USBSTS_H_SRI_Msk (0x01UL << USB1_USBSTS_H_SRI_Pos) /*!< USB1 USBSTS_H: SRI Mask */ #define USB1_USBSTS_H_SLI_Pos 8 /*!< USB1 USBSTS_H: SLI Position */ #define USB1_USBSTS_H_SLI_Msk (0x01UL << USB1_USBSTS_H_SLI_Pos) /*!< USB1 USBSTS_H: SLI Mask */ #define USB1_USBSTS_H_HCH_Pos 12 /*!< USB1 USBSTS_H: HCH Position */ #define USB1_USBSTS_H_HCH_Msk (0x01UL << USB1_USBSTS_H_HCH_Pos) /*!< USB1 USBSTS_H: HCH Mask */ #define USB1_USBSTS_H_RCL_Pos 13 /*!< USB1 USBSTS_H: RCL Position */ #define USB1_USBSTS_H_RCL_Msk (0x01UL << USB1_USBSTS_H_RCL_Pos) /*!< USB1 USBSTS_H: RCL Mask */ #define USB1_USBSTS_H_PS_Pos 14 /*!< USB1 USBSTS_H: PS Position */ #define USB1_USBSTS_H_PS_Msk (0x01UL << USB1_USBSTS_H_PS_Pos) /*!< USB1 USBSTS_H: PS Mask */ #define USB1_USBSTS_H_AS_Pos 15 /*!< USB1 USBSTS_H: AS Position */ #define USB1_USBSTS_H_AS_Msk (0x01UL << USB1_USBSTS_H_AS_Pos) /*!< USB1 USBSTS_H: AS Mask */ #define USB1_USBSTS_H_UAI_Pos 18 /*!< USB1 USBSTS_H: UAI Position */ #define USB1_USBSTS_H_UAI_Msk (0x01UL << USB1_USBSTS_H_UAI_Pos) /*!< USB1 USBSTS_H: UAI Mask */ #define USB1_USBSTS_H_UPI_Pos 19 /*!< USB1 USBSTS_H: UPI Position */ #define USB1_USBSTS_H_UPI_Msk (0x01UL << USB1_USBSTS_H_UPI_Pos) /*!< USB1 USBSTS_H: UPI Mask */ /* ------------------------------- USB1_USBINTR_D ------------------------------- */ #define USB1_USBINTR_D_UE_Pos 0 /*!< USB1 USBINTR_D: UE Position */ #define USB1_USBINTR_D_UE_Msk (0x01UL << USB1_USBINTR_D_UE_Pos) /*!< USB1 USBINTR_D: UE Mask */ #define USB1_USBINTR_D_UEE_Pos 1 /*!< USB1 USBINTR_D: UEE Position */ #define USB1_USBINTR_D_UEE_Msk (0x01UL << USB1_USBINTR_D_UEE_Pos) /*!< USB1 USBINTR_D: UEE Mask */ #define USB1_USBINTR_D_PCE_Pos 2 /*!< USB1 USBINTR_D: PCE Position */ #define USB1_USBINTR_D_PCE_Msk (0x01UL << USB1_USBINTR_D_PCE_Pos) /*!< USB1 USBINTR_D: PCE Mask */ #define USB1_USBINTR_D_URE_Pos 6 /*!< USB1 USBINTR_D: URE Position */ #define USB1_USBINTR_D_URE_Msk (0x01UL << USB1_USBINTR_D_URE_Pos) /*!< USB1 USBINTR_D: URE Mask */ #define USB1_USBINTR_D_SRE_Pos 7 /*!< USB1 USBINTR_D: SRE Position */ #define USB1_USBINTR_D_SRE_Msk (0x01UL << USB1_USBINTR_D_SRE_Pos) /*!< USB1 USBINTR_D: SRE Mask */ #define USB1_USBINTR_D_SLE_Pos 8 /*!< USB1 USBINTR_D: SLE Position */ #define USB1_USBINTR_D_SLE_Msk (0x01UL << USB1_USBINTR_D_SLE_Pos) /*!< USB1 USBINTR_D: SLE Mask */ #define USB1_USBINTR_D_NAKE_Pos 16 /*!< USB1 USBINTR_D: NAKE Position */ #define USB1_USBINTR_D_NAKE_Msk (0x01UL << USB1_USBINTR_D_NAKE_Pos) /*!< USB1 USBINTR_D: NAKE Mask */ #define USB1_USBINTR_D_UAIE_Pos 18 /*!< USB1 USBINTR_D: UAIE Position */ #define USB1_USBINTR_D_UAIE_Msk (0x01UL << USB1_USBINTR_D_UAIE_Pos) /*!< USB1 USBINTR_D: UAIE Mask */ #define USB1_USBINTR_D_UPIA_Pos 19 /*!< USB1 USBINTR_D: UPIA Position */ #define USB1_USBINTR_D_UPIA_Msk (0x01UL << USB1_USBINTR_D_UPIA_Pos) /*!< USB1 USBINTR_D: UPIA Mask */ /* ------------------------------- USB1_USBINTR_H ------------------------------- */ #define USB1_USBINTR_H_UE_Pos 0 /*!< USB1 USBINTR_H: UE Position */ #define USB1_USBINTR_H_UE_Msk (0x01UL << USB1_USBINTR_H_UE_Pos) /*!< USB1 USBINTR_H: UE Mask */ #define USB1_USBINTR_H_UEE_Pos 1 /*!< USB1 USBINTR_H: UEE Position */ #define USB1_USBINTR_H_UEE_Msk (0x01UL << USB1_USBINTR_H_UEE_Pos) /*!< USB1 USBINTR_H: UEE Mask */ #define USB1_USBINTR_H_PCE_Pos 2 /*!< USB1 USBINTR_H: PCE Position */ #define USB1_USBINTR_H_PCE_Msk (0x01UL << USB1_USBINTR_H_PCE_Pos) /*!< USB1 USBINTR_H: PCE Mask */ #define USB1_USBINTR_H_FRE_Pos 3 /*!< USB1 USBINTR_H: FRE Position */ #define USB1_USBINTR_H_FRE_Msk (0x01UL << USB1_USBINTR_H_FRE_Pos) /*!< USB1 USBINTR_H: FRE Mask */ #define USB1_USBINTR_H_AAE_Pos 5 /*!< USB1 USBINTR_H: AAE Position */ #define USB1_USBINTR_H_AAE_Msk (0x01UL << USB1_USBINTR_H_AAE_Pos) /*!< USB1 USBINTR_H: AAE Mask */ #define USB1_USBINTR_H_SRE_Pos 7 /*!< USB1 USBINTR_H: SRE Position */ #define USB1_USBINTR_H_SRE_Msk (0x01UL << USB1_USBINTR_H_SRE_Pos) /*!< USB1 USBINTR_H: SRE Mask */ #define USB1_USBINTR_H_UAIE_Pos 18 /*!< USB1 USBINTR_H: UAIE Position */ #define USB1_USBINTR_H_UAIE_Msk (0x01UL << USB1_USBINTR_H_UAIE_Pos) /*!< USB1 USBINTR_H: UAIE Mask */ #define USB1_USBINTR_H_UPIA_Pos 19 /*!< USB1 USBINTR_H: UPIA Position */ #define USB1_USBINTR_H_UPIA_Msk (0x01UL << USB1_USBINTR_H_UPIA_Pos) /*!< USB1 USBINTR_H: UPIA Mask */ /* ------------------------------- USB1_FRINDEX_D ------------------------------- */ #define USB1_FRINDEX_D_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_D: FRINDEX2_0 Position */ #define USB1_FRINDEX_D_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_D_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_D: FRINDEX2_0 Mask */ #define USB1_FRINDEX_D_FRINDEX13_3_Pos 3 /*!< USB1 FRINDEX_D: FRINDEX13_3 Position */ #define USB1_FRINDEX_D_FRINDEX13_3_Msk (0x000007ffUL << USB1_FRINDEX_D_FRINDEX13_3_Pos) /*!< USB1 FRINDEX_D: FRINDEX13_3 Mask */ /* ------------------------------- USB1_FRINDEX_H ------------------------------- */ #define USB1_FRINDEX_H_FRINDEX2_0_Pos 0 /*!< USB1 FRINDEX_H: FRINDEX2_0 Position */ #define USB1_FRINDEX_H_FRINDEX2_0_Msk (0x07UL << USB1_FRINDEX_H_FRINDEX2_0_Pos) /*!< USB1 FRINDEX_H: FRINDEX2_0 Mask */ #define USB1_FRINDEX_H_FRINDEX12_3_Pos 3 /*!< USB1 FRINDEX_H: FRINDEX12_3 Position */ #define USB1_FRINDEX_H_FRINDEX12_3_Msk (0x000003ffUL << USB1_FRINDEX_H_FRINDEX12_3_Pos) /*!< USB1 FRINDEX_H: FRINDEX12_3 Mask */ /* ------------------------------- USB1_DEVICEADDR ------------------------------ */ #define USB1_DEVICEADDR_USBADRA_Pos 24 /*!< USB1 DEVICEADDR: USBADRA Position */ #define USB1_DEVICEADDR_USBADRA_Msk (0x01UL << USB1_DEVICEADDR_USBADRA_Pos) /*!< USB1 DEVICEADDR: USBADRA Mask */ #define USB1_DEVICEADDR_USBADR_Pos 25 /*!< USB1 DEVICEADDR: USBADR Position */ #define USB1_DEVICEADDR_USBADR_Msk (0x7fUL << USB1_DEVICEADDR_USBADR_Pos) /*!< USB1 DEVICEADDR: USBADR Mask */ /* ---------------------------- USB1_PERIODICLISTBASE --------------------------- */ #define USB1_PERIODICLISTBASE_PERBASE31_12_Pos 12 /*!< USB1 PERIODICLISTBASE: PERBASE31_12 Position */ #define USB1_PERIODICLISTBASE_PERBASE31_12_Msk (0x000fffffUL << USB1_PERIODICLISTBASE_PERBASE31_12_Pos)/*!< USB1 PERIODICLISTBASE: PERBASE31_12 Mask */ /* ---------------------------- USB1_ENDPOINTLISTADDR --------------------------- */ #define USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos 11 /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Position */ #define USB1_ENDPOINTLISTADDR_EPBASE31_11_Msk (0x001fffffUL << USB1_ENDPOINTLISTADDR_EPBASE31_11_Pos) /*!< USB1 ENDPOINTLISTADDR: EPBASE31_11 Mask */ /* ----------------------------- USB1_ASYNCLISTADDR ----------------------------- */ #define USB1_ASYNCLISTADDR_ASYBASE31_5_Pos 5 /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Position */ #define USB1_ASYNCLISTADDR_ASYBASE31_5_Msk (0x07ffffffUL << USB1_ASYNCLISTADDR_ASYBASE31_5_Pos) /*!< USB1 ASYNCLISTADDR: ASYBASE31_5 Mask */ /* --------------------------------- USB1_TTCTRL -------------------------------- */ #define USB1_TTCTRL_TTHA_Pos 24 /*!< USB1 TTCTRL: TTHA Position */ #define USB1_TTCTRL_TTHA_Msk (0x7fUL << USB1_TTCTRL_TTHA_Pos) /*!< USB1 TTCTRL: TTHA Mask */ /* ------------------------------- USB1_BURSTSIZE ------------------------------- */ #define USB1_BURSTSIZE_RXPBURST_Pos 0 /*!< USB1 BURSTSIZE: RXPBURST Position */ #define USB1_BURSTSIZE_RXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_RXPBURST_Pos) /*!< USB1 BURSTSIZE: RXPBURST Mask */ #define USB1_BURSTSIZE_TXPBURST_Pos 8 /*!< USB1 BURSTSIZE: TXPBURST Position */ #define USB1_BURSTSIZE_TXPBURST_Msk (0x000000ffUL << USB1_BURSTSIZE_TXPBURST_Pos) /*!< USB1 BURSTSIZE: TXPBURST Mask */ /* ------------------------------ USB1_TXFILLTUNING ----------------------------- */ #define USB1_TXFILLTUNING_TXSCHOH_Pos 0 /*!< USB1 TXFILLTUNING: TXSCHOH Position */ #define USB1_TXFILLTUNING_TXSCHOH_Msk (0x000000ffUL << USB1_TXFILLTUNING_TXSCHOH_Pos) /*!< USB1 TXFILLTUNING: TXSCHOH Mask */ #define USB1_TXFILLTUNING_TXSCHEATLTH_Pos 8 /*!< USB1 TXFILLTUNING: TXSCHEATLTH Position */ #define USB1_TXFILLTUNING_TXSCHEATLTH_Msk (0x1fUL << USB1_TXFILLTUNING_TXSCHEATLTH_Pos) /*!< USB1 TXFILLTUNING: TXSCHEATLTH Mask */ #define USB1_TXFILLTUNING_TXFIFOTHRES_Pos 16 /*!< USB1 TXFILLTUNING: TXFIFOTHRES Position */ #define USB1_TXFILLTUNING_TXFIFOTHRES_Msk (0x3fUL << USB1_TXFILLTUNING_TXFIFOTHRES_Pos) /*!< USB1 TXFILLTUNING: TXFIFOTHRES Mask */ /* ------------------------------ USB1_ULPIVIEWPORT ----------------------------- */ #define USB1_ULPIVIEWPORT_ULPIDATWR_Pos 0 /*!< USB1 ULPIVIEWPORT: ULPIDATWR Position */ #define USB1_ULPIVIEWPORT_ULPIDATWR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATWR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATWR Mask */ #define USB1_ULPIVIEWPORT_ULPIDATRD_Pos 8 /*!< USB1 ULPIVIEWPORT: ULPIDATRD Position */ #define USB1_ULPIVIEWPORT_ULPIDATRD_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIDATRD_Pos) /*!< USB1 ULPIVIEWPORT: ULPIDATRD Mask */ #define USB1_ULPIVIEWPORT_ULPIADDR_Pos 16 /*!< USB1 ULPIVIEWPORT: ULPIADDR Position */ #define USB1_ULPIVIEWPORT_ULPIADDR_Msk (0x000000ffUL << USB1_ULPIVIEWPORT_ULPIADDR_Pos) /*!< USB1 ULPIVIEWPORT: ULPIADDR Mask */ #define USB1_ULPIVIEWPORT_ULPIPORT_Pos 24 /*!< USB1 ULPIVIEWPORT: ULPIPORT Position */ #define USB1_ULPIVIEWPORT_ULPIPORT_Msk (0x07UL << USB1_ULPIVIEWPORT_ULPIPORT_Pos) /*!< USB1 ULPIVIEWPORT: ULPIPORT Mask */ #define USB1_ULPIVIEWPORT_ULPISS_Pos 27 /*!< USB1 ULPIVIEWPORT: ULPISS Position */ #define USB1_ULPIVIEWPORT_ULPISS_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPISS_Pos) /*!< USB1 ULPIVIEWPORT: ULPISS Mask */ #define USB1_ULPIVIEWPORT_ULPIRW_Pos 29 /*!< USB1 ULPIVIEWPORT: ULPIRW Position */ #define USB1_ULPIVIEWPORT_ULPIRW_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRW_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRW Mask */ #define USB1_ULPIVIEWPORT_ULPIRUN_Pos 30 /*!< USB1 ULPIVIEWPORT: ULPIRUN Position */ #define USB1_ULPIVIEWPORT_ULPIRUN_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIRUN_Pos) /*!< USB1 ULPIVIEWPORT: ULPIRUN Mask */ #define USB1_ULPIVIEWPORT_ULPIWU_Pos 31 /*!< USB1 ULPIVIEWPORT: ULPIWU Position */ #define USB1_ULPIVIEWPORT_ULPIWU_Msk (0x01UL << USB1_ULPIVIEWPORT_ULPIWU_Pos) /*!< USB1 ULPIVIEWPORT: ULPIWU Mask */ /* ------------------------------- USB1_BINTERVAL ------------------------------- */ #define USB1_BINTERVAL_BINT_Pos 0 /*!< USB1 BINTERVAL: BINT Position */ #define USB1_BINTERVAL_BINT_Msk (0x0fUL << USB1_BINTERVAL_BINT_Pos) /*!< USB1 BINTERVAL: BINT Mask */ /* -------------------------------- USB1_ENDPTNAK ------------------------------- */ #define USB1_ENDPTNAK_EPRN0_Pos 0 /*!< USB1 ENDPTNAK: EPRN0 Position */ #define USB1_ENDPTNAK_EPRN0_Msk (0x01UL << USB1_ENDPTNAK_EPRN0_Pos) /*!< USB1 ENDPTNAK: EPRN0 Mask */ #define USB1_ENDPTNAK_EPRN1_Pos 1 /*!< USB1 ENDPTNAK: EPRN1 Position */ #define USB1_ENDPTNAK_EPRN1_Msk (0x01UL << USB1_ENDPTNAK_EPRN1_Pos) /*!< USB1 ENDPTNAK: EPRN1 Mask */ #define USB1_ENDPTNAK_EPRN2_Pos 2 /*!< USB1 ENDPTNAK: EPRN2 Position */ #define USB1_ENDPTNAK_EPRN2_Msk (0x01UL << USB1_ENDPTNAK_EPRN2_Pos) /*!< USB1 ENDPTNAK: EPRN2 Mask */ #define USB1_ENDPTNAK_EPRN3_Pos 3 /*!< USB1 ENDPTNAK: EPRN3 Position */ #define USB1_ENDPTNAK_EPRN3_Msk (0x01UL << USB1_ENDPTNAK_EPRN3_Pos) /*!< USB1 ENDPTNAK: EPRN3 Mask */ #define USB1_ENDPTNAK_EPTN16_Pos 16 /*!< USB1 ENDPTNAK: EPTN16 Position */ #define USB1_ENDPTNAK_EPTN16_Msk (0x01UL << USB1_ENDPTNAK_EPTN16_Pos) /*!< USB1 ENDPTNAK: EPTN16 Mask */ #define USB1_ENDPTNAK_EPTN17_Pos 17 /*!< USB1 ENDPTNAK: EPTN17 Position */ #define USB1_ENDPTNAK_EPTN17_Msk (0x01UL << USB1_ENDPTNAK_EPTN17_Pos) /*!< USB1 ENDPTNAK: EPTN17 Mask */ #define USB1_ENDPTNAK_EPTN18_Pos 18 /*!< USB1 ENDPTNAK: EPTN18 Position */ #define USB1_ENDPTNAK_EPTN18_Msk (0x01UL << USB1_ENDPTNAK_EPTN18_Pos) /*!< USB1 ENDPTNAK: EPTN18 Mask */ #define USB1_ENDPTNAK_EPTN19_Pos 19 /*!< USB1 ENDPTNAK: EPTN19 Position */ #define USB1_ENDPTNAK_EPTN19_Msk (0x01UL << USB1_ENDPTNAK_EPTN19_Pos) /*!< USB1 ENDPTNAK: EPTN19 Mask */ /* ------------------------------- USB1_ENDPTNAKEN ------------------------------ */ #define USB1_ENDPTNAKEN_EPRNE0_Pos 0 /*!< USB1 ENDPTNAKEN: EPRNE0 Position */ #define USB1_ENDPTNAKEN_EPRNE0_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE0_Pos) /*!< USB1 ENDPTNAKEN: EPRNE0 Mask */ #define USB1_ENDPTNAKEN_EPRNE1_Pos 1 /*!< USB1 ENDPTNAKEN: EPRNE1 Position */ #define USB1_ENDPTNAKEN_EPRNE1_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE1_Pos) /*!< USB1 ENDPTNAKEN: EPRNE1 Mask */ #define USB1_ENDPTNAKEN_EPRNE2_Pos 2 /*!< USB1 ENDPTNAKEN: EPRNE2 Position */ #define USB1_ENDPTNAKEN_EPRNE2_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE2_Pos) /*!< USB1 ENDPTNAKEN: EPRNE2 Mask */ #define USB1_ENDPTNAKEN_EPRNE3_Pos 3 /*!< USB1 ENDPTNAKEN: EPRNE3 Position */ #define USB1_ENDPTNAKEN_EPRNE3_Msk (0x01UL << USB1_ENDPTNAKEN_EPRNE3_Pos) /*!< USB1 ENDPTNAKEN: EPRNE3 Mask */ #define USB1_ENDPTNAKEN_EPTNE16_Pos 16 /*!< USB1 ENDPTNAKEN: EPTNE16 Position */ #define USB1_ENDPTNAKEN_EPTNE16_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE16_Pos) /*!< USB1 ENDPTNAKEN: EPTNE16 Mask */ #define USB1_ENDPTNAKEN_EPTNE17_Pos 17 /*!< USB1 ENDPTNAKEN: EPTNE17 Position */ #define USB1_ENDPTNAKEN_EPTNE17_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE17_Pos) /*!< USB1 ENDPTNAKEN: EPTNE17 Mask */ #define USB1_ENDPTNAKEN_EPTNE18_Pos 18 /*!< USB1 ENDPTNAKEN: EPTNE18 Position */ #define USB1_ENDPTNAKEN_EPTNE18_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE18_Pos) /*!< USB1 ENDPTNAKEN: EPTNE18 Mask */ #define USB1_ENDPTNAKEN_EPTNE19_Pos 19 /*!< USB1 ENDPTNAKEN: EPTNE19 Position */ #define USB1_ENDPTNAKEN_EPTNE19_Msk (0x01UL << USB1_ENDPTNAKEN_EPTNE19_Pos) /*!< USB1 ENDPTNAKEN: EPTNE19 Mask */ /* ------------------------------- USB1_PORTSC1_D ------------------------------- */ #define USB1_PORTSC1_D_CCS_Pos 0 /*!< USB1 PORTSC1_D: CCS Position */ #define USB1_PORTSC1_D_CCS_Msk (0x01UL << USB1_PORTSC1_D_CCS_Pos) /*!< USB1 PORTSC1_D: CCS Mask */ #define USB1_PORTSC1_D_CSC_Pos 1 /*!< USB1 PORTSC1_D: CSC Position */ #define USB1_PORTSC1_D_CSC_Msk (0x01UL << USB1_PORTSC1_D_CSC_Pos) /*!< USB1 PORTSC1_D: CSC Mask */ #define USB1_PORTSC1_D_PE_Pos 2 /*!< USB1 PORTSC1_D: PE Position */ #define USB1_PORTSC1_D_PE_Msk (0x01UL << USB1_PORTSC1_D_PE_Pos) /*!< USB1 PORTSC1_D: PE Mask */ #define USB1_PORTSC1_D_PEC_Pos 3 /*!< USB1 PORTSC1_D: PEC Position */ #define USB1_PORTSC1_D_PEC_Msk (0x01UL << USB1_PORTSC1_D_PEC_Pos) /*!< USB1 PORTSC1_D: PEC Mask */ #define USB1_PORTSC1_D_FPR_Pos 6 /*!< USB1 PORTSC1_D: FPR Position */ #define USB1_PORTSC1_D_FPR_Msk (0x01UL << USB1_PORTSC1_D_FPR_Pos) /*!< USB1 PORTSC1_D: FPR Mask */ #define USB1_PORTSC1_D_SUSP_Pos 7 /*!< USB1 PORTSC1_D: SUSP Position */ #define USB1_PORTSC1_D_SUSP_Msk (0x01UL << USB1_PORTSC1_D_SUSP_Pos) /*!< USB1 PORTSC1_D: SUSP Mask */ #define USB1_PORTSC1_D_PR_Pos 8 /*!< USB1 PORTSC1_D: PR Position */ #define USB1_PORTSC1_D_PR_Msk (0x01UL << USB1_PORTSC1_D_PR_Pos) /*!< USB1 PORTSC1_D: PR Mask */ #define USB1_PORTSC1_D_HSP_Pos 9 /*!< USB1 PORTSC1_D: HSP Position */ #define USB1_PORTSC1_D_HSP_Msk (0x01UL << USB1_PORTSC1_D_HSP_Pos) /*!< USB1 PORTSC1_D: HSP Mask */ #define USB1_PORTSC1_D_LS_Pos 10 /*!< USB1 PORTSC1_D: LS Position */ #define USB1_PORTSC1_D_LS_Msk (0x03UL << USB1_PORTSC1_D_LS_Pos) /*!< USB1 PORTSC1_D: LS Mask */ #define USB1_PORTSC1_D_PP_Pos 12 /*!< USB1 PORTSC1_D: PP Position */ #define USB1_PORTSC1_D_PP_Msk (0x01UL << USB1_PORTSC1_D_PP_Pos) /*!< USB1 PORTSC1_D: PP Mask */ #define USB1_PORTSC1_D_PIC1_0_Pos 14 /*!< USB1 PORTSC1_D: PIC1_0 Position */ #define USB1_PORTSC1_D_PIC1_0_Msk (0x03UL << USB1_PORTSC1_D_PIC1_0_Pos) /*!< USB1 PORTSC1_D: PIC1_0 Mask */ #define USB1_PORTSC1_D_PTC3_0_Pos 16 /*!< USB1 PORTSC1_D: PTC3_0 Position */ #define USB1_PORTSC1_D_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_D_PTC3_0_Pos) /*!< USB1 PORTSC1_D: PTC3_0 Mask */ #define USB1_PORTSC1_D_PHCD_Pos 23 /*!< USB1 PORTSC1_D: PHCD Position */ #define USB1_PORTSC1_D_PHCD_Msk (0x01UL << USB1_PORTSC1_D_PHCD_Pos) /*!< USB1 PORTSC1_D: PHCD Mask */ #define USB1_PORTSC1_D_PFSC_Pos 24 /*!< USB1 PORTSC1_D: PFSC Position */ #define USB1_PORTSC1_D_PFSC_Msk (0x01UL << USB1_PORTSC1_D_PFSC_Pos) /*!< USB1 PORTSC1_D: PFSC Mask */ #define USB1_PORTSC1_D_PSPD_Pos 26 /*!< USB1 PORTSC1_D: PSPD Position */ #define USB1_PORTSC1_D_PSPD_Msk (0x03UL << USB1_PORTSC1_D_PSPD_Pos) /*!< USB1 PORTSC1_D: PSPD Mask */ #define USB1_PORTSC1_D_PTS_Pos 30 /*!< USB1 PORTSC1_D: PTS Position */ #define USB1_PORTSC1_D_PTS_Msk (0x03UL << USB1_PORTSC1_D_PTS_Pos) /*!< USB1 PORTSC1_D: PTS Mask */ /* ------------------------------- USB1_PORTSC1_H ------------------------------- */ #define USB1_PORTSC1_H_CCS_Pos 0 /*!< USB1 PORTSC1_H: CCS Position */ #define USB1_PORTSC1_H_CCS_Msk (0x01UL << USB1_PORTSC1_H_CCS_Pos) /*!< USB1 PORTSC1_H: CCS Mask */ #define USB1_PORTSC1_H_CSC_Pos 1 /*!< USB1 PORTSC1_H: CSC Position */ #define USB1_PORTSC1_H_CSC_Msk (0x01UL << USB1_PORTSC1_H_CSC_Pos) /*!< USB1 PORTSC1_H: CSC Mask */ #define USB1_PORTSC1_H_PE_Pos 2 /*!< USB1 PORTSC1_H: PE Position */ #define USB1_PORTSC1_H_PE_Msk (0x01UL << USB1_PORTSC1_H_PE_Pos) /*!< USB1 PORTSC1_H: PE Mask */ #define USB1_PORTSC1_H_PEC_Pos 3 /*!< USB1 PORTSC1_H: PEC Position */ #define USB1_PORTSC1_H_PEC_Msk (0x01UL << USB1_PORTSC1_H_PEC_Pos) /*!< USB1 PORTSC1_H: PEC Mask */ #define USB1_PORTSC1_H_OCA_Pos 4 /*!< USB1 PORTSC1_H: OCA Position */ #define USB1_PORTSC1_H_OCA_Msk (0x01UL << USB1_PORTSC1_H_OCA_Pos) /*!< USB1 PORTSC1_H: OCA Mask */ #define USB1_PORTSC1_H_OCC_Pos 5 /*!< USB1 PORTSC1_H: OCC Position */ #define USB1_PORTSC1_H_OCC_Msk (0x01UL << USB1_PORTSC1_H_OCC_Pos) /*!< USB1 PORTSC1_H: OCC Mask */ #define USB1_PORTSC1_H_FPR_Pos 6 /*!< USB1 PORTSC1_H: FPR Position */ #define USB1_PORTSC1_H_FPR_Msk (0x01UL << USB1_PORTSC1_H_FPR_Pos) /*!< USB1 PORTSC1_H: FPR Mask */ #define USB1_PORTSC1_H_SUSP_Pos 7 /*!< USB1 PORTSC1_H: SUSP Position */ #define USB1_PORTSC1_H_SUSP_Msk (0x01UL << USB1_PORTSC1_H_SUSP_Pos) /*!< USB1 PORTSC1_H: SUSP Mask */ #define USB1_PORTSC1_H_PR_Pos 8 /*!< USB1 PORTSC1_H: PR Position */ #define USB1_PORTSC1_H_PR_Msk (0x01UL << USB1_PORTSC1_H_PR_Pos) /*!< USB1 PORTSC1_H: PR Mask */ #define USB1_PORTSC1_H_HSP_Pos 9 /*!< USB1 PORTSC1_H: HSP Position */ #define USB1_PORTSC1_H_HSP_Msk (0x01UL << USB1_PORTSC1_H_HSP_Pos) /*!< USB1 PORTSC1_H: HSP Mask */ #define USB1_PORTSC1_H_LS_Pos 10 /*!< USB1 PORTSC1_H: LS Position */ #define USB1_PORTSC1_H_LS_Msk (0x03UL << USB1_PORTSC1_H_LS_Pos) /*!< USB1 PORTSC1_H: LS Mask */ #define USB1_PORTSC1_H_PP_Pos 12 /*!< USB1 PORTSC1_H: PP Position */ #define USB1_PORTSC1_H_PP_Msk (0x01UL << USB1_PORTSC1_H_PP_Pos) /*!< USB1 PORTSC1_H: PP Mask */ #define USB1_PORTSC1_H_PIC1_0_Pos 14 /*!< USB1 PORTSC1_H: PIC1_0 Position */ #define USB1_PORTSC1_H_PIC1_0_Msk (0x03UL << USB1_PORTSC1_H_PIC1_0_Pos) /*!< USB1 PORTSC1_H: PIC1_0 Mask */ #define USB1_PORTSC1_H_PTC3_0_Pos 16 /*!< USB1 PORTSC1_H: PTC3_0 Position */ #define USB1_PORTSC1_H_PTC3_0_Msk (0x0fUL << USB1_PORTSC1_H_PTC3_0_Pos) /*!< USB1 PORTSC1_H: PTC3_0 Mask */ #define USB1_PORTSC1_H_WKCN_Pos 20 /*!< USB1 PORTSC1_H: WKCN Position */ #define USB1_PORTSC1_H_WKCN_Msk (0x01UL << USB1_PORTSC1_H_WKCN_Pos) /*!< USB1 PORTSC1_H: WKCN Mask */ #define USB1_PORTSC1_H_WKDC_Pos 21 /*!< USB1 PORTSC1_H: WKDC Position */ #define USB1_PORTSC1_H_WKDC_Msk (0x01UL << USB1_PORTSC1_H_WKDC_Pos) /*!< USB1 PORTSC1_H: WKDC Mask */ #define USB1_PORTSC1_H_WKOC_Pos 22 /*!< USB1 PORTSC1_H: WKOC Position */ #define USB1_PORTSC1_H_WKOC_Msk (0x01UL << USB1_PORTSC1_H_WKOC_Pos) /*!< USB1 PORTSC1_H: WKOC Mask */ #define USB1_PORTSC1_H_PHCD_Pos 23 /*!< USB1 PORTSC1_H: PHCD Position */ #define USB1_PORTSC1_H_PHCD_Msk (0x01UL << USB1_PORTSC1_H_PHCD_Pos) /*!< USB1 PORTSC1_H: PHCD Mask */ #define USB1_PORTSC1_H_PFSC_Pos 24 /*!< USB1 PORTSC1_H: PFSC Position */ #define USB1_PORTSC1_H_PFSC_Msk (0x01UL << USB1_PORTSC1_H_PFSC_Pos) /*!< USB1 PORTSC1_H: PFSC Mask */ #define USB1_PORTSC1_H_PSPD_Pos 26 /*!< USB1 PORTSC1_H: PSPD Position */ #define USB1_PORTSC1_H_PSPD_Msk (0x03UL << USB1_PORTSC1_H_PSPD_Pos) /*!< USB1 PORTSC1_H: PSPD Mask */ #define USB1_PORTSC1_H_PTS_Pos 30 /*!< USB1 PORTSC1_H: PTS Position */ #define USB1_PORTSC1_H_PTS_Msk (0x03UL << USB1_PORTSC1_H_PTS_Pos) /*!< USB1 PORTSC1_H: PTS Mask */ /* ------------------------------- USB1_USBMODE_D ------------------------------- */ #define USB1_USBMODE_D_CM1_0_Pos 0 /*!< USB1 USBMODE_D: CM1_0 Position */ #define USB1_USBMODE_D_CM1_0_Msk (0x03UL << USB1_USBMODE_D_CM1_0_Pos) /*!< USB1 USBMODE_D: CM1_0 Mask */ #define USB1_USBMODE_D_ES_Pos 2 /*!< USB1 USBMODE_D: ES Position */ #define USB1_USBMODE_D_ES_Msk (0x01UL << USB1_USBMODE_D_ES_Pos) /*!< USB1 USBMODE_D: ES Mask */ #define USB1_USBMODE_D_SLOM_Pos 3 /*!< USB1 USBMODE_D: SLOM Position */ #define USB1_USBMODE_D_SLOM_Msk (0x01UL << USB1_USBMODE_D_SLOM_Pos) /*!< USB1 USBMODE_D: SLOM Mask */ #define USB1_USBMODE_D_SDIS_Pos 4 /*!< USB1 USBMODE_D: SDIS Position */ #define USB1_USBMODE_D_SDIS_Msk (0x01UL << USB1_USBMODE_D_SDIS_Pos) /*!< USB1 USBMODE_D: SDIS Mask */ /* ------------------------------- USB1_USBMODE_H ------------------------------- */ #define USB1_USBMODE_H_CM1_0_Pos 0 /*!< USB1 USBMODE_H: CM1_0 Position */ #define USB1_USBMODE_H_CM1_0_Msk (0x03UL << USB1_USBMODE_H_CM1_0_Pos) /*!< USB1 USBMODE_H: CM1_0 Mask */ #define USB1_USBMODE_H_ES_Pos 2 /*!< USB1 USBMODE_H: ES Position */ #define USB1_USBMODE_H_ES_Msk (0x01UL << USB1_USBMODE_H_ES_Pos) /*!< USB1 USBMODE_H: ES Mask */ #define USB1_USBMODE_H_SDIS_Pos 4 /*!< USB1 USBMODE_H: SDIS Position */ #define USB1_USBMODE_H_SDIS_Msk (0x01UL << USB1_USBMODE_H_SDIS_Pos) /*!< USB1 USBMODE_H: SDIS Mask */ #define USB1_USBMODE_H_VBPS_Pos 5 /*!< USB1 USBMODE_H: VBPS Position */ #define USB1_USBMODE_H_VBPS_Msk (0x01UL << USB1_USBMODE_H_VBPS_Pos) /*!< USB1 USBMODE_H: VBPS Mask */ /* ----------------------------- USB1_ENDPTSETUPSTAT ---------------------------- */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos 0 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Position */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT0_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT0 Mask */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos 1 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Position */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT1_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT1 Mask */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos 2 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Position */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT2_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT2 Mask */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos 3 /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Position */ #define USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Msk (0x01UL << USB1_ENDPTSETUPSTAT_ENDPTSETUPSTAT3_Pos) /*!< USB1 ENDPTSETUPSTAT: ENDPTSETUPSTAT3 Mask */ /* ------------------------------- USB1_ENDPTPRIME ------------------------------ */ #define USB1_ENDPTPRIME_PERB0_Pos 0 /*!< USB1 ENDPTPRIME: PERB0 Position */ #define USB1_ENDPTPRIME_PERB0_Msk (0x01UL << USB1_ENDPTPRIME_PERB0_Pos) /*!< USB1 ENDPTPRIME: PERB0 Mask */ #define USB1_ENDPTPRIME_PERB1_Pos 1 /*!< USB1 ENDPTPRIME: PERB1 Position */ #define USB1_ENDPTPRIME_PERB1_Msk (0x01UL << USB1_ENDPTPRIME_PERB1_Pos) /*!< USB1 ENDPTPRIME: PERB1 Mask */ #define USB1_ENDPTPRIME_PERB2_Pos 2 /*!< USB1 ENDPTPRIME: PERB2 Position */ #define USB1_ENDPTPRIME_PERB2_Msk (0x01UL << USB1_ENDPTPRIME_PERB2_Pos) /*!< USB1 ENDPTPRIME: PERB2 Mask */ #define USB1_ENDPTPRIME_PERB3_Pos 3 /*!< USB1 ENDPTPRIME: PERB3 Position */ #define USB1_ENDPTPRIME_PERB3_Msk (0x01UL << USB1_ENDPTPRIME_PERB3_Pos) /*!< USB1 ENDPTPRIME: PERB3 Mask */ #define USB1_ENDPTPRIME_PETB0_Pos 16 /*!< USB1 ENDPTPRIME: PETB0 Position */ #define USB1_ENDPTPRIME_PETB0_Msk (0x01UL << USB1_ENDPTPRIME_PETB0_Pos) /*!< USB1 ENDPTPRIME: PETB0 Mask */ #define USB1_ENDPTPRIME_PETB1_Pos 17 /*!< USB1 ENDPTPRIME: PETB1 Position */ #define USB1_ENDPTPRIME_PETB1_Msk (0x01UL << USB1_ENDPTPRIME_PETB1_Pos) /*!< USB1 ENDPTPRIME: PETB1 Mask */ #define USB1_ENDPTPRIME_PETB2_Pos 18 /*!< USB1 ENDPTPRIME: PETB2 Position */ #define USB1_ENDPTPRIME_PETB2_Msk (0x01UL << USB1_ENDPTPRIME_PETB2_Pos) /*!< USB1 ENDPTPRIME: PETB2 Mask */ #define USB1_ENDPTPRIME_PETB3_Pos 19 /*!< USB1 ENDPTPRIME: PETB3 Position */ #define USB1_ENDPTPRIME_PETB3_Msk (0x01UL << USB1_ENDPTPRIME_PETB3_Pos) /*!< USB1 ENDPTPRIME: PETB3 Mask */ /* ------------------------------- USB1_ENDPTFLUSH ------------------------------ */ #define USB1_ENDPTFLUSH_FERB0_Pos 0 /*!< USB1 ENDPTFLUSH: FERB0 Position */ #define USB1_ENDPTFLUSH_FERB0_Msk (0x01UL << USB1_ENDPTFLUSH_FERB0_Pos) /*!< USB1 ENDPTFLUSH: FERB0 Mask */ #define USB1_ENDPTFLUSH_FERB1_Pos 1 /*!< USB1 ENDPTFLUSH: FERB1 Position */ #define USB1_ENDPTFLUSH_FERB1_Msk (0x01UL << USB1_ENDPTFLUSH_FERB1_Pos) /*!< USB1 ENDPTFLUSH: FERB1 Mask */ #define USB1_ENDPTFLUSH_FERB2_Pos 2 /*!< USB1 ENDPTFLUSH: FERB2 Position */ #define USB1_ENDPTFLUSH_FERB2_Msk (0x01UL << USB1_ENDPTFLUSH_FERB2_Pos) /*!< USB1 ENDPTFLUSH: FERB2 Mask */ #define USB1_ENDPTFLUSH_FERB3_Pos 3 /*!< USB1 ENDPTFLUSH: FERB3 Position */ #define USB1_ENDPTFLUSH_FERB3_Msk (0x01UL << USB1_ENDPTFLUSH_FERB3_Pos) /*!< USB1 ENDPTFLUSH: FERB3 Mask */ #define USB1_ENDPTFLUSH_FETB0_Pos 16 /*!< USB1 ENDPTFLUSH: FETB0 Position */ #define USB1_ENDPTFLUSH_FETB0_Msk (0x01UL << USB1_ENDPTFLUSH_FETB0_Pos) /*!< USB1 ENDPTFLUSH: FETB0 Mask */ #define USB1_ENDPTFLUSH_FETB1_Pos 17 /*!< USB1 ENDPTFLUSH: FETB1 Position */ #define USB1_ENDPTFLUSH_FETB1_Msk (0x01UL << USB1_ENDPTFLUSH_FETB1_Pos) /*!< USB1 ENDPTFLUSH: FETB1 Mask */ #define USB1_ENDPTFLUSH_FETB2_Pos 18 /*!< USB1 ENDPTFLUSH: FETB2 Position */ #define USB1_ENDPTFLUSH_FETB2_Msk (0x01UL << USB1_ENDPTFLUSH_FETB2_Pos) /*!< USB1 ENDPTFLUSH: FETB2 Mask */ #define USB1_ENDPTFLUSH_FETB3_Pos 19 /*!< USB1 ENDPTFLUSH: FETB3 Position */ #define USB1_ENDPTFLUSH_FETB3_Msk (0x01UL << USB1_ENDPTFLUSH_FETB3_Pos) /*!< USB1 ENDPTFLUSH: FETB3 Mask */ /* ------------------------------- USB1_ENDPTSTAT ------------------------------- */ #define USB1_ENDPTSTAT_ERBR0_Pos 0 /*!< USB1 ENDPTSTAT: ERBR0 Position */ #define USB1_ENDPTSTAT_ERBR0_Msk (0x01UL << USB1_ENDPTSTAT_ERBR0_Pos) /*!< USB1 ENDPTSTAT: ERBR0 Mask */ #define USB1_ENDPTSTAT_ERBR1_Pos 1 /*!< USB1 ENDPTSTAT: ERBR1 Position */ #define USB1_ENDPTSTAT_ERBR1_Msk (0x01UL << USB1_ENDPTSTAT_ERBR1_Pos) /*!< USB1 ENDPTSTAT: ERBR1 Mask */ #define USB1_ENDPTSTAT_ERBR2_Pos 2 /*!< USB1 ENDPTSTAT: ERBR2 Position */ #define USB1_ENDPTSTAT_ERBR2_Msk (0x01UL << USB1_ENDPTSTAT_ERBR2_Pos) /*!< USB1 ENDPTSTAT: ERBR2 Mask */ #define USB1_ENDPTSTAT_ERBR3_Pos 3 /*!< USB1 ENDPTSTAT: ERBR3 Position */ #define USB1_ENDPTSTAT_ERBR3_Msk (0x01UL << USB1_ENDPTSTAT_ERBR3_Pos) /*!< USB1 ENDPTSTAT: ERBR3 Mask */ #define USB1_ENDPTSTAT_ETBR0_Pos 16 /*!< USB1 ENDPTSTAT: ETBR0 Position */ #define USB1_ENDPTSTAT_ETBR0_Msk (0x01UL << USB1_ENDPTSTAT_ETBR0_Pos) /*!< USB1 ENDPTSTAT: ETBR0 Mask */ #define USB1_ENDPTSTAT_ETBR1_Pos 17 /*!< USB1 ENDPTSTAT: ETBR1 Position */ #define USB1_ENDPTSTAT_ETBR1_Msk (0x01UL << USB1_ENDPTSTAT_ETBR1_Pos) /*!< USB1 ENDPTSTAT: ETBR1 Mask */ #define USB1_ENDPTSTAT_ETBR2_Pos 18 /*!< USB1 ENDPTSTAT: ETBR2 Position */ #define USB1_ENDPTSTAT_ETBR2_Msk (0x01UL << USB1_ENDPTSTAT_ETBR2_Pos) /*!< USB1 ENDPTSTAT: ETBR2 Mask */ #define USB1_ENDPTSTAT_ETBR3_Pos 19 /*!< USB1 ENDPTSTAT: ETBR3 Position */ #define USB1_ENDPTSTAT_ETBR3_Msk (0x01UL << USB1_ENDPTSTAT_ETBR3_Pos) /*!< USB1 ENDPTSTAT: ETBR3 Mask */ /* ----------------------------- USB1_ENDPTCOMPLETE ----------------------------- */ #define USB1_ENDPTCOMPLETE_ERCE0_Pos 0 /*!< USB1 ENDPTCOMPLETE: ERCE0 Position */ #define USB1_ENDPTCOMPLETE_ERCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE0 Mask */ #define USB1_ENDPTCOMPLETE_ERCE1_Pos 1 /*!< USB1 ENDPTCOMPLETE: ERCE1 Position */ #define USB1_ENDPTCOMPLETE_ERCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE1 Mask */ #define USB1_ENDPTCOMPLETE_ERCE2_Pos 2 /*!< USB1 ENDPTCOMPLETE: ERCE2 Position */ #define USB1_ENDPTCOMPLETE_ERCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE2 Mask */ #define USB1_ENDPTCOMPLETE_ERCE3_Pos 3 /*!< USB1 ENDPTCOMPLETE: ERCE3 Position */ #define USB1_ENDPTCOMPLETE_ERCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ERCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ERCE3 Mask */ #define USB1_ENDPTCOMPLETE_ETCE0_Pos 16 /*!< USB1 ENDPTCOMPLETE: ETCE0 Position */ #define USB1_ENDPTCOMPLETE_ETCE0_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE0_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE0 Mask */ #define USB1_ENDPTCOMPLETE_ETCE1_Pos 17 /*!< USB1 ENDPTCOMPLETE: ETCE1 Position */ #define USB1_ENDPTCOMPLETE_ETCE1_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE1_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE1 Mask */ #define USB1_ENDPTCOMPLETE_ETCE2_Pos 18 /*!< USB1 ENDPTCOMPLETE: ETCE2 Position */ #define USB1_ENDPTCOMPLETE_ETCE2_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE2_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE2 Mask */ #define USB1_ENDPTCOMPLETE_ETCE3_Pos 19 /*!< USB1 ENDPTCOMPLETE: ETCE3 Position */ #define USB1_ENDPTCOMPLETE_ETCE3_Msk (0x01UL << USB1_ENDPTCOMPLETE_ETCE3_Pos) /*!< USB1 ENDPTCOMPLETE: ETCE3 Mask */ /* ------------------------------- USB1_ENDPTCTRL0 ------------------------------ */ #define USB1_ENDPTCTRL0_RXS_Pos 0 /*!< USB1 ENDPTCTRL0: RXS Position */ #define USB1_ENDPTCTRL0_RXS_Msk (0x01UL << USB1_ENDPTCTRL0_RXS_Pos) /*!< USB1 ENDPTCTRL0: RXS Mask */ #define USB1_ENDPTCTRL0_RXT_Pos 2 /*!< USB1 ENDPTCTRL0: RXT Position */ #define USB1_ENDPTCTRL0_RXT_Msk (0x03UL << USB1_ENDPTCTRL0_RXT_Pos) /*!< USB1 ENDPTCTRL0: RXT Mask */ #define USB1_ENDPTCTRL0_RXE_Pos 7 /*!< USB1 ENDPTCTRL0: RXE Position */ #define USB1_ENDPTCTRL0_RXE_Msk (0x01UL << USB1_ENDPTCTRL0_RXE_Pos) /*!< USB1 ENDPTCTRL0: RXE Mask */ #define USB1_ENDPTCTRL0_TXS_Pos 16 /*!< USB1 ENDPTCTRL0: TXS Position */ #define USB1_ENDPTCTRL0_TXS_Msk (0x01UL << USB1_ENDPTCTRL0_TXS_Pos) /*!< USB1 ENDPTCTRL0: TXS Mask */ #define USB1_ENDPTCTRL0_TXT_Pos 18 /*!< USB1 ENDPTCTRL0: TXT Position */ #define USB1_ENDPTCTRL0_TXT_Msk (0x03UL << USB1_ENDPTCTRL0_TXT_Pos) /*!< USB1 ENDPTCTRL0: TXT Mask */ #define USB1_ENDPTCTRL0_TXE_Pos 23 /*!< USB1 ENDPTCTRL0: TXE Position */ #define USB1_ENDPTCTRL0_TXE_Msk (0x01UL << USB1_ENDPTCTRL0_TXE_Pos) /*!< USB1 ENDPTCTRL0: TXE Mask */ /* ------------------------------- USB1_ENDPTCTRL1 ------------------------------ */ #define USB1_ENDPTCTRL1_RXS_Pos 0 /*!< USB1 ENDPTCTRL1: RXS Position */ #define USB1_ENDPTCTRL1_RXS_Msk (0x01UL << USB1_ENDPTCTRL1_RXS_Pos) /*!< USB1 ENDPTCTRL1: RXS Mask */ #define USB1_ENDPTCTRL1_RXT_Pos 2 /*!< USB1 ENDPTCTRL1: RXT Position */ #define USB1_ENDPTCTRL1_RXT_Msk (0x03UL << USB1_ENDPTCTRL1_RXT_Pos) /*!< USB1 ENDPTCTRL1: RXT Mask */ #define USB1_ENDPTCTRL1_RXI_Pos 5 /*!< USB1 ENDPTCTRL1: RXI Position */ #define USB1_ENDPTCTRL1_RXI_Msk (0x01UL << USB1_ENDPTCTRL1_RXI_Pos) /*!< USB1 ENDPTCTRL1: RXI Mask */ #define USB1_ENDPTCTRL1_RXR_Pos 6 /*!< USB1 ENDPTCTRL1: RXR Position */ #define USB1_ENDPTCTRL1_RXR_Msk (0x01UL << USB1_ENDPTCTRL1_RXR_Pos) /*!< USB1 ENDPTCTRL1: RXR Mask */ #define USB1_ENDPTCTRL1_RXE_Pos 7 /*!< USB1 ENDPTCTRL1: RXE Position */ #define USB1_ENDPTCTRL1_RXE_Msk (0x01UL << USB1_ENDPTCTRL1_RXE_Pos) /*!< USB1 ENDPTCTRL1: RXE Mask */ #define USB1_ENDPTCTRL1_TXS_Pos 16 /*!< USB1 ENDPTCTRL1: TXS Position */ #define USB1_ENDPTCTRL1_TXS_Msk (0x01UL << USB1_ENDPTCTRL1_TXS_Pos) /*!< USB1 ENDPTCTRL1: TXS Mask */ #define USB1_ENDPTCTRL1_TXT_Pos 18 /*!< USB1 ENDPTCTRL1: TXT Position */ #define USB1_ENDPTCTRL1_TXT_Msk (0x03UL << USB1_ENDPTCTRL1_TXT_Pos) /*!< USB1 ENDPTCTRL1: TXT Mask */ #define USB1_ENDPTCTRL1_TXI_Pos 21 /*!< USB1 ENDPTCTRL1: TXI Position */ #define USB1_ENDPTCTRL1_TXI_Msk (0x01UL << USB1_ENDPTCTRL1_TXI_Pos) /*!< USB1 ENDPTCTRL1: TXI Mask */ #define USB1_ENDPTCTRL1_TXR_Pos 22 /*!< USB1 ENDPTCTRL1: TXR Position */ #define USB1_ENDPTCTRL1_TXR_Msk (0x01UL << USB1_ENDPTCTRL1_TXR_Pos) /*!< USB1 ENDPTCTRL1: TXR Mask */ #define USB1_ENDPTCTRL1_TXE_Pos 23 /*!< USB1 ENDPTCTRL1: TXE Position */ #define USB1_ENDPTCTRL1_TXE_Msk (0x01UL << USB1_ENDPTCTRL1_TXE_Pos) /*!< USB1 ENDPTCTRL1: TXE Mask */ /* ------------------------------- USB1_ENDPTCTRL2 ------------------------------ */ #define USB1_ENDPTCTRL2_RXS_Pos 0 /*!< USB1 ENDPTCTRL2: RXS Position */ #define USB1_ENDPTCTRL2_RXS_Msk (0x01UL << USB1_ENDPTCTRL2_RXS_Pos) /*!< USB1 ENDPTCTRL2: RXS Mask */ #define USB1_ENDPTCTRL2_RXT_Pos 2 /*!< USB1 ENDPTCTRL2: RXT Position */ #define USB1_ENDPTCTRL2_RXT_Msk (0x03UL << USB1_ENDPTCTRL2_RXT_Pos) /*!< USB1 ENDPTCTRL2: RXT Mask */ #define USB1_ENDPTCTRL2_RXI_Pos 5 /*!< USB1 ENDPTCTRL2: RXI Position */ #define USB1_ENDPTCTRL2_RXI_Msk (0x01UL << USB1_ENDPTCTRL2_RXI_Pos) /*!< USB1 ENDPTCTRL2: RXI Mask */ #define USB1_ENDPTCTRL2_RXR_Pos 6 /*!< USB1 ENDPTCTRL2: RXR Position */ #define USB1_ENDPTCTRL2_RXR_Msk (0x01UL << USB1_ENDPTCTRL2_RXR_Pos) /*!< USB1 ENDPTCTRL2: RXR Mask */ #define USB1_ENDPTCTRL2_RXE_Pos 7 /*!< USB1 ENDPTCTRL2: RXE Position */ #define USB1_ENDPTCTRL2_RXE_Msk (0x01UL << USB1_ENDPTCTRL2_RXE_Pos) /*!< USB1 ENDPTCTRL2: RXE Mask */ #define USB1_ENDPTCTRL2_TXS_Pos 16 /*!< USB1 ENDPTCTRL2: TXS Position */ #define USB1_ENDPTCTRL2_TXS_Msk (0x01UL << USB1_ENDPTCTRL2_TXS_Pos) /*!< USB1 ENDPTCTRL2: TXS Mask */ #define USB1_ENDPTCTRL2_TXT_Pos 18 /*!< USB1 ENDPTCTRL2: TXT Position */ #define USB1_ENDPTCTRL2_TXT_Msk (0x03UL << USB1_ENDPTCTRL2_TXT_Pos) /*!< USB1 ENDPTCTRL2: TXT Mask */ #define USB1_ENDPTCTRL2_TXI_Pos 21 /*!< USB1 ENDPTCTRL2: TXI Position */ #define USB1_ENDPTCTRL2_TXI_Msk (0x01UL << USB1_ENDPTCTRL2_TXI_Pos) /*!< USB1 ENDPTCTRL2: TXI Mask */ #define USB1_ENDPTCTRL2_TXR_Pos 22 /*!< USB1 ENDPTCTRL2: TXR Position */ #define USB1_ENDPTCTRL2_TXR_Msk (0x01UL << USB1_ENDPTCTRL2_TXR_Pos) /*!< USB1 ENDPTCTRL2: TXR Mask */ #define USB1_ENDPTCTRL2_TXE_Pos 23 /*!< USB1 ENDPTCTRL2: TXE Position */ #define USB1_ENDPTCTRL2_TXE_Msk (0x01UL << USB1_ENDPTCTRL2_TXE_Pos) /*!< USB1 ENDPTCTRL2: TXE Mask */ /* ------------------------------- USB1_ENDPTCTRL3 ------------------------------ */ #define USB1_ENDPTCTRL3_RXS_Pos 0 /*!< USB1 ENDPTCTRL3: RXS Position */ #define USB1_ENDPTCTRL3_RXS_Msk (0x01UL << USB1_ENDPTCTRL3_RXS_Pos) /*!< USB1 ENDPTCTRL3: RXS Mask */ #define USB1_ENDPTCTRL3_RXT_Pos 2 /*!< USB1 ENDPTCTRL3: RXT Position */ #define USB1_ENDPTCTRL3_RXT_Msk (0x03UL << USB1_ENDPTCTRL3_RXT_Pos) /*!< USB1 ENDPTCTRL3: RXT Mask */ #define USB1_ENDPTCTRL3_RXI_Pos 5 /*!< USB1 ENDPTCTRL3: RXI Position */ #define USB1_ENDPTCTRL3_RXI_Msk (0x01UL << USB1_ENDPTCTRL3_RXI_Pos) /*!< USB1 ENDPTCTRL3: RXI Mask */ #define USB1_ENDPTCTRL3_RXR_Pos 6 /*!< USB1 ENDPTCTRL3: RXR Position */ #define USB1_ENDPTCTRL3_RXR_Msk (0x01UL << USB1_ENDPTCTRL3_RXR_Pos) /*!< USB1 ENDPTCTRL3: RXR Mask */ #define USB1_ENDPTCTRL3_RXE_Pos 7 /*!< USB1 ENDPTCTRL3: RXE Position */ #define USB1_ENDPTCTRL3_RXE_Msk (0x01UL << USB1_ENDPTCTRL3_RXE_Pos) /*!< USB1 ENDPTCTRL3: RXE Mask */ #define USB1_ENDPTCTRL3_TXS_Pos 16 /*!< USB1 ENDPTCTRL3: TXS Position */ #define USB1_ENDPTCTRL3_TXS_Msk (0x01UL << USB1_ENDPTCTRL3_TXS_Pos) /*!< USB1 ENDPTCTRL3: TXS Mask */ #define USB1_ENDPTCTRL3_TXT_Pos 18 /*!< USB1 ENDPTCTRL3: TXT Position */ #define USB1_ENDPTCTRL3_TXT_Msk (0x03UL << USB1_ENDPTCTRL3_TXT_Pos) /*!< USB1 ENDPTCTRL3: TXT Mask */ #define USB1_ENDPTCTRL3_TXI_Pos 21 /*!< USB1 ENDPTCTRL3: TXI Position */ #define USB1_ENDPTCTRL3_TXI_Msk (0x01UL << USB1_ENDPTCTRL3_TXI_Pos) /*!< USB1 ENDPTCTRL3: TXI Mask */ #define USB1_ENDPTCTRL3_TXR_Pos 22 /*!< USB1 ENDPTCTRL3: TXR Position */ #define USB1_ENDPTCTRL3_TXR_Msk (0x01UL << USB1_ENDPTCTRL3_TXR_Pos) /*!< USB1 ENDPTCTRL3: TXR Mask */ #define USB1_ENDPTCTRL3_TXE_Pos 23 /*!< USB1 ENDPTCTRL3: TXE Position */ #define USB1_ENDPTCTRL3_TXE_Msk (0x01UL << USB1_ENDPTCTRL3_TXE_Pos) /*!< USB1 ENDPTCTRL3: TXE Mask */ /* ================================================================================ */ /* ================ struct 'LCD' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- LCD_TIMH ---------------------------------- */ #define LCD_TIMH_PPL_Pos 2 /*!< LCD TIMH: PPL Position */ #define LCD_TIMH_PPL_Msk (0x3fUL << LCD_TIMH_PPL_Pos) /*!< LCD TIMH: PPL Mask */ #define LCD_TIMH_HSW_Pos 8 /*!< LCD TIMH: HSW Position */ #define LCD_TIMH_HSW_Msk (0x000000ffUL << LCD_TIMH_HSW_Pos) /*!< LCD TIMH: HSW Mask */ #define LCD_TIMH_HFP_Pos 16 /*!< LCD TIMH: HFP Position */ #define LCD_TIMH_HFP_Msk (0x000000ffUL << LCD_TIMH_HFP_Pos) /*!< LCD TIMH: HFP Mask */ #define LCD_TIMH_HBP_Pos 24 /*!< LCD TIMH: HBP Position */ #define LCD_TIMH_HBP_Msk (0x000000ffUL << LCD_TIMH_HBP_Pos) /*!< LCD TIMH: HBP Mask */ /* ---------------------------------- LCD_TIMV ---------------------------------- */ #define LCD_TIMV_LPP_Pos 0 /*!< LCD TIMV: LPP Position */ #define LCD_TIMV_LPP_Msk (0x000003ffUL << LCD_TIMV_LPP_Pos) /*!< LCD TIMV: LPP Mask */ #define LCD_TIMV_VSW_Pos 10 /*!< LCD TIMV: VSW Position */ #define LCD_TIMV_VSW_Msk (0x3fUL << LCD_TIMV_VSW_Pos) /*!< LCD TIMV: VSW Mask */ #define LCD_TIMV_VFP_Pos 16 /*!< LCD TIMV: VFP Position */ #define LCD_TIMV_VFP_Msk (0x000000ffUL << LCD_TIMV_VFP_Pos) /*!< LCD TIMV: VFP Mask */ #define LCD_TIMV_VBP_Pos 24 /*!< LCD TIMV: VBP Position */ #define LCD_TIMV_VBP_Msk (0x000000ffUL << LCD_TIMV_VBP_Pos) /*!< LCD TIMV: VBP Mask */ /* ----------------------------------- LCD_POL ---------------------------------- */ #define LCD_POL_PCD_LO_Pos 0 /*!< LCD POL: PCD_LO Position */ #define LCD_POL_PCD_LO_Msk (0x1fUL << LCD_POL_PCD_LO_Pos) /*!< LCD POL: PCD_LO Mask */ #define LCD_POL_CLKSEL_Pos 5 /*!< LCD POL: CLKSEL Position */ #define LCD_POL_CLKSEL_Msk (0x01UL << LCD_POL_CLKSEL_Pos) /*!< LCD POL: CLKSEL Mask */ #define LCD_POL_ACB_Pos 6 /*!< LCD POL: ACB Position */ #define LCD_POL_ACB_Msk (0x1fUL << LCD_POL_ACB_Pos) /*!< LCD POL: ACB Mask */ #define LCD_POL_IVS_Pos 11 /*!< LCD POL: IVS Position */ #define LCD_POL_IVS_Msk (0x01UL << LCD_POL_IVS_Pos) /*!< LCD POL: IVS Mask */ #define LCD_POL_IHS_Pos 12 /*!< LCD POL: IHS Position */ #define LCD_POL_IHS_Msk (0x01UL << LCD_POL_IHS_Pos) /*!< LCD POL: IHS Mask */ #define LCD_POL_IPC_Pos 13 /*!< LCD POL: IPC Position */ #define LCD_POL_IPC_Msk (0x01UL << LCD_POL_IPC_Pos) /*!< LCD POL: IPC Mask */ #define LCD_POL_IOE_Pos 14 /*!< LCD POL: IOE Position */ #define LCD_POL_IOE_Msk (0x01UL << LCD_POL_IOE_Pos) /*!< LCD POL: IOE Mask */ #define LCD_POL_CPL_Pos 16 /*!< LCD POL: CPL Position */ #define LCD_POL_CPL_Msk (0x000003ffUL << LCD_POL_CPL_Pos) /*!< LCD POL: CPL Mask */ #define LCD_POL_BCD_Pos 26 /*!< LCD POL: BCD Position */ #define LCD_POL_BCD_Msk (0x01UL << LCD_POL_BCD_Pos) /*!< LCD POL: BCD Mask */ #define LCD_POL_PCD_HI_Pos 27 /*!< LCD POL: PCD_HI Position */ #define LCD_POL_PCD_HI_Msk (0x1fUL << LCD_POL_PCD_HI_Pos) /*!< LCD POL: PCD_HI Mask */ /* ----------------------------------- LCD_LE ----------------------------------- */ #define LCD_LE_LED_Pos 0 /*!< LCD LE: LED Position */ #define LCD_LE_LED_Msk (0x7fUL << LCD_LE_LED_Pos) /*!< LCD LE: LED Mask */ #define LCD_LE_LEE_Pos 16 /*!< LCD LE: LEE Position */ #define LCD_LE_LEE_Msk (0x01UL << LCD_LE_LEE_Pos) /*!< LCD LE: LEE Mask */ /* --------------------------------- LCD_UPBASE --------------------------------- */ #define LCD_UPBASE_LCDUPBASE_Pos 3 /*!< LCD UPBASE: LCDUPBASE Position */ #define LCD_UPBASE_LCDUPBASE_Msk (0x1fffffffUL << LCD_UPBASE_LCDUPBASE_Pos) /*!< LCD UPBASE: LCDUPBASE Mask */ /* --------------------------------- LCD_LPBASE --------------------------------- */ #define LCD_LPBASE_LCDLPBASE_Pos 3 /*!< LCD LPBASE: LCDLPBASE Position */ #define LCD_LPBASE_LCDLPBASE_Msk (0x1fffffffUL << LCD_LPBASE_LCDLPBASE_Pos) /*!< LCD LPBASE: LCDLPBASE Mask */ /* ---------------------------------- LCD_CTRL ---------------------------------- */ #define LCD_CTRL_LCDEN_Pos 0 /*!< LCD CTRL: LCDEN Position */ #define LCD_CTRL_LCDEN_Msk (0x01UL << LCD_CTRL_LCDEN_Pos) /*!< LCD CTRL: LCDEN Mask */ #define LCD_CTRL_LCDBPP_Pos 1 /*!< LCD CTRL: LCDBPP Position */ #define LCD_CTRL_LCDBPP_Msk (0x07UL << LCD_CTRL_LCDBPP_Pos) /*!< LCD CTRL: LCDBPP Mask */ #define LCD_CTRL_LCDBW_Pos 4 /*!< LCD CTRL: LCDBW Position */ #define LCD_CTRL_LCDBW_Msk (0x01UL << LCD_CTRL_LCDBW_Pos) /*!< LCD CTRL: LCDBW Mask */ #define LCD_CTRL_LCDTFT_Pos 5 /*!< LCD CTRL: LCDTFT Position */ #define LCD_CTRL_LCDTFT_Msk (0x01UL << LCD_CTRL_LCDTFT_Pos) /*!< LCD CTRL: LCDTFT Mask */ #define LCD_CTRL_LCDMONO8_Pos 6 /*!< LCD CTRL: LCDMONO8 Position */ #define LCD_CTRL_LCDMONO8_Msk (0x01UL << LCD_CTRL_LCDMONO8_Pos) /*!< LCD CTRL: LCDMONO8 Mask */ #define LCD_CTRL_LCDDUAL_Pos 7 /*!< LCD CTRL: LCDDUAL Position */ #define LCD_CTRL_LCDDUAL_Msk (0x01UL << LCD_CTRL_LCDDUAL_Pos) /*!< LCD CTRL: LCDDUAL Mask */ #define LCD_CTRL_BGR_Pos 8 /*!< LCD CTRL: BGR Position */ #define LCD_CTRL_BGR_Msk (0x01UL << LCD_CTRL_BGR_Pos) /*!< LCD CTRL: BGR Mask */ #define LCD_CTRL_BEBO_Pos 9 /*!< LCD CTRL: BEBO Position */ #define LCD_CTRL_BEBO_Msk (0x01UL << LCD_CTRL_BEBO_Pos) /*!< LCD CTRL: BEBO Mask */ #define LCD_CTRL_BEPO_Pos 10 /*!< LCD CTRL: BEPO Position */ #define LCD_CTRL_BEPO_Msk (0x01UL << LCD_CTRL_BEPO_Pos) /*!< LCD CTRL: BEPO Mask */ #define LCD_CTRL_LCDPWR_Pos 11 /*!< LCD CTRL: LCDPWR Position */ #define LCD_CTRL_LCDPWR_Msk (0x01UL << LCD_CTRL_LCDPWR_Pos) /*!< LCD CTRL: LCDPWR Mask */ #define LCD_CTRL_LCDVCOMP_Pos 12 /*!< LCD CTRL: LCDVCOMP Position */ #define LCD_CTRL_LCDVCOMP_Msk (0x03UL << LCD_CTRL_LCDVCOMP_Pos) /*!< LCD CTRL: LCDVCOMP Mask */ #define LCD_CTRL_WATERMARK_Pos 16 /*!< LCD CTRL: WATERMARK Position */ #define LCD_CTRL_WATERMARK_Msk (0x01UL << LCD_CTRL_WATERMARK_Pos) /*!< LCD CTRL: WATERMARK Mask */ /* --------------------------------- LCD_INTMSK --------------------------------- */ #define LCD_INTMSK_FUFIM_Pos 1 /*!< LCD INTMSK: FUFIM Position */ #define LCD_INTMSK_FUFIM_Msk (0x01UL << LCD_INTMSK_FUFIM_Pos) /*!< LCD INTMSK: FUFIM Mask */ #define LCD_INTMSK_LNBUIM_Pos 2 /*!< LCD INTMSK: LNBUIM Position */ #define LCD_INTMSK_LNBUIM_Msk (0x01UL << LCD_INTMSK_LNBUIM_Pos) /*!< LCD INTMSK: LNBUIM Mask */ #define LCD_INTMSK_VCOMPIM_Pos 3 /*!< LCD INTMSK: VCOMPIM Position */ #define LCD_INTMSK_VCOMPIM_Msk (0x01UL << LCD_INTMSK_VCOMPIM_Pos) /*!< LCD INTMSK: VCOMPIM Mask */ #define LCD_INTMSK_BERIM_Pos 4 /*!< LCD INTMSK: BERIM Position */ #define LCD_INTMSK_BERIM_Msk (0x01UL << LCD_INTMSK_BERIM_Pos) /*!< LCD INTMSK: BERIM Mask */ /* --------------------------------- LCD_INTRAW --------------------------------- */ #define LCD_INTRAW_FUFRIS_Pos 1 /*!< LCD INTRAW: FUFRIS Position */ #define LCD_INTRAW_FUFRIS_Msk (0x01UL << LCD_INTRAW_FUFRIS_Pos) /*!< LCD INTRAW: FUFRIS Mask */ #define LCD_INTRAW_LNBURIS_Pos 2 /*!< LCD INTRAW: LNBURIS Position */ #define LCD_INTRAW_LNBURIS_Msk (0x01UL << LCD_INTRAW_LNBURIS_Pos) /*!< LCD INTRAW: LNBURIS Mask */ #define LCD_INTRAW_VCOMPRIS_Pos 3 /*!< LCD INTRAW: VCOMPRIS Position */ #define LCD_INTRAW_VCOMPRIS_Msk (0x01UL << LCD_INTRAW_VCOMPRIS_Pos) /*!< LCD INTRAW: VCOMPRIS Mask */ #define LCD_INTRAW_BERRAW_Pos 4 /*!< LCD INTRAW: BERRAW Position */ #define LCD_INTRAW_BERRAW_Msk (0x01UL << LCD_INTRAW_BERRAW_Pos) /*!< LCD INTRAW: BERRAW Mask */ /* --------------------------------- LCD_INTSTAT -------------------------------- */ #define LCD_INTSTAT_FUFMIS_Pos 1 /*!< LCD INTSTAT: FUFMIS Position */ #define LCD_INTSTAT_FUFMIS_Msk (0x01UL << LCD_INTSTAT_FUFMIS_Pos) /*!< LCD INTSTAT: FUFMIS Mask */ #define LCD_INTSTAT_LNBUMIS_Pos 2 /*!< LCD INTSTAT: LNBUMIS Position */ #define LCD_INTSTAT_LNBUMIS_Msk (0x01UL << LCD_INTSTAT_LNBUMIS_Pos) /*!< LCD INTSTAT: LNBUMIS Mask */ #define LCD_INTSTAT_VCOMPMIS_Pos 3 /*!< LCD INTSTAT: VCOMPMIS Position */ #define LCD_INTSTAT_VCOMPMIS_Msk (0x01UL << LCD_INTSTAT_VCOMPMIS_Pos) /*!< LCD INTSTAT: VCOMPMIS Mask */ #define LCD_INTSTAT_BERMIS_Pos 4 /*!< LCD INTSTAT: BERMIS Position */ #define LCD_INTSTAT_BERMIS_Msk (0x01UL << LCD_INTSTAT_BERMIS_Pos) /*!< LCD INTSTAT: BERMIS Mask */ /* --------------------------------- LCD_INTCLR --------------------------------- */ #define LCD_INTCLR_FUFIC_Pos 1 /*!< LCD INTCLR: FUFIC Position */ #define LCD_INTCLR_FUFIC_Msk (0x01UL << LCD_INTCLR_FUFIC_Pos) /*!< LCD INTCLR: FUFIC Mask */ #define LCD_INTCLR_LNBUIC_Pos 2 /*!< LCD INTCLR: LNBUIC Position */ #define LCD_INTCLR_LNBUIC_Msk (0x01UL << LCD_INTCLR_LNBUIC_Pos) /*!< LCD INTCLR: LNBUIC Mask */ #define LCD_INTCLR_VCOMPIC_Pos 3 /*!< LCD INTCLR: VCOMPIC Position */ #define LCD_INTCLR_VCOMPIC_Msk (0x01UL << LCD_INTCLR_VCOMPIC_Pos) /*!< LCD INTCLR: VCOMPIC Mask */ #define LCD_INTCLR_BERIC_Pos 4 /*!< LCD INTCLR: BERIC Position */ #define LCD_INTCLR_BERIC_Msk (0x01UL << LCD_INTCLR_BERIC_Pos) /*!< LCD INTCLR: BERIC Mask */ /* --------------------------------- LCD_UPCURR --------------------------------- */ #define LCD_UPCURR_LCDUPCURR_Pos 0 /*!< LCD UPCURR: LCDUPCURR Position */ #define LCD_UPCURR_LCDUPCURR_Msk (0xffffffffUL << LCD_UPCURR_LCDUPCURR_Pos) /*!< LCD UPCURR: LCDUPCURR Mask */ /* --------------------------------- LCD_LPCURR --------------------------------- */ #define LCD_LPCURR_LCDLPCURR_Pos 0 /*!< LCD LPCURR: LCDLPCURR Position */ #define LCD_LPCURR_LCDLPCURR_Msk (0xffffffffUL << LCD_LPCURR_LCDLPCURR_Pos) /*!< LCD LPCURR: LCDLPCURR Mask */ /* ----------------------------------- LCD_PAL ---------------------------------- */ #define LCD_PAL_R04_0_Pos 0 /*!< LCD PAL: R04_0 Position */ #define LCD_PAL_R04_0_Msk (0x1fUL << LCD_PAL_R04_0_Pos) /*!< LCD PAL: R04_0 Mask */ #define LCD_PAL_G04_0_Pos 5 /*!< LCD PAL: G04_0 Position */ #define LCD_PAL_G04_0_Msk (0x1fUL << LCD_PAL_G04_0_Pos) /*!< LCD PAL: G04_0 Mask */ #define LCD_PAL_B04_0_Pos 10 /*!< LCD PAL: B04_0 Position */ #define LCD_PAL_B04_0_Msk (0x1fUL << LCD_PAL_B04_0_Pos) /*!< LCD PAL: B04_0 Mask */ #define LCD_PAL_I0_Pos 15 /*!< LCD PAL: I0 Position */ #define LCD_PAL_I0_Msk (0x01UL << LCD_PAL_I0_Pos) /*!< LCD PAL: I0 Mask */ #define LCD_PAL_R14_0_Pos 16 /*!< LCD PAL: R14_0 Position */ #define LCD_PAL_R14_0_Msk (0x1fUL << LCD_PAL_R14_0_Pos) /*!< LCD PAL: R14_0 Mask */ #define LCD_PAL_G14_0_Pos 21 /*!< LCD PAL: G14_0 Position */ #define LCD_PAL_G14_0_Msk (0x1fUL << LCD_PAL_G14_0_Pos) /*!< LCD PAL: G14_0 Mask */ #define LCD_PAL_B14_0_Pos 26 /*!< LCD PAL: B14_0 Position */ #define LCD_PAL_B14_0_Msk (0x1fUL << LCD_PAL_B14_0_Pos) /*!< LCD PAL: B14_0 Mask */ #define LCD_PAL_I1_Pos 31 /*!< LCD PAL: I1 Position */ #define LCD_PAL_I1_Msk (0x01UL << LCD_PAL_I1_Pos) /*!< LCD PAL: I1 Mask */ /* -------------------------------- LCD_CRSR_IMG -------------------------------- */ #define LCD_CRSR_IMG_CRSR_IMG_Pos 0 /*!< LCD CRSR_IMG: CRSR_IMG Position */ #define LCD_CRSR_IMG_CRSR_IMG_Msk (0xffffffffUL << LCD_CRSR_IMG_CRSR_IMG_Pos) /*!< LCD CRSR_IMG: CRSR_IMG Mask */ /* -------------------------------- LCD_CRSR_CTRL ------------------------------- */ #define LCD_CRSR_CTRL_CrsrOn_Pos 0 /*!< LCD CRSR_CTRL: CrsrOn Position */ #define LCD_CRSR_CTRL_CrsrOn_Msk (0x01UL << LCD_CRSR_CTRL_CrsrOn_Pos) /*!< LCD CRSR_CTRL: CrsrOn Mask */ #define LCD_CRSR_CTRL_CRSRNUM1_0_Pos 4 /*!< LCD CRSR_CTRL: CRSRNUM1_0 Position */ #define LCD_CRSR_CTRL_CRSRNUM1_0_Msk (0x03UL << LCD_CRSR_CTRL_CRSRNUM1_0_Pos) /*!< LCD CRSR_CTRL: CRSRNUM1_0 Mask */ /* -------------------------------- LCD_CRSR_CFG -------------------------------- */ #define LCD_CRSR_CFG_CrsrSize_Pos 0 /*!< LCD CRSR_CFG: CrsrSize Position */ #define LCD_CRSR_CFG_CrsrSize_Msk (0x01UL << LCD_CRSR_CFG_CrsrSize_Pos) /*!< LCD CRSR_CFG: CrsrSize Mask */ #define LCD_CRSR_CFG_FRAMESYNC_Pos 1 /*!< LCD CRSR_CFG: FRAMESYNC Position */ #define LCD_CRSR_CFG_FRAMESYNC_Msk (0x01UL << LCD_CRSR_CFG_FRAMESYNC_Pos) /*!< LCD CRSR_CFG: FRAMESYNC Mask */ /* -------------------------------- LCD_CRSR_PAL0 ------------------------------- */ #define LCD_CRSR_PAL0_RED_Pos 0 /*!< LCD CRSR_PAL0: RED Position */ #define LCD_CRSR_PAL0_RED_Msk (0x000000ffUL << LCD_CRSR_PAL0_RED_Pos) /*!< LCD CRSR_PAL0: RED Mask */ #define LCD_CRSR_PAL0_GREEN_Pos 8 /*!< LCD CRSR_PAL0: GREEN Position */ #define LCD_CRSR_PAL0_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL0_GREEN_Pos) /*!< LCD CRSR_PAL0: GREEN Mask */ #define LCD_CRSR_PAL0_BLUE_Pos 16 /*!< LCD CRSR_PAL0: BLUE Position */ #define LCD_CRSR_PAL0_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL0_BLUE_Pos) /*!< LCD CRSR_PAL0: BLUE Mask */ /* -------------------------------- LCD_CRSR_PAL1 ------------------------------- */ #define LCD_CRSR_PAL1_RED_Pos 0 /*!< LCD CRSR_PAL1: RED Position */ #define LCD_CRSR_PAL1_RED_Msk (0x000000ffUL << LCD_CRSR_PAL1_RED_Pos) /*!< LCD CRSR_PAL1: RED Mask */ #define LCD_CRSR_PAL1_GREEN_Pos 8 /*!< LCD CRSR_PAL1: GREEN Position */ #define LCD_CRSR_PAL1_GREEN_Msk (0x000000ffUL << LCD_CRSR_PAL1_GREEN_Pos) /*!< LCD CRSR_PAL1: GREEN Mask */ #define LCD_CRSR_PAL1_BLUE_Pos 16 /*!< LCD CRSR_PAL1: BLUE Position */ #define LCD_CRSR_PAL1_BLUE_Msk (0x000000ffUL << LCD_CRSR_PAL1_BLUE_Pos) /*!< LCD CRSR_PAL1: BLUE Mask */ /* --------------------------------- LCD_CRSR_XY -------------------------------- */ #define LCD_CRSR_XY_CRSRX_Pos 0 /*!< LCD CRSR_XY: CRSRX Position */ #define LCD_CRSR_XY_CRSRX_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRX_Pos) /*!< LCD CRSR_XY: CRSRX Mask */ #define LCD_CRSR_XY_CRSRY_Pos 16 /*!< LCD CRSR_XY: CRSRY Position */ #define LCD_CRSR_XY_CRSRY_Msk (0x000003ffUL << LCD_CRSR_XY_CRSRY_Pos) /*!< LCD CRSR_XY: CRSRY Mask */ /* -------------------------------- LCD_CRSR_CLIP ------------------------------- */ #define LCD_CRSR_CLIP_CRSRCLIPX_Pos 0 /*!< LCD CRSR_CLIP: CRSRCLIPX Position */ #define LCD_CRSR_CLIP_CRSRCLIPX_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPX_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPX Mask */ #define LCD_CRSR_CLIP_CRSRCLIPY_Pos 8 /*!< LCD CRSR_CLIP: CRSRCLIPY Position */ #define LCD_CRSR_CLIP_CRSRCLIPY_Msk (0x3fUL << LCD_CRSR_CLIP_CRSRCLIPY_Pos) /*!< LCD CRSR_CLIP: CRSRCLIPY Mask */ /* ------------------------------- LCD_CRSR_INTMSK ------------------------------ */ #define LCD_CRSR_INTMSK_CRSRIM_Pos 0 /*!< LCD CRSR_INTMSK: CRSRIM Position */ #define LCD_CRSR_INTMSK_CRSRIM_Msk (0x01UL << LCD_CRSR_INTMSK_CRSRIM_Pos) /*!< LCD CRSR_INTMSK: CRSRIM Mask */ /* ------------------------------- LCD_CRSR_INTCLR ------------------------------ */ #define LCD_CRSR_INTCLR_CRSRIC_Pos 0 /*!< LCD CRSR_INTCLR: CRSRIC Position */ #define LCD_CRSR_INTCLR_CRSRIC_Msk (0x01UL << LCD_CRSR_INTCLR_CRSRIC_Pos) /*!< LCD CRSR_INTCLR: CRSRIC Mask */ /* ------------------------------- LCD_CRSR_INTRAW ------------------------------ */ #define LCD_CRSR_INTRAW_CRSRRIS_Pos 0 /*!< LCD CRSR_INTRAW: CRSRRIS Position */ #define LCD_CRSR_INTRAW_CRSRRIS_Msk (0x01UL << LCD_CRSR_INTRAW_CRSRRIS_Pos) /*!< LCD CRSR_INTRAW: CRSRRIS Mask */ /* ------------------------------ LCD_CRSR_INTSTAT ------------------------------ */ #define LCD_CRSR_INTSTAT_CRSRMIS_Pos 0 /*!< LCD CRSR_INTSTAT: CRSRMIS Position */ #define LCD_CRSR_INTSTAT_CRSRMIS_Msk (0x01UL << LCD_CRSR_INTSTAT_CRSRMIS_Pos) /*!< LCD CRSR_INTSTAT: CRSRMIS Mask */ /* ================================================================================ */ /* ================ struct 'EEPROM' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- EEPROM_CMD --------------------------------- */ #define EEPROM_CMD_CMD_Pos 0 /*!< EEPROM CMD: CMD Position */ #define EEPROM_CMD_CMD_Msk (0x07UL << EEPROM_CMD_CMD_Pos) /*!< EEPROM CMD: CMD Mask */ /* ------------------------------- EEPROM_RWSTATE ------------------------------- */ #define EEPROM_RWSTATE_RPHASE2_Pos 0 /*!< EEPROM RWSTATE: RPHASE2 Position */ #define EEPROM_RWSTATE_RPHASE2_Msk (0x000000ffUL << EEPROM_RWSTATE_RPHASE2_Pos) /*!< EEPROM RWSTATE: RPHASE2 Mask */ #define EEPROM_RWSTATE_RPHASE1_Pos 8 /*!< EEPROM RWSTATE: RPHASE1 Position */ #define EEPROM_RWSTATE_RPHASE1_Msk (0x000000ffUL << EEPROM_RWSTATE_RPHASE1_Pos) /*!< EEPROM RWSTATE: RPHASE1 Mask */ /* ------------------------------- EEPROM_AUTOPROG ------------------------------ */ #define EEPROM_AUTOPROG_AUTOPROG_Pos 0 /*!< EEPROM AUTOPROG: AUTOPROG Position */ #define EEPROM_AUTOPROG_AUTOPROG_Msk (0x03UL << EEPROM_AUTOPROG_AUTOPROG_Pos) /*!< EEPROM AUTOPROG: AUTOPROG Mask */ /* -------------------------------- EEPROM_WSTATE ------------------------------- */ #define EEPROM_WSTATE_PHASE3_Pos 0 /*!< EEPROM WSTATE: PHASE3 Position */ #define EEPROM_WSTATE_PHASE3_Msk (0x000000ffUL << EEPROM_WSTATE_PHASE3_Pos) /*!< EEPROM WSTATE: PHASE3 Mask */ #define EEPROM_WSTATE_PHASE2_Pos 8 /*!< EEPROM WSTATE: PHASE2 Position */ #define EEPROM_WSTATE_PHASE2_Msk (0x000000ffUL << EEPROM_WSTATE_PHASE2_Pos) /*!< EEPROM WSTATE: PHASE2 Mask */ #define EEPROM_WSTATE_PHASE1_Pos 16 /*!< EEPROM WSTATE: PHASE1 Position */ #define EEPROM_WSTATE_PHASE1_Msk (0x000000ffUL << EEPROM_WSTATE_PHASE1_Pos) /*!< EEPROM WSTATE: PHASE1 Mask */ #define EEPROM_WSTATE_LCK_PARWEP_Pos 31 /*!< EEPROM WSTATE: LCK_PARWEP Position */ #define EEPROM_WSTATE_LCK_PARWEP_Msk (0x01UL << EEPROM_WSTATE_LCK_PARWEP_Pos) /*!< EEPROM WSTATE: LCK_PARWEP Mask */ /* -------------------------------- EEPROM_CLKDIV ------------------------------- */ #define EEPROM_CLKDIV_CLKDIV_Pos 0 /*!< EEPROM CLKDIV: CLKDIV Position */ #define EEPROM_CLKDIV_CLKDIV_Msk (0x0000ffffUL << EEPROM_CLKDIV_CLKDIV_Pos) /*!< EEPROM CLKDIV: CLKDIV Mask */ /* -------------------------------- EEPROM_PWRDWN ------------------------------- */ #define EEPROM_PWRDWN_PWRDWN_Pos 0 /*!< EEPROM PWRDWN: PWRDWN Position */ #define EEPROM_PWRDWN_PWRDWN_Msk (0x01UL << EEPROM_PWRDWN_PWRDWN_Pos) /*!< EEPROM PWRDWN: PWRDWN Mask */ /* ------------------------------- EEPROM_INTENCLR ------------------------------ */ #define EEPROM_INTENCLR_PROG_CLR_EN_Pos 2 /*!< EEPROM INTENCLR: PROG_CLR_EN Position */ #define EEPROM_INTENCLR_PROG_CLR_EN_Msk (0x01UL << EEPROM_INTENCLR_PROG_CLR_EN_Pos) /*!< EEPROM INTENCLR: PROG_CLR_EN Mask */ /* ------------------------------- EEPROM_INTENSET ------------------------------ */ #define EEPROM_INTENSET_PROG_SET_EN_Pos 2 /*!< EEPROM INTENSET: PROG_SET_EN Position */ #define EEPROM_INTENSET_PROG_SET_EN_Msk (0x01UL << EEPROM_INTENSET_PROG_SET_EN_Pos) /*!< EEPROM INTENSET: PROG_SET_EN Mask */ /* ------------------------------- EEPROM_INTSTAT ------------------------------- */ #define EEPROM_INTSTAT_END_OF_PROG_Pos 2 /*!< EEPROM INTSTAT: END_OF_PROG Position */ #define EEPROM_INTSTAT_END_OF_PROG_Msk (0x01UL << EEPROM_INTSTAT_END_OF_PROG_Pos) /*!< EEPROM INTSTAT: END_OF_PROG Mask */ /* -------------------------------- EEPROM_INTEN -------------------------------- */ #define EEPROM_INTEN_EE_PROG_DONE_Pos 2 /*!< EEPROM INTEN: EE_PROG_DONE Position */ #define EEPROM_INTEN_EE_PROG_DONE_Msk (0x01UL << EEPROM_INTEN_EE_PROG_DONE_Pos) /*!< EEPROM INTEN: EE_PROG_DONE Mask */ /* ------------------------------ EEPROM_INTSTATCLR ----------------------------- */ #define EEPROM_INTSTATCLR_PROG_CLR_ST_Pos 2 /*!< EEPROM INTSTATCLR: PROG_CLR_ST Position */ #define EEPROM_INTSTATCLR_PROG_CLR_ST_Msk (0x01UL << EEPROM_INTSTATCLR_PROG_CLR_ST_Pos) /*!< EEPROM INTSTATCLR: PROG_CLR_ST Mask */ /* ================================================================================ */ /* ================ struct 'ETHERNET' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------- ETHERNET_MAC_CONFIG ---------------------------- */ #define ETHERNET_MAC_CONFIG_RE_Pos 2 /*!< ETHERNET MAC_CONFIG: RE Position */ #define ETHERNET_MAC_CONFIG_RE_Msk (0x01UL << ETHERNET_MAC_CONFIG_RE_Pos) /*!< ETHERNET MAC_CONFIG: RE Mask */ #define ETHERNET_MAC_CONFIG_TE_Pos 3 /*!< ETHERNET MAC_CONFIG: TE Position */ #define ETHERNET_MAC_CONFIG_TE_Msk (0x01UL << ETHERNET_MAC_CONFIG_TE_Pos) /*!< ETHERNET MAC_CONFIG: TE Mask */ #define ETHERNET_MAC_CONFIG_DF_Pos 4 /*!< ETHERNET MAC_CONFIG: DF Position */ #define ETHERNET_MAC_CONFIG_DF_Msk (0x01UL << ETHERNET_MAC_CONFIG_DF_Pos) /*!< ETHERNET MAC_CONFIG: DF Mask */ #define ETHERNET_MAC_CONFIG_BL_Pos 5 /*!< ETHERNET MAC_CONFIG: BL Position */ #define ETHERNET_MAC_CONFIG_BL_Msk (0x03UL << ETHERNET_MAC_CONFIG_BL_Pos) /*!< ETHERNET MAC_CONFIG: BL Mask */ #define ETHERNET_MAC_CONFIG_ACS_Pos 7 /*!< ETHERNET MAC_CONFIG: ACS Position */ #define ETHERNET_MAC_CONFIG_ACS_Msk (0x01UL << ETHERNET_MAC_CONFIG_ACS_Pos) /*!< ETHERNET MAC_CONFIG: ACS Mask */ #define ETHERNET_MAC_CONFIG_DR_Pos 9 /*!< ETHERNET MAC_CONFIG: DR Position */ #define ETHERNET_MAC_CONFIG_DR_Msk (0x01UL << ETHERNET_MAC_CONFIG_DR_Pos) /*!< ETHERNET MAC_CONFIG: DR Mask */ #define ETHERNET_MAC_CONFIG_DM_Pos 11 /*!< ETHERNET MAC_CONFIG: DM Position */ #define ETHERNET_MAC_CONFIG_DM_Msk (0x01UL << ETHERNET_MAC_CONFIG_DM_Pos) /*!< ETHERNET MAC_CONFIG: DM Mask */ #define ETHERNET_MAC_CONFIG_LM_Pos 12 /*!< ETHERNET MAC_CONFIG: LM Position */ #define ETHERNET_MAC_CONFIG_LM_Msk (0x01UL << ETHERNET_MAC_CONFIG_LM_Pos) /*!< ETHERNET MAC_CONFIG: LM Mask */ #define ETHERNET_MAC_CONFIG_DO_Pos 13 /*!< ETHERNET MAC_CONFIG: DO Position */ #define ETHERNET_MAC_CONFIG_DO_Msk (0x01UL << ETHERNET_MAC_CONFIG_DO_Pos) /*!< ETHERNET MAC_CONFIG: DO Mask */ #define ETHERNET_MAC_CONFIG_FES_Pos 14 /*!< ETHERNET MAC_CONFIG: FES Position */ #define ETHERNET_MAC_CONFIG_FES_Msk (0x01UL << ETHERNET_MAC_CONFIG_FES_Pos) /*!< ETHERNET MAC_CONFIG: FES Mask */ #define ETHERNET_MAC_CONFIG_PS_Pos 15 /*!< ETHERNET MAC_CONFIG: PS Position */ #define ETHERNET_MAC_CONFIG_PS_Msk (0x01UL << ETHERNET_MAC_CONFIG_PS_Pos) /*!< ETHERNET MAC_CONFIG: PS Mask */ #define ETHERNET_MAC_CONFIG_DCRS_Pos 16 /*!< ETHERNET MAC_CONFIG: DCRS Position */ #define ETHERNET_MAC_CONFIG_DCRS_Msk (0x01UL << ETHERNET_MAC_CONFIG_DCRS_Pos) /*!< ETHERNET MAC_CONFIG: DCRS Mask */ #define ETHERNET_MAC_CONFIG_IFG_Pos 17 /*!< ETHERNET MAC_CONFIG: IFG Position */ #define ETHERNET_MAC_CONFIG_IFG_Msk (0x07UL << ETHERNET_MAC_CONFIG_IFG_Pos) /*!< ETHERNET MAC_CONFIG: IFG Mask */ #define ETHERNET_MAC_CONFIG_JE_Pos 20 /*!< ETHERNET MAC_CONFIG: JE Position */ #define ETHERNET_MAC_CONFIG_JE_Msk (0x01UL << ETHERNET_MAC_CONFIG_JE_Pos) /*!< ETHERNET MAC_CONFIG: JE Mask */ #define ETHERNET_MAC_CONFIG_JD_Pos 22 /*!< ETHERNET MAC_CONFIG: JD Position */ #define ETHERNET_MAC_CONFIG_JD_Msk (0x01UL << ETHERNET_MAC_CONFIG_JD_Pos) /*!< ETHERNET MAC_CONFIG: JD Mask */ #define ETHERNET_MAC_CONFIG_WD_Pos 23 /*!< ETHERNET MAC_CONFIG: WD Position */ #define ETHERNET_MAC_CONFIG_WD_Msk (0x01UL << ETHERNET_MAC_CONFIG_WD_Pos) /*!< ETHERNET MAC_CONFIG: WD Mask */ /* -------------------------- ETHERNET_MAC_FRAME_FILTER ------------------------- */ #define ETHERNET_MAC_FRAME_FILTER_PR_Pos 0 /*!< ETHERNET MAC_FRAME_FILTER: PR Position */ #define ETHERNET_MAC_FRAME_FILTER_PR_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PR_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PR Mask */ #define ETHERNET_MAC_FRAME_FILTER_HUC_Pos 1 /*!< ETHERNET MAC_FRAME_FILTER: HUC Position */ #define ETHERNET_MAC_FRAME_FILTER_HUC_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_HUC_Pos) /*!< ETHERNET MAC_FRAME_FILTER: HUC Mask */ #define ETHERNET_MAC_FRAME_FILTER_HMC_Pos 2 /*!< ETHERNET MAC_FRAME_FILTER: HMC Position */ #define ETHERNET_MAC_FRAME_FILTER_HMC_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_HMC_Pos) /*!< ETHERNET MAC_FRAME_FILTER: HMC Mask */ #define ETHERNET_MAC_FRAME_FILTER_DAIF_Pos 3 /*!< ETHERNET MAC_FRAME_FILTER: DAIF Position */ #define ETHERNET_MAC_FRAME_FILTER_DAIF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DAIF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DAIF Mask */ #define ETHERNET_MAC_FRAME_FILTER_PM_Pos 4 /*!< ETHERNET MAC_FRAME_FILTER: PM Position */ #define ETHERNET_MAC_FRAME_FILTER_PM_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_PM_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PM Mask */ #define ETHERNET_MAC_FRAME_FILTER_DBF_Pos 5 /*!< ETHERNET MAC_FRAME_FILTER: DBF Position */ #define ETHERNET_MAC_FRAME_FILTER_DBF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_DBF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: DBF Mask */ #define ETHERNET_MAC_FRAME_FILTER_PCF_Pos 6 /*!< ETHERNET MAC_FRAME_FILTER: PCF Position */ #define ETHERNET_MAC_FRAME_FILTER_PCF_Msk (0x03UL << ETHERNET_MAC_FRAME_FILTER_PCF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: PCF Mask */ #define ETHERNET_MAC_FRAME_FILTER_HPF_Pos 10 /*!< ETHERNET MAC_FRAME_FILTER: HPF Position */ #define ETHERNET_MAC_FRAME_FILTER_HPF_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_HPF_Pos) /*!< ETHERNET MAC_FRAME_FILTER: HPF Mask */ #define ETHERNET_MAC_FRAME_FILTER_RA_Pos 31 /*!< ETHERNET MAC_FRAME_FILTER: RA Position */ #define ETHERNET_MAC_FRAME_FILTER_RA_Msk (0x01UL << ETHERNET_MAC_FRAME_FILTER_RA_Pos) /*!< ETHERNET MAC_FRAME_FILTER: RA Mask */ /* ------------------------- ETHERNET_MAC_HASHTABLE_HIGH ------------------------ */ #define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos 0 /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Position */ #define ETHERNET_MAC_HASHTABLE_HIGH_HTH_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_HIGH_HTH_Pos) /*!< ETHERNET MAC_HASHTABLE_HIGH: HTH Mask */ /* ------------------------- ETHERNET_MAC_HASHTABLE_LOW ------------------------- */ #define ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos 0 /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Position */ #define ETHERNET_MAC_HASHTABLE_LOW_HTL_Msk (0xffffffffUL << ETHERNET_MAC_HASHTABLE_LOW_HTL_Pos) /*!< ETHERNET MAC_HASHTABLE_LOW: HTL Mask */ /* ---------------------------- ETHERNET_MAC_MII_ADDR --------------------------- */ #define ETHERNET_MAC_MII_ADDR_GB_Pos 0 /*!< ETHERNET MAC_MII_ADDR: GB Position */ #define ETHERNET_MAC_MII_ADDR_GB_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_GB_Pos) /*!< ETHERNET MAC_MII_ADDR: GB Mask */ #define ETHERNET_MAC_MII_ADDR_W_Pos 1 /*!< ETHERNET MAC_MII_ADDR: W Position */ #define ETHERNET_MAC_MII_ADDR_W_Msk (0x01UL << ETHERNET_MAC_MII_ADDR_W_Pos) /*!< ETHERNET MAC_MII_ADDR: W Mask */ #define ETHERNET_MAC_MII_ADDR_CR_Pos 2 /*!< ETHERNET MAC_MII_ADDR: CR Position */ #define ETHERNET_MAC_MII_ADDR_CR_Msk (0x0fUL << ETHERNET_MAC_MII_ADDR_CR_Pos) /*!< ETHERNET MAC_MII_ADDR: CR Mask */ #define ETHERNET_MAC_MII_ADDR_GR_Pos 6 /*!< ETHERNET MAC_MII_ADDR: GR Position */ #define ETHERNET_MAC_MII_ADDR_GR_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_GR_Pos) /*!< ETHERNET MAC_MII_ADDR: GR Mask */ #define ETHERNET_MAC_MII_ADDR_PA_Pos 11 /*!< ETHERNET MAC_MII_ADDR: PA Position */ #define ETHERNET_MAC_MII_ADDR_PA_Msk (0x1fUL << ETHERNET_MAC_MII_ADDR_PA_Pos) /*!< ETHERNET MAC_MII_ADDR: PA Mask */ /* ---------------------------- ETHERNET_MAC_MII_DATA --------------------------- */ #define ETHERNET_MAC_MII_DATA_GD_Pos 0 /*!< ETHERNET MAC_MII_DATA: GD Position */ #define ETHERNET_MAC_MII_DATA_GD_Msk (0x0000ffffUL << ETHERNET_MAC_MII_DATA_GD_Pos) /*!< ETHERNET MAC_MII_DATA: GD Mask */ /* --------------------------- ETHERNET_MAC_FLOW_CTRL --------------------------- */ #define ETHERNET_MAC_FLOW_CTRL_FCB_Pos 0 /*!< ETHERNET MAC_FLOW_CTRL: FCB Position */ #define ETHERNET_MAC_FLOW_CTRL_FCB_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_FCB_Pos) /*!< ETHERNET MAC_FLOW_CTRL: FCB Mask */ #define ETHERNET_MAC_FLOW_CTRL_TFE_Pos 1 /*!< ETHERNET MAC_FLOW_CTRL: TFE Position */ #define ETHERNET_MAC_FLOW_CTRL_TFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_TFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: TFE Mask */ #define ETHERNET_MAC_FLOW_CTRL_RFE_Pos 2 /*!< ETHERNET MAC_FLOW_CTRL: RFE Position */ #define ETHERNET_MAC_FLOW_CTRL_RFE_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_RFE_Pos) /*!< ETHERNET MAC_FLOW_CTRL: RFE Mask */ #define ETHERNET_MAC_FLOW_CTRL_UP_Pos 3 /*!< ETHERNET MAC_FLOW_CTRL: UP Position */ #define ETHERNET_MAC_FLOW_CTRL_UP_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_UP_Pos) /*!< ETHERNET MAC_FLOW_CTRL: UP Mask */ #define ETHERNET_MAC_FLOW_CTRL_PLT_Pos 4 /*!< ETHERNET MAC_FLOW_CTRL: PLT Position */ #define ETHERNET_MAC_FLOW_CTRL_PLT_Msk (0x03UL << ETHERNET_MAC_FLOW_CTRL_PLT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PLT Mask */ #define ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos 7 /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Position */ #define ETHERNET_MAC_FLOW_CTRL_DZPQ_Msk (0x01UL << ETHERNET_MAC_FLOW_CTRL_DZPQ_Pos) /*!< ETHERNET MAC_FLOW_CTRL: DZPQ Mask */ #define ETHERNET_MAC_FLOW_CTRL_PT_Pos 16 /*!< ETHERNET MAC_FLOW_CTRL: PT Position */ #define ETHERNET_MAC_FLOW_CTRL_PT_Msk (0x0000ffffUL << ETHERNET_MAC_FLOW_CTRL_PT_Pos) /*!< ETHERNET MAC_FLOW_CTRL: PT Mask */ /* ---------------------------- ETHERNET_MAC_VLAN_TAG --------------------------- */ #define ETHERNET_MAC_VLAN_TAG_VL_Pos 0 /*!< ETHERNET MAC_VLAN_TAG: VL Position */ #define ETHERNET_MAC_VLAN_TAG_VL_Msk (0x0000ffffUL << ETHERNET_MAC_VLAN_TAG_VL_Pos) /*!< ETHERNET MAC_VLAN_TAG: VL Mask */ #define ETHERNET_MAC_VLAN_TAG_ETV_Pos 16 /*!< ETHERNET MAC_VLAN_TAG: ETV Position */ #define ETHERNET_MAC_VLAN_TAG_ETV_Msk (0x01UL << ETHERNET_MAC_VLAN_TAG_ETV_Pos) /*!< ETHERNET MAC_VLAN_TAG: ETV Mask */ /* ----------------------------- ETHERNET_MAC_DEBUG ----------------------------- */ #define ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos 0 /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Position */ #define ETHERNET_MAC_DEBUG_RXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXIDLESTAT Mask */ #define ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos 1 /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Position */ #define ETHERNET_MAC_DEBUG_FIFOSTAT0_Msk (0x03UL << ETHERNET_MAC_DEBUG_FIFOSTAT0_Pos) /*!< ETHERNET MAC_DEBUG: FIFOSTAT0 Mask */ #define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos 4 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Position */ #define ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT1 Mask */ #define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos 5 /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Position */ #define ETHERNET_MAC_DEBUG_RXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOSTAT Mask */ #define ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos 8 /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Position */ #define ETHERNET_MAC_DEBUG_RXFIFOLVL_Msk (0x03UL << ETHERNET_MAC_DEBUG_RXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: RXFIFOLVL Mask */ #define ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos 16 /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Position */ #define ETHERNET_MAC_DEBUG_TXIDLESTAT_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXIDLESTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXIDLESTAT Mask */ #define ETHERNET_MAC_DEBUG_TXSTAT_Pos 17 /*!< ETHERNET MAC_DEBUG: TXSTAT Position */ #define ETHERNET_MAC_DEBUG_TXSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXSTAT Mask */ #define ETHERNET_MAC_DEBUG_PAUSE_Pos 19 /*!< ETHERNET MAC_DEBUG: PAUSE Position */ #define ETHERNET_MAC_DEBUG_PAUSE_Msk (0x01UL << ETHERNET_MAC_DEBUG_PAUSE_Pos) /*!< ETHERNET MAC_DEBUG: PAUSE Mask */ #define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos 20 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Position */ #define ETHERNET_MAC_DEBUG_TXFIFOSTAT_Msk (0x03UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT Mask */ #define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos 22 /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Position */ #define ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOSTAT1_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOSTAT1 Mask */ #define ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos 24 /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Position */ #define ETHERNET_MAC_DEBUG_TXFIFOLVL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOLVL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOLVL Mask */ #define ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos 25 /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Position */ #define ETHERNET_MAC_DEBUG_TXFIFOFULL_Msk (0x01UL << ETHERNET_MAC_DEBUG_TXFIFOFULL_Pos) /*!< ETHERNET MAC_DEBUG: TXFIFOFULL Mask */ /* -------------------------- ETHERNET_MAC_RWAKE_FRFLT -------------------------- */ #define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos 0 /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Position */ #define ETHERNET_MAC_RWAKE_FRFLT_ADDR_Msk (0xffffffffUL << ETHERNET_MAC_RWAKE_FRFLT_ADDR_Pos) /*!< ETHERNET MAC_RWAKE_FRFLT: ADDR Mask */ /* ------------------------- ETHERNET_MAC_PMT_CTRL_STAT ------------------------- */ #define ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos 0 /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Position */ #define ETHERNET_MAC_PMT_CTRL_STAT_PD_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_PD_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: PD Mask */ #define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos 1 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Position */ #define ETHERNET_MAC_PMT_CTRL_STAT_MPE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPE Mask */ #define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos 2 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Position */ #define ETHERNET_MAC_PMT_CTRL_STAT_WFE_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFE_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFE Mask */ #define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos 5 /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Position */ #define ETHERNET_MAC_PMT_CTRL_STAT_MPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_MPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: MPR Mask */ #define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos 6 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Position */ #define ETHERNET_MAC_PMT_CTRL_STAT_WFR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFR Mask */ #define ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos 9 /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Position */ #define ETHERNET_MAC_PMT_CTRL_STAT_GU_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_GU_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: GU Mask */ #define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos 31 /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Position */ #define ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Msk (0x01UL << ETHERNET_MAC_PMT_CTRL_STAT_WFFRPR_Pos) /*!< ETHERNET MAC_PMT_CTRL_STAT: WFFRPR Mask */ /* ------------------------------ ETHERNET_MAC_INTR ----------------------------- */ #define ETHERNET_MAC_INTR_PMT_Pos 3 /*!< ETHERNET MAC_INTR: PMT Position */ #define ETHERNET_MAC_INTR_PMT_Msk (0x01UL << ETHERNET_MAC_INTR_PMT_Pos) /*!< ETHERNET MAC_INTR: PMT Mask */ #define ETHERNET_MAC_INTR_TS_Pos 9 /*!< ETHERNET MAC_INTR: TS Position */ #define ETHERNET_MAC_INTR_TS_Msk (0x01UL << ETHERNET_MAC_INTR_TS_Pos) /*!< ETHERNET MAC_INTR: TS Mask */ /* --------------------------- ETHERNET_MAC_INTR_MASK --------------------------- */ #define ETHERNET_MAC_INTR_MASK_PMTIM_Pos 3 /*!< ETHERNET MAC_INTR_MASK: PMTIM Position */ #define ETHERNET_MAC_INTR_MASK_PMTIM_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_PMTIM_Pos) /*!< ETHERNET MAC_INTR_MASK: PMTIM Mask */ #define ETHERNET_MAC_INTR_MASK_TSIM_Pos 9 /*!< ETHERNET MAC_INTR_MASK: TSIM Position */ #define ETHERNET_MAC_INTR_MASK_TSIM_Msk (0x01UL << ETHERNET_MAC_INTR_MASK_TSIM_Pos) /*!< ETHERNET MAC_INTR_MASK: TSIM Mask */ /* --------------------------- ETHERNET_MAC_ADDR0_HIGH -------------------------- */ #define ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos 0 /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Position */ #define ETHERNET_MAC_ADDR0_HIGH_A47_32_Msk (0x0000ffffUL << ETHERNET_MAC_ADDR0_HIGH_A47_32_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: A47_32 Mask */ #define ETHERNET_MAC_ADDR0_HIGH_MO_Pos 31 /*!< ETHERNET MAC_ADDR0_HIGH: MO Position */ #define ETHERNET_MAC_ADDR0_HIGH_MO_Msk (0x01UL << ETHERNET_MAC_ADDR0_HIGH_MO_Pos) /*!< ETHERNET MAC_ADDR0_HIGH: MO Mask */ /* --------------------------- ETHERNET_MAC_ADDR0_LOW --------------------------- */ #define ETHERNET_MAC_ADDR0_LOW_A31_0_Pos 0 /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Position */ #define ETHERNET_MAC_ADDR0_LOW_A31_0_Msk (0xffffffffUL << ETHERNET_MAC_ADDR0_LOW_A31_0_Pos) /*!< ETHERNET MAC_ADDR0_LOW: A31_0 Mask */ /* -------------------------- ETHERNET_MAC_TIMESTP_CTRL ------------------------- */ #define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos 0 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENA Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos 1 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCFUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCFUPDT Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos 2 /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSINIT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSINIT Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos 3 /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSUPDT_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSUPDT Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos 4 /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSTRIG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSTRIG Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos 5 /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSADDREG_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSADDREG Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos 8 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENALL_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSENALL Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos 9 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSCTRLSSR_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCTRLSSR Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos 10 /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSVER2ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSVER2ENA Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos 11 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPENA Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos 12 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV6ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV6ENA Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos 13 /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSIPV4ENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSIPV4ENA Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos 14 /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSEVNTENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSEVNTENA Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos 15 /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSMSTRENA_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSMSTRENA Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos 16 /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Msk (0x03UL << ETHERNET_MAC_TIMESTP_CTRL_TSCLKTYPE_Pos) /*!< ETHERNET MAC_TIMESTP_CTRL: TSCLKTYPE Mask */ #define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos 18 /*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Position */ #define ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Msk (0x01UL << ETHERNET_MAC_TIMESTP_CTRL_TSENMACADDR_Pos)/*!< ETHERNET MAC_TIMESTP_CTRL: TSENMACADDR Mask */ /* --------------------------- ETHERNET_SUBSECOND_INCR -------------------------- */ #define ETHERNET_SUBSECOND_INCR_SSINC_Pos 0 /*!< ETHERNET SUBSECOND_INCR: SSINC Position */ #define ETHERNET_SUBSECOND_INCR_SSINC_Msk (0x000000ffUL << ETHERNET_SUBSECOND_INCR_SSINC_Pos) /*!< ETHERNET SUBSECOND_INCR: SSINC Mask */ /* ------------------------------ ETHERNET_SECONDS ------------------------------ */ #define ETHERNET_SECONDS_TSS_Pos 0 /*!< ETHERNET SECONDS: TSS Position */ #define ETHERNET_SECONDS_TSS_Msk (0xffffffffUL << ETHERNET_SECONDS_TSS_Pos) /*!< ETHERNET SECONDS: TSS Mask */ /* ---------------------------- ETHERNET_NANOSECONDS ---------------------------- */ #define ETHERNET_NANOSECONDS_TSSS_Pos 0 /*!< ETHERNET NANOSECONDS: TSSS Position */ #define ETHERNET_NANOSECONDS_TSSS_Msk (0x7fffffffUL << ETHERNET_NANOSECONDS_TSSS_Pos) /*!< ETHERNET NANOSECONDS: TSSS Mask */ #define ETHERNET_NANOSECONDS_PSNT_Pos 31 /*!< ETHERNET NANOSECONDS: PSNT Position */ #define ETHERNET_NANOSECONDS_PSNT_Msk (0x01UL << ETHERNET_NANOSECONDS_PSNT_Pos) /*!< ETHERNET NANOSECONDS: PSNT Mask */ /* --------------------------- ETHERNET_SECONDSUPDATE --------------------------- */ #define ETHERNET_SECONDSUPDATE_TSS_Pos 0 /*!< ETHERNET SECONDSUPDATE: TSS Position */ #define ETHERNET_SECONDSUPDATE_TSS_Msk (0xffffffffUL << ETHERNET_SECONDSUPDATE_TSS_Pos) /*!< ETHERNET SECONDSUPDATE: TSS Mask */ /* ------------------------- ETHERNET_NANOSECONDSUPDATE ------------------------- */ #define ETHERNET_NANOSECONDSUPDATE_TSSS_Pos 0 /*!< ETHERNET NANOSECONDSUPDATE: TSSS Position */ #define ETHERNET_NANOSECONDSUPDATE_TSSS_Msk (0x7fffffffUL << ETHERNET_NANOSECONDSUPDATE_TSSS_Pos) /*!< ETHERNET NANOSECONDSUPDATE: TSSS Mask */ #define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos 31 /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Position */ #define ETHERNET_NANOSECONDSUPDATE_ADDSUB_Msk (0x01UL << ETHERNET_NANOSECONDSUPDATE_ADDSUB_Pos) /*!< ETHERNET NANOSECONDSUPDATE: ADDSUB Mask */ /* ------------------------------- ETHERNET_ADDEND ------------------------------ */ #define ETHERNET_ADDEND_TSAR_Pos 0 /*!< ETHERNET ADDEND: TSAR Position */ #define ETHERNET_ADDEND_TSAR_Msk (0xffffffffUL << ETHERNET_ADDEND_TSAR_Pos) /*!< ETHERNET ADDEND: TSAR Mask */ /* --------------------------- ETHERNET_TARGETSECONDS --------------------------- */ #define ETHERNET_TARGETSECONDS_TSTR_Pos 0 /*!< ETHERNET TARGETSECONDS: TSTR Position */ #define ETHERNET_TARGETSECONDS_TSTR_Msk (0xffffffffUL << ETHERNET_TARGETSECONDS_TSTR_Pos) /*!< ETHERNET TARGETSECONDS: TSTR Mask */ /* ------------------------- ETHERNET_TARGETNANOSECONDS ------------------------- */ #define ETHERNET_TARGETNANOSECONDS_TSTR_Pos 0 /*!< ETHERNET TARGETNANOSECONDS: TSTR Position */ #define ETHERNET_TARGETNANOSECONDS_TSTR_Msk (0x7fffffffUL << ETHERNET_TARGETNANOSECONDS_TSTR_Pos) /*!< ETHERNET TARGETNANOSECONDS: TSTR Mask */ /* ------------------------------ ETHERNET_HIGHWORD ----------------------------- */ #define ETHERNET_HIGHWORD_TSHWR_Pos 0 /*!< ETHERNET HIGHWORD: TSHWR Position */ #define ETHERNET_HIGHWORD_TSHWR_Msk (0x0000ffffUL << ETHERNET_HIGHWORD_TSHWR_Pos) /*!< ETHERNET HIGHWORD: TSHWR Mask */ /* --------------------------- ETHERNET_TIMESTAMPSTAT --------------------------- */ #define ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos 0 /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Position */ #define ETHERNET_TIMESTAMPSTAT_TSSOVF_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_TSSOVF_Pos) /*!< ETHERNET TIMESTAMPSTAT: TSSOVF Mask */ #define ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos 1 /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Position */ #define ETHERNET_TIMESTAMPSTAT_TSTARGT_Msk (0x01UL << ETHERNET_TIMESTAMPSTAT_TSTARGT_Pos) /*!< ETHERNET TIMESTAMPSTAT: TSTARGT Mask */ /* ---------------------------- ETHERNET_DMA_BUS_MODE --------------------------- */ #define ETHERNET_DMA_BUS_MODE_SWR_Pos 0 /*!< ETHERNET DMA_BUS_MODE: SWR Position */ #define ETHERNET_DMA_BUS_MODE_SWR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_SWR_Pos) /*!< ETHERNET DMA_BUS_MODE: SWR Mask */ #define ETHERNET_DMA_BUS_MODE_DA_Pos 1 /*!< ETHERNET DMA_BUS_MODE: DA Position */ #define ETHERNET_DMA_BUS_MODE_DA_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_DA_Pos) /*!< ETHERNET DMA_BUS_MODE: DA Mask */ #define ETHERNET_DMA_BUS_MODE_DSL_Pos 2 /*!< ETHERNET DMA_BUS_MODE: DSL Position */ #define ETHERNET_DMA_BUS_MODE_DSL_Msk (0x1fUL << ETHERNET_DMA_BUS_MODE_DSL_Pos) /*!< ETHERNET DMA_BUS_MODE: DSL Mask */ #define ETHERNET_DMA_BUS_MODE_ATDS_Pos 7 /*!< ETHERNET DMA_BUS_MODE: ATDS Position */ #define ETHERNET_DMA_BUS_MODE_ATDS_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_ATDS_Pos) /*!< ETHERNET DMA_BUS_MODE: ATDS Mask */ #define ETHERNET_DMA_BUS_MODE_PBL_Pos 8 /*!< ETHERNET DMA_BUS_MODE: PBL Position */ #define ETHERNET_DMA_BUS_MODE_PBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_PBL_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL Mask */ #define ETHERNET_DMA_BUS_MODE_PR_Pos 14 /*!< ETHERNET DMA_BUS_MODE: PR Position */ #define ETHERNET_DMA_BUS_MODE_PR_Msk (0x03UL << ETHERNET_DMA_BUS_MODE_PR_Pos) /*!< ETHERNET DMA_BUS_MODE: PR Mask */ #define ETHERNET_DMA_BUS_MODE_FB_Pos 16 /*!< ETHERNET DMA_BUS_MODE: FB Position */ #define ETHERNET_DMA_BUS_MODE_FB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_FB_Pos) /*!< ETHERNET DMA_BUS_MODE: FB Mask */ #define ETHERNET_DMA_BUS_MODE_RPBL_Pos 17 /*!< ETHERNET DMA_BUS_MODE: RPBL Position */ #define ETHERNET_DMA_BUS_MODE_RPBL_Msk (0x3fUL << ETHERNET_DMA_BUS_MODE_RPBL_Pos) /*!< ETHERNET DMA_BUS_MODE: RPBL Mask */ #define ETHERNET_DMA_BUS_MODE_USP_Pos 23 /*!< ETHERNET DMA_BUS_MODE: USP Position */ #define ETHERNET_DMA_BUS_MODE_USP_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_USP_Pos) /*!< ETHERNET DMA_BUS_MODE: USP Mask */ #define ETHERNET_DMA_BUS_MODE_PBL8X_Pos 24 /*!< ETHERNET DMA_BUS_MODE: PBL8X Position */ #define ETHERNET_DMA_BUS_MODE_PBL8X_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_PBL8X_Pos) /*!< ETHERNET DMA_BUS_MODE: PBL8X Mask */ #define ETHERNET_DMA_BUS_MODE_AAL_Pos 25 /*!< ETHERNET DMA_BUS_MODE: AAL Position */ #define ETHERNET_DMA_BUS_MODE_AAL_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_AAL_Pos) /*!< ETHERNET DMA_BUS_MODE: AAL Mask */ #define ETHERNET_DMA_BUS_MODE_MB_Pos 26 /*!< ETHERNET DMA_BUS_MODE: MB Position */ #define ETHERNET_DMA_BUS_MODE_MB_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_MB_Pos) /*!< ETHERNET DMA_BUS_MODE: MB Mask */ #define ETHERNET_DMA_BUS_MODE_TXPR_Pos 27 /*!< ETHERNET DMA_BUS_MODE: TXPR Position */ #define ETHERNET_DMA_BUS_MODE_TXPR_Msk (0x01UL << ETHERNET_DMA_BUS_MODE_TXPR_Pos) /*!< ETHERNET DMA_BUS_MODE: TXPR Mask */ /* ----------------------- ETHERNET_DMA_TRANS_POLL_DEMAND ----------------------- */ #define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos 0 /*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Position */ #define ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_POLL_DEMAND_TPD_Pos)/*!< ETHERNET DMA_TRANS_POLL_DEMAND: TPD Mask */ /* ------------------------ ETHERNET_DMA_REC_POLL_DEMAND ------------------------ */ #define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos 0 /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Position */ #define ETHERNET_DMA_REC_POLL_DEMAND_RPD_Msk (0xffffffffUL << ETHERNET_DMA_REC_POLL_DEMAND_RPD_Pos) /*!< ETHERNET DMA_REC_POLL_DEMAND: RPD Mask */ /* -------------------------- ETHERNET_DMA_REC_DES_ADDR ------------------------- */ #define ETHERNET_DMA_REC_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_REC_DES_ADDR: SRL Position */ #define ETHERNET_DMA_REC_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_REC_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_REC_DES_ADDR: SRL Mask */ /* ------------------------- ETHERNET_DMA_TRANS_DES_ADDR ------------------------ */ #define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos 0 /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Position */ #define ETHERNET_DMA_TRANS_DES_ADDR_SRL_Msk (0xffffffffUL << ETHERNET_DMA_TRANS_DES_ADDR_SRL_Pos) /*!< ETHERNET DMA_TRANS_DES_ADDR: SRL Mask */ /* ------------------------------ ETHERNET_DMA_STAT ----------------------------- */ #define ETHERNET_DMA_STAT_TI_Pos 0 /*!< ETHERNET DMA_STAT: TI Position */ #define ETHERNET_DMA_STAT_TI_Msk (0x01UL << ETHERNET_DMA_STAT_TI_Pos) /*!< ETHERNET DMA_STAT: TI Mask */ #define ETHERNET_DMA_STAT_TPS_Pos 1 /*!< ETHERNET DMA_STAT: TPS Position */ #define ETHERNET_DMA_STAT_TPS_Msk (0x01UL << ETHERNET_DMA_STAT_TPS_Pos) /*!< ETHERNET DMA_STAT: TPS Mask */ #define ETHERNET_DMA_STAT_TU_Pos 2 /*!< ETHERNET DMA_STAT: TU Position */ #define ETHERNET_DMA_STAT_TU_Msk (0x01UL << ETHERNET_DMA_STAT_TU_Pos) /*!< ETHERNET DMA_STAT: TU Mask */ #define ETHERNET_DMA_STAT_TJT_Pos 3 /*!< ETHERNET DMA_STAT: TJT Position */ #define ETHERNET_DMA_STAT_TJT_Msk (0x01UL << ETHERNET_DMA_STAT_TJT_Pos) /*!< ETHERNET DMA_STAT: TJT Mask */ #define ETHERNET_DMA_STAT_OVF_Pos 4 /*!< ETHERNET DMA_STAT: OVF Position */ #define ETHERNET_DMA_STAT_OVF_Msk (0x01UL << ETHERNET_DMA_STAT_OVF_Pos) /*!< ETHERNET DMA_STAT: OVF Mask */ #define ETHERNET_DMA_STAT_UNF_Pos 5 /*!< ETHERNET DMA_STAT: UNF Position */ #define ETHERNET_DMA_STAT_UNF_Msk (0x01UL << ETHERNET_DMA_STAT_UNF_Pos) /*!< ETHERNET DMA_STAT: UNF Mask */ #define ETHERNET_DMA_STAT_RI_Pos 6 /*!< ETHERNET DMA_STAT: RI Position */ #define ETHERNET_DMA_STAT_RI_Msk (0x01UL << ETHERNET_DMA_STAT_RI_Pos) /*!< ETHERNET DMA_STAT: RI Mask */ #define ETHERNET_DMA_STAT_RU_Pos 7 /*!< ETHERNET DMA_STAT: RU Position */ #define ETHERNET_DMA_STAT_RU_Msk (0x01UL << ETHERNET_DMA_STAT_RU_Pos) /*!< ETHERNET DMA_STAT: RU Mask */ #define ETHERNET_DMA_STAT_RPS_Pos 8 /*!< ETHERNET DMA_STAT: RPS Position */ #define ETHERNET_DMA_STAT_RPS_Msk (0x01UL << ETHERNET_DMA_STAT_RPS_Pos) /*!< ETHERNET DMA_STAT: RPS Mask */ #define ETHERNET_DMA_STAT_RWT_Pos 9 /*!< ETHERNET DMA_STAT: RWT Position */ #define ETHERNET_DMA_STAT_RWT_Msk (0x01UL << ETHERNET_DMA_STAT_RWT_Pos) /*!< ETHERNET DMA_STAT: RWT Mask */ #define ETHERNET_DMA_STAT_ETI_Pos 10 /*!< ETHERNET DMA_STAT: ETI Position */ #define ETHERNET_DMA_STAT_ETI_Msk (0x01UL << ETHERNET_DMA_STAT_ETI_Pos) /*!< ETHERNET DMA_STAT: ETI Mask */ #define ETHERNET_DMA_STAT_FBI_Pos 13 /*!< ETHERNET DMA_STAT: FBI Position */ #define ETHERNET_DMA_STAT_FBI_Msk (0x01UL << ETHERNET_DMA_STAT_FBI_Pos) /*!< ETHERNET DMA_STAT: FBI Mask */ #define ETHERNET_DMA_STAT_ERI_Pos 14 /*!< ETHERNET DMA_STAT: ERI Position */ #define ETHERNET_DMA_STAT_ERI_Msk (0x01UL << ETHERNET_DMA_STAT_ERI_Pos) /*!< ETHERNET DMA_STAT: ERI Mask */ #define ETHERNET_DMA_STAT_AIE_Pos 15 /*!< ETHERNET DMA_STAT: AIE Position */ #define ETHERNET_DMA_STAT_AIE_Msk (0x01UL << ETHERNET_DMA_STAT_AIE_Pos) /*!< ETHERNET DMA_STAT: AIE Mask */ #define ETHERNET_DMA_STAT_NIS_Pos 16 /*!< ETHERNET DMA_STAT: NIS Position */ #define ETHERNET_DMA_STAT_NIS_Msk (0x01UL << ETHERNET_DMA_STAT_NIS_Pos) /*!< ETHERNET DMA_STAT: NIS Mask */ #define ETHERNET_DMA_STAT_RS_Pos 17 /*!< ETHERNET DMA_STAT: RS Position */ #define ETHERNET_DMA_STAT_RS_Msk (0x07UL << ETHERNET_DMA_STAT_RS_Pos) /*!< ETHERNET DMA_STAT: RS Mask */ #define ETHERNET_DMA_STAT_TS_Pos 20 /*!< ETHERNET DMA_STAT: TS Position */ #define ETHERNET_DMA_STAT_TS_Msk (0x07UL << ETHERNET_DMA_STAT_TS_Pos) /*!< ETHERNET DMA_STAT: TS Mask */ #define ETHERNET_DMA_STAT_EB1_Pos 23 /*!< ETHERNET DMA_STAT: EB1 Position */ #define ETHERNET_DMA_STAT_EB1_Msk (0x01UL << ETHERNET_DMA_STAT_EB1_Pos) /*!< ETHERNET DMA_STAT: EB1 Mask */ #define ETHERNET_DMA_STAT_EB2_Pos 24 /*!< ETHERNET DMA_STAT: EB2 Position */ #define ETHERNET_DMA_STAT_EB2_Msk (0x01UL << ETHERNET_DMA_STAT_EB2_Pos) /*!< ETHERNET DMA_STAT: EB2 Mask */ #define ETHERNET_DMA_STAT_EB3_Pos 25 /*!< ETHERNET DMA_STAT: EB3 Position */ #define ETHERNET_DMA_STAT_EB3_Msk (0x01UL << ETHERNET_DMA_STAT_EB3_Pos) /*!< ETHERNET DMA_STAT: EB3 Mask */ /* ---------------------------- ETHERNET_DMA_OP_MODE ---------------------------- */ #define ETHERNET_DMA_OP_MODE_SR_Pos 1 /*!< ETHERNET DMA_OP_MODE: SR Position */ #define ETHERNET_DMA_OP_MODE_SR_Msk (0x01UL << ETHERNET_DMA_OP_MODE_SR_Pos) /*!< ETHERNET DMA_OP_MODE: SR Mask */ #define ETHERNET_DMA_OP_MODE_OSF_Pos 2 /*!< ETHERNET DMA_OP_MODE: OSF Position */ #define ETHERNET_DMA_OP_MODE_OSF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_OSF_Pos) /*!< ETHERNET DMA_OP_MODE: OSF Mask */ #define ETHERNET_DMA_OP_MODE_RTC_Pos 3 /*!< ETHERNET DMA_OP_MODE: RTC Position */ #define ETHERNET_DMA_OP_MODE_RTC_Msk (0x03UL << ETHERNET_DMA_OP_MODE_RTC_Pos) /*!< ETHERNET DMA_OP_MODE: RTC Mask */ #define ETHERNET_DMA_OP_MODE_FUF_Pos 6 /*!< ETHERNET DMA_OP_MODE: FUF Position */ #define ETHERNET_DMA_OP_MODE_FUF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FUF_Pos) /*!< ETHERNET DMA_OP_MODE: FUF Mask */ #define ETHERNET_DMA_OP_MODE_FEF_Pos 7 /*!< ETHERNET DMA_OP_MODE: FEF Position */ #define ETHERNET_DMA_OP_MODE_FEF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FEF_Pos) /*!< ETHERNET DMA_OP_MODE: FEF Mask */ #define ETHERNET_DMA_OP_MODE_ST_Pos 13 /*!< ETHERNET DMA_OP_MODE: ST Position */ #define ETHERNET_DMA_OP_MODE_ST_Msk (0x01UL << ETHERNET_DMA_OP_MODE_ST_Pos) /*!< ETHERNET DMA_OP_MODE: ST Mask */ #define ETHERNET_DMA_OP_MODE_TTC_Pos 14 /*!< ETHERNET DMA_OP_MODE: TTC Position */ #define ETHERNET_DMA_OP_MODE_TTC_Msk (0x07UL << ETHERNET_DMA_OP_MODE_TTC_Pos) /*!< ETHERNET DMA_OP_MODE: TTC Mask */ #define ETHERNET_DMA_OP_MODE_FTF_Pos 20 /*!< ETHERNET DMA_OP_MODE: FTF Position */ #define ETHERNET_DMA_OP_MODE_FTF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_FTF_Pos) /*!< ETHERNET DMA_OP_MODE: FTF Mask */ #define ETHERNET_DMA_OP_MODE_DFF_Pos 24 /*!< ETHERNET DMA_OP_MODE: DFF Position */ #define ETHERNET_DMA_OP_MODE_DFF_Msk (0x01UL << ETHERNET_DMA_OP_MODE_DFF_Pos) /*!< ETHERNET DMA_OP_MODE: DFF Mask */ /* ----------------------------- ETHERNET_DMA_INT_EN ---------------------------- */ #define ETHERNET_DMA_INT_EN_TIE_Pos 0 /*!< ETHERNET DMA_INT_EN: TIE Position */ #define ETHERNET_DMA_INT_EN_TIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TIE_Pos) /*!< ETHERNET DMA_INT_EN: TIE Mask */ #define ETHERNET_DMA_INT_EN_TSE_Pos 1 /*!< ETHERNET DMA_INT_EN: TSE Position */ #define ETHERNET_DMA_INT_EN_TSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TSE_Pos) /*!< ETHERNET DMA_INT_EN: TSE Mask */ #define ETHERNET_DMA_INT_EN_TUE_Pos 2 /*!< ETHERNET DMA_INT_EN: TUE Position */ #define ETHERNET_DMA_INT_EN_TUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TUE_Pos) /*!< ETHERNET DMA_INT_EN: TUE Mask */ #define ETHERNET_DMA_INT_EN_TJE_Pos 3 /*!< ETHERNET DMA_INT_EN: TJE Position */ #define ETHERNET_DMA_INT_EN_TJE_Msk (0x01UL << ETHERNET_DMA_INT_EN_TJE_Pos) /*!< ETHERNET DMA_INT_EN: TJE Mask */ #define ETHERNET_DMA_INT_EN_OVE_Pos 4 /*!< ETHERNET DMA_INT_EN: OVE Position */ #define ETHERNET_DMA_INT_EN_OVE_Msk (0x01UL << ETHERNET_DMA_INT_EN_OVE_Pos) /*!< ETHERNET DMA_INT_EN: OVE Mask */ #define ETHERNET_DMA_INT_EN_UNE_Pos 5 /*!< ETHERNET DMA_INT_EN: UNE Position */ #define ETHERNET_DMA_INT_EN_UNE_Msk (0x01UL << ETHERNET_DMA_INT_EN_UNE_Pos) /*!< ETHERNET DMA_INT_EN: UNE Mask */ #define ETHERNET_DMA_INT_EN_RIE_Pos 6 /*!< ETHERNET DMA_INT_EN: RIE Position */ #define ETHERNET_DMA_INT_EN_RIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RIE_Pos) /*!< ETHERNET DMA_INT_EN: RIE Mask */ #define ETHERNET_DMA_INT_EN_RUE_Pos 7 /*!< ETHERNET DMA_INT_EN: RUE Position */ #define ETHERNET_DMA_INT_EN_RUE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RUE_Pos) /*!< ETHERNET DMA_INT_EN: RUE Mask */ #define ETHERNET_DMA_INT_EN_RSE_Pos 8 /*!< ETHERNET DMA_INT_EN: RSE Position */ #define ETHERNET_DMA_INT_EN_RSE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RSE_Pos) /*!< ETHERNET DMA_INT_EN: RSE Mask */ #define ETHERNET_DMA_INT_EN_RWE_Pos 9 /*!< ETHERNET DMA_INT_EN: RWE Position */ #define ETHERNET_DMA_INT_EN_RWE_Msk (0x01UL << ETHERNET_DMA_INT_EN_RWE_Pos) /*!< ETHERNET DMA_INT_EN: RWE Mask */ #define ETHERNET_DMA_INT_EN_ETE_Pos 10 /*!< ETHERNET DMA_INT_EN: ETE Position */ #define ETHERNET_DMA_INT_EN_ETE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ETE_Pos) /*!< ETHERNET DMA_INT_EN: ETE Mask */ #define ETHERNET_DMA_INT_EN_FBE_Pos 13 /*!< ETHERNET DMA_INT_EN: FBE Position */ #define ETHERNET_DMA_INT_EN_FBE_Msk (0x01UL << ETHERNET_DMA_INT_EN_FBE_Pos) /*!< ETHERNET DMA_INT_EN: FBE Mask */ #define ETHERNET_DMA_INT_EN_ERE_Pos 14 /*!< ETHERNET DMA_INT_EN: ERE Position */ #define ETHERNET_DMA_INT_EN_ERE_Msk (0x01UL << ETHERNET_DMA_INT_EN_ERE_Pos) /*!< ETHERNET DMA_INT_EN: ERE Mask */ #define ETHERNET_DMA_INT_EN_AIE_Pos 15 /*!< ETHERNET DMA_INT_EN: AIE Position */ #define ETHERNET_DMA_INT_EN_AIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_AIE_Pos) /*!< ETHERNET DMA_INT_EN: AIE Mask */ #define ETHERNET_DMA_INT_EN_NIE_Pos 16 /*!< ETHERNET DMA_INT_EN: NIE Position */ #define ETHERNET_DMA_INT_EN_NIE_Msk (0x01UL << ETHERNET_DMA_INT_EN_NIE_Pos) /*!< ETHERNET DMA_INT_EN: NIE Mask */ /* --------------------------- ETHERNET_DMA_MFRM_BUFOF -------------------------- */ #define ETHERNET_DMA_MFRM_BUFOF_FMC_Pos 0 /*!< ETHERNET DMA_MFRM_BUFOF: FMC Position */ #define ETHERNET_DMA_MFRM_BUFOF_FMC_Msk (0x0000ffffUL << ETHERNET_DMA_MFRM_BUFOF_FMC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMC Mask */ #define ETHERNET_DMA_MFRM_BUFOF_OC_Pos 16 /*!< ETHERNET DMA_MFRM_BUFOF: OC Position */ #define ETHERNET_DMA_MFRM_BUFOF_OC_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OC_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OC Mask */ #define ETHERNET_DMA_MFRM_BUFOF_FMA_Pos 17 /*!< ETHERNET DMA_MFRM_BUFOF: FMA Position */ #define ETHERNET_DMA_MFRM_BUFOF_FMA_Msk (0x000007ffUL << ETHERNET_DMA_MFRM_BUFOF_FMA_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: FMA Mask */ #define ETHERNET_DMA_MFRM_BUFOF_OF_Pos 28 /*!< ETHERNET DMA_MFRM_BUFOF: OF Position */ #define ETHERNET_DMA_MFRM_BUFOF_OF_Msk (0x01UL << ETHERNET_DMA_MFRM_BUFOF_OF_Pos) /*!< ETHERNET DMA_MFRM_BUFOF: OF Mask */ /* -------------------------- ETHERNET_DMA_REC_INT_WDT -------------------------- */ #define ETHERNET_DMA_REC_INT_WDT_RIWT_Pos 0 /*!< ETHERNET DMA_REC_INT_WDT: RIWT Position */ #define ETHERNET_DMA_REC_INT_WDT_RIWT_Msk (0x000000ffUL << ETHERNET_DMA_REC_INT_WDT_RIWT_Pos) /*!< ETHERNET DMA_REC_INT_WDT: RIWT Mask */ /* ----------------------- ETHERNET_DMA_CURHOST_TRANS_DES ----------------------- */ #define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Position */ #define ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_DES_HTD_Pos)/*!< ETHERNET DMA_CURHOST_TRANS_DES: HTD Mask */ /* ------------------------ ETHERNET_DMA_CURHOST_REC_DES ------------------------ */ #define ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Position */ #define ETHERNET_DMA_CURHOST_REC_DES_HRD_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_DES_HRD_Pos) /*!< ETHERNET DMA_CURHOST_REC_DES: HRD Mask */ /* ----------------------- ETHERNET_DMA_CURHOST_TRANS_BUF ----------------------- */ #define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos 0 /*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Position */ #define ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_TRANS_BUF_HTB_Pos)/*!< ETHERNET DMA_CURHOST_TRANS_BUF: HTB Mask */ /* ------------------------ ETHERNET_DMA_CURHOST_REC_BUF ------------------------ */ #define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos 0 /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Position */ #define ETHERNET_DMA_CURHOST_REC_BUF_HRB_Msk (0xffffffffUL << ETHERNET_DMA_CURHOST_REC_BUF_HRB_Pos) /*!< ETHERNET DMA_CURHOST_REC_BUF: HRB Mask */ /* ================================================================================ */ /* ================ struct 'ATIMER' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------- ATIMER_DOWNCOUNTER ----------------------------- */ #define ATIMER_DOWNCOUNTER_CVAL_Pos 0 /*!< ATIMER DOWNCOUNTER: CVAL Position */ #define ATIMER_DOWNCOUNTER_CVAL_Msk (0x0000ffffUL << ATIMER_DOWNCOUNTER_CVAL_Pos) /*!< ATIMER DOWNCOUNTER: CVAL Mask */ /* -------------------------------- ATIMER_PRESET ------------------------------- */ #define ATIMER_PRESET_PRESETVAL_Pos 0 /*!< ATIMER PRESET: PRESETVAL Position */ #define ATIMER_PRESET_PRESETVAL_Msk (0x0000ffffUL << ATIMER_PRESET_PRESETVAL_Pos) /*!< ATIMER PRESET: PRESETVAL Mask */ /* -------------------------------- ATIMER_CLR_EN ------------------------------- */ #define ATIMER_CLR_EN_CLR_EN_Pos 0 /*!< ATIMER CLR_EN: CLR_EN Position */ #define ATIMER_CLR_EN_CLR_EN_Msk (0x01UL << ATIMER_CLR_EN_CLR_EN_Pos) /*!< ATIMER CLR_EN: CLR_EN Mask */ /* -------------------------------- ATIMER_SET_EN ------------------------------- */ #define ATIMER_SET_EN_SET_EN_Pos 0 /*!< ATIMER SET_EN: SET_EN Position */ #define ATIMER_SET_EN_SET_EN_Msk (0x01UL << ATIMER_SET_EN_SET_EN_Pos) /*!< ATIMER SET_EN: SET_EN Mask */ /* -------------------------------- ATIMER_STATUS ------------------------------- */ #define ATIMER_STATUS_STAT_Pos 0 /*!< ATIMER STATUS: STAT Position */ #define ATIMER_STATUS_STAT_Msk (0x01UL << ATIMER_STATUS_STAT_Pos) /*!< ATIMER STATUS: STAT Mask */ /* -------------------------------- ATIMER_ENABLE ------------------------------- */ #define ATIMER_ENABLE_EN_Pos 0 /*!< ATIMER ENABLE: EN Position */ #define ATIMER_ENABLE_EN_Msk (0x01UL << ATIMER_ENABLE_EN_Pos) /*!< ATIMER ENABLE: EN Mask */ /* ------------------------------- ATIMER_CLR_STAT ------------------------------ */ #define ATIMER_CLR_STAT_CSTAT_Pos 0 /*!< ATIMER CLR_STAT: CSTAT Position */ #define ATIMER_CLR_STAT_CSTAT_Msk (0x01UL << ATIMER_CLR_STAT_CSTAT_Pos) /*!< ATIMER CLR_STAT: CSTAT Mask */ /* ------------------------------- ATIMER_SET_STAT ------------------------------ */ #define ATIMER_SET_STAT_SSTAT_Pos 0 /*!< ATIMER SET_STAT: SSTAT Position */ #define ATIMER_SET_STAT_SSTAT_Msk (0x01UL << ATIMER_SET_STAT_SSTAT_Pos) /*!< ATIMER SET_STAT: SSTAT Mask */ /* ================================================================================ */ /* ================ struct 'REGFILE' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------- REGFILE_REGFILE ------------------------------ */ #define REGFILE_REGFILE_REGVAL_Pos 0 /*!< REGFILE REGFILE: REGVAL Position */ #define REGFILE_REGFILE_REGVAL_Msk (0xffffffffUL << REGFILE_REGFILE_REGVAL_Pos) /*!< REGFILE REGFILE: REGVAL Mask */ /* ================================================================================ */ /* ================ struct 'PMC' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------- PMC_PD0_SLEEP0_HW_ENA --------------------------- */ #define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos 0 /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Position */ #define PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Msk (0x01UL << PMC_PD0_SLEEP0_HW_ENA_ENA_EVENT0_Pos) /*!< PMC PD0_SLEEP0_HW_ENA: ENA_EVENT0 Mask */ /* ----------------------------- PMC_PD0_SLEEP0_MODE ---------------------------- */ #define PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos 0 /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Position */ #define PMC_PD0_SLEEP0_MODE_PWR_STATE_Msk (0xffffffffUL << PMC_PD0_SLEEP0_MODE_PWR_STATE_Pos) /*!< PMC PD0_SLEEP0_MODE: PWR_STATE Mask */ /* ================================================================================ */ /* ================ struct 'CREG' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- CREG_CREG0 --------------------------------- */ #define CREG_CREG0_EN1KHZ_Pos 0 /*!< CREG CREG0: EN1KHZ Position */ #define CREG_CREG0_EN1KHZ_Msk (0x01UL << CREG_CREG0_EN1KHZ_Pos) /*!< CREG CREG0: EN1KHZ Mask */ #define CREG_CREG0_EN32KHZ_Pos 1 /*!< CREG CREG0: EN32KHZ Position */ #define CREG_CREG0_EN32KHZ_Msk (0x01UL << CREG_CREG0_EN32KHZ_Pos) /*!< CREG CREG0: EN32KHZ Mask */ #define CREG_CREG0_RESET32KHZ_Pos 2 /*!< CREG CREG0: RESET32KHZ Position */ #define CREG_CREG0_RESET32KHZ_Msk (0x01UL << CREG_CREG0_RESET32KHZ_Pos) /*!< CREG CREG0: RESET32KHZ Mask */ #define CREG_CREG0_PD32KHZ_Pos 3 /*!< CREG CREG0: PD32KHZ Position */ #define CREG_CREG0_PD32KHZ_Msk (0x01UL << CREG_CREG0_PD32KHZ_Pos) /*!< CREG CREG0: PD32KHZ Mask */ #define CREG_CREG0_USB0PHY_Pos 5 /*!< CREG CREG0: USB0PHY Position */ #define CREG_CREG0_USB0PHY_Msk (0x01UL << CREG_CREG0_USB0PHY_Pos) /*!< CREG CREG0: USB0PHY Mask */ #define CREG_CREG0_ALARMCTRL_Pos 6 /*!< CREG CREG0: ALARMCTRL Position */ #define CREG_CREG0_ALARMCTRL_Msk (0x03UL << CREG_CREG0_ALARMCTRL_Pos) /*!< CREG CREG0: ALARMCTRL Mask */ #define CREG_CREG0_BODLVL1_Pos 8 /*!< CREG CREG0: BODLVL1 Position */ #define CREG_CREG0_BODLVL1_Msk (0x03UL << CREG_CREG0_BODLVL1_Pos) /*!< CREG CREG0: BODLVL1 Mask */ #define CREG_CREG0_BODLVL2_Pos 10 /*!< CREG CREG0: BODLVL2 Position */ #define CREG_CREG0_BODLVL2_Msk (0x03UL << CREG_CREG0_BODLVL2_Pos) /*!< CREG CREG0: BODLVL2 Mask */ #define CREG_CREG0_SAMPLECTRL_Pos 12 /*!< CREG CREG0: SAMPLECTRL Position */ #define CREG_CREG0_SAMPLECTRL_Msk (0x03UL << CREG_CREG0_SAMPLECTRL_Pos) /*!< CREG CREG0: SAMPLECTRL Mask */ #define CREG_CREG0_WAKEUP0CTRL_Pos 14 /*!< CREG CREG0: WAKEUP0CTRL Position */ #define CREG_CREG0_WAKEUP0CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP0CTRL_Pos) /*!< CREG CREG0: WAKEUP0CTRL Mask */ #define CREG_CREG0_WAKEUP1CTRL_Pos 16 /*!< CREG CREG0: WAKEUP1CTRL Position */ #define CREG_CREG0_WAKEUP1CTRL_Msk (0x03UL << CREG_CREG0_WAKEUP1CTRL_Pos) /*!< CREG CREG0: WAKEUP1CTRL Mask */ /* -------------------------------- CREG_M4MEMMAP ------------------------------- */ #define CREG_M4MEMMAP_M4MAP_Pos 12 /*!< CREG M4MEMMAP: M4MAP Position */ #define CREG_M4MEMMAP_M4MAP_Msk (0x000fffffUL << CREG_M4MEMMAP_M4MAP_Pos) /*!< CREG M4MEMMAP: M4MAP Mask */ /* --------------------------------- CREG_CREG5 --------------------------------- */ #define CREG_CREG5_M0SUBTAPSEL_Pos 10 /*!< CREG CREG5: M0SUBTAPSEL Position */ #define CREG_CREG5_M0SUBTAPSEL_Msk (0x01UL << CREG_CREG5_M0SUBTAPSEL_Pos) /*!< CREG CREG5: M0SUBTAPSEL Mask */ #define CREG_CREG5_M4TAPSEL_Pos 11 /*!< CREG CREG5: M4TAPSEL Position */ #define CREG_CREG5_M4TAPSEL_Msk (0x01UL << CREG_CREG5_M4TAPSEL_Pos) /*!< CREG CREG5: M4TAPSEL Mask */ #define CREG_CREG5_M0APPTAPSEL_Pos 12 /*!< CREG CREG5: M0APPTAPSEL Position */ #define CREG_CREG5_M0APPTAPSEL_Msk (0x01UL << CREG_CREG5_M0APPTAPSEL_Pos) /*!< CREG CREG5: M0APPTAPSEL Mask */ /* --------------------------------- CREG_DMAMUX -------------------------------- */ #define CREG_DMAMUX_DMAMUXPER0_Pos 0 /*!< CREG DMAMUX: DMAMUXPER0 Position */ #define CREG_DMAMUX_DMAMUXPER0_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER0_Pos) /*!< CREG DMAMUX: DMAMUXPER0 Mask */ #define CREG_DMAMUX_DMAMUXPER1_Pos 2 /*!< CREG DMAMUX: DMAMUXPER1 Position */ #define CREG_DMAMUX_DMAMUXPER1_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER1_Pos) /*!< CREG DMAMUX: DMAMUXPER1 Mask */ #define CREG_DMAMUX_DMAMUXPER2_Pos 4 /*!< CREG DMAMUX: DMAMUXPER2 Position */ #define CREG_DMAMUX_DMAMUXPER2_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER2_Pos) /*!< CREG DMAMUX: DMAMUXPER2 Mask */ #define CREG_DMAMUX_DMAMUXPER3_Pos 6 /*!< CREG DMAMUX: DMAMUXPER3 Position */ #define CREG_DMAMUX_DMAMUXPER3_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER3_Pos) /*!< CREG DMAMUX: DMAMUXPER3 Mask */ #define CREG_DMAMUX_DMAMUXPER4_Pos 8 /*!< CREG DMAMUX: DMAMUXPER4 Position */ #define CREG_DMAMUX_DMAMUXPER4_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER4_Pos) /*!< CREG DMAMUX: DMAMUXPER4 Mask */ #define CREG_DMAMUX_DMAMUXPER5_Pos 10 /*!< CREG DMAMUX: DMAMUXPER5 Position */ #define CREG_DMAMUX_DMAMUXPER5_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER5_Pos) /*!< CREG DMAMUX: DMAMUXPER5 Mask */ #define CREG_DMAMUX_DMAMUXPER6_Pos 12 /*!< CREG DMAMUX: DMAMUXPER6 Position */ #define CREG_DMAMUX_DMAMUXPER6_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER6_Pos) /*!< CREG DMAMUX: DMAMUXPER6 Mask */ #define CREG_DMAMUX_DMAMUXPER7_Pos 14 /*!< CREG DMAMUX: DMAMUXPER7 Position */ #define CREG_DMAMUX_DMAMUXPER7_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER7_Pos) /*!< CREG DMAMUX: DMAMUXPER7 Mask */ #define CREG_DMAMUX_DMAMUXPER8_Pos 16 /*!< CREG DMAMUX: DMAMUXPER8 Position */ #define CREG_DMAMUX_DMAMUXPER8_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER8_Pos) /*!< CREG DMAMUX: DMAMUXPER8 Mask */ #define CREG_DMAMUX_DMAMUXPER9_Pos 18 /*!< CREG DMAMUX: DMAMUXPER9 Position */ #define CREG_DMAMUX_DMAMUXPER9_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER9_Pos) /*!< CREG DMAMUX: DMAMUXPER9 Mask */ #define CREG_DMAMUX_DMAMUXPER10_Pos 20 /*!< CREG DMAMUX: DMAMUXPER10 Position */ #define CREG_DMAMUX_DMAMUXPER10_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER10_Pos) /*!< CREG DMAMUX: DMAMUXPER10 Mask */ #define CREG_DMAMUX_DMAMUXPER11_Pos 22 /*!< CREG DMAMUX: DMAMUXPER11 Position */ #define CREG_DMAMUX_DMAMUXPER11_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER11_Pos) /*!< CREG DMAMUX: DMAMUXPER11 Mask */ #define CREG_DMAMUX_DMAMUXPER12_Pos 24 /*!< CREG DMAMUX: DMAMUXPER12 Position */ #define CREG_DMAMUX_DMAMUXPER12_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER12_Pos) /*!< CREG DMAMUX: DMAMUXPER12 Mask */ #define CREG_DMAMUX_DMAMUXPER13_Pos 26 /*!< CREG DMAMUX: DMAMUXPER13 Position */ #define CREG_DMAMUX_DMAMUXPER13_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER13_Pos) /*!< CREG DMAMUX: DMAMUXPER13 Mask */ #define CREG_DMAMUX_DMAMUXPER14_Pos 28 /*!< CREG DMAMUX: DMAMUXPER14 Position */ #define CREG_DMAMUX_DMAMUXPER14_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER14_Pos) /*!< CREG DMAMUX: DMAMUXPER14 Mask */ #define CREG_DMAMUX_DMAMUXPER15_Pos 30 /*!< CREG DMAMUX: DMAMUXPER15 Position */ #define CREG_DMAMUX_DMAMUXPER15_Msk (0x03UL << CREG_DMAMUX_DMAMUXPER15_Pos) /*!< CREG DMAMUX: DMAMUXPER15 Mask */ /* ------------------------------- CREG_FLASHCFGA ------------------------------- */ #define CREG_FLASHCFGA_FLASHTIM_Pos 12 /*!< CREG FLASHCFGA: FLASHTIM Position */ #define CREG_FLASHCFGA_FLASHTIM_Msk (0x0fUL << CREG_FLASHCFGA_FLASHTIM_Pos) /*!< CREG FLASHCFGA: FLASHTIM Mask */ #define CREG_FLASHCFGA_POW_Pos 31 /*!< CREG FLASHCFGA: POW Position */ #define CREG_FLASHCFGA_POW_Msk (0x01UL << CREG_FLASHCFGA_POW_Pos) /*!< CREG FLASHCFGA: POW Mask */ /* ------------------------------- CREG_FLASHCFGB ------------------------------- */ #define CREG_FLASHCFGB_FLASHTIM_Pos 12 /*!< CREG FLASHCFGB: FLASHTIM Position */ #define CREG_FLASHCFGB_FLASHTIM_Msk (0x0fUL << CREG_FLASHCFGB_FLASHTIM_Pos) /*!< CREG FLASHCFGB: FLASHTIM Mask */ #define CREG_FLASHCFGB_POW_Pos 31 /*!< CREG FLASHCFGB: POW Position */ #define CREG_FLASHCFGB_POW_Msk (0x01UL << CREG_FLASHCFGB_POW_Pos) /*!< CREG FLASHCFGB: POW Mask */ /* --------------------------------- CREG_ETBCFG -------------------------------- */ #define CREG_ETBCFG_ETB_Pos 0 /*!< CREG ETBCFG: ETB Position */ #define CREG_ETBCFG_ETB_Msk (0x01UL << CREG_ETBCFG_ETB_Pos) /*!< CREG ETBCFG: ETB Mask */ /* --------------------------------- CREG_CREG6 --------------------------------- */ #define CREG_CREG6_ETHMODE_Pos 0 /*!< CREG CREG6: ETHMODE Position */ #define CREG_CREG6_ETHMODE_Msk (0x07UL << CREG_CREG6_ETHMODE_Pos) /*!< CREG CREG6: ETHMODE Mask */ #define CREG_CREG6_CTOUTCTRL_Pos 4 /*!< CREG CREG6: CTOUTCTRL Position */ #define CREG_CREG6_CTOUTCTRL_Msk (0x01UL << CREG_CREG6_CTOUTCTRL_Pos) /*!< CREG CREG6: CTOUTCTRL Mask */ #define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos 12 /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Position */ #define CREG_CREG6_I2S0_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_TX_SCK_IN_SEL Mask */ #define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos 13 /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Position */ #define CREG_CREG6_I2S0_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S0_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S0_RX_SCK_IN_SEL Mask */ #define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos 14 /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Position */ #define CREG_CREG6_I2S1_TX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_TX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_TX_SCK_IN_SEL Mask */ #define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos 15 /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Position */ #define CREG_CREG6_I2S1_RX_SCK_IN_SEL_Msk (0x01UL << CREG_CREG6_I2S1_RX_SCK_IN_SEL_Pos) /*!< CREG CREG6: I2S1_RX_SCK_IN_SEL Mask */ #define CREG_CREG6_EMC_CLK_SEL_Pos 16 /*!< CREG CREG6: EMC_CLK_SEL Position */ #define CREG_CREG6_EMC_CLK_SEL_Msk (0x01UL << CREG_CREG6_EMC_CLK_SEL_Pos) /*!< CREG CREG6: EMC_CLK_SEL Mask */ /* ------------------------------- CREG_M4TXEVENT ------------------------------- */ #define CREG_M4TXEVENT_TXEVCLR_Pos 0 /*!< CREG M4TXEVENT: TXEVCLR Position */ #define CREG_M4TXEVENT_TXEVCLR_Msk (0x01UL << CREG_M4TXEVENT_TXEVCLR_Pos) /*!< CREG M4TXEVENT: TXEVCLR Mask */ /* --------------------------------- CREG_CHIPID -------------------------------- */ #define CREG_CHIPID_ID_Pos 0 /*!< CREG CHIPID: ID Position */ #define CREG_CHIPID_ID_Msk (0xffffffffUL << CREG_CHIPID_ID_Pos) /*!< CREG CHIPID: ID Mask */ /* ------------------------------ CREG_M0SUBMEMMAP ------------------------------ */ #define CREG_M0SUBMEMMAP_M0SUBMAP_Pos 12 /*!< CREG M0SUBMEMMAP: M0SUBMAP Position */ #define CREG_M0SUBMEMMAP_M0SUBMAP_Msk (0x000fffffUL << CREG_M0SUBMEMMAP_M0SUBMAP_Pos) /*!< CREG M0SUBMEMMAP: M0SUBMAP Mask */ /* ------------------------------ CREG_M0SUBTXEVENT ----------------------------- */ #define CREG_M0SUBTXEVENT_TXEVCLR_Pos 0 /*!< CREG M0SUBTXEVENT: TXEVCLR Position */ #define CREG_M0SUBTXEVENT_TXEVCLR_Msk (0x01UL << CREG_M0SUBTXEVENT_TXEVCLR_Pos) /*!< CREG M0SUBTXEVENT: TXEVCLR Mask */ /* ------------------------------ CREG_M0APPTXEVENT ----------------------------- */ #define CREG_M0APPTXEVENT_TXEVCLR_Pos 0 /*!< CREG M0APPTXEVENT: TXEVCLR Position */ #define CREG_M0APPTXEVENT_TXEVCLR_Msk (0x01UL << CREG_M0APPTXEVENT_TXEVCLR_Pos) /*!< CREG M0APPTXEVENT: TXEVCLR Mask */ /* ------------------------------ CREG_M0APPMEMMAP ------------------------------ */ #define CREG_M0APPMEMMAP_M0APPMAP_Pos 12 /*!< CREG M0APPMEMMAP: M0APPMAP Position */ #define CREG_M0APPMEMMAP_M0APPMAP_Msk (0x000fffffUL << CREG_M0APPMEMMAP_M0APPMAP_Pos) /*!< CREG M0APPMEMMAP: M0APPMAP Mask */ /* ------------------------------- CREG_USB0FLADJ ------------------------------- */ #define CREG_USB0FLADJ_FLTV_Pos 0 /*!< CREG USB0FLADJ: FLTV Position */ #define CREG_USB0FLADJ_FLTV_Msk (0x3fUL << CREG_USB0FLADJ_FLTV_Pos) /*!< CREG USB0FLADJ: FLTV Mask */ /* ------------------------------- CREG_USB1FLADJ ------------------------------- */ #define CREG_USB1FLADJ_FLTV_Pos 0 /*!< CREG USB1FLADJ: FLTV Position */ #define CREG_USB1FLADJ_FLTV_Msk (0x3fUL << CREG_USB1FLADJ_FLTV_Pos) /*!< CREG USB1FLADJ: FLTV Mask */ /* ================================================================================ */ /* ================ struct 'EVENTROUTER' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------ EVENTROUTER_HILO ------------------------------ */ #define EVENTROUTER_HILO_WAKEUP0_L_Pos 0 /*!< EVENTROUTER HILO: WAKEUP0_L Position */ #define EVENTROUTER_HILO_WAKEUP0_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP0_L_Pos) /*!< EVENTROUTER HILO: WAKEUP0_L Mask */ #define EVENTROUTER_HILO_WAKEUP1_L_Pos 1 /*!< EVENTROUTER HILO: WAKEUP1_L Position */ #define EVENTROUTER_HILO_WAKEUP1_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP1_L_Pos) /*!< EVENTROUTER HILO: WAKEUP1_L Mask */ #define EVENTROUTER_HILO_WAKEUP2_L_Pos 2 /*!< EVENTROUTER HILO: WAKEUP2_L Position */ #define EVENTROUTER_HILO_WAKEUP2_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP2_L_Pos) /*!< EVENTROUTER HILO: WAKEUP2_L Mask */ #define EVENTROUTER_HILO_WAKEUP3_L_Pos 3 /*!< EVENTROUTER HILO: WAKEUP3_L Position */ #define EVENTROUTER_HILO_WAKEUP3_L_Msk (0x01UL << EVENTROUTER_HILO_WAKEUP3_L_Pos) /*!< EVENTROUTER HILO: WAKEUP3_L Mask */ #define EVENTROUTER_HILO_ATIMER_L_Pos 4 /*!< EVENTROUTER HILO: ATIMER_L Position */ #define EVENTROUTER_HILO_ATIMER_L_Msk (0x01UL << EVENTROUTER_HILO_ATIMER_L_Pos) /*!< EVENTROUTER HILO: ATIMER_L Mask */ #define EVENTROUTER_HILO_RTC_L_Pos 5 /*!< EVENTROUTER HILO: RTC_L Position */ #define EVENTROUTER_HILO_RTC_L_Msk (0x01UL << EVENTROUTER_HILO_RTC_L_Pos) /*!< EVENTROUTER HILO: RTC_L Mask */ #define EVENTROUTER_HILO_BOD_L_Pos 6 /*!< EVENTROUTER HILO: BOD_L Position */ #define EVENTROUTER_HILO_BOD_L_Msk (0x01UL << EVENTROUTER_HILO_BOD_L_Pos) /*!< EVENTROUTER HILO: BOD_L Mask */ #define EVENTROUTER_HILO_WWDT_L_Pos 7 /*!< EVENTROUTER HILO: WWDT_L Position */ #define EVENTROUTER_HILO_WWDT_L_Msk (0x01UL << EVENTROUTER_HILO_WWDT_L_Pos) /*!< EVENTROUTER HILO: WWDT_L Mask */ #define EVENTROUTER_HILO_ETH_L_Pos 8 /*!< EVENTROUTER HILO: ETH_L Position */ #define EVENTROUTER_HILO_ETH_L_Msk (0x01UL << EVENTROUTER_HILO_ETH_L_Pos) /*!< EVENTROUTER HILO: ETH_L Mask */ #define EVENTROUTER_HILO_USB0_L_Pos 9 /*!< EVENTROUTER HILO: USB0_L Position */ #define EVENTROUTER_HILO_USB0_L_Msk (0x01UL << EVENTROUTER_HILO_USB0_L_Pos) /*!< EVENTROUTER HILO: USB0_L Mask */ #define EVENTROUTER_HILO_USB1_L_Pos 10 /*!< EVENTROUTER HILO: USB1_L Position */ #define EVENTROUTER_HILO_USB1_L_Msk (0x01UL << EVENTROUTER_HILO_USB1_L_Pos) /*!< EVENTROUTER HILO: USB1_L Mask */ #define EVENTROUTER_HILO_SDMMC_L_Pos 11 /*!< EVENTROUTER HILO: SDMMC_L Position */ #define EVENTROUTER_HILO_SDMMC_L_Msk (0x01UL << EVENTROUTER_HILO_SDMMC_L_Pos) /*!< EVENTROUTER HILO: SDMMC_L Mask */ #define EVENTROUTER_HILO_CAN_L_Pos 12 /*!< EVENTROUTER HILO: CAN_L Position */ #define EVENTROUTER_HILO_CAN_L_Msk (0x01UL << EVENTROUTER_HILO_CAN_L_Pos) /*!< EVENTROUTER HILO: CAN_L Mask */ #define EVENTROUTER_HILO_TIM2_L_Pos 13 /*!< EVENTROUTER HILO: TIM2_L Position */ #define EVENTROUTER_HILO_TIM2_L_Msk (0x01UL << EVENTROUTER_HILO_TIM2_L_Pos) /*!< EVENTROUTER HILO: TIM2_L Mask */ #define EVENTROUTER_HILO_TIM6_L_Pos 14 /*!< EVENTROUTER HILO: TIM6_L Position */ #define EVENTROUTER_HILO_TIM6_L_Msk (0x01UL << EVENTROUTER_HILO_TIM6_L_Pos) /*!< EVENTROUTER HILO: TIM6_L Mask */ #define EVENTROUTER_HILO_QEI_L_Pos 15 /*!< EVENTROUTER HILO: QEI_L Position */ #define EVENTROUTER_HILO_QEI_L_Msk (0x01UL << EVENTROUTER_HILO_QEI_L_Pos) /*!< EVENTROUTER HILO: QEI_L Mask */ #define EVENTROUTER_HILO_TIM14_L_Pos 16 /*!< EVENTROUTER HILO: TIM14_L Position */ #define EVENTROUTER_HILO_TIM14_L_Msk (0x01UL << EVENTROUTER_HILO_TIM14_L_Pos) /*!< EVENTROUTER HILO: TIM14_L Mask */ #define EVENTROUTER_HILO_RESET_L_Pos 19 /*!< EVENTROUTER HILO: RESET_L Position */ #define EVENTROUTER_HILO_RESET_L_Msk (0x01UL << EVENTROUTER_HILO_RESET_L_Pos) /*!< EVENTROUTER HILO: RESET_L Mask */ #define EVENTROUTER_HILO_BODRESET_L_Pos 20 /*!< EVENTROUTER HILO: BODRESET_L Position */ #define EVENTROUTER_HILO_BODRESET_L_Msk (0x01UL << EVENTROUTER_HILO_BODRESET_L_Pos) /*!< EVENTROUTER HILO: BODRESET_L Mask */ #define EVENTROUTER_HILO_DPDRESET_L_Pos 21 /*!< EVENTROUTER HILO: DPDRESET_L Position */ #define EVENTROUTER_HILO_DPDRESET_L_Msk (0x01UL << EVENTROUTER_HILO_DPDRESET_L_Pos) /*!< EVENTROUTER HILO: DPDRESET_L Mask */ /* ------------------------------ EVENTROUTER_EDGE ------------------------------ */ #define EVENTROUTER_EDGE_WAKEUP0_E_Pos 0 /*!< EVENTROUTER EDGE: WAKEUP0_E Position */ #define EVENTROUTER_EDGE_WAKEUP0_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP0_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP0_E Mask */ #define EVENTROUTER_EDGE_WAKEUP1_E_Pos 1 /*!< EVENTROUTER EDGE: WAKEUP1_E Position */ #define EVENTROUTER_EDGE_WAKEUP1_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP1_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP1_E Mask */ #define EVENTROUTER_EDGE_WAKEUP2_E_Pos 2 /*!< EVENTROUTER EDGE: WAKEUP2_E Position */ #define EVENTROUTER_EDGE_WAKEUP2_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP2_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP2_E Mask */ #define EVENTROUTER_EDGE_WAKEUP3_E_Pos 3 /*!< EVENTROUTER EDGE: WAKEUP3_E Position */ #define EVENTROUTER_EDGE_WAKEUP3_E_Msk (0x01UL << EVENTROUTER_EDGE_WAKEUP3_E_Pos) /*!< EVENTROUTER EDGE: WAKEUP3_E Mask */ #define EVENTROUTER_EDGE_ATIMER_E_Pos 4 /*!< EVENTROUTER EDGE: ATIMER_E Position */ #define EVENTROUTER_EDGE_ATIMER_E_Msk (0x01UL << EVENTROUTER_EDGE_ATIMER_E_Pos) /*!< EVENTROUTER EDGE: ATIMER_E Mask */ #define EVENTROUTER_EDGE_RTC_E_Pos 5 /*!< EVENTROUTER EDGE: RTC_E Position */ #define EVENTROUTER_EDGE_RTC_E_Msk (0x01UL << EVENTROUTER_EDGE_RTC_E_Pos) /*!< EVENTROUTER EDGE: RTC_E Mask */ #define EVENTROUTER_EDGE_BOD_E_Pos 6 /*!< EVENTROUTER EDGE: BOD_E Position */ #define EVENTROUTER_EDGE_BOD_E_Msk (0x01UL << EVENTROUTER_EDGE_BOD_E_Pos) /*!< EVENTROUTER EDGE: BOD_E Mask */ #define EVENTROUTER_EDGE_WWDT_E_Pos 7 /*!< EVENTROUTER EDGE: WWDT_E Position */ #define EVENTROUTER_EDGE_WWDT_E_Msk (0x01UL << EVENTROUTER_EDGE_WWDT_E_Pos) /*!< EVENTROUTER EDGE: WWDT_E Mask */ #define EVENTROUTER_EDGE_ETH_E_Pos 8 /*!< EVENTROUTER EDGE: ETH_E Position */ #define EVENTROUTER_EDGE_ETH_E_Msk (0x01UL << EVENTROUTER_EDGE_ETH_E_Pos) /*!< EVENTROUTER EDGE: ETH_E Mask */ #define EVENTROUTER_EDGE_USB0_E_Pos 9 /*!< EVENTROUTER EDGE: USB0_E Position */ #define EVENTROUTER_EDGE_USB0_E_Msk (0x01UL << EVENTROUTER_EDGE_USB0_E_Pos) /*!< EVENTROUTER EDGE: USB0_E Mask */ #define EVENTROUTER_EDGE_USB1_E_Pos 10 /*!< EVENTROUTER EDGE: USB1_E Position */ #define EVENTROUTER_EDGE_USB1_E_Msk (0x01UL << EVENTROUTER_EDGE_USB1_E_Pos) /*!< EVENTROUTER EDGE: USB1_E Mask */ #define EVENTROUTER_EDGE_SDMMC_E_Pos 11 /*!< EVENTROUTER EDGE: SDMMC_E Position */ #define EVENTROUTER_EDGE_SDMMC_E_Msk (0x01UL << EVENTROUTER_EDGE_SDMMC_E_Pos) /*!< EVENTROUTER EDGE: SDMMC_E Mask */ #define EVENTROUTER_EDGE_CAN_E_Pos 12 /*!< EVENTROUTER EDGE: CAN_E Position */ #define EVENTROUTER_EDGE_CAN_E_Msk (0x01UL << EVENTROUTER_EDGE_CAN_E_Pos) /*!< EVENTROUTER EDGE: CAN_E Mask */ #define EVENTROUTER_EDGE_TIM2_E_Pos 13 /*!< EVENTROUTER EDGE: TIM2_E Position */ #define EVENTROUTER_EDGE_TIM2_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM2_E_Pos) /*!< EVENTROUTER EDGE: TIM2_E Mask */ #define EVENTROUTER_EDGE_TIM6_E_Pos 14 /*!< EVENTROUTER EDGE: TIM6_E Position */ #define EVENTROUTER_EDGE_TIM6_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM6_E_Pos) /*!< EVENTROUTER EDGE: TIM6_E Mask */ #define EVENTROUTER_EDGE_QEI_E_Pos 15 /*!< EVENTROUTER EDGE: QEI_E Position */ #define EVENTROUTER_EDGE_QEI_E_Msk (0x01UL << EVENTROUTER_EDGE_QEI_E_Pos) /*!< EVENTROUTER EDGE: QEI_E Mask */ #define EVENTROUTER_EDGE_TIM14_E_Pos 16 /*!< EVENTROUTER EDGE: TIM14_E Position */ #define EVENTROUTER_EDGE_TIM14_E_Msk (0x01UL << EVENTROUTER_EDGE_TIM14_E_Pos) /*!< EVENTROUTER EDGE: TIM14_E Mask */ #define EVENTROUTER_EDGE_RESET_E_Pos 19 /*!< EVENTROUTER EDGE: RESET_E Position */ #define EVENTROUTER_EDGE_RESET_E_Msk (0x01UL << EVENTROUTER_EDGE_RESET_E_Pos) /*!< EVENTROUTER EDGE: RESET_E Mask */ #define EVENTROUTER_EDGE_BODRESET_E_Pos 20 /*!< EVENTROUTER EDGE: BODRESET_E Position */ #define EVENTROUTER_EDGE_BODRESET_E_Msk (0x01UL << EVENTROUTER_EDGE_BODRESET_E_Pos) /*!< EVENTROUTER EDGE: BODRESET_E Mask */ #define EVENTROUTER_EDGE_DPDRESET_E_Pos 21 /*!< EVENTROUTER EDGE: DPDRESET_E Position */ #define EVENTROUTER_EDGE_DPDRESET_E_Msk (0x01UL << EVENTROUTER_EDGE_DPDRESET_E_Pos) /*!< EVENTROUTER EDGE: DPDRESET_E Mask */ /* ----------------------------- EVENTROUTER_CLR_EN ----------------------------- */ #define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos 0 /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Position */ #define EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP0_CLREN Mask */ #define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos 1 /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Position */ #define EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP1_CLREN Mask */ #define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos 2 /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Position */ #define EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP2_CLREN Mask */ #define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos 3 /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Position */ #define EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WAKEUP3_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WAKEUP3_CLREN Mask */ #define EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos 4 /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Position */ #define EVENTROUTER_CLR_EN_ATIMER_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ATIMER_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ATIMER_CLREN Mask */ #define EVENTROUTER_CLR_EN_RTC_CLREN_Pos 5 /*!< EVENTROUTER CLR_EN: RTC_CLREN Position */ #define EVENTROUTER_CLR_EN_RTC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RTC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RTC_CLREN Mask */ #define EVENTROUTER_CLR_EN_BOD_CLREN_Pos 6 /*!< EVENTROUTER CLR_EN: BOD_CLREN Position */ #define EVENTROUTER_CLR_EN_BOD_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BOD_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BOD_CLREN Mask */ #define EVENTROUTER_CLR_EN_WWDT_CLREN_Pos 7 /*!< EVENTROUTER CLR_EN: WWDT_CLREN Position */ #define EVENTROUTER_CLR_EN_WWDT_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_WWDT_CLREN_Pos) /*!< EVENTROUTER CLR_EN: WWDT_CLREN Mask */ #define EVENTROUTER_CLR_EN_ETH_CLREN_Pos 8 /*!< EVENTROUTER CLR_EN: ETH_CLREN Position */ #define EVENTROUTER_CLR_EN_ETH_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_ETH_CLREN_Pos) /*!< EVENTROUTER CLR_EN: ETH_CLREN Mask */ #define EVENTROUTER_CLR_EN_USB0_CLREN_Pos 9 /*!< EVENTROUTER CLR_EN: USB0_CLREN Position */ #define EVENTROUTER_CLR_EN_USB0_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB0_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB0_CLREN Mask */ #define EVENTROUTER_CLR_EN_USB1_CLREN_Pos 10 /*!< EVENTROUTER CLR_EN: USB1_CLREN Position */ #define EVENTROUTER_CLR_EN_USB1_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_USB1_CLREN_Pos) /*!< EVENTROUTER CLR_EN: USB1_CLREN Mask */ #define EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos 11 /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Position */ #define EVENTROUTER_CLR_EN_SDMMC_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_SDMMC_CLREN_Pos) /*!< EVENTROUTER CLR_EN: SDMMC_CLREN Mask */ #define EVENTROUTER_CLR_EN_CAN_CLREN_Pos 12 /*!< EVENTROUTER CLR_EN: CAN_CLREN Position */ #define EVENTROUTER_CLR_EN_CAN_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_CAN_CLREN_Pos) /*!< EVENTROUTER CLR_EN: CAN_CLREN Mask */ #define EVENTROUTER_CLR_EN_TIM2_CLREN_Pos 13 /*!< EVENTROUTER CLR_EN: TIM2_CLREN Position */ #define EVENTROUTER_CLR_EN_TIM2_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM2_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM2_CLREN Mask */ #define EVENTROUTER_CLR_EN_TIM6_CLREN_Pos 14 /*!< EVENTROUTER CLR_EN: TIM6_CLREN Position */ #define EVENTROUTER_CLR_EN_TIM6_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM6_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM6_CLREN Mask */ #define EVENTROUTER_CLR_EN_QEI_CLREN_Pos 15 /*!< EVENTROUTER CLR_EN: QEI_CLREN Position */ #define EVENTROUTER_CLR_EN_QEI_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_QEI_CLREN_Pos) /*!< EVENTROUTER CLR_EN: QEI_CLREN Mask */ #define EVENTROUTER_CLR_EN_TIM14_CLREN_Pos 16 /*!< EVENTROUTER CLR_EN: TIM14_CLREN Position */ #define EVENTROUTER_CLR_EN_TIM14_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_TIM14_CLREN_Pos) /*!< EVENTROUTER CLR_EN: TIM14_CLREN Mask */ #define EVENTROUTER_CLR_EN_RESET_CLREN_Pos 19 /*!< EVENTROUTER CLR_EN: RESET_CLREN Position */ #define EVENTROUTER_CLR_EN_RESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_RESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: RESET_CLREN Mask */ #define EVENTROUTER_CLR_EN_BODRESET_CLREN_Pos 20 /*!< EVENTROUTER CLR_EN: BODRESET_CLREN Position */ #define EVENTROUTER_CLR_EN_BODRESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_BODRESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: BODRESET_CLREN Mask */ #define EVENTROUTER_CLR_EN_DPDRESET_CLREN_Pos 21 /*!< EVENTROUTER CLR_EN: DPDRESET_CLREN Position */ #define EVENTROUTER_CLR_EN_DPDRESET_CLREN_Msk (0x01UL << EVENTROUTER_CLR_EN_DPDRESET_CLREN_Pos) /*!< EVENTROUTER CLR_EN: DPDRESET_CLREN Mask */ /* ----------------------------- EVENTROUTER_SET_EN ----------------------------- */ #define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos 0 /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Position */ #define EVENTROUTER_SET_EN_WAKEUP0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP0_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP0_SETEN Mask */ #define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos 1 /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Position */ #define EVENTROUTER_SET_EN_WAKEUP1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP1_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP1_SETEN Mask */ #define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos 2 /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Position */ #define EVENTROUTER_SET_EN_WAKEUP2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP2_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP2_SETEN Mask */ #define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos 3 /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Position */ #define EVENTROUTER_SET_EN_WAKEUP3_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WAKEUP3_SETEN_Pos) /*!< EVENTROUTER SET_EN: WAKEUP3_SETEN Mask */ #define EVENTROUTER_SET_EN_ATIMER_SETEN_Pos 4 /*!< EVENTROUTER SET_EN: ATIMER_SETEN Position */ #define EVENTROUTER_SET_EN_ATIMER_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ATIMER_SETEN_Pos) /*!< EVENTROUTER SET_EN: ATIMER_SETEN Mask */ #define EVENTROUTER_SET_EN_RTC_SETEN_Pos 5 /*!< EVENTROUTER SET_EN: RTC_SETEN Position */ #define EVENTROUTER_SET_EN_RTC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RTC_SETEN_Pos) /*!< EVENTROUTER SET_EN: RTC_SETEN Mask */ #define EVENTROUTER_SET_EN_BOD_SETEN_Pos 6 /*!< EVENTROUTER SET_EN: BOD_SETEN Position */ #define EVENTROUTER_SET_EN_BOD_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BOD_SETEN_Pos) /*!< EVENTROUTER SET_EN: BOD_SETEN Mask */ #define EVENTROUTER_SET_EN_WWDT_SETEN_Pos 7 /*!< EVENTROUTER SET_EN: WWDT_SETEN Position */ #define EVENTROUTER_SET_EN_WWDT_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_WWDT_SETEN_Pos) /*!< EVENTROUTER SET_EN: WWDT_SETEN Mask */ #define EVENTROUTER_SET_EN_ETH_SETEN_Pos 8 /*!< EVENTROUTER SET_EN: ETH_SETEN Position */ #define EVENTROUTER_SET_EN_ETH_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_ETH_SETEN_Pos) /*!< EVENTROUTER SET_EN: ETH_SETEN Mask */ #define EVENTROUTER_SET_EN_USB0_SETEN_Pos 9 /*!< EVENTROUTER SET_EN: USB0_SETEN Position */ #define EVENTROUTER_SET_EN_USB0_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB0_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB0_SETEN Mask */ #define EVENTROUTER_SET_EN_USB1_SETEN_Pos 10 /*!< EVENTROUTER SET_EN: USB1_SETEN Position */ #define EVENTROUTER_SET_EN_USB1_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_USB1_SETEN_Pos) /*!< EVENTROUTER SET_EN: USB1_SETEN Mask */ #define EVENTROUTER_SET_EN_SDMMC_SETEN_Pos 11 /*!< EVENTROUTER SET_EN: SDMMC_SETEN Position */ #define EVENTROUTER_SET_EN_SDMMC_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_SDMMC_SETEN_Pos) /*!< EVENTROUTER SET_EN: SDMMC_SETEN Mask */ #define EVENTROUTER_SET_EN_CAN_SETEN_Pos 12 /*!< EVENTROUTER SET_EN: CAN_SETEN Position */ #define EVENTROUTER_SET_EN_CAN_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_CAN_SETEN_Pos) /*!< EVENTROUTER SET_EN: CAN_SETEN Mask */ #define EVENTROUTER_SET_EN_TIM2_SETEN_Pos 13 /*!< EVENTROUTER SET_EN: TIM2_SETEN Position */ #define EVENTROUTER_SET_EN_TIM2_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM2_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM2_SETEN Mask */ #define EVENTROUTER_SET_EN_TIM6_SETEN_Pos 14 /*!< EVENTROUTER SET_EN: TIM6_SETEN Position */ #define EVENTROUTER_SET_EN_TIM6_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM6_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM6_SETEN Mask */ #define EVENTROUTER_SET_EN_QEI_SETEN_Pos 15 /*!< EVENTROUTER SET_EN: QEI_SETEN Position */ #define EVENTROUTER_SET_EN_QEI_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_QEI_SETEN_Pos) /*!< EVENTROUTER SET_EN: QEI_SETEN Mask */ #define EVENTROUTER_SET_EN_TIM14_SETEN_Pos 16 /*!< EVENTROUTER SET_EN: TIM14_SETEN Position */ #define EVENTROUTER_SET_EN_TIM14_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_TIM14_SETEN_Pos) /*!< EVENTROUTER SET_EN: TIM14_SETEN Mask */ #define EVENTROUTER_SET_EN_RESET_SETEN_Pos 19 /*!< EVENTROUTER SET_EN: RESET_SETEN Position */ #define EVENTROUTER_SET_EN_RESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_RESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: RESET_SETEN Mask */ #define EVENTROUTER_SET_EN_BODRESET_SETEN_Pos 20 /*!< EVENTROUTER SET_EN: BODRESET_SETEN Position */ #define EVENTROUTER_SET_EN_BODRESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_BODRESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: BODRESET_SETEN Mask */ #define EVENTROUTER_SET_EN_DPDRESET_SETEN_Pos 21 /*!< EVENTROUTER SET_EN: DPDRESET_SETEN Position */ #define EVENTROUTER_SET_EN_DPDRESET_SETEN_Msk (0x01UL << EVENTROUTER_SET_EN_DPDRESET_SETEN_Pos) /*!< EVENTROUTER SET_EN: DPDRESET_SETEN Mask */ /* ----------------------------- EVENTROUTER_STATUS ----------------------------- */ #define EVENTROUTER_STATUS_WAKEUP0_ST_Pos 0 /*!< EVENTROUTER STATUS: WAKEUP0_ST Position */ #define EVENTROUTER_STATUS_WAKEUP0_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP0_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP0_ST Mask */ #define EVENTROUTER_STATUS_WAKEUP1_ST_Pos 1 /*!< EVENTROUTER STATUS: WAKEUP1_ST Position */ #define EVENTROUTER_STATUS_WAKEUP1_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP1_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP1_ST Mask */ #define EVENTROUTER_STATUS_WAKEUP2_ST_Pos 2 /*!< EVENTROUTER STATUS: WAKEUP2_ST Position */ #define EVENTROUTER_STATUS_WAKEUP2_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP2_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP2_ST Mask */ #define EVENTROUTER_STATUS_WAKEUP3_ST_Pos 3 /*!< EVENTROUTER STATUS: WAKEUP3_ST Position */ #define EVENTROUTER_STATUS_WAKEUP3_ST_Msk (0x01UL << EVENTROUTER_STATUS_WAKEUP3_ST_Pos) /*!< EVENTROUTER STATUS: WAKEUP3_ST Mask */ #define EVENTROUTER_STATUS_ATIMER_ST_Pos 4 /*!< EVENTROUTER STATUS: ATIMER_ST Position */ #define EVENTROUTER_STATUS_ATIMER_ST_Msk (0x01UL << EVENTROUTER_STATUS_ATIMER_ST_Pos) /*!< EVENTROUTER STATUS: ATIMER_ST Mask */ #define EVENTROUTER_STATUS_RTC_ST_Pos 5 /*!< EVENTROUTER STATUS: RTC_ST Position */ #define EVENTROUTER_STATUS_RTC_ST_Msk (0x01UL << EVENTROUTER_STATUS_RTC_ST_Pos) /*!< EVENTROUTER STATUS: RTC_ST Mask */ #define EVENTROUTER_STATUS_BOD_ST_Pos 6 /*!< EVENTROUTER STATUS: BOD_ST Position */ #define EVENTROUTER_STATUS_BOD_ST_Msk (0x01UL << EVENTROUTER_STATUS_BOD_ST_Pos) /*!< EVENTROUTER STATUS: BOD_ST Mask */ #define EVENTROUTER_STATUS_WWDT_ST_Pos 7 /*!< EVENTROUTER STATUS: WWDT_ST Position */ #define EVENTROUTER_STATUS_WWDT_ST_Msk (0x01UL << EVENTROUTER_STATUS_WWDT_ST_Pos) /*!< EVENTROUTER STATUS: WWDT_ST Mask */ #define EVENTROUTER_STATUS_ETH_ST_Pos 8 /*!< EVENTROUTER STATUS: ETH_ST Position */ #define EVENTROUTER_STATUS_ETH_ST_Msk (0x01UL << EVENTROUTER_STATUS_ETH_ST_Pos) /*!< EVENTROUTER STATUS: ETH_ST Mask */ #define EVENTROUTER_STATUS_USB0_ST_Pos 9 /*!< EVENTROUTER STATUS: USB0_ST Position */ #define EVENTROUTER_STATUS_USB0_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB0_ST_Pos) /*!< EVENTROUTER STATUS: USB0_ST Mask */ #define EVENTROUTER_STATUS_USB1_ST_Pos 10 /*!< EVENTROUTER STATUS: USB1_ST Position */ #define EVENTROUTER_STATUS_USB1_ST_Msk (0x01UL << EVENTROUTER_STATUS_USB1_ST_Pos) /*!< EVENTROUTER STATUS: USB1_ST Mask */ #define EVENTROUTER_STATUS_SDMMC_ST_Pos 11 /*!< EVENTROUTER STATUS: SDMMC_ST Position */ #define EVENTROUTER_STATUS_SDMMC_ST_Msk (0x01UL << EVENTROUTER_STATUS_SDMMC_ST_Pos) /*!< EVENTROUTER STATUS: SDMMC_ST Mask */ #define EVENTROUTER_STATUS_CAN_ST_Pos 12 /*!< EVENTROUTER STATUS: CAN_ST Position */ #define EVENTROUTER_STATUS_CAN_ST_Msk (0x01UL << EVENTROUTER_STATUS_CAN_ST_Pos) /*!< EVENTROUTER STATUS: CAN_ST Mask */ #define EVENTROUTER_STATUS_TIM2_ST_Pos 13 /*!< EVENTROUTER STATUS: TIM2_ST Position */ #define EVENTROUTER_STATUS_TIM2_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM2_ST_Pos) /*!< EVENTROUTER STATUS: TIM2_ST Mask */ #define EVENTROUTER_STATUS_TIM6_ST_Pos 14 /*!< EVENTROUTER STATUS: TIM6_ST Position */ #define EVENTROUTER_STATUS_TIM6_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM6_ST_Pos) /*!< EVENTROUTER STATUS: TIM6_ST Mask */ #define EVENTROUTER_STATUS_QEI_ST_Pos 15 /*!< EVENTROUTER STATUS: QEI_ST Position */ #define EVENTROUTER_STATUS_QEI_ST_Msk (0x01UL << EVENTROUTER_STATUS_QEI_ST_Pos) /*!< EVENTROUTER STATUS: QEI_ST Mask */ #define EVENTROUTER_STATUS_TIM14_ST_Pos 16 /*!< EVENTROUTER STATUS: TIM14_ST Position */ #define EVENTROUTER_STATUS_TIM14_ST_Msk (0x01UL << EVENTROUTER_STATUS_TIM14_ST_Pos) /*!< EVENTROUTER STATUS: TIM14_ST Mask */ #define EVENTROUTER_STATUS_RESET_ST_Pos 19 /*!< EVENTROUTER STATUS: RESET_ST Position */ #define EVENTROUTER_STATUS_RESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_RESET_ST_Pos) /*!< EVENTROUTER STATUS: RESET_ST Mask */ #define EVENTROUTER_STATUS_BODRESET_ST_Pos 20 /*!< EVENTROUTER STATUS: BODRESET_ST Position */ #define EVENTROUTER_STATUS_BODRESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_BODRESET_ST_Pos) /*!< EVENTROUTER STATUS: BODRESET_ST Mask */ #define EVENTROUTER_STATUS_DPDRESET_ST_Pos 21 /*!< EVENTROUTER STATUS: DPDRESET_ST Position */ #define EVENTROUTER_STATUS_DPDRESET_ST_Msk (0x01UL << EVENTROUTER_STATUS_DPDRESET_ST_Pos) /*!< EVENTROUTER STATUS: DPDRESET_ST Mask */ /* ----------------------------- EVENTROUTER_ENABLE ----------------------------- */ #define EVENTROUTER_ENABLE_WAKEUP0_EN_Pos 0 /*!< EVENTROUTER ENABLE: WAKEUP0_EN Position */ #define EVENTROUTER_ENABLE_WAKEUP0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP0_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP0_EN Mask */ #define EVENTROUTER_ENABLE_WAKEUP1_EN_Pos 1 /*!< EVENTROUTER ENABLE: WAKEUP1_EN Position */ #define EVENTROUTER_ENABLE_WAKEUP1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP1_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP1_EN Mask */ #define EVENTROUTER_ENABLE_WAKEUP2_EN_Pos 2 /*!< EVENTROUTER ENABLE: WAKEUP2_EN Position */ #define EVENTROUTER_ENABLE_WAKEUP2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP2_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP2_EN Mask */ #define EVENTROUTER_ENABLE_WAKEUP3_EN_Pos 3 /*!< EVENTROUTER ENABLE: WAKEUP3_EN Position */ #define EVENTROUTER_ENABLE_WAKEUP3_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WAKEUP3_EN_Pos) /*!< EVENTROUTER ENABLE: WAKEUP3_EN Mask */ #define EVENTROUTER_ENABLE_ATIMER_EN_Pos 4 /*!< EVENTROUTER ENABLE: ATIMER_EN Position */ #define EVENTROUTER_ENABLE_ATIMER_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ATIMER_EN_Pos) /*!< EVENTROUTER ENABLE: ATIMER_EN Mask */ #define EVENTROUTER_ENABLE_RTC_EN_Pos 5 /*!< EVENTROUTER ENABLE: RTC_EN Position */ #define EVENTROUTER_ENABLE_RTC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RTC_EN_Pos) /*!< EVENTROUTER ENABLE: RTC_EN Mask */ #define EVENTROUTER_ENABLE_BOD_EN_Pos 6 /*!< EVENTROUTER ENABLE: BOD_EN Position */ #define EVENTROUTER_ENABLE_BOD_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BOD_EN_Pos) /*!< EVENTROUTER ENABLE: BOD_EN Mask */ #define EVENTROUTER_ENABLE_WWDT_EN_Pos 7 /*!< EVENTROUTER ENABLE: WWDT_EN Position */ #define EVENTROUTER_ENABLE_WWDT_EN_Msk (0x01UL << EVENTROUTER_ENABLE_WWDT_EN_Pos) /*!< EVENTROUTER ENABLE: WWDT_EN Mask */ #define EVENTROUTER_ENABLE_ETH_EN_Pos 8 /*!< EVENTROUTER ENABLE: ETH_EN Position */ #define EVENTROUTER_ENABLE_ETH_EN_Msk (0x01UL << EVENTROUTER_ENABLE_ETH_EN_Pos) /*!< EVENTROUTER ENABLE: ETH_EN Mask */ #define EVENTROUTER_ENABLE_USB0_EN_Pos 9 /*!< EVENTROUTER ENABLE: USB0_EN Position */ #define EVENTROUTER_ENABLE_USB0_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB0_EN_Pos) /*!< EVENTROUTER ENABLE: USB0_EN Mask */ #define EVENTROUTER_ENABLE_USB1_EN_Pos 10 /*!< EVENTROUTER ENABLE: USB1_EN Position */ #define EVENTROUTER_ENABLE_USB1_EN_Msk (0x01UL << EVENTROUTER_ENABLE_USB1_EN_Pos) /*!< EVENTROUTER ENABLE: USB1_EN Mask */ #define EVENTROUTER_ENABLE_SDMMC_EN_Pos 11 /*!< EVENTROUTER ENABLE: SDMMC_EN Position */ #define EVENTROUTER_ENABLE_SDMMC_EN_Msk (0x01UL << EVENTROUTER_ENABLE_SDMMC_EN_Pos) /*!< EVENTROUTER ENABLE: SDMMC_EN Mask */ #define EVENTROUTER_ENABLE_CAN_EN_Pos 12 /*!< EVENTROUTER ENABLE: CAN_EN Position */ #define EVENTROUTER_ENABLE_CAN_EN_Msk (0x01UL << EVENTROUTER_ENABLE_CAN_EN_Pos) /*!< EVENTROUTER ENABLE: CAN_EN Mask */ #define EVENTROUTER_ENABLE_TIM2_EN_Pos 13 /*!< EVENTROUTER ENABLE: TIM2_EN Position */ #define EVENTROUTER_ENABLE_TIM2_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM2_EN_Pos) /*!< EVENTROUTER ENABLE: TIM2_EN Mask */ #define EVENTROUTER_ENABLE_TIM6_EN_Pos 14 /*!< EVENTROUTER ENABLE: TIM6_EN Position */ #define EVENTROUTER_ENABLE_TIM6_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM6_EN_Pos) /*!< EVENTROUTER ENABLE: TIM6_EN Mask */ #define EVENTROUTER_ENABLE_QEI_EN_Pos 15 /*!< EVENTROUTER ENABLE: QEI_EN Position */ #define EVENTROUTER_ENABLE_QEI_EN_Msk (0x01UL << EVENTROUTER_ENABLE_QEI_EN_Pos) /*!< EVENTROUTER ENABLE: QEI_EN Mask */ #define EVENTROUTER_ENABLE_TIM14_EN_Pos 16 /*!< EVENTROUTER ENABLE: TIM14_EN Position */ #define EVENTROUTER_ENABLE_TIM14_EN_Msk (0x01UL << EVENTROUTER_ENABLE_TIM14_EN_Pos) /*!< EVENTROUTER ENABLE: TIM14_EN Mask */ #define EVENTROUTER_ENABLE_RESET_EN_Pos 19 /*!< EVENTROUTER ENABLE: RESET_EN Position */ #define EVENTROUTER_ENABLE_RESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_RESET_EN_Pos) /*!< EVENTROUTER ENABLE: RESET_EN Mask */ #define EVENTROUTER_ENABLE_BODRESET_EN_Pos 20 /*!< EVENTROUTER ENABLE: BODRESET_EN Position */ #define EVENTROUTER_ENABLE_BODRESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_BODRESET_EN_Pos) /*!< EVENTROUTER ENABLE: BODRESET_EN Mask */ #define EVENTROUTER_ENABLE_DPDRESET_EN_Pos 21 /*!< EVENTROUTER ENABLE: DPDRESET_EN Position */ #define EVENTROUTER_ENABLE_DPDRESET_EN_Msk (0x01UL << EVENTROUTER_ENABLE_DPDRESET_EN_Pos) /*!< EVENTROUTER ENABLE: DPDRESET_EN Mask */ /* ---------------------------- EVENTROUTER_CLR_STAT ---------------------------- */ #define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos 0 /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Position */ #define EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP0_CLRST Mask */ #define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos 1 /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Position */ #define EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP1_CLRST Mask */ #define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos 2 /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Position */ #define EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP2_CLRST Mask */ #define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos 3 /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Position */ #define EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WAKEUP3_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WAKEUP3_CLRST Mask */ #define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos 4 /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Position */ #define EVENTROUTER_CLR_STAT_ATIMER_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ATIMER_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ATIMER_CLRST Mask */ #define EVENTROUTER_CLR_STAT_RTC_CLRST_Pos 5 /*!< EVENTROUTER CLR_STAT: RTC_CLRST Position */ #define EVENTROUTER_CLR_STAT_RTC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RTC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RTC_CLRST Mask */ #define EVENTROUTER_CLR_STAT_BOD_CLRST_Pos 6 /*!< EVENTROUTER CLR_STAT: BOD_CLRST Position */ #define EVENTROUTER_CLR_STAT_BOD_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BOD_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BOD_CLRST Mask */ #define EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos 7 /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Position */ #define EVENTROUTER_CLR_STAT_WWDT_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_WWDT_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: WWDT_CLRST Mask */ #define EVENTROUTER_CLR_STAT_ETH_CLRST_Pos 8 /*!< EVENTROUTER CLR_STAT: ETH_CLRST Position */ #define EVENTROUTER_CLR_STAT_ETH_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_ETH_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: ETH_CLRST Mask */ #define EVENTROUTER_CLR_STAT_USB0_CLRST_Pos 9 /*!< EVENTROUTER CLR_STAT: USB0_CLRST Position */ #define EVENTROUTER_CLR_STAT_USB0_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB0_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB0_CLRST Mask */ #define EVENTROUTER_CLR_STAT_USB1_CLRST_Pos 10 /*!< EVENTROUTER CLR_STAT: USB1_CLRST Position */ #define EVENTROUTER_CLR_STAT_USB1_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_USB1_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: USB1_CLRST Mask */ #define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos 11 /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Position */ #define EVENTROUTER_CLR_STAT_SDMMC_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_SDMMC_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: SDMMC_CLRST Mask */ #define EVENTROUTER_CLR_STAT_CAN_CLRST_Pos 12 /*!< EVENTROUTER CLR_STAT: CAN_CLRST Position */ #define EVENTROUTER_CLR_STAT_CAN_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_CAN_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: CAN_CLRST Mask */ #define EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos 13 /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Position */ #define EVENTROUTER_CLR_STAT_TIM2_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM2_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM2_CLRST Mask */ #define EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos 14 /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Position */ #define EVENTROUTER_CLR_STAT_TIM6_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM6_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM6_CLRST Mask */ #define EVENTROUTER_CLR_STAT_QEI_CLRST_Pos 15 /*!< EVENTROUTER CLR_STAT: QEI_CLRST Position */ #define EVENTROUTER_CLR_STAT_QEI_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_QEI_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: QEI_CLRST Mask */ #define EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos 16 /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Position */ #define EVENTROUTER_CLR_STAT_TIM14_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_TIM14_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: TIM14_CLRST Mask */ #define EVENTROUTER_CLR_STAT_RESET_CLRST_Pos 19 /*!< EVENTROUTER CLR_STAT: RESET_CLRST Position */ #define EVENTROUTER_CLR_STAT_RESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_RESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: RESET_CLRST Mask */ #define EVENTROUTER_CLR_STAT_BODRESET_CLRST_Pos 20 /*!< EVENTROUTER CLR_STAT: BODRESET_CLRST Position */ #define EVENTROUTER_CLR_STAT_BODRESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_BODRESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: BODRESET_CLRST Mask */ #define EVENTROUTER_CLR_STAT_DPDRESET_CLRST_Pos 21 /*!< EVENTROUTER CLR_STAT: DPDRESET_CLRST Position */ #define EVENTROUTER_CLR_STAT_DPDRESET_CLRST_Msk (0x01UL << EVENTROUTER_CLR_STAT_DPDRESET_CLRST_Pos) /*!< EVENTROUTER CLR_STAT: DPDRESET_CLRST Mask */ /* ---------------------------- EVENTROUTER_SET_STAT ---------------------------- */ #define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos 0 /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Position */ #define EVENTROUTER_SET_STAT_WAKEUP0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP0_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP0_SETST Mask */ #define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos 1 /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Position */ #define EVENTROUTER_SET_STAT_WAKEUP1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP1_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP1_SETST Mask */ #define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos 2 /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Position */ #define EVENTROUTER_SET_STAT_WAKEUP2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP2_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP2_SETST Mask */ #define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos 3 /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Position */ #define EVENTROUTER_SET_STAT_WAKEUP3_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WAKEUP3_SETST_Pos) /*!< EVENTROUTER SET_STAT: WAKEUP3_SETST Mask */ #define EVENTROUTER_SET_STAT_ATIMER_SETST_Pos 4 /*!< EVENTROUTER SET_STAT: ATIMER_SETST Position */ #define EVENTROUTER_SET_STAT_ATIMER_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ATIMER_SETST_Pos) /*!< EVENTROUTER SET_STAT: ATIMER_SETST Mask */ #define EVENTROUTER_SET_STAT_RTC_SETST_Pos 5 /*!< EVENTROUTER SET_STAT: RTC_SETST Position */ #define EVENTROUTER_SET_STAT_RTC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RTC_SETST_Pos) /*!< EVENTROUTER SET_STAT: RTC_SETST Mask */ #define EVENTROUTER_SET_STAT_BOD_SETST_Pos 6 /*!< EVENTROUTER SET_STAT: BOD_SETST Position */ #define EVENTROUTER_SET_STAT_BOD_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BOD_SETST_Pos) /*!< EVENTROUTER SET_STAT: BOD_SETST Mask */ #define EVENTROUTER_SET_STAT_WWDT_SETST_Pos 7 /*!< EVENTROUTER SET_STAT: WWDT_SETST Position */ #define EVENTROUTER_SET_STAT_WWDT_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_WWDT_SETST_Pos) /*!< EVENTROUTER SET_STAT: WWDT_SETST Mask */ #define EVENTROUTER_SET_STAT_ETH_SETST_Pos 8 /*!< EVENTROUTER SET_STAT: ETH_SETST Position */ #define EVENTROUTER_SET_STAT_ETH_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_ETH_SETST_Pos) /*!< EVENTROUTER SET_STAT: ETH_SETST Mask */ #define EVENTROUTER_SET_STAT_USB0_SETST_Pos 9 /*!< EVENTROUTER SET_STAT: USB0_SETST Position */ #define EVENTROUTER_SET_STAT_USB0_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB0_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB0_SETST Mask */ #define EVENTROUTER_SET_STAT_USB1_SETST_Pos 10 /*!< EVENTROUTER SET_STAT: USB1_SETST Position */ #define EVENTROUTER_SET_STAT_USB1_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_USB1_SETST_Pos) /*!< EVENTROUTER SET_STAT: USB1_SETST Mask */ #define EVENTROUTER_SET_STAT_SDMMC_SETST_Pos 11 /*!< EVENTROUTER SET_STAT: SDMMC_SETST Position */ #define EVENTROUTER_SET_STAT_SDMMC_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_SDMMC_SETST_Pos) /*!< EVENTROUTER SET_STAT: SDMMC_SETST Mask */ #define EVENTROUTER_SET_STAT_CAN_SETST_Pos 12 /*!< EVENTROUTER SET_STAT: CAN_SETST Position */ #define EVENTROUTER_SET_STAT_CAN_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_CAN_SETST_Pos) /*!< EVENTROUTER SET_STAT: CAN_SETST Mask */ #define EVENTROUTER_SET_STAT_TIM2_SETST_Pos 13 /*!< EVENTROUTER SET_STAT: TIM2_SETST Position */ #define EVENTROUTER_SET_STAT_TIM2_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM2_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM2_SETST Mask */ #define EVENTROUTER_SET_STAT_TIM6_SETST_Pos 14 /*!< EVENTROUTER SET_STAT: TIM6_SETST Position */ #define EVENTROUTER_SET_STAT_TIM6_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM6_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM6_SETST Mask */ #define EVENTROUTER_SET_STAT_QEI_SETST_Pos 15 /*!< EVENTROUTER SET_STAT: QEI_SETST Position */ #define EVENTROUTER_SET_STAT_QEI_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_QEI_SETST_Pos) /*!< EVENTROUTER SET_STAT: QEI_SETST Mask */ #define EVENTROUTER_SET_STAT_TIM14_SETST_Pos 16 /*!< EVENTROUTER SET_STAT: TIM14_SETST Position */ #define EVENTROUTER_SET_STAT_TIM14_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_TIM14_SETST_Pos) /*!< EVENTROUTER SET_STAT: TIM14_SETST Mask */ #define EVENTROUTER_SET_STAT_RESET_SETST_Pos 19 /*!< EVENTROUTER SET_STAT: RESET_SETST Position */ #define EVENTROUTER_SET_STAT_RESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_RESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: RESET_SETST Mask */ #define EVENTROUTER_SET_STAT_BODRESET_SETST_Pos 20 /*!< EVENTROUTER SET_STAT: BODRESET_SETST Position */ #define EVENTROUTER_SET_STAT_BODRESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_BODRESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: BODRESET_SETST Mask */ #define EVENTROUTER_SET_STAT_DPDRESET_SETST_Pos 21 /*!< EVENTROUTER SET_STAT: DPDRESET_SETST Position */ #define EVENTROUTER_SET_STAT_DPDRESET_SETST_Msk (0x01UL << EVENTROUTER_SET_STAT_DPDRESET_SETST_Pos) /*!< EVENTROUTER SET_STAT: DPDRESET_SETST Mask */ /* ================================================================================ */ /* ================ struct 'RTC' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- RTC_ILR ---------------------------------- */ #define RTC_ILR_RTCCIF_Pos 0 /*!< RTC ILR: RTCCIF Position */ #define RTC_ILR_RTCCIF_Msk (0x01UL << RTC_ILR_RTCCIF_Pos) /*!< RTC ILR: RTCCIF Mask */ #define RTC_ILR_RTCALF_Pos 1 /*!< RTC ILR: RTCALF Position */ #define RTC_ILR_RTCALF_Msk (0x01UL << RTC_ILR_RTCALF_Pos) /*!< RTC ILR: RTCALF Mask */ /* ----------------------------------- RTC_CCR ---------------------------------- */ #define RTC_CCR_CLKEN_Pos 0 /*!< RTC CCR: CLKEN Position */ #define RTC_CCR_CLKEN_Msk (0x01UL << RTC_CCR_CLKEN_Pos) /*!< RTC CCR: CLKEN Mask */ #define RTC_CCR_CTCRST_Pos 1 /*!< RTC CCR: CTCRST Position */ #define RTC_CCR_CTCRST_Msk (0x01UL << RTC_CCR_CTCRST_Pos) /*!< RTC CCR: CTCRST Mask */ #define RTC_CCR_CCALEN_Pos 4 /*!< RTC CCR: CCALEN Position */ #define RTC_CCR_CCALEN_Msk (0x01UL << RTC_CCR_CCALEN_Pos) /*!< RTC CCR: CCALEN Mask */ /* ---------------------------------- RTC_CIIR ---------------------------------- */ #define RTC_CIIR_IMSEC_Pos 0 /*!< RTC CIIR: IMSEC Position */ #define RTC_CIIR_IMSEC_Msk (0x01UL << RTC_CIIR_IMSEC_Pos) /*!< RTC CIIR: IMSEC Mask */ #define RTC_CIIR_IMMIN_Pos 1 /*!< RTC CIIR: IMMIN Position */ #define RTC_CIIR_IMMIN_Msk (0x01UL << RTC_CIIR_IMMIN_Pos) /*!< RTC CIIR: IMMIN Mask */ #define RTC_CIIR_IMHOUR_Pos 2 /*!< RTC CIIR: IMHOUR Position */ #define RTC_CIIR_IMHOUR_Msk (0x01UL << RTC_CIIR_IMHOUR_Pos) /*!< RTC CIIR: IMHOUR Mask */ #define RTC_CIIR_IMDOM_Pos 3 /*!< RTC CIIR: IMDOM Position */ #define RTC_CIIR_IMDOM_Msk (0x01UL << RTC_CIIR_IMDOM_Pos) /*!< RTC CIIR: IMDOM Mask */ #define RTC_CIIR_IMDOW_Pos 4 /*!< RTC CIIR: IMDOW Position */ #define RTC_CIIR_IMDOW_Msk (0x01UL << RTC_CIIR_IMDOW_Pos) /*!< RTC CIIR: IMDOW Mask */ #define RTC_CIIR_IMDOY_Pos 5 /*!< RTC CIIR: IMDOY Position */ #define RTC_CIIR_IMDOY_Msk (0x01UL << RTC_CIIR_IMDOY_Pos) /*!< RTC CIIR: IMDOY Mask */ #define RTC_CIIR_IMMON_Pos 6 /*!< RTC CIIR: IMMON Position */ #define RTC_CIIR_IMMON_Msk (0x01UL << RTC_CIIR_IMMON_Pos) /*!< RTC CIIR: IMMON Mask */ #define RTC_CIIR_IMYEAR_Pos 7 /*!< RTC CIIR: IMYEAR Position */ #define RTC_CIIR_IMYEAR_Msk (0x01UL << RTC_CIIR_IMYEAR_Pos) /*!< RTC CIIR: IMYEAR Mask */ /* ----------------------------------- RTC_AMR ---------------------------------- */ #define RTC_AMR_AMRSEC_Pos 0 /*!< RTC AMR: AMRSEC Position */ #define RTC_AMR_AMRSEC_Msk (0x01UL << RTC_AMR_AMRSEC_Pos) /*!< RTC AMR: AMRSEC Mask */ #define RTC_AMR_AMRMIN_Pos 1 /*!< RTC AMR: AMRMIN Position */ #define RTC_AMR_AMRMIN_Msk (0x01UL << RTC_AMR_AMRMIN_Pos) /*!< RTC AMR: AMRMIN Mask */ #define RTC_AMR_AMRHOUR_Pos 2 /*!< RTC AMR: AMRHOUR Position */ #define RTC_AMR_AMRHOUR_Msk (0x01UL << RTC_AMR_AMRHOUR_Pos) /*!< RTC AMR: AMRHOUR Mask */ #define RTC_AMR_AMRDOM_Pos 3 /*!< RTC AMR: AMRDOM Position */ #define RTC_AMR_AMRDOM_Msk (0x01UL << RTC_AMR_AMRDOM_Pos) /*!< RTC AMR: AMRDOM Mask */ #define RTC_AMR_AMRDOW_Pos 4 /*!< RTC AMR: AMRDOW Position */ #define RTC_AMR_AMRDOW_Msk (0x01UL << RTC_AMR_AMRDOW_Pos) /*!< RTC AMR: AMRDOW Mask */ #define RTC_AMR_AMRDOY_Pos 5 /*!< RTC AMR: AMRDOY Position */ #define RTC_AMR_AMRDOY_Msk (0x01UL << RTC_AMR_AMRDOY_Pos) /*!< RTC AMR: AMRDOY Mask */ #define RTC_AMR_AMRMON_Pos 6 /*!< RTC AMR: AMRMON Position */ #define RTC_AMR_AMRMON_Msk (0x01UL << RTC_AMR_AMRMON_Pos) /*!< RTC AMR: AMRMON Mask */ #define RTC_AMR_AMRYEAR_Pos 7 /*!< RTC AMR: AMRYEAR Position */ #define RTC_AMR_AMRYEAR_Msk (0x01UL << RTC_AMR_AMRYEAR_Pos) /*!< RTC AMR: AMRYEAR Mask */ /* --------------------------------- RTC_CTIME0 --------------------------------- */ #define RTC_CTIME0_SECONDS_Pos 0 /*!< RTC CTIME0: SECONDS Position */ #define RTC_CTIME0_SECONDS_Msk (0x3fUL << RTC_CTIME0_SECONDS_Pos) /*!< RTC CTIME0: SECONDS Mask */ #define RTC_CTIME0_MINUTES_Pos 8 /*!< RTC CTIME0: MINUTES Position */ #define RTC_CTIME0_MINUTES_Msk (0x3fUL << RTC_CTIME0_MINUTES_Pos) /*!< RTC CTIME0: MINUTES Mask */ #define RTC_CTIME0_HOURS_Pos 16 /*!< RTC CTIME0: HOURS Position */ #define RTC_CTIME0_HOURS_Msk (0x1fUL << RTC_CTIME0_HOURS_Pos) /*!< RTC CTIME0: HOURS Mask */ #define RTC_CTIME0_DOW_Pos 24 /*!< RTC CTIME0: DOW Position */ #define RTC_CTIME0_DOW_Msk (0x07UL << RTC_CTIME0_DOW_Pos) /*!< RTC CTIME0: DOW Mask */ /* --------------------------------- RTC_CTIME1 --------------------------------- */ #define RTC_CTIME1_DOM_Pos 0 /*!< RTC CTIME1: DOM Position */ #define RTC_CTIME1_DOM_Msk (0x1fUL << RTC_CTIME1_DOM_Pos) /*!< RTC CTIME1: DOM Mask */ #define RTC_CTIME1_MONTH_Pos 8 /*!< RTC CTIME1: MONTH Position */ #define RTC_CTIME1_MONTH_Msk (0x0fUL << RTC_CTIME1_MONTH_Pos) /*!< RTC CTIME1: MONTH Mask */ #define RTC_CTIME1_YEAR_Pos 16 /*!< RTC CTIME1: YEAR Position */ #define RTC_CTIME1_YEAR_Msk (0x00000fffUL << RTC_CTIME1_YEAR_Pos) /*!< RTC CTIME1: YEAR Mask */ /* --------------------------------- RTC_CTIME2 --------------------------------- */ #define RTC_CTIME2_DOY_Pos 0 /*!< RTC CTIME2: DOY Position */ #define RTC_CTIME2_DOY_Msk (0x00000fffUL << RTC_CTIME2_DOY_Pos) /*!< RTC CTIME2: DOY Mask */ /* ----------------------------------- RTC_SEC ---------------------------------- */ #define RTC_SEC_SECONDS_Pos 0 /*!< RTC SEC: SECONDS Position */ #define RTC_SEC_SECONDS_Msk (0x3fUL << RTC_SEC_SECONDS_Pos) /*!< RTC SEC: SECONDS Mask */ /* ----------------------------------- RTC_MIN ---------------------------------- */ #define RTC_MIN_MINUTES_Pos 0 /*!< RTC MIN: MINUTES Position */ #define RTC_MIN_MINUTES_Msk (0x3fUL << RTC_MIN_MINUTES_Pos) /*!< RTC MIN: MINUTES Mask */ /* ----------------------------------- RTC_HRS ---------------------------------- */ #define RTC_HRS_HOURS_Pos 0 /*!< RTC HRS: HOURS Position */ #define RTC_HRS_HOURS_Msk (0x1fUL << RTC_HRS_HOURS_Pos) /*!< RTC HRS: HOURS Mask */ /* ----------------------------------- RTC_DOM ---------------------------------- */ #define RTC_DOM_DOM_Pos 0 /*!< RTC DOM: DOM Position */ #define RTC_DOM_DOM_Msk (0x1fUL << RTC_DOM_DOM_Pos) /*!< RTC DOM: DOM Mask */ /* ----------------------------------- RTC_DOW ---------------------------------- */ #define RTC_DOW_DOW_Pos 0 /*!< RTC DOW: DOW Position */ #define RTC_DOW_DOW_Msk (0x07UL << RTC_DOW_DOW_Pos) /*!< RTC DOW: DOW Mask */ /* ----------------------------------- RTC_DOY ---------------------------------- */ #define RTC_DOY_DOY_Pos 0 /*!< RTC DOY: DOY Position */ #define RTC_DOY_DOY_Msk (0x000001ffUL << RTC_DOY_DOY_Pos) /*!< RTC DOY: DOY Mask */ /* ---------------------------------- RTC_MONTH --------------------------------- */ #define RTC_MONTH_MONTH_Pos 0 /*!< RTC MONTH: MONTH Position */ #define RTC_MONTH_MONTH_Msk (0x0fUL << RTC_MONTH_MONTH_Pos) /*!< RTC MONTH: MONTH Mask */ /* ---------------------------------- RTC_YEAR ---------------------------------- */ #define RTC_YEAR_YEAR_Pos 0 /*!< RTC YEAR: YEAR Position */ #define RTC_YEAR_YEAR_Msk (0x00000fffUL << RTC_YEAR_YEAR_Pos) /*!< RTC YEAR: YEAR Mask */ /* ------------------------------- RTC_CALIBRATION ------------------------------ */ #define RTC_CALIBRATION_CALVAL_Pos 0 /*!< RTC CALIBRATION: CALVAL Position */ #define RTC_CALIBRATION_CALVAL_Msk (0x0001ffffUL << RTC_CALIBRATION_CALVAL_Pos) /*!< RTC CALIBRATION: CALVAL Mask */ #define RTC_CALIBRATION_CALDIR_Pos 17 /*!< RTC CALIBRATION: CALDIR Position */ #define RTC_CALIBRATION_CALDIR_Msk (0x01UL << RTC_CALIBRATION_CALDIR_Pos) /*!< RTC CALIBRATION: CALDIR Mask */ /* ---------------------------------- RTC_ASEC ---------------------------------- */ #define RTC_ASEC_SECONDS_Pos 0 /*!< RTC ASEC: SECONDS Position */ #define RTC_ASEC_SECONDS_Msk (0x3fUL << RTC_ASEC_SECONDS_Pos) /*!< RTC ASEC: SECONDS Mask */ /* ---------------------------------- RTC_AMIN ---------------------------------- */ #define RTC_AMIN_MINUTES_Pos 0 /*!< RTC AMIN: MINUTES Position */ #define RTC_AMIN_MINUTES_Msk (0x3fUL << RTC_AMIN_MINUTES_Pos) /*!< RTC AMIN: MINUTES Mask */ /* ---------------------------------- RTC_AHRS ---------------------------------- */ #define RTC_AHRS_HOURS_Pos 0 /*!< RTC AHRS: HOURS Position */ #define RTC_AHRS_HOURS_Msk (0x1fUL << RTC_AHRS_HOURS_Pos) /*!< RTC AHRS: HOURS Mask */ /* ---------------------------------- RTC_ADOM ---------------------------------- */ #define RTC_ADOM_DOM_Pos 0 /*!< RTC ADOM: DOM Position */ #define RTC_ADOM_DOM_Msk (0x1fUL << RTC_ADOM_DOM_Pos) /*!< RTC ADOM: DOM Mask */ /* ---------------------------------- RTC_ADOW ---------------------------------- */ #define RTC_ADOW_DOW_Pos 0 /*!< RTC ADOW: DOW Position */ #define RTC_ADOW_DOW_Msk (0x07UL << RTC_ADOW_DOW_Pos) /*!< RTC ADOW: DOW Mask */ /* ---------------------------------- RTC_ADOY ---------------------------------- */ #define RTC_ADOY_DOY_Pos 0 /*!< RTC ADOY: DOY Position */ #define RTC_ADOY_DOY_Msk (0x000001ffUL << RTC_ADOY_DOY_Pos) /*!< RTC ADOY: DOY Mask */ /* ---------------------------------- RTC_AMON ---------------------------------- */ #define RTC_AMON_MONTH_Pos 0 /*!< RTC AMON: MONTH Position */ #define RTC_AMON_MONTH_Msk (0x0fUL << RTC_AMON_MONTH_Pos) /*!< RTC AMON: MONTH Mask */ /* ---------------------------------- RTC_AYRS ---------------------------------- */ #define RTC_AYRS_YEAR_Pos 0 /*!< RTC AYRS: YEAR Position */ #define RTC_AYRS_YEAR_Msk (0x00000fffUL << RTC_AYRS_YEAR_Pos) /*!< RTC AYRS: YEAR Mask */ /* -------------------------------- RTC_ERSTATUS -------------------------------- */ #define RTC_ERSTATUS_EV0_Pos 0 /*!< RTC ERSTATUS: EV0 Position */ #define RTC_ERSTATUS_EV0_Msk (0x01UL << RTC_ERSTATUS_EV0_Pos) /*!< RTC ERSTATUS: EV0 Mask */ #define RTC_ERSTATUS_EV1_Pos 1 /*!< RTC ERSTATUS: EV1 Position */ #define RTC_ERSTATUS_EV1_Msk (0x01UL << RTC_ERSTATUS_EV1_Pos) /*!< RTC ERSTATUS: EV1 Mask */ #define RTC_ERSTATUS_EV2_Pos 2 /*!< RTC ERSTATUS: EV2 Position */ #define RTC_ERSTATUS_EV2_Msk (0x01UL << RTC_ERSTATUS_EV2_Pos) /*!< RTC ERSTATUS: EV2 Mask */ #define RTC_ERSTATUS_GP_CLEARED_Pos 3 /*!< RTC ERSTATUS: GP_CLEARED Position */ #define RTC_ERSTATUS_GP_CLEARED_Msk (0x01UL << RTC_ERSTATUS_GP_CLEARED_Pos) /*!< RTC ERSTATUS: GP_CLEARED Mask */ #define RTC_ERSTATUS_WAKEUP_Pos 31 /*!< RTC ERSTATUS: WAKEUP Position */ #define RTC_ERSTATUS_WAKEUP_Msk (0x01UL << RTC_ERSTATUS_WAKEUP_Pos) /*!< RTC ERSTATUS: WAKEUP Mask */ /* -------------------------------- RTC_ERCONTRO -------------------------------- */ #define RTC_ERCONTRO_INTWAKE_EN0_Pos 0 /*!< RTC ERCONTRO: INTWAKE_EN0 Position */ #define RTC_ERCONTRO_INTWAKE_EN0_Msk (0x01UL << RTC_ERCONTRO_INTWAKE_EN0_Pos) /*!< RTC ERCONTRO: INTWAKE_EN0 Mask */ #define RTC_ERCONTRO_GPCLEAR_EN0_Pos 1 /*!< RTC ERCONTRO: GPCLEAR_EN0 Position */ #define RTC_ERCONTRO_GPCLEAR_EN0_Msk (0x01UL << RTC_ERCONTRO_GPCLEAR_EN0_Pos) /*!< RTC ERCONTRO: GPCLEAR_EN0 Mask */ #define RTC_ERCONTRO_POL0_Pos 2 /*!< RTC ERCONTRO: POL0 Position */ #define RTC_ERCONTRO_POL0_Msk (0x01UL << RTC_ERCONTRO_POL0_Pos) /*!< RTC ERCONTRO: POL0 Mask */ #define RTC_ERCONTRO_EV0_INPUT_EN_Pos 3 /*!< RTC ERCONTRO: EV0_INPUT_EN Position */ #define RTC_ERCONTRO_EV0_INPUT_EN_Msk (0x01UL << RTC_ERCONTRO_EV0_INPUT_EN_Pos) /*!< RTC ERCONTRO: EV0_INPUT_EN Mask */ #define RTC_ERCONTRO_INTWAKE_EN1_Pos 10 /*!< RTC ERCONTRO: INTWAKE_EN1 Position */ #define RTC_ERCONTRO_INTWAKE_EN1_Msk (0x01UL << RTC_ERCONTRO_INTWAKE_EN1_Pos) /*!< RTC ERCONTRO: INTWAKE_EN1 Mask */ #define RTC_ERCONTRO_GPCLEAR_EN1_Pos 11 /*!< RTC ERCONTRO: GPCLEAR_EN1 Position */ #define RTC_ERCONTRO_GPCLEAR_EN1_Msk (0x01UL << RTC_ERCONTRO_GPCLEAR_EN1_Pos) /*!< RTC ERCONTRO: GPCLEAR_EN1 Mask */ #define RTC_ERCONTRO_POL1_Pos 12 /*!< RTC ERCONTRO: POL1 Position */ #define RTC_ERCONTRO_POL1_Msk (0x01UL << RTC_ERCONTRO_POL1_Pos) /*!< RTC ERCONTRO: POL1 Mask */ #define RTC_ERCONTRO_EV1_INPUT_EN_Pos 13 /*!< RTC ERCONTRO: EV1_INPUT_EN Position */ #define RTC_ERCONTRO_EV1_INPUT_EN_Msk (0x01UL << RTC_ERCONTRO_EV1_INPUT_EN_Pos) /*!< RTC ERCONTRO: EV1_INPUT_EN Mask */ #define RTC_ERCONTRO_INTWAKE_EN2_Pos 20 /*!< RTC ERCONTRO: INTWAKE_EN2 Position */ #define RTC_ERCONTRO_INTWAKE_EN2_Msk (0x01UL << RTC_ERCONTRO_INTWAKE_EN2_Pos) /*!< RTC ERCONTRO: INTWAKE_EN2 Mask */ #define RTC_ERCONTRO_GPCLEAR_EN2_Pos 21 /*!< RTC ERCONTRO: GPCLEAR_EN2 Position */ #define RTC_ERCONTRO_GPCLEAR_EN2_Msk (0x01UL << RTC_ERCONTRO_GPCLEAR_EN2_Pos) /*!< RTC ERCONTRO: GPCLEAR_EN2 Mask */ #define RTC_ERCONTRO_POL2_Pos 22 /*!< RTC ERCONTRO: POL2 Position */ #define RTC_ERCONTRO_POL2_Msk (0x01UL << RTC_ERCONTRO_POL2_Pos) /*!< RTC ERCONTRO: POL2 Mask */ #define RTC_ERCONTRO_EV2_INPUT_EN_Pos 23 /*!< RTC ERCONTRO: EV2_INPUT_EN Position */ #define RTC_ERCONTRO_EV2_INPUT_EN_Msk (0x01UL << RTC_ERCONTRO_EV2_INPUT_EN_Pos) /*!< RTC ERCONTRO: EV2_INPUT_EN Mask */ #define RTC_ERCONTRO_ERMODE_Pos 30 /*!< RTC ERCONTRO: ERMODE Position */ #define RTC_ERCONTRO_ERMODE_Msk (0x03UL << RTC_ERCONTRO_ERMODE_Pos) /*!< RTC ERCONTRO: ERMODE Mask */ /* ------------------------------- RTC_ERCOUNTERS ------------------------------- */ #define RTC_ERCOUNTERS_COUNTER0_Pos 0 /*!< RTC ERCOUNTERS: COUNTER0 Position */ #define RTC_ERCOUNTERS_COUNTER0_Msk (0x07UL << RTC_ERCOUNTERS_COUNTER0_Pos) /*!< RTC ERCOUNTERS: COUNTER0 Mask */ #define RTC_ERCOUNTERS_COUNTER1_Pos 8 /*!< RTC ERCOUNTERS: COUNTER1 Position */ #define RTC_ERCOUNTERS_COUNTER1_Msk (0x07UL << RTC_ERCOUNTERS_COUNTER1_Pos) /*!< RTC ERCOUNTERS: COUNTER1 Mask */ #define RTC_ERCOUNTERS_COUNTER2_Pos 16 /*!< RTC ERCOUNTERS: COUNTER2 Position */ #define RTC_ERCOUNTERS_COUNTER2_Msk (0x07UL << RTC_ERCOUNTERS_COUNTER2_Pos) /*!< RTC ERCOUNTERS: COUNTER2 Mask */ /* ------------------------------ RTC_ERFIRSTSTAMP0 ----------------------------- */ #define RTC_ERFIRSTSTAMP0_SEC_Pos 0 /*!< RTC ERFIRSTSTAMP0: SEC Position */ #define RTC_ERFIRSTSTAMP0_SEC_Msk (0x3fUL << RTC_ERFIRSTSTAMP0_SEC_Pos) /*!< RTC ERFIRSTSTAMP0: SEC Mask */ #define RTC_ERFIRSTSTAMP0_MIN_Pos 6 /*!< RTC ERFIRSTSTAMP0: MIN Position */ #define RTC_ERFIRSTSTAMP0_MIN_Msk (0x3fUL << RTC_ERFIRSTSTAMP0_MIN_Pos) /*!< RTC ERFIRSTSTAMP0: MIN Mask */ #define RTC_ERFIRSTSTAMP0_HOUR_Pos 12 /*!< RTC ERFIRSTSTAMP0: HOUR Position */ #define RTC_ERFIRSTSTAMP0_HOUR_Msk (0x1fUL << RTC_ERFIRSTSTAMP0_HOUR_Pos) /*!< RTC ERFIRSTSTAMP0: HOUR Mask */ #define RTC_ERFIRSTSTAMP0_DOY_Pos 17 /*!< RTC ERFIRSTSTAMP0: DOY Position */ #define RTC_ERFIRSTSTAMP0_DOY_Msk (0x000001ffUL << RTC_ERFIRSTSTAMP0_DOY_Pos) /*!< RTC ERFIRSTSTAMP0: DOY Mask */ /* ------------------------------ RTC_ERFIRSTSTAMP1 ----------------------------- */ #define RTC_ERFIRSTSTAMP1_SEC_Pos 0 /*!< RTC ERFIRSTSTAMP1: SEC Position */ #define RTC_ERFIRSTSTAMP1_SEC_Msk (0x3fUL << RTC_ERFIRSTSTAMP1_SEC_Pos) /*!< RTC ERFIRSTSTAMP1: SEC Mask */ #define RTC_ERFIRSTSTAMP1_MIN_Pos 6 /*!< RTC ERFIRSTSTAMP1: MIN Position */ #define RTC_ERFIRSTSTAMP1_MIN_Msk (0x3fUL << RTC_ERFIRSTSTAMP1_MIN_Pos) /*!< RTC ERFIRSTSTAMP1: MIN Mask */ #define RTC_ERFIRSTSTAMP1_HOUR_Pos 12 /*!< RTC ERFIRSTSTAMP1: HOUR Position */ #define RTC_ERFIRSTSTAMP1_HOUR_Msk (0x1fUL << RTC_ERFIRSTSTAMP1_HOUR_Pos) /*!< RTC ERFIRSTSTAMP1: HOUR Mask */ #define RTC_ERFIRSTSTAMP1_DOY_Pos 17 /*!< RTC ERFIRSTSTAMP1: DOY Position */ #define RTC_ERFIRSTSTAMP1_DOY_Msk (0x000001ffUL << RTC_ERFIRSTSTAMP1_DOY_Pos) /*!< RTC ERFIRSTSTAMP1: DOY Mask */ /* ------------------------------ RTC_ERFIRSTSTAMP2 ----------------------------- */ #define RTC_ERFIRSTSTAMP2_SEC_Pos 0 /*!< RTC ERFIRSTSTAMP2: SEC Position */ #define RTC_ERFIRSTSTAMP2_SEC_Msk (0x3fUL << RTC_ERFIRSTSTAMP2_SEC_Pos) /*!< RTC ERFIRSTSTAMP2: SEC Mask */ #define RTC_ERFIRSTSTAMP2_MIN_Pos 6 /*!< RTC ERFIRSTSTAMP2: MIN Position */ #define RTC_ERFIRSTSTAMP2_MIN_Msk (0x3fUL << RTC_ERFIRSTSTAMP2_MIN_Pos) /*!< RTC ERFIRSTSTAMP2: MIN Mask */ #define RTC_ERFIRSTSTAMP2_HOUR_Pos 12 /*!< RTC ERFIRSTSTAMP2: HOUR Position */ #define RTC_ERFIRSTSTAMP2_HOUR_Msk (0x1fUL << RTC_ERFIRSTSTAMP2_HOUR_Pos) /*!< RTC ERFIRSTSTAMP2: HOUR Mask */ #define RTC_ERFIRSTSTAMP2_DOY_Pos 17 /*!< RTC ERFIRSTSTAMP2: DOY Position */ #define RTC_ERFIRSTSTAMP2_DOY_Msk (0x000001ffUL << RTC_ERFIRSTSTAMP2_DOY_Pos) /*!< RTC ERFIRSTSTAMP2: DOY Mask */ /* ------------------------------ RTC_ERLASTSTAMP0 ------------------------------ */ #define RTC_ERLASTSTAMP0_SEC_Pos 0 /*!< RTC ERLASTSTAMP0: SEC Position */ #define RTC_ERLASTSTAMP0_SEC_Msk (0x3fUL << RTC_ERLASTSTAMP0_SEC_Pos) /*!< RTC ERLASTSTAMP0: SEC Mask */ #define RTC_ERLASTSTAMP0_MIN_Pos 6 /*!< RTC ERLASTSTAMP0: MIN Position */ #define RTC_ERLASTSTAMP0_MIN_Msk (0x3fUL << RTC_ERLASTSTAMP0_MIN_Pos) /*!< RTC ERLASTSTAMP0: MIN Mask */ #define RTC_ERLASTSTAMP0_HOUR_Pos 12 /*!< RTC ERLASTSTAMP0: HOUR Position */ #define RTC_ERLASTSTAMP0_HOUR_Msk (0x1fUL << RTC_ERLASTSTAMP0_HOUR_Pos) /*!< RTC ERLASTSTAMP0: HOUR Mask */ #define RTC_ERLASTSTAMP0_DOY_Pos 17 /*!< RTC ERLASTSTAMP0: DOY Position */ #define RTC_ERLASTSTAMP0_DOY_Msk (0x000001ffUL << RTC_ERLASTSTAMP0_DOY_Pos) /*!< RTC ERLASTSTAMP0: DOY Mask */ /* ------------------------------ RTC_ERLASTSTAMP1 ------------------------------ */ #define RTC_ERLASTSTAMP1_SEC_Pos 0 /*!< RTC ERLASTSTAMP1: SEC Position */ #define RTC_ERLASTSTAMP1_SEC_Msk (0x3fUL << RTC_ERLASTSTAMP1_SEC_Pos) /*!< RTC ERLASTSTAMP1: SEC Mask */ #define RTC_ERLASTSTAMP1_MIN_Pos 6 /*!< RTC ERLASTSTAMP1: MIN Position */ #define RTC_ERLASTSTAMP1_MIN_Msk (0x3fUL << RTC_ERLASTSTAMP1_MIN_Pos) /*!< RTC ERLASTSTAMP1: MIN Mask */ #define RTC_ERLASTSTAMP1_HOUR_Pos 12 /*!< RTC ERLASTSTAMP1: HOUR Position */ #define RTC_ERLASTSTAMP1_HOUR_Msk (0x1fUL << RTC_ERLASTSTAMP1_HOUR_Pos) /*!< RTC ERLASTSTAMP1: HOUR Mask */ #define RTC_ERLASTSTAMP1_DOY_Pos 17 /*!< RTC ERLASTSTAMP1: DOY Position */ #define RTC_ERLASTSTAMP1_DOY_Msk (0x000001ffUL << RTC_ERLASTSTAMP1_DOY_Pos) /*!< RTC ERLASTSTAMP1: DOY Mask */ /* ------------------------------ RTC_ERLASTSTAMP2 ------------------------------ */ #define RTC_ERLASTSTAMP2_SEC_Pos 0 /*!< RTC ERLASTSTAMP2: SEC Position */ #define RTC_ERLASTSTAMP2_SEC_Msk (0x3fUL << RTC_ERLASTSTAMP2_SEC_Pos) /*!< RTC ERLASTSTAMP2: SEC Mask */ #define RTC_ERLASTSTAMP2_MIN_Pos 6 /*!< RTC ERLASTSTAMP2: MIN Position */ #define RTC_ERLASTSTAMP2_MIN_Msk (0x3fUL << RTC_ERLASTSTAMP2_MIN_Pos) /*!< RTC ERLASTSTAMP2: MIN Mask */ #define RTC_ERLASTSTAMP2_HOUR_Pos 12 /*!< RTC ERLASTSTAMP2: HOUR Position */ #define RTC_ERLASTSTAMP2_HOUR_Msk (0x1fUL << RTC_ERLASTSTAMP2_HOUR_Pos) /*!< RTC ERLASTSTAMP2: HOUR Mask */ #define RTC_ERLASTSTAMP2_DOY_Pos 17 /*!< RTC ERLASTSTAMP2: DOY Position */ #define RTC_ERLASTSTAMP2_DOY_Msk (0x000001ffUL << RTC_ERLASTSTAMP2_DOY_Pos) /*!< RTC ERLASTSTAMP2: DOY Mask */ /* ================================================================================ */ /* ================ struct 'CGU' Position & Mask ================ */ /* ================================================================================ */ /* -------------------------------- CGU_FREQ_MON -------------------------------- */ #define CGU_FREQ_MON_RCNT_Pos 0 /*!< CGU FREQ_MON: RCNT Position */ #define CGU_FREQ_MON_RCNT_Msk (0x000001ffUL << CGU_FREQ_MON_RCNT_Pos) /*!< CGU FREQ_MON: RCNT Mask */ #define CGU_FREQ_MON_FCNT_Pos 9 /*!< CGU FREQ_MON: FCNT Position */ #define CGU_FREQ_MON_FCNT_Msk (0x00003fffUL << CGU_FREQ_MON_FCNT_Pos) /*!< CGU FREQ_MON: FCNT Mask */ #define CGU_FREQ_MON_MEAS_Pos 23 /*!< CGU FREQ_MON: MEAS Position */ #define CGU_FREQ_MON_MEAS_Msk (0x01UL << CGU_FREQ_MON_MEAS_Pos) /*!< CGU FREQ_MON: MEAS Mask */ #define CGU_FREQ_MON_CLK_SEL_Pos 24 /*!< CGU FREQ_MON: CLK_SEL Position */ #define CGU_FREQ_MON_CLK_SEL_Msk (0x1fUL << CGU_FREQ_MON_CLK_SEL_Pos) /*!< CGU FREQ_MON: CLK_SEL Mask */ /* ------------------------------ CGU_XTAL_OSC_CTRL ----------------------------- */ #define CGU_XTAL_OSC_CTRL_ENABLE_Pos 0 /*!< CGU XTAL_OSC_CTRL: ENABLE Position */ #define CGU_XTAL_OSC_CTRL_ENABLE_Msk (0x01UL << CGU_XTAL_OSC_CTRL_ENABLE_Pos) /*!< CGU XTAL_OSC_CTRL: ENABLE Mask */ #define CGU_XTAL_OSC_CTRL_BYPASS_Pos 1 /*!< CGU XTAL_OSC_CTRL: BYPASS Position */ #define CGU_XTAL_OSC_CTRL_BYPASS_Msk (0x01UL << CGU_XTAL_OSC_CTRL_BYPASS_Pos) /*!< CGU XTAL_OSC_CTRL: BYPASS Mask */ #define CGU_XTAL_OSC_CTRL_HF_Pos 2 /*!< CGU XTAL_OSC_CTRL: HF Position */ #define CGU_XTAL_OSC_CTRL_HF_Msk (0x01UL << CGU_XTAL_OSC_CTRL_HF_Pos) /*!< CGU XTAL_OSC_CTRL: HF Mask */ /* ------------------------------ CGU_PLL0USB_STAT ------------------------------ */ #define CGU_PLL0USB_STAT_LOCK_Pos 0 /*!< CGU PLL0USB_STAT: LOCK Position */ #define CGU_PLL0USB_STAT_LOCK_Msk (0x01UL << CGU_PLL0USB_STAT_LOCK_Pos) /*!< CGU PLL0USB_STAT: LOCK Mask */ #define CGU_PLL0USB_STAT_FR_Pos 1 /*!< CGU PLL0USB_STAT: FR Position */ #define CGU_PLL0USB_STAT_FR_Msk (0x01UL << CGU_PLL0USB_STAT_FR_Pos) /*!< CGU PLL0USB_STAT: FR Mask */ /* ------------------------------ CGU_PLL0USB_CTRL ------------------------------ */ #define CGU_PLL0USB_CTRL_PD_Pos 0 /*!< CGU PLL0USB_CTRL: PD Position */ #define CGU_PLL0USB_CTRL_PD_Msk (0x01UL << CGU_PLL0USB_CTRL_PD_Pos) /*!< CGU PLL0USB_CTRL: PD Mask */ #define CGU_PLL0USB_CTRL_BYPASS_Pos 1 /*!< CGU PLL0USB_CTRL: BYPASS Position */ #define CGU_PLL0USB_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0USB_CTRL_BYPASS_Pos) /*!< CGU PLL0USB_CTRL: BYPASS Mask */ #define CGU_PLL0USB_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0USB_CTRL: DIRECTI Position */ #define CGU_PLL0USB_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTI_Pos) /*!< CGU PLL0USB_CTRL: DIRECTI Mask */ #define CGU_PLL0USB_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0USB_CTRL: DIRECTO Position */ #define CGU_PLL0USB_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0USB_CTRL_DIRECTO_Pos) /*!< CGU PLL0USB_CTRL: DIRECTO Mask */ #define CGU_PLL0USB_CTRL_CLKEN_Pos 4 /*!< CGU PLL0USB_CTRL: CLKEN Position */ #define CGU_PLL0USB_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0USB_CTRL_CLKEN_Pos) /*!< CGU PLL0USB_CTRL: CLKEN Mask */ #define CGU_PLL0USB_CTRL_FRM_Pos 6 /*!< CGU PLL0USB_CTRL: FRM Position */ #define CGU_PLL0USB_CTRL_FRM_Msk (0x01UL << CGU_PLL0USB_CTRL_FRM_Pos) /*!< CGU PLL0USB_CTRL: FRM Mask */ #define CGU_PLL0USB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0USB_CTRL: AUTOBLOCK Position */ #define CGU_PLL0USB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0USB_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0USB_CTRL: AUTOBLOCK Mask */ #define CGU_PLL0USB_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0USB_CTRL: CLK_SEL Position */ #define CGU_PLL0USB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0USB_CTRL_CLK_SEL_Pos) /*!< CGU PLL0USB_CTRL: CLK_SEL Mask */ /* ------------------------------ CGU_PLL0USB_MDIV ------------------------------ */ #define CGU_PLL0USB_MDIV_MDEC_Pos 0 /*!< CGU PLL0USB_MDIV: MDEC Position */ #define CGU_PLL0USB_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0USB_MDIV_MDEC_Pos) /*!< CGU PLL0USB_MDIV: MDEC Mask */ #define CGU_PLL0USB_MDIV_SELP_Pos 17 /*!< CGU PLL0USB_MDIV: SELP Position */ #define CGU_PLL0USB_MDIV_SELP_Msk (0x1fUL << CGU_PLL0USB_MDIV_SELP_Pos) /*!< CGU PLL0USB_MDIV: SELP Mask */ #define CGU_PLL0USB_MDIV_SELI_Pos 22 /*!< CGU PLL0USB_MDIV: SELI Position */ #define CGU_PLL0USB_MDIV_SELI_Msk (0x3fUL << CGU_PLL0USB_MDIV_SELI_Pos) /*!< CGU PLL0USB_MDIV: SELI Mask */ #define CGU_PLL0USB_MDIV_SELR_Pos 28 /*!< CGU PLL0USB_MDIV: SELR Position */ #define CGU_PLL0USB_MDIV_SELR_Msk (0x0fUL << CGU_PLL0USB_MDIV_SELR_Pos) /*!< CGU PLL0USB_MDIV: SELR Mask */ /* ----------------------------- CGU_PLL0USB_NP_DIV ----------------------------- */ #define CGU_PLL0USB_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0USB_NP_DIV: PDEC Position */ #define CGU_PLL0USB_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0USB_NP_DIV_PDEC_Pos) /*!< CGU PLL0USB_NP_DIV: PDEC Mask */ #define CGU_PLL0USB_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0USB_NP_DIV: NDEC Position */ #define CGU_PLL0USB_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0USB_NP_DIV_NDEC_Pos) /*!< CGU PLL0USB_NP_DIV: NDEC Mask */ /* ----------------------------- CGU_PLL0AUDIO_STAT ----------------------------- */ #define CGU_PLL0AUDIO_STAT_LOCK_Pos 0 /*!< CGU PLL0AUDIO_STAT: LOCK Position */ #define CGU_PLL0AUDIO_STAT_LOCK_Msk (0x01UL << CGU_PLL0AUDIO_STAT_LOCK_Pos) /*!< CGU PLL0AUDIO_STAT: LOCK Mask */ #define CGU_PLL0AUDIO_STAT_FR_Pos 1 /*!< CGU PLL0AUDIO_STAT: FR Position */ #define CGU_PLL0AUDIO_STAT_FR_Msk (0x01UL << CGU_PLL0AUDIO_STAT_FR_Pos) /*!< CGU PLL0AUDIO_STAT: FR Mask */ /* ----------------------------- CGU_PLL0AUDIO_CTRL ----------------------------- */ #define CGU_PLL0AUDIO_CTRL_PD_Pos 0 /*!< CGU PLL0AUDIO_CTRL: PD Position */ #define CGU_PLL0AUDIO_CTRL_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: PD Mask */ #define CGU_PLL0AUDIO_CTRL_BYPASS_Pos 1 /*!< CGU PLL0AUDIO_CTRL: BYPASS Position */ #define CGU_PLL0AUDIO_CTRL_BYPASS_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_BYPASS_Pos) /*!< CGU PLL0AUDIO_CTRL: BYPASS Mask */ #define CGU_PLL0AUDIO_CTRL_DIRECTI_Pos 2 /*!< CGU PLL0AUDIO_CTRL: DIRECTI Position */ #define CGU_PLL0AUDIO_CTRL_DIRECTI_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTI_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTI Mask */ #define CGU_PLL0AUDIO_CTRL_DIRECTO_Pos 3 /*!< CGU PLL0AUDIO_CTRL: DIRECTO Position */ #define CGU_PLL0AUDIO_CTRL_DIRECTO_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_DIRECTO_Pos) /*!< CGU PLL0AUDIO_CTRL: DIRECTO Mask */ #define CGU_PLL0AUDIO_CTRL_CLKEN_Pos 4 /*!< CGU PLL0AUDIO_CTRL: CLKEN Position */ #define CGU_PLL0AUDIO_CTRL_CLKEN_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_CLKEN_Pos) /*!< CGU PLL0AUDIO_CTRL: CLKEN Mask */ #define CGU_PLL0AUDIO_CTRL_FRM_Pos 6 /*!< CGU PLL0AUDIO_CTRL: FRM Position */ #define CGU_PLL0AUDIO_CTRL_FRM_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_FRM_Pos) /*!< CGU PLL0AUDIO_CTRL: FRM Mask */ #define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Position */ #define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL0AUDIO_CTRL: AUTOBLOCK Mask */ #define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_Pos 12 /*!< CGU PLL0AUDIO_CTRL: PLLFRACT_REQ Position */ #define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_Pos) /*!< CGU PLL0AUDIO_CTRL: PLLFRACT_REQ Mask */ #define CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos 13 /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Position */ #define CGU_PLL0AUDIO_CTRL_SEL_EXT_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_SEL_EXT_Pos) /*!< CGU PLL0AUDIO_CTRL: SEL_EXT Mask */ #define CGU_PLL0AUDIO_CTRL_MOD_PD_Pos 14 /*!< CGU PLL0AUDIO_CTRL: MOD_PD Position */ #define CGU_PLL0AUDIO_CTRL_MOD_PD_Msk (0x01UL << CGU_PLL0AUDIO_CTRL_MOD_PD_Pos) /*!< CGU PLL0AUDIO_CTRL: MOD_PD Mask */ #define CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Position */ #define CGU_PLL0AUDIO_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL0AUDIO_CTRL_CLK_SEL_Pos) /*!< CGU PLL0AUDIO_CTRL: CLK_SEL Mask */ /* ----------------------------- CGU_PLL0AUDIO_MDIV ----------------------------- */ #define CGU_PLL0AUDIO_MDIV_MDEC_Pos 0 /*!< CGU PLL0AUDIO_MDIV: MDEC Position */ #define CGU_PLL0AUDIO_MDIV_MDEC_Msk (0x0001ffffUL << CGU_PLL0AUDIO_MDIV_MDEC_Pos) /*!< CGU PLL0AUDIO_MDIV: MDEC Mask */ /* ---------------------------- CGU_PLL0AUDIO_NP_DIV ---------------------------- */ #define CGU_PLL0AUDIO_NP_DIV_PDEC_Pos 0 /*!< CGU PLL0AUDIO_NP_DIV: PDEC Position */ #define CGU_PLL0AUDIO_NP_DIV_PDEC_Msk (0x7fUL << CGU_PLL0AUDIO_NP_DIV_PDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: PDEC Mask */ #define CGU_PLL0AUDIO_NP_DIV_NDEC_Pos 12 /*!< CGU PLL0AUDIO_NP_DIV: NDEC Position */ #define CGU_PLL0AUDIO_NP_DIV_NDEC_Msk (0x000003ffUL << CGU_PLL0AUDIO_NP_DIV_NDEC_Pos) /*!< CGU PLL0AUDIO_NP_DIV: NDEC Mask */ /* ----------------------------- CGU_PLL0AUDIO_FRAC ----------------------------- */ #define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos 0 /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Position */ #define CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Msk (0x003fffffUL << CGU_PLL0AUDIO_FRAC_PLLFRACT_CTRL_Pos) /*!< CGU PLL0AUDIO_FRAC: PLLFRACT_CTRL Mask */ /* -------------------------------- CGU_PLL1_STAT ------------------------------- */ #define CGU_PLL1_STAT_LOCK_Pos 0 /*!< CGU PLL1_STAT: LOCK Position */ #define CGU_PLL1_STAT_LOCK_Msk (0x01UL << CGU_PLL1_STAT_LOCK_Pos) /*!< CGU PLL1_STAT: LOCK Mask */ /* -------------------------------- CGU_PLL1_CTRL ------------------------------- */ #define CGU_PLL1_CTRL_PD_Pos 0 /*!< CGU PLL1_CTRL: PD Position */ #define CGU_PLL1_CTRL_PD_Msk (0x01UL << CGU_PLL1_CTRL_PD_Pos) /*!< CGU PLL1_CTRL: PD Mask */ #define CGU_PLL1_CTRL_BYPASS_Pos 1 /*!< CGU PLL1_CTRL: BYPASS Position */ #define CGU_PLL1_CTRL_BYPASS_Msk (0x01UL << CGU_PLL1_CTRL_BYPASS_Pos) /*!< CGU PLL1_CTRL: BYPASS Mask */ #define CGU_PLL1_CTRL_FBSEL_Pos 6 /*!< CGU PLL1_CTRL: FBSEL Position */ #define CGU_PLL1_CTRL_FBSEL_Msk (0x01UL << CGU_PLL1_CTRL_FBSEL_Pos) /*!< CGU PLL1_CTRL: FBSEL Mask */ #define CGU_PLL1_CTRL_DIRECT_Pos 7 /*!< CGU PLL1_CTRL: DIRECT Position */ #define CGU_PLL1_CTRL_DIRECT_Msk (0x01UL << CGU_PLL1_CTRL_DIRECT_Pos) /*!< CGU PLL1_CTRL: DIRECT Mask */ #define CGU_PLL1_CTRL_PSEL_Pos 8 /*!< CGU PLL1_CTRL: PSEL Position */ #define CGU_PLL1_CTRL_PSEL_Msk (0x03UL << CGU_PLL1_CTRL_PSEL_Pos) /*!< CGU PLL1_CTRL: PSEL Mask */ #define CGU_PLL1_CTRL_AUTOBLOCK_Pos 11 /*!< CGU PLL1_CTRL: AUTOBLOCK Position */ #define CGU_PLL1_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_PLL1_CTRL_AUTOBLOCK_Pos) /*!< CGU PLL1_CTRL: AUTOBLOCK Mask */ #define CGU_PLL1_CTRL_NSEL_Pos 12 /*!< CGU PLL1_CTRL: NSEL Position */ #define CGU_PLL1_CTRL_NSEL_Msk (0x03UL << CGU_PLL1_CTRL_NSEL_Pos) /*!< CGU PLL1_CTRL: NSEL Mask */ #define CGU_PLL1_CTRL_MSEL_Pos 16 /*!< CGU PLL1_CTRL: MSEL Position */ #define CGU_PLL1_CTRL_MSEL_Msk (0x000000ffUL << CGU_PLL1_CTRL_MSEL_Pos) /*!< CGU PLL1_CTRL: MSEL Mask */ #define CGU_PLL1_CTRL_CLK_SEL_Pos 24 /*!< CGU PLL1_CTRL: CLK_SEL Position */ #define CGU_PLL1_CTRL_CLK_SEL_Msk (0x1fUL << CGU_PLL1_CTRL_CLK_SEL_Pos) /*!< CGU PLL1_CTRL: CLK_SEL Mask */ /* ------------------------------- CGU_IDIVA_CTRL ------------------------------- */ #define CGU_IDIVA_CTRL_PD_Pos 0 /*!< CGU IDIVA_CTRL: PD Position */ #define CGU_IDIVA_CTRL_PD_Msk (0x01UL << CGU_IDIVA_CTRL_PD_Pos) /*!< CGU IDIVA_CTRL: PD Mask */ #define CGU_IDIVA_CTRL_IDIV_Pos 2 /*!< CGU IDIVA_CTRL: IDIV Position */ #define CGU_IDIVA_CTRL_IDIV_Msk (0x03UL << CGU_IDIVA_CTRL_IDIV_Pos) /*!< CGU IDIVA_CTRL: IDIV Mask */ #define CGU_IDIVA_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVA_CTRL: AUTOBLOCK Position */ #define CGU_IDIVA_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVA_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVA_CTRL: AUTOBLOCK Mask */ #define CGU_IDIVA_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVA_CTRL: CLK_SEL Position */ #define CGU_IDIVA_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVA_CTRL_CLK_SEL_Pos) /*!< CGU IDIVA_CTRL: CLK_SEL Mask */ /* ------------------------------- CGU_IDIVB_CTRL ------------------------------- */ #define CGU_IDIVB_CTRL_PD_Pos 0 /*!< CGU IDIVB_CTRL: PD Position */ #define CGU_IDIVB_CTRL_PD_Msk (0x01UL << CGU_IDIVB_CTRL_PD_Pos) /*!< CGU IDIVB_CTRL: PD Mask */ #define CGU_IDIVB_CTRL_IDIV_Pos 2 /*!< CGU IDIVB_CTRL: IDIV Position */ #define CGU_IDIVB_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVB_CTRL_IDIV_Pos) /*!< CGU IDIVB_CTRL: IDIV Mask */ #define CGU_IDIVB_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVB_CTRL: AUTOBLOCK Position */ #define CGU_IDIVB_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVB_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVB_CTRL: AUTOBLOCK Mask */ #define CGU_IDIVB_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVB_CTRL: CLK_SEL Position */ #define CGU_IDIVB_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVB_CTRL_CLK_SEL_Pos) /*!< CGU IDIVB_CTRL: CLK_SEL Mask */ /* ------------------------------- CGU_IDIVC_CTRL ------------------------------- */ #define CGU_IDIVC_CTRL_PD_Pos 0 /*!< CGU IDIVC_CTRL: PD Position */ #define CGU_IDIVC_CTRL_PD_Msk (0x01UL << CGU_IDIVC_CTRL_PD_Pos) /*!< CGU IDIVC_CTRL: PD Mask */ #define CGU_IDIVC_CTRL_IDIV_Pos 2 /*!< CGU IDIVC_CTRL: IDIV Position */ #define CGU_IDIVC_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVC_CTRL_IDIV_Pos) /*!< CGU IDIVC_CTRL: IDIV Mask */ #define CGU_IDIVC_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVC_CTRL: AUTOBLOCK Position */ #define CGU_IDIVC_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVC_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVC_CTRL: AUTOBLOCK Mask */ #define CGU_IDIVC_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVC_CTRL: CLK_SEL Position */ #define CGU_IDIVC_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVC_CTRL_CLK_SEL_Pos) /*!< CGU IDIVC_CTRL: CLK_SEL Mask */ /* ------------------------------- CGU_IDIVD_CTRL ------------------------------- */ #define CGU_IDIVD_CTRL_PD_Pos 0 /*!< CGU IDIVD_CTRL: PD Position */ #define CGU_IDIVD_CTRL_PD_Msk (0x01UL << CGU_IDIVD_CTRL_PD_Pos) /*!< CGU IDIVD_CTRL: PD Mask */ #define CGU_IDIVD_CTRL_IDIV_Pos 2 /*!< CGU IDIVD_CTRL: IDIV Position */ #define CGU_IDIVD_CTRL_IDIV_Msk (0x0fUL << CGU_IDIVD_CTRL_IDIV_Pos) /*!< CGU IDIVD_CTRL: IDIV Mask */ #define CGU_IDIVD_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVD_CTRL: AUTOBLOCK Position */ #define CGU_IDIVD_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVD_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVD_CTRL: AUTOBLOCK Mask */ #define CGU_IDIVD_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVD_CTRL: CLK_SEL Position */ #define CGU_IDIVD_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVD_CTRL_CLK_SEL_Pos) /*!< CGU IDIVD_CTRL: CLK_SEL Mask */ /* ------------------------------- CGU_IDIVE_CTRL ------------------------------- */ #define CGU_IDIVE_CTRL_PD_Pos 0 /*!< CGU IDIVE_CTRL: PD Position */ #define CGU_IDIVE_CTRL_PD_Msk (0x01UL << CGU_IDIVE_CTRL_PD_Pos) /*!< CGU IDIVE_CTRL: PD Mask */ #define CGU_IDIVE_CTRL_IDIV_Pos 2 /*!< CGU IDIVE_CTRL: IDIV Position */ #define CGU_IDIVE_CTRL_IDIV_Msk (0x000000ffUL << CGU_IDIVE_CTRL_IDIV_Pos) /*!< CGU IDIVE_CTRL: IDIV Mask */ #define CGU_IDIVE_CTRL_AUTOBLOCK_Pos 11 /*!< CGU IDIVE_CTRL: AUTOBLOCK Position */ #define CGU_IDIVE_CTRL_AUTOBLOCK_Msk (0x01UL << CGU_IDIVE_CTRL_AUTOBLOCK_Pos) /*!< CGU IDIVE_CTRL: AUTOBLOCK Mask */ #define CGU_IDIVE_CTRL_CLK_SEL_Pos 24 /*!< CGU IDIVE_CTRL: CLK_SEL Position */ #define CGU_IDIVE_CTRL_CLK_SEL_Msk (0x1fUL << CGU_IDIVE_CTRL_CLK_SEL_Pos) /*!< CGU IDIVE_CTRL: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_SAFE_CLK ----------------------------- */ #define CGU_BASE_SAFE_CLK_PD_Pos 0 /*!< CGU BASE_SAFE_CLK: PD Position */ #define CGU_BASE_SAFE_CLK_PD_Msk (0x01UL << CGU_BASE_SAFE_CLK_PD_Pos) /*!< CGU BASE_SAFE_CLK: PD Mask */ #define CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Position */ #define CGU_BASE_SAFE_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SAFE_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SAFE_CLK: AUTOBLOCK Mask */ #define CGU_BASE_SAFE_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SAFE_CLK: CLK_SEL Position */ #define CGU_BASE_SAFE_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SAFE_CLK_CLK_SEL_Pos) /*!< CGU BASE_SAFE_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_USB0_CLK ----------------------------- */ #define CGU_BASE_USB0_CLK_PD_Pos 0 /*!< CGU BASE_USB0_CLK: PD Position */ #define CGU_BASE_USB0_CLK_PD_Msk (0x01UL << CGU_BASE_USB0_CLK_PD_Pos) /*!< CGU BASE_USB0_CLK: PD Mask */ #define CGU_BASE_USB0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB0_CLK: AUTOBLOCK Position */ #define CGU_BASE_USB0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB0_CLK: AUTOBLOCK Mask */ #define CGU_BASE_USB0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB0_CLK: CLK_SEL Position */ #define CGU_BASE_USB0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB0_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB0_CLK: CLK_SEL Mask */ /* ----------------------------- CGU_BASE_PERIPH_CLK ---------------------------- */ #define CGU_BASE_PERIPH_CLK_PD_Pos 0 /*!< CGU BASE_PERIPH_CLK: PD Position */ #define CGU_BASE_PERIPH_CLK_PD_Msk (0x01UL << CGU_BASE_PERIPH_CLK_PD_Pos) /*!< CGU BASE_PERIPH_CLK: PD Mask */ #define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Position */ #define CGU_BASE_PERIPH_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PERIPH_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PERIPH_CLK: AUTOBLOCK Mask */ #define CGU_BASE_PERIPH_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PERIPH_CLK: CLK_SEL Position */ #define CGU_BASE_PERIPH_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PERIPH_CLK_CLK_SEL_Pos) /*!< CGU BASE_PERIPH_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_USB1_CLK ----------------------------- */ #define CGU_BASE_USB1_CLK_PD_Pos 0 /*!< CGU BASE_USB1_CLK: PD Position */ #define CGU_BASE_USB1_CLK_PD_Msk (0x01UL << CGU_BASE_USB1_CLK_PD_Pos) /*!< CGU BASE_USB1_CLK: PD Mask */ #define CGU_BASE_USB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_USB1_CLK: AUTOBLOCK Position */ #define CGU_BASE_USB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_USB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_USB1_CLK: AUTOBLOCK Mask */ #define CGU_BASE_USB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_USB1_CLK: CLK_SEL Position */ #define CGU_BASE_USB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_USB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_USB1_CLK: CLK_SEL Mask */ /* ------------------------------- CGU_BASE_M4_CLK ------------------------------ */ #define CGU_BASE_M4_CLK_PD_Pos 0 /*!< CGU BASE_M4_CLK: PD Position */ #define CGU_BASE_M4_CLK_PD_Msk (0x01UL << CGU_BASE_M4_CLK_PD_Pos) /*!< CGU BASE_M4_CLK: PD Mask */ #define CGU_BASE_M4_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_M4_CLK: AUTOBLOCK Position */ #define CGU_BASE_M4_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_M4_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_M4_CLK: AUTOBLOCK Mask */ #define CGU_BASE_M4_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_M4_CLK: CLK_SEL Position */ #define CGU_BASE_M4_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_M4_CLK_CLK_SEL_Pos) /*!< CGU BASE_M4_CLK: CLK_SEL Mask */ /* ----------------------------- CGU_BASE_SPIFI_CLK ----------------------------- */ #define CGU_BASE_SPIFI_CLK_PD_Pos 0 /*!< CGU BASE_SPIFI_CLK: PD Position */ #define CGU_BASE_SPIFI_CLK_PD_Msk (0x01UL << CGU_BASE_SPIFI_CLK_PD_Pos) /*!< CGU BASE_SPIFI_CLK: PD Mask */ #define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Position */ #define CGU_BASE_SPIFI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPIFI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPIFI_CLK: AUTOBLOCK Mask */ #define CGU_BASE_SPIFI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPIFI_CLK: CLK_SEL Position */ #define CGU_BASE_SPIFI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPIFI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPIFI_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_SPI_CLK ------------------------------ */ #define CGU_BASE_SPI_CLK_PD_Pos 0 /*!< CGU BASE_SPI_CLK: PD Position */ #define CGU_BASE_SPI_CLK_PD_Msk (0x01UL << CGU_BASE_SPI_CLK_PD_Pos) /*!< CGU BASE_SPI_CLK: PD Mask */ #define CGU_BASE_SPI_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SPI_CLK: AUTOBLOCK Position */ #define CGU_BASE_SPI_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SPI_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SPI_CLK: AUTOBLOCK Mask */ #define CGU_BASE_SPI_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SPI_CLK: CLK_SEL Position */ #define CGU_BASE_SPI_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SPI_CLK_CLK_SEL_Pos) /*!< CGU BASE_SPI_CLK: CLK_SEL Mask */ /* ----------------------------- CGU_BASE_PHY_RX_CLK ---------------------------- */ #define CGU_BASE_PHY_RX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_RX_CLK: PD Position */ #define CGU_BASE_PHY_RX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_PD_Pos) /*!< CGU BASE_PHY_RX_CLK: PD Mask */ #define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Position */ #define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_RX_CLK: AUTOBLOCK Mask */ #define CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Position */ #define CGU_BASE_PHY_RX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_RX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_RX_CLK: CLK_SEL Mask */ /* ----------------------------- CGU_BASE_PHY_TX_CLK ---------------------------- */ #define CGU_BASE_PHY_TX_CLK_PD_Pos 0 /*!< CGU BASE_PHY_TX_CLK: PD Position */ #define CGU_BASE_PHY_TX_CLK_PD_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_PD_Pos) /*!< CGU BASE_PHY_TX_CLK: PD Mask */ #define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Position */ #define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_PHY_TX_CLK: AUTOBLOCK Mask */ #define CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Position */ #define CGU_BASE_PHY_TX_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_PHY_TX_CLK_CLK_SEL_Pos) /*!< CGU BASE_PHY_TX_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_APB1_CLK ----------------------------- */ #define CGU_BASE_APB1_CLK_PD_Pos 0 /*!< CGU BASE_APB1_CLK: PD Position */ #define CGU_BASE_APB1_CLK_PD_Msk (0x01UL << CGU_BASE_APB1_CLK_PD_Pos) /*!< CGU BASE_APB1_CLK: PD Mask */ #define CGU_BASE_APB1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB1_CLK: AUTOBLOCK Position */ #define CGU_BASE_APB1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB1_CLK: AUTOBLOCK Mask */ #define CGU_BASE_APB1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB1_CLK: CLK_SEL Position */ #define CGU_BASE_APB1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB1_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB1_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_APB3_CLK ----------------------------- */ #define CGU_BASE_APB3_CLK_PD_Pos 0 /*!< CGU BASE_APB3_CLK: PD Position */ #define CGU_BASE_APB3_CLK_PD_Msk (0x01UL << CGU_BASE_APB3_CLK_PD_Pos) /*!< CGU BASE_APB3_CLK: PD Mask */ #define CGU_BASE_APB3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APB3_CLK: AUTOBLOCK Position */ #define CGU_BASE_APB3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APB3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APB3_CLK: AUTOBLOCK Mask */ #define CGU_BASE_APB3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APB3_CLK: CLK_SEL Position */ #define CGU_BASE_APB3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APB3_CLK_CLK_SEL_Pos) /*!< CGU BASE_APB3_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_LCD_CLK ------------------------------ */ #define CGU_BASE_LCD_CLK_PD_Pos 0 /*!< CGU BASE_LCD_CLK: PD Position */ #define CGU_BASE_LCD_CLK_PD_Msk (0x01UL << CGU_BASE_LCD_CLK_PD_Pos) /*!< CGU BASE_LCD_CLK: PD Mask */ #define CGU_BASE_LCD_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_LCD_CLK: AUTOBLOCK Position */ #define CGU_BASE_LCD_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_LCD_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_LCD_CLK: AUTOBLOCK Mask */ #define CGU_BASE_LCD_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_LCD_CLK: CLK_SEL Position */ #define CGU_BASE_LCD_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_LCD_CLK_CLK_SEL_Pos) /*!< CGU BASE_LCD_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_SDIO_CLK ----------------------------- */ #define CGU_BASE_SDIO_CLK_PD_Pos 0 /*!< CGU BASE_SDIO_CLK: PD Position */ #define CGU_BASE_SDIO_CLK_PD_Msk (0x01UL << CGU_BASE_SDIO_CLK_PD_Pos) /*!< CGU BASE_SDIO_CLK: PD Mask */ #define CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Position */ #define CGU_BASE_SDIO_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SDIO_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SDIO_CLK: AUTOBLOCK Mask */ #define CGU_BASE_SDIO_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SDIO_CLK: CLK_SEL Position */ #define CGU_BASE_SDIO_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SDIO_CLK_CLK_SEL_Pos) /*!< CGU BASE_SDIO_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_SSP0_CLK ----------------------------- */ #define CGU_BASE_SSP0_CLK_PD_Pos 0 /*!< CGU BASE_SSP0_CLK: PD Position */ #define CGU_BASE_SSP0_CLK_PD_Msk (0x01UL << CGU_BASE_SSP0_CLK_PD_Pos) /*!< CGU BASE_SSP0_CLK: PD Mask */ #define CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Position */ #define CGU_BASE_SSP0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP0_CLK: AUTOBLOCK Mask */ #define CGU_BASE_SSP0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP0_CLK: CLK_SEL Position */ #define CGU_BASE_SSP0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP0_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP0_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_SSP1_CLK ----------------------------- */ #define CGU_BASE_SSP1_CLK_PD_Pos 0 /*!< CGU BASE_SSP1_CLK: PD Position */ #define CGU_BASE_SSP1_CLK_PD_Msk (0x01UL << CGU_BASE_SSP1_CLK_PD_Pos) /*!< CGU BASE_SSP1_CLK: PD Mask */ #define CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Position */ #define CGU_BASE_SSP1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_SSP1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_SSP1_CLK: AUTOBLOCK Mask */ #define CGU_BASE_SSP1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_SSP1_CLK: CLK_SEL Position */ #define CGU_BASE_SSP1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_SSP1_CLK_CLK_SEL_Pos) /*!< CGU BASE_SSP1_CLK: CLK_SEL Mask */ /* ----------------------------- CGU_BASE_UART0_CLK ----------------------------- */ #define CGU_BASE_UART0_CLK_PD_Pos 0 /*!< CGU BASE_UART0_CLK: PD Position */ #define CGU_BASE_UART0_CLK_PD_Msk (0x01UL << CGU_BASE_UART0_CLK_PD_Pos) /*!< CGU BASE_UART0_CLK: PD Mask */ #define CGU_BASE_UART0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART0_CLK: AUTOBLOCK Position */ #define CGU_BASE_UART0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART0_CLK: AUTOBLOCK Mask */ #define CGU_BASE_UART0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART0_CLK: CLK_SEL Position */ #define CGU_BASE_UART0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART0_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART0_CLK: CLK_SEL Mask */ /* ----------------------------- CGU_BASE_UART1_CLK ----------------------------- */ #define CGU_BASE_UART1_CLK_PD_Pos 0 /*!< CGU BASE_UART1_CLK: PD Position */ #define CGU_BASE_UART1_CLK_PD_Msk (0x01UL << CGU_BASE_UART1_CLK_PD_Pos) /*!< CGU BASE_UART1_CLK: PD Mask */ #define CGU_BASE_UART1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART1_CLK: AUTOBLOCK Position */ #define CGU_BASE_UART1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART1_CLK: AUTOBLOCK Mask */ #define CGU_BASE_UART1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART1_CLK: CLK_SEL Position */ #define CGU_BASE_UART1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART1_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART1_CLK: CLK_SEL Mask */ /* ----------------------------- CGU_BASE_UART2_CLK ----------------------------- */ #define CGU_BASE_UART2_CLK_PD_Pos 0 /*!< CGU BASE_UART2_CLK: PD Position */ #define CGU_BASE_UART2_CLK_PD_Msk (0x01UL << CGU_BASE_UART2_CLK_PD_Pos) /*!< CGU BASE_UART2_CLK: PD Mask */ #define CGU_BASE_UART2_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART2_CLK: AUTOBLOCK Position */ #define CGU_BASE_UART2_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART2_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART2_CLK: AUTOBLOCK Mask */ #define CGU_BASE_UART2_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART2_CLK: CLK_SEL Position */ #define CGU_BASE_UART2_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART2_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART2_CLK: CLK_SEL Mask */ /* ----------------------------- CGU_BASE_UART3_CLK ----------------------------- */ #define CGU_BASE_UART3_CLK_PD_Pos 0 /*!< CGU BASE_UART3_CLK: PD Position */ #define CGU_BASE_UART3_CLK_PD_Msk (0x01UL << CGU_BASE_UART3_CLK_PD_Pos) /*!< CGU BASE_UART3_CLK: PD Mask */ #define CGU_BASE_UART3_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_UART3_CLK: AUTOBLOCK Position */ #define CGU_BASE_UART3_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_UART3_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_UART3_CLK: AUTOBLOCK Mask */ #define CGU_BASE_UART3_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_UART3_CLK: CLK_SEL Position */ #define CGU_BASE_UART3_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_UART3_CLK_CLK_SEL_Pos) /*!< CGU BASE_UART3_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_OUT_CLK ------------------------------ */ #define CGU_BASE_OUT_CLK_PD_Pos 0 /*!< CGU BASE_OUT_CLK: PD Position */ #define CGU_BASE_OUT_CLK_PD_Msk (0x01UL << CGU_BASE_OUT_CLK_PD_Pos) /*!< CGU BASE_OUT_CLK: PD Mask */ #define CGU_BASE_OUT_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_OUT_CLK: AUTOBLOCK Position */ #define CGU_BASE_OUT_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_OUT_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_OUT_CLK: AUTOBLOCK Mask */ #define CGU_BASE_OUT_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_OUT_CLK: CLK_SEL Position */ #define CGU_BASE_OUT_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_OUT_CLK_CLK_SEL_Pos) /*!< CGU BASE_OUT_CLK: CLK_SEL Mask */ /* ------------------------------ CGU_BASE_APLL_CLK ----------------------------- */ #define CGU_BASE_APLL_CLK_PD_Pos 0 /*!< CGU BASE_APLL_CLK: PD Position */ #define CGU_BASE_APLL_CLK_PD_Msk (0x01UL << CGU_BASE_APLL_CLK_PD_Pos) /*!< CGU BASE_APLL_CLK: PD Mask */ #define CGU_BASE_APLL_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_APLL_CLK: AUTOBLOCK Position */ #define CGU_BASE_APLL_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_APLL_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_APLL_CLK: AUTOBLOCK Mask */ #define CGU_BASE_APLL_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_APLL_CLK: CLK_SEL Position */ #define CGU_BASE_APLL_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_APLL_CLK_CLK_SEL_Pos) /*!< CGU BASE_APLL_CLK: CLK_SEL Mask */ /* ---------------------------- CGU_BASE_CGU_OUT0_CLK --------------------------- */ #define CGU_BASE_CGU_OUT0_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT0_CLK: PD Position */ #define CGU_BASE_CGU_OUT0_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT0_CLK: PD Mask */ #define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Position */ #define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT0_CLK: AUTOBLOCK Mask */ #define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Position */ #define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT0_CLK: CLK_SEL Mask */ /* ---------------------------- CGU_BASE_CGU_OUT1_CLK --------------------------- */ #define CGU_BASE_CGU_OUT1_CLK_PD_Pos 0 /*!< CGU BASE_CGU_OUT1_CLK: PD Position */ #define CGU_BASE_CGU_OUT1_CLK_PD_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_PD_Pos) /*!< CGU BASE_CGU_OUT1_CLK: PD Mask */ #define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos 11 /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Position */ #define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Msk (0x01UL << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_Pos) /*!< CGU BASE_CGU_OUT1_CLK: AUTOBLOCK Mask */ #define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos 24 /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Position */ #define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Msk (0x1fUL << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_Pos) /*!< CGU BASE_CGU_OUT1_CLK: CLK_SEL Mask */ /* ================================================================================ */ /* ================ struct 'CCU1' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- CCU1_PM ---------------------------------- */ #define CCU1_PM_PD_Pos 0 /*!< CCU1 PM: PD Position */ #define CCU1_PM_PD_Msk (0x01UL << CCU1_PM_PD_Pos) /*!< CCU1 PM: PD Mask */ /* ------------------------------- CCU1_BASE_STAT ------------------------------- */ #define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos 0 /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Position */ #define CCU1_BASE_STAT_BASE_APB3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB3_CLK_IND Mask */ #define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos 1 /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Position */ #define CCU1_BASE_STAT_BASE_APB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_APB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_APB1_CLK_IND Mask */ #define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos 2 /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Position */ #define CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_SPIFI_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_SPIFI_CLK_IND Mask */ #define CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos 3 /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Position */ #define CCU1_BASE_STAT_BASE_M3_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_M3_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_M3_CLK_IND Mask */ #define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos 7 /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Position */ #define CCU1_BASE_STAT_BASE_USB0_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB0_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB0_CLK_IND Mask */ #define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos 8 /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Position */ #define CCU1_BASE_STAT_BASE_USB1_CLK_IND_Msk (0x01UL << CCU1_BASE_STAT_BASE_USB1_CLK_IND_Pos) /*!< CCU1 BASE_STAT: BASE_USB1_CLK_IND Mask */ /* ---------------------------- CCU1_CLK_APB3_BUS_CFG --------------------------- */ #define CCU1_CLK_APB3_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_CFG: RUN Position */ #define CCU1_CLK_APB3_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: RUN Mask */ #define CCU1_CLK_APB3_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Position */ #define CCU1_CLK_APB3_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: AUTO Mask */ #define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Position */ #define CCU1_CLK_APB3_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_BUS_STAT --------------------------- */ #define CCU1_CLK_APB3_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_BUS_STAT: RUN Position */ #define CCU1_CLK_APB3_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: RUN Mask */ #define CCU1_CLK_APB3_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Position */ #define CCU1_CLK_APB3_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: AUTO Mask */ #define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Position */ #define CCU1_CLK_APB3_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_BUS_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_I2C1_CFG --------------------------- */ #define CCU1_CLK_APB3_I2C1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Position */ #define CCU1_CLK_APB3_I2C1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: RUN Mask */ #define CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Position */ #define CCU1_CLK_APB3_I2C1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: AUTO Mask */ #define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Position */ #define CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_I2C1_STAT -------------------------- */ #define CCU1_CLK_APB3_I2C1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Position */ #define CCU1_CLK_APB3_I2C1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: RUN Mask */ #define CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Position */ #define CCU1_CLK_APB3_I2C1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: AUTO Mask */ #define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Position */ #define CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_I2C1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_I2C1_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_APB3_DAC_CFG --------------------------- */ #define CCU1_CLK_APB3_DAC_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_CFG: RUN Position */ #define CCU1_CLK_APB3_DAC_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: RUN Mask */ #define CCU1_CLK_APB3_DAC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Position */ #define CCU1_CLK_APB3_DAC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: AUTO Mask */ #define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Position */ #define CCU1_CLK_APB3_DAC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_DAC_STAT --------------------------- */ #define CCU1_CLK_APB3_DAC_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_DAC_STAT: RUN Position */ #define CCU1_CLK_APB3_DAC_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: RUN Mask */ #define CCU1_CLK_APB3_DAC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Position */ #define CCU1_CLK_APB3_DAC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: AUTO Mask */ #define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Position */ #define CCU1_CLK_APB3_DAC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_DAC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_DAC_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_ADC0_CFG --------------------------- */ #define CCU1_CLK_APB3_ADC0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Position */ #define CCU1_CLK_APB3_ADC0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: RUN Mask */ #define CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Position */ #define CCU1_CLK_APB3_ADC0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: AUTO Mask */ #define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Position */ #define CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_ADC0_STAT -------------------------- */ #define CCU1_CLK_APB3_ADC0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Position */ #define CCU1_CLK_APB3_ADC0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: RUN Mask */ #define CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Position */ #define CCU1_CLK_APB3_ADC0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: AUTO Mask */ #define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Position */ #define CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC0_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_ADC1_CFG --------------------------- */ #define CCU1_CLK_APB3_ADC1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Position */ #define CCU1_CLK_APB3_ADC1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: RUN Mask */ #define CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Position */ #define CCU1_CLK_APB3_ADC1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: AUTO Mask */ #define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Position */ #define CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_ADC1_STAT -------------------------- */ #define CCU1_CLK_APB3_ADC1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Position */ #define CCU1_CLK_APB3_ADC1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: RUN Mask */ #define CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Position */ #define CCU1_CLK_APB3_ADC1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: AUTO Mask */ #define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Position */ #define CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_ADC1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_ADC1_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_CAN0_CFG --------------------------- */ #define CCU1_CLK_APB3_CAN0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Position */ #define CCU1_CLK_APB3_CAN0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: RUN Mask */ #define CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Position */ #define CCU1_CLK_APB3_CAN0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: AUTO Mask */ #define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Position */ #define CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB3_CAN0_STAT -------------------------- */ #define CCU1_CLK_APB3_CAN0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Position */ #define CCU1_CLK_APB3_CAN0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_RUN_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: RUN Mask */ #define CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Position */ #define CCU1_CLK_APB3_CAN0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: AUTO Mask */ #define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Position */ #define CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB3_CAN0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB3_CAN0_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_APB1_BUS_CFG --------------------------- */ #define CCU1_CLK_APB1_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_CFG: RUN Position */ #define CCU1_CLK_APB1_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: RUN Mask */ #define CCU1_CLK_APB1_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Position */ #define CCU1_CLK_APB1_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: AUTO Mask */ #define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Position */ #define CCU1_CLK_APB1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB1_BUS_STAT --------------------------- */ #define CCU1_CLK_APB1_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_BUS_STAT: RUN Position */ #define CCU1_CLK_APB1_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: RUN Mask */ #define CCU1_CLK_APB1_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Position */ #define CCU1_CLK_APB1_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: AUTO Mask */ #define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Position */ #define CCU1_CLK_APB1_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_BUS_STAT: WAKEUP Mask */ /* ------------------------ CCU1_CLK_APB1_MOTOCONPWM_CFG ------------------------ */ #define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Position */ #define CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: RUN Mask */ #define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Position */ #define CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: AUTO Mask */ #define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Position */ #define CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_CFG: WAKEUP Mask */ /* ------------------------ CCU1_CLK_APB1_MOTOCONPWM_STAT ----------------------- */ #define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Position */ #define CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: RUN Mask */ #define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Position */ #define CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: AUTO Mask */ #define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Position */ #define CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_MOTOCONPWM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_MOTOCONPWM_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB1_I2C0_CFG --------------------------- */ #define CCU1_CLK_APB1_I2C0_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_CFG: RUN Position */ #define CCU1_CLK_APB1_I2C0_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_CFG: RUN Mask */ #define CCU1_CLK_APB1_I2C0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_CFG: AUTO Position */ #define CCU1_CLK_APB1_I2C0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_CFG: AUTO Mask */ #define CCU1_CLK_APB1_I2C0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_CFG: WAKEUP Position */ #define CCU1_CLK_APB1_I2C0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB1_I2C0_STAT -------------------------- */ #define CCU1_CLK_APB1_I2C0_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Position */ #define CCU1_CLK_APB1_I2C0_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: RUN Mask */ #define CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Position */ #define CCU1_CLK_APB1_I2C0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: AUTO Mask */ #define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Position */ #define CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2C0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2C0_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_APB1_I2S_CFG --------------------------- */ #define CCU1_CLK_APB1_I2S_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_CFG: RUN Position */ #define CCU1_CLK_APB1_I2S_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: RUN Mask */ #define CCU1_CLK_APB1_I2S_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Position */ #define CCU1_CLK_APB1_I2S_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: AUTO Mask */ #define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Position */ #define CCU1_CLK_APB1_I2S_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB1_I2S_STAT --------------------------- */ #define CCU1_CLK_APB1_I2S_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_I2S_STAT: RUN Position */ #define CCU1_CLK_APB1_I2S_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: RUN Mask */ #define CCU1_CLK_APB1_I2S_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Position */ #define CCU1_CLK_APB1_I2S_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: AUTO Mask */ #define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Position */ #define CCU1_CLK_APB1_I2S_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_I2S_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_I2S_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB1_CAN1_CFG --------------------------- */ #define CCU1_CLK_APB1_CAN1_CFG_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Position */ #define CCU1_CLK_APB1_CAN1_CFG_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: RUN Mask */ #define CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Position */ #define CCU1_CLK_APB1_CAN1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: AUTO Mask */ #define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Position */ #define CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_APB1_CAN1_STAT -------------------------- */ #define CCU1_CLK_APB1_CAN1_STAT_RUN_Pos 0 /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Position */ #define CCU1_CLK_APB1_CAN1_STAT_RUN_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_RUN_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: RUN Mask */ #define CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Position */ #define CCU1_CLK_APB1_CAN1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_AUTO_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: AUTO Mask */ #define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Position */ #define CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_APB1_CAN1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_APB1_CAN1_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_SPIFI_CFG ----------------------------- */ #define CCU1_CLK_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_CFG: RUN Position */ #define CCU1_CLK_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_SPIFI_CFG: RUN Mask */ #define CCU1_CLK_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_CFG: AUTO Position */ #define CCU1_CLK_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPIFI_CFG: AUTO Mask */ #define CCU1_CLK_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Position */ #define CCU1_CLK_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_CFG: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_SPIFI_STAT ---------------------------- */ #define CCU1_CLK_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPIFI_STAT: RUN Position */ #define CCU1_CLK_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_SPIFI_STAT: RUN Mask */ #define CCU1_CLK_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPIFI_STAT: AUTO Position */ #define CCU1_CLK_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPIFI_STAT: AUTO Mask */ #define CCU1_CLK_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Position */ #define CCU1_CLK_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPIFI_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_M4_BUS_CFG ---------------------------- */ #define CCU1_CLK_M4_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_BUS_CFG: RUN Position */ #define CCU1_CLK_M4_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_M4_BUS_CFG: RUN Mask */ #define CCU1_CLK_M4_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_BUS_CFG: AUTO Position */ #define CCU1_CLK_M4_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_BUS_CFG: AUTO Mask */ #define CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Position */ #define CCU1_CLK_M4_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_BUS_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_BUS_STAT ---------------------------- */ #define CCU1_CLK_M4_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_BUS_STAT: RUN Position */ #define CCU1_CLK_M4_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_M4_BUS_STAT: RUN Mask */ #define CCU1_CLK_M4_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_BUS_STAT: AUTO Position */ #define CCU1_CLK_M4_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_BUS_STAT: AUTO Mask */ #define CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Position */ #define CCU1_CLK_M4_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_BUS_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SPIFI_CFG --------------------------- */ #define CCU1_CLK_M4_SPIFI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Position */ #define CCU1_CLK_M4_SPIFI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: RUN Mask */ #define CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Position */ #define CCU1_CLK_M4_SPIFI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: AUTO Mask */ #define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Position */ #define CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SPIFI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SPIFI_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_SPIFI_STAT --------------------------- */ #define CCU1_CLK_M4_SPIFI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Position */ #define CCU1_CLK_M4_SPIFI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: RUN Mask */ #define CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Position */ #define CCU1_CLK_M4_SPIFI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: AUTO Mask */ #define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Position */ #define CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SPIFI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SPIFI_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_GPIO_CFG ---------------------------- */ #define CCU1_CLK_M4_GPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_GPIO_CFG: RUN Position */ #define CCU1_CLK_M4_GPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_RUN_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: RUN Mask */ #define CCU1_CLK_M4_GPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Position */ #define CCU1_CLK_M4_GPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: AUTO Mask */ #define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Position */ #define CCU1_CLK_M4_GPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_GPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_GPIO_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_GPIO_STAT --------------------------- */ #define CCU1_CLK_M4_GPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_GPIO_STAT: RUN Position */ #define CCU1_CLK_M4_GPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_RUN_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: RUN Mask */ #define CCU1_CLK_M4_GPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Position */ #define CCU1_CLK_M4_GPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: AUTO Mask */ #define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Position */ #define CCU1_CLK_M4_GPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_GPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_GPIO_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_M4_LCD_CFG ---------------------------- */ #define CCU1_CLK_M4_LCD_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_LCD_CFG: RUN Position */ #define CCU1_CLK_M4_LCD_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_RUN_Pos) /*!< CCU1 CLK_M4_LCD_CFG: RUN Mask */ #define CCU1_CLK_M4_LCD_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_LCD_CFG: AUTO Position */ #define CCU1_CLK_M4_LCD_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_LCD_CFG: AUTO Mask */ #define CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Position */ #define CCU1_CLK_M4_LCD_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_LCD_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_LCD_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_LCD_STAT ---------------------------- */ #define CCU1_CLK_M4_LCD_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_LCD_STAT: RUN Position */ #define CCU1_CLK_M4_LCD_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_RUN_Pos) /*!< CCU1 CLK_M4_LCD_STAT: RUN Mask */ #define CCU1_CLK_M4_LCD_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_LCD_STAT: AUTO Position */ #define CCU1_CLK_M4_LCD_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_LCD_STAT: AUTO Mask */ #define CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Position */ #define CCU1_CLK_M4_LCD_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_LCD_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_LCD_STAT: WAKEUP Mask */ /* -------------------------- CCU1_CLK_M4_ETHERNET_CFG -------------------------- */ #define CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Position */ #define CCU1_CLK_M4_ETHERNET_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_RUN_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: RUN Mask */ #define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Position */ #define CCU1_CLK_M4_ETHERNET_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: AUTO Mask */ #define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Position */ #define CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_ETHERNET_CFG: WAKEUP Mask */ /* -------------------------- CCU1_CLK_M4_ETHERNET_STAT ------------------------- */ #define CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Position */ #define CCU1_CLK_M4_ETHERNET_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_RUN_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: RUN Mask */ #define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Position */ #define CCU1_CLK_M4_ETHERNET_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: AUTO Mask */ #define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Position */ #define CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ETHERNET_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_ETHERNET_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_USB0_CFG ---------------------------- */ #define CCU1_CLK_M4_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USB0_CFG: RUN Position */ #define CCU1_CLK_M4_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USB0_CFG: RUN Mask */ #define CCU1_CLK_M4_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB0_CFG: AUTO Position */ #define CCU1_CLK_M4_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USB0_CFG: AUTO Mask */ #define CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Position */ #define CCU1_CLK_M4_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB0_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_USB0_STAT --------------------------- */ #define CCU1_CLK_M4_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USB0_STAT: RUN Position */ #define CCU1_CLK_M4_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USB0_STAT: RUN Mask */ #define CCU1_CLK_M4_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB0_STAT: AUTO Position */ #define CCU1_CLK_M4_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USB0_STAT: AUTO Mask */ #define CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Position */ #define CCU1_CLK_M4_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB0_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_M4_EMC_CFG ---------------------------- */ #define CCU1_CLK_M4_EMC_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EMC_CFG: RUN Position */ #define CCU1_CLK_M4_EMC_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EMC_CFG: RUN Mask */ #define CCU1_CLK_M4_EMC_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMC_CFG: AUTO Position */ #define CCU1_CLK_M4_EMC_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EMC_CFG: AUTO Mask */ #define CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Position */ #define CCU1_CLK_M4_EMC_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMC_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMC_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_EMC_STAT ---------------------------- */ #define CCU1_CLK_M4_EMC_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EMC_STAT: RUN Position */ #define CCU1_CLK_M4_EMC_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EMC_STAT: RUN Mask */ #define CCU1_CLK_M4_EMC_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMC_STAT: AUTO Position */ #define CCU1_CLK_M4_EMC_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EMC_STAT: AUTO Mask */ #define CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Position */ #define CCU1_CLK_M4_EMC_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMC_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMC_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SDIO_CFG ---------------------------- */ #define CCU1_CLK_M4_SDIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SDIO_CFG: RUN Position */ #define CCU1_CLK_M4_SDIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: RUN Mask */ #define CCU1_CLK_M4_SDIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Position */ #define CCU1_CLK_M4_SDIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: AUTO Mask */ #define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Position */ #define CCU1_CLK_M4_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SDIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SDIO_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SDIO_STAT --------------------------- */ #define CCU1_CLK_M4_SDIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SDIO_STAT: RUN Position */ #define CCU1_CLK_M4_SDIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: RUN Mask */ #define CCU1_CLK_M4_SDIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Position */ #define CCU1_CLK_M4_SDIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: AUTO Mask */ #define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Position */ #define CCU1_CLK_M4_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SDIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SDIO_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_M4_DMA_CFG ---------------------------- */ #define CCU1_CLK_M4_DMA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_DMA_CFG: RUN Position */ #define CCU1_CLK_M4_DMA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_RUN_Pos) /*!< CCU1 CLK_M4_DMA_CFG: RUN Mask */ #define CCU1_CLK_M4_DMA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_DMA_CFG: AUTO Position */ #define CCU1_CLK_M4_DMA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_DMA_CFG: AUTO Mask */ #define CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Position */ #define CCU1_CLK_M4_DMA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_DMA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_DMA_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_DMA_STAT ---------------------------- */ #define CCU1_CLK_M4_DMA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_DMA_STAT: RUN Position */ #define CCU1_CLK_M4_DMA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_RUN_Pos) /*!< CCU1 CLK_M4_DMA_STAT: RUN Mask */ #define CCU1_CLK_M4_DMA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_DMA_STAT: AUTO Position */ #define CCU1_CLK_M4_DMA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_DMA_STAT: AUTO Mask */ #define CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Position */ #define CCU1_CLK_M4_DMA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_DMA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_DMA_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_M4CORE_CFG --------------------------- */ #define CCU1_CLK_M4_M4CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Position */ #define CCU1_CLK_M4_M4CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_RUN_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: RUN Mask */ #define CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Position */ #define CCU1_CLK_M4_M4CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: AUTO Mask */ #define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Position */ #define CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M4CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_M4CORE_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_M4CORE_STAT -------------------------- */ #define CCU1_CLK_M4_M4CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_M4CORE_STAT: RUN Position */ #define CCU1_CLK_M4_M4CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_M4CORE_STAT_RUN_Pos) /*!< CCU1 CLK_M4_M4CORE_STAT: RUN Mask */ #define CCU1_CLK_M4_M4CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_M4CORE_STAT: AUTO Position */ #define CCU1_CLK_M4_M4CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_M4CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_M4CORE_STAT: AUTO Mask */ #define CCU1_CLK_M4_M4CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M4CORE_STAT: WAKEUP Position */ #define CCU1_CLK_M4_M4CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M4CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_M4CORE_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_M4_SCT_CFG ---------------------------- */ #define CCU1_CLK_M4_SCT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SCT_CFG: RUN Position */ #define CCU1_CLK_M4_SCT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SCT_CFG: RUN Mask */ #define CCU1_CLK_M4_SCT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCT_CFG: AUTO Position */ #define CCU1_CLK_M4_SCT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SCT_CFG: AUTO Mask */ #define CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Position */ #define CCU1_CLK_M4_SCT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCT_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SCT_STAT ---------------------------- */ #define CCU1_CLK_M4_SCT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SCT_STAT: RUN Position */ #define CCU1_CLK_M4_SCT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SCT_STAT: RUN Mask */ #define CCU1_CLK_M4_SCT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCT_STAT: AUTO Position */ #define CCU1_CLK_M4_SCT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SCT_STAT: AUTO Mask */ #define CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Position */ #define CCU1_CLK_M4_SCT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCT_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_USB1_CFG ---------------------------- */ #define CCU1_CLK_M4_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USB1_CFG: RUN Position */ #define CCU1_CLK_M4_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USB1_CFG: RUN Mask */ #define CCU1_CLK_M4_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB1_CFG: AUTO Position */ #define CCU1_CLK_M4_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USB1_CFG: AUTO Mask */ #define CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Position */ #define CCU1_CLK_M4_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB1_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_USB1_STAT --------------------------- */ #define CCU1_CLK_M4_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USB1_STAT: RUN Position */ #define CCU1_CLK_M4_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USB1_STAT: RUN Mask */ #define CCU1_CLK_M4_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USB1_STAT: AUTO Position */ #define CCU1_CLK_M4_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USB1_STAT: AUTO Mask */ #define CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Position */ #define CCU1_CLK_M4_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USB1_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_EMCDIV_CFG --------------------------- */ #define CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Position */ #define CCU1_CLK_M4_EMCDIV_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: RUN Mask */ #define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Position */ #define CCU1_CLK_M4_EMCDIV_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: AUTO Mask */ #define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Position */ #define CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMCDIV_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_EMCDIV_STAT -------------------------- */ #define CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Position */ #define CCU1_CLK_M4_EMCDIV_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: RUN Mask */ #define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Position */ #define CCU1_CLK_M4_EMCDIV_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: AUTO Mask */ #define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Position */ #define CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EMCDIV_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EMCDIV_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_FLASHA_CFG --------------------------- */ #define CCU1_CLK_M4_FLASHA_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_FLASHA_CFG: RUN Position */ #define CCU1_CLK_M4_FLASHA_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_FLASHA_CFG_RUN_Pos) /*!< CCU1 CLK_M4_FLASHA_CFG: RUN Mask */ #define CCU1_CLK_M4_FLASHA_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_FLASHA_CFG: AUTO Position */ #define CCU1_CLK_M4_FLASHA_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_FLASHA_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_FLASHA_CFG: AUTO Mask */ #define CCU1_CLK_M4_FLASHA_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_FLASHA_CFG: WAKEUP Position */ #define CCU1_CLK_M4_FLASHA_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_FLASHA_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_FLASHA_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_FLASHA_STAT -------------------------- */ #define CCU1_CLK_M4_FLASHA_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_FLASHA_STAT: RUN Position */ #define CCU1_CLK_M4_FLASHA_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_FLASHA_STAT_RUN_Pos) /*!< CCU1 CLK_M4_FLASHA_STAT: RUN Mask */ #define CCU1_CLK_M4_FLASHA_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_FLASHA_STAT: AUTO Position */ #define CCU1_CLK_M4_FLASHA_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_FLASHA_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_FLASHA_STAT: AUTO Mask */ #define CCU1_CLK_M4_FLASHA_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_FLASHA_STAT: WAKEUP Position */ #define CCU1_CLK_M4_FLASHA_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_FLASHA_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_FLASHA_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_FLASHB_CFG --------------------------- */ #define CCU1_CLK_M4_FLASHB_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_FLASHB_CFG: RUN Position */ #define CCU1_CLK_M4_FLASHB_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_FLASHB_CFG_RUN_Pos) /*!< CCU1 CLK_M4_FLASHB_CFG: RUN Mask */ #define CCU1_CLK_M4_FLASHB_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_FLASHB_CFG: AUTO Position */ #define CCU1_CLK_M4_FLASHB_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_FLASHB_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_FLASHB_CFG: AUTO Mask */ #define CCU1_CLK_M4_FLASHB_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_FLASHB_CFG: WAKEUP Position */ #define CCU1_CLK_M4_FLASHB_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_FLASHB_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_FLASHB_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_FLASHB_STAT -------------------------- */ #define CCU1_CLK_M4_FLASHB_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_FLASHB_STAT: RUN Position */ #define CCU1_CLK_M4_FLASHB_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_FLASHB_STAT_RUN_Pos) /*!< CCU1 CLK_M4_FLASHB_STAT: RUN Mask */ #define CCU1_CLK_M4_FLASHB_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_FLASHB_STAT: AUTO Position */ #define CCU1_CLK_M4_FLASHB_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_FLASHB_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_FLASHB_STAT: AUTO Mask */ #define CCU1_CLK_M4_FLASHB_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_FLASHB_STAT: WAKEUP Position */ #define CCU1_CLK_M4_FLASHB_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_FLASHB_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_FLASHB_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_M0APP_CFG --------------------------- */ #define CCU1_CLK_M4_M0APP_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_M0APP_CFG: RUN Position */ #define CCU1_CLK_M4_M0APP_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_RUN_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: RUN Mask */ #define CCU1_CLK_M4_M0APP_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Position */ #define CCU1_CLK_M4_M0APP_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: AUTO Mask */ #define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Position */ #define CCU1_CLK_M4_M0APP_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M0APP_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_M0APP_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_M0APP_STAT --------------------------- */ #define CCU1_CLK_M4_M0APP_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_M0APP_STAT: RUN Position */ #define CCU1_CLK_M4_M0APP_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_RUN_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: RUN Mask */ #define CCU1_CLK_M4_M0APP_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Position */ #define CCU1_CLK_M4_M0APP_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: AUTO Mask */ #define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Position */ #define CCU1_CLK_M4_M0APP_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_M0APP_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_M0APP_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_ADCHS_CFG --------------------------- */ #define CCU1_CLK_M4_ADCHS_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_ADCHS_CFG: RUN Position */ #define CCU1_CLK_M4_ADCHS_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_ADCHS_CFG_RUN_Pos) /*!< CCU1 CLK_M4_ADCHS_CFG: RUN Mask */ #define CCU1_CLK_M4_ADCHS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_ADCHS_CFG: AUTO Position */ #define CCU1_CLK_M4_ADCHS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_ADCHS_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_ADCHS_CFG: AUTO Mask */ #define CCU1_CLK_M4_ADCHS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ADCHS_CFG: WAKEUP Position */ #define CCU1_CLK_M4_ADCHS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ADCHS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_ADCHS_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_ADCHS_STAT --------------------------- */ #define CCU1_CLK_M4_ADCHS_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_ADCHS_STAT: RUN Position */ #define CCU1_CLK_M4_ADCHS_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_ADCHS_STAT_RUN_Pos) /*!< CCU1 CLK_M4_ADCHS_STAT: RUN Mask */ #define CCU1_CLK_M4_ADCHS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_ADCHS_STAT: AUTO Position */ #define CCU1_CLK_M4_ADCHS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_ADCHS_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_ADCHS_STAT: AUTO Mask */ #define CCU1_CLK_M4_ADCHS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_ADCHS_STAT: WAKEUP Position */ #define CCU1_CLK_M4_ADCHS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_ADCHS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_ADCHS_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_EEPROM_CFG --------------------------- */ #define CCU1_CLK_M4_EEPROM_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_EEPROM_CFG: RUN Position */ #define CCU1_CLK_M4_EEPROM_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_EEPROM_CFG_RUN_Pos) /*!< CCU1 CLK_M4_EEPROM_CFG: RUN Mask */ #define CCU1_CLK_M4_EEPROM_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_EEPROM_CFG: AUTO Position */ #define CCU1_CLK_M4_EEPROM_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_EEPROM_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_EEPROM_CFG: AUTO Mask */ #define CCU1_CLK_M4_EEPROM_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EEPROM_CFG: WAKEUP Position */ #define CCU1_CLK_M4_EEPROM_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EEPROM_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_EEPROM_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_EEPROM_STAT -------------------------- */ #define CCU1_CLK_M4_EEPROM_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_EEPROM_STAT: RUN Position */ #define CCU1_CLK_M4_EEPROM_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_EEPROM_STAT_RUN_Pos) /*!< CCU1 CLK_M4_EEPROM_STAT: RUN Mask */ #define CCU1_CLK_M4_EEPROM_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_EEPROM_STAT: AUTO Position */ #define CCU1_CLK_M4_EEPROM_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_EEPROM_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_EEPROM_STAT: AUTO Mask */ #define CCU1_CLK_M4_EEPROM_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_EEPROM_STAT: WAKEUP Position */ #define CCU1_CLK_M4_EEPROM_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_EEPROM_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_EEPROM_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_WWDT_CFG ---------------------------- */ #define CCU1_CLK_M4_WWDT_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_WWDT_CFG: RUN Position */ #define CCU1_CLK_M4_WWDT_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_RUN_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: RUN Mask */ #define CCU1_CLK_M4_WWDT_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Position */ #define CCU1_CLK_M4_WWDT_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: AUTO Mask */ #define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Position */ #define CCU1_CLK_M4_WWDT_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_WWDT_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_WWDT_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_WWDT_STAT --------------------------- */ #define CCU1_CLK_M4_WWDT_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_WWDT_STAT: RUN Position */ #define CCU1_CLK_M4_WWDT_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_RUN_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: RUN Mask */ #define CCU1_CLK_M4_WWDT_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Position */ #define CCU1_CLK_M4_WWDT_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: AUTO Mask */ #define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Position */ #define CCU1_CLK_M4_WWDT_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_WWDT_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_WWDT_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_USART0_CFG --------------------------- */ #define CCU1_CLK_M4_USART0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART0_CFG: RUN Position */ #define CCU1_CLK_M4_USART0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART0_CFG: RUN Mask */ #define CCU1_CLK_M4_USART0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART0_CFG: AUTO Position */ #define CCU1_CLK_M4_USART0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART0_CFG: AUTO Mask */ #define CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Position */ #define CCU1_CLK_M4_USART0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART0_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_USART0_STAT -------------------------- */ #define CCU1_CLK_M4_USART0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART0_STAT: RUN Position */ #define CCU1_CLK_M4_USART0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART0_STAT: RUN Mask */ #define CCU1_CLK_M4_USART0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART0_STAT: AUTO Position */ #define CCU1_CLK_M4_USART0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART0_STAT: AUTO Mask */ #define CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Position */ #define CCU1_CLK_M4_USART0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART0_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_UART1_CFG --------------------------- */ #define CCU1_CLK_M4_UART1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_UART1_CFG: RUN Position */ #define CCU1_CLK_M4_UART1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_UART1_CFG: RUN Mask */ #define CCU1_CLK_M4_UART1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_UART1_CFG: AUTO Position */ #define CCU1_CLK_M4_UART1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_UART1_CFG: AUTO Mask */ #define CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Position */ #define CCU1_CLK_M4_UART1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_UART1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_UART1_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_UART1_STAT --------------------------- */ #define CCU1_CLK_M4_UART1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_UART1_STAT: RUN Position */ #define CCU1_CLK_M4_UART1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_UART1_STAT: RUN Mask */ #define CCU1_CLK_M4_UART1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_UART1_STAT: AUTO Position */ #define CCU1_CLK_M4_UART1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_UART1_STAT: AUTO Mask */ #define CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Position */ #define CCU1_CLK_M4_UART1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_UART1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_UART1_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SSP0_CFG ---------------------------- */ #define CCU1_CLK_M4_SSP0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP0_CFG: RUN Position */ #define CCU1_CLK_M4_SSP0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: RUN Mask */ #define CCU1_CLK_M4_SSP0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Position */ #define CCU1_CLK_M4_SSP0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: AUTO Mask */ #define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Position */ #define CCU1_CLK_M4_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP0_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SSP0_STAT --------------------------- */ #define CCU1_CLK_M4_SSP0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP0_STAT: RUN Position */ #define CCU1_CLK_M4_SSP0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: RUN Mask */ #define CCU1_CLK_M4_SSP0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Position */ #define CCU1_CLK_M4_SSP0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: AUTO Mask */ #define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Position */ #define CCU1_CLK_M4_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP0_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_TIMER0_CFG --------------------------- */ #define CCU1_CLK_M4_TIMER0_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Position */ #define CCU1_CLK_M4_TIMER0_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: RUN Mask */ #define CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Position */ #define CCU1_CLK_M4_TIMER0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: AUTO Mask */ #define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Position */ #define CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER0_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_TIMER0_STAT -------------------------- */ #define CCU1_CLK_M4_TIMER0_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Position */ #define CCU1_CLK_M4_TIMER0_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: RUN Mask */ #define CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Position */ #define CCU1_CLK_M4_TIMER0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: AUTO Mask */ #define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Position */ #define CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER0_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_TIMER1_CFG --------------------------- */ #define CCU1_CLK_M4_TIMER1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Position */ #define CCU1_CLK_M4_TIMER1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: RUN Mask */ #define CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Position */ #define CCU1_CLK_M4_TIMER1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: AUTO Mask */ #define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Position */ #define CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER1_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_TIMER1_STAT -------------------------- */ #define CCU1_CLK_M4_TIMER1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Position */ #define CCU1_CLK_M4_TIMER1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: RUN Mask */ #define CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Position */ #define CCU1_CLK_M4_TIMER1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: AUTO Mask */ #define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Position */ #define CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER1_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_M4_SCU_CFG ---------------------------- */ #define CCU1_CLK_M4_SCU_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SCU_CFG: RUN Position */ #define CCU1_CLK_M4_SCU_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SCU_CFG: RUN Mask */ #define CCU1_CLK_M4_SCU_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCU_CFG: AUTO Position */ #define CCU1_CLK_M4_SCU_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SCU_CFG: AUTO Mask */ #define CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Position */ #define CCU1_CLK_M4_SCU_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCU_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCU_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SCU_STAT ---------------------------- */ #define CCU1_CLK_M4_SCU_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SCU_STAT: RUN Position */ #define CCU1_CLK_M4_SCU_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SCU_STAT: RUN Mask */ #define CCU1_CLK_M4_SCU_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SCU_STAT: AUTO Position */ #define CCU1_CLK_M4_SCU_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SCU_STAT: AUTO Mask */ #define CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Position */ #define CCU1_CLK_M4_SCU_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SCU_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SCU_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_CREG_CFG ---------------------------- */ #define CCU1_CLK_M4_CREG_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_CREG_CFG: RUN Position */ #define CCU1_CLK_M4_CREG_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_RUN_Pos) /*!< CCU1 CLK_M4_CREG_CFG: RUN Mask */ #define CCU1_CLK_M4_CREG_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_CREG_CFG: AUTO Position */ #define CCU1_CLK_M4_CREG_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_CREG_CFG: AUTO Mask */ #define CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Position */ #define CCU1_CLK_M4_CREG_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_CREG_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_CREG_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_CREG_STAT --------------------------- */ #define CCU1_CLK_M4_CREG_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_CREG_STAT: RUN Position */ #define CCU1_CLK_M4_CREG_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_RUN_Pos) /*!< CCU1 CLK_M4_CREG_STAT: RUN Mask */ #define CCU1_CLK_M4_CREG_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_CREG_STAT: AUTO Position */ #define CCU1_CLK_M4_CREG_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_CREG_STAT: AUTO Mask */ #define CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Position */ #define CCU1_CLK_M4_CREG_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_CREG_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_CREG_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_RITIMER_CFG -------------------------- */ #define CCU1_CLK_M4_RITIMER_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Position */ #define CCU1_CLK_M4_RITIMER_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_RUN_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: RUN Mask */ #define CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Position */ #define CCU1_CLK_M4_RITIMER_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: AUTO Mask */ #define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Position */ #define CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_RITIMER_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_RITIMER_CFG: WAKEUP Mask */ /* -------------------------- CCU1_CLK_M4_RITIMER_STAT -------------------------- */ #define CCU1_CLK_M4_RITIMER_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Position */ #define CCU1_CLK_M4_RITIMER_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_RUN_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: RUN Mask */ #define CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Position */ #define CCU1_CLK_M4_RITIMER_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: AUTO Mask */ #define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Position */ #define CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_RITIMER_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_RITIMER_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_USART2_CFG --------------------------- */ #define CCU1_CLK_M4_USART2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART2_CFG: RUN Position */ #define CCU1_CLK_M4_USART2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART2_CFG: RUN Mask */ #define CCU1_CLK_M4_USART2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART2_CFG: AUTO Position */ #define CCU1_CLK_M4_USART2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART2_CFG: AUTO Mask */ #define CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Position */ #define CCU1_CLK_M4_USART2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART2_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_USART2_STAT -------------------------- */ #define CCU1_CLK_M4_USART2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART2_STAT: RUN Position */ #define CCU1_CLK_M4_USART2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART2_STAT: RUN Mask */ #define CCU1_CLK_M4_USART2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART2_STAT: AUTO Position */ #define CCU1_CLK_M4_USART2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART2_STAT: AUTO Mask */ #define CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Position */ #define CCU1_CLK_M4_USART2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART2_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_USART3_CFG --------------------------- */ #define CCU1_CLK_M4_USART3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_USART3_CFG: RUN Position */ #define CCU1_CLK_M4_USART3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_RUN_Pos) /*!< CCU1 CLK_M4_USART3_CFG: RUN Mask */ #define CCU1_CLK_M4_USART3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART3_CFG: AUTO Position */ #define CCU1_CLK_M4_USART3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_USART3_CFG: AUTO Mask */ #define CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Position */ #define CCU1_CLK_M4_USART3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART3_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_USART3_STAT -------------------------- */ #define CCU1_CLK_M4_USART3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_USART3_STAT: RUN Position */ #define CCU1_CLK_M4_USART3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_RUN_Pos) /*!< CCU1 CLK_M4_USART3_STAT: RUN Mask */ #define CCU1_CLK_M4_USART3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_USART3_STAT: AUTO Position */ #define CCU1_CLK_M4_USART3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_USART3_STAT: AUTO Mask */ #define CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Position */ #define CCU1_CLK_M4_USART3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_USART3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_USART3_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_TIMER2_CFG --------------------------- */ #define CCU1_CLK_M4_TIMER2_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Position */ #define CCU1_CLK_M4_TIMER2_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: RUN Mask */ #define CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Position */ #define CCU1_CLK_M4_TIMER2_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: AUTO Mask */ #define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Position */ #define CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER2_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER2_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_TIMER2_STAT -------------------------- */ #define CCU1_CLK_M4_TIMER2_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Position */ #define CCU1_CLK_M4_TIMER2_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: RUN Mask */ #define CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Position */ #define CCU1_CLK_M4_TIMER2_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: AUTO Mask */ #define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Position */ #define CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER2_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER2_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_TIMER3_CFG --------------------------- */ #define CCU1_CLK_M4_TIMER3_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Position */ #define CCU1_CLK_M4_TIMER3_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_RUN_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: RUN Mask */ #define CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Position */ #define CCU1_CLK_M4_TIMER3_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: AUTO Mask */ #define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Position */ #define CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER3_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER3_CFG: WAKEUP Mask */ /* --------------------------- CCU1_CLK_M4_TIMER3_STAT -------------------------- */ #define CCU1_CLK_M4_TIMER3_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Position */ #define CCU1_CLK_M4_TIMER3_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_RUN_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: RUN Mask */ #define CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Position */ #define CCU1_CLK_M4_TIMER3_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: AUTO Mask */ #define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Position */ #define CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_TIMER3_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_TIMER3_STAT: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SSP1_CFG ---------------------------- */ #define CCU1_CLK_M4_SSP1_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP1_CFG: RUN Position */ #define CCU1_CLK_M4_SSP1_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_RUN_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: RUN Mask */ #define CCU1_CLK_M4_SSP1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Position */ #define CCU1_CLK_M4_SSP1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: AUTO Mask */ #define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Position */ #define CCU1_CLK_M4_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP1_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_SSP1_STAT --------------------------- */ #define CCU1_CLK_M4_SSP1_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_SSP1_STAT: RUN Position */ #define CCU1_CLK_M4_SSP1_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_RUN_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: RUN Mask */ #define CCU1_CLK_M4_SSP1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Position */ #define CCU1_CLK_M4_SSP1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: AUTO Mask */ #define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Position */ #define CCU1_CLK_M4_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_SSP1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_SSP1_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_M4_QEI_CFG ---------------------------- */ #define CCU1_CLK_M4_QEI_CFG_RUN_Pos 0 /*!< CCU1 CLK_M4_QEI_CFG: RUN Position */ #define CCU1_CLK_M4_QEI_CFG_RUN_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_RUN_Pos) /*!< CCU1 CLK_M4_QEI_CFG: RUN Mask */ #define CCU1_CLK_M4_QEI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_M4_QEI_CFG: AUTO Position */ #define CCU1_CLK_M4_QEI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_AUTO_Pos) /*!< CCU1 CLK_M4_QEI_CFG: AUTO Mask */ #define CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Position */ #define CCU1_CLK_M4_QEI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_QEI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_M4_QEI_CFG: WAKEUP Mask */ /* ---------------------------- CCU1_CLK_M4_QEI_STAT ---------------------------- */ #define CCU1_CLK_M4_QEI_STAT_RUN_Pos 0 /*!< CCU1 CLK_M4_QEI_STAT: RUN Position */ #define CCU1_CLK_M4_QEI_STAT_RUN_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_RUN_Pos) /*!< CCU1 CLK_M4_QEI_STAT: RUN Mask */ #define CCU1_CLK_M4_QEI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_M4_QEI_STAT: AUTO Position */ #define CCU1_CLK_M4_QEI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_AUTO_Pos) /*!< CCU1 CLK_M4_QEI_STAT: AUTO Mask */ #define CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Position */ #define CCU1_CLK_M4_QEI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_M4_QEI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_M4_QEI_STAT: WAKEUP Mask */ /* --------------------------- CCU1_CLK_PERIPH_BUS_CFG -------------------------- */ #define CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Position */ #define CCU1_CLK_PERIPH_BUS_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: RUN Mask */ #define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Position */ #define CCU1_CLK_PERIPH_BUS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: AUTO Mask */ #define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Position */ #define CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_CFG: WAKEUP Mask */ /* -------------------------- CCU1_CLK_PERIPH_BUS_STAT -------------------------- */ #define CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Position */ #define CCU1_CLK_PERIPH_BUS_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: RUN Mask */ #define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Position */ #define CCU1_CLK_PERIPH_BUS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: AUTO Mask */ #define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Position */ #define CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_BUS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_BUS_STAT: WAKEUP Mask */ /* -------------------------- CCU1_CLK_PERIPH_CORE_CFG -------------------------- */ #define CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Position */ #define CCU1_CLK_PERIPH_CORE_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: RUN Mask */ #define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Position */ #define CCU1_CLK_PERIPH_CORE_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: AUTO Mask */ #define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Position */ #define CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_CFG: WAKEUP Mask */ /* -------------------------- CCU1_CLK_PERIPH_CORE_STAT ------------------------- */ #define CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Position */ #define CCU1_CLK_PERIPH_CORE_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: RUN Mask */ #define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Position */ #define CCU1_CLK_PERIPH_CORE_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: AUTO Mask */ #define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Position */ #define CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_CORE_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_CORE_STAT: WAKEUP Mask */ /* -------------------------- CCU1_CLK_PERIPH_SGPIO_CFG ------------------------- */ #define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Position */ #define CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_RUN_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: RUN Mask */ #define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Position */ #define CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_AUTO_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: AUTO Mask */ #define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Position */ #define CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_CFG_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_CFG: WAKEUP Mask */ /* ------------------------- CCU1_CLK_PERIPH_SGPIO_STAT ------------------------- */ #define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos 0 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Position */ #define CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_RUN_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: RUN Mask */ #define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos 1 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Position */ #define CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_AUTO_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: AUTO Mask */ #define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Position */ #define CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_PERIPH_SGPIO_STAT_WAKEUP_Pos) /*!< CCU1 CLK_PERIPH_SGPIO_STAT: WAKEUP Mask */ /* ------------------------------ CCU1_CLK_USB0_CFG ----------------------------- */ #define CCU1_CLK_USB0_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB0_CFG: RUN Position */ #define CCU1_CLK_USB0_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB0_CFG_RUN_Pos) /*!< CCU1 CLK_USB0_CFG: RUN Mask */ #define CCU1_CLK_USB0_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB0_CFG: AUTO Position */ #define CCU1_CLK_USB0_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB0_CFG_AUTO_Pos) /*!< CCU1 CLK_USB0_CFG: AUTO Mask */ #define CCU1_CLK_USB0_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_CFG: WAKEUP Position */ #define CCU1_CLK_USB0_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB0_CFG: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_USB0_STAT ----------------------------- */ #define CCU1_CLK_USB0_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB0_STAT: RUN Position */ #define CCU1_CLK_USB0_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB0_STAT_RUN_Pos) /*!< CCU1 CLK_USB0_STAT: RUN Mask */ #define CCU1_CLK_USB0_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB0_STAT: AUTO Position */ #define CCU1_CLK_USB0_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB0_STAT_AUTO_Pos) /*!< CCU1 CLK_USB0_STAT: AUTO Mask */ #define CCU1_CLK_USB0_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB0_STAT: WAKEUP Position */ #define CCU1_CLK_USB0_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB0_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB0_STAT: WAKEUP Mask */ /* ------------------------------ CCU1_CLK_USB1_CFG ----------------------------- */ #define CCU1_CLK_USB1_CFG_RUN_Pos 0 /*!< CCU1 CLK_USB1_CFG: RUN Position */ #define CCU1_CLK_USB1_CFG_RUN_Msk (0x01UL << CCU1_CLK_USB1_CFG_RUN_Pos) /*!< CCU1 CLK_USB1_CFG: RUN Mask */ #define CCU1_CLK_USB1_CFG_AUTO_Pos 1 /*!< CCU1 CLK_USB1_CFG: AUTO Position */ #define CCU1_CLK_USB1_CFG_AUTO_Msk (0x01UL << CCU1_CLK_USB1_CFG_AUTO_Pos) /*!< CCU1 CLK_USB1_CFG: AUTO Mask */ #define CCU1_CLK_USB1_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_CFG: WAKEUP Position */ #define CCU1_CLK_USB1_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_CFG_WAKEUP_Pos) /*!< CCU1 CLK_USB1_CFG: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_USB1_STAT ----------------------------- */ #define CCU1_CLK_USB1_STAT_RUN_Pos 0 /*!< CCU1 CLK_USB1_STAT: RUN Position */ #define CCU1_CLK_USB1_STAT_RUN_Msk (0x01UL << CCU1_CLK_USB1_STAT_RUN_Pos) /*!< CCU1 CLK_USB1_STAT: RUN Mask */ #define CCU1_CLK_USB1_STAT_AUTO_Pos 1 /*!< CCU1 CLK_USB1_STAT: AUTO Position */ #define CCU1_CLK_USB1_STAT_AUTO_Msk (0x01UL << CCU1_CLK_USB1_STAT_AUTO_Pos) /*!< CCU1 CLK_USB1_STAT: AUTO Mask */ #define CCU1_CLK_USB1_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_USB1_STAT: WAKEUP Position */ #define CCU1_CLK_USB1_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_USB1_STAT_WAKEUP_Pos) /*!< CCU1 CLK_USB1_STAT: WAKEUP Mask */ /* ------------------------------ CCU1_CLK_SPI_CFG ------------------------------ */ #define CCU1_CLK_SPI_CFG_RUN_Pos 0 /*!< CCU1 CLK_SPI_CFG: RUN Position */ #define CCU1_CLK_SPI_CFG_RUN_Msk (0x01UL << CCU1_CLK_SPI_CFG_RUN_Pos) /*!< CCU1 CLK_SPI_CFG: RUN Mask */ #define CCU1_CLK_SPI_CFG_AUTO_Pos 1 /*!< CCU1 CLK_SPI_CFG: AUTO Position */ #define CCU1_CLK_SPI_CFG_AUTO_Msk (0x01UL << CCU1_CLK_SPI_CFG_AUTO_Pos) /*!< CCU1 CLK_SPI_CFG: AUTO Mask */ #define CCU1_CLK_SPI_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_SPI_CFG: WAKEUP Position */ #define CCU1_CLK_SPI_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_SPI_CFG_WAKEUP_Pos) /*!< CCU1 CLK_SPI_CFG: WAKEUP Mask */ /* ------------------------------ CCU1_CLK_SPI_STAT ----------------------------- */ #define CCU1_CLK_SPI_STAT_RUN_Pos 0 /*!< CCU1 CLK_SPI_STAT: RUN Position */ #define CCU1_CLK_SPI_STAT_RUN_Msk (0x01UL << CCU1_CLK_SPI_STAT_RUN_Pos) /*!< CCU1 CLK_SPI_STAT: RUN Mask */ #define CCU1_CLK_SPI_STAT_AUTO_Pos 1 /*!< CCU1 CLK_SPI_STAT: AUTO Position */ #define CCU1_CLK_SPI_STAT_AUTO_Msk (0x01UL << CCU1_CLK_SPI_STAT_AUTO_Pos) /*!< CCU1 CLK_SPI_STAT: AUTO Mask */ #define CCU1_CLK_SPI_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_SPI_STAT: WAKEUP Position */ #define CCU1_CLK_SPI_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_SPI_STAT_WAKEUP_Pos) /*!< CCU1 CLK_SPI_STAT: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_ADCHS_CFG ----------------------------- */ #define CCU1_CLK_ADCHS_CFG_RUN_Pos 0 /*!< CCU1 CLK_ADCHS_CFG: RUN Position */ #define CCU1_CLK_ADCHS_CFG_RUN_Msk (0x01UL << CCU1_CLK_ADCHS_CFG_RUN_Pos) /*!< CCU1 CLK_ADCHS_CFG: RUN Mask */ #define CCU1_CLK_ADCHS_CFG_AUTO_Pos 1 /*!< CCU1 CLK_ADCHS_CFG: AUTO Position */ #define CCU1_CLK_ADCHS_CFG_AUTO_Msk (0x01UL << CCU1_CLK_ADCHS_CFG_AUTO_Pos) /*!< CCU1 CLK_ADCHS_CFG: AUTO Mask */ #define CCU1_CLK_ADCHS_CFG_WAKEUP_Pos 2 /*!< CCU1 CLK_ADCHS_CFG: WAKEUP Position */ #define CCU1_CLK_ADCHS_CFG_WAKEUP_Msk (0x01UL << CCU1_CLK_ADCHS_CFG_WAKEUP_Pos) /*!< CCU1 CLK_ADCHS_CFG: WAKEUP Mask */ /* ----------------------------- CCU1_CLK_ADCHS_STAT ---------------------------- */ #define CCU1_CLK_ADCHS_STAT_RUN_Pos 0 /*!< CCU1 CLK_ADCHS_STAT: RUN Position */ #define CCU1_CLK_ADCHS_STAT_RUN_Msk (0x01UL << CCU1_CLK_ADCHS_STAT_RUN_Pos) /*!< CCU1 CLK_ADCHS_STAT: RUN Mask */ #define CCU1_CLK_ADCHS_STAT_AUTO_Pos 1 /*!< CCU1 CLK_ADCHS_STAT: AUTO Position */ #define CCU1_CLK_ADCHS_STAT_AUTO_Msk (0x01UL << CCU1_CLK_ADCHS_STAT_AUTO_Pos) /*!< CCU1 CLK_ADCHS_STAT: AUTO Mask */ #define CCU1_CLK_ADCHS_STAT_WAKEUP_Pos 2 /*!< CCU1 CLK_ADCHS_STAT: WAKEUP Position */ #define CCU1_CLK_ADCHS_STAT_WAKEUP_Msk (0x01UL << CCU1_CLK_ADCHS_STAT_WAKEUP_Pos) /*!< CCU1 CLK_ADCHS_STAT: WAKEUP Mask */ /* ================================================================================ */ /* ================ struct 'CCU2' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- CCU2_PM ---------------------------------- */ #define CCU2_PM_PD_Pos 0 /*!< CCU2 PM: PD Position */ #define CCU2_PM_PD_Msk (0x01UL << CCU2_PM_PD_Pos) /*!< CCU2 PM: PD Mask */ /* ------------------------------- CCU2_BASE_STAT ------------------------------- */ #define CCU2_BASE_STAT_BASE_UART3_CLK_Pos 1 /*!< CCU2 BASE_STAT: BASE_UART3_CLK Position */ #define CCU2_BASE_STAT_BASE_UART3_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART3_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART3_CLK Mask */ #define CCU2_BASE_STAT_BASE_UART2_CLK_Pos 2 /*!< CCU2 BASE_STAT: BASE_UART2_CLK Position */ #define CCU2_BASE_STAT_BASE_UART2_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART2_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART2_CLK Mask */ #define CCU2_BASE_STAT_BASE_UART1_CLK_Pos 3 /*!< CCU2 BASE_STAT: BASE_UART1_CLK Position */ #define CCU2_BASE_STAT_BASE_UART1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART1_CLK Mask */ #define CCU2_BASE_STAT_BASE_UART0_CLK_Pos 4 /*!< CCU2 BASE_STAT: BASE_UART0_CLK Position */ #define CCU2_BASE_STAT_BASE_UART0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_UART0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_UART0_CLK Mask */ #define CCU2_BASE_STAT_BASE_SSP1_CLK_Pos 5 /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Position */ #define CCU2_BASE_STAT_BASE_SSP1_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP1_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP1_CLK Mask */ #define CCU2_BASE_STAT_BASE_SSP0_CLK_Pos 6 /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Position */ #define CCU2_BASE_STAT_BASE_SSP0_CLK_Msk (0x01UL << CCU2_BASE_STAT_BASE_SSP0_CLK_Pos) /*!< CCU2 BASE_STAT: BASE_SSP0_CLK Mask */ /* ----------------------------- CCU2_CLK_AUDIO_CFG ----------------------------- */ #define CCU2_CLK_AUDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_AUDIO_CFG: RUN Position */ #define CCU2_CLK_AUDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_AUDIO_CFG_RUN_Pos) /*!< CCU2 CLK_AUDIO_CFG: RUN Mask */ #define CCU2_CLK_AUDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_AUDIO_CFG: AUTO Position */ #define CCU2_CLK_AUDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_AUDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_AUDIO_CFG: AUTO Mask */ #define CCU2_CLK_AUDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_AUDIO_CFG: WAKEUP Position */ #define CCU2_CLK_AUDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_AUDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_AUDIO_CFG: WAKEUP Mask */ /* ----------------------------- CCU2_CLK_AUDIO_STAT ---------------------------- */ #define CCU2_CLK_AUDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_AUDIO_STAT: RUN Position */ #define CCU2_CLK_AUDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_AUDIO_STAT_RUN_Pos) /*!< CCU2 CLK_AUDIO_STAT: RUN Mask */ #define CCU2_CLK_AUDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_AUDIO_STAT: AUTO Position */ #define CCU2_CLK_AUDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_AUDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_AUDIO_STAT: AUTO Mask */ #define CCU2_CLK_AUDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_AUDIO_STAT: WAKEUP Position */ #define CCU2_CLK_AUDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_AUDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_AUDIO_STAT: WAKEUP Mask */ /* -------------------------- CCU2_CLK_APB2_USART3_CFG -------------------------- */ #define CCU2_CLK_APB2_USART3_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_CFG: RUN Position */ #define CCU2_CLK_APB2_USART3_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: RUN Mask */ #define CCU2_CLK_APB2_USART3_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Position */ #define CCU2_CLK_APB2_USART3_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: AUTO Mask */ #define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Position */ #define CCU2_CLK_APB2_USART3_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_CFG: WAKEUP Mask */ /* -------------------------- CCU2_CLK_APB2_USART3_STAT ------------------------- */ #define CCU2_CLK_APB2_USART3_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART3_STAT: RUN Position */ #define CCU2_CLK_APB2_USART3_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: RUN Mask */ #define CCU2_CLK_APB2_USART3_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Position */ #define CCU2_CLK_APB2_USART3_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: AUTO Mask */ #define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Position */ #define CCU2_CLK_APB2_USART3_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART3_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART3_STAT: WAKEUP Mask */ /* -------------------------- CCU2_CLK_APB2_USART2_CFG -------------------------- */ #define CCU2_CLK_APB2_USART2_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_CFG: RUN Position */ #define CCU2_CLK_APB2_USART2_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: RUN Mask */ #define CCU2_CLK_APB2_USART2_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Position */ #define CCU2_CLK_APB2_USART2_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: AUTO Mask */ #define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Position */ #define CCU2_CLK_APB2_USART2_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_CFG: WAKEUP Mask */ /* -------------------------- CCU2_CLK_APB2_USART2_STAT ------------------------- */ #define CCU2_CLK_APB2_USART2_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_USART2_STAT: RUN Position */ #define CCU2_CLK_APB2_USART2_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: RUN Mask */ #define CCU2_CLK_APB2_USART2_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Position */ #define CCU2_CLK_APB2_USART2_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: AUTO Mask */ #define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Position */ #define CCU2_CLK_APB2_USART2_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_USART2_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_USART2_STAT: WAKEUP Mask */ /* ------------------------- CCU2_CLK_APB0_UART1_BUS_CFG ------------------------ */ #define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Position */ #define CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: RUN Mask */ #define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Position */ #define CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: AUTO Mask */ #define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Position */ #define CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_BUS_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_BUS_CFG: WAKEUP Mask */ /* -------------------------- CCU2_CLK_APB0_UART1_STAT -------------------------- */ #define CCU2_CLK_APB0_UART1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_UART1_STAT: RUN Position */ #define CCU2_CLK_APB0_UART1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: RUN Mask */ #define CCU2_CLK_APB0_UART1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Position */ #define CCU2_CLK_APB0_UART1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: AUTO Mask */ #define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Position */ #define CCU2_CLK_APB0_UART1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_UART1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_UART1_STAT: WAKEUP Mask */ /* -------------------------- CCU2_CLK_APB0_USART0_CFG -------------------------- */ #define CCU2_CLK_APB0_USART0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_CFG: RUN Position */ #define CCU2_CLK_APB0_USART0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: RUN Mask */ #define CCU2_CLK_APB0_USART0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Position */ #define CCU2_CLK_APB0_USART0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: AUTO Mask */ #define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Position */ #define CCU2_CLK_APB0_USART0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_CFG: WAKEUP Mask */ /* -------------------------- CCU2_CLK_APB0_USART0_STAT ------------------------- */ #define CCU2_CLK_APB0_USART0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_USART0_STAT: RUN Position */ #define CCU2_CLK_APB0_USART0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: RUN Mask */ #define CCU2_CLK_APB0_USART0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Position */ #define CCU2_CLK_APB0_USART0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: AUTO Mask */ #define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Position */ #define CCU2_CLK_APB0_USART0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_USART0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_USART0_STAT: WAKEUP Mask */ /* --------------------------- CCU2_CLK_APB2_SSP1_CFG --------------------------- */ #define CCU2_CLK_APB2_SSP1_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Position */ #define CCU2_CLK_APB2_SSP1_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: RUN Mask */ #define CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Position */ #define CCU2_CLK_APB2_SSP1_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: AUTO Mask */ #define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Position */ #define CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_CFG: WAKEUP Mask */ /* --------------------------- CCU2_CLK_APB2_SSP1_STAT -------------------------- */ #define CCU2_CLK_APB2_SSP1_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Position */ #define CCU2_CLK_APB2_SSP1_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_RUN_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: RUN Mask */ #define CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Position */ #define CCU2_CLK_APB2_SSP1_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_AUTO_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: AUTO Mask */ #define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Position */ #define CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB2_SSP1_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB2_SSP1_STAT: WAKEUP Mask */ /* --------------------------- CCU2_CLK_APB0_SSP0_CFG --------------------------- */ #define CCU2_CLK_APB0_SSP0_CFG_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Position */ #define CCU2_CLK_APB0_SSP0_CFG_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: RUN Mask */ #define CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Position */ #define CCU2_CLK_APB0_SSP0_CFG_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: AUTO Mask */ #define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Position */ #define CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_CFG_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_CFG: WAKEUP Mask */ /* --------------------------- CCU2_CLK_APB0_SSP0_STAT -------------------------- */ #define CCU2_CLK_APB0_SSP0_STAT_RUN_Pos 0 /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Position */ #define CCU2_CLK_APB0_SSP0_STAT_RUN_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_RUN_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: RUN Mask */ #define CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos 1 /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Position */ #define CCU2_CLK_APB0_SSP0_STAT_AUTO_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_AUTO_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: AUTO Mask */ #define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Position */ #define CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_APB0_SSP0_STAT_WAKEUP_Pos) /*!< CCU2 CLK_APB0_SSP0_STAT: WAKEUP Mask */ /* ------------------------------ CCU2_CLK_SDIO_CFG ----------------------------- */ #define CCU2_CLK_SDIO_CFG_RUN_Pos 0 /*!< CCU2 CLK_SDIO_CFG: RUN Position */ #define CCU2_CLK_SDIO_CFG_RUN_Msk (0x01UL << CCU2_CLK_SDIO_CFG_RUN_Pos) /*!< CCU2 CLK_SDIO_CFG: RUN Mask */ #define CCU2_CLK_SDIO_CFG_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_CFG: AUTO Position */ #define CCU2_CLK_SDIO_CFG_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_CFG_AUTO_Pos) /*!< CCU2 CLK_SDIO_CFG: AUTO Mask */ #define CCU2_CLK_SDIO_CFG_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_CFG: WAKEUP Position */ #define CCU2_CLK_SDIO_CFG_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_CFG_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_CFG: WAKEUP Mask */ /* ----------------------------- CCU2_CLK_SDIO_STAT ----------------------------- */ #define CCU2_CLK_SDIO_STAT_RUN_Pos 0 /*!< CCU2 CLK_SDIO_STAT: RUN Position */ #define CCU2_CLK_SDIO_STAT_RUN_Msk (0x01UL << CCU2_CLK_SDIO_STAT_RUN_Pos) /*!< CCU2 CLK_SDIO_STAT: RUN Mask */ #define CCU2_CLK_SDIO_STAT_AUTO_Pos 1 /*!< CCU2 CLK_SDIO_STAT: AUTO Position */ #define CCU2_CLK_SDIO_STAT_AUTO_Msk (0x01UL << CCU2_CLK_SDIO_STAT_AUTO_Pos) /*!< CCU2 CLK_SDIO_STAT: AUTO Mask */ #define CCU2_CLK_SDIO_STAT_WAKEUP_Pos 2 /*!< CCU2 CLK_SDIO_STAT: WAKEUP Position */ #define CCU2_CLK_SDIO_STAT_WAKEUP_Msk (0x01UL << CCU2_CLK_SDIO_STAT_WAKEUP_Pos) /*!< CCU2 CLK_SDIO_STAT: WAKEUP Mask */ /* ================================================================================ */ /* ================ struct 'RGU' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------- RGU_RESET_CTRL0 ------------------------------ */ #define RGU_RESET_CTRL0_CORE_RST_Pos 0 /*!< RGU RESET_CTRL0: CORE_RST Position */ #define RGU_RESET_CTRL0_CORE_RST_Msk (0x01UL << RGU_RESET_CTRL0_CORE_RST_Pos) /*!< RGU RESET_CTRL0: CORE_RST Mask */ #define RGU_RESET_CTRL0_PERIPH_RST_Pos 1 /*!< RGU RESET_CTRL0: PERIPH_RST Position */ #define RGU_RESET_CTRL0_PERIPH_RST_Msk (0x01UL << RGU_RESET_CTRL0_PERIPH_RST_Pos) /*!< RGU RESET_CTRL0: PERIPH_RST Mask */ #define RGU_RESET_CTRL0_MASTER_RST_Pos 2 /*!< RGU RESET_CTRL0: MASTER_RST Position */ #define RGU_RESET_CTRL0_MASTER_RST_Msk (0x01UL << RGU_RESET_CTRL0_MASTER_RST_Pos) /*!< RGU RESET_CTRL0: MASTER_RST Mask */ #define RGU_RESET_CTRL0_WWDT_RST_Pos 4 /*!< RGU RESET_CTRL0: WWDT_RST Position */ #define RGU_RESET_CTRL0_WWDT_RST_Msk (0x01UL << RGU_RESET_CTRL0_WWDT_RST_Pos) /*!< RGU RESET_CTRL0: WWDT_RST Mask */ #define RGU_RESET_CTRL0_CREG_RST_Pos 5 /*!< RGU RESET_CTRL0: CREG_RST Position */ #define RGU_RESET_CTRL0_CREG_RST_Msk (0x01UL << RGU_RESET_CTRL0_CREG_RST_Pos) /*!< RGU RESET_CTRL0: CREG_RST Mask */ #define RGU_RESET_CTRL0_BUS_RST_Pos 8 /*!< RGU RESET_CTRL0: BUS_RST Position */ #define RGU_RESET_CTRL0_BUS_RST_Msk (0x01UL << RGU_RESET_CTRL0_BUS_RST_Pos) /*!< RGU RESET_CTRL0: BUS_RST Mask */ #define RGU_RESET_CTRL0_SCU_RST_Pos 9 /*!< RGU RESET_CTRL0: SCU_RST Position */ #define RGU_RESET_CTRL0_SCU_RST_Msk (0x01UL << RGU_RESET_CTRL0_SCU_RST_Pos) /*!< RGU RESET_CTRL0: SCU_RST Mask */ #define RGU_RESET_CTRL0_M0_SUB_RST_Pos 12 /*!< RGU RESET_CTRL0: M0_SUB_RST Position */ #define RGU_RESET_CTRL0_M0_SUB_RST_Msk (0x01UL << RGU_RESET_CTRL0_M0_SUB_RST_Pos) /*!< RGU RESET_CTRL0: M0_SUB_RST Mask */ #define RGU_RESET_CTRL0_M4_RST_Pos 13 /*!< RGU RESET_CTRL0: M4_RST Position */ #define RGU_RESET_CTRL0_M4_RST_Msk (0x01UL << RGU_RESET_CTRL0_M4_RST_Pos) /*!< RGU RESET_CTRL0: M4_RST Mask */ #define RGU_RESET_CTRL0_LCD_RST_Pos 16 /*!< RGU RESET_CTRL0: LCD_RST Position */ #define RGU_RESET_CTRL0_LCD_RST_Msk (0x01UL << RGU_RESET_CTRL0_LCD_RST_Pos) /*!< RGU RESET_CTRL0: LCD_RST Mask */ #define RGU_RESET_CTRL0_USB0_RST_Pos 17 /*!< RGU RESET_CTRL0: USB0_RST Position */ #define RGU_RESET_CTRL0_USB0_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB0_RST_Pos) /*!< RGU RESET_CTRL0: USB0_RST Mask */ #define RGU_RESET_CTRL0_USB1_RST_Pos 18 /*!< RGU RESET_CTRL0: USB1_RST Position */ #define RGU_RESET_CTRL0_USB1_RST_Msk (0x01UL << RGU_RESET_CTRL0_USB1_RST_Pos) /*!< RGU RESET_CTRL0: USB1_RST Mask */ #define RGU_RESET_CTRL0_DMA_RST_Pos 19 /*!< RGU RESET_CTRL0: DMA_RST Position */ #define RGU_RESET_CTRL0_DMA_RST_Msk (0x01UL << RGU_RESET_CTRL0_DMA_RST_Pos) /*!< RGU RESET_CTRL0: DMA_RST Mask */ #define RGU_RESET_CTRL0_SDIO_RST_Pos 20 /*!< RGU RESET_CTRL0: SDIO_RST Position */ #define RGU_RESET_CTRL0_SDIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_SDIO_RST_Pos) /*!< RGU RESET_CTRL0: SDIO_RST Mask */ #define RGU_RESET_CTRL0_EMC_RST_Pos 21 /*!< RGU RESET_CTRL0: EMC_RST Position */ #define RGU_RESET_CTRL0_EMC_RST_Msk (0x01UL << RGU_RESET_CTRL0_EMC_RST_Pos) /*!< RGU RESET_CTRL0: EMC_RST Mask */ #define RGU_RESET_CTRL0_ETHERNET_RST_Pos 22 /*!< RGU RESET_CTRL0: ETHERNET_RST Position */ #define RGU_RESET_CTRL0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_CTRL0_ETHERNET_RST_Pos) /*!< RGU RESET_CTRL0: ETHERNET_RST Mask */ #define RGU_RESET_CTRL0_FLASHA_RST_Pos 25 /*!< RGU RESET_CTRL0: FLASHA_RST Position */ #define RGU_RESET_CTRL0_FLASHA_RST_Msk (0x01UL << RGU_RESET_CTRL0_FLASHA_RST_Pos) /*!< RGU RESET_CTRL0: FLASHA_RST Mask */ #define RGU_RESET_CTRL0_EEPROM_RST_Pos 27 /*!< RGU RESET_CTRL0: EEPROM_RST Position */ #define RGU_RESET_CTRL0_EEPROM_RST_Msk (0x01UL << RGU_RESET_CTRL0_EEPROM_RST_Pos) /*!< RGU RESET_CTRL0: EEPROM_RST Mask */ #define RGU_RESET_CTRL0_GPIO_RST_Pos 28 /*!< RGU RESET_CTRL0: GPIO_RST Position */ #define RGU_RESET_CTRL0_GPIO_RST_Msk (0x01UL << RGU_RESET_CTRL0_GPIO_RST_Pos) /*!< RGU RESET_CTRL0: GPIO_RST Mask */ #define RGU_RESET_CTRL0_FLASHB_RST_Pos 29 /*!< RGU RESET_CTRL0: FLASHB_RST Position */ #define RGU_RESET_CTRL0_FLASHB_RST_Msk (0x01UL << RGU_RESET_CTRL0_FLASHB_RST_Pos) /*!< RGU RESET_CTRL0: FLASHB_RST Mask */ /* ------------------------------- RGU_RESET_CTRL1 ------------------------------ */ #define RGU_RESET_CTRL1_TIMER0_RST_Pos 0 /*!< RGU RESET_CTRL1: TIMER0_RST Position */ #define RGU_RESET_CTRL1_TIMER0_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER0_RST_Pos) /*!< RGU RESET_CTRL1: TIMER0_RST Mask */ #define RGU_RESET_CTRL1_TIMER1_RST_Pos 1 /*!< RGU RESET_CTRL1: TIMER1_RST Position */ #define RGU_RESET_CTRL1_TIMER1_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER1_RST_Pos) /*!< RGU RESET_CTRL1: TIMER1_RST Mask */ #define RGU_RESET_CTRL1_TIMER2_RST_Pos 2 /*!< RGU RESET_CTRL1: TIMER2_RST Position */ #define RGU_RESET_CTRL1_TIMER2_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER2_RST_Pos) /*!< RGU RESET_CTRL1: TIMER2_RST Mask */ #define RGU_RESET_CTRL1_TIMER3_RST_Pos 3 /*!< RGU RESET_CTRL1: TIMER3_RST Position */ #define RGU_RESET_CTRL1_TIMER3_RST_Msk (0x01UL << RGU_RESET_CTRL1_TIMER3_RST_Pos) /*!< RGU RESET_CTRL1: TIMER3_RST Mask */ #define RGU_RESET_CTRL1_RITIMER_RST_Pos 4 /*!< RGU RESET_CTRL1: RITIMER_RST Position */ #define RGU_RESET_CTRL1_RITIMER_RST_Msk (0x01UL << RGU_RESET_CTRL1_RITIMER_RST_Pos) /*!< RGU RESET_CTRL1: RITIMER_RST Mask */ #define RGU_RESET_CTRL1_SCT_RST_Pos 5 /*!< RGU RESET_CTRL1: SCT_RST Position */ #define RGU_RESET_CTRL1_SCT_RST_Msk (0x01UL << RGU_RESET_CTRL1_SCT_RST_Pos) /*!< RGU RESET_CTRL1: SCT_RST Mask */ #define RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Position */ #define RGU_RESET_CTRL1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_CTRL1_MOTOCONPWM_RST_Pos) /*!< RGU RESET_CTRL1: MOTOCONPWM_RST Mask */ #define RGU_RESET_CTRL1_QEI_RST_Pos 7 /*!< RGU RESET_CTRL1: QEI_RST Position */ #define RGU_RESET_CTRL1_QEI_RST_Msk (0x01UL << RGU_RESET_CTRL1_QEI_RST_Pos) /*!< RGU RESET_CTRL1: QEI_RST Mask */ #define RGU_RESET_CTRL1_ADC0_RST_Pos 8 /*!< RGU RESET_CTRL1: ADC0_RST Position */ #define RGU_RESET_CTRL1_ADC0_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC0_RST_Pos) /*!< RGU RESET_CTRL1: ADC0_RST Mask */ #define RGU_RESET_CTRL1_ADC1_RST_Pos 9 /*!< RGU RESET_CTRL1: ADC1_RST Position */ #define RGU_RESET_CTRL1_ADC1_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADC1_RST_Pos) /*!< RGU RESET_CTRL1: ADC1_RST Mask */ #define RGU_RESET_CTRL1_DAC_RST_Pos 10 /*!< RGU RESET_CTRL1: DAC_RST Position */ #define RGU_RESET_CTRL1_DAC_RST_Msk (0x01UL << RGU_RESET_CTRL1_DAC_RST_Pos) /*!< RGU RESET_CTRL1: DAC_RST Mask */ #define RGU_RESET_CTRL1_UART0_RST_Pos 12 /*!< RGU RESET_CTRL1: UART0_RST Position */ #define RGU_RESET_CTRL1_UART0_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART0_RST_Pos) /*!< RGU RESET_CTRL1: UART0_RST Mask */ #define RGU_RESET_CTRL1_UART1_RST_Pos 13 /*!< RGU RESET_CTRL1: UART1_RST Position */ #define RGU_RESET_CTRL1_UART1_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART1_RST_Pos) /*!< RGU RESET_CTRL1: UART1_RST Mask */ #define RGU_RESET_CTRL1_UART2_RST_Pos 14 /*!< RGU RESET_CTRL1: UART2_RST Position */ #define RGU_RESET_CTRL1_UART2_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART2_RST_Pos) /*!< RGU RESET_CTRL1: UART2_RST Mask */ #define RGU_RESET_CTRL1_UART3_RST_Pos 15 /*!< RGU RESET_CTRL1: UART3_RST Position */ #define RGU_RESET_CTRL1_UART3_RST_Msk (0x01UL << RGU_RESET_CTRL1_UART3_RST_Pos) /*!< RGU RESET_CTRL1: UART3_RST Mask */ #define RGU_RESET_CTRL1_I2C0_RST_Pos 16 /*!< RGU RESET_CTRL1: I2C0_RST Position */ #define RGU_RESET_CTRL1_I2C0_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C0_RST_Pos) /*!< RGU RESET_CTRL1: I2C0_RST Mask */ #define RGU_RESET_CTRL1_I2C1_RST_Pos 17 /*!< RGU RESET_CTRL1: I2C1_RST Position */ #define RGU_RESET_CTRL1_I2C1_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2C1_RST_Pos) /*!< RGU RESET_CTRL1: I2C1_RST Mask */ #define RGU_RESET_CTRL1_SSP0_RST_Pos 18 /*!< RGU RESET_CTRL1: SSP0_RST Position */ #define RGU_RESET_CTRL1_SSP0_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP0_RST_Pos) /*!< RGU RESET_CTRL1: SSP0_RST Mask */ #define RGU_RESET_CTRL1_SSP1_RST_Pos 19 /*!< RGU RESET_CTRL1: SSP1_RST Position */ #define RGU_RESET_CTRL1_SSP1_RST_Msk (0x01UL << RGU_RESET_CTRL1_SSP1_RST_Pos) /*!< RGU RESET_CTRL1: SSP1_RST Mask */ #define RGU_RESET_CTRL1_I2S_RST_Pos 20 /*!< RGU RESET_CTRL1: I2S_RST Position */ #define RGU_RESET_CTRL1_I2S_RST_Msk (0x01UL << RGU_RESET_CTRL1_I2S_RST_Pos) /*!< RGU RESET_CTRL1: I2S_RST Mask */ #define RGU_RESET_CTRL1_SPIFI_RST_Pos 21 /*!< RGU RESET_CTRL1: SPIFI_RST Position */ #define RGU_RESET_CTRL1_SPIFI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPIFI_RST_Pos) /*!< RGU RESET_CTRL1: SPIFI_RST Mask */ #define RGU_RESET_CTRL1_CAN1_RST_Pos 22 /*!< RGU RESET_CTRL1: CAN1_RST Position */ #define RGU_RESET_CTRL1_CAN1_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN1_RST_Pos) /*!< RGU RESET_CTRL1: CAN1_RST Mask */ #define RGU_RESET_CTRL1_CAN0_RST_Pos 23 /*!< RGU RESET_CTRL1: CAN0_RST Position */ #define RGU_RESET_CTRL1_CAN0_RST_Msk (0x01UL << RGU_RESET_CTRL1_CAN0_RST_Pos) /*!< RGU RESET_CTRL1: CAN0_RST Mask */ #define RGU_RESET_CTRL1_M0APP_RST_Pos 24 /*!< RGU RESET_CTRL1: M0APP_RST Position */ #define RGU_RESET_CTRL1_M0APP_RST_Msk (0x01UL << RGU_RESET_CTRL1_M0APP_RST_Pos) /*!< RGU RESET_CTRL1: M0APP_RST Mask */ #define RGU_RESET_CTRL1_SGPIO_RST_Pos 25 /*!< RGU RESET_CTRL1: SGPIO_RST Position */ #define RGU_RESET_CTRL1_SGPIO_RST_Msk (0x01UL << RGU_RESET_CTRL1_SGPIO_RST_Pos) /*!< RGU RESET_CTRL1: SGPIO_RST Mask */ #define RGU_RESET_CTRL1_SPI_RST_Pos 26 /*!< RGU RESET_CTRL1: SPI_RST Position */ #define RGU_RESET_CTRL1_SPI_RST_Msk (0x01UL << RGU_RESET_CTRL1_SPI_RST_Pos) /*!< RGU RESET_CTRL1: SPI_RST Mask */ #define RGU_RESET_CTRL1_ADCHS_RST_Pos 28 /*!< RGU RESET_CTRL1: ADCHS_RST Position */ #define RGU_RESET_CTRL1_ADCHS_RST_Msk (0x01UL << RGU_RESET_CTRL1_ADCHS_RST_Pos) /*!< RGU RESET_CTRL1: ADCHS_RST Mask */ /* ------------------------------ RGU_RESET_STATUS0 ----------------------------- */ #define RGU_RESET_STATUS0_PERIPH_RST_Pos 2 /*!< RGU RESET_STATUS0: PERIPH_RST Position */ #define RGU_RESET_STATUS0_PERIPH_RST_Msk (0x03UL << RGU_RESET_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_STATUS0: PERIPH_RST Mask */ #define RGU_RESET_STATUS0_MASTER_RST_Pos 4 /*!< RGU RESET_STATUS0: MASTER_RST Position */ #define RGU_RESET_STATUS0_MASTER_RST_Msk (0x03UL << RGU_RESET_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_STATUS0: MASTER_RST Mask */ #define RGU_RESET_STATUS0_WWDT_RST_Pos 8 /*!< RGU RESET_STATUS0: WWDT_RST Position */ #define RGU_RESET_STATUS0_WWDT_RST_Msk (0x03UL << RGU_RESET_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_STATUS0: WWDT_RST Mask */ #define RGU_RESET_STATUS0_CREG_RST_Pos 10 /*!< RGU RESET_STATUS0: CREG_RST Position */ #define RGU_RESET_STATUS0_CREG_RST_Msk (0x03UL << RGU_RESET_STATUS0_CREG_RST_Pos) /*!< RGU RESET_STATUS0: CREG_RST Mask */ #define RGU_RESET_STATUS0_BUS_RST_Pos 16 /*!< RGU RESET_STATUS0: BUS_RST Position */ #define RGU_RESET_STATUS0_BUS_RST_Msk (0x03UL << RGU_RESET_STATUS0_BUS_RST_Pos) /*!< RGU RESET_STATUS0: BUS_RST Mask */ #define RGU_RESET_STATUS0_SCU_RST_Pos 18 /*!< RGU RESET_STATUS0: SCU_RST Position */ #define RGU_RESET_STATUS0_SCU_RST_Msk (0x03UL << RGU_RESET_STATUS0_SCU_RST_Pos) /*!< RGU RESET_STATUS0: SCU_RST Mask */ #define RGU_RESET_STATUS0_M0SUB_RST_Pos 24 /*!< RGU RESET_STATUS0: M0SUB_RST Position */ #define RGU_RESET_STATUS0_M0SUB_RST_Msk (0x03UL << RGU_RESET_STATUS0_M0SUB_RST_Pos) /*!< RGU RESET_STATUS0: M0SUB_RST Mask */ #define RGU_RESET_STATUS0_M4_RST_Pos 26 /*!< RGU RESET_STATUS0: M4_RST Position */ #define RGU_RESET_STATUS0_M4_RST_Msk (0x03UL << RGU_RESET_STATUS0_M4_RST_Pos) /*!< RGU RESET_STATUS0: M4_RST Mask */ /* ------------------------------ RGU_RESET_STATUS1 ----------------------------- */ #define RGU_RESET_STATUS1_LCD_RST_Pos 0 /*!< RGU RESET_STATUS1: LCD_RST Position */ #define RGU_RESET_STATUS1_LCD_RST_Msk (0x03UL << RGU_RESET_STATUS1_LCD_RST_Pos) /*!< RGU RESET_STATUS1: LCD_RST Mask */ #define RGU_RESET_STATUS1_USB0_RST_Pos 2 /*!< RGU RESET_STATUS1: USB0_RST Position */ #define RGU_RESET_STATUS1_USB0_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB0_RST_Pos) /*!< RGU RESET_STATUS1: USB0_RST Mask */ #define RGU_RESET_STATUS1_USB1_RST_Pos 4 /*!< RGU RESET_STATUS1: USB1_RST Position */ #define RGU_RESET_STATUS1_USB1_RST_Msk (0x03UL << RGU_RESET_STATUS1_USB1_RST_Pos) /*!< RGU RESET_STATUS1: USB1_RST Mask */ #define RGU_RESET_STATUS1_DMA_RST_Pos 6 /*!< RGU RESET_STATUS1: DMA_RST Position */ #define RGU_RESET_STATUS1_DMA_RST_Msk (0x03UL << RGU_RESET_STATUS1_DMA_RST_Pos) /*!< RGU RESET_STATUS1: DMA_RST Mask */ #define RGU_RESET_STATUS1_SDIO_RST_Pos 8 /*!< RGU RESET_STATUS1: SDIO_RST Position */ #define RGU_RESET_STATUS1_SDIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_SDIO_RST_Pos) /*!< RGU RESET_STATUS1: SDIO_RST Mask */ #define RGU_RESET_STATUS1_EMC_RST_Pos 10 /*!< RGU RESET_STATUS1: EMC_RST Position */ #define RGU_RESET_STATUS1_EMC_RST_Msk (0x03UL << RGU_RESET_STATUS1_EMC_RST_Pos) /*!< RGU RESET_STATUS1: EMC_RST Mask */ #define RGU_RESET_STATUS1_ETHERNET_RST_Pos 12 /*!< RGU RESET_STATUS1: ETHERNET_RST Position */ #define RGU_RESET_STATUS1_ETHERNET_RST_Msk (0x03UL << RGU_RESET_STATUS1_ETHERNET_RST_Pos) /*!< RGU RESET_STATUS1: ETHERNET_RST Mask */ #define RGU_RESET_STATUS1_FLASHA_RST_Pos 18 /*!< RGU RESET_STATUS1: FLASHA_RST Position */ #define RGU_RESET_STATUS1_FLASHA_RST_Msk (0x03UL << RGU_RESET_STATUS1_FLASHA_RST_Pos) /*!< RGU RESET_STATUS1: FLASHA_RST Mask */ #define RGU_RESET_STATUS1_EEPROM_RST_Pos 22 /*!< RGU RESET_STATUS1: EEPROM_RST Position */ #define RGU_RESET_STATUS1_EEPROM_RST_Msk (0x03UL << RGU_RESET_STATUS1_EEPROM_RST_Pos) /*!< RGU RESET_STATUS1: EEPROM_RST Mask */ #define RGU_RESET_STATUS1_GPIO_RST_Pos 24 /*!< RGU RESET_STATUS1: GPIO_RST Position */ #define RGU_RESET_STATUS1_GPIO_RST_Msk (0x03UL << RGU_RESET_STATUS1_GPIO_RST_Pos) /*!< RGU RESET_STATUS1: GPIO_RST Mask */ #define RGU_RESET_STATUS1_FLASHB_RST_Pos 26 /*!< RGU RESET_STATUS1: FLASHB_RST Position */ #define RGU_RESET_STATUS1_FLASHB_RST_Msk (0x03UL << RGU_RESET_STATUS1_FLASHB_RST_Pos) /*!< RGU RESET_STATUS1: FLASHB_RST Mask */ /* ------------------------------ RGU_RESET_STATUS2 ----------------------------- */ #define RGU_RESET_STATUS2_TIMER0_RST_Pos 0 /*!< RGU RESET_STATUS2: TIMER0_RST Position */ #define RGU_RESET_STATUS2_TIMER0_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER0_RST_Pos) /*!< RGU RESET_STATUS2: TIMER0_RST Mask */ #define RGU_RESET_STATUS2_TIMER1_RST_Pos 2 /*!< RGU RESET_STATUS2: TIMER1_RST Position */ #define RGU_RESET_STATUS2_TIMER1_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER1_RST_Pos) /*!< RGU RESET_STATUS2: TIMER1_RST Mask */ #define RGU_RESET_STATUS2_TIMER2_RST_Pos 4 /*!< RGU RESET_STATUS2: TIMER2_RST Position */ #define RGU_RESET_STATUS2_TIMER2_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER2_RST_Pos) /*!< RGU RESET_STATUS2: TIMER2_RST Mask */ #define RGU_RESET_STATUS2_TIMER3_RST_Pos 6 /*!< RGU RESET_STATUS2: TIMER3_RST Position */ #define RGU_RESET_STATUS2_TIMER3_RST_Msk (0x03UL << RGU_RESET_STATUS2_TIMER3_RST_Pos) /*!< RGU RESET_STATUS2: TIMER3_RST Mask */ #define RGU_RESET_STATUS2_RITIMER_RST_Pos 8 /*!< RGU RESET_STATUS2: RITIMER_RST Position */ #define RGU_RESET_STATUS2_RITIMER_RST_Msk (0x03UL << RGU_RESET_STATUS2_RITIMER_RST_Pos) /*!< RGU RESET_STATUS2: RITIMER_RST Mask */ #define RGU_RESET_STATUS2_SCT_RST_Pos 10 /*!< RGU RESET_STATUS2: SCT_RST Position */ #define RGU_RESET_STATUS2_SCT_RST_Msk (0x03UL << RGU_RESET_STATUS2_SCT_RST_Pos) /*!< RGU RESET_STATUS2: SCT_RST Mask */ #define RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos 12 /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Position */ #define RGU_RESET_STATUS2_MOTOCONPWM_RST_Msk (0x03UL << RGU_RESET_STATUS2_MOTOCONPWM_RST_Pos) /*!< RGU RESET_STATUS2: MOTOCONPWM_RST Mask */ #define RGU_RESET_STATUS2_QEI_RST_Pos 14 /*!< RGU RESET_STATUS2: QEI_RST Position */ #define RGU_RESET_STATUS2_QEI_RST_Msk (0x03UL << RGU_RESET_STATUS2_QEI_RST_Pos) /*!< RGU RESET_STATUS2: QEI_RST Mask */ #define RGU_RESET_STATUS2_ADC0_RST_Pos 16 /*!< RGU RESET_STATUS2: ADC0_RST Position */ #define RGU_RESET_STATUS2_ADC0_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC0_RST_Pos) /*!< RGU RESET_STATUS2: ADC0_RST Mask */ #define RGU_RESET_STATUS2_ADC1_RST_Pos 18 /*!< RGU RESET_STATUS2: ADC1_RST Position */ #define RGU_RESET_STATUS2_ADC1_RST_Msk (0x03UL << RGU_RESET_STATUS2_ADC1_RST_Pos) /*!< RGU RESET_STATUS2: ADC1_RST Mask */ #define RGU_RESET_STATUS2_DAC_RST_Pos 20 /*!< RGU RESET_STATUS2: DAC_RST Position */ #define RGU_RESET_STATUS2_DAC_RST_Msk (0x03UL << RGU_RESET_STATUS2_DAC_RST_Pos) /*!< RGU RESET_STATUS2: DAC_RST Mask */ #define RGU_RESET_STATUS2_UART0_RST_Pos 24 /*!< RGU RESET_STATUS2: UART0_RST Position */ #define RGU_RESET_STATUS2_UART0_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART0_RST_Pos) /*!< RGU RESET_STATUS2: UART0_RST Mask */ #define RGU_RESET_STATUS2_UART1_RST_Pos 26 /*!< RGU RESET_STATUS2: UART1_RST Position */ #define RGU_RESET_STATUS2_UART1_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART1_RST_Pos) /*!< RGU RESET_STATUS2: UART1_RST Mask */ #define RGU_RESET_STATUS2_UART2_RST_Pos 28 /*!< RGU RESET_STATUS2: UART2_RST Position */ #define RGU_RESET_STATUS2_UART2_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART2_RST_Pos) /*!< RGU RESET_STATUS2: UART2_RST Mask */ #define RGU_RESET_STATUS2_UART3_RST_Pos 30 /*!< RGU RESET_STATUS2: UART3_RST Position */ #define RGU_RESET_STATUS2_UART3_RST_Msk (0x03UL << RGU_RESET_STATUS2_UART3_RST_Pos) /*!< RGU RESET_STATUS2: UART3_RST Mask */ /* ------------------------------ RGU_RESET_STATUS3 ----------------------------- */ #define RGU_RESET_STATUS3_I2C0_RST_Pos 0 /*!< RGU RESET_STATUS3: I2C0_RST Position */ #define RGU_RESET_STATUS3_I2C0_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C0_RST_Pos) /*!< RGU RESET_STATUS3: I2C0_RST Mask */ #define RGU_RESET_STATUS3_I2C1_RST_Pos 2 /*!< RGU RESET_STATUS3: I2C1_RST Position */ #define RGU_RESET_STATUS3_I2C1_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2C1_RST_Pos) /*!< RGU RESET_STATUS3: I2C1_RST Mask */ #define RGU_RESET_STATUS3_SSP0_RST_Pos 4 /*!< RGU RESET_STATUS3: SSP0_RST Position */ #define RGU_RESET_STATUS3_SSP0_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP0_RST_Pos) /*!< RGU RESET_STATUS3: SSP0_RST Mask */ #define RGU_RESET_STATUS3_SSP1_RST_Pos 6 /*!< RGU RESET_STATUS3: SSP1_RST Position */ #define RGU_RESET_STATUS3_SSP1_RST_Msk (0x03UL << RGU_RESET_STATUS3_SSP1_RST_Pos) /*!< RGU RESET_STATUS3: SSP1_RST Mask */ #define RGU_RESET_STATUS3_I2S_RST_Pos 8 /*!< RGU RESET_STATUS3: I2S_RST Position */ #define RGU_RESET_STATUS3_I2S_RST_Msk (0x03UL << RGU_RESET_STATUS3_I2S_RST_Pos) /*!< RGU RESET_STATUS3: I2S_RST Mask */ #define RGU_RESET_STATUS3_SPIFI_RST_Pos 10 /*!< RGU RESET_STATUS3: SPIFI_RST Position */ #define RGU_RESET_STATUS3_SPIFI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPIFI_RST_Pos) /*!< RGU RESET_STATUS3: SPIFI_RST Mask */ #define RGU_RESET_STATUS3_CAN1_RST_Pos 12 /*!< RGU RESET_STATUS3: CAN1_RST Position */ #define RGU_RESET_STATUS3_CAN1_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN1_RST_Pos) /*!< RGU RESET_STATUS3: CAN1_RST Mask */ #define RGU_RESET_STATUS3_CAN0_RST_Pos 14 /*!< RGU RESET_STATUS3: CAN0_RST Position */ #define RGU_RESET_STATUS3_CAN0_RST_Msk (0x03UL << RGU_RESET_STATUS3_CAN0_RST_Pos) /*!< RGU RESET_STATUS3: CAN0_RST Mask */ #define RGU_RESET_STATUS3_M0APP_RST_Pos 16 /*!< RGU RESET_STATUS3: M0APP_RST Position */ #define RGU_RESET_STATUS3_M0APP_RST_Msk (0x03UL << RGU_RESET_STATUS3_M0APP_RST_Pos) /*!< RGU RESET_STATUS3: M0APP_RST Mask */ #define RGU_RESET_STATUS3_SGPIO_RST_Pos 18 /*!< RGU RESET_STATUS3: SGPIO_RST Position */ #define RGU_RESET_STATUS3_SGPIO_RST_Msk (0x03UL << RGU_RESET_STATUS3_SGPIO_RST_Pos) /*!< RGU RESET_STATUS3: SGPIO_RST Mask */ #define RGU_RESET_STATUS3_SPI_RST_Pos 20 /*!< RGU RESET_STATUS3: SPI_RST Position */ #define RGU_RESET_STATUS3_SPI_RST_Msk (0x03UL << RGU_RESET_STATUS3_SPI_RST_Pos) /*!< RGU RESET_STATUS3: SPI_RST Mask */ #define RGU_RESET_STATUS3_ADCHS_RST_Pos 24 /*!< RGU RESET_STATUS3: ADCHS_RST Position */ #define RGU_RESET_STATUS3_ADCHS_RST_Msk (0x03UL << RGU_RESET_STATUS3_ADCHS_RST_Pos) /*!< RGU RESET_STATUS3: ADCHS_RST Mask */ /* -------------------------- RGU_RESET_ACTIVE_STATUS0 -------------------------- */ #define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_CORE_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CORE_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CORE_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_PERIPH_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: PERIPH_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_MASTER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: MASTER_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_WWDT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: WWDT_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_CREG_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_CREG_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: CREG_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_BUS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_BUS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: BUS_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_SCU_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SCU_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SCU_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_M0SUB_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS0: M0SUB_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_M0SUB_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M0SUB_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M0SUB_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_M4_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS0: M4_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_M4_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_M4_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: M4_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_LCD_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_LCD_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: LCD_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_USB0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB0_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_USB1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_USB1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: USB1_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_DMA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_DMA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: DMA_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_SDIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: SDIO_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_EMC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EMC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EMC_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_ETHERNET_RST_Pos)/*!< RGU RESET_ACTIVE_STATUS0: ETHERNET_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_FLASHA_RST_Pos 25 /*!< RGU RESET_ACTIVE_STATUS0: FLASHA_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_FLASHA_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_FLASHA_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: FLASHA_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_EEPROM_RST_Pos 27 /*!< RGU RESET_ACTIVE_STATUS0: EEPROM_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_EEPROM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_EEPROM_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: EEPROM_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_GPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: GPIO_RST Mask */ #define RGU_RESET_ACTIVE_STATUS0_FLASHB_RST_Pos 29 /*!< RGU RESET_ACTIVE_STATUS0: FLASHB_RST Position */ #define RGU_RESET_ACTIVE_STATUS0_FLASHB_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS0_FLASHB_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS0: FLASHB_RST Mask */ /* -------------------------- RGU_RESET_ACTIVE_STATUS1 -------------------------- */ #define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos 0 /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER0_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos 1 /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER1_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos 2 /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER2_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos 3 /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_TIMER3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: TIMER3_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos 4 /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_RITIMER_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: RITIMER_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos 5 /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_SCT_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SCT_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SCT_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos 6 /*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_Pos)/*!< RGU RESET_ACTIVE_STATUS1: MOTOCONPWM_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos 7 /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_QEI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_QEI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: QEI_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos 8 /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC0_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos 9 /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADC1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADC1_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos 10 /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_DAC_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_DAC_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: DAC_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos 12 /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_UART0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART0_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos 13 /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_UART1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART1_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos 14 /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_UART2_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART2_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART2_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos 15 /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_UART3_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_UART3_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: UART3_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos 16 /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C0_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos 17 /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2C1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2C1_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos 18 /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP0_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos 19 /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SSP1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SSP1_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos 20 /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_I2S_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_I2S_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: I2S_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos 21 /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPIFI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPIFI_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos 22 /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN1_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN1_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos 23 /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_CAN0_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: CAN0_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_M0APP_RST_Pos 24 /*!< RGU RESET_ACTIVE_STATUS1: M0APP_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_M0APP_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_M0APP_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: M0APP_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos 25 /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SGPIO_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SGPIO_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos 26 /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_SPI_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_SPI_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: SPI_RST Mask */ #define RGU_RESET_ACTIVE_STATUS1_ADCHS_RST_Pos 28 /*!< RGU RESET_ACTIVE_STATUS1: ADCHS_RST Position */ #define RGU_RESET_ACTIVE_STATUS1_ADCHS_RST_Msk (0x01UL << RGU_RESET_ACTIVE_STATUS1_ADCHS_RST_Pos) /*!< RGU RESET_ACTIVE_STATUS1: ADCHS_RST Mask */ /* ----------------------------- RGU_RESET_EXT_STAT1 ---------------------------- */ #define RGU_RESET_EXT_STAT1_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT1: CORE_RESET Position */ #define RGU_RESET_EXT_STAT1_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT1_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT1: CORE_RESET Mask */ /* ----------------------------- RGU_RESET_EXT_STAT2 ---------------------------- */ #define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT2_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT2: PERIPHERAL_RESET Mask */ /* ----------------------------- RGU_RESET_EXT_STAT5 ---------------------------- */ #define RGU_RESET_EXT_STAT5_CORE_RESET_Pos 1 /*!< RGU RESET_EXT_STAT5: CORE_RESET Position */ #define RGU_RESET_EXT_STAT5_CORE_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT5_CORE_RESET_Pos) /*!< RGU RESET_EXT_STAT5: CORE_RESET Mask */ /* ----------------------------- RGU_RESET_EXT_STAT8 ---------------------------- */ #define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT8_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT8: PERIPHERAL_RESET Mask */ /* ----------------------------- RGU_RESET_EXT_STAT9 ---------------------------- */ #define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT9_PERIPHERAL_RESET_Pos) /*!< RGU RESET_EXT_STAT9: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT12 ---------------------------- */ #define RGU_RESET_EXT_STAT12_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT12: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT12_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT12_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT12: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT13 ---------------------------- */ #define RGU_RESET_EXT_STAT13_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT13: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT13_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT13_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT13: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT16 ---------------------------- */ #define RGU_RESET_EXT_STAT16_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT16: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT16_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT16_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT16: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT17 ---------------------------- */ #define RGU_RESET_EXT_STAT17_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT17: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT17_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT17_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT17: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT18 ---------------------------- */ #define RGU_RESET_EXT_STAT18_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT18: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT18_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT18_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT18: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT19 ---------------------------- */ #define RGU_RESET_EXT_STAT19_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT19: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT19_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT19_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT19: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT20 ---------------------------- */ #define RGU_RESET_EXT_STAT20_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT20: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT20_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT20_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT20: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT21 ---------------------------- */ #define RGU_RESET_EXT_STAT21_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT21: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT21_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT21_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT21: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT22 ---------------------------- */ #define RGU_RESET_EXT_STAT22_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT22: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT22_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT22_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT22: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT25 ---------------------------- */ #define RGU_RESET_EXT_STAT25_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT25: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT25_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT25_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT25: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT27 ---------------------------- */ #define RGU_RESET_EXT_STAT27_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT27: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT27_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT27_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT27: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT28 ---------------------------- */ #define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT28_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT28: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT29 ---------------------------- */ #define RGU_RESET_EXT_STAT29_MASTER_RESET_Pos 3 /*!< RGU RESET_EXT_STAT29: MASTER_RESET Position */ #define RGU_RESET_EXT_STAT29_MASTER_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT29_MASTER_RESET_Pos) /*!< RGU RESET_EXT_STAT29: MASTER_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT32 ---------------------------- */ #define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT32_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT32: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT33 ---------------------------- */ #define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT33_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT33: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT34 ---------------------------- */ #define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT34_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT34: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT35 ---------------------------- */ #define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT35_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT35: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT36 ---------------------------- */ #define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT36_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT36: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT37 ---------------------------- */ #define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT37_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT37: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT38 ---------------------------- */ #define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT38_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT38: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT39 ---------------------------- */ #define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT39_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT39: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT40 ---------------------------- */ #define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT40_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT40: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT41 ---------------------------- */ #define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT41_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT41: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT42 ---------------------------- */ #define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT42_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT42: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT44 ---------------------------- */ #define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT44_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT44: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT45 ---------------------------- */ #define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT45_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT45: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT46 ---------------------------- */ #define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT46_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT46: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT47 ---------------------------- */ #define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT47_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT47: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT48 ---------------------------- */ #define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT48_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT48: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT49 ---------------------------- */ #define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT49_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT49: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT50 ---------------------------- */ #define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT50_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT50: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT51 ---------------------------- */ #define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT51_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT51: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT52 ---------------------------- */ #define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT52_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT52: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT53 ---------------------------- */ #define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT53_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT53: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT54 ---------------------------- */ #define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT54_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT54: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT55 ---------------------------- */ #define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT55_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT55: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT56 ---------------------------- */ #define RGU_RESET_EXT_STAT56_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT56: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT56_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT56_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT56: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT57 ---------------------------- */ #define RGU_RESET_EXT_STAT57_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT57: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT57_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT57_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT57: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT58 ---------------------------- */ #define RGU_RESET_EXT_STAT58_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT58: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT58_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT58_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT58: PERIPHERAL_RESET Mask */ /* ---------------------------- RGU_RESET_EXT_STAT60 ---------------------------- */ #define RGU_RESET_EXT_STAT60_PERIPHERAL_RESET_Pos 2 /*!< RGU RESET_EXT_STAT60: PERIPHERAL_RESET Position */ #define RGU_RESET_EXT_STAT60_PERIPHERAL_RESET_Msk (0x01UL << RGU_RESET_EXT_STAT60_PERIPHERAL_RESET_Pos)/*!< RGU RESET_EXT_STAT60: PERIPHERAL_RESET Mask */ /* ================================================================================ */ /* ================ struct 'WWDT' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- WWDT_MOD ---------------------------------- */ #define WWDT_MOD_WDEN_Pos 0 /*!< WWDT MOD: WDEN Position */ #define WWDT_MOD_WDEN_Msk (0x01UL << WWDT_MOD_WDEN_Pos) /*!< WWDT MOD: WDEN Mask */ #define WWDT_MOD_WDRESET_Pos 1 /*!< WWDT MOD: WDRESET Position */ #define WWDT_MOD_WDRESET_Msk (0x01UL << WWDT_MOD_WDRESET_Pos) /*!< WWDT MOD: WDRESET Mask */ #define WWDT_MOD_WDTOF_Pos 2 /*!< WWDT MOD: WDTOF Position */ #define WWDT_MOD_WDTOF_Msk (0x01UL << WWDT_MOD_WDTOF_Pos) /*!< WWDT MOD: WDTOF Mask */ #define WWDT_MOD_WDINT_Pos 3 /*!< WWDT MOD: WDINT Position */ #define WWDT_MOD_WDINT_Msk (0x01UL << WWDT_MOD_WDINT_Pos) /*!< WWDT MOD: WDINT Mask */ #define WWDT_MOD_WDPROTECT_Pos 4 /*!< WWDT MOD: WDPROTECT Position */ #define WWDT_MOD_WDPROTECT_Msk (0x01UL << WWDT_MOD_WDPROTECT_Pos) /*!< WWDT MOD: WDPROTECT Mask */ /* ----------------------------------- WWDT_TC ---------------------------------- */ #define WWDT_TC_WDTC_Pos 0 /*!< WWDT TC: WDTC Position */ #define WWDT_TC_WDTC_Msk (0x00ffffffUL << WWDT_TC_WDTC_Pos) /*!< WWDT TC: WDTC Mask */ /* ---------------------------------- WWDT_FEED --------------------------------- */ #define WWDT_FEED_Feed_Pos 0 /*!< WWDT FEED: Feed Position */ #define WWDT_FEED_Feed_Msk (0x000000ffUL << WWDT_FEED_Feed_Pos) /*!< WWDT FEED: Feed Mask */ /* ----------------------------------- WWDT_TV ---------------------------------- */ #define WWDT_TV_Count_Pos 0 /*!< WWDT TV: Count Position */ #define WWDT_TV_Count_Msk (0x00ffffffUL << WWDT_TV_Count_Pos) /*!< WWDT TV: Count Mask */ /* -------------------------------- WWDT_WARNINT -------------------------------- */ #define WWDT_WARNINT_WDWARNINT_Pos 0 /*!< WWDT WARNINT: WDWARNINT Position */ #define WWDT_WARNINT_WDWARNINT_Msk (0x000003ffUL << WWDT_WARNINT_WDWARNINT_Pos) /*!< WWDT WARNINT: WDWARNINT Mask */ /* --------------------------------- WWDT_WINDOW -------------------------------- */ #define WWDT_WINDOW_WDWINDOW_Pos 0 /*!< WWDT WINDOW: WDWINDOW Position */ #define WWDT_WINDOW_WDWINDOW_Msk (0x00ffffffUL << WWDT_WINDOW_WDWINDOW_Pos) /*!< WWDT WINDOW: WDWINDOW Mask */ /* ================================================================================ */ /* ================ Group 'USARTn' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- USARTn_RBR --------------------------------- */ #define USARTn_RBR_RBR_Pos 0 /*!< USARTn RBR: RBR Position */ #define USARTn_RBR_RBR_Msk (0x000000ffUL << USARTn_RBR_RBR_Pos) /*!< USARTn RBR: RBR Mask */ /* --------------------------------- USARTn_THR --------------------------------- */ #define USARTn_THR_THR_Pos 0 /*!< USARTn THR: THR Position */ #define USARTn_THR_THR_Msk (0x000000ffUL << USARTn_THR_THR_Pos) /*!< USARTn THR: THR Mask */ /* --------------------------------- USARTn_DLL --------------------------------- */ #define USARTn_DLL_DLLSB_Pos 0 /*!< USARTn DLL: DLLSB Position */ #define USARTn_DLL_DLLSB_Msk (0x000000ffUL << USARTn_DLL_DLLSB_Pos) /*!< USARTn DLL: DLLSB Mask */ /* --------------------------------- USARTn_DLM --------------------------------- */ #define USARTn_DLM_DLMSB_Pos 0 /*!< USARTn DLM: DLMSB Position */ #define USARTn_DLM_DLMSB_Msk (0x000000ffUL << USARTn_DLM_DLMSB_Pos) /*!< USARTn DLM: DLMSB Mask */ /* --------------------------------- USARTn_IER --------------------------------- */ #define USARTn_IER_RBRIE_Pos 0 /*!< USARTn IER: RBRIE Position */ #define USARTn_IER_RBRIE_Msk (0x01UL << USARTn_IER_RBRIE_Pos) /*!< USARTn IER: RBRIE Mask */ #define USARTn_IER_THREIE_Pos 1 /*!< USARTn IER: THREIE Position */ #define USARTn_IER_THREIE_Msk (0x01UL << USARTn_IER_THREIE_Pos) /*!< USARTn IER: THREIE Mask */ #define USARTn_IER_RXIE_Pos 2 /*!< USARTn IER: RXIE Position */ #define USARTn_IER_RXIE_Msk (0x01UL << USARTn_IER_RXIE_Pos) /*!< USARTn IER: RXIE Mask */ #define USARTn_IER_ABEOINTEN_Pos 8 /*!< USARTn IER: ABEOINTEN Position */ #define USARTn_IER_ABEOINTEN_Msk (0x01UL << USARTn_IER_ABEOINTEN_Pos) /*!< USARTn IER: ABEOINTEN Mask */ #define USARTn_IER_ABTOINTEN_Pos 9 /*!< USARTn IER: ABTOINTEN Position */ #define USARTn_IER_ABTOINTEN_Msk (0x01UL << USARTn_IER_ABTOINTEN_Pos) /*!< USARTn IER: ABTOINTEN Mask */ /* --------------------------------- USARTn_IIR --------------------------------- */ #define USARTn_IIR_INTSTATUS_Pos 0 /*!< USARTn IIR: INTSTATUS Position */ #define USARTn_IIR_INTSTATUS_Msk (0x01UL << USARTn_IIR_INTSTATUS_Pos) /*!< USARTn IIR: INTSTATUS Mask */ #define USARTn_IIR_INTID_Pos 1 /*!< USARTn IIR: INTID Position */ #define USARTn_IIR_INTID_Msk (0x07UL << USARTn_IIR_INTID_Pos) /*!< USARTn IIR: INTID Mask */ #define USARTn_IIR_FIFOENABLE_Pos 6 /*!< USARTn IIR: FIFOENABLE Position */ #define USARTn_IIR_FIFOENABLE_Msk (0x03UL << USARTn_IIR_FIFOENABLE_Pos) /*!< USARTn IIR: FIFOENABLE Mask */ #define USARTn_IIR_ABEOINT_Pos 8 /*!< USARTn IIR: ABEOINT Position */ #define USARTn_IIR_ABEOINT_Msk (0x01UL << USARTn_IIR_ABEOINT_Pos) /*!< USARTn IIR: ABEOINT Mask */ #define USARTn_IIR_ABTOINT_Pos 9 /*!< USARTn IIR: ABTOINT Position */ #define USARTn_IIR_ABTOINT_Msk (0x01UL << USARTn_IIR_ABTOINT_Pos) /*!< USARTn IIR: ABTOINT Mask */ /* --------------------------------- USARTn_FCR --------------------------------- */ #define USARTn_FCR_FIFOEN_Pos 0 /*!< USARTn FCR: FIFOEN Position */ #define USARTn_FCR_FIFOEN_Msk (0x01UL << USARTn_FCR_FIFOEN_Pos) /*!< USARTn FCR: FIFOEN Mask */ #define USARTn_FCR_RXFIFORES_Pos 1 /*!< USARTn FCR: RXFIFORES Position */ #define USARTn_FCR_RXFIFORES_Msk (0x01UL << USARTn_FCR_RXFIFORES_Pos) /*!< USARTn FCR: RXFIFORES Mask */ #define USARTn_FCR_TXFIFORES_Pos 2 /*!< USARTn FCR: TXFIFORES Position */ #define USARTn_FCR_TXFIFORES_Msk (0x01UL << USARTn_FCR_TXFIFORES_Pos) /*!< USARTn FCR: TXFIFORES Mask */ #define USARTn_FCR_DMAMODE_Pos 3 /*!< USARTn FCR: DMAMODE Position */ #define USARTn_FCR_DMAMODE_Msk (0x01UL << USARTn_FCR_DMAMODE_Pos) /*!< USARTn FCR: DMAMODE Mask */ #define USARTn_FCR_RXTRIGLVL_Pos 6 /*!< USARTn FCR: RXTRIGLVL Position */ #define USARTn_FCR_RXTRIGLVL_Msk (0x03UL << USARTn_FCR_RXTRIGLVL_Pos) /*!< USARTn FCR: RXTRIGLVL Mask */ /* --------------------------------- USARTn_LCR --------------------------------- */ #define USARTn_LCR_WLS_Pos 0 /*!< USARTn LCR: WLS Position */ #define USARTn_LCR_WLS_Msk (0x03UL << USARTn_LCR_WLS_Pos) /*!< USARTn LCR: WLS Mask */ #define USARTn_LCR_SBS_Pos 2 /*!< USARTn LCR: SBS Position */ #define USARTn_LCR_SBS_Msk (0x01UL << USARTn_LCR_SBS_Pos) /*!< USARTn LCR: SBS Mask */ #define USARTn_LCR_PE_Pos 3 /*!< USARTn LCR: PE Position */ #define USARTn_LCR_PE_Msk (0x01UL << USARTn_LCR_PE_Pos) /*!< USARTn LCR: PE Mask */ #define USARTn_LCR_PS_Pos 4 /*!< USARTn LCR: PS Position */ #define USARTn_LCR_PS_Msk (0x03UL << USARTn_LCR_PS_Pos) /*!< USARTn LCR: PS Mask */ #define USARTn_LCR_BC_Pos 6 /*!< USARTn LCR: BC Position */ #define USARTn_LCR_BC_Msk (0x01UL << USARTn_LCR_BC_Pos) /*!< USARTn LCR: BC Mask */ #define USARTn_LCR_DLAB_Pos 7 /*!< USARTn LCR: DLAB Position */ #define USARTn_LCR_DLAB_Msk (0x01UL << USARTn_LCR_DLAB_Pos) /*!< USARTn LCR: DLAB Mask */ /* --------------------------------- USARTn_LSR --------------------------------- */ #define USARTn_LSR_RDR_Pos 0 /*!< USARTn LSR: RDR Position */ #define USARTn_LSR_RDR_Msk (0x01UL << USARTn_LSR_RDR_Pos) /*!< USARTn LSR: RDR Mask */ #define USARTn_LSR_OE_Pos 1 /*!< USARTn LSR: OE Position */ #define USARTn_LSR_OE_Msk (0x01UL << USARTn_LSR_OE_Pos) /*!< USARTn LSR: OE Mask */ #define USARTn_LSR_PE_Pos 2 /*!< USARTn LSR: PE Position */ #define USARTn_LSR_PE_Msk (0x01UL << USARTn_LSR_PE_Pos) /*!< USARTn LSR: PE Mask */ #define USARTn_LSR_FE_Pos 3 /*!< USARTn LSR: FE Position */ #define USARTn_LSR_FE_Msk (0x01UL << USARTn_LSR_FE_Pos) /*!< USARTn LSR: FE Mask */ #define USARTn_LSR_BI_Pos 4 /*!< USARTn LSR: BI Position */ #define USARTn_LSR_BI_Msk (0x01UL << USARTn_LSR_BI_Pos) /*!< USARTn LSR: BI Mask */ #define USARTn_LSR_THRE_Pos 5 /*!< USARTn LSR: THRE Position */ #define USARTn_LSR_THRE_Msk (0x01UL << USARTn_LSR_THRE_Pos) /*!< USARTn LSR: THRE Mask */ #define USARTn_LSR_TEMT_Pos 6 /*!< USARTn LSR: TEMT Position */ #define USARTn_LSR_TEMT_Msk (0x01UL << USARTn_LSR_TEMT_Pos) /*!< USARTn LSR: TEMT Mask */ #define USARTn_LSR_RXFE_Pos 7 /*!< USARTn LSR: RXFE Position */ #define USARTn_LSR_RXFE_Msk (0x01UL << USARTn_LSR_RXFE_Pos) /*!< USARTn LSR: RXFE Mask */ #define USARTn_LSR_TXERR_Pos 8 /*!< USARTn LSR: TXERR Position */ #define USARTn_LSR_TXERR_Msk (0x01UL << USARTn_LSR_TXERR_Pos) /*!< USARTn LSR: TXERR Mask */ /* --------------------------------- USARTn_SCR --------------------------------- */ #define USARTn_SCR_PAD_Pos 0 /*!< USARTn SCR: PAD Position */ #define USARTn_SCR_PAD_Msk (0x000000ffUL << USARTn_SCR_PAD_Pos) /*!< USARTn SCR: PAD Mask */ /* --------------------------------- USARTn_ACR --------------------------------- */ #define USARTn_ACR_START_Pos 0 /*!< USARTn ACR: START Position */ #define USARTn_ACR_START_Msk (0x01UL << USARTn_ACR_START_Pos) /*!< USARTn ACR: START Mask */ #define USARTn_ACR_MODE_Pos 1 /*!< USARTn ACR: MODE Position */ #define USARTn_ACR_MODE_Msk (0x01UL << USARTn_ACR_MODE_Pos) /*!< USARTn ACR: MODE Mask */ #define USARTn_ACR_AUTORESTART_Pos 2 /*!< USARTn ACR: AUTORESTART Position */ #define USARTn_ACR_AUTORESTART_Msk (0x01UL << USARTn_ACR_AUTORESTART_Pos) /*!< USARTn ACR: AUTORESTART Mask */ #define USARTn_ACR_ABEOINTCLR_Pos 8 /*!< USARTn ACR: ABEOINTCLR Position */ #define USARTn_ACR_ABEOINTCLR_Msk (0x01UL << USARTn_ACR_ABEOINTCLR_Pos) /*!< USARTn ACR: ABEOINTCLR Mask */ #define USARTn_ACR_ABTOINTCLR_Pos 9 /*!< USARTn ACR: ABTOINTCLR Position */ #define USARTn_ACR_ABTOINTCLR_Msk (0x01UL << USARTn_ACR_ABTOINTCLR_Pos) /*!< USARTn ACR: ABTOINTCLR Mask */ /* --------------------------------- USARTn_ICR --------------------------------- */ #define USARTn_ICR_IRDAEN_Pos 0 /*!< USARTn ICR: IRDAEN Position */ #define USARTn_ICR_IRDAEN_Msk (0x01UL << USARTn_ICR_IRDAEN_Pos) /*!< USARTn ICR: IRDAEN Mask */ #define USARTn_ICR_IRDAINV_Pos 1 /*!< USARTn ICR: IRDAINV Position */ #define USARTn_ICR_IRDAINV_Msk (0x01UL << USARTn_ICR_IRDAINV_Pos) /*!< USARTn ICR: IRDAINV Mask */ #define USARTn_ICR_FIXPULSEEN_Pos 2 /*!< USARTn ICR: FIXPULSEEN Position */ #define USARTn_ICR_FIXPULSEEN_Msk (0x01UL << USARTn_ICR_FIXPULSEEN_Pos) /*!< USARTn ICR: FIXPULSEEN Mask */ #define USARTn_ICR_PULSEDIV_Pos 3 /*!< USARTn ICR: PULSEDIV Position */ #define USARTn_ICR_PULSEDIV_Msk (0x07UL << USARTn_ICR_PULSEDIV_Pos) /*!< USARTn ICR: PULSEDIV Mask */ /* --------------------------------- USARTn_FDR --------------------------------- */ #define USARTn_FDR_DIVADDVAL_Pos 0 /*!< USARTn FDR: DIVADDVAL Position */ #define USARTn_FDR_DIVADDVAL_Msk (0x0fUL << USARTn_FDR_DIVADDVAL_Pos) /*!< USARTn FDR: DIVADDVAL Mask */ #define USARTn_FDR_MULVAL_Pos 4 /*!< USARTn FDR: MULVAL Position */ #define USARTn_FDR_MULVAL_Msk (0x0fUL << USARTn_FDR_MULVAL_Pos) /*!< USARTn FDR: MULVAL Mask */ /* --------------------------------- USARTn_OSR --------------------------------- */ #define USARTn_OSR_OSFRAC_Pos 1 /*!< USARTn OSR: OSFRAC Position */ #define USARTn_OSR_OSFRAC_Msk (0x07UL << USARTn_OSR_OSFRAC_Pos) /*!< USARTn OSR: OSFRAC Mask */ #define USARTn_OSR_OSINT_Pos 4 /*!< USARTn OSR: OSINT Position */ #define USARTn_OSR_OSINT_Msk (0x0fUL << USARTn_OSR_OSINT_Pos) /*!< USARTn OSR: OSINT Mask */ #define USARTn_OSR_FDINT_Pos 8 /*!< USARTn OSR: FDINT Position */ #define USARTn_OSR_FDINT_Msk (0x7fUL << USARTn_OSR_FDINT_Pos) /*!< USARTn OSR: FDINT Mask */ /* --------------------------------- USARTn_HDEN -------------------------------- */ #define USARTn_HDEN_HDEN_Pos 0 /*!< USARTn HDEN: HDEN Position */ #define USARTn_HDEN_HDEN_Msk (0x01UL << USARTn_HDEN_HDEN_Pos) /*!< USARTn HDEN: HDEN Mask */ /* ------------------------------- USARTn_SCICTRL ------------------------------- */ #define USARTn_SCICTRL_SCIEN_Pos 0 /*!< USARTn SCICTRL: SCIEN Position */ #define USARTn_SCICTRL_SCIEN_Msk (0x01UL << USARTn_SCICTRL_SCIEN_Pos) /*!< USARTn SCICTRL: SCIEN Mask */ #define USARTn_SCICTRL_NACKDIS_Pos 1 /*!< USARTn SCICTRL: NACKDIS Position */ #define USARTn_SCICTRL_NACKDIS_Msk (0x01UL << USARTn_SCICTRL_NACKDIS_Pos) /*!< USARTn SCICTRL: NACKDIS Mask */ #define USARTn_SCICTRL_PROTSEL_Pos 2 /*!< USARTn SCICTRL: PROTSEL Position */ #define USARTn_SCICTRL_PROTSEL_Msk (0x01UL << USARTn_SCICTRL_PROTSEL_Pos) /*!< USARTn SCICTRL: PROTSEL Mask */ #define USARTn_SCICTRL_TXRETRY_Pos 5 /*!< USARTn SCICTRL: TXRETRY Position */ #define USARTn_SCICTRL_TXRETRY_Msk (0x07UL << USARTn_SCICTRL_TXRETRY_Pos) /*!< USARTn SCICTRL: TXRETRY Mask */ #define USARTn_SCICTRL_GUARDTIME_Pos 8 /*!< USARTn SCICTRL: GUARDTIME Position */ #define USARTn_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USARTn_SCICTRL_GUARDTIME_Pos) /*!< USARTn SCICTRL: GUARDTIME Mask */ /* ------------------------------ USARTn_RS485CTRL ------------------------------ */ #define USARTn_RS485CTRL_NMMEN_Pos 0 /*!< USARTn RS485CTRL: NMMEN Position */ #define USARTn_RS485CTRL_NMMEN_Msk (0x01UL << USARTn_RS485CTRL_NMMEN_Pos) /*!< USARTn RS485CTRL: NMMEN Mask */ #define USARTn_RS485CTRL_RXDIS_Pos 1 /*!< USARTn RS485CTRL: RXDIS Position */ #define USARTn_RS485CTRL_RXDIS_Msk (0x01UL << USARTn_RS485CTRL_RXDIS_Pos) /*!< USARTn RS485CTRL: RXDIS Mask */ #define USARTn_RS485CTRL_AADEN_Pos 2 /*!< USARTn RS485CTRL: AADEN Position */ #define USARTn_RS485CTRL_AADEN_Msk (0x01UL << USARTn_RS485CTRL_AADEN_Pos) /*!< USARTn RS485CTRL: AADEN Mask */ #define USARTn_RS485CTRL_DCTRL_Pos 4 /*!< USARTn RS485CTRL: DCTRL Position */ #define USARTn_RS485CTRL_DCTRL_Msk (0x01UL << USARTn_RS485CTRL_DCTRL_Pos) /*!< USARTn RS485CTRL: DCTRL Mask */ #define USARTn_RS485CTRL_OINV_Pos 5 /*!< USARTn RS485CTRL: OINV Position */ #define USARTn_RS485CTRL_OINV_Msk (0x01UL << USARTn_RS485CTRL_OINV_Pos) /*!< USARTn RS485CTRL: OINV Mask */ /* ---------------------------- USARTn_RS485ADRMATCH ---------------------------- */ #define USARTn_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USARTn RS485ADRMATCH: ADRMATCH Position */ #define USARTn_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USARTn_RS485ADRMATCH_ADRMATCH_Pos) /*!< USARTn RS485ADRMATCH: ADRMATCH Mask */ /* ------------------------------- USARTn_RS485DLY ------------------------------ */ #define USARTn_RS485DLY_DLY_Pos 0 /*!< USARTn RS485DLY: DLY Position */ #define USARTn_RS485DLY_DLY_Msk (0x000000ffUL << USARTn_RS485DLY_DLY_Pos) /*!< USARTn RS485DLY: DLY Mask */ /* ------------------------------- USARTn_SYNCCTRL ------------------------------ */ #define USARTn_SYNCCTRL_SYNC_Pos 0 /*!< USARTn SYNCCTRL: SYNC Position */ #define USARTn_SYNCCTRL_SYNC_Msk (0x01UL << USARTn_SYNCCTRL_SYNC_Pos) /*!< USARTn SYNCCTRL: SYNC Mask */ #define USARTn_SYNCCTRL_CSRC_Pos 1 /*!< USARTn SYNCCTRL: CSRC Position */ #define USARTn_SYNCCTRL_CSRC_Msk (0x01UL << USARTn_SYNCCTRL_CSRC_Pos) /*!< USARTn SYNCCTRL: CSRC Mask */ #define USARTn_SYNCCTRL_FES_Pos 2 /*!< USARTn SYNCCTRL: FES Position */ #define USARTn_SYNCCTRL_FES_Msk (0x01UL << USARTn_SYNCCTRL_FES_Pos) /*!< USARTn SYNCCTRL: FES Mask */ #define USARTn_SYNCCTRL_TSBYPASS_Pos 3 /*!< USARTn SYNCCTRL: TSBYPASS Position */ #define USARTn_SYNCCTRL_TSBYPASS_Msk (0x01UL << USARTn_SYNCCTRL_TSBYPASS_Pos) /*!< USARTn SYNCCTRL: TSBYPASS Mask */ #define USARTn_SYNCCTRL_CSCEN_Pos 4 /*!< USARTn SYNCCTRL: CSCEN Position */ #define USARTn_SYNCCTRL_CSCEN_Msk (0x01UL << USARTn_SYNCCTRL_CSCEN_Pos) /*!< USARTn SYNCCTRL: CSCEN Mask */ #define USARTn_SYNCCTRL_SSSDIS_Pos 5 /*!< USARTn SYNCCTRL: SSSDIS Position */ #define USARTn_SYNCCTRL_SSSDIS_Msk (0x01UL << USARTn_SYNCCTRL_SSSDIS_Pos) /*!< USARTn SYNCCTRL: SSSDIS Mask */ #define USARTn_SYNCCTRL_CCCLR_Pos 6 /*!< USARTn SYNCCTRL: CCCLR Position */ #define USARTn_SYNCCTRL_CCCLR_Msk (0x01UL << USARTn_SYNCCTRL_CCCLR_Pos) /*!< USARTn SYNCCTRL: CCCLR Mask */ /* --------------------------------- USARTn_TER --------------------------------- */ #define USARTn_TER_TXEN_Pos 0 /*!< USARTn TER: TXEN Position */ #define USARTn_TER_TXEN_Msk (0x01UL << USARTn_TER_TXEN_Pos) /*!< USARTn TER: TXEN Mask */ /* ================================================================================ */ /* ================ struct 'USART0' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- USART0_RBR --------------------------------- */ #define USART0_RBR_RBR_Pos 0 /*!< USART0 RBR: RBR Position */ #define USART0_RBR_RBR_Msk (0x000000ffUL << USART0_RBR_RBR_Pos) /*!< USART0 RBR: RBR Mask */ /* --------------------------------- USART0_THR --------------------------------- */ #define USART0_THR_THR_Pos 0 /*!< USART0 THR: THR Position */ #define USART0_THR_THR_Msk (0x000000ffUL << USART0_THR_THR_Pos) /*!< USART0 THR: THR Mask */ /* --------------------------------- USART0_DLL --------------------------------- */ #define USART0_DLL_DLLSB_Pos 0 /*!< USART0 DLL: DLLSB Position */ #define USART0_DLL_DLLSB_Msk (0x000000ffUL << USART0_DLL_DLLSB_Pos) /*!< USART0 DLL: DLLSB Mask */ /* --------------------------------- USART0_DLM --------------------------------- */ #define USART0_DLM_DLMSB_Pos 0 /*!< USART0 DLM: DLMSB Position */ #define USART0_DLM_DLMSB_Msk (0x000000ffUL << USART0_DLM_DLMSB_Pos) /*!< USART0 DLM: DLMSB Mask */ /* --------------------------------- USART0_IER --------------------------------- */ #define USART0_IER_RBRIE_Pos 0 /*!< USART0 IER: RBRIE Position */ #define USART0_IER_RBRIE_Msk (0x01UL << USART0_IER_RBRIE_Pos) /*!< USART0 IER: RBRIE Mask */ #define USART0_IER_THREIE_Pos 1 /*!< USART0 IER: THREIE Position */ #define USART0_IER_THREIE_Msk (0x01UL << USART0_IER_THREIE_Pos) /*!< USART0 IER: THREIE Mask */ #define USART0_IER_RXIE_Pos 2 /*!< USART0 IER: RXIE Position */ #define USART0_IER_RXIE_Msk (0x01UL << USART0_IER_RXIE_Pos) /*!< USART0 IER: RXIE Mask */ #define USART0_IER_ABEOINTEN_Pos 8 /*!< USART0 IER: ABEOINTEN Position */ #define USART0_IER_ABEOINTEN_Msk (0x01UL << USART0_IER_ABEOINTEN_Pos) /*!< USART0 IER: ABEOINTEN Mask */ #define USART0_IER_ABTOINTEN_Pos 9 /*!< USART0 IER: ABTOINTEN Position */ #define USART0_IER_ABTOINTEN_Msk (0x01UL << USART0_IER_ABTOINTEN_Pos) /*!< USART0 IER: ABTOINTEN Mask */ /* --------------------------------- USART0_IIR --------------------------------- */ #define USART0_IIR_INTSTATUS_Pos 0 /*!< USART0 IIR: INTSTATUS Position */ #define USART0_IIR_INTSTATUS_Msk (0x01UL << USART0_IIR_INTSTATUS_Pos) /*!< USART0 IIR: INTSTATUS Mask */ #define USART0_IIR_INTID_Pos 1 /*!< USART0 IIR: INTID Position */ #define USART0_IIR_INTID_Msk (0x07UL << USART0_IIR_INTID_Pos) /*!< USART0 IIR: INTID Mask */ #define USART0_IIR_FIFOENABLE_Pos 6 /*!< USART0 IIR: FIFOENABLE Position */ #define USART0_IIR_FIFOENABLE_Msk (0x03UL << USART0_IIR_FIFOENABLE_Pos) /*!< USART0 IIR: FIFOENABLE Mask */ #define USART0_IIR_ABEOINT_Pos 8 /*!< USART0 IIR: ABEOINT Position */ #define USART0_IIR_ABEOINT_Msk (0x01UL << USART0_IIR_ABEOINT_Pos) /*!< USART0 IIR: ABEOINT Mask */ #define USART0_IIR_ABTOINT_Pos 9 /*!< USART0 IIR: ABTOINT Position */ #define USART0_IIR_ABTOINT_Msk (0x01UL << USART0_IIR_ABTOINT_Pos) /*!< USART0 IIR: ABTOINT Mask */ /* --------------------------------- USART0_FCR --------------------------------- */ #define USART0_FCR_FIFOEN_Pos 0 /*!< USART0 FCR: FIFOEN Position */ #define USART0_FCR_FIFOEN_Msk (0x01UL << USART0_FCR_FIFOEN_Pos) /*!< USART0 FCR: FIFOEN Mask */ #define USART0_FCR_RXFIFORES_Pos 1 /*!< USART0 FCR: RXFIFORES Position */ #define USART0_FCR_RXFIFORES_Msk (0x01UL << USART0_FCR_RXFIFORES_Pos) /*!< USART0 FCR: RXFIFORES Mask */ #define USART0_FCR_TXFIFORES_Pos 2 /*!< USART0 FCR: TXFIFORES Position */ #define USART0_FCR_TXFIFORES_Msk (0x01UL << USART0_FCR_TXFIFORES_Pos) /*!< USART0 FCR: TXFIFORES Mask */ #define USART0_FCR_DMAMODE_Pos 3 /*!< USART0 FCR: DMAMODE Position */ #define USART0_FCR_DMAMODE_Msk (0x01UL << USART0_FCR_DMAMODE_Pos) /*!< USART0 FCR: DMAMODE Mask */ #define USART0_FCR_RXTRIGLVL_Pos 6 /*!< USART0 FCR: RXTRIGLVL Position */ #define USART0_FCR_RXTRIGLVL_Msk (0x03UL << USART0_FCR_RXTRIGLVL_Pos) /*!< USART0 FCR: RXTRIGLVL Mask */ /* --------------------------------- USART0_LCR --------------------------------- */ #define USART0_LCR_WLS_Pos 0 /*!< USART0 LCR: WLS Position */ #define USART0_LCR_WLS_Msk (0x03UL << USART0_LCR_WLS_Pos) /*!< USART0 LCR: WLS Mask */ #define USART0_LCR_SBS_Pos 2 /*!< USART0 LCR: SBS Position */ #define USART0_LCR_SBS_Msk (0x01UL << USART0_LCR_SBS_Pos) /*!< USART0 LCR: SBS Mask */ #define USART0_LCR_PE_Pos 3 /*!< USART0 LCR: PE Position */ #define USART0_LCR_PE_Msk (0x01UL << USART0_LCR_PE_Pos) /*!< USART0 LCR: PE Mask */ #define USART0_LCR_PS_Pos 4 /*!< USART0 LCR: PS Position */ #define USART0_LCR_PS_Msk (0x03UL << USART0_LCR_PS_Pos) /*!< USART0 LCR: PS Mask */ #define USART0_LCR_BC_Pos 6 /*!< USART0 LCR: BC Position */ #define USART0_LCR_BC_Msk (0x01UL << USART0_LCR_BC_Pos) /*!< USART0 LCR: BC Mask */ #define USART0_LCR_DLAB_Pos 7 /*!< USART0 LCR: DLAB Position */ #define USART0_LCR_DLAB_Msk (0x01UL << USART0_LCR_DLAB_Pos) /*!< USART0 LCR: DLAB Mask */ /* --------------------------------- USART0_LSR --------------------------------- */ #define USART0_LSR_RDR_Pos 0 /*!< USART0 LSR: RDR Position */ #define USART0_LSR_RDR_Msk (0x01UL << USART0_LSR_RDR_Pos) /*!< USART0 LSR: RDR Mask */ #define USART0_LSR_OE_Pos 1 /*!< USART0 LSR: OE Position */ #define USART0_LSR_OE_Msk (0x01UL << USART0_LSR_OE_Pos) /*!< USART0 LSR: OE Mask */ #define USART0_LSR_PE_Pos 2 /*!< USART0 LSR: PE Position */ #define USART0_LSR_PE_Msk (0x01UL << USART0_LSR_PE_Pos) /*!< USART0 LSR: PE Mask */ #define USART0_LSR_FE_Pos 3 /*!< USART0 LSR: FE Position */ #define USART0_LSR_FE_Msk (0x01UL << USART0_LSR_FE_Pos) /*!< USART0 LSR: FE Mask */ #define USART0_LSR_BI_Pos 4 /*!< USART0 LSR: BI Position */ #define USART0_LSR_BI_Msk (0x01UL << USART0_LSR_BI_Pos) /*!< USART0 LSR: BI Mask */ #define USART0_LSR_THRE_Pos 5 /*!< USART0 LSR: THRE Position */ #define USART0_LSR_THRE_Msk (0x01UL << USART0_LSR_THRE_Pos) /*!< USART0 LSR: THRE Mask */ #define USART0_LSR_TEMT_Pos 6 /*!< USART0 LSR: TEMT Position */ #define USART0_LSR_TEMT_Msk (0x01UL << USART0_LSR_TEMT_Pos) /*!< USART0 LSR: TEMT Mask */ #define USART0_LSR_RXFE_Pos 7 /*!< USART0 LSR: RXFE Position */ #define USART0_LSR_RXFE_Msk (0x01UL << USART0_LSR_RXFE_Pos) /*!< USART0 LSR: RXFE Mask */ #define USART0_LSR_TXERR_Pos 8 /*!< USART0 LSR: TXERR Position */ #define USART0_LSR_TXERR_Msk (0x01UL << USART0_LSR_TXERR_Pos) /*!< USART0 LSR: TXERR Mask */ /* --------------------------------- USART0_SCR --------------------------------- */ #define USART0_SCR_PAD_Pos 0 /*!< USART0 SCR: PAD Position */ #define USART0_SCR_PAD_Msk (0x000000ffUL << USART0_SCR_PAD_Pos) /*!< USART0 SCR: PAD Mask */ /* --------------------------------- USART0_ACR --------------------------------- */ #define USART0_ACR_START_Pos 0 /*!< USART0 ACR: START Position */ #define USART0_ACR_START_Msk (0x01UL << USART0_ACR_START_Pos) /*!< USART0 ACR: START Mask */ #define USART0_ACR_MODE_Pos 1 /*!< USART0 ACR: MODE Position */ #define USART0_ACR_MODE_Msk (0x01UL << USART0_ACR_MODE_Pos) /*!< USART0 ACR: MODE Mask */ #define USART0_ACR_AUTORESTART_Pos 2 /*!< USART0 ACR: AUTORESTART Position */ #define USART0_ACR_AUTORESTART_Msk (0x01UL << USART0_ACR_AUTORESTART_Pos) /*!< USART0 ACR: AUTORESTART Mask */ #define USART0_ACR_ABEOINTCLR_Pos 8 /*!< USART0 ACR: ABEOINTCLR Position */ #define USART0_ACR_ABEOINTCLR_Msk (0x01UL << USART0_ACR_ABEOINTCLR_Pos) /*!< USART0 ACR: ABEOINTCLR Mask */ #define USART0_ACR_ABTOINTCLR_Pos 9 /*!< USART0 ACR: ABTOINTCLR Position */ #define USART0_ACR_ABTOINTCLR_Msk (0x01UL << USART0_ACR_ABTOINTCLR_Pos) /*!< USART0 ACR: ABTOINTCLR Mask */ /* --------------------------------- USART0_ICR --------------------------------- */ #define USART0_ICR_IRDAEN_Pos 0 /*!< USART0 ICR: IRDAEN Position */ #define USART0_ICR_IRDAEN_Msk (0x01UL << USART0_ICR_IRDAEN_Pos) /*!< USART0 ICR: IRDAEN Mask */ #define USART0_ICR_IRDAINV_Pos 1 /*!< USART0 ICR: IRDAINV Position */ #define USART0_ICR_IRDAINV_Msk (0x01UL << USART0_ICR_IRDAINV_Pos) /*!< USART0 ICR: IRDAINV Mask */ #define USART0_ICR_FIXPULSEEN_Pos 2 /*!< USART0 ICR: FIXPULSEEN Position */ #define USART0_ICR_FIXPULSEEN_Msk (0x01UL << USART0_ICR_FIXPULSEEN_Pos) /*!< USART0 ICR: FIXPULSEEN Mask */ #define USART0_ICR_PULSEDIV_Pos 3 /*!< USART0 ICR: PULSEDIV Position */ #define USART0_ICR_PULSEDIV_Msk (0x07UL << USART0_ICR_PULSEDIV_Pos) /*!< USART0 ICR: PULSEDIV Mask */ /* --------------------------------- USART0_FDR --------------------------------- */ #define USART0_FDR_DIVADDVAL_Pos 0 /*!< USART0 FDR: DIVADDVAL Position */ #define USART0_FDR_DIVADDVAL_Msk (0x0fUL << USART0_FDR_DIVADDVAL_Pos) /*!< USART0 FDR: DIVADDVAL Mask */ #define USART0_FDR_MULVAL_Pos 4 /*!< USART0 FDR: MULVAL Position */ #define USART0_FDR_MULVAL_Msk (0x0fUL << USART0_FDR_MULVAL_Pos) /*!< USART0 FDR: MULVAL Mask */ /* --------------------------------- USART0_OSR --------------------------------- */ #define USART0_OSR_OSFRAC_Pos 1 /*!< USART0 OSR: OSFRAC Position */ #define USART0_OSR_OSFRAC_Msk (0x07UL << USART0_OSR_OSFRAC_Pos) /*!< USART0 OSR: OSFRAC Mask */ #define USART0_OSR_OSINT_Pos 4 /*!< USART0 OSR: OSINT Position */ #define USART0_OSR_OSINT_Msk (0x0fUL << USART0_OSR_OSINT_Pos) /*!< USART0 OSR: OSINT Mask */ #define USART0_OSR_FDINT_Pos 8 /*!< USART0 OSR: FDINT Position */ #define USART0_OSR_FDINT_Msk (0x7fUL << USART0_OSR_FDINT_Pos) /*!< USART0 OSR: FDINT Mask */ /* --------------------------------- USART0_HDEN -------------------------------- */ #define USART0_HDEN_HDEN_Pos 0 /*!< USART0 HDEN: HDEN Position */ #define USART0_HDEN_HDEN_Msk (0x01UL << USART0_HDEN_HDEN_Pos) /*!< USART0 HDEN: HDEN Mask */ /* ------------------------------- USART0_SCICTRL ------------------------------- */ #define USART0_SCICTRL_SCIEN_Pos 0 /*!< USART0 SCICTRL: SCIEN Position */ #define USART0_SCICTRL_SCIEN_Msk (0x01UL << USART0_SCICTRL_SCIEN_Pos) /*!< USART0 SCICTRL: SCIEN Mask */ #define USART0_SCICTRL_NACKDIS_Pos 1 /*!< USART0 SCICTRL: NACKDIS Position */ #define USART0_SCICTRL_NACKDIS_Msk (0x01UL << USART0_SCICTRL_NACKDIS_Pos) /*!< USART0 SCICTRL: NACKDIS Mask */ #define USART0_SCICTRL_PROTSEL_Pos 2 /*!< USART0 SCICTRL: PROTSEL Position */ #define USART0_SCICTRL_PROTSEL_Msk (0x01UL << USART0_SCICTRL_PROTSEL_Pos) /*!< USART0 SCICTRL: PROTSEL Mask */ #define USART0_SCICTRL_TXRETRY_Pos 5 /*!< USART0 SCICTRL: TXRETRY Position */ #define USART0_SCICTRL_TXRETRY_Msk (0x07UL << USART0_SCICTRL_TXRETRY_Pos) /*!< USART0 SCICTRL: TXRETRY Mask */ #define USART0_SCICTRL_GUARDTIME_Pos 8 /*!< USART0 SCICTRL: GUARDTIME Position */ #define USART0_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART0_SCICTRL_GUARDTIME_Pos) /*!< USART0 SCICTRL: GUARDTIME Mask */ /* ------------------------------ USART0_RS485CTRL ------------------------------ */ #define USART0_RS485CTRL_NMMEN_Pos 0 /*!< USART0 RS485CTRL: NMMEN Position */ #define USART0_RS485CTRL_NMMEN_Msk (0x01UL << USART0_RS485CTRL_NMMEN_Pos) /*!< USART0 RS485CTRL: NMMEN Mask */ #define USART0_RS485CTRL_RXDIS_Pos 1 /*!< USART0 RS485CTRL: RXDIS Position */ #define USART0_RS485CTRL_RXDIS_Msk (0x01UL << USART0_RS485CTRL_RXDIS_Pos) /*!< USART0 RS485CTRL: RXDIS Mask */ #define USART0_RS485CTRL_AADEN_Pos 2 /*!< USART0 RS485CTRL: AADEN Position */ #define USART0_RS485CTRL_AADEN_Msk (0x01UL << USART0_RS485CTRL_AADEN_Pos) /*!< USART0 RS485CTRL: AADEN Mask */ #define USART0_RS485CTRL_DCTRL_Pos 4 /*!< USART0 RS485CTRL: DCTRL Position */ #define USART0_RS485CTRL_DCTRL_Msk (0x01UL << USART0_RS485CTRL_DCTRL_Pos) /*!< USART0 RS485CTRL: DCTRL Mask */ #define USART0_RS485CTRL_OINV_Pos 5 /*!< USART0 RS485CTRL: OINV Position */ #define USART0_RS485CTRL_OINV_Msk (0x01UL << USART0_RS485CTRL_OINV_Pos) /*!< USART0 RS485CTRL: OINV Mask */ /* ---------------------------- USART0_RS485ADRMATCH ---------------------------- */ #define USART0_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART0 RS485ADRMATCH: ADRMATCH Position */ #define USART0_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART0_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART0 RS485ADRMATCH: ADRMATCH Mask */ /* ------------------------------- USART0_RS485DLY ------------------------------ */ #define USART0_RS485DLY_DLY_Pos 0 /*!< USART0 RS485DLY: DLY Position */ #define USART0_RS485DLY_DLY_Msk (0x000000ffUL << USART0_RS485DLY_DLY_Pos) /*!< USART0 RS485DLY: DLY Mask */ /* ------------------------------- USART0_SYNCCTRL ------------------------------ */ #define USART0_SYNCCTRL_SYNC_Pos 0 /*!< USART0 SYNCCTRL: SYNC Position */ #define USART0_SYNCCTRL_SYNC_Msk (0x01UL << USART0_SYNCCTRL_SYNC_Pos) /*!< USART0 SYNCCTRL: SYNC Mask */ #define USART0_SYNCCTRL_CSRC_Pos 1 /*!< USART0 SYNCCTRL: CSRC Position */ #define USART0_SYNCCTRL_CSRC_Msk (0x01UL << USART0_SYNCCTRL_CSRC_Pos) /*!< USART0 SYNCCTRL: CSRC Mask */ #define USART0_SYNCCTRL_FES_Pos 2 /*!< USART0 SYNCCTRL: FES Position */ #define USART0_SYNCCTRL_FES_Msk (0x01UL << USART0_SYNCCTRL_FES_Pos) /*!< USART0 SYNCCTRL: FES Mask */ #define USART0_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART0 SYNCCTRL: TSBYPASS Position */ #define USART0_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART0_SYNCCTRL_TSBYPASS_Pos) /*!< USART0 SYNCCTRL: TSBYPASS Mask */ #define USART0_SYNCCTRL_CSCEN_Pos 4 /*!< USART0 SYNCCTRL: CSCEN Position */ #define USART0_SYNCCTRL_CSCEN_Msk (0x01UL << USART0_SYNCCTRL_CSCEN_Pos) /*!< USART0 SYNCCTRL: CSCEN Mask */ #define USART0_SYNCCTRL_SSSDIS_Pos 5 /*!< USART0 SYNCCTRL: SSSDIS Position */ #define USART0_SYNCCTRL_SSSDIS_Msk (0x01UL << USART0_SYNCCTRL_SSSDIS_Pos) /*!< USART0 SYNCCTRL: SSSDIS Mask */ #define USART0_SYNCCTRL_CCCLR_Pos 6 /*!< USART0 SYNCCTRL: CCCLR Position */ #define USART0_SYNCCTRL_CCCLR_Msk (0x01UL << USART0_SYNCCTRL_CCCLR_Pos) /*!< USART0 SYNCCTRL: CCCLR Mask */ /* --------------------------------- USART0_TER --------------------------------- */ #define USART0_TER_TXEN_Pos 0 /*!< USART0 TER: TXEN Position */ #define USART0_TER_TXEN_Msk (0x01UL << USART0_TER_TXEN_Pos) /*!< USART0 TER: TXEN Mask */ /* ================================================================================ */ /* ================ struct 'USART2' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- USART2_DLL --------------------------------- */ #define USART2_DLL_DLLSB_Pos 0 /*!< USART2 DLL: DLLSB Position */ #define USART2_DLL_DLLSB_Msk (0x000000ffUL << USART2_DLL_DLLSB_Pos) /*!< USART2 DLL: DLLSB Mask */ /* --------------------------------- USART2_THR --------------------------------- */ #define USART2_THR_THR_Pos 0 /*!< USART2 THR: THR Position */ #define USART2_THR_THR_Msk (0x000000ffUL << USART2_THR_THR_Pos) /*!< USART2 THR: THR Mask */ /* --------------------------------- USART2_RBR --------------------------------- */ #define USART2_RBR_RBR_Pos 0 /*!< USART2 RBR: RBR Position */ #define USART2_RBR_RBR_Msk (0x000000ffUL << USART2_RBR_RBR_Pos) /*!< USART2 RBR: RBR Mask */ /* --------------------------------- USART2_IER --------------------------------- */ #define USART2_IER_RBRIE_Pos 0 /*!< USART2 IER: RBRIE Position */ #define USART2_IER_RBRIE_Msk (0x01UL << USART2_IER_RBRIE_Pos) /*!< USART2 IER: RBRIE Mask */ #define USART2_IER_THREIE_Pos 1 /*!< USART2 IER: THREIE Position */ #define USART2_IER_THREIE_Msk (0x01UL << USART2_IER_THREIE_Pos) /*!< USART2 IER: THREIE Mask */ #define USART2_IER_RXIE_Pos 2 /*!< USART2 IER: RXIE Position */ #define USART2_IER_RXIE_Msk (0x01UL << USART2_IER_RXIE_Pos) /*!< USART2 IER: RXIE Mask */ #define USART2_IER_ABEOINTEN_Pos 8 /*!< USART2 IER: ABEOINTEN Position */ #define USART2_IER_ABEOINTEN_Msk (0x01UL << USART2_IER_ABEOINTEN_Pos) /*!< USART2 IER: ABEOINTEN Mask */ #define USART2_IER_ABTOINTEN_Pos 9 /*!< USART2 IER: ABTOINTEN Position */ #define USART2_IER_ABTOINTEN_Msk (0x01UL << USART2_IER_ABTOINTEN_Pos) /*!< USART2 IER: ABTOINTEN Mask */ /* --------------------------------- USART2_DLM --------------------------------- */ #define USART2_DLM_DLMSB_Pos 0 /*!< USART2 DLM: DLMSB Position */ #define USART2_DLM_DLMSB_Msk (0x000000ffUL << USART2_DLM_DLMSB_Pos) /*!< USART2 DLM: DLMSB Mask */ /* --------------------------------- USART2_FCR --------------------------------- */ #define USART2_FCR_FIFOEN_Pos 0 /*!< USART2 FCR: FIFOEN Position */ #define USART2_FCR_FIFOEN_Msk (0x01UL << USART2_FCR_FIFOEN_Pos) /*!< USART2 FCR: FIFOEN Mask */ #define USART2_FCR_RXFIFORES_Pos 1 /*!< USART2 FCR: RXFIFORES Position */ #define USART2_FCR_RXFIFORES_Msk (0x01UL << USART2_FCR_RXFIFORES_Pos) /*!< USART2 FCR: RXFIFORES Mask */ #define USART2_FCR_TXFIFORES_Pos 2 /*!< USART2 FCR: TXFIFORES Position */ #define USART2_FCR_TXFIFORES_Msk (0x01UL << USART2_FCR_TXFIFORES_Pos) /*!< USART2 FCR: TXFIFORES Mask */ #define USART2_FCR_DMAMODE_Pos 3 /*!< USART2 FCR: DMAMODE Position */ #define USART2_FCR_DMAMODE_Msk (0x01UL << USART2_FCR_DMAMODE_Pos) /*!< USART2 FCR: DMAMODE Mask */ #define USART2_FCR_RXTRIGLVL_Pos 6 /*!< USART2 FCR: RXTRIGLVL Position */ #define USART2_FCR_RXTRIGLVL_Msk (0x03UL << USART2_FCR_RXTRIGLVL_Pos) /*!< USART2 FCR: RXTRIGLVL Mask */ /* --------------------------------- USART2_IIR --------------------------------- */ #define USART2_IIR_INTSTATUS_Pos 0 /*!< USART2 IIR: INTSTATUS Position */ #define USART2_IIR_INTSTATUS_Msk (0x01UL << USART2_IIR_INTSTATUS_Pos) /*!< USART2 IIR: INTSTATUS Mask */ #define USART2_IIR_INTID_Pos 1 /*!< USART2 IIR: INTID Position */ #define USART2_IIR_INTID_Msk (0x07UL << USART2_IIR_INTID_Pos) /*!< USART2 IIR: INTID Mask */ #define USART2_IIR_FIFOENABLE_Pos 6 /*!< USART2 IIR: FIFOENABLE Position */ #define USART2_IIR_FIFOENABLE_Msk (0x03UL << USART2_IIR_FIFOENABLE_Pos) /*!< USART2 IIR: FIFOENABLE Mask */ #define USART2_IIR_ABEOINT_Pos 8 /*!< USART2 IIR: ABEOINT Position */ #define USART2_IIR_ABEOINT_Msk (0x01UL << USART2_IIR_ABEOINT_Pos) /*!< USART2 IIR: ABEOINT Mask */ #define USART2_IIR_ABTOINT_Pos 9 /*!< USART2 IIR: ABTOINT Position */ #define USART2_IIR_ABTOINT_Msk (0x01UL << USART2_IIR_ABTOINT_Pos) /*!< USART2 IIR: ABTOINT Mask */ /* --------------------------------- USART2_LCR --------------------------------- */ #define USART2_LCR_WLS_Pos 0 /*!< USART2 LCR: WLS Position */ #define USART2_LCR_WLS_Msk (0x03UL << USART2_LCR_WLS_Pos) /*!< USART2 LCR: WLS Mask */ #define USART2_LCR_SBS_Pos 2 /*!< USART2 LCR: SBS Position */ #define USART2_LCR_SBS_Msk (0x01UL << USART2_LCR_SBS_Pos) /*!< USART2 LCR: SBS Mask */ #define USART2_LCR_PE_Pos 3 /*!< USART2 LCR: PE Position */ #define USART2_LCR_PE_Msk (0x01UL << USART2_LCR_PE_Pos) /*!< USART2 LCR: PE Mask */ #define USART2_LCR_PS_Pos 4 /*!< USART2 LCR: PS Position */ #define USART2_LCR_PS_Msk (0x03UL << USART2_LCR_PS_Pos) /*!< USART2 LCR: PS Mask */ #define USART2_LCR_BC_Pos 6 /*!< USART2 LCR: BC Position */ #define USART2_LCR_BC_Msk (0x01UL << USART2_LCR_BC_Pos) /*!< USART2 LCR: BC Mask */ #define USART2_LCR_DLAB_Pos 7 /*!< USART2 LCR: DLAB Position */ #define USART2_LCR_DLAB_Msk (0x01UL << USART2_LCR_DLAB_Pos) /*!< USART2 LCR: DLAB Mask */ /* --------------------------------- USART2_LSR --------------------------------- */ #define USART2_LSR_RDR_Pos 0 /*!< USART2 LSR: RDR Position */ #define USART2_LSR_RDR_Msk (0x01UL << USART2_LSR_RDR_Pos) /*!< USART2 LSR: RDR Mask */ #define USART2_LSR_OE_Pos 1 /*!< USART2 LSR: OE Position */ #define USART2_LSR_OE_Msk (0x01UL << USART2_LSR_OE_Pos) /*!< USART2 LSR: OE Mask */ #define USART2_LSR_PE_Pos 2 /*!< USART2 LSR: PE Position */ #define USART2_LSR_PE_Msk (0x01UL << USART2_LSR_PE_Pos) /*!< USART2 LSR: PE Mask */ #define USART2_LSR_FE_Pos 3 /*!< USART2 LSR: FE Position */ #define USART2_LSR_FE_Msk (0x01UL << USART2_LSR_FE_Pos) /*!< USART2 LSR: FE Mask */ #define USART2_LSR_BI_Pos 4 /*!< USART2 LSR: BI Position */ #define USART2_LSR_BI_Msk (0x01UL << USART2_LSR_BI_Pos) /*!< USART2 LSR: BI Mask */ #define USART2_LSR_THRE_Pos 5 /*!< USART2 LSR: THRE Position */ #define USART2_LSR_THRE_Msk (0x01UL << USART2_LSR_THRE_Pos) /*!< USART2 LSR: THRE Mask */ #define USART2_LSR_TEMT_Pos 6 /*!< USART2 LSR: TEMT Position */ #define USART2_LSR_TEMT_Msk (0x01UL << USART2_LSR_TEMT_Pos) /*!< USART2 LSR: TEMT Mask */ #define USART2_LSR_RXFE_Pos 7 /*!< USART2 LSR: RXFE Position */ #define USART2_LSR_RXFE_Msk (0x01UL << USART2_LSR_RXFE_Pos) /*!< USART2 LSR: RXFE Mask */ #define USART2_LSR_TXERR_Pos 8 /*!< USART2 LSR: TXERR Position */ #define USART2_LSR_TXERR_Msk (0x01UL << USART2_LSR_TXERR_Pos) /*!< USART2 LSR: TXERR Mask */ /* --------------------------------- USART2_SCR --------------------------------- */ #define USART2_SCR_PAD_Pos 0 /*!< USART2 SCR: PAD Position */ #define USART2_SCR_PAD_Msk (0x000000ffUL << USART2_SCR_PAD_Pos) /*!< USART2 SCR: PAD Mask */ /* --------------------------------- USART2_ACR --------------------------------- */ #define USART2_ACR_START_Pos 0 /*!< USART2 ACR: START Position */ #define USART2_ACR_START_Msk (0x01UL << USART2_ACR_START_Pos) /*!< USART2 ACR: START Mask */ #define USART2_ACR_MODE_Pos 1 /*!< USART2 ACR: MODE Position */ #define USART2_ACR_MODE_Msk (0x01UL << USART2_ACR_MODE_Pos) /*!< USART2 ACR: MODE Mask */ #define USART2_ACR_AUTORESTART_Pos 2 /*!< USART2 ACR: AUTORESTART Position */ #define USART2_ACR_AUTORESTART_Msk (0x01UL << USART2_ACR_AUTORESTART_Pos) /*!< USART2 ACR: AUTORESTART Mask */ #define USART2_ACR_ABEOINTCLR_Pos 8 /*!< USART2 ACR: ABEOINTCLR Position */ #define USART2_ACR_ABEOINTCLR_Msk (0x01UL << USART2_ACR_ABEOINTCLR_Pos) /*!< USART2 ACR: ABEOINTCLR Mask */ #define USART2_ACR_ABTOINTCLR_Pos 9 /*!< USART2 ACR: ABTOINTCLR Position */ #define USART2_ACR_ABTOINTCLR_Msk (0x01UL << USART2_ACR_ABTOINTCLR_Pos) /*!< USART2 ACR: ABTOINTCLR Mask */ /* --------------------------------- USART2_ICR --------------------------------- */ #define USART2_ICR_IRDAEN_Pos 0 /*!< USART2 ICR: IRDAEN Position */ #define USART2_ICR_IRDAEN_Msk (0x01UL << USART2_ICR_IRDAEN_Pos) /*!< USART2 ICR: IRDAEN Mask */ #define USART2_ICR_IRDAINV_Pos 1 /*!< USART2 ICR: IRDAINV Position */ #define USART2_ICR_IRDAINV_Msk (0x01UL << USART2_ICR_IRDAINV_Pos) /*!< USART2 ICR: IRDAINV Mask */ #define USART2_ICR_FIXPULSEEN_Pos 2 /*!< USART2 ICR: FIXPULSEEN Position */ #define USART2_ICR_FIXPULSEEN_Msk (0x01UL << USART2_ICR_FIXPULSEEN_Pos) /*!< USART2 ICR: FIXPULSEEN Mask */ #define USART2_ICR_PULSEDIV_Pos 3 /*!< USART2 ICR: PULSEDIV Position */ #define USART2_ICR_PULSEDIV_Msk (0x07UL << USART2_ICR_PULSEDIV_Pos) /*!< USART2 ICR: PULSEDIV Mask */ /* --------------------------------- USART2_FDR --------------------------------- */ #define USART2_FDR_DIVADDVAL_Pos 0 /*!< USART2 FDR: DIVADDVAL Position */ #define USART2_FDR_DIVADDVAL_Msk (0x0fUL << USART2_FDR_DIVADDVAL_Pos) /*!< USART2 FDR: DIVADDVAL Mask */ #define USART2_FDR_MULVAL_Pos 4 /*!< USART2 FDR: MULVAL Position */ #define USART2_FDR_MULVAL_Msk (0x0fUL << USART2_FDR_MULVAL_Pos) /*!< USART2 FDR: MULVAL Mask */ /* --------------------------------- USART2_OSR --------------------------------- */ #define USART2_OSR_OSFRAC_Pos 1 /*!< USART2 OSR: OSFRAC Position */ #define USART2_OSR_OSFRAC_Msk (0x07UL << USART2_OSR_OSFRAC_Pos) /*!< USART2 OSR: OSFRAC Mask */ #define USART2_OSR_OSINT_Pos 4 /*!< USART2 OSR: OSINT Position */ #define USART2_OSR_OSINT_Msk (0x0fUL << USART2_OSR_OSINT_Pos) /*!< USART2 OSR: OSINT Mask */ #define USART2_OSR_FDINT_Pos 8 /*!< USART2 OSR: FDINT Position */ #define USART2_OSR_FDINT_Msk (0x7fUL << USART2_OSR_FDINT_Pos) /*!< USART2 OSR: FDINT Mask */ /* --------------------------------- USART2_HDEN -------------------------------- */ #define USART2_HDEN_HDEN_Pos 0 /*!< USART2 HDEN: HDEN Position */ #define USART2_HDEN_HDEN_Msk (0x01UL << USART2_HDEN_HDEN_Pos) /*!< USART2 HDEN: HDEN Mask */ /* ------------------------------- USART2_SCICTRL ------------------------------- */ #define USART2_SCICTRL_SCIEN_Pos 0 /*!< USART2 SCICTRL: SCIEN Position */ #define USART2_SCICTRL_SCIEN_Msk (0x01UL << USART2_SCICTRL_SCIEN_Pos) /*!< USART2 SCICTRL: SCIEN Mask */ #define USART2_SCICTRL_NACKDIS_Pos 1 /*!< USART2 SCICTRL: NACKDIS Position */ #define USART2_SCICTRL_NACKDIS_Msk (0x01UL << USART2_SCICTRL_NACKDIS_Pos) /*!< USART2 SCICTRL: NACKDIS Mask */ #define USART2_SCICTRL_PROTSEL_Pos 2 /*!< USART2 SCICTRL: PROTSEL Position */ #define USART2_SCICTRL_PROTSEL_Msk (0x01UL << USART2_SCICTRL_PROTSEL_Pos) /*!< USART2 SCICTRL: PROTSEL Mask */ #define USART2_SCICTRL_TXRETRY_Pos 5 /*!< USART2 SCICTRL: TXRETRY Position */ #define USART2_SCICTRL_TXRETRY_Msk (0x07UL << USART2_SCICTRL_TXRETRY_Pos) /*!< USART2 SCICTRL: TXRETRY Mask */ #define USART2_SCICTRL_GUARDTIME_Pos 8 /*!< USART2 SCICTRL: GUARDTIME Position */ #define USART2_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART2_SCICTRL_GUARDTIME_Pos) /*!< USART2 SCICTRL: GUARDTIME Mask */ /* ------------------------------ USART2_RS485CTRL ------------------------------ */ #define USART2_RS485CTRL_NMMEN_Pos 0 /*!< USART2 RS485CTRL: NMMEN Position */ #define USART2_RS485CTRL_NMMEN_Msk (0x01UL << USART2_RS485CTRL_NMMEN_Pos) /*!< USART2 RS485CTRL: NMMEN Mask */ #define USART2_RS485CTRL_RXDIS_Pos 1 /*!< USART2 RS485CTRL: RXDIS Position */ #define USART2_RS485CTRL_RXDIS_Msk (0x01UL << USART2_RS485CTRL_RXDIS_Pos) /*!< USART2 RS485CTRL: RXDIS Mask */ #define USART2_RS485CTRL_AADEN_Pos 2 /*!< USART2 RS485CTRL: AADEN Position */ #define USART2_RS485CTRL_AADEN_Msk (0x01UL << USART2_RS485CTRL_AADEN_Pos) /*!< USART2 RS485CTRL: AADEN Mask */ #define USART2_RS485CTRL_DCTRL_Pos 4 /*!< USART2 RS485CTRL: DCTRL Position */ #define USART2_RS485CTRL_DCTRL_Msk (0x01UL << USART2_RS485CTRL_DCTRL_Pos) /*!< USART2 RS485CTRL: DCTRL Mask */ #define USART2_RS485CTRL_OINV_Pos 5 /*!< USART2 RS485CTRL: OINV Position */ #define USART2_RS485CTRL_OINV_Msk (0x01UL << USART2_RS485CTRL_OINV_Pos) /*!< USART2 RS485CTRL: OINV Mask */ /* ---------------------------- USART2_RS485ADRMATCH ---------------------------- */ #define USART2_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART2 RS485ADRMATCH: ADRMATCH Position */ #define USART2_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART2_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART2 RS485ADRMATCH: ADRMATCH Mask */ /* ------------------------------- USART2_RS485DLY ------------------------------ */ #define USART2_RS485DLY_DLY_Pos 0 /*!< USART2 RS485DLY: DLY Position */ #define USART2_RS485DLY_DLY_Msk (0x000000ffUL << USART2_RS485DLY_DLY_Pos) /*!< USART2 RS485DLY: DLY Mask */ /* ------------------------------- USART2_SYNCCTRL ------------------------------ */ #define USART2_SYNCCTRL_SYNC_Pos 0 /*!< USART2 SYNCCTRL: SYNC Position */ #define USART2_SYNCCTRL_SYNC_Msk (0x01UL << USART2_SYNCCTRL_SYNC_Pos) /*!< USART2 SYNCCTRL: SYNC Mask */ #define USART2_SYNCCTRL_CSRC_Pos 1 /*!< USART2 SYNCCTRL: CSRC Position */ #define USART2_SYNCCTRL_CSRC_Msk (0x01UL << USART2_SYNCCTRL_CSRC_Pos) /*!< USART2 SYNCCTRL: CSRC Mask */ #define USART2_SYNCCTRL_FES_Pos 2 /*!< USART2 SYNCCTRL: FES Position */ #define USART2_SYNCCTRL_FES_Msk (0x01UL << USART2_SYNCCTRL_FES_Pos) /*!< USART2 SYNCCTRL: FES Mask */ #define USART2_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART2 SYNCCTRL: TSBYPASS Position */ #define USART2_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART2_SYNCCTRL_TSBYPASS_Pos) /*!< USART2 SYNCCTRL: TSBYPASS Mask */ #define USART2_SYNCCTRL_CSCEN_Pos 4 /*!< USART2 SYNCCTRL: CSCEN Position */ #define USART2_SYNCCTRL_CSCEN_Msk (0x01UL << USART2_SYNCCTRL_CSCEN_Pos) /*!< USART2 SYNCCTRL: CSCEN Mask */ #define USART2_SYNCCTRL_SSSDIS_Pos 5 /*!< USART2 SYNCCTRL: SSSDIS Position */ #define USART2_SYNCCTRL_SSSDIS_Msk (0x01UL << USART2_SYNCCTRL_SSSDIS_Pos) /*!< USART2 SYNCCTRL: SSSDIS Mask */ #define USART2_SYNCCTRL_CCCLR_Pos 6 /*!< USART2 SYNCCTRL: CCCLR Position */ #define USART2_SYNCCTRL_CCCLR_Msk (0x01UL << USART2_SYNCCTRL_CCCLR_Pos) /*!< USART2 SYNCCTRL: CCCLR Mask */ /* --------------------------------- USART2_TER --------------------------------- */ #define USART2_TER_TXEN_Pos 0 /*!< USART2 TER: TXEN Position */ #define USART2_TER_TXEN_Msk (0x01UL << USART2_TER_TXEN_Pos) /*!< USART2 TER: TXEN Mask */ /* ================================================================================ */ /* ================ struct 'USART3' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- USART3_DLL --------------------------------- */ #define USART3_DLL_DLLSB_Pos 0 /*!< USART3 DLL: DLLSB Position */ #define USART3_DLL_DLLSB_Msk (0x000000ffUL << USART3_DLL_DLLSB_Pos) /*!< USART3 DLL: DLLSB Mask */ /* --------------------------------- USART3_THR --------------------------------- */ #define USART3_THR_THR_Pos 0 /*!< USART3 THR: THR Position */ #define USART3_THR_THR_Msk (0x000000ffUL << USART3_THR_THR_Pos) /*!< USART3 THR: THR Mask */ /* --------------------------------- USART3_RBR --------------------------------- */ #define USART3_RBR_RBR_Pos 0 /*!< USART3 RBR: RBR Position */ #define USART3_RBR_RBR_Msk (0x000000ffUL << USART3_RBR_RBR_Pos) /*!< USART3 RBR: RBR Mask */ /* --------------------------------- USART3_IER --------------------------------- */ #define USART3_IER_RBRIE_Pos 0 /*!< USART3 IER: RBRIE Position */ #define USART3_IER_RBRIE_Msk (0x01UL << USART3_IER_RBRIE_Pos) /*!< USART3 IER: RBRIE Mask */ #define USART3_IER_THREIE_Pos 1 /*!< USART3 IER: THREIE Position */ #define USART3_IER_THREIE_Msk (0x01UL << USART3_IER_THREIE_Pos) /*!< USART3 IER: THREIE Mask */ #define USART3_IER_RXIE_Pos 2 /*!< USART3 IER: RXIE Position */ #define USART3_IER_RXIE_Msk (0x01UL << USART3_IER_RXIE_Pos) /*!< USART3 IER: RXIE Mask */ #define USART3_IER_ABEOINTEN_Pos 8 /*!< USART3 IER: ABEOINTEN Position */ #define USART3_IER_ABEOINTEN_Msk (0x01UL << USART3_IER_ABEOINTEN_Pos) /*!< USART3 IER: ABEOINTEN Mask */ #define USART3_IER_ABTOINTEN_Pos 9 /*!< USART3 IER: ABTOINTEN Position */ #define USART3_IER_ABTOINTEN_Msk (0x01UL << USART3_IER_ABTOINTEN_Pos) /*!< USART3 IER: ABTOINTEN Mask */ /* --------------------------------- USART3_DLM --------------------------------- */ #define USART3_DLM_DLMSB_Pos 0 /*!< USART3 DLM: DLMSB Position */ #define USART3_DLM_DLMSB_Msk (0x000000ffUL << USART3_DLM_DLMSB_Pos) /*!< USART3 DLM: DLMSB Mask */ /* --------------------------------- USART3_FCR --------------------------------- */ #define USART3_FCR_FIFOEN_Pos 0 /*!< USART3 FCR: FIFOEN Position */ #define USART3_FCR_FIFOEN_Msk (0x01UL << USART3_FCR_FIFOEN_Pos) /*!< USART3 FCR: FIFOEN Mask */ #define USART3_FCR_RXFIFORES_Pos 1 /*!< USART3 FCR: RXFIFORES Position */ #define USART3_FCR_RXFIFORES_Msk (0x01UL << USART3_FCR_RXFIFORES_Pos) /*!< USART3 FCR: RXFIFORES Mask */ #define USART3_FCR_TXFIFORES_Pos 2 /*!< USART3 FCR: TXFIFORES Position */ #define USART3_FCR_TXFIFORES_Msk (0x01UL << USART3_FCR_TXFIFORES_Pos) /*!< USART3 FCR: TXFIFORES Mask */ #define USART3_FCR_DMAMODE_Pos 3 /*!< USART3 FCR: DMAMODE Position */ #define USART3_FCR_DMAMODE_Msk (0x01UL << USART3_FCR_DMAMODE_Pos) /*!< USART3 FCR: DMAMODE Mask */ #define USART3_FCR_RXTRIGLVL_Pos 6 /*!< USART3 FCR: RXTRIGLVL Position */ #define USART3_FCR_RXTRIGLVL_Msk (0x03UL << USART3_FCR_RXTRIGLVL_Pos) /*!< USART3 FCR: RXTRIGLVL Mask */ /* --------------------------------- USART3_IIR --------------------------------- */ #define USART3_IIR_INTSTATUS_Pos 0 /*!< USART3 IIR: INTSTATUS Position */ #define USART3_IIR_INTSTATUS_Msk (0x01UL << USART3_IIR_INTSTATUS_Pos) /*!< USART3 IIR: INTSTATUS Mask */ #define USART3_IIR_INTID_Pos 1 /*!< USART3 IIR: INTID Position */ #define USART3_IIR_INTID_Msk (0x07UL << USART3_IIR_INTID_Pos) /*!< USART3 IIR: INTID Mask */ #define USART3_IIR_FIFOENABLE_Pos 6 /*!< USART3 IIR: FIFOENABLE Position */ #define USART3_IIR_FIFOENABLE_Msk (0x03UL << USART3_IIR_FIFOENABLE_Pos) /*!< USART3 IIR: FIFOENABLE Mask */ #define USART3_IIR_ABEOINT_Pos 8 /*!< USART3 IIR: ABEOINT Position */ #define USART3_IIR_ABEOINT_Msk (0x01UL << USART3_IIR_ABEOINT_Pos) /*!< USART3 IIR: ABEOINT Mask */ #define USART3_IIR_ABTOINT_Pos 9 /*!< USART3 IIR: ABTOINT Position */ #define USART3_IIR_ABTOINT_Msk (0x01UL << USART3_IIR_ABTOINT_Pos) /*!< USART3 IIR: ABTOINT Mask */ /* --------------------------------- USART3_LCR --------------------------------- */ #define USART3_LCR_WLS_Pos 0 /*!< USART3 LCR: WLS Position */ #define USART3_LCR_WLS_Msk (0x03UL << USART3_LCR_WLS_Pos) /*!< USART3 LCR: WLS Mask */ #define USART3_LCR_SBS_Pos 2 /*!< USART3 LCR: SBS Position */ #define USART3_LCR_SBS_Msk (0x01UL << USART3_LCR_SBS_Pos) /*!< USART3 LCR: SBS Mask */ #define USART3_LCR_PE_Pos 3 /*!< USART3 LCR: PE Position */ #define USART3_LCR_PE_Msk (0x01UL << USART3_LCR_PE_Pos) /*!< USART3 LCR: PE Mask */ #define USART3_LCR_PS_Pos 4 /*!< USART3 LCR: PS Position */ #define USART3_LCR_PS_Msk (0x03UL << USART3_LCR_PS_Pos) /*!< USART3 LCR: PS Mask */ #define USART3_LCR_BC_Pos 6 /*!< USART3 LCR: BC Position */ #define USART3_LCR_BC_Msk (0x01UL << USART3_LCR_BC_Pos) /*!< USART3 LCR: BC Mask */ #define USART3_LCR_DLAB_Pos 7 /*!< USART3 LCR: DLAB Position */ #define USART3_LCR_DLAB_Msk (0x01UL << USART3_LCR_DLAB_Pos) /*!< USART3 LCR: DLAB Mask */ /* --------------------------------- USART3_LSR --------------------------------- */ #define USART3_LSR_RDR_Pos 0 /*!< USART3 LSR: RDR Position */ #define USART3_LSR_RDR_Msk (0x01UL << USART3_LSR_RDR_Pos) /*!< USART3 LSR: RDR Mask */ #define USART3_LSR_OE_Pos 1 /*!< USART3 LSR: OE Position */ #define USART3_LSR_OE_Msk (0x01UL << USART3_LSR_OE_Pos) /*!< USART3 LSR: OE Mask */ #define USART3_LSR_PE_Pos 2 /*!< USART3 LSR: PE Position */ #define USART3_LSR_PE_Msk (0x01UL << USART3_LSR_PE_Pos) /*!< USART3 LSR: PE Mask */ #define USART3_LSR_FE_Pos 3 /*!< USART3 LSR: FE Position */ #define USART3_LSR_FE_Msk (0x01UL << USART3_LSR_FE_Pos) /*!< USART3 LSR: FE Mask */ #define USART3_LSR_BI_Pos 4 /*!< USART3 LSR: BI Position */ #define USART3_LSR_BI_Msk (0x01UL << USART3_LSR_BI_Pos) /*!< USART3 LSR: BI Mask */ #define USART3_LSR_THRE_Pos 5 /*!< USART3 LSR: THRE Position */ #define USART3_LSR_THRE_Msk (0x01UL << USART3_LSR_THRE_Pos) /*!< USART3 LSR: THRE Mask */ #define USART3_LSR_TEMT_Pos 6 /*!< USART3 LSR: TEMT Position */ #define USART3_LSR_TEMT_Msk (0x01UL << USART3_LSR_TEMT_Pos) /*!< USART3 LSR: TEMT Mask */ #define USART3_LSR_RXFE_Pos 7 /*!< USART3 LSR: RXFE Position */ #define USART3_LSR_RXFE_Msk (0x01UL << USART3_LSR_RXFE_Pos) /*!< USART3 LSR: RXFE Mask */ #define USART3_LSR_TXERR_Pos 8 /*!< USART3 LSR: TXERR Position */ #define USART3_LSR_TXERR_Msk (0x01UL << USART3_LSR_TXERR_Pos) /*!< USART3 LSR: TXERR Mask */ /* --------------------------------- USART3_SCR --------------------------------- */ #define USART3_SCR_PAD_Pos 0 /*!< USART3 SCR: PAD Position */ #define USART3_SCR_PAD_Msk (0x000000ffUL << USART3_SCR_PAD_Pos) /*!< USART3 SCR: PAD Mask */ /* --------------------------------- USART3_ACR --------------------------------- */ #define USART3_ACR_START_Pos 0 /*!< USART3 ACR: START Position */ #define USART3_ACR_START_Msk (0x01UL << USART3_ACR_START_Pos) /*!< USART3 ACR: START Mask */ #define USART3_ACR_MODE_Pos 1 /*!< USART3 ACR: MODE Position */ #define USART3_ACR_MODE_Msk (0x01UL << USART3_ACR_MODE_Pos) /*!< USART3 ACR: MODE Mask */ #define USART3_ACR_AUTORESTART_Pos 2 /*!< USART3 ACR: AUTORESTART Position */ #define USART3_ACR_AUTORESTART_Msk (0x01UL << USART3_ACR_AUTORESTART_Pos) /*!< USART3 ACR: AUTORESTART Mask */ #define USART3_ACR_ABEOINTCLR_Pos 8 /*!< USART3 ACR: ABEOINTCLR Position */ #define USART3_ACR_ABEOINTCLR_Msk (0x01UL << USART3_ACR_ABEOINTCLR_Pos) /*!< USART3 ACR: ABEOINTCLR Mask */ #define USART3_ACR_ABTOINTCLR_Pos 9 /*!< USART3 ACR: ABTOINTCLR Position */ #define USART3_ACR_ABTOINTCLR_Msk (0x01UL << USART3_ACR_ABTOINTCLR_Pos) /*!< USART3 ACR: ABTOINTCLR Mask */ /* --------------------------------- USART3_ICR --------------------------------- */ #define USART3_ICR_IRDAEN_Pos 0 /*!< USART3 ICR: IRDAEN Position */ #define USART3_ICR_IRDAEN_Msk (0x01UL << USART3_ICR_IRDAEN_Pos) /*!< USART3 ICR: IRDAEN Mask */ #define USART3_ICR_IRDAINV_Pos 1 /*!< USART3 ICR: IRDAINV Position */ #define USART3_ICR_IRDAINV_Msk (0x01UL << USART3_ICR_IRDAINV_Pos) /*!< USART3 ICR: IRDAINV Mask */ #define USART3_ICR_FIXPULSEEN_Pos 2 /*!< USART3 ICR: FIXPULSEEN Position */ #define USART3_ICR_FIXPULSEEN_Msk (0x01UL << USART3_ICR_FIXPULSEEN_Pos) /*!< USART3 ICR: FIXPULSEEN Mask */ #define USART3_ICR_PULSEDIV_Pos 3 /*!< USART3 ICR: PULSEDIV Position */ #define USART3_ICR_PULSEDIV_Msk (0x07UL << USART3_ICR_PULSEDIV_Pos) /*!< USART3 ICR: PULSEDIV Mask */ /* --------------------------------- USART3_FDR --------------------------------- */ #define USART3_FDR_DIVADDVAL_Pos 0 /*!< USART3 FDR: DIVADDVAL Position */ #define USART3_FDR_DIVADDVAL_Msk (0x0fUL << USART3_FDR_DIVADDVAL_Pos) /*!< USART3 FDR: DIVADDVAL Mask */ #define USART3_FDR_MULVAL_Pos 4 /*!< USART3 FDR: MULVAL Position */ #define USART3_FDR_MULVAL_Msk (0x0fUL << USART3_FDR_MULVAL_Pos) /*!< USART3 FDR: MULVAL Mask */ /* --------------------------------- USART3_OSR --------------------------------- */ #define USART3_OSR_OSFRAC_Pos 1 /*!< USART3 OSR: OSFRAC Position */ #define USART3_OSR_OSFRAC_Msk (0x07UL << USART3_OSR_OSFRAC_Pos) /*!< USART3 OSR: OSFRAC Mask */ #define USART3_OSR_OSINT_Pos 4 /*!< USART3 OSR: OSINT Position */ #define USART3_OSR_OSINT_Msk (0x0fUL << USART3_OSR_OSINT_Pos) /*!< USART3 OSR: OSINT Mask */ #define USART3_OSR_FDINT_Pos 8 /*!< USART3 OSR: FDINT Position */ #define USART3_OSR_FDINT_Msk (0x7fUL << USART3_OSR_FDINT_Pos) /*!< USART3 OSR: FDINT Mask */ /* --------------------------------- USART3_HDEN -------------------------------- */ #define USART3_HDEN_HDEN_Pos 0 /*!< USART3 HDEN: HDEN Position */ #define USART3_HDEN_HDEN_Msk (0x01UL << USART3_HDEN_HDEN_Pos) /*!< USART3 HDEN: HDEN Mask */ /* ------------------------------- USART3_SCICTRL ------------------------------- */ #define USART3_SCICTRL_SCIEN_Pos 0 /*!< USART3 SCICTRL: SCIEN Position */ #define USART3_SCICTRL_SCIEN_Msk (0x01UL << USART3_SCICTRL_SCIEN_Pos) /*!< USART3 SCICTRL: SCIEN Mask */ #define USART3_SCICTRL_NACKDIS_Pos 1 /*!< USART3 SCICTRL: NACKDIS Position */ #define USART3_SCICTRL_NACKDIS_Msk (0x01UL << USART3_SCICTRL_NACKDIS_Pos) /*!< USART3 SCICTRL: NACKDIS Mask */ #define USART3_SCICTRL_PROTSEL_Pos 2 /*!< USART3 SCICTRL: PROTSEL Position */ #define USART3_SCICTRL_PROTSEL_Msk (0x01UL << USART3_SCICTRL_PROTSEL_Pos) /*!< USART3 SCICTRL: PROTSEL Mask */ #define USART3_SCICTRL_TXRETRY_Pos 5 /*!< USART3 SCICTRL: TXRETRY Position */ #define USART3_SCICTRL_TXRETRY_Msk (0x07UL << USART3_SCICTRL_TXRETRY_Pos) /*!< USART3 SCICTRL: TXRETRY Mask */ #define USART3_SCICTRL_GUARDTIME_Pos 8 /*!< USART3 SCICTRL: GUARDTIME Position */ #define USART3_SCICTRL_GUARDTIME_Msk (0x000000ffUL << USART3_SCICTRL_GUARDTIME_Pos) /*!< USART3 SCICTRL: GUARDTIME Mask */ /* ------------------------------ USART3_RS485CTRL ------------------------------ */ #define USART3_RS485CTRL_NMMEN_Pos 0 /*!< USART3 RS485CTRL: NMMEN Position */ #define USART3_RS485CTRL_NMMEN_Msk (0x01UL << USART3_RS485CTRL_NMMEN_Pos) /*!< USART3 RS485CTRL: NMMEN Mask */ #define USART3_RS485CTRL_RXDIS_Pos 1 /*!< USART3 RS485CTRL: RXDIS Position */ #define USART3_RS485CTRL_RXDIS_Msk (0x01UL << USART3_RS485CTRL_RXDIS_Pos) /*!< USART3 RS485CTRL: RXDIS Mask */ #define USART3_RS485CTRL_AADEN_Pos 2 /*!< USART3 RS485CTRL: AADEN Position */ #define USART3_RS485CTRL_AADEN_Msk (0x01UL << USART3_RS485CTRL_AADEN_Pos) /*!< USART3 RS485CTRL: AADEN Mask */ #define USART3_RS485CTRL_DCTRL_Pos 4 /*!< USART3 RS485CTRL: DCTRL Position */ #define USART3_RS485CTRL_DCTRL_Msk (0x01UL << USART3_RS485CTRL_DCTRL_Pos) /*!< USART3 RS485CTRL: DCTRL Mask */ #define USART3_RS485CTRL_OINV_Pos 5 /*!< USART3 RS485CTRL: OINV Position */ #define USART3_RS485CTRL_OINV_Msk (0x01UL << USART3_RS485CTRL_OINV_Pos) /*!< USART3 RS485CTRL: OINV Mask */ /* ---------------------------- USART3_RS485ADRMATCH ---------------------------- */ #define USART3_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< USART3 RS485ADRMATCH: ADRMATCH Position */ #define USART3_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << USART3_RS485ADRMATCH_ADRMATCH_Pos) /*!< USART3 RS485ADRMATCH: ADRMATCH Mask */ /* ------------------------------- USART3_RS485DLY ------------------------------ */ #define USART3_RS485DLY_DLY_Pos 0 /*!< USART3 RS485DLY: DLY Position */ #define USART3_RS485DLY_DLY_Msk (0x000000ffUL << USART3_RS485DLY_DLY_Pos) /*!< USART3 RS485DLY: DLY Mask */ /* ------------------------------- USART3_SYNCCTRL ------------------------------ */ #define USART3_SYNCCTRL_SYNC_Pos 0 /*!< USART3 SYNCCTRL: SYNC Position */ #define USART3_SYNCCTRL_SYNC_Msk (0x01UL << USART3_SYNCCTRL_SYNC_Pos) /*!< USART3 SYNCCTRL: SYNC Mask */ #define USART3_SYNCCTRL_CSRC_Pos 1 /*!< USART3 SYNCCTRL: CSRC Position */ #define USART3_SYNCCTRL_CSRC_Msk (0x01UL << USART3_SYNCCTRL_CSRC_Pos) /*!< USART3 SYNCCTRL: CSRC Mask */ #define USART3_SYNCCTRL_FES_Pos 2 /*!< USART3 SYNCCTRL: FES Position */ #define USART3_SYNCCTRL_FES_Msk (0x01UL << USART3_SYNCCTRL_FES_Pos) /*!< USART3 SYNCCTRL: FES Mask */ #define USART3_SYNCCTRL_TSBYPASS_Pos 3 /*!< USART3 SYNCCTRL: TSBYPASS Position */ #define USART3_SYNCCTRL_TSBYPASS_Msk (0x01UL << USART3_SYNCCTRL_TSBYPASS_Pos) /*!< USART3 SYNCCTRL: TSBYPASS Mask */ #define USART3_SYNCCTRL_CSCEN_Pos 4 /*!< USART3 SYNCCTRL: CSCEN Position */ #define USART3_SYNCCTRL_CSCEN_Msk (0x01UL << USART3_SYNCCTRL_CSCEN_Pos) /*!< USART3 SYNCCTRL: CSCEN Mask */ #define USART3_SYNCCTRL_SSSDIS_Pos 5 /*!< USART3 SYNCCTRL: SSSDIS Position */ #define USART3_SYNCCTRL_SSSDIS_Msk (0x01UL << USART3_SYNCCTRL_SSSDIS_Pos) /*!< USART3 SYNCCTRL: SSSDIS Mask */ #define USART3_SYNCCTRL_CCCLR_Pos 6 /*!< USART3 SYNCCTRL: CCCLR Position */ #define USART3_SYNCCTRL_CCCLR_Msk (0x01UL << USART3_SYNCCTRL_CCCLR_Pos) /*!< USART3 SYNCCTRL: CCCLR Mask */ /* --------------------------------- USART3_TER --------------------------------- */ #define USART3_TER_TXEN_Pos 0 /*!< USART3 TER: TXEN Position */ #define USART3_TER_TXEN_Msk (0x01UL << USART3_TER_TXEN_Pos) /*!< USART3 TER: TXEN Mask */ /* ================================================================================ */ /* ================ struct 'UART1' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- UART1_RBR --------------------------------- */ #define UART1_RBR_RBR_Pos 0 /*!< UART1 RBR: RBR Position */ #define UART1_RBR_RBR_Msk (0x000000ffUL << UART1_RBR_RBR_Pos) /*!< UART1 RBR: RBR Mask */ /* ---------------------------------- UART1_THR --------------------------------- */ #define UART1_THR_THR_Pos 0 /*!< UART1 THR: THR Position */ #define UART1_THR_THR_Msk (0x000000ffUL << UART1_THR_THR_Pos) /*!< UART1 THR: THR Mask */ /* ---------------------------------- UART1_DLL --------------------------------- */ #define UART1_DLL_DLLSB_Pos 0 /*!< UART1 DLL: DLLSB Position */ #define UART1_DLL_DLLSB_Msk (0x000000ffUL << UART1_DLL_DLLSB_Pos) /*!< UART1 DLL: DLLSB Mask */ /* ---------------------------------- UART1_DLM --------------------------------- */ #define UART1_DLM_DLMSB_Pos 0 /*!< UART1 DLM: DLMSB Position */ #define UART1_DLM_DLMSB_Msk (0x000000ffUL << UART1_DLM_DLMSB_Pos) /*!< UART1 DLM: DLMSB Mask */ /* ---------------------------------- UART1_IER --------------------------------- */ #define UART1_IER_RBRIE_Pos 0 /*!< UART1 IER: RBRIE Position */ #define UART1_IER_RBRIE_Msk (0x01UL << UART1_IER_RBRIE_Pos) /*!< UART1 IER: RBRIE Mask */ #define UART1_IER_THREIE_Pos 1 /*!< UART1 IER: THREIE Position */ #define UART1_IER_THREIE_Msk (0x01UL << UART1_IER_THREIE_Pos) /*!< UART1 IER: THREIE Mask */ #define UART1_IER_RXIE_Pos 2 /*!< UART1 IER: RXIE Position */ #define UART1_IER_RXIE_Msk (0x01UL << UART1_IER_RXIE_Pos) /*!< UART1 IER: RXIE Mask */ #define UART1_IER_MSIE_Pos 3 /*!< UART1 IER: MSIE Position */ #define UART1_IER_MSIE_Msk (0x01UL << UART1_IER_MSIE_Pos) /*!< UART1 IER: MSIE Mask */ #define UART1_IER_CTSIE_Pos 7 /*!< UART1 IER: CTSIE Position */ #define UART1_IER_CTSIE_Msk (0x01UL << UART1_IER_CTSIE_Pos) /*!< UART1 IER: CTSIE Mask */ #define UART1_IER_ABEOIE_Pos 8 /*!< UART1 IER: ABEOIE Position */ #define UART1_IER_ABEOIE_Msk (0x01UL << UART1_IER_ABEOIE_Pos) /*!< UART1 IER: ABEOIE Mask */ #define UART1_IER_ABTOIE_Pos 9 /*!< UART1 IER: ABTOIE Position */ #define UART1_IER_ABTOIE_Msk (0x01UL << UART1_IER_ABTOIE_Pos) /*!< UART1 IER: ABTOIE Mask */ /* ---------------------------------- UART1_IIR --------------------------------- */ #define UART1_IIR_INTSTATUS_Pos 0 /*!< UART1 IIR: INTSTATUS Position */ #define UART1_IIR_INTSTATUS_Msk (0x01UL << UART1_IIR_INTSTATUS_Pos) /*!< UART1 IIR: INTSTATUS Mask */ #define UART1_IIR_INTID_Pos 1 /*!< UART1 IIR: INTID Position */ #define UART1_IIR_INTID_Msk (0x07UL << UART1_IIR_INTID_Pos) /*!< UART1 IIR: INTID Mask */ #define UART1_IIR_FIFOENABLE_Pos 6 /*!< UART1 IIR: FIFOENABLE Position */ #define UART1_IIR_FIFOENABLE_Msk (0x03UL << UART1_IIR_FIFOENABLE_Pos) /*!< UART1 IIR: FIFOENABLE Mask */ #define UART1_IIR_ABEOINT_Pos 8 /*!< UART1 IIR: ABEOINT Position */ #define UART1_IIR_ABEOINT_Msk (0x01UL << UART1_IIR_ABEOINT_Pos) /*!< UART1 IIR: ABEOINT Mask */ #define UART1_IIR_ABTOINT_Pos 9 /*!< UART1 IIR: ABTOINT Position */ #define UART1_IIR_ABTOINT_Msk (0x01UL << UART1_IIR_ABTOINT_Pos) /*!< UART1 IIR: ABTOINT Mask */ /* ---------------------------------- UART1_FCR --------------------------------- */ #define UART1_FCR_FIFOEN_Pos 0 /*!< UART1 FCR: FIFOEN Position */ #define UART1_FCR_FIFOEN_Msk (0x01UL << UART1_FCR_FIFOEN_Pos) /*!< UART1 FCR: FIFOEN Mask */ #define UART1_FCR_RXFIFORES_Pos 1 /*!< UART1 FCR: RXFIFORES Position */ #define UART1_FCR_RXFIFORES_Msk (0x01UL << UART1_FCR_RXFIFORES_Pos) /*!< UART1 FCR: RXFIFORES Mask */ #define UART1_FCR_TXFIFORES_Pos 2 /*!< UART1 FCR: TXFIFORES Position */ #define UART1_FCR_TXFIFORES_Msk (0x01UL << UART1_FCR_TXFIFORES_Pos) /*!< UART1 FCR: TXFIFORES Mask */ #define UART1_FCR_DMAMODE_Pos 3 /*!< UART1 FCR: DMAMODE Position */ #define UART1_FCR_DMAMODE_Msk (0x01UL << UART1_FCR_DMAMODE_Pos) /*!< UART1 FCR: DMAMODE Mask */ #define UART1_FCR_RXTRIGLVL_Pos 6 /*!< UART1 FCR: RXTRIGLVL Position */ #define UART1_FCR_RXTRIGLVL_Msk (0x03UL << UART1_FCR_RXTRIGLVL_Pos) /*!< UART1 FCR: RXTRIGLVL Mask */ /* ---------------------------------- UART1_LCR --------------------------------- */ #define UART1_LCR_WLS_Pos 0 /*!< UART1 LCR: WLS Position */ #define UART1_LCR_WLS_Msk (0x03UL << UART1_LCR_WLS_Pos) /*!< UART1 LCR: WLS Mask */ #define UART1_LCR_SBS_Pos 2 /*!< UART1 LCR: SBS Position */ #define UART1_LCR_SBS_Msk (0x01UL << UART1_LCR_SBS_Pos) /*!< UART1 LCR: SBS Mask */ #define UART1_LCR_PE_Pos 3 /*!< UART1 LCR: PE Position */ #define UART1_LCR_PE_Msk (0x01UL << UART1_LCR_PE_Pos) /*!< UART1 LCR: PE Mask */ #define UART1_LCR_PS_Pos 4 /*!< UART1 LCR: PS Position */ #define UART1_LCR_PS_Msk (0x03UL << UART1_LCR_PS_Pos) /*!< UART1 LCR: PS Mask */ #define UART1_LCR_BC_Pos 6 /*!< UART1 LCR: BC Position */ #define UART1_LCR_BC_Msk (0x01UL << UART1_LCR_BC_Pos) /*!< UART1 LCR: BC Mask */ #define UART1_LCR_DLAB_Pos 7 /*!< UART1 LCR: DLAB Position */ #define UART1_LCR_DLAB_Msk (0x01UL << UART1_LCR_DLAB_Pos) /*!< UART1 LCR: DLAB Mask */ /* ---------------------------------- UART1_MCR --------------------------------- */ #define UART1_MCR_DTRCTRL_Pos 0 /*!< UART1 MCR: DTRCTRL Position */ #define UART1_MCR_DTRCTRL_Msk (0x01UL << UART1_MCR_DTRCTRL_Pos) /*!< UART1 MCR: DTRCTRL Mask */ #define UART1_MCR_RTSCTRL_Pos 1 /*!< UART1 MCR: RTSCTRL Position */ #define UART1_MCR_RTSCTRL_Msk (0x01UL << UART1_MCR_RTSCTRL_Pos) /*!< UART1 MCR: RTSCTRL Mask */ #define UART1_MCR_LMS_Pos 4 /*!< UART1 MCR: LMS Position */ #define UART1_MCR_LMS_Msk (0x01UL << UART1_MCR_LMS_Pos) /*!< UART1 MCR: LMS Mask */ #define UART1_MCR_RTSEN_Pos 6 /*!< UART1 MCR: RTSEN Position */ #define UART1_MCR_RTSEN_Msk (0x01UL << UART1_MCR_RTSEN_Pos) /*!< UART1 MCR: RTSEN Mask */ #define UART1_MCR_CTSEN_Pos 7 /*!< UART1 MCR: CTSEN Position */ #define UART1_MCR_CTSEN_Msk (0x01UL << UART1_MCR_CTSEN_Pos) /*!< UART1 MCR: CTSEN Mask */ /* ---------------------------------- UART1_LSR --------------------------------- */ #define UART1_LSR_RDR_Pos 0 /*!< UART1 LSR: RDR Position */ #define UART1_LSR_RDR_Msk (0x01UL << UART1_LSR_RDR_Pos) /*!< UART1 LSR: RDR Mask */ #define UART1_LSR_OE_Pos 1 /*!< UART1 LSR: OE Position */ #define UART1_LSR_OE_Msk (0x01UL << UART1_LSR_OE_Pos) /*!< UART1 LSR: OE Mask */ #define UART1_LSR_PE_Pos 2 /*!< UART1 LSR: PE Position */ #define UART1_LSR_PE_Msk (0x01UL << UART1_LSR_PE_Pos) /*!< UART1 LSR: PE Mask */ #define UART1_LSR_FE_Pos 3 /*!< UART1 LSR: FE Position */ #define UART1_LSR_FE_Msk (0x01UL << UART1_LSR_FE_Pos) /*!< UART1 LSR: FE Mask */ #define UART1_LSR_BI_Pos 4 /*!< UART1 LSR: BI Position */ #define UART1_LSR_BI_Msk (0x01UL << UART1_LSR_BI_Pos) /*!< UART1 LSR: BI Mask */ #define UART1_LSR_THRE_Pos 5 /*!< UART1 LSR: THRE Position */ #define UART1_LSR_THRE_Msk (0x01UL << UART1_LSR_THRE_Pos) /*!< UART1 LSR: THRE Mask */ #define UART1_LSR_TEMT_Pos 6 /*!< UART1 LSR: TEMT Position */ #define UART1_LSR_TEMT_Msk (0x01UL << UART1_LSR_TEMT_Pos) /*!< UART1 LSR: TEMT Mask */ #define UART1_LSR_RXFE_Pos 7 /*!< UART1 LSR: RXFE Position */ #define UART1_LSR_RXFE_Msk (0x01UL << UART1_LSR_RXFE_Pos) /*!< UART1 LSR: RXFE Mask */ /* ---------------------------------- UART1_MSR --------------------------------- */ #define UART1_MSR_DCTS_Pos 0 /*!< UART1 MSR: DCTS Position */ #define UART1_MSR_DCTS_Msk (0x01UL << UART1_MSR_DCTS_Pos) /*!< UART1 MSR: DCTS Mask */ #define UART1_MSR_DDSR_Pos 1 /*!< UART1 MSR: DDSR Position */ #define UART1_MSR_DDSR_Msk (0x01UL << UART1_MSR_DDSR_Pos) /*!< UART1 MSR: DDSR Mask */ #define UART1_MSR_TERI_Pos 2 /*!< UART1 MSR: TERI Position */ #define UART1_MSR_TERI_Msk (0x01UL << UART1_MSR_TERI_Pos) /*!< UART1 MSR: TERI Mask */ #define UART1_MSR_DDCD_Pos 3 /*!< UART1 MSR: DDCD Position */ #define UART1_MSR_DDCD_Msk (0x01UL << UART1_MSR_DDCD_Pos) /*!< UART1 MSR: DDCD Mask */ #define UART1_MSR_CTS_Pos 4 /*!< UART1 MSR: CTS Position */ #define UART1_MSR_CTS_Msk (0x01UL << UART1_MSR_CTS_Pos) /*!< UART1 MSR: CTS Mask */ #define UART1_MSR_DSR_Pos 5 /*!< UART1 MSR: DSR Position */ #define UART1_MSR_DSR_Msk (0x01UL << UART1_MSR_DSR_Pos) /*!< UART1 MSR: DSR Mask */ #define UART1_MSR_RI_Pos 6 /*!< UART1 MSR: RI Position */ #define UART1_MSR_RI_Msk (0x01UL << UART1_MSR_RI_Pos) /*!< UART1 MSR: RI Mask */ #define UART1_MSR_DCD_Pos 7 /*!< UART1 MSR: DCD Position */ #define UART1_MSR_DCD_Msk (0x01UL << UART1_MSR_DCD_Pos) /*!< UART1 MSR: DCD Mask */ /* ---------------------------------- UART1_SCR --------------------------------- */ #define UART1_SCR_Pad_Pos 0 /*!< UART1 SCR: Pad Position */ #define UART1_SCR_Pad_Msk (0x000000ffUL << UART1_SCR_Pad_Pos) /*!< UART1 SCR: Pad Mask */ /* ---------------------------------- UART1_ACR --------------------------------- */ #define UART1_ACR_START_Pos 0 /*!< UART1 ACR: START Position */ #define UART1_ACR_START_Msk (0x01UL << UART1_ACR_START_Pos) /*!< UART1 ACR: START Mask */ #define UART1_ACR_MODE_Pos 1 /*!< UART1 ACR: MODE Position */ #define UART1_ACR_MODE_Msk (0x01UL << UART1_ACR_MODE_Pos) /*!< UART1 ACR: MODE Mask */ #define UART1_ACR_AUTORESTART_Pos 2 /*!< UART1 ACR: AUTORESTART Position */ #define UART1_ACR_AUTORESTART_Msk (0x01UL << UART1_ACR_AUTORESTART_Pos) /*!< UART1 ACR: AUTORESTART Mask */ #define UART1_ACR_ABEOINTCLR_Pos 8 /*!< UART1 ACR: ABEOINTCLR Position */ #define UART1_ACR_ABEOINTCLR_Msk (0x01UL << UART1_ACR_ABEOINTCLR_Pos) /*!< UART1 ACR: ABEOINTCLR Mask */ #define UART1_ACR_ABTOINTCLR_Pos 9 /*!< UART1 ACR: ABTOINTCLR Position */ #define UART1_ACR_ABTOINTCLR_Msk (0x01UL << UART1_ACR_ABTOINTCLR_Pos) /*!< UART1 ACR: ABTOINTCLR Mask */ /* ---------------------------------- UART1_FDR --------------------------------- */ #define UART1_FDR_DIVADDVAL_Pos 0 /*!< UART1 FDR: DIVADDVAL Position */ #define UART1_FDR_DIVADDVAL_Msk (0x0fUL << UART1_FDR_DIVADDVAL_Pos) /*!< UART1 FDR: DIVADDVAL Mask */ #define UART1_FDR_MULVAL_Pos 4 /*!< UART1 FDR: MULVAL Position */ #define UART1_FDR_MULVAL_Msk (0x0fUL << UART1_FDR_MULVAL_Pos) /*!< UART1 FDR: MULVAL Mask */ /* ------------------------------- UART1_RS485CTRL ------------------------------ */ #define UART1_RS485CTRL_NMMEN_Pos 0 /*!< UART1 RS485CTRL: NMMEN Position */ #define UART1_RS485CTRL_NMMEN_Msk (0x01UL << UART1_RS485CTRL_NMMEN_Pos) /*!< UART1 RS485CTRL: NMMEN Mask */ #define UART1_RS485CTRL_RXDIS_Pos 1 /*!< UART1 RS485CTRL: RXDIS Position */ #define UART1_RS485CTRL_RXDIS_Msk (0x01UL << UART1_RS485CTRL_RXDIS_Pos) /*!< UART1 RS485CTRL: RXDIS Mask */ #define UART1_RS485CTRL_AADEN_Pos 2 /*!< UART1 RS485CTRL: AADEN Position */ #define UART1_RS485CTRL_AADEN_Msk (0x01UL << UART1_RS485CTRL_AADEN_Pos) /*!< UART1 RS485CTRL: AADEN Mask */ #define UART1_RS485CTRL_SEL_Pos 3 /*!< UART1 RS485CTRL: SEL Position */ #define UART1_RS485CTRL_SEL_Msk (0x01UL << UART1_RS485CTRL_SEL_Pos) /*!< UART1 RS485CTRL: SEL Mask */ #define UART1_RS485CTRL_DCTRL_Pos 4 /*!< UART1 RS485CTRL: DCTRL Position */ #define UART1_RS485CTRL_DCTRL_Msk (0x01UL << UART1_RS485CTRL_DCTRL_Pos) /*!< UART1 RS485CTRL: DCTRL Mask */ #define UART1_RS485CTRL_OINV_Pos 5 /*!< UART1 RS485CTRL: OINV Position */ #define UART1_RS485CTRL_OINV_Msk (0x01UL << UART1_RS485CTRL_OINV_Pos) /*!< UART1 RS485CTRL: OINV Mask */ /* ----------------------------- UART1_RS485ADRMATCH ---------------------------- */ #define UART1_RS485ADRMATCH_ADRMATCH_Pos 0 /*!< UART1 RS485ADRMATCH: ADRMATCH Position */ #define UART1_RS485ADRMATCH_ADRMATCH_Msk (0x000000ffUL << UART1_RS485ADRMATCH_ADRMATCH_Pos) /*!< UART1 RS485ADRMATCH: ADRMATCH Mask */ /* ------------------------------- UART1_RS485DLY ------------------------------- */ #define UART1_RS485DLY_DLY_Pos 0 /*!< UART1 RS485DLY: DLY Position */ #define UART1_RS485DLY_DLY_Msk (0x000000ffUL << UART1_RS485DLY_DLY_Pos) /*!< UART1 RS485DLY: DLY Mask */ /* ---------------------------------- UART1_TER --------------------------------- */ #define UART1_TER_TXEN_Pos 0 /*!< UART1 TER: TXEN Position */ #define UART1_TER_TXEN_Msk (0x01UL << UART1_TER_TXEN_Pos) /*!< UART1 TER: TXEN Mask */ /* ================================================================================ */ /* ================ Group 'SSPn' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- SSPn_CR0 ---------------------------------- */ #define SSPn_CR0_DSS_Pos 0 /*!< SSPn CR0: DSS Position */ #define SSPn_CR0_DSS_Msk (0x0fUL << SSPn_CR0_DSS_Pos) /*!< SSPn CR0: DSS Mask */ #define SSPn_CR0_FRF_Pos 4 /*!< SSPn CR0: FRF Position */ #define SSPn_CR0_FRF_Msk (0x03UL << SSPn_CR0_FRF_Pos) /*!< SSPn CR0: FRF Mask */ #define SSPn_CR0_CPOL_Pos 6 /*!< SSPn CR0: CPOL Position */ #define SSPn_CR0_CPOL_Msk (0x01UL << SSPn_CR0_CPOL_Pos) /*!< SSPn CR0: CPOL Mask */ #define SSPn_CR0_CPHA_Pos 7 /*!< SSPn CR0: CPHA Position */ #define SSPn_CR0_CPHA_Msk (0x01UL << SSPn_CR0_CPHA_Pos) /*!< SSPn CR0: CPHA Mask */ #define SSPn_CR0_SCR_Pos 8 /*!< SSPn CR0: SCR Position */ #define SSPn_CR0_SCR_Msk (0x000000ffUL << SSPn_CR0_SCR_Pos) /*!< SSPn CR0: SCR Mask */ /* ---------------------------------- SSPn_CR1 ---------------------------------- */ #define SSPn_CR1_LBM_Pos 0 /*!< SSPn CR1: LBM Position */ #define SSPn_CR1_LBM_Msk (0x01UL << SSPn_CR1_LBM_Pos) /*!< SSPn CR1: LBM Mask */ #define SSPn_CR1_SSE_Pos 1 /*!< SSPn CR1: SSE Position */ #define SSPn_CR1_SSE_Msk (0x01UL << SSPn_CR1_SSE_Pos) /*!< SSPn CR1: SSE Mask */ #define SSPn_CR1_MS_Pos 2 /*!< SSPn CR1: MS Position */ #define SSPn_CR1_MS_Msk (0x01UL << SSPn_CR1_MS_Pos) /*!< SSPn CR1: MS Mask */ #define SSPn_CR1_SOD_Pos 3 /*!< SSPn CR1: SOD Position */ #define SSPn_CR1_SOD_Msk (0x01UL << SSPn_CR1_SOD_Pos) /*!< SSPn CR1: SOD Mask */ /* ----------------------------------- SSPn_DR ---------------------------------- */ #define SSPn_DR_DATA_Pos 0 /*!< SSPn DR: DATA Position */ #define SSPn_DR_DATA_Msk (0x0000ffffUL << SSPn_DR_DATA_Pos) /*!< SSPn DR: DATA Mask */ /* ----------------------------------- SSPn_SR ---------------------------------- */ #define SSPn_SR_TFE_Pos 0 /*!< SSPn SR: TFE Position */ #define SSPn_SR_TFE_Msk (0x01UL << SSPn_SR_TFE_Pos) /*!< SSPn SR: TFE Mask */ #define SSPn_SR_TNF_Pos 1 /*!< SSPn SR: TNF Position */ #define SSPn_SR_TNF_Msk (0x01UL << SSPn_SR_TNF_Pos) /*!< SSPn SR: TNF Mask */ #define SSPn_SR_RNE_Pos 2 /*!< SSPn SR: RNE Position */ #define SSPn_SR_RNE_Msk (0x01UL << SSPn_SR_RNE_Pos) /*!< SSPn SR: RNE Mask */ #define SSPn_SR_RFF_Pos 3 /*!< SSPn SR: RFF Position */ #define SSPn_SR_RFF_Msk (0x01UL << SSPn_SR_RFF_Pos) /*!< SSPn SR: RFF Mask */ #define SSPn_SR_BSY_Pos 4 /*!< SSPn SR: BSY Position */ #define SSPn_SR_BSY_Msk (0x01UL << SSPn_SR_BSY_Pos) /*!< SSPn SR: BSY Mask */ /* ---------------------------------- SSPn_CPSR --------------------------------- */ #define SSPn_CPSR_CPSDVSR_Pos 0 /*!< SSPn CPSR: CPSDVSR Position */ #define SSPn_CPSR_CPSDVSR_Msk (0x000000ffUL << SSPn_CPSR_CPSDVSR_Pos) /*!< SSPn CPSR: CPSDVSR Mask */ /* ---------------------------------- SSPn_IMSC --------------------------------- */ #define SSPn_IMSC_RORIM_Pos 0 /*!< SSPn IMSC: RORIM Position */ #define SSPn_IMSC_RORIM_Msk (0x01UL << SSPn_IMSC_RORIM_Pos) /*!< SSPn IMSC: RORIM Mask */ #define SSPn_IMSC_RTIM_Pos 1 /*!< SSPn IMSC: RTIM Position */ #define SSPn_IMSC_RTIM_Msk (0x01UL << SSPn_IMSC_RTIM_Pos) /*!< SSPn IMSC: RTIM Mask */ #define SSPn_IMSC_RXIM_Pos 2 /*!< SSPn IMSC: RXIM Position */ #define SSPn_IMSC_RXIM_Msk (0x01UL << SSPn_IMSC_RXIM_Pos) /*!< SSPn IMSC: RXIM Mask */ #define SSPn_IMSC_TXIM_Pos 3 /*!< SSPn IMSC: TXIM Position */ #define SSPn_IMSC_TXIM_Msk (0x01UL << SSPn_IMSC_TXIM_Pos) /*!< SSPn IMSC: TXIM Mask */ /* ---------------------------------- SSPn_RIS ---------------------------------- */ #define SSPn_RIS_RORRIS_Pos 0 /*!< SSPn RIS: RORRIS Position */ #define SSPn_RIS_RORRIS_Msk (0x01UL << SSPn_RIS_RORRIS_Pos) /*!< SSPn RIS: RORRIS Mask */ #define SSPn_RIS_RTRIS_Pos 1 /*!< SSPn RIS: RTRIS Position */ #define SSPn_RIS_RTRIS_Msk (0x01UL << SSPn_RIS_RTRIS_Pos) /*!< SSPn RIS: RTRIS Mask */ #define SSPn_RIS_RXRIS_Pos 2 /*!< SSPn RIS: RXRIS Position */ #define SSPn_RIS_RXRIS_Msk (0x01UL << SSPn_RIS_RXRIS_Pos) /*!< SSPn RIS: RXRIS Mask */ #define SSPn_RIS_TXRIS_Pos 3 /*!< SSPn RIS: TXRIS Position */ #define SSPn_RIS_TXRIS_Msk (0x01UL << SSPn_RIS_TXRIS_Pos) /*!< SSPn RIS: TXRIS Mask */ /* ---------------------------------- SSPn_MIS ---------------------------------- */ #define SSPn_MIS_RORMIS_Pos 0 /*!< SSPn MIS: RORMIS Position */ #define SSPn_MIS_RORMIS_Msk (0x01UL << SSPn_MIS_RORMIS_Pos) /*!< SSPn MIS: RORMIS Mask */ #define SSPn_MIS_RTMIS_Pos 1 /*!< SSPn MIS: RTMIS Position */ #define SSPn_MIS_RTMIS_Msk (0x01UL << SSPn_MIS_RTMIS_Pos) /*!< SSPn MIS: RTMIS Mask */ #define SSPn_MIS_RXMIS_Pos 2 /*!< SSPn MIS: RXMIS Position */ #define SSPn_MIS_RXMIS_Msk (0x01UL << SSPn_MIS_RXMIS_Pos) /*!< SSPn MIS: RXMIS Mask */ #define SSPn_MIS_TXMIS_Pos 3 /*!< SSPn MIS: TXMIS Position */ #define SSPn_MIS_TXMIS_Msk (0x01UL << SSPn_MIS_TXMIS_Pos) /*!< SSPn MIS: TXMIS Mask */ /* ---------------------------------- SSPn_ICR ---------------------------------- */ #define SSPn_ICR_RORIC_Pos 0 /*!< SSPn ICR: RORIC Position */ #define SSPn_ICR_RORIC_Msk (0x01UL << SSPn_ICR_RORIC_Pos) /*!< SSPn ICR: RORIC Mask */ #define SSPn_ICR_RTIC_Pos 1 /*!< SSPn ICR: RTIC Position */ #define SSPn_ICR_RTIC_Msk (0x01UL << SSPn_ICR_RTIC_Pos) /*!< SSPn ICR: RTIC Mask */ /* --------------------------------- SSPn_DMACR --------------------------------- */ #define SSPn_DMACR_RXDMAE_Pos 0 /*!< SSPn DMACR: RXDMAE Position */ #define SSPn_DMACR_RXDMAE_Msk (0x01UL << SSPn_DMACR_RXDMAE_Pos) /*!< SSPn DMACR: RXDMAE Mask */ #define SSPn_DMACR_TXDMAE_Pos 1 /*!< SSPn DMACR: TXDMAE Position */ #define SSPn_DMACR_TXDMAE_Msk (0x01UL << SSPn_DMACR_TXDMAE_Pos) /*!< SSPn DMACR: TXDMAE Mask */ /* ================================================================================ */ /* ================ struct 'SSP0' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- SSP0_CR0 ---------------------------------- */ #define SSP0_CR0_DSS_Pos 0 /*!< SSP0 CR0: DSS Position */ #define SSP0_CR0_DSS_Msk (0x0fUL << SSP0_CR0_DSS_Pos) /*!< SSP0 CR0: DSS Mask */ #define SSP0_CR0_FRF_Pos 4 /*!< SSP0 CR0: FRF Position */ #define SSP0_CR0_FRF_Msk (0x03UL << SSP0_CR0_FRF_Pos) /*!< SSP0 CR0: FRF Mask */ #define SSP0_CR0_CPOL_Pos 6 /*!< SSP0 CR0: CPOL Position */ #define SSP0_CR0_CPOL_Msk (0x01UL << SSP0_CR0_CPOL_Pos) /*!< SSP0 CR0: CPOL Mask */ #define SSP0_CR0_CPHA_Pos 7 /*!< SSP0 CR0: CPHA Position */ #define SSP0_CR0_CPHA_Msk (0x01UL << SSP0_CR0_CPHA_Pos) /*!< SSP0 CR0: CPHA Mask */ #define SSP0_CR0_SCR_Pos 8 /*!< SSP0 CR0: SCR Position */ #define SSP0_CR0_SCR_Msk (0x000000ffUL << SSP0_CR0_SCR_Pos) /*!< SSP0 CR0: SCR Mask */ /* ---------------------------------- SSP0_CR1 ---------------------------------- */ #define SSP0_CR1_LBM_Pos 0 /*!< SSP0 CR1: LBM Position */ #define SSP0_CR1_LBM_Msk (0x01UL << SSP0_CR1_LBM_Pos) /*!< SSP0 CR1: LBM Mask */ #define SSP0_CR1_SSE_Pos 1 /*!< SSP0 CR1: SSE Position */ #define SSP0_CR1_SSE_Msk (0x01UL << SSP0_CR1_SSE_Pos) /*!< SSP0 CR1: SSE Mask */ #define SSP0_CR1_MS_Pos 2 /*!< SSP0 CR1: MS Position */ #define SSP0_CR1_MS_Msk (0x01UL << SSP0_CR1_MS_Pos) /*!< SSP0 CR1: MS Mask */ #define SSP0_CR1_SOD_Pos 3 /*!< SSP0 CR1: SOD Position */ #define SSP0_CR1_SOD_Msk (0x01UL << SSP0_CR1_SOD_Pos) /*!< SSP0 CR1: SOD Mask */ /* ----------------------------------- SSP0_DR ---------------------------------- */ #define SSP0_DR_DATA_Pos 0 /*!< SSP0 DR: DATA Position */ #define SSP0_DR_DATA_Msk (0x0000ffffUL << SSP0_DR_DATA_Pos) /*!< SSP0 DR: DATA Mask */ /* ----------------------------------- SSP0_SR ---------------------------------- */ #define SSP0_SR_TFE_Pos 0 /*!< SSP0 SR: TFE Position */ #define SSP0_SR_TFE_Msk (0x01UL << SSP0_SR_TFE_Pos) /*!< SSP0 SR: TFE Mask */ #define SSP0_SR_TNF_Pos 1 /*!< SSP0 SR: TNF Position */ #define SSP0_SR_TNF_Msk (0x01UL << SSP0_SR_TNF_Pos) /*!< SSP0 SR: TNF Mask */ #define SSP0_SR_RNE_Pos 2 /*!< SSP0 SR: RNE Position */ #define SSP0_SR_RNE_Msk (0x01UL << SSP0_SR_RNE_Pos) /*!< SSP0 SR: RNE Mask */ #define SSP0_SR_RFF_Pos 3 /*!< SSP0 SR: RFF Position */ #define SSP0_SR_RFF_Msk (0x01UL << SSP0_SR_RFF_Pos) /*!< SSP0 SR: RFF Mask */ #define SSP0_SR_BSY_Pos 4 /*!< SSP0 SR: BSY Position */ #define SSP0_SR_BSY_Msk (0x01UL << SSP0_SR_BSY_Pos) /*!< SSP0 SR: BSY Mask */ /* ---------------------------------- SSP0_CPSR --------------------------------- */ #define SSP0_CPSR_CPSDVSR_Pos 0 /*!< SSP0 CPSR: CPSDVSR Position */ #define SSP0_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP0_CPSR_CPSDVSR_Pos) /*!< SSP0 CPSR: CPSDVSR Mask */ /* ---------------------------------- SSP0_IMSC --------------------------------- */ #define SSP0_IMSC_RORIM_Pos 0 /*!< SSP0 IMSC: RORIM Position */ #define SSP0_IMSC_RORIM_Msk (0x01UL << SSP0_IMSC_RORIM_Pos) /*!< SSP0 IMSC: RORIM Mask */ #define SSP0_IMSC_RTIM_Pos 1 /*!< SSP0 IMSC: RTIM Position */ #define SSP0_IMSC_RTIM_Msk (0x01UL << SSP0_IMSC_RTIM_Pos) /*!< SSP0 IMSC: RTIM Mask */ #define SSP0_IMSC_RXIM_Pos 2 /*!< SSP0 IMSC: RXIM Position */ #define SSP0_IMSC_RXIM_Msk (0x01UL << SSP0_IMSC_RXIM_Pos) /*!< SSP0 IMSC: RXIM Mask */ #define SSP0_IMSC_TXIM_Pos 3 /*!< SSP0 IMSC: TXIM Position */ #define SSP0_IMSC_TXIM_Msk (0x01UL << SSP0_IMSC_TXIM_Pos) /*!< SSP0 IMSC: TXIM Mask */ /* ---------------------------------- SSP0_RIS ---------------------------------- */ #define SSP0_RIS_RORRIS_Pos 0 /*!< SSP0 RIS: RORRIS Position */ #define SSP0_RIS_RORRIS_Msk (0x01UL << SSP0_RIS_RORRIS_Pos) /*!< SSP0 RIS: RORRIS Mask */ #define SSP0_RIS_RTRIS_Pos 1 /*!< SSP0 RIS: RTRIS Position */ #define SSP0_RIS_RTRIS_Msk (0x01UL << SSP0_RIS_RTRIS_Pos) /*!< SSP0 RIS: RTRIS Mask */ #define SSP0_RIS_RXRIS_Pos 2 /*!< SSP0 RIS: RXRIS Position */ #define SSP0_RIS_RXRIS_Msk (0x01UL << SSP0_RIS_RXRIS_Pos) /*!< SSP0 RIS: RXRIS Mask */ #define SSP0_RIS_TXRIS_Pos 3 /*!< SSP0 RIS: TXRIS Position */ #define SSP0_RIS_TXRIS_Msk (0x01UL << SSP0_RIS_TXRIS_Pos) /*!< SSP0 RIS: TXRIS Mask */ /* ---------------------------------- SSP0_MIS ---------------------------------- */ #define SSP0_MIS_RORMIS_Pos 0 /*!< SSP0 MIS: RORMIS Position */ #define SSP0_MIS_RORMIS_Msk (0x01UL << SSP0_MIS_RORMIS_Pos) /*!< SSP0 MIS: RORMIS Mask */ #define SSP0_MIS_RTMIS_Pos 1 /*!< SSP0 MIS: RTMIS Position */ #define SSP0_MIS_RTMIS_Msk (0x01UL << SSP0_MIS_RTMIS_Pos) /*!< SSP0 MIS: RTMIS Mask */ #define SSP0_MIS_RXMIS_Pos 2 /*!< SSP0 MIS: RXMIS Position */ #define SSP0_MIS_RXMIS_Msk (0x01UL << SSP0_MIS_RXMIS_Pos) /*!< SSP0 MIS: RXMIS Mask */ #define SSP0_MIS_TXMIS_Pos 3 /*!< SSP0 MIS: TXMIS Position */ #define SSP0_MIS_TXMIS_Msk (0x01UL << SSP0_MIS_TXMIS_Pos) /*!< SSP0 MIS: TXMIS Mask */ /* ---------------------------------- SSP0_ICR ---------------------------------- */ #define SSP0_ICR_RORIC_Pos 0 /*!< SSP0 ICR: RORIC Position */ #define SSP0_ICR_RORIC_Msk (0x01UL << SSP0_ICR_RORIC_Pos) /*!< SSP0 ICR: RORIC Mask */ #define SSP0_ICR_RTIC_Pos 1 /*!< SSP0 ICR: RTIC Position */ #define SSP0_ICR_RTIC_Msk (0x01UL << SSP0_ICR_RTIC_Pos) /*!< SSP0 ICR: RTIC Mask */ /* --------------------------------- SSP0_DMACR --------------------------------- */ #define SSP0_DMACR_RXDMAE_Pos 0 /*!< SSP0 DMACR: RXDMAE Position */ #define SSP0_DMACR_RXDMAE_Msk (0x01UL << SSP0_DMACR_RXDMAE_Pos) /*!< SSP0 DMACR: RXDMAE Mask */ #define SSP0_DMACR_TXDMAE_Pos 1 /*!< SSP0 DMACR: TXDMAE Position */ #define SSP0_DMACR_TXDMAE_Msk (0x01UL << SSP0_DMACR_TXDMAE_Pos) /*!< SSP0 DMACR: TXDMAE Mask */ /* ================================================================================ */ /* ================ struct 'SSP1' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- SSP1_CR0 ---------------------------------- */ #define SSP1_CR0_DSS_Pos 0 /*!< SSP1 CR0: DSS Position */ #define SSP1_CR0_DSS_Msk (0x0fUL << SSP1_CR0_DSS_Pos) /*!< SSP1 CR0: DSS Mask */ #define SSP1_CR0_FRF_Pos 4 /*!< SSP1 CR0: FRF Position */ #define SSP1_CR0_FRF_Msk (0x03UL << SSP1_CR0_FRF_Pos) /*!< SSP1 CR0: FRF Mask */ #define SSP1_CR0_CPOL_Pos 6 /*!< SSP1 CR0: CPOL Position */ #define SSP1_CR0_CPOL_Msk (0x01UL << SSP1_CR0_CPOL_Pos) /*!< SSP1 CR0: CPOL Mask */ #define SSP1_CR0_CPHA_Pos 7 /*!< SSP1 CR0: CPHA Position */ #define SSP1_CR0_CPHA_Msk (0x01UL << SSP1_CR0_CPHA_Pos) /*!< SSP1 CR0: CPHA Mask */ #define SSP1_CR0_SCR_Pos 8 /*!< SSP1 CR0: SCR Position */ #define SSP1_CR0_SCR_Msk (0x000000ffUL << SSP1_CR0_SCR_Pos) /*!< SSP1 CR0: SCR Mask */ /* ---------------------------------- SSP1_CR1 ---------------------------------- */ #define SSP1_CR1_LBM_Pos 0 /*!< SSP1 CR1: LBM Position */ #define SSP1_CR1_LBM_Msk (0x01UL << SSP1_CR1_LBM_Pos) /*!< SSP1 CR1: LBM Mask */ #define SSP1_CR1_SSE_Pos 1 /*!< SSP1 CR1: SSE Position */ #define SSP1_CR1_SSE_Msk (0x01UL << SSP1_CR1_SSE_Pos) /*!< SSP1 CR1: SSE Mask */ #define SSP1_CR1_MS_Pos 2 /*!< SSP1 CR1: MS Position */ #define SSP1_CR1_MS_Msk (0x01UL << SSP1_CR1_MS_Pos) /*!< SSP1 CR1: MS Mask */ #define SSP1_CR1_SOD_Pos 3 /*!< SSP1 CR1: SOD Position */ #define SSP1_CR1_SOD_Msk (0x01UL << SSP1_CR1_SOD_Pos) /*!< SSP1 CR1: SOD Mask */ /* ----------------------------------- SSP1_DR ---------------------------------- */ #define SSP1_DR_DATA_Pos 0 /*!< SSP1 DR: DATA Position */ #define SSP1_DR_DATA_Msk (0x0000ffffUL << SSP1_DR_DATA_Pos) /*!< SSP1 DR: DATA Mask */ /* ----------------------------------- SSP1_SR ---------------------------------- */ #define SSP1_SR_TFE_Pos 0 /*!< SSP1 SR: TFE Position */ #define SSP1_SR_TFE_Msk (0x01UL << SSP1_SR_TFE_Pos) /*!< SSP1 SR: TFE Mask */ #define SSP1_SR_TNF_Pos 1 /*!< SSP1 SR: TNF Position */ #define SSP1_SR_TNF_Msk (0x01UL << SSP1_SR_TNF_Pos) /*!< SSP1 SR: TNF Mask */ #define SSP1_SR_RNE_Pos 2 /*!< SSP1 SR: RNE Position */ #define SSP1_SR_RNE_Msk (0x01UL << SSP1_SR_RNE_Pos) /*!< SSP1 SR: RNE Mask */ #define SSP1_SR_RFF_Pos 3 /*!< SSP1 SR: RFF Position */ #define SSP1_SR_RFF_Msk (0x01UL << SSP1_SR_RFF_Pos) /*!< SSP1 SR: RFF Mask */ #define SSP1_SR_BSY_Pos 4 /*!< SSP1 SR: BSY Position */ #define SSP1_SR_BSY_Msk (0x01UL << SSP1_SR_BSY_Pos) /*!< SSP1 SR: BSY Mask */ /* ---------------------------------- SSP1_CPSR --------------------------------- */ #define SSP1_CPSR_CPSDVSR_Pos 0 /*!< SSP1 CPSR: CPSDVSR Position */ #define SSP1_CPSR_CPSDVSR_Msk (0x000000ffUL << SSP1_CPSR_CPSDVSR_Pos) /*!< SSP1 CPSR: CPSDVSR Mask */ /* ---------------------------------- SSP1_IMSC --------------------------------- */ #define SSP1_IMSC_RORIM_Pos 0 /*!< SSP1 IMSC: RORIM Position */ #define SSP1_IMSC_RORIM_Msk (0x01UL << SSP1_IMSC_RORIM_Pos) /*!< SSP1 IMSC: RORIM Mask */ #define SSP1_IMSC_RTIM_Pos 1 /*!< SSP1 IMSC: RTIM Position */ #define SSP1_IMSC_RTIM_Msk (0x01UL << SSP1_IMSC_RTIM_Pos) /*!< SSP1 IMSC: RTIM Mask */ #define SSP1_IMSC_RXIM_Pos 2 /*!< SSP1 IMSC: RXIM Position */ #define SSP1_IMSC_RXIM_Msk (0x01UL << SSP1_IMSC_RXIM_Pos) /*!< SSP1 IMSC: RXIM Mask */ #define SSP1_IMSC_TXIM_Pos 3 /*!< SSP1 IMSC: TXIM Position */ #define SSP1_IMSC_TXIM_Msk (0x01UL << SSP1_IMSC_TXIM_Pos) /*!< SSP1 IMSC: TXIM Mask */ /* ---------------------------------- SSP1_RIS ---------------------------------- */ #define SSP1_RIS_RORRIS_Pos 0 /*!< SSP1 RIS: RORRIS Position */ #define SSP1_RIS_RORRIS_Msk (0x01UL << SSP1_RIS_RORRIS_Pos) /*!< SSP1 RIS: RORRIS Mask */ #define SSP1_RIS_RTRIS_Pos 1 /*!< SSP1 RIS: RTRIS Position */ #define SSP1_RIS_RTRIS_Msk (0x01UL << SSP1_RIS_RTRIS_Pos) /*!< SSP1 RIS: RTRIS Mask */ #define SSP1_RIS_RXRIS_Pos 2 /*!< SSP1 RIS: RXRIS Position */ #define SSP1_RIS_RXRIS_Msk (0x01UL << SSP1_RIS_RXRIS_Pos) /*!< SSP1 RIS: RXRIS Mask */ #define SSP1_RIS_TXRIS_Pos 3 /*!< SSP1 RIS: TXRIS Position */ #define SSP1_RIS_TXRIS_Msk (0x01UL << SSP1_RIS_TXRIS_Pos) /*!< SSP1 RIS: TXRIS Mask */ /* ---------------------------------- SSP1_MIS ---------------------------------- */ #define SSP1_MIS_RORMIS_Pos 0 /*!< SSP1 MIS: RORMIS Position */ #define SSP1_MIS_RORMIS_Msk (0x01UL << SSP1_MIS_RORMIS_Pos) /*!< SSP1 MIS: RORMIS Mask */ #define SSP1_MIS_RTMIS_Pos 1 /*!< SSP1 MIS: RTMIS Position */ #define SSP1_MIS_RTMIS_Msk (0x01UL << SSP1_MIS_RTMIS_Pos) /*!< SSP1 MIS: RTMIS Mask */ #define SSP1_MIS_RXMIS_Pos 2 /*!< SSP1 MIS: RXMIS Position */ #define SSP1_MIS_RXMIS_Msk (0x01UL << SSP1_MIS_RXMIS_Pos) /*!< SSP1 MIS: RXMIS Mask */ #define SSP1_MIS_TXMIS_Pos 3 /*!< SSP1 MIS: TXMIS Position */ #define SSP1_MIS_TXMIS_Msk (0x01UL << SSP1_MIS_TXMIS_Pos) /*!< SSP1 MIS: TXMIS Mask */ /* ---------------------------------- SSP1_ICR ---------------------------------- */ #define SSP1_ICR_RORIC_Pos 0 /*!< SSP1 ICR: RORIC Position */ #define SSP1_ICR_RORIC_Msk (0x01UL << SSP1_ICR_RORIC_Pos) /*!< SSP1 ICR: RORIC Mask */ #define SSP1_ICR_RTIC_Pos 1 /*!< SSP1 ICR: RTIC Position */ #define SSP1_ICR_RTIC_Msk (0x01UL << SSP1_ICR_RTIC_Pos) /*!< SSP1 ICR: RTIC Mask */ /* --------------------------------- SSP1_DMACR --------------------------------- */ #define SSP1_DMACR_RXDMAE_Pos 0 /*!< SSP1 DMACR: RXDMAE Position */ #define SSP1_DMACR_RXDMAE_Msk (0x01UL << SSP1_DMACR_RXDMAE_Pos) /*!< SSP1 DMACR: RXDMAE Mask */ #define SSP1_DMACR_TXDMAE_Pos 1 /*!< SSP1 DMACR: TXDMAE Position */ #define SSP1_DMACR_TXDMAE_Msk (0x01UL << SSP1_DMACR_TXDMAE_Pos) /*!< SSP1 DMACR: TXDMAE Mask */ /* ================================================================================ */ /* ================ Group 'TIMERn' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- TIMERn_IR --------------------------------- */ #define TIMERn_IR_MR0INT_Pos 0 /*!< TIMERn IR: MR0INT Position */ #define TIMERn_IR_MR0INT_Msk (0x01UL << TIMERn_IR_MR0INT_Pos) /*!< TIMERn IR: MR0INT Mask */ #define TIMERn_IR_MR1INT_Pos 1 /*!< TIMERn IR: MR1INT Position */ #define TIMERn_IR_MR1INT_Msk (0x01UL << TIMERn_IR_MR1INT_Pos) /*!< TIMERn IR: MR1INT Mask */ #define TIMERn_IR_MR2INT_Pos 2 /*!< TIMERn IR: MR2INT Position */ #define TIMERn_IR_MR2INT_Msk (0x01UL << TIMERn_IR_MR2INT_Pos) /*!< TIMERn IR: MR2INT Mask */ #define TIMERn_IR_MR3INT_Pos 3 /*!< TIMERn IR: MR3INT Position */ #define TIMERn_IR_MR3INT_Msk (0x01UL << TIMERn_IR_MR3INT_Pos) /*!< TIMERn IR: MR3INT Mask */ #define TIMERn_IR_CR0INT_Pos 4 /*!< TIMERn IR: CR0INT Position */ #define TIMERn_IR_CR0INT_Msk (0x01UL << TIMERn_IR_CR0INT_Pos) /*!< TIMERn IR: CR0INT Mask */ #define TIMERn_IR_CR1INT_Pos 5 /*!< TIMERn IR: CR1INT Position */ #define TIMERn_IR_CR1INT_Msk (0x01UL << TIMERn_IR_CR1INT_Pos) /*!< TIMERn IR: CR1INT Mask */ #define TIMERn_IR_CR2INT_Pos 6 /*!< TIMERn IR: CR2INT Position */ #define TIMERn_IR_CR2INT_Msk (0x01UL << TIMERn_IR_CR2INT_Pos) /*!< TIMERn IR: CR2INT Mask */ #define TIMERn_IR_CR3INT_Pos 7 /*!< TIMERn IR: CR3INT Position */ #define TIMERn_IR_CR3INT_Msk (0x01UL << TIMERn_IR_CR3INT_Pos) /*!< TIMERn IR: CR3INT Mask */ /* --------------------------------- TIMERn_TCR --------------------------------- */ #define TIMERn_TCR_CEN_Pos 0 /*!< TIMERn TCR: CEN Position */ #define TIMERn_TCR_CEN_Msk (0x01UL << TIMERn_TCR_CEN_Pos) /*!< TIMERn TCR: CEN Mask */ #define TIMERn_TCR_CRST_Pos 1 /*!< TIMERn TCR: CRST Position */ #define TIMERn_TCR_CRST_Msk (0x01UL << TIMERn_TCR_CRST_Pos) /*!< TIMERn TCR: CRST Mask */ /* ---------------------------------- TIMERn_TC --------------------------------- */ #define TIMERn_TC_TC_Pos 0 /*!< TIMERn TC: TC Position */ #define TIMERn_TC_TC_Msk (0xffffffffUL << TIMERn_TC_TC_Pos) /*!< TIMERn TC: TC Mask */ /* ---------------------------------- TIMERn_PR --------------------------------- */ #define TIMERn_PR_PM_Pos 0 /*!< TIMERn PR: PM Position */ #define TIMERn_PR_PM_Msk (0xffffffffUL << TIMERn_PR_PM_Pos) /*!< TIMERn PR: PM Mask */ /* ---------------------------------- TIMERn_PC --------------------------------- */ #define TIMERn_PC_PC_Pos 0 /*!< TIMERn PC: PC Position */ #define TIMERn_PC_PC_Msk (0xffffffffUL << TIMERn_PC_PC_Pos) /*!< TIMERn PC: PC Mask */ /* --------------------------------- TIMERn_MCR --------------------------------- */ #define TIMERn_MCR_MR0I_Pos 0 /*!< TIMERn MCR: MR0I Position */ #define TIMERn_MCR_MR0I_Msk (0x01UL << TIMERn_MCR_MR0I_Pos) /*!< TIMERn MCR: MR0I Mask */ #define TIMERn_MCR_MR0R_Pos 1 /*!< TIMERn MCR: MR0R Position */ #define TIMERn_MCR_MR0R_Msk (0x01UL << TIMERn_MCR_MR0R_Pos) /*!< TIMERn MCR: MR0R Mask */ #define TIMERn_MCR_MR0S_Pos 2 /*!< TIMERn MCR: MR0S Position */ #define TIMERn_MCR_MR0S_Msk (0x01UL << TIMERn_MCR_MR0S_Pos) /*!< TIMERn MCR: MR0S Mask */ #define TIMERn_MCR_MR1I_Pos 3 /*!< TIMERn MCR: MR1I Position */ #define TIMERn_MCR_MR1I_Msk (0x01UL << TIMERn_MCR_MR1I_Pos) /*!< TIMERn MCR: MR1I Mask */ #define TIMERn_MCR_MR1R_Pos 4 /*!< TIMERn MCR: MR1R Position */ #define TIMERn_MCR_MR1R_Msk (0x01UL << TIMERn_MCR_MR1R_Pos) /*!< TIMERn MCR: MR1R Mask */ #define TIMERn_MCR_MR1S_Pos 5 /*!< TIMERn MCR: MR1S Position */ #define TIMERn_MCR_MR1S_Msk (0x01UL << TIMERn_MCR_MR1S_Pos) /*!< TIMERn MCR: MR1S Mask */ #define TIMERn_MCR_MR2I_Pos 6 /*!< TIMERn MCR: MR2I Position */ #define TIMERn_MCR_MR2I_Msk (0x01UL << TIMERn_MCR_MR2I_Pos) /*!< TIMERn MCR: MR2I Mask */ #define TIMERn_MCR_MR2R_Pos 7 /*!< TIMERn MCR: MR2R Position */ #define TIMERn_MCR_MR2R_Msk (0x01UL << TIMERn_MCR_MR2R_Pos) /*!< TIMERn MCR: MR2R Mask */ #define TIMERn_MCR_MR2S_Pos 8 /*!< TIMERn MCR: MR2S Position */ #define TIMERn_MCR_MR2S_Msk (0x01UL << TIMERn_MCR_MR2S_Pos) /*!< TIMERn MCR: MR2S Mask */ #define TIMERn_MCR_MR3I_Pos 9 /*!< TIMERn MCR: MR3I Position */ #define TIMERn_MCR_MR3I_Msk (0x01UL << TIMERn_MCR_MR3I_Pos) /*!< TIMERn MCR: MR3I Mask */ #define TIMERn_MCR_MR3R_Pos 10 /*!< TIMERn MCR: MR3R Position */ #define TIMERn_MCR_MR3R_Msk (0x01UL << TIMERn_MCR_MR3R_Pos) /*!< TIMERn MCR: MR3R Mask */ #define TIMERn_MCR_MR3S_Pos 11 /*!< TIMERn MCR: MR3S Position */ #define TIMERn_MCR_MR3S_Msk (0x01UL << TIMERn_MCR_MR3S_Pos) /*!< TIMERn MCR: MR3S Mask */ /* --------------------------------- TIMERn_MR0 --------------------------------- */ #define TIMERn_MR0_MATCH_Pos 0 /*!< TIMERn MR0: MATCH Position */ #define TIMERn_MR0_MATCH_Msk (0xffffffffUL << TIMERn_MR0_MATCH_Pos) /*!< TIMERn MR0: MATCH Mask */ /* --------------------------------- TIMERn_MR1 --------------------------------- */ #define TIMERn_MR1_MATCH_Pos 0 /*!< TIMERn MR1: MATCH Position */ #define TIMERn_MR1_MATCH_Msk (0xffffffffUL << TIMERn_MR1_MATCH_Pos) /*!< TIMERn MR1: MATCH Mask */ /* --------------------------------- TIMERn_MR2 --------------------------------- */ #define TIMERn_MR2_MATCH_Pos 0 /*!< TIMERn MR2: MATCH Position */ #define TIMERn_MR2_MATCH_Msk (0xffffffffUL << TIMERn_MR2_MATCH_Pos) /*!< TIMERn MR2: MATCH Mask */ /* --------------------------------- TIMERn_MR3 --------------------------------- */ #define TIMERn_MR3_MATCH_Pos 0 /*!< TIMERn MR3: MATCH Position */ #define TIMERn_MR3_MATCH_Msk (0xffffffffUL << TIMERn_MR3_MATCH_Pos) /*!< TIMERn MR3: MATCH Mask */ /* --------------------------------- TIMERn_CCR --------------------------------- */ #define TIMERn_CCR_CAP0RE_Pos 0 /*!< TIMERn CCR: CAP0RE Position */ #define TIMERn_CCR_CAP0RE_Msk (0x01UL << TIMERn_CCR_CAP0RE_Pos) /*!< TIMERn CCR: CAP0RE Mask */ #define TIMERn_CCR_CAP0FE_Pos 1 /*!< TIMERn CCR: CAP0FE Position */ #define TIMERn_CCR_CAP0FE_Msk (0x01UL << TIMERn_CCR_CAP0FE_Pos) /*!< TIMERn CCR: CAP0FE Mask */ #define TIMERn_CCR_CAP0I_Pos 2 /*!< TIMERn CCR: CAP0I Position */ #define TIMERn_CCR_CAP0I_Msk (0x01UL << TIMERn_CCR_CAP0I_Pos) /*!< TIMERn CCR: CAP0I Mask */ #define TIMERn_CCR_CAP1RE_Pos 3 /*!< TIMERn CCR: CAP1RE Position */ #define TIMERn_CCR_CAP1RE_Msk (0x01UL << TIMERn_CCR_CAP1RE_Pos) /*!< TIMERn CCR: CAP1RE Mask */ #define TIMERn_CCR_CAP1FE_Pos 4 /*!< TIMERn CCR: CAP1FE Position */ #define TIMERn_CCR_CAP1FE_Msk (0x01UL << TIMERn_CCR_CAP1FE_Pos) /*!< TIMERn CCR: CAP1FE Mask */ #define TIMERn_CCR_CAP1I_Pos 5 /*!< TIMERn CCR: CAP1I Position */ #define TIMERn_CCR_CAP1I_Msk (0x01UL << TIMERn_CCR_CAP1I_Pos) /*!< TIMERn CCR: CAP1I Mask */ #define TIMERn_CCR_CAP2RE_Pos 6 /*!< TIMERn CCR: CAP2RE Position */ #define TIMERn_CCR_CAP2RE_Msk (0x01UL << TIMERn_CCR_CAP2RE_Pos) /*!< TIMERn CCR: CAP2RE Mask */ #define TIMERn_CCR_CAP2FE_Pos 7 /*!< TIMERn CCR: CAP2FE Position */ #define TIMERn_CCR_CAP2FE_Msk (0x01UL << TIMERn_CCR_CAP2FE_Pos) /*!< TIMERn CCR: CAP2FE Mask */ #define TIMERn_CCR_CAP2I_Pos 8 /*!< TIMERn CCR: CAP2I Position */ #define TIMERn_CCR_CAP2I_Msk (0x01UL << TIMERn_CCR_CAP2I_Pos) /*!< TIMERn CCR: CAP2I Mask */ #define TIMERn_CCR_CAP3RE_Pos 9 /*!< TIMERn CCR: CAP3RE Position */ #define TIMERn_CCR_CAP3RE_Msk (0x01UL << TIMERn_CCR_CAP3RE_Pos) /*!< TIMERn CCR: CAP3RE Mask */ #define TIMERn_CCR_CAP3FE_Pos 10 /*!< TIMERn CCR: CAP3FE Position */ #define TIMERn_CCR_CAP3FE_Msk (0x01UL << TIMERn_CCR_CAP3FE_Pos) /*!< TIMERn CCR: CAP3FE Mask */ #define TIMERn_CCR_CAP3I_Pos 11 /*!< TIMERn CCR: CAP3I Position */ #define TIMERn_CCR_CAP3I_Msk (0x01UL << TIMERn_CCR_CAP3I_Pos) /*!< TIMERn CCR: CAP3I Mask */ /* --------------------------------- TIMERn_CR0 --------------------------------- */ #define TIMERn_CR0_CAP_Pos 0 /*!< TIMERn CR0: CAP Position */ #define TIMERn_CR0_CAP_Msk (0xffffffffUL << TIMERn_CR0_CAP_Pos) /*!< TIMERn CR0: CAP Mask */ /* --------------------------------- TIMERn_CR1 --------------------------------- */ #define TIMERn_CR1_CAP_Pos 0 /*!< TIMERn CR1: CAP Position */ #define TIMERn_CR1_CAP_Msk (0xffffffffUL << TIMERn_CR1_CAP_Pos) /*!< TIMERn CR1: CAP Mask */ /* --------------------------------- TIMERn_CR2 --------------------------------- */ #define TIMERn_CR2_CAP_Pos 0 /*!< TIMERn CR2: CAP Position */ #define TIMERn_CR2_CAP_Msk (0xffffffffUL << TIMERn_CR2_CAP_Pos) /*!< TIMERn CR2: CAP Mask */ /* --------------------------------- TIMERn_CR3 --------------------------------- */ #define TIMERn_CR3_CAP_Pos 0 /*!< TIMERn CR3: CAP Position */ #define TIMERn_CR3_CAP_Msk (0xffffffffUL << TIMERn_CR3_CAP_Pos) /*!< TIMERn CR3: CAP Mask */ /* --------------------------------- TIMERn_EMR --------------------------------- */ #define TIMERn_EMR_EM0_Pos 0 /*!< TIMERn EMR: EM0 Position */ #define TIMERn_EMR_EM0_Msk (0x01UL << TIMERn_EMR_EM0_Pos) /*!< TIMERn EMR: EM0 Mask */ #define TIMERn_EMR_EM1_Pos 1 /*!< TIMERn EMR: EM1 Position */ #define TIMERn_EMR_EM1_Msk (0x01UL << TIMERn_EMR_EM1_Pos) /*!< TIMERn EMR: EM1 Mask */ #define TIMERn_EMR_EM2_Pos 2 /*!< TIMERn EMR: EM2 Position */ #define TIMERn_EMR_EM2_Msk (0x01UL << TIMERn_EMR_EM2_Pos) /*!< TIMERn EMR: EM2 Mask */ #define TIMERn_EMR_EM3_Pos 3 /*!< TIMERn EMR: EM3 Position */ #define TIMERn_EMR_EM3_Msk (0x01UL << TIMERn_EMR_EM3_Pos) /*!< TIMERn EMR: EM3 Mask */ #define TIMERn_EMR_EMC0_Pos 4 /*!< TIMERn EMR: EMC0 Position */ #define TIMERn_EMR_EMC0_Msk (0x03UL << TIMERn_EMR_EMC0_Pos) /*!< TIMERn EMR: EMC0 Mask */ #define TIMERn_EMR_EMC1_Pos 6 /*!< TIMERn EMR: EMC1 Position */ #define TIMERn_EMR_EMC1_Msk (0x03UL << TIMERn_EMR_EMC1_Pos) /*!< TIMERn EMR: EMC1 Mask */ #define TIMERn_EMR_EMC2_Pos 8 /*!< TIMERn EMR: EMC2 Position */ #define TIMERn_EMR_EMC2_Msk (0x03UL << TIMERn_EMR_EMC2_Pos) /*!< TIMERn EMR: EMC2 Mask */ #define TIMERn_EMR_EMC3_Pos 10 /*!< TIMERn EMR: EMC3 Position */ #define TIMERn_EMR_EMC3_Msk (0x03UL << TIMERn_EMR_EMC3_Pos) /*!< TIMERn EMR: EMC3 Mask */ /* --------------------------------- TIMERn_CTCR -------------------------------- */ #define TIMERn_CTCR_CTMODE_Pos 0 /*!< TIMERn CTCR: CTMODE Position */ #define TIMERn_CTCR_CTMODE_Msk (0x03UL << TIMERn_CTCR_CTMODE_Pos) /*!< TIMERn CTCR: CTMODE Mask */ #define TIMERn_CTCR_CINSEL_Pos 2 /*!< TIMERn CTCR: CINSEL Position */ #define TIMERn_CTCR_CINSEL_Msk (0x03UL << TIMERn_CTCR_CINSEL_Pos) /*!< TIMERn CTCR: CINSEL Mask */ /* ================================================================================ */ /* ================ struct 'TIMER0' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- TIMER0_IR --------------------------------- */ #define TIMER0_IR_MR0INT_Pos 0 /*!< TIMER0 IR: MR0INT Position */ #define TIMER0_IR_MR0INT_Msk (0x01UL << TIMER0_IR_MR0INT_Pos) /*!< TIMER0 IR: MR0INT Mask */ #define TIMER0_IR_MR1INT_Pos 1 /*!< TIMER0 IR: MR1INT Position */ #define TIMER0_IR_MR1INT_Msk (0x01UL << TIMER0_IR_MR1INT_Pos) /*!< TIMER0 IR: MR1INT Mask */ #define TIMER0_IR_MR2INT_Pos 2 /*!< TIMER0 IR: MR2INT Position */ #define TIMER0_IR_MR2INT_Msk (0x01UL << TIMER0_IR_MR2INT_Pos) /*!< TIMER0 IR: MR2INT Mask */ #define TIMER0_IR_MR3INT_Pos 3 /*!< TIMER0 IR: MR3INT Position */ #define TIMER0_IR_MR3INT_Msk (0x01UL << TIMER0_IR_MR3INT_Pos) /*!< TIMER0 IR: MR3INT Mask */ #define TIMER0_IR_CR0INT_Pos 4 /*!< TIMER0 IR: CR0INT Position */ #define TIMER0_IR_CR0INT_Msk (0x01UL << TIMER0_IR_CR0INT_Pos) /*!< TIMER0 IR: CR0INT Mask */ #define TIMER0_IR_CR1INT_Pos 5 /*!< TIMER0 IR: CR1INT Position */ #define TIMER0_IR_CR1INT_Msk (0x01UL << TIMER0_IR_CR1INT_Pos) /*!< TIMER0 IR: CR1INT Mask */ #define TIMER0_IR_CR2INT_Pos 6 /*!< TIMER0 IR: CR2INT Position */ #define TIMER0_IR_CR2INT_Msk (0x01UL << TIMER0_IR_CR2INT_Pos) /*!< TIMER0 IR: CR2INT Mask */ #define TIMER0_IR_CR3INT_Pos 7 /*!< TIMER0 IR: CR3INT Position */ #define TIMER0_IR_CR3INT_Msk (0x01UL << TIMER0_IR_CR3INT_Pos) /*!< TIMER0 IR: CR3INT Mask */ /* --------------------------------- TIMER0_TCR --------------------------------- */ #define TIMER0_TCR_CEN_Pos 0 /*!< TIMER0 TCR: CEN Position */ #define TIMER0_TCR_CEN_Msk (0x01UL << TIMER0_TCR_CEN_Pos) /*!< TIMER0 TCR: CEN Mask */ #define TIMER0_TCR_CRST_Pos 1 /*!< TIMER0 TCR: CRST Position */ #define TIMER0_TCR_CRST_Msk (0x01UL << TIMER0_TCR_CRST_Pos) /*!< TIMER0 TCR: CRST Mask */ /* ---------------------------------- TIMER0_TC --------------------------------- */ #define TIMER0_TC_TC_Pos 0 /*!< TIMER0 TC: TC Position */ #define TIMER0_TC_TC_Msk (0xffffffffUL << TIMER0_TC_TC_Pos) /*!< TIMER0 TC: TC Mask */ /* ---------------------------------- TIMER0_PR --------------------------------- */ #define TIMER0_PR_PM_Pos 0 /*!< TIMER0 PR: PM Position */ #define TIMER0_PR_PM_Msk (0xffffffffUL << TIMER0_PR_PM_Pos) /*!< TIMER0 PR: PM Mask */ /* ---------------------------------- TIMER0_PC --------------------------------- */ #define TIMER0_PC_PC_Pos 0 /*!< TIMER0 PC: PC Position */ #define TIMER0_PC_PC_Msk (0xffffffffUL << TIMER0_PC_PC_Pos) /*!< TIMER0 PC: PC Mask */ /* --------------------------------- TIMER0_MCR --------------------------------- */ #define TIMER0_MCR_MR0I_Pos 0 /*!< TIMER0 MCR: MR0I Position */ #define TIMER0_MCR_MR0I_Msk (0x01UL << TIMER0_MCR_MR0I_Pos) /*!< TIMER0 MCR: MR0I Mask */ #define TIMER0_MCR_MR0R_Pos 1 /*!< TIMER0 MCR: MR0R Position */ #define TIMER0_MCR_MR0R_Msk (0x01UL << TIMER0_MCR_MR0R_Pos) /*!< TIMER0 MCR: MR0R Mask */ #define TIMER0_MCR_MR0S_Pos 2 /*!< TIMER0 MCR: MR0S Position */ #define TIMER0_MCR_MR0S_Msk (0x01UL << TIMER0_MCR_MR0S_Pos) /*!< TIMER0 MCR: MR0S Mask */ #define TIMER0_MCR_MR1I_Pos 3 /*!< TIMER0 MCR: MR1I Position */ #define TIMER0_MCR_MR1I_Msk (0x01UL << TIMER0_MCR_MR1I_Pos) /*!< TIMER0 MCR: MR1I Mask */ #define TIMER0_MCR_MR1R_Pos 4 /*!< TIMER0 MCR: MR1R Position */ #define TIMER0_MCR_MR1R_Msk (0x01UL << TIMER0_MCR_MR1R_Pos) /*!< TIMER0 MCR: MR1R Mask */ #define TIMER0_MCR_MR1S_Pos 5 /*!< TIMER0 MCR: MR1S Position */ #define TIMER0_MCR_MR1S_Msk (0x01UL << TIMER0_MCR_MR1S_Pos) /*!< TIMER0 MCR: MR1S Mask */ #define TIMER0_MCR_MR2I_Pos 6 /*!< TIMER0 MCR: MR2I Position */ #define TIMER0_MCR_MR2I_Msk (0x01UL << TIMER0_MCR_MR2I_Pos) /*!< TIMER0 MCR: MR2I Mask */ #define TIMER0_MCR_MR2R_Pos 7 /*!< TIMER0 MCR: MR2R Position */ #define TIMER0_MCR_MR2R_Msk (0x01UL << TIMER0_MCR_MR2R_Pos) /*!< TIMER0 MCR: MR2R Mask */ #define TIMER0_MCR_MR2S_Pos 8 /*!< TIMER0 MCR: MR2S Position */ #define TIMER0_MCR_MR2S_Msk (0x01UL << TIMER0_MCR_MR2S_Pos) /*!< TIMER0 MCR: MR2S Mask */ #define TIMER0_MCR_MR3I_Pos 9 /*!< TIMER0 MCR: MR3I Position */ #define TIMER0_MCR_MR3I_Msk (0x01UL << TIMER0_MCR_MR3I_Pos) /*!< TIMER0 MCR: MR3I Mask */ #define TIMER0_MCR_MR3R_Pos 10 /*!< TIMER0 MCR: MR3R Position */ #define TIMER0_MCR_MR3R_Msk (0x01UL << TIMER0_MCR_MR3R_Pos) /*!< TIMER0 MCR: MR3R Mask */ #define TIMER0_MCR_MR3S_Pos 11 /*!< TIMER0 MCR: MR3S Position */ #define TIMER0_MCR_MR3S_Msk (0x01UL << TIMER0_MCR_MR3S_Pos) /*!< TIMER0 MCR: MR3S Mask */ /* --------------------------------- TIMER0_MR0 --------------------------------- */ #define TIMER0_MR0_MATCH_Pos 0 /*!< TIMER0 MR0: MATCH Position */ #define TIMER0_MR0_MATCH_Msk (0xffffffffUL << TIMER0_MR0_MATCH_Pos) /*!< TIMER0 MR0: MATCH Mask */ /* --------------------------------- TIMER0_MR1 --------------------------------- */ #define TIMER0_MR1_MATCH_Pos 0 /*!< TIMER0 MR1: MATCH Position */ #define TIMER0_MR1_MATCH_Msk (0xffffffffUL << TIMER0_MR1_MATCH_Pos) /*!< TIMER0 MR1: MATCH Mask */ /* --------------------------------- TIMER0_MR2 --------------------------------- */ #define TIMER0_MR2_MATCH_Pos 0 /*!< TIMER0 MR2: MATCH Position */ #define TIMER0_MR2_MATCH_Msk (0xffffffffUL << TIMER0_MR2_MATCH_Pos) /*!< TIMER0 MR2: MATCH Mask */ /* --------------------------------- TIMER0_MR3 --------------------------------- */ #define TIMER0_MR3_MATCH_Pos 0 /*!< TIMER0 MR3: MATCH Position */ #define TIMER0_MR3_MATCH_Msk (0xffffffffUL << TIMER0_MR3_MATCH_Pos) /*!< TIMER0 MR3: MATCH Mask */ /* --------------------------------- TIMER0_CCR --------------------------------- */ #define TIMER0_CCR_CAP0RE_Pos 0 /*!< TIMER0 CCR: CAP0RE Position */ #define TIMER0_CCR_CAP0RE_Msk (0x01UL << TIMER0_CCR_CAP0RE_Pos) /*!< TIMER0 CCR: CAP0RE Mask */ #define TIMER0_CCR_CAP0FE_Pos 1 /*!< TIMER0 CCR: CAP0FE Position */ #define TIMER0_CCR_CAP0FE_Msk (0x01UL << TIMER0_CCR_CAP0FE_Pos) /*!< TIMER0 CCR: CAP0FE Mask */ #define TIMER0_CCR_CAP0I_Pos 2 /*!< TIMER0 CCR: CAP0I Position */ #define TIMER0_CCR_CAP0I_Msk (0x01UL << TIMER0_CCR_CAP0I_Pos) /*!< TIMER0 CCR: CAP0I Mask */ #define TIMER0_CCR_CAP1RE_Pos 3 /*!< TIMER0 CCR: CAP1RE Position */ #define TIMER0_CCR_CAP1RE_Msk (0x01UL << TIMER0_CCR_CAP1RE_Pos) /*!< TIMER0 CCR: CAP1RE Mask */ #define TIMER0_CCR_CAP1FE_Pos 4 /*!< TIMER0 CCR: CAP1FE Position */ #define TIMER0_CCR_CAP1FE_Msk (0x01UL << TIMER0_CCR_CAP1FE_Pos) /*!< TIMER0 CCR: CAP1FE Mask */ #define TIMER0_CCR_CAP1I_Pos 5 /*!< TIMER0 CCR: CAP1I Position */ #define TIMER0_CCR_CAP1I_Msk (0x01UL << TIMER0_CCR_CAP1I_Pos) /*!< TIMER0 CCR: CAP1I Mask */ #define TIMER0_CCR_CAP2RE_Pos 6 /*!< TIMER0 CCR: CAP2RE Position */ #define TIMER0_CCR_CAP2RE_Msk (0x01UL << TIMER0_CCR_CAP2RE_Pos) /*!< TIMER0 CCR: CAP2RE Mask */ #define TIMER0_CCR_CAP2FE_Pos 7 /*!< TIMER0 CCR: CAP2FE Position */ #define TIMER0_CCR_CAP2FE_Msk (0x01UL << TIMER0_CCR_CAP2FE_Pos) /*!< TIMER0 CCR: CAP2FE Mask */ #define TIMER0_CCR_CAP2I_Pos 8 /*!< TIMER0 CCR: CAP2I Position */ #define TIMER0_CCR_CAP2I_Msk (0x01UL << TIMER0_CCR_CAP2I_Pos) /*!< TIMER0 CCR: CAP2I Mask */ #define TIMER0_CCR_CAP3RE_Pos 9 /*!< TIMER0 CCR: CAP3RE Position */ #define TIMER0_CCR_CAP3RE_Msk (0x01UL << TIMER0_CCR_CAP3RE_Pos) /*!< TIMER0 CCR: CAP3RE Mask */ #define TIMER0_CCR_CAP3FE_Pos 10 /*!< TIMER0 CCR: CAP3FE Position */ #define TIMER0_CCR_CAP3FE_Msk (0x01UL << TIMER0_CCR_CAP3FE_Pos) /*!< TIMER0 CCR: CAP3FE Mask */ #define TIMER0_CCR_CAP3I_Pos 11 /*!< TIMER0 CCR: CAP3I Position */ #define TIMER0_CCR_CAP3I_Msk (0x01UL << TIMER0_CCR_CAP3I_Pos) /*!< TIMER0 CCR: CAP3I Mask */ /* --------------------------------- TIMER0_CR0 --------------------------------- */ #define TIMER0_CR0_CAP_Pos 0 /*!< TIMER0 CR0: CAP Position */ #define TIMER0_CR0_CAP_Msk (0xffffffffUL << TIMER0_CR0_CAP_Pos) /*!< TIMER0 CR0: CAP Mask */ /* --------------------------------- TIMER0_CR1 --------------------------------- */ #define TIMER0_CR1_CAP_Pos 0 /*!< TIMER0 CR1: CAP Position */ #define TIMER0_CR1_CAP_Msk (0xffffffffUL << TIMER0_CR1_CAP_Pos) /*!< TIMER0 CR1: CAP Mask */ /* --------------------------------- TIMER0_CR2 --------------------------------- */ #define TIMER0_CR2_CAP_Pos 0 /*!< TIMER0 CR2: CAP Position */ #define TIMER0_CR2_CAP_Msk (0xffffffffUL << TIMER0_CR2_CAP_Pos) /*!< TIMER0 CR2: CAP Mask */ /* --------------------------------- TIMER0_CR3 --------------------------------- */ #define TIMER0_CR3_CAP_Pos 0 /*!< TIMER0 CR3: CAP Position */ #define TIMER0_CR3_CAP_Msk (0xffffffffUL << TIMER0_CR3_CAP_Pos) /*!< TIMER0 CR3: CAP Mask */ /* --------------------------------- TIMER0_EMR --------------------------------- */ #define TIMER0_EMR_EM0_Pos 0 /*!< TIMER0 EMR: EM0 Position */ #define TIMER0_EMR_EM0_Msk (0x01UL << TIMER0_EMR_EM0_Pos) /*!< TIMER0 EMR: EM0 Mask */ #define TIMER0_EMR_EM1_Pos 1 /*!< TIMER0 EMR: EM1 Position */ #define TIMER0_EMR_EM1_Msk (0x01UL << TIMER0_EMR_EM1_Pos) /*!< TIMER0 EMR: EM1 Mask */ #define TIMER0_EMR_EM2_Pos 2 /*!< TIMER0 EMR: EM2 Position */ #define TIMER0_EMR_EM2_Msk (0x01UL << TIMER0_EMR_EM2_Pos) /*!< TIMER0 EMR: EM2 Mask */ #define TIMER0_EMR_EM3_Pos 3 /*!< TIMER0 EMR: EM3 Position */ #define TIMER0_EMR_EM3_Msk (0x01UL << TIMER0_EMR_EM3_Pos) /*!< TIMER0 EMR: EM3 Mask */ #define TIMER0_EMR_EMC0_Pos 4 /*!< TIMER0 EMR: EMC0 Position */ #define TIMER0_EMR_EMC0_Msk (0x03UL << TIMER0_EMR_EMC0_Pos) /*!< TIMER0 EMR: EMC0 Mask */ #define TIMER0_EMR_EMC1_Pos 6 /*!< TIMER0 EMR: EMC1 Position */ #define TIMER0_EMR_EMC1_Msk (0x03UL << TIMER0_EMR_EMC1_Pos) /*!< TIMER0 EMR: EMC1 Mask */ #define TIMER0_EMR_EMC2_Pos 8 /*!< TIMER0 EMR: EMC2 Position */ #define TIMER0_EMR_EMC2_Msk (0x03UL << TIMER0_EMR_EMC2_Pos) /*!< TIMER0 EMR: EMC2 Mask */ #define TIMER0_EMR_EMC3_Pos 10 /*!< TIMER0 EMR: EMC3 Position */ #define TIMER0_EMR_EMC3_Msk (0x03UL << TIMER0_EMR_EMC3_Pos) /*!< TIMER0 EMR: EMC3 Mask */ /* --------------------------------- TIMER0_CTCR -------------------------------- */ #define TIMER0_CTCR_CTMODE_Pos 0 /*!< TIMER0 CTCR: CTMODE Position */ #define TIMER0_CTCR_CTMODE_Msk (0x03UL << TIMER0_CTCR_CTMODE_Pos) /*!< TIMER0 CTCR: CTMODE Mask */ #define TIMER0_CTCR_CINSEL_Pos 2 /*!< TIMER0 CTCR: CINSEL Position */ #define TIMER0_CTCR_CINSEL_Msk (0x03UL << TIMER0_CTCR_CINSEL_Pos) /*!< TIMER0 CTCR: CINSEL Mask */ /* ================================================================================ */ /* ================ struct 'TIMER1' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- TIMER1_IR --------------------------------- */ #define TIMER1_IR_MR0INT_Pos 0 /*!< TIMER1 IR: MR0INT Position */ #define TIMER1_IR_MR0INT_Msk (0x01UL << TIMER1_IR_MR0INT_Pos) /*!< TIMER1 IR: MR0INT Mask */ #define TIMER1_IR_MR1INT_Pos 1 /*!< TIMER1 IR: MR1INT Position */ #define TIMER1_IR_MR1INT_Msk (0x01UL << TIMER1_IR_MR1INT_Pos) /*!< TIMER1 IR: MR1INT Mask */ #define TIMER1_IR_MR2INT_Pos 2 /*!< TIMER1 IR: MR2INT Position */ #define TIMER1_IR_MR2INT_Msk (0x01UL << TIMER1_IR_MR2INT_Pos) /*!< TIMER1 IR: MR2INT Mask */ #define TIMER1_IR_MR3INT_Pos 3 /*!< TIMER1 IR: MR3INT Position */ #define TIMER1_IR_MR3INT_Msk (0x01UL << TIMER1_IR_MR3INT_Pos) /*!< TIMER1 IR: MR3INT Mask */ #define TIMER1_IR_CR0INT_Pos 4 /*!< TIMER1 IR: CR0INT Position */ #define TIMER1_IR_CR0INT_Msk (0x01UL << TIMER1_IR_CR0INT_Pos) /*!< TIMER1 IR: CR0INT Mask */ #define TIMER1_IR_CR1INT_Pos 5 /*!< TIMER1 IR: CR1INT Position */ #define TIMER1_IR_CR1INT_Msk (0x01UL << TIMER1_IR_CR1INT_Pos) /*!< TIMER1 IR: CR1INT Mask */ #define TIMER1_IR_CR2INT_Pos 6 /*!< TIMER1 IR: CR2INT Position */ #define TIMER1_IR_CR2INT_Msk (0x01UL << TIMER1_IR_CR2INT_Pos) /*!< TIMER1 IR: CR2INT Mask */ #define TIMER1_IR_CR3INT_Pos 7 /*!< TIMER1 IR: CR3INT Position */ #define TIMER1_IR_CR3INT_Msk (0x01UL << TIMER1_IR_CR3INT_Pos) /*!< TIMER1 IR: CR3INT Mask */ /* --------------------------------- TIMER1_TCR --------------------------------- */ #define TIMER1_TCR_CEN_Pos 0 /*!< TIMER1 TCR: CEN Position */ #define TIMER1_TCR_CEN_Msk (0x01UL << TIMER1_TCR_CEN_Pos) /*!< TIMER1 TCR: CEN Mask */ #define TIMER1_TCR_CRST_Pos 1 /*!< TIMER1 TCR: CRST Position */ #define TIMER1_TCR_CRST_Msk (0x01UL << TIMER1_TCR_CRST_Pos) /*!< TIMER1 TCR: CRST Mask */ /* ---------------------------------- TIMER1_TC --------------------------------- */ #define TIMER1_TC_TC_Pos 0 /*!< TIMER1 TC: TC Position */ #define TIMER1_TC_TC_Msk (0xffffffffUL << TIMER1_TC_TC_Pos) /*!< TIMER1 TC: TC Mask */ /* ---------------------------------- TIMER1_PR --------------------------------- */ #define TIMER1_PR_PM_Pos 0 /*!< TIMER1 PR: PM Position */ #define TIMER1_PR_PM_Msk (0xffffffffUL << TIMER1_PR_PM_Pos) /*!< TIMER1 PR: PM Mask */ /* ---------------------------------- TIMER1_PC --------------------------------- */ #define TIMER1_PC_PC_Pos 0 /*!< TIMER1 PC: PC Position */ #define TIMER1_PC_PC_Msk (0xffffffffUL << TIMER1_PC_PC_Pos) /*!< TIMER1 PC: PC Mask */ /* --------------------------------- TIMER1_MCR --------------------------------- */ #define TIMER1_MCR_MR0I_Pos 0 /*!< TIMER1 MCR: MR0I Position */ #define TIMER1_MCR_MR0I_Msk (0x01UL << TIMER1_MCR_MR0I_Pos) /*!< TIMER1 MCR: MR0I Mask */ #define TIMER1_MCR_MR0R_Pos 1 /*!< TIMER1 MCR: MR0R Position */ #define TIMER1_MCR_MR0R_Msk (0x01UL << TIMER1_MCR_MR0R_Pos) /*!< TIMER1 MCR: MR0R Mask */ #define TIMER1_MCR_MR0S_Pos 2 /*!< TIMER1 MCR: MR0S Position */ #define TIMER1_MCR_MR0S_Msk (0x01UL << TIMER1_MCR_MR0S_Pos) /*!< TIMER1 MCR: MR0S Mask */ #define TIMER1_MCR_MR1I_Pos 3 /*!< TIMER1 MCR: MR1I Position */ #define TIMER1_MCR_MR1I_Msk (0x01UL << TIMER1_MCR_MR1I_Pos) /*!< TIMER1 MCR: MR1I Mask */ #define TIMER1_MCR_MR1R_Pos 4 /*!< TIMER1 MCR: MR1R Position */ #define TIMER1_MCR_MR1R_Msk (0x01UL << TIMER1_MCR_MR1R_Pos) /*!< TIMER1 MCR: MR1R Mask */ #define TIMER1_MCR_MR1S_Pos 5 /*!< TIMER1 MCR: MR1S Position */ #define TIMER1_MCR_MR1S_Msk (0x01UL << TIMER1_MCR_MR1S_Pos) /*!< TIMER1 MCR: MR1S Mask */ #define TIMER1_MCR_MR2I_Pos 6 /*!< TIMER1 MCR: MR2I Position */ #define TIMER1_MCR_MR2I_Msk (0x01UL << TIMER1_MCR_MR2I_Pos) /*!< TIMER1 MCR: MR2I Mask */ #define TIMER1_MCR_MR2R_Pos 7 /*!< TIMER1 MCR: MR2R Position */ #define TIMER1_MCR_MR2R_Msk (0x01UL << TIMER1_MCR_MR2R_Pos) /*!< TIMER1 MCR: MR2R Mask */ #define TIMER1_MCR_MR2S_Pos 8 /*!< TIMER1 MCR: MR2S Position */ #define TIMER1_MCR_MR2S_Msk (0x01UL << TIMER1_MCR_MR2S_Pos) /*!< TIMER1 MCR: MR2S Mask */ #define TIMER1_MCR_MR3I_Pos 9 /*!< TIMER1 MCR: MR3I Position */ #define TIMER1_MCR_MR3I_Msk (0x01UL << TIMER1_MCR_MR3I_Pos) /*!< TIMER1 MCR: MR3I Mask */ #define TIMER1_MCR_MR3R_Pos 10 /*!< TIMER1 MCR: MR3R Position */ #define TIMER1_MCR_MR3R_Msk (0x01UL << TIMER1_MCR_MR3R_Pos) /*!< TIMER1 MCR: MR3R Mask */ #define TIMER1_MCR_MR3S_Pos 11 /*!< TIMER1 MCR: MR3S Position */ #define TIMER1_MCR_MR3S_Msk (0x01UL << TIMER1_MCR_MR3S_Pos) /*!< TIMER1 MCR: MR3S Mask */ /* --------------------------------- TIMER1_MR0 --------------------------------- */ #define TIMER1_MR0_MATCH_Pos 0 /*!< TIMER1 MR0: MATCH Position */ #define TIMER1_MR0_MATCH_Msk (0xffffffffUL << TIMER1_MR0_MATCH_Pos) /*!< TIMER1 MR0: MATCH Mask */ /* --------------------------------- TIMER1_MR1 --------------------------------- */ #define TIMER1_MR1_MATCH_Pos 0 /*!< TIMER1 MR1: MATCH Position */ #define TIMER1_MR1_MATCH_Msk (0xffffffffUL << TIMER1_MR1_MATCH_Pos) /*!< TIMER1 MR1: MATCH Mask */ /* --------------------------------- TIMER1_MR2 --------------------------------- */ #define TIMER1_MR2_MATCH_Pos 0 /*!< TIMER1 MR2: MATCH Position */ #define TIMER1_MR2_MATCH_Msk (0xffffffffUL << TIMER1_MR2_MATCH_Pos) /*!< TIMER1 MR2: MATCH Mask */ /* --------------------------------- TIMER1_MR3 --------------------------------- */ #define TIMER1_MR3_MATCH_Pos 0 /*!< TIMER1 MR3: MATCH Position */ #define TIMER1_MR3_MATCH_Msk (0xffffffffUL << TIMER1_MR3_MATCH_Pos) /*!< TIMER1 MR3: MATCH Mask */ /* --------------------------------- TIMER1_CCR --------------------------------- */ #define TIMER1_CCR_CAP0RE_Pos 0 /*!< TIMER1 CCR: CAP0RE Position */ #define TIMER1_CCR_CAP0RE_Msk (0x01UL << TIMER1_CCR_CAP0RE_Pos) /*!< TIMER1 CCR: CAP0RE Mask */ #define TIMER1_CCR_CAP0FE_Pos 1 /*!< TIMER1 CCR: CAP0FE Position */ #define TIMER1_CCR_CAP0FE_Msk (0x01UL << TIMER1_CCR_CAP0FE_Pos) /*!< TIMER1 CCR: CAP0FE Mask */ #define TIMER1_CCR_CAP0I_Pos 2 /*!< TIMER1 CCR: CAP0I Position */ #define TIMER1_CCR_CAP0I_Msk (0x01UL << TIMER1_CCR_CAP0I_Pos) /*!< TIMER1 CCR: CAP0I Mask */ #define TIMER1_CCR_CAP1RE_Pos 3 /*!< TIMER1 CCR: CAP1RE Position */ #define TIMER1_CCR_CAP1RE_Msk (0x01UL << TIMER1_CCR_CAP1RE_Pos) /*!< TIMER1 CCR: CAP1RE Mask */ #define TIMER1_CCR_CAP1FE_Pos 4 /*!< TIMER1 CCR: CAP1FE Position */ #define TIMER1_CCR_CAP1FE_Msk (0x01UL << TIMER1_CCR_CAP1FE_Pos) /*!< TIMER1 CCR: CAP1FE Mask */ #define TIMER1_CCR_CAP1I_Pos 5 /*!< TIMER1 CCR: CAP1I Position */ #define TIMER1_CCR_CAP1I_Msk (0x01UL << TIMER1_CCR_CAP1I_Pos) /*!< TIMER1 CCR: CAP1I Mask */ #define TIMER1_CCR_CAP2RE_Pos 6 /*!< TIMER1 CCR: CAP2RE Position */ #define TIMER1_CCR_CAP2RE_Msk (0x01UL << TIMER1_CCR_CAP2RE_Pos) /*!< TIMER1 CCR: CAP2RE Mask */ #define TIMER1_CCR_CAP2FE_Pos 7 /*!< TIMER1 CCR: CAP2FE Position */ #define TIMER1_CCR_CAP2FE_Msk (0x01UL << TIMER1_CCR_CAP2FE_Pos) /*!< TIMER1 CCR: CAP2FE Mask */ #define TIMER1_CCR_CAP2I_Pos 8 /*!< TIMER1 CCR: CAP2I Position */ #define TIMER1_CCR_CAP2I_Msk (0x01UL << TIMER1_CCR_CAP2I_Pos) /*!< TIMER1 CCR: CAP2I Mask */ #define TIMER1_CCR_CAP3RE_Pos 9 /*!< TIMER1 CCR: CAP3RE Position */ #define TIMER1_CCR_CAP3RE_Msk (0x01UL << TIMER1_CCR_CAP3RE_Pos) /*!< TIMER1 CCR: CAP3RE Mask */ #define TIMER1_CCR_CAP3FE_Pos 10 /*!< TIMER1 CCR: CAP3FE Position */ #define TIMER1_CCR_CAP3FE_Msk (0x01UL << TIMER1_CCR_CAP3FE_Pos) /*!< TIMER1 CCR: CAP3FE Mask */ #define TIMER1_CCR_CAP3I_Pos 11 /*!< TIMER1 CCR: CAP3I Position */ #define TIMER1_CCR_CAP3I_Msk (0x01UL << TIMER1_CCR_CAP3I_Pos) /*!< TIMER1 CCR: CAP3I Mask */ /* --------------------------------- TIMER1_CR0 --------------------------------- */ #define TIMER1_CR0_CAP_Pos 0 /*!< TIMER1 CR0: CAP Position */ #define TIMER1_CR0_CAP_Msk (0xffffffffUL << TIMER1_CR0_CAP_Pos) /*!< TIMER1 CR0: CAP Mask */ /* --------------------------------- TIMER1_CR1 --------------------------------- */ #define TIMER1_CR1_CAP_Pos 0 /*!< TIMER1 CR1: CAP Position */ #define TIMER1_CR1_CAP_Msk (0xffffffffUL << TIMER1_CR1_CAP_Pos) /*!< TIMER1 CR1: CAP Mask */ /* --------------------------------- TIMER1_CR2 --------------------------------- */ #define TIMER1_CR2_CAP_Pos 0 /*!< TIMER1 CR2: CAP Position */ #define TIMER1_CR2_CAP_Msk (0xffffffffUL << TIMER1_CR2_CAP_Pos) /*!< TIMER1 CR2: CAP Mask */ /* --------------------------------- TIMER1_CR3 --------------------------------- */ #define TIMER1_CR3_CAP_Pos 0 /*!< TIMER1 CR3: CAP Position */ #define TIMER1_CR3_CAP_Msk (0xffffffffUL << TIMER1_CR3_CAP_Pos) /*!< TIMER1 CR3: CAP Mask */ /* --------------------------------- TIMER1_EMR --------------------------------- */ #define TIMER1_EMR_EM0_Pos 0 /*!< TIMER1 EMR: EM0 Position */ #define TIMER1_EMR_EM0_Msk (0x01UL << TIMER1_EMR_EM0_Pos) /*!< TIMER1 EMR: EM0 Mask */ #define TIMER1_EMR_EM1_Pos 1 /*!< TIMER1 EMR: EM1 Position */ #define TIMER1_EMR_EM1_Msk (0x01UL << TIMER1_EMR_EM1_Pos) /*!< TIMER1 EMR: EM1 Mask */ #define TIMER1_EMR_EM2_Pos 2 /*!< TIMER1 EMR: EM2 Position */ #define TIMER1_EMR_EM2_Msk (0x01UL << TIMER1_EMR_EM2_Pos) /*!< TIMER1 EMR: EM2 Mask */ #define TIMER1_EMR_EM3_Pos 3 /*!< TIMER1 EMR: EM3 Position */ #define TIMER1_EMR_EM3_Msk (0x01UL << TIMER1_EMR_EM3_Pos) /*!< TIMER1 EMR: EM3 Mask */ #define TIMER1_EMR_EMC0_Pos 4 /*!< TIMER1 EMR: EMC0 Position */ #define TIMER1_EMR_EMC0_Msk (0x03UL << TIMER1_EMR_EMC0_Pos) /*!< TIMER1 EMR: EMC0 Mask */ #define TIMER1_EMR_EMC1_Pos 6 /*!< TIMER1 EMR: EMC1 Position */ #define TIMER1_EMR_EMC1_Msk (0x03UL << TIMER1_EMR_EMC1_Pos) /*!< TIMER1 EMR: EMC1 Mask */ #define TIMER1_EMR_EMC2_Pos 8 /*!< TIMER1 EMR: EMC2 Position */ #define TIMER1_EMR_EMC2_Msk (0x03UL << TIMER1_EMR_EMC2_Pos) /*!< TIMER1 EMR: EMC2 Mask */ #define TIMER1_EMR_EMC3_Pos 10 /*!< TIMER1 EMR: EMC3 Position */ #define TIMER1_EMR_EMC3_Msk (0x03UL << TIMER1_EMR_EMC3_Pos) /*!< TIMER1 EMR: EMC3 Mask */ /* --------------------------------- TIMER1_CTCR -------------------------------- */ #define TIMER1_CTCR_CTMODE_Pos 0 /*!< TIMER1 CTCR: CTMODE Position */ #define TIMER1_CTCR_CTMODE_Msk (0x03UL << TIMER1_CTCR_CTMODE_Pos) /*!< TIMER1 CTCR: CTMODE Mask */ #define TIMER1_CTCR_CINSEL_Pos 2 /*!< TIMER1 CTCR: CINSEL Position */ #define TIMER1_CTCR_CINSEL_Msk (0x03UL << TIMER1_CTCR_CINSEL_Pos) /*!< TIMER1 CTCR: CINSEL Mask */ /* ================================================================================ */ /* ================ struct 'TIMER2' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- TIMER2_IR --------------------------------- */ #define TIMER2_IR_MR0INT_Pos 0 /*!< TIMER2 IR: MR0INT Position */ #define TIMER2_IR_MR0INT_Msk (0x01UL << TIMER2_IR_MR0INT_Pos) /*!< TIMER2 IR: MR0INT Mask */ #define TIMER2_IR_MR1INT_Pos 1 /*!< TIMER2 IR: MR1INT Position */ #define TIMER2_IR_MR1INT_Msk (0x01UL << TIMER2_IR_MR1INT_Pos) /*!< TIMER2 IR: MR1INT Mask */ #define TIMER2_IR_MR2INT_Pos 2 /*!< TIMER2 IR: MR2INT Position */ #define TIMER2_IR_MR2INT_Msk (0x01UL << TIMER2_IR_MR2INT_Pos) /*!< TIMER2 IR: MR2INT Mask */ #define TIMER2_IR_MR3INT_Pos 3 /*!< TIMER2 IR: MR3INT Position */ #define TIMER2_IR_MR3INT_Msk (0x01UL << TIMER2_IR_MR3INT_Pos) /*!< TIMER2 IR: MR3INT Mask */ #define TIMER2_IR_CR0INT_Pos 4 /*!< TIMER2 IR: CR0INT Position */ #define TIMER2_IR_CR0INT_Msk (0x01UL << TIMER2_IR_CR0INT_Pos) /*!< TIMER2 IR: CR0INT Mask */ #define TIMER2_IR_CR1INT_Pos 5 /*!< TIMER2 IR: CR1INT Position */ #define TIMER2_IR_CR1INT_Msk (0x01UL << TIMER2_IR_CR1INT_Pos) /*!< TIMER2 IR: CR1INT Mask */ #define TIMER2_IR_CR2INT_Pos 6 /*!< TIMER2 IR: CR2INT Position */ #define TIMER2_IR_CR2INT_Msk (0x01UL << TIMER2_IR_CR2INT_Pos) /*!< TIMER2 IR: CR2INT Mask */ #define TIMER2_IR_CR3INT_Pos 7 /*!< TIMER2 IR: CR3INT Position */ #define TIMER2_IR_CR3INT_Msk (0x01UL << TIMER2_IR_CR3INT_Pos) /*!< TIMER2 IR: CR3INT Mask */ /* --------------------------------- TIMER2_TCR --------------------------------- */ #define TIMER2_TCR_CEN_Pos 0 /*!< TIMER2 TCR: CEN Position */ #define TIMER2_TCR_CEN_Msk (0x01UL << TIMER2_TCR_CEN_Pos) /*!< TIMER2 TCR: CEN Mask */ #define TIMER2_TCR_CRST_Pos 1 /*!< TIMER2 TCR: CRST Position */ #define TIMER2_TCR_CRST_Msk (0x01UL << TIMER2_TCR_CRST_Pos) /*!< TIMER2 TCR: CRST Mask */ /* ---------------------------------- TIMER2_TC --------------------------------- */ #define TIMER2_TC_TC_Pos 0 /*!< TIMER2 TC: TC Position */ #define TIMER2_TC_TC_Msk (0xffffffffUL << TIMER2_TC_TC_Pos) /*!< TIMER2 TC: TC Mask */ /* ---------------------------------- TIMER2_PR --------------------------------- */ #define TIMER2_PR_PM_Pos 0 /*!< TIMER2 PR: PM Position */ #define TIMER2_PR_PM_Msk (0xffffffffUL << TIMER2_PR_PM_Pos) /*!< TIMER2 PR: PM Mask */ /* ---------------------------------- TIMER2_PC --------------------------------- */ #define TIMER2_PC_PC_Pos 0 /*!< TIMER2 PC: PC Position */ #define TIMER2_PC_PC_Msk (0xffffffffUL << TIMER2_PC_PC_Pos) /*!< TIMER2 PC: PC Mask */ /* --------------------------------- TIMER2_MCR --------------------------------- */ #define TIMER2_MCR_MR0I_Pos 0 /*!< TIMER2 MCR: MR0I Position */ #define TIMER2_MCR_MR0I_Msk (0x01UL << TIMER2_MCR_MR0I_Pos) /*!< TIMER2 MCR: MR0I Mask */ #define TIMER2_MCR_MR0R_Pos 1 /*!< TIMER2 MCR: MR0R Position */ #define TIMER2_MCR_MR0R_Msk (0x01UL << TIMER2_MCR_MR0R_Pos) /*!< TIMER2 MCR: MR0R Mask */ #define TIMER2_MCR_MR0S_Pos 2 /*!< TIMER2 MCR: MR0S Position */ #define TIMER2_MCR_MR0S_Msk (0x01UL << TIMER2_MCR_MR0S_Pos) /*!< TIMER2 MCR: MR0S Mask */ #define TIMER2_MCR_MR1I_Pos 3 /*!< TIMER2 MCR: MR1I Position */ #define TIMER2_MCR_MR1I_Msk (0x01UL << TIMER2_MCR_MR1I_Pos) /*!< TIMER2 MCR: MR1I Mask */ #define TIMER2_MCR_MR1R_Pos 4 /*!< TIMER2 MCR: MR1R Position */ #define TIMER2_MCR_MR1R_Msk (0x01UL << TIMER2_MCR_MR1R_Pos) /*!< TIMER2 MCR: MR1R Mask */ #define TIMER2_MCR_MR1S_Pos 5 /*!< TIMER2 MCR: MR1S Position */ #define TIMER2_MCR_MR1S_Msk (0x01UL << TIMER2_MCR_MR1S_Pos) /*!< TIMER2 MCR: MR1S Mask */ #define TIMER2_MCR_MR2I_Pos 6 /*!< TIMER2 MCR: MR2I Position */ #define TIMER2_MCR_MR2I_Msk (0x01UL << TIMER2_MCR_MR2I_Pos) /*!< TIMER2 MCR: MR2I Mask */ #define TIMER2_MCR_MR2R_Pos 7 /*!< TIMER2 MCR: MR2R Position */ #define TIMER2_MCR_MR2R_Msk (0x01UL << TIMER2_MCR_MR2R_Pos) /*!< TIMER2 MCR: MR2R Mask */ #define TIMER2_MCR_MR2S_Pos 8 /*!< TIMER2 MCR: MR2S Position */ #define TIMER2_MCR_MR2S_Msk (0x01UL << TIMER2_MCR_MR2S_Pos) /*!< TIMER2 MCR: MR2S Mask */ #define TIMER2_MCR_MR3I_Pos 9 /*!< TIMER2 MCR: MR3I Position */ #define TIMER2_MCR_MR3I_Msk (0x01UL << TIMER2_MCR_MR3I_Pos) /*!< TIMER2 MCR: MR3I Mask */ #define TIMER2_MCR_MR3R_Pos 10 /*!< TIMER2 MCR: MR3R Position */ #define TIMER2_MCR_MR3R_Msk (0x01UL << TIMER2_MCR_MR3R_Pos) /*!< TIMER2 MCR: MR3R Mask */ #define TIMER2_MCR_MR3S_Pos 11 /*!< TIMER2 MCR: MR3S Position */ #define TIMER2_MCR_MR3S_Msk (0x01UL << TIMER2_MCR_MR3S_Pos) /*!< TIMER2 MCR: MR3S Mask */ /* --------------------------------- TIMER2_MR0 --------------------------------- */ #define TIMER2_MR0_MATCH_Pos 0 /*!< TIMER2 MR0: MATCH Position */ #define TIMER2_MR0_MATCH_Msk (0xffffffffUL << TIMER2_MR0_MATCH_Pos) /*!< TIMER2 MR0: MATCH Mask */ /* --------------------------------- TIMER2_MR1 --------------------------------- */ #define TIMER2_MR1_MATCH_Pos 0 /*!< TIMER2 MR1: MATCH Position */ #define TIMER2_MR1_MATCH_Msk (0xffffffffUL << TIMER2_MR1_MATCH_Pos) /*!< TIMER2 MR1: MATCH Mask */ /* --------------------------------- TIMER2_MR2 --------------------------------- */ #define TIMER2_MR2_MATCH_Pos 0 /*!< TIMER2 MR2: MATCH Position */ #define TIMER2_MR2_MATCH_Msk (0xffffffffUL << TIMER2_MR2_MATCH_Pos) /*!< TIMER2 MR2: MATCH Mask */ /* --------------------------------- TIMER2_MR3 --------------------------------- */ #define TIMER2_MR3_MATCH_Pos 0 /*!< TIMER2 MR3: MATCH Position */ #define TIMER2_MR3_MATCH_Msk (0xffffffffUL << TIMER2_MR3_MATCH_Pos) /*!< TIMER2 MR3: MATCH Mask */ /* --------------------------------- TIMER2_CCR --------------------------------- */ #define TIMER2_CCR_CAP0RE_Pos 0 /*!< TIMER2 CCR: CAP0RE Position */ #define TIMER2_CCR_CAP0RE_Msk (0x01UL << TIMER2_CCR_CAP0RE_Pos) /*!< TIMER2 CCR: CAP0RE Mask */ #define TIMER2_CCR_CAP0FE_Pos 1 /*!< TIMER2 CCR: CAP0FE Position */ #define TIMER2_CCR_CAP0FE_Msk (0x01UL << TIMER2_CCR_CAP0FE_Pos) /*!< TIMER2 CCR: CAP0FE Mask */ #define TIMER2_CCR_CAP0I_Pos 2 /*!< TIMER2 CCR: CAP0I Position */ #define TIMER2_CCR_CAP0I_Msk (0x01UL << TIMER2_CCR_CAP0I_Pos) /*!< TIMER2 CCR: CAP0I Mask */ #define TIMER2_CCR_CAP1RE_Pos 3 /*!< TIMER2 CCR: CAP1RE Position */ #define TIMER2_CCR_CAP1RE_Msk (0x01UL << TIMER2_CCR_CAP1RE_Pos) /*!< TIMER2 CCR: CAP1RE Mask */ #define TIMER2_CCR_CAP1FE_Pos 4 /*!< TIMER2 CCR: CAP1FE Position */ #define TIMER2_CCR_CAP1FE_Msk (0x01UL << TIMER2_CCR_CAP1FE_Pos) /*!< TIMER2 CCR: CAP1FE Mask */ #define TIMER2_CCR_CAP1I_Pos 5 /*!< TIMER2 CCR: CAP1I Position */ #define TIMER2_CCR_CAP1I_Msk (0x01UL << TIMER2_CCR_CAP1I_Pos) /*!< TIMER2 CCR: CAP1I Mask */ #define TIMER2_CCR_CAP2RE_Pos 6 /*!< TIMER2 CCR: CAP2RE Position */ #define TIMER2_CCR_CAP2RE_Msk (0x01UL << TIMER2_CCR_CAP2RE_Pos) /*!< TIMER2 CCR: CAP2RE Mask */ #define TIMER2_CCR_CAP2FE_Pos 7 /*!< TIMER2 CCR: CAP2FE Position */ #define TIMER2_CCR_CAP2FE_Msk (0x01UL << TIMER2_CCR_CAP2FE_Pos) /*!< TIMER2 CCR: CAP2FE Mask */ #define TIMER2_CCR_CAP2I_Pos 8 /*!< TIMER2 CCR: CAP2I Position */ #define TIMER2_CCR_CAP2I_Msk (0x01UL << TIMER2_CCR_CAP2I_Pos) /*!< TIMER2 CCR: CAP2I Mask */ #define TIMER2_CCR_CAP3RE_Pos 9 /*!< TIMER2 CCR: CAP3RE Position */ #define TIMER2_CCR_CAP3RE_Msk (0x01UL << TIMER2_CCR_CAP3RE_Pos) /*!< TIMER2 CCR: CAP3RE Mask */ #define TIMER2_CCR_CAP3FE_Pos 10 /*!< TIMER2 CCR: CAP3FE Position */ #define TIMER2_CCR_CAP3FE_Msk (0x01UL << TIMER2_CCR_CAP3FE_Pos) /*!< TIMER2 CCR: CAP3FE Mask */ #define TIMER2_CCR_CAP3I_Pos 11 /*!< TIMER2 CCR: CAP3I Position */ #define TIMER2_CCR_CAP3I_Msk (0x01UL << TIMER2_CCR_CAP3I_Pos) /*!< TIMER2 CCR: CAP3I Mask */ /* --------------------------------- TIMER2_CR0 --------------------------------- */ #define TIMER2_CR0_CAP_Pos 0 /*!< TIMER2 CR0: CAP Position */ #define TIMER2_CR0_CAP_Msk (0xffffffffUL << TIMER2_CR0_CAP_Pos) /*!< TIMER2 CR0: CAP Mask */ /* --------------------------------- TIMER2_CR1 --------------------------------- */ #define TIMER2_CR1_CAP_Pos 0 /*!< TIMER2 CR1: CAP Position */ #define TIMER2_CR1_CAP_Msk (0xffffffffUL << TIMER2_CR1_CAP_Pos) /*!< TIMER2 CR1: CAP Mask */ /* --------------------------------- TIMER2_CR2 --------------------------------- */ #define TIMER2_CR2_CAP_Pos 0 /*!< TIMER2 CR2: CAP Position */ #define TIMER2_CR2_CAP_Msk (0xffffffffUL << TIMER2_CR2_CAP_Pos) /*!< TIMER2 CR2: CAP Mask */ /* --------------------------------- TIMER2_CR3 --------------------------------- */ #define TIMER2_CR3_CAP_Pos 0 /*!< TIMER2 CR3: CAP Position */ #define TIMER2_CR3_CAP_Msk (0xffffffffUL << TIMER2_CR3_CAP_Pos) /*!< TIMER2 CR3: CAP Mask */ /* --------------------------------- TIMER2_EMR --------------------------------- */ #define TIMER2_EMR_EM0_Pos 0 /*!< TIMER2 EMR: EM0 Position */ #define TIMER2_EMR_EM0_Msk (0x01UL << TIMER2_EMR_EM0_Pos) /*!< TIMER2 EMR: EM0 Mask */ #define TIMER2_EMR_EM1_Pos 1 /*!< TIMER2 EMR: EM1 Position */ #define TIMER2_EMR_EM1_Msk (0x01UL << TIMER2_EMR_EM1_Pos) /*!< TIMER2 EMR: EM1 Mask */ #define TIMER2_EMR_EM2_Pos 2 /*!< TIMER2 EMR: EM2 Position */ #define TIMER2_EMR_EM2_Msk (0x01UL << TIMER2_EMR_EM2_Pos) /*!< TIMER2 EMR: EM2 Mask */ #define TIMER2_EMR_EM3_Pos 3 /*!< TIMER2 EMR: EM3 Position */ #define TIMER2_EMR_EM3_Msk (0x01UL << TIMER2_EMR_EM3_Pos) /*!< TIMER2 EMR: EM3 Mask */ #define TIMER2_EMR_EMC0_Pos 4 /*!< TIMER2 EMR: EMC0 Position */ #define TIMER2_EMR_EMC0_Msk (0x03UL << TIMER2_EMR_EMC0_Pos) /*!< TIMER2 EMR: EMC0 Mask */ #define TIMER2_EMR_EMC1_Pos 6 /*!< TIMER2 EMR: EMC1 Position */ #define TIMER2_EMR_EMC1_Msk (0x03UL << TIMER2_EMR_EMC1_Pos) /*!< TIMER2 EMR: EMC1 Mask */ #define TIMER2_EMR_EMC2_Pos 8 /*!< TIMER2 EMR: EMC2 Position */ #define TIMER2_EMR_EMC2_Msk (0x03UL << TIMER2_EMR_EMC2_Pos) /*!< TIMER2 EMR: EMC2 Mask */ #define TIMER2_EMR_EMC3_Pos 10 /*!< TIMER2 EMR: EMC3 Position */ #define TIMER2_EMR_EMC3_Msk (0x03UL << TIMER2_EMR_EMC3_Pos) /*!< TIMER2 EMR: EMC3 Mask */ /* --------------------------------- TIMER2_CTCR -------------------------------- */ #define TIMER2_CTCR_CTMODE_Pos 0 /*!< TIMER2 CTCR: CTMODE Position */ #define TIMER2_CTCR_CTMODE_Msk (0x03UL << TIMER2_CTCR_CTMODE_Pos) /*!< TIMER2 CTCR: CTMODE Mask */ #define TIMER2_CTCR_CINSEL_Pos 2 /*!< TIMER2 CTCR: CINSEL Position */ #define TIMER2_CTCR_CINSEL_Msk (0x03UL << TIMER2_CTCR_CINSEL_Pos) /*!< TIMER2 CTCR: CINSEL Mask */ /* ================================================================================ */ /* ================ struct 'TIMER3' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- TIMER3_IR --------------------------------- */ #define TIMER3_IR_MR0INT_Pos 0 /*!< TIMER3 IR: MR0INT Position */ #define TIMER3_IR_MR0INT_Msk (0x01UL << TIMER3_IR_MR0INT_Pos) /*!< TIMER3 IR: MR0INT Mask */ #define TIMER3_IR_MR1INT_Pos 1 /*!< TIMER3 IR: MR1INT Position */ #define TIMER3_IR_MR1INT_Msk (0x01UL << TIMER3_IR_MR1INT_Pos) /*!< TIMER3 IR: MR1INT Mask */ #define TIMER3_IR_MR2INT_Pos 2 /*!< TIMER3 IR: MR2INT Position */ #define TIMER3_IR_MR2INT_Msk (0x01UL << TIMER3_IR_MR2INT_Pos) /*!< TIMER3 IR: MR2INT Mask */ #define TIMER3_IR_MR3INT_Pos 3 /*!< TIMER3 IR: MR3INT Position */ #define TIMER3_IR_MR3INT_Msk (0x01UL << TIMER3_IR_MR3INT_Pos) /*!< TIMER3 IR: MR3INT Mask */ #define TIMER3_IR_CR0INT_Pos 4 /*!< TIMER3 IR: CR0INT Position */ #define TIMER3_IR_CR0INT_Msk (0x01UL << TIMER3_IR_CR0INT_Pos) /*!< TIMER3 IR: CR0INT Mask */ #define TIMER3_IR_CR1INT_Pos 5 /*!< TIMER3 IR: CR1INT Position */ #define TIMER3_IR_CR1INT_Msk (0x01UL << TIMER3_IR_CR1INT_Pos) /*!< TIMER3 IR: CR1INT Mask */ #define TIMER3_IR_CR2INT_Pos 6 /*!< TIMER3 IR: CR2INT Position */ #define TIMER3_IR_CR2INT_Msk (0x01UL << TIMER3_IR_CR2INT_Pos) /*!< TIMER3 IR: CR2INT Mask */ #define TIMER3_IR_CR3INT_Pos 7 /*!< TIMER3 IR: CR3INT Position */ #define TIMER3_IR_CR3INT_Msk (0x01UL << TIMER3_IR_CR3INT_Pos) /*!< TIMER3 IR: CR3INT Mask */ /* --------------------------------- TIMER3_TCR --------------------------------- */ #define TIMER3_TCR_CEN_Pos 0 /*!< TIMER3 TCR: CEN Position */ #define TIMER3_TCR_CEN_Msk (0x01UL << TIMER3_TCR_CEN_Pos) /*!< TIMER3 TCR: CEN Mask */ #define TIMER3_TCR_CRST_Pos 1 /*!< TIMER3 TCR: CRST Position */ #define TIMER3_TCR_CRST_Msk (0x01UL << TIMER3_TCR_CRST_Pos) /*!< TIMER3 TCR: CRST Mask */ /* ---------------------------------- TIMER3_TC --------------------------------- */ #define TIMER3_TC_TC_Pos 0 /*!< TIMER3 TC: TC Position */ #define TIMER3_TC_TC_Msk (0xffffffffUL << TIMER3_TC_TC_Pos) /*!< TIMER3 TC: TC Mask */ /* ---------------------------------- TIMER3_PR --------------------------------- */ #define TIMER3_PR_PM_Pos 0 /*!< TIMER3 PR: PM Position */ #define TIMER3_PR_PM_Msk (0xffffffffUL << TIMER3_PR_PM_Pos) /*!< TIMER3 PR: PM Mask */ /* ---------------------------------- TIMER3_PC --------------------------------- */ #define TIMER3_PC_PC_Pos 0 /*!< TIMER3 PC: PC Position */ #define TIMER3_PC_PC_Msk (0xffffffffUL << TIMER3_PC_PC_Pos) /*!< TIMER3 PC: PC Mask */ /* --------------------------------- TIMER3_MCR --------------------------------- */ #define TIMER3_MCR_MR0I_Pos 0 /*!< TIMER3 MCR: MR0I Position */ #define TIMER3_MCR_MR0I_Msk (0x01UL << TIMER3_MCR_MR0I_Pos) /*!< TIMER3 MCR: MR0I Mask */ #define TIMER3_MCR_MR0R_Pos 1 /*!< TIMER3 MCR: MR0R Position */ #define TIMER3_MCR_MR0R_Msk (0x01UL << TIMER3_MCR_MR0R_Pos) /*!< TIMER3 MCR: MR0R Mask */ #define TIMER3_MCR_MR0S_Pos 2 /*!< TIMER3 MCR: MR0S Position */ #define TIMER3_MCR_MR0S_Msk (0x01UL << TIMER3_MCR_MR0S_Pos) /*!< TIMER3 MCR: MR0S Mask */ #define TIMER3_MCR_MR1I_Pos 3 /*!< TIMER3 MCR: MR1I Position */ #define TIMER3_MCR_MR1I_Msk (0x01UL << TIMER3_MCR_MR1I_Pos) /*!< TIMER3 MCR: MR1I Mask */ #define TIMER3_MCR_MR1R_Pos 4 /*!< TIMER3 MCR: MR1R Position */ #define TIMER3_MCR_MR1R_Msk (0x01UL << TIMER3_MCR_MR1R_Pos) /*!< TIMER3 MCR: MR1R Mask */ #define TIMER3_MCR_MR1S_Pos 5 /*!< TIMER3 MCR: MR1S Position */ #define TIMER3_MCR_MR1S_Msk (0x01UL << TIMER3_MCR_MR1S_Pos) /*!< TIMER3 MCR: MR1S Mask */ #define TIMER3_MCR_MR2I_Pos 6 /*!< TIMER3 MCR: MR2I Position */ #define TIMER3_MCR_MR2I_Msk (0x01UL << TIMER3_MCR_MR2I_Pos) /*!< TIMER3 MCR: MR2I Mask */ #define TIMER3_MCR_MR2R_Pos 7 /*!< TIMER3 MCR: MR2R Position */ #define TIMER3_MCR_MR2R_Msk (0x01UL << TIMER3_MCR_MR2R_Pos) /*!< TIMER3 MCR: MR2R Mask */ #define TIMER3_MCR_MR2S_Pos 8 /*!< TIMER3 MCR: MR2S Position */ #define TIMER3_MCR_MR2S_Msk (0x01UL << TIMER3_MCR_MR2S_Pos) /*!< TIMER3 MCR: MR2S Mask */ #define TIMER3_MCR_MR3I_Pos 9 /*!< TIMER3 MCR: MR3I Position */ #define TIMER3_MCR_MR3I_Msk (0x01UL << TIMER3_MCR_MR3I_Pos) /*!< TIMER3 MCR: MR3I Mask */ #define TIMER3_MCR_MR3R_Pos 10 /*!< TIMER3 MCR: MR3R Position */ #define TIMER3_MCR_MR3R_Msk (0x01UL << TIMER3_MCR_MR3R_Pos) /*!< TIMER3 MCR: MR3R Mask */ #define TIMER3_MCR_MR3S_Pos 11 /*!< TIMER3 MCR: MR3S Position */ #define TIMER3_MCR_MR3S_Msk (0x01UL << TIMER3_MCR_MR3S_Pos) /*!< TIMER3 MCR: MR3S Mask */ /* --------------------------------- TIMER3_MR0 --------------------------------- */ #define TIMER3_MR0_MATCH_Pos 0 /*!< TIMER3 MR0: MATCH Position */ #define TIMER3_MR0_MATCH_Msk (0xffffffffUL << TIMER3_MR0_MATCH_Pos) /*!< TIMER3 MR0: MATCH Mask */ /* --------------------------------- TIMER3_MR1 --------------------------------- */ #define TIMER3_MR1_MATCH_Pos 0 /*!< TIMER3 MR1: MATCH Position */ #define TIMER3_MR1_MATCH_Msk (0xffffffffUL << TIMER3_MR1_MATCH_Pos) /*!< TIMER3 MR1: MATCH Mask */ /* --------------------------------- TIMER3_MR2 --------------------------------- */ #define TIMER3_MR2_MATCH_Pos 0 /*!< TIMER3 MR2: MATCH Position */ #define TIMER3_MR2_MATCH_Msk (0xffffffffUL << TIMER3_MR2_MATCH_Pos) /*!< TIMER3 MR2: MATCH Mask */ /* --------------------------------- TIMER3_MR3 --------------------------------- */ #define TIMER3_MR3_MATCH_Pos 0 /*!< TIMER3 MR3: MATCH Position */ #define TIMER3_MR3_MATCH_Msk (0xffffffffUL << TIMER3_MR3_MATCH_Pos) /*!< TIMER3 MR3: MATCH Mask */ /* --------------------------------- TIMER3_CCR --------------------------------- */ #define TIMER3_CCR_CAP0RE_Pos 0 /*!< TIMER3 CCR: CAP0RE Position */ #define TIMER3_CCR_CAP0RE_Msk (0x01UL << TIMER3_CCR_CAP0RE_Pos) /*!< TIMER3 CCR: CAP0RE Mask */ #define TIMER3_CCR_CAP0FE_Pos 1 /*!< TIMER3 CCR: CAP0FE Position */ #define TIMER3_CCR_CAP0FE_Msk (0x01UL << TIMER3_CCR_CAP0FE_Pos) /*!< TIMER3 CCR: CAP0FE Mask */ #define TIMER3_CCR_CAP0I_Pos 2 /*!< TIMER3 CCR: CAP0I Position */ #define TIMER3_CCR_CAP0I_Msk (0x01UL << TIMER3_CCR_CAP0I_Pos) /*!< TIMER3 CCR: CAP0I Mask */ #define TIMER3_CCR_CAP1RE_Pos 3 /*!< TIMER3 CCR: CAP1RE Position */ #define TIMER3_CCR_CAP1RE_Msk (0x01UL << TIMER3_CCR_CAP1RE_Pos) /*!< TIMER3 CCR: CAP1RE Mask */ #define TIMER3_CCR_CAP1FE_Pos 4 /*!< TIMER3 CCR: CAP1FE Position */ #define TIMER3_CCR_CAP1FE_Msk (0x01UL << TIMER3_CCR_CAP1FE_Pos) /*!< TIMER3 CCR: CAP1FE Mask */ #define TIMER3_CCR_CAP1I_Pos 5 /*!< TIMER3 CCR: CAP1I Position */ #define TIMER3_CCR_CAP1I_Msk (0x01UL << TIMER3_CCR_CAP1I_Pos) /*!< TIMER3 CCR: CAP1I Mask */ #define TIMER3_CCR_CAP2RE_Pos 6 /*!< TIMER3 CCR: CAP2RE Position */ #define TIMER3_CCR_CAP2RE_Msk (0x01UL << TIMER3_CCR_CAP2RE_Pos) /*!< TIMER3 CCR: CAP2RE Mask */ #define TIMER3_CCR_CAP2FE_Pos 7 /*!< TIMER3 CCR: CAP2FE Position */ #define TIMER3_CCR_CAP2FE_Msk (0x01UL << TIMER3_CCR_CAP2FE_Pos) /*!< TIMER3 CCR: CAP2FE Mask */ #define TIMER3_CCR_CAP2I_Pos 8 /*!< TIMER3 CCR: CAP2I Position */ #define TIMER3_CCR_CAP2I_Msk (0x01UL << TIMER3_CCR_CAP2I_Pos) /*!< TIMER3 CCR: CAP2I Mask */ #define TIMER3_CCR_CAP3RE_Pos 9 /*!< TIMER3 CCR: CAP3RE Position */ #define TIMER3_CCR_CAP3RE_Msk (0x01UL << TIMER3_CCR_CAP3RE_Pos) /*!< TIMER3 CCR: CAP3RE Mask */ #define TIMER3_CCR_CAP3FE_Pos 10 /*!< TIMER3 CCR: CAP3FE Position */ #define TIMER3_CCR_CAP3FE_Msk (0x01UL << TIMER3_CCR_CAP3FE_Pos) /*!< TIMER3 CCR: CAP3FE Mask */ #define TIMER3_CCR_CAP3I_Pos 11 /*!< TIMER3 CCR: CAP3I Position */ #define TIMER3_CCR_CAP3I_Msk (0x01UL << TIMER3_CCR_CAP3I_Pos) /*!< TIMER3 CCR: CAP3I Mask */ /* --------------------------------- TIMER3_CR0 --------------------------------- */ #define TIMER3_CR0_CAP_Pos 0 /*!< TIMER3 CR0: CAP Position */ #define TIMER3_CR0_CAP_Msk (0xffffffffUL << TIMER3_CR0_CAP_Pos) /*!< TIMER3 CR0: CAP Mask */ /* --------------------------------- TIMER3_CR1 --------------------------------- */ #define TIMER3_CR1_CAP_Pos 0 /*!< TIMER3 CR1: CAP Position */ #define TIMER3_CR1_CAP_Msk (0xffffffffUL << TIMER3_CR1_CAP_Pos) /*!< TIMER3 CR1: CAP Mask */ /* --------------------------------- TIMER3_CR2 --------------------------------- */ #define TIMER3_CR2_CAP_Pos 0 /*!< TIMER3 CR2: CAP Position */ #define TIMER3_CR2_CAP_Msk (0xffffffffUL << TIMER3_CR2_CAP_Pos) /*!< TIMER3 CR2: CAP Mask */ /* --------------------------------- TIMER3_CR3 --------------------------------- */ #define TIMER3_CR3_CAP_Pos 0 /*!< TIMER3 CR3: CAP Position */ #define TIMER3_CR3_CAP_Msk (0xffffffffUL << TIMER3_CR3_CAP_Pos) /*!< TIMER3 CR3: CAP Mask */ /* --------------------------------- TIMER3_EMR --------------------------------- */ #define TIMER3_EMR_EM0_Pos 0 /*!< TIMER3 EMR: EM0 Position */ #define TIMER3_EMR_EM0_Msk (0x01UL << TIMER3_EMR_EM0_Pos) /*!< TIMER3 EMR: EM0 Mask */ #define TIMER3_EMR_EM1_Pos 1 /*!< TIMER3 EMR: EM1 Position */ #define TIMER3_EMR_EM1_Msk (0x01UL << TIMER3_EMR_EM1_Pos) /*!< TIMER3 EMR: EM1 Mask */ #define TIMER3_EMR_EM2_Pos 2 /*!< TIMER3 EMR: EM2 Position */ #define TIMER3_EMR_EM2_Msk (0x01UL << TIMER3_EMR_EM2_Pos) /*!< TIMER3 EMR: EM2 Mask */ #define TIMER3_EMR_EM3_Pos 3 /*!< TIMER3 EMR: EM3 Position */ #define TIMER3_EMR_EM3_Msk (0x01UL << TIMER3_EMR_EM3_Pos) /*!< TIMER3 EMR: EM3 Mask */ #define TIMER3_EMR_EMC0_Pos 4 /*!< TIMER3 EMR: EMC0 Position */ #define TIMER3_EMR_EMC0_Msk (0x03UL << TIMER3_EMR_EMC0_Pos) /*!< TIMER3 EMR: EMC0 Mask */ #define TIMER3_EMR_EMC1_Pos 6 /*!< TIMER3 EMR: EMC1 Position */ #define TIMER3_EMR_EMC1_Msk (0x03UL << TIMER3_EMR_EMC1_Pos) /*!< TIMER3 EMR: EMC1 Mask */ #define TIMER3_EMR_EMC2_Pos 8 /*!< TIMER3 EMR: EMC2 Position */ #define TIMER3_EMR_EMC2_Msk (0x03UL << TIMER3_EMR_EMC2_Pos) /*!< TIMER3 EMR: EMC2 Mask */ #define TIMER3_EMR_EMC3_Pos 10 /*!< TIMER3 EMR: EMC3 Position */ #define TIMER3_EMR_EMC3_Msk (0x03UL << TIMER3_EMR_EMC3_Pos) /*!< TIMER3 EMR: EMC3 Mask */ /* --------------------------------- TIMER3_CTCR -------------------------------- */ #define TIMER3_CTCR_CTMODE_Pos 0 /*!< TIMER3 CTCR: CTMODE Position */ #define TIMER3_CTCR_CTMODE_Msk (0x03UL << TIMER3_CTCR_CTMODE_Pos) /*!< TIMER3 CTCR: CTMODE Mask */ #define TIMER3_CTCR_CINSEL_Pos 2 /*!< TIMER3 CTCR: CINSEL Position */ #define TIMER3_CTCR_CINSEL_Msk (0x03UL << TIMER3_CTCR_CINSEL_Pos) /*!< TIMER3 CTCR: CINSEL Mask */ /* ================================================================================ */ /* ================ struct 'SCU' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- SCU_SFSP0_0 -------------------------------- */ #define SCU_SFSP0_0_MODE_Pos 0 /*!< SCU SFSP0_0: MODE Position */ #define SCU_SFSP0_0_MODE_Msk (0x07UL << SCU_SFSP0_0_MODE_Pos) /*!< SCU SFSP0_0: MODE Mask */ #define SCU_SFSP0_0_EPD_Pos 3 /*!< SCU SFSP0_0: EPD Position */ #define SCU_SFSP0_0_EPD_Msk (0x01UL << SCU_SFSP0_0_EPD_Pos) /*!< SCU SFSP0_0: EPD Mask */ #define SCU_SFSP0_0_EPUN_Pos 4 /*!< SCU SFSP0_0: EPUN Position */ #define SCU_SFSP0_0_EPUN_Msk (0x01UL << SCU_SFSP0_0_EPUN_Pos) /*!< SCU SFSP0_0: EPUN Mask */ #define SCU_SFSP0_0_EHS_Pos 5 /*!< SCU SFSP0_0: EHS Position */ #define SCU_SFSP0_0_EHS_Msk (0x01UL << SCU_SFSP0_0_EHS_Pos) /*!< SCU SFSP0_0: EHS Mask */ #define SCU_SFSP0_0_EZI_Pos 6 /*!< SCU SFSP0_0: EZI Position */ #define SCU_SFSP0_0_EZI_Msk (0x01UL << SCU_SFSP0_0_EZI_Pos) /*!< SCU SFSP0_0: EZI Mask */ #define SCU_SFSP0_0_ZIF_Pos 7 /*!< SCU SFSP0_0: ZIF Position */ #define SCU_SFSP0_0_ZIF_Msk (0x01UL << SCU_SFSP0_0_ZIF_Pos) /*!< SCU SFSP0_0: ZIF Mask */ /* --------------------------------- SCU_SFSP0_1 -------------------------------- */ #define SCU_SFSP0_1_MODE_Pos 0 /*!< SCU SFSP0_1: MODE Position */ #define SCU_SFSP0_1_MODE_Msk (0x07UL << SCU_SFSP0_1_MODE_Pos) /*!< SCU SFSP0_1: MODE Mask */ #define SCU_SFSP0_1_EPD_Pos 3 /*!< SCU SFSP0_1: EPD Position */ #define SCU_SFSP0_1_EPD_Msk (0x01UL << SCU_SFSP0_1_EPD_Pos) /*!< SCU SFSP0_1: EPD Mask */ #define SCU_SFSP0_1_EPUN_Pos 4 /*!< SCU SFSP0_1: EPUN Position */ #define SCU_SFSP0_1_EPUN_Msk (0x01UL << SCU_SFSP0_1_EPUN_Pos) /*!< SCU SFSP0_1: EPUN Mask */ #define SCU_SFSP0_1_EHS_Pos 5 /*!< SCU SFSP0_1: EHS Position */ #define SCU_SFSP0_1_EHS_Msk (0x01UL << SCU_SFSP0_1_EHS_Pos) /*!< SCU SFSP0_1: EHS Mask */ #define SCU_SFSP0_1_EZI_Pos 6 /*!< SCU SFSP0_1: EZI Position */ #define SCU_SFSP0_1_EZI_Msk (0x01UL << SCU_SFSP0_1_EZI_Pos) /*!< SCU SFSP0_1: EZI Mask */ #define SCU_SFSP0_1_ZIF_Pos 7 /*!< SCU SFSP0_1: ZIF Position */ #define SCU_SFSP0_1_ZIF_Msk (0x01UL << SCU_SFSP0_1_ZIF_Pos) /*!< SCU SFSP0_1: ZIF Mask */ /* --------------------------------- SCU_SFSP1_0 -------------------------------- */ #define SCU_SFSP1_0_MODE_Pos 0 /*!< SCU SFSP1_0: MODE Position */ #define SCU_SFSP1_0_MODE_Msk (0x07UL << SCU_SFSP1_0_MODE_Pos) /*!< SCU SFSP1_0: MODE Mask */ #define SCU_SFSP1_0_EPD_Pos 3 /*!< SCU SFSP1_0: EPD Position */ #define SCU_SFSP1_0_EPD_Msk (0x01UL << SCU_SFSP1_0_EPD_Pos) /*!< SCU SFSP1_0: EPD Mask */ #define SCU_SFSP1_0_EPUN_Pos 4 /*!< SCU SFSP1_0: EPUN Position */ #define SCU_SFSP1_0_EPUN_Msk (0x01UL << SCU_SFSP1_0_EPUN_Pos) /*!< SCU SFSP1_0: EPUN Mask */ #define SCU_SFSP1_0_EHS_Pos 5 /*!< SCU SFSP1_0: EHS Position */ #define SCU_SFSP1_0_EHS_Msk (0x01UL << SCU_SFSP1_0_EHS_Pos) /*!< SCU SFSP1_0: EHS Mask */ #define SCU_SFSP1_0_EZI_Pos 6 /*!< SCU SFSP1_0: EZI Position */ #define SCU_SFSP1_0_EZI_Msk (0x01UL << SCU_SFSP1_0_EZI_Pos) /*!< SCU SFSP1_0: EZI Mask */ #define SCU_SFSP1_0_ZIF_Pos 7 /*!< SCU SFSP1_0: ZIF Position */ #define SCU_SFSP1_0_ZIF_Msk (0x01UL << SCU_SFSP1_0_ZIF_Pos) /*!< SCU SFSP1_0: ZIF Mask */ /* --------------------------------- SCU_SFSP1_1 -------------------------------- */ #define SCU_SFSP1_1_MODE_Pos 0 /*!< SCU SFSP1_1: MODE Position */ #define SCU_SFSP1_1_MODE_Msk (0x07UL << SCU_SFSP1_1_MODE_Pos) /*!< SCU SFSP1_1: MODE Mask */ #define SCU_SFSP1_1_EPD_Pos 3 /*!< SCU SFSP1_1: EPD Position */ #define SCU_SFSP1_1_EPD_Msk (0x01UL << SCU_SFSP1_1_EPD_Pos) /*!< SCU SFSP1_1: EPD Mask */ #define SCU_SFSP1_1_EPUN_Pos 4 /*!< SCU SFSP1_1: EPUN Position */ #define SCU_SFSP1_1_EPUN_Msk (0x01UL << SCU_SFSP1_1_EPUN_Pos) /*!< SCU SFSP1_1: EPUN Mask */ #define SCU_SFSP1_1_EHS_Pos 5 /*!< SCU SFSP1_1: EHS Position */ #define SCU_SFSP1_1_EHS_Msk (0x01UL << SCU_SFSP1_1_EHS_Pos) /*!< SCU SFSP1_1: EHS Mask */ #define SCU_SFSP1_1_EZI_Pos 6 /*!< SCU SFSP1_1: EZI Position */ #define SCU_SFSP1_1_EZI_Msk (0x01UL << SCU_SFSP1_1_EZI_Pos) /*!< SCU SFSP1_1: EZI Mask */ #define SCU_SFSP1_1_ZIF_Pos 7 /*!< SCU SFSP1_1: ZIF Position */ #define SCU_SFSP1_1_ZIF_Msk (0x01UL << SCU_SFSP1_1_ZIF_Pos) /*!< SCU SFSP1_1: ZIF Mask */ /* --------------------------------- SCU_SFSP1_2 -------------------------------- */ #define SCU_SFSP1_2_MODE_Pos 0 /*!< SCU SFSP1_2: MODE Position */ #define SCU_SFSP1_2_MODE_Msk (0x07UL << SCU_SFSP1_2_MODE_Pos) /*!< SCU SFSP1_2: MODE Mask */ #define SCU_SFSP1_2_EPD_Pos 3 /*!< SCU SFSP1_2: EPD Position */ #define SCU_SFSP1_2_EPD_Msk (0x01UL << SCU_SFSP1_2_EPD_Pos) /*!< SCU SFSP1_2: EPD Mask */ #define SCU_SFSP1_2_EPUN_Pos 4 /*!< SCU SFSP1_2: EPUN Position */ #define SCU_SFSP1_2_EPUN_Msk (0x01UL << SCU_SFSP1_2_EPUN_Pos) /*!< SCU SFSP1_2: EPUN Mask */ #define SCU_SFSP1_2_EHS_Pos 5 /*!< SCU SFSP1_2: EHS Position */ #define SCU_SFSP1_2_EHS_Msk (0x01UL << SCU_SFSP1_2_EHS_Pos) /*!< SCU SFSP1_2: EHS Mask */ #define SCU_SFSP1_2_EZI_Pos 6 /*!< SCU SFSP1_2: EZI Position */ #define SCU_SFSP1_2_EZI_Msk (0x01UL << SCU_SFSP1_2_EZI_Pos) /*!< SCU SFSP1_2: EZI Mask */ #define SCU_SFSP1_2_ZIF_Pos 7 /*!< SCU SFSP1_2: ZIF Position */ #define SCU_SFSP1_2_ZIF_Msk (0x01UL << SCU_SFSP1_2_ZIF_Pos) /*!< SCU SFSP1_2: ZIF Mask */ /* --------------------------------- SCU_SFSP1_3 -------------------------------- */ #define SCU_SFSP1_3_MODE_Pos 0 /*!< SCU SFSP1_3: MODE Position */ #define SCU_SFSP1_3_MODE_Msk (0x07UL << SCU_SFSP1_3_MODE_Pos) /*!< SCU SFSP1_3: MODE Mask */ #define SCU_SFSP1_3_EPD_Pos 3 /*!< SCU SFSP1_3: EPD Position */ #define SCU_SFSP1_3_EPD_Msk (0x01UL << SCU_SFSP1_3_EPD_Pos) /*!< SCU SFSP1_3: EPD Mask */ #define SCU_SFSP1_3_EPUN_Pos 4 /*!< SCU SFSP1_3: EPUN Position */ #define SCU_SFSP1_3_EPUN_Msk (0x01UL << SCU_SFSP1_3_EPUN_Pos) /*!< SCU SFSP1_3: EPUN Mask */ #define SCU_SFSP1_3_EHS_Pos 5 /*!< SCU SFSP1_3: EHS Position */ #define SCU_SFSP1_3_EHS_Msk (0x01UL << SCU_SFSP1_3_EHS_Pos) /*!< SCU SFSP1_3: EHS Mask */ #define SCU_SFSP1_3_EZI_Pos 6 /*!< SCU SFSP1_3: EZI Position */ #define SCU_SFSP1_3_EZI_Msk (0x01UL << SCU_SFSP1_3_EZI_Pos) /*!< SCU SFSP1_3: EZI Mask */ #define SCU_SFSP1_3_ZIF_Pos 7 /*!< SCU SFSP1_3: ZIF Position */ #define SCU_SFSP1_3_ZIF_Msk (0x01UL << SCU_SFSP1_3_ZIF_Pos) /*!< SCU SFSP1_3: ZIF Mask */ /* --------------------------------- SCU_SFSP1_4 -------------------------------- */ #define SCU_SFSP1_4_MODE_Pos 0 /*!< SCU SFSP1_4: MODE Position */ #define SCU_SFSP1_4_MODE_Msk (0x07UL << SCU_SFSP1_4_MODE_Pos) /*!< SCU SFSP1_4: MODE Mask */ #define SCU_SFSP1_4_EPD_Pos 3 /*!< SCU SFSP1_4: EPD Position */ #define SCU_SFSP1_4_EPD_Msk (0x01UL << SCU_SFSP1_4_EPD_Pos) /*!< SCU SFSP1_4: EPD Mask */ #define SCU_SFSP1_4_EPUN_Pos 4 /*!< SCU SFSP1_4: EPUN Position */ #define SCU_SFSP1_4_EPUN_Msk (0x01UL << SCU_SFSP1_4_EPUN_Pos) /*!< SCU SFSP1_4: EPUN Mask */ #define SCU_SFSP1_4_EHS_Pos 5 /*!< SCU SFSP1_4: EHS Position */ #define SCU_SFSP1_4_EHS_Msk (0x01UL << SCU_SFSP1_4_EHS_Pos) /*!< SCU SFSP1_4: EHS Mask */ #define SCU_SFSP1_4_EZI_Pos 6 /*!< SCU SFSP1_4: EZI Position */ #define SCU_SFSP1_4_EZI_Msk (0x01UL << SCU_SFSP1_4_EZI_Pos) /*!< SCU SFSP1_4: EZI Mask */ #define SCU_SFSP1_4_ZIF_Pos 7 /*!< SCU SFSP1_4: ZIF Position */ #define SCU_SFSP1_4_ZIF_Msk (0x01UL << SCU_SFSP1_4_ZIF_Pos) /*!< SCU SFSP1_4: ZIF Mask */ /* --------------------------------- SCU_SFSP1_5 -------------------------------- */ #define SCU_SFSP1_5_MODE_Pos 0 /*!< SCU SFSP1_5: MODE Position */ #define SCU_SFSP1_5_MODE_Msk (0x07UL << SCU_SFSP1_5_MODE_Pos) /*!< SCU SFSP1_5: MODE Mask */ #define SCU_SFSP1_5_EPD_Pos 3 /*!< SCU SFSP1_5: EPD Position */ #define SCU_SFSP1_5_EPD_Msk (0x01UL << SCU_SFSP1_5_EPD_Pos) /*!< SCU SFSP1_5: EPD Mask */ #define SCU_SFSP1_5_EPUN_Pos 4 /*!< SCU SFSP1_5: EPUN Position */ #define SCU_SFSP1_5_EPUN_Msk (0x01UL << SCU_SFSP1_5_EPUN_Pos) /*!< SCU SFSP1_5: EPUN Mask */ #define SCU_SFSP1_5_EHS_Pos 5 /*!< SCU SFSP1_5: EHS Position */ #define SCU_SFSP1_5_EHS_Msk (0x01UL << SCU_SFSP1_5_EHS_Pos) /*!< SCU SFSP1_5: EHS Mask */ #define SCU_SFSP1_5_EZI_Pos 6 /*!< SCU SFSP1_5: EZI Position */ #define SCU_SFSP1_5_EZI_Msk (0x01UL << SCU_SFSP1_5_EZI_Pos) /*!< SCU SFSP1_5: EZI Mask */ #define SCU_SFSP1_5_ZIF_Pos 7 /*!< SCU SFSP1_5: ZIF Position */ #define SCU_SFSP1_5_ZIF_Msk (0x01UL << SCU_SFSP1_5_ZIF_Pos) /*!< SCU SFSP1_5: ZIF Mask */ /* --------------------------------- SCU_SFSP1_6 -------------------------------- */ #define SCU_SFSP1_6_MODE_Pos 0 /*!< SCU SFSP1_6: MODE Position */ #define SCU_SFSP1_6_MODE_Msk (0x07UL << SCU_SFSP1_6_MODE_Pos) /*!< SCU SFSP1_6: MODE Mask */ #define SCU_SFSP1_6_EPD_Pos 3 /*!< SCU SFSP1_6: EPD Position */ #define SCU_SFSP1_6_EPD_Msk (0x01UL << SCU_SFSP1_6_EPD_Pos) /*!< SCU SFSP1_6: EPD Mask */ #define SCU_SFSP1_6_EPUN_Pos 4 /*!< SCU SFSP1_6: EPUN Position */ #define SCU_SFSP1_6_EPUN_Msk (0x01UL << SCU_SFSP1_6_EPUN_Pos) /*!< SCU SFSP1_6: EPUN Mask */ #define SCU_SFSP1_6_EHS_Pos 5 /*!< SCU SFSP1_6: EHS Position */ #define SCU_SFSP1_6_EHS_Msk (0x01UL << SCU_SFSP1_6_EHS_Pos) /*!< SCU SFSP1_6: EHS Mask */ #define SCU_SFSP1_6_EZI_Pos 6 /*!< SCU SFSP1_6: EZI Position */ #define SCU_SFSP1_6_EZI_Msk (0x01UL << SCU_SFSP1_6_EZI_Pos) /*!< SCU SFSP1_6: EZI Mask */ #define SCU_SFSP1_6_ZIF_Pos 7 /*!< SCU SFSP1_6: ZIF Position */ #define SCU_SFSP1_6_ZIF_Msk (0x01UL << SCU_SFSP1_6_ZIF_Pos) /*!< SCU SFSP1_6: ZIF Mask */ /* --------------------------------- SCU_SFSP1_7 -------------------------------- */ #define SCU_SFSP1_7_MODE_Pos 0 /*!< SCU SFSP1_7: MODE Position */ #define SCU_SFSP1_7_MODE_Msk (0x07UL << SCU_SFSP1_7_MODE_Pos) /*!< SCU SFSP1_7: MODE Mask */ #define SCU_SFSP1_7_EPD_Pos 3 /*!< SCU SFSP1_7: EPD Position */ #define SCU_SFSP1_7_EPD_Msk (0x01UL << SCU_SFSP1_7_EPD_Pos) /*!< SCU SFSP1_7: EPD Mask */ #define SCU_SFSP1_7_EPUN_Pos 4 /*!< SCU SFSP1_7: EPUN Position */ #define SCU_SFSP1_7_EPUN_Msk (0x01UL << SCU_SFSP1_7_EPUN_Pos) /*!< SCU SFSP1_7: EPUN Mask */ #define SCU_SFSP1_7_EHS_Pos 5 /*!< SCU SFSP1_7: EHS Position */ #define SCU_SFSP1_7_EHS_Msk (0x01UL << SCU_SFSP1_7_EHS_Pos) /*!< SCU SFSP1_7: EHS Mask */ #define SCU_SFSP1_7_EZI_Pos 6 /*!< SCU SFSP1_7: EZI Position */ #define SCU_SFSP1_7_EZI_Msk (0x01UL << SCU_SFSP1_7_EZI_Pos) /*!< SCU SFSP1_7: EZI Mask */ #define SCU_SFSP1_7_ZIF_Pos 7 /*!< SCU SFSP1_7: ZIF Position */ #define SCU_SFSP1_7_ZIF_Msk (0x01UL << SCU_SFSP1_7_ZIF_Pos) /*!< SCU SFSP1_7: ZIF Mask */ /* --------------------------------- SCU_SFSP1_8 -------------------------------- */ #define SCU_SFSP1_8_MODE_Pos 0 /*!< SCU SFSP1_8: MODE Position */ #define SCU_SFSP1_8_MODE_Msk (0x07UL << SCU_SFSP1_8_MODE_Pos) /*!< SCU SFSP1_8: MODE Mask */ #define SCU_SFSP1_8_EPD_Pos 3 /*!< SCU SFSP1_8: EPD Position */ #define SCU_SFSP1_8_EPD_Msk (0x01UL << SCU_SFSP1_8_EPD_Pos) /*!< SCU SFSP1_8: EPD Mask */ #define SCU_SFSP1_8_EPUN_Pos 4 /*!< SCU SFSP1_8: EPUN Position */ #define SCU_SFSP1_8_EPUN_Msk (0x01UL << SCU_SFSP1_8_EPUN_Pos) /*!< SCU SFSP1_8: EPUN Mask */ #define SCU_SFSP1_8_EHS_Pos 5 /*!< SCU SFSP1_8: EHS Position */ #define SCU_SFSP1_8_EHS_Msk (0x01UL << SCU_SFSP1_8_EHS_Pos) /*!< SCU SFSP1_8: EHS Mask */ #define SCU_SFSP1_8_EZI_Pos 6 /*!< SCU SFSP1_8: EZI Position */ #define SCU_SFSP1_8_EZI_Msk (0x01UL << SCU_SFSP1_8_EZI_Pos) /*!< SCU SFSP1_8: EZI Mask */ #define SCU_SFSP1_8_ZIF_Pos 7 /*!< SCU SFSP1_8: ZIF Position */ #define SCU_SFSP1_8_ZIF_Msk (0x01UL << SCU_SFSP1_8_ZIF_Pos) /*!< SCU SFSP1_8: ZIF Mask */ /* --------------------------------- SCU_SFSP1_9 -------------------------------- */ #define SCU_SFSP1_9_MODE_Pos 0 /*!< SCU SFSP1_9: MODE Position */ #define SCU_SFSP1_9_MODE_Msk (0x07UL << SCU_SFSP1_9_MODE_Pos) /*!< SCU SFSP1_9: MODE Mask */ #define SCU_SFSP1_9_EPD_Pos 3 /*!< SCU SFSP1_9: EPD Position */ #define SCU_SFSP1_9_EPD_Msk (0x01UL << SCU_SFSP1_9_EPD_Pos) /*!< SCU SFSP1_9: EPD Mask */ #define SCU_SFSP1_9_EPUN_Pos 4 /*!< SCU SFSP1_9: EPUN Position */ #define SCU_SFSP1_9_EPUN_Msk (0x01UL << SCU_SFSP1_9_EPUN_Pos) /*!< SCU SFSP1_9: EPUN Mask */ #define SCU_SFSP1_9_EHS_Pos 5 /*!< SCU SFSP1_9: EHS Position */ #define SCU_SFSP1_9_EHS_Msk (0x01UL << SCU_SFSP1_9_EHS_Pos) /*!< SCU SFSP1_9: EHS Mask */ #define SCU_SFSP1_9_EZI_Pos 6 /*!< SCU SFSP1_9: EZI Position */ #define SCU_SFSP1_9_EZI_Msk (0x01UL << SCU_SFSP1_9_EZI_Pos) /*!< SCU SFSP1_9: EZI Mask */ #define SCU_SFSP1_9_ZIF_Pos 7 /*!< SCU SFSP1_9: ZIF Position */ #define SCU_SFSP1_9_ZIF_Msk (0x01UL << SCU_SFSP1_9_ZIF_Pos) /*!< SCU SFSP1_9: ZIF Mask */ /* -------------------------------- SCU_SFSP1_10 -------------------------------- */ #define SCU_SFSP1_10_MODE_Pos 0 /*!< SCU SFSP1_10: MODE Position */ #define SCU_SFSP1_10_MODE_Msk (0x07UL << SCU_SFSP1_10_MODE_Pos) /*!< SCU SFSP1_10: MODE Mask */ #define SCU_SFSP1_10_EPD_Pos 3 /*!< SCU SFSP1_10: EPD Position */ #define SCU_SFSP1_10_EPD_Msk (0x01UL << SCU_SFSP1_10_EPD_Pos) /*!< SCU SFSP1_10: EPD Mask */ #define SCU_SFSP1_10_EPUN_Pos 4 /*!< SCU SFSP1_10: EPUN Position */ #define SCU_SFSP1_10_EPUN_Msk (0x01UL << SCU_SFSP1_10_EPUN_Pos) /*!< SCU SFSP1_10: EPUN Mask */ #define SCU_SFSP1_10_EHS_Pos 5 /*!< SCU SFSP1_10: EHS Position */ #define SCU_SFSP1_10_EHS_Msk (0x01UL << SCU_SFSP1_10_EHS_Pos) /*!< SCU SFSP1_10: EHS Mask */ #define SCU_SFSP1_10_EZI_Pos 6 /*!< SCU SFSP1_10: EZI Position */ #define SCU_SFSP1_10_EZI_Msk (0x01UL << SCU_SFSP1_10_EZI_Pos) /*!< SCU SFSP1_10: EZI Mask */ #define SCU_SFSP1_10_ZIF_Pos 7 /*!< SCU SFSP1_10: ZIF Position */ #define SCU_SFSP1_10_ZIF_Msk (0x01UL << SCU_SFSP1_10_ZIF_Pos) /*!< SCU SFSP1_10: ZIF Mask */ /* -------------------------------- SCU_SFSP1_11 -------------------------------- */ #define SCU_SFSP1_11_MODE_Pos 0 /*!< SCU SFSP1_11: MODE Position */ #define SCU_SFSP1_11_MODE_Msk (0x07UL << SCU_SFSP1_11_MODE_Pos) /*!< SCU SFSP1_11: MODE Mask */ #define SCU_SFSP1_11_EPD_Pos 3 /*!< SCU SFSP1_11: EPD Position */ #define SCU_SFSP1_11_EPD_Msk (0x01UL << SCU_SFSP1_11_EPD_Pos) /*!< SCU SFSP1_11: EPD Mask */ #define SCU_SFSP1_11_EPUN_Pos 4 /*!< SCU SFSP1_11: EPUN Position */ #define SCU_SFSP1_11_EPUN_Msk (0x01UL << SCU_SFSP1_11_EPUN_Pos) /*!< SCU SFSP1_11: EPUN Mask */ #define SCU_SFSP1_11_EHS_Pos 5 /*!< SCU SFSP1_11: EHS Position */ #define SCU_SFSP1_11_EHS_Msk (0x01UL << SCU_SFSP1_11_EHS_Pos) /*!< SCU SFSP1_11: EHS Mask */ #define SCU_SFSP1_11_EZI_Pos 6 /*!< SCU SFSP1_11: EZI Position */ #define SCU_SFSP1_11_EZI_Msk (0x01UL << SCU_SFSP1_11_EZI_Pos) /*!< SCU SFSP1_11: EZI Mask */ #define SCU_SFSP1_11_ZIF_Pos 7 /*!< SCU SFSP1_11: ZIF Position */ #define SCU_SFSP1_11_ZIF_Msk (0x01UL << SCU_SFSP1_11_ZIF_Pos) /*!< SCU SFSP1_11: ZIF Mask */ /* -------------------------------- SCU_SFSP1_12 -------------------------------- */ #define SCU_SFSP1_12_MODE_Pos 0 /*!< SCU SFSP1_12: MODE Position */ #define SCU_SFSP1_12_MODE_Msk (0x07UL << SCU_SFSP1_12_MODE_Pos) /*!< SCU SFSP1_12: MODE Mask */ #define SCU_SFSP1_12_EPD_Pos 3 /*!< SCU SFSP1_12: EPD Position */ #define SCU_SFSP1_12_EPD_Msk (0x01UL << SCU_SFSP1_12_EPD_Pos) /*!< SCU SFSP1_12: EPD Mask */ #define SCU_SFSP1_12_EPUN_Pos 4 /*!< SCU SFSP1_12: EPUN Position */ #define SCU_SFSP1_12_EPUN_Msk (0x01UL << SCU_SFSP1_12_EPUN_Pos) /*!< SCU SFSP1_12: EPUN Mask */ #define SCU_SFSP1_12_EHS_Pos 5 /*!< SCU SFSP1_12: EHS Position */ #define SCU_SFSP1_12_EHS_Msk (0x01UL << SCU_SFSP1_12_EHS_Pos) /*!< SCU SFSP1_12: EHS Mask */ #define SCU_SFSP1_12_EZI_Pos 6 /*!< SCU SFSP1_12: EZI Position */ #define SCU_SFSP1_12_EZI_Msk (0x01UL << SCU_SFSP1_12_EZI_Pos) /*!< SCU SFSP1_12: EZI Mask */ #define SCU_SFSP1_12_ZIF_Pos 7 /*!< SCU SFSP1_12: ZIF Position */ #define SCU_SFSP1_12_ZIF_Msk (0x01UL << SCU_SFSP1_12_ZIF_Pos) /*!< SCU SFSP1_12: ZIF Mask */ /* -------------------------------- SCU_SFSP1_13 -------------------------------- */ #define SCU_SFSP1_13_MODE_Pos 0 /*!< SCU SFSP1_13: MODE Position */ #define SCU_SFSP1_13_MODE_Msk (0x07UL << SCU_SFSP1_13_MODE_Pos) /*!< SCU SFSP1_13: MODE Mask */ #define SCU_SFSP1_13_EPD_Pos 3 /*!< SCU SFSP1_13: EPD Position */ #define SCU_SFSP1_13_EPD_Msk (0x01UL << SCU_SFSP1_13_EPD_Pos) /*!< SCU SFSP1_13: EPD Mask */ #define SCU_SFSP1_13_EPUN_Pos 4 /*!< SCU SFSP1_13: EPUN Position */ #define SCU_SFSP1_13_EPUN_Msk (0x01UL << SCU_SFSP1_13_EPUN_Pos) /*!< SCU SFSP1_13: EPUN Mask */ #define SCU_SFSP1_13_EHS_Pos 5 /*!< SCU SFSP1_13: EHS Position */ #define SCU_SFSP1_13_EHS_Msk (0x01UL << SCU_SFSP1_13_EHS_Pos) /*!< SCU SFSP1_13: EHS Mask */ #define SCU_SFSP1_13_EZI_Pos 6 /*!< SCU SFSP1_13: EZI Position */ #define SCU_SFSP1_13_EZI_Msk (0x01UL << SCU_SFSP1_13_EZI_Pos) /*!< SCU SFSP1_13: EZI Mask */ #define SCU_SFSP1_13_ZIF_Pos 7 /*!< SCU SFSP1_13: ZIF Position */ #define SCU_SFSP1_13_ZIF_Msk (0x01UL << SCU_SFSP1_13_ZIF_Pos) /*!< SCU SFSP1_13: ZIF Mask */ /* -------------------------------- SCU_SFSP1_14 -------------------------------- */ #define SCU_SFSP1_14_MODE_Pos 0 /*!< SCU SFSP1_14: MODE Position */ #define SCU_SFSP1_14_MODE_Msk (0x07UL << SCU_SFSP1_14_MODE_Pos) /*!< SCU SFSP1_14: MODE Mask */ #define SCU_SFSP1_14_EPD_Pos 3 /*!< SCU SFSP1_14: EPD Position */ #define SCU_SFSP1_14_EPD_Msk (0x01UL << SCU_SFSP1_14_EPD_Pos) /*!< SCU SFSP1_14: EPD Mask */ #define SCU_SFSP1_14_EPUN_Pos 4 /*!< SCU SFSP1_14: EPUN Position */ #define SCU_SFSP1_14_EPUN_Msk (0x01UL << SCU_SFSP1_14_EPUN_Pos) /*!< SCU SFSP1_14: EPUN Mask */ #define SCU_SFSP1_14_EHS_Pos 5 /*!< SCU SFSP1_14: EHS Position */ #define SCU_SFSP1_14_EHS_Msk (0x01UL << SCU_SFSP1_14_EHS_Pos) /*!< SCU SFSP1_14: EHS Mask */ #define SCU_SFSP1_14_EZI_Pos 6 /*!< SCU SFSP1_14: EZI Position */ #define SCU_SFSP1_14_EZI_Msk (0x01UL << SCU_SFSP1_14_EZI_Pos) /*!< SCU SFSP1_14: EZI Mask */ #define SCU_SFSP1_14_ZIF_Pos 7 /*!< SCU SFSP1_14: ZIF Position */ #define SCU_SFSP1_14_ZIF_Msk (0x01UL << SCU_SFSP1_14_ZIF_Pos) /*!< SCU SFSP1_14: ZIF Mask */ /* -------------------------------- SCU_SFSP1_15 -------------------------------- */ #define SCU_SFSP1_15_MODE_Pos 0 /*!< SCU SFSP1_15: MODE Position */ #define SCU_SFSP1_15_MODE_Msk (0x07UL << SCU_SFSP1_15_MODE_Pos) /*!< SCU SFSP1_15: MODE Mask */ #define SCU_SFSP1_15_EPD_Pos 3 /*!< SCU SFSP1_15: EPD Position */ #define SCU_SFSP1_15_EPD_Msk (0x01UL << SCU_SFSP1_15_EPD_Pos) /*!< SCU SFSP1_15: EPD Mask */ #define SCU_SFSP1_15_EPUN_Pos 4 /*!< SCU SFSP1_15: EPUN Position */ #define SCU_SFSP1_15_EPUN_Msk (0x01UL << SCU_SFSP1_15_EPUN_Pos) /*!< SCU SFSP1_15: EPUN Mask */ #define SCU_SFSP1_15_EHS_Pos 5 /*!< SCU SFSP1_15: EHS Position */ #define SCU_SFSP1_15_EHS_Msk (0x01UL << SCU_SFSP1_15_EHS_Pos) /*!< SCU SFSP1_15: EHS Mask */ #define SCU_SFSP1_15_EZI_Pos 6 /*!< SCU SFSP1_15: EZI Position */ #define SCU_SFSP1_15_EZI_Msk (0x01UL << SCU_SFSP1_15_EZI_Pos) /*!< SCU SFSP1_15: EZI Mask */ #define SCU_SFSP1_15_ZIF_Pos 7 /*!< SCU SFSP1_15: ZIF Position */ #define SCU_SFSP1_15_ZIF_Msk (0x01UL << SCU_SFSP1_15_ZIF_Pos) /*!< SCU SFSP1_15: ZIF Mask */ /* -------------------------------- SCU_SFSP1_16 -------------------------------- */ #define SCU_SFSP1_16_MODE_Pos 0 /*!< SCU SFSP1_16: MODE Position */ #define SCU_SFSP1_16_MODE_Msk (0x07UL << SCU_SFSP1_16_MODE_Pos) /*!< SCU SFSP1_16: MODE Mask */ #define SCU_SFSP1_16_EPD_Pos 3 /*!< SCU SFSP1_16: EPD Position */ #define SCU_SFSP1_16_EPD_Msk (0x01UL << SCU_SFSP1_16_EPD_Pos) /*!< SCU SFSP1_16: EPD Mask */ #define SCU_SFSP1_16_EPUN_Pos 4 /*!< SCU SFSP1_16: EPUN Position */ #define SCU_SFSP1_16_EPUN_Msk (0x01UL << SCU_SFSP1_16_EPUN_Pos) /*!< SCU SFSP1_16: EPUN Mask */ #define SCU_SFSP1_16_EHS_Pos 5 /*!< SCU SFSP1_16: EHS Position */ #define SCU_SFSP1_16_EHS_Msk (0x01UL << SCU_SFSP1_16_EHS_Pos) /*!< SCU SFSP1_16: EHS Mask */ #define SCU_SFSP1_16_EZI_Pos 6 /*!< SCU SFSP1_16: EZI Position */ #define SCU_SFSP1_16_EZI_Msk (0x01UL << SCU_SFSP1_16_EZI_Pos) /*!< SCU SFSP1_16: EZI Mask */ #define SCU_SFSP1_16_ZIF_Pos 7 /*!< SCU SFSP1_16: ZIF Position */ #define SCU_SFSP1_16_ZIF_Msk (0x01UL << SCU_SFSP1_16_ZIF_Pos) /*!< SCU SFSP1_16: ZIF Mask */ /* -------------------------------- SCU_SFSP1_17 -------------------------------- */ #define SCU_SFSP1_17_MODE_Pos 0 /*!< SCU SFSP1_17: MODE Position */ #define SCU_SFSP1_17_MODE_Msk (0x07UL << SCU_SFSP1_17_MODE_Pos) /*!< SCU SFSP1_17: MODE Mask */ #define SCU_SFSP1_17_EPD_Pos 3 /*!< SCU SFSP1_17: EPD Position */ #define SCU_SFSP1_17_EPD_Msk (0x01UL << SCU_SFSP1_17_EPD_Pos) /*!< SCU SFSP1_17: EPD Mask */ #define SCU_SFSP1_17_EPUN_Pos 4 /*!< SCU SFSP1_17: EPUN Position */ #define SCU_SFSP1_17_EPUN_Msk (0x01UL << SCU_SFSP1_17_EPUN_Pos) /*!< SCU SFSP1_17: EPUN Mask */ #define SCU_SFSP1_17_EZI_Pos 6 /*!< SCU SFSP1_17: EZI Position */ #define SCU_SFSP1_17_EZI_Msk (0x01UL << SCU_SFSP1_17_EZI_Pos) /*!< SCU SFSP1_17: EZI Mask */ #define SCU_SFSP1_17_ZIF_Pos 7 /*!< SCU SFSP1_17: ZIF Position */ #define SCU_SFSP1_17_ZIF_Msk (0x01UL << SCU_SFSP1_17_ZIF_Pos) /*!< SCU SFSP1_17: ZIF Mask */ #define SCU_SFSP1_17_EHD_Pos 8 /*!< SCU SFSP1_17: EHD Position */ #define SCU_SFSP1_17_EHD_Msk (0x03UL << SCU_SFSP1_17_EHD_Pos) /*!< SCU SFSP1_17: EHD Mask */ /* -------------------------------- SCU_SFSP1_18 -------------------------------- */ #define SCU_SFSP1_18_MODE_Pos 0 /*!< SCU SFSP1_18: MODE Position */ #define SCU_SFSP1_18_MODE_Msk (0x07UL << SCU_SFSP1_18_MODE_Pos) /*!< SCU SFSP1_18: MODE Mask */ #define SCU_SFSP1_18_EPD_Pos 3 /*!< SCU SFSP1_18: EPD Position */ #define SCU_SFSP1_18_EPD_Msk (0x01UL << SCU_SFSP1_18_EPD_Pos) /*!< SCU SFSP1_18: EPD Mask */ #define SCU_SFSP1_18_EPUN_Pos 4 /*!< SCU SFSP1_18: EPUN Position */ #define SCU_SFSP1_18_EPUN_Msk (0x01UL << SCU_SFSP1_18_EPUN_Pos) /*!< SCU SFSP1_18: EPUN Mask */ #define SCU_SFSP1_18_EHS_Pos 5 /*!< SCU SFSP1_18: EHS Position */ #define SCU_SFSP1_18_EHS_Msk (0x01UL << SCU_SFSP1_18_EHS_Pos) /*!< SCU SFSP1_18: EHS Mask */ #define SCU_SFSP1_18_EZI_Pos 6 /*!< SCU SFSP1_18: EZI Position */ #define SCU_SFSP1_18_EZI_Msk (0x01UL << SCU_SFSP1_18_EZI_Pos) /*!< SCU SFSP1_18: EZI Mask */ #define SCU_SFSP1_18_ZIF_Pos 7 /*!< SCU SFSP1_18: ZIF Position */ #define SCU_SFSP1_18_ZIF_Msk (0x01UL << SCU_SFSP1_18_ZIF_Pos) /*!< SCU SFSP1_18: ZIF Mask */ /* -------------------------------- SCU_SFSP1_19 -------------------------------- */ #define SCU_SFSP1_19_MODE_Pos 0 /*!< SCU SFSP1_19: MODE Position */ #define SCU_SFSP1_19_MODE_Msk (0x07UL << SCU_SFSP1_19_MODE_Pos) /*!< SCU SFSP1_19: MODE Mask */ #define SCU_SFSP1_19_EPD_Pos 3 /*!< SCU SFSP1_19: EPD Position */ #define SCU_SFSP1_19_EPD_Msk (0x01UL << SCU_SFSP1_19_EPD_Pos) /*!< SCU SFSP1_19: EPD Mask */ #define SCU_SFSP1_19_EPUN_Pos 4 /*!< SCU SFSP1_19: EPUN Position */ #define SCU_SFSP1_19_EPUN_Msk (0x01UL << SCU_SFSP1_19_EPUN_Pos) /*!< SCU SFSP1_19: EPUN Mask */ #define SCU_SFSP1_19_EHS_Pos 5 /*!< SCU SFSP1_19: EHS Position */ #define SCU_SFSP1_19_EHS_Msk (0x01UL << SCU_SFSP1_19_EHS_Pos) /*!< SCU SFSP1_19: EHS Mask */ #define SCU_SFSP1_19_EZI_Pos 6 /*!< SCU SFSP1_19: EZI Position */ #define SCU_SFSP1_19_EZI_Msk (0x01UL << SCU_SFSP1_19_EZI_Pos) /*!< SCU SFSP1_19: EZI Mask */ #define SCU_SFSP1_19_ZIF_Pos 7 /*!< SCU SFSP1_19: ZIF Position */ #define SCU_SFSP1_19_ZIF_Msk (0x01UL << SCU_SFSP1_19_ZIF_Pos) /*!< SCU SFSP1_19: ZIF Mask */ /* -------------------------------- SCU_SFSP1_20 -------------------------------- */ #define SCU_SFSP1_20_MODE_Pos 0 /*!< SCU SFSP1_20: MODE Position */ #define SCU_SFSP1_20_MODE_Msk (0x07UL << SCU_SFSP1_20_MODE_Pos) /*!< SCU SFSP1_20: MODE Mask */ #define SCU_SFSP1_20_EPD_Pos 3 /*!< SCU SFSP1_20: EPD Position */ #define SCU_SFSP1_20_EPD_Msk (0x01UL << SCU_SFSP1_20_EPD_Pos) /*!< SCU SFSP1_20: EPD Mask */ #define SCU_SFSP1_20_EPUN_Pos 4 /*!< SCU SFSP1_20: EPUN Position */ #define SCU_SFSP1_20_EPUN_Msk (0x01UL << SCU_SFSP1_20_EPUN_Pos) /*!< SCU SFSP1_20: EPUN Mask */ #define SCU_SFSP1_20_EHS_Pos 5 /*!< SCU SFSP1_20: EHS Position */ #define SCU_SFSP1_20_EHS_Msk (0x01UL << SCU_SFSP1_20_EHS_Pos) /*!< SCU SFSP1_20: EHS Mask */ #define SCU_SFSP1_20_EZI_Pos 6 /*!< SCU SFSP1_20: EZI Position */ #define SCU_SFSP1_20_EZI_Msk (0x01UL << SCU_SFSP1_20_EZI_Pos) /*!< SCU SFSP1_20: EZI Mask */ #define SCU_SFSP1_20_ZIF_Pos 7 /*!< SCU SFSP1_20: ZIF Position */ #define SCU_SFSP1_20_ZIF_Msk (0x01UL << SCU_SFSP1_20_ZIF_Pos) /*!< SCU SFSP1_20: ZIF Mask */ /* --------------------------------- SCU_SFSP2_0 -------------------------------- */ #define SCU_SFSP2_0_MODE_Pos 0 /*!< SCU SFSP2_0: MODE Position */ #define SCU_SFSP2_0_MODE_Msk (0x07UL << SCU_SFSP2_0_MODE_Pos) /*!< SCU SFSP2_0: MODE Mask */ #define SCU_SFSP2_0_EPD_Pos 3 /*!< SCU SFSP2_0: EPD Position */ #define SCU_SFSP2_0_EPD_Msk (0x01UL << SCU_SFSP2_0_EPD_Pos) /*!< SCU SFSP2_0: EPD Mask */ #define SCU_SFSP2_0_EPUN_Pos 4 /*!< SCU SFSP2_0: EPUN Position */ #define SCU_SFSP2_0_EPUN_Msk (0x01UL << SCU_SFSP2_0_EPUN_Pos) /*!< SCU SFSP2_0: EPUN Mask */ #define SCU_SFSP2_0_EHS_Pos 5 /*!< SCU SFSP2_0: EHS Position */ #define SCU_SFSP2_0_EHS_Msk (0x01UL << SCU_SFSP2_0_EHS_Pos) /*!< SCU SFSP2_0: EHS Mask */ #define SCU_SFSP2_0_EZI_Pos 6 /*!< SCU SFSP2_0: EZI Position */ #define SCU_SFSP2_0_EZI_Msk (0x01UL << SCU_SFSP2_0_EZI_Pos) /*!< SCU SFSP2_0: EZI Mask */ #define SCU_SFSP2_0_ZIF_Pos 7 /*!< SCU SFSP2_0: ZIF Position */ #define SCU_SFSP2_0_ZIF_Msk (0x01UL << SCU_SFSP2_0_ZIF_Pos) /*!< SCU SFSP2_0: ZIF Mask */ /* --------------------------------- SCU_SFSP2_1 -------------------------------- */ #define SCU_SFSP2_1_MODE_Pos 0 /*!< SCU SFSP2_1: MODE Position */ #define SCU_SFSP2_1_MODE_Msk (0x07UL << SCU_SFSP2_1_MODE_Pos) /*!< SCU SFSP2_1: MODE Mask */ #define SCU_SFSP2_1_EPD_Pos 3 /*!< SCU SFSP2_1: EPD Position */ #define SCU_SFSP2_1_EPD_Msk (0x01UL << SCU_SFSP2_1_EPD_Pos) /*!< SCU SFSP2_1: EPD Mask */ #define SCU_SFSP2_1_EPUN_Pos 4 /*!< SCU SFSP2_1: EPUN Position */ #define SCU_SFSP2_1_EPUN_Msk (0x01UL << SCU_SFSP2_1_EPUN_Pos) /*!< SCU SFSP2_1: EPUN Mask */ #define SCU_SFSP2_1_EHS_Pos 5 /*!< SCU SFSP2_1: EHS Position */ #define SCU_SFSP2_1_EHS_Msk (0x01UL << SCU_SFSP2_1_EHS_Pos) /*!< SCU SFSP2_1: EHS Mask */ #define SCU_SFSP2_1_EZI_Pos 6 /*!< SCU SFSP2_1: EZI Position */ #define SCU_SFSP2_1_EZI_Msk (0x01UL << SCU_SFSP2_1_EZI_Pos) /*!< SCU SFSP2_1: EZI Mask */ #define SCU_SFSP2_1_ZIF_Pos 7 /*!< SCU SFSP2_1: ZIF Position */ #define SCU_SFSP2_1_ZIF_Msk (0x01UL << SCU_SFSP2_1_ZIF_Pos) /*!< SCU SFSP2_1: ZIF Mask */ /* --------------------------------- SCU_SFSP2_2 -------------------------------- */ #define SCU_SFSP2_2_MODE_Pos 0 /*!< SCU SFSP2_2: MODE Position */ #define SCU_SFSP2_2_MODE_Msk (0x07UL << SCU_SFSP2_2_MODE_Pos) /*!< SCU SFSP2_2: MODE Mask */ #define SCU_SFSP2_2_EPD_Pos 3 /*!< SCU SFSP2_2: EPD Position */ #define SCU_SFSP2_2_EPD_Msk (0x01UL << SCU_SFSP2_2_EPD_Pos) /*!< SCU SFSP2_2: EPD Mask */ #define SCU_SFSP2_2_EPUN_Pos 4 /*!< SCU SFSP2_2: EPUN Position */ #define SCU_SFSP2_2_EPUN_Msk (0x01UL << SCU_SFSP2_2_EPUN_Pos) /*!< SCU SFSP2_2: EPUN Mask */ #define SCU_SFSP2_2_EHS_Pos 5 /*!< SCU SFSP2_2: EHS Position */ #define SCU_SFSP2_2_EHS_Msk (0x01UL << SCU_SFSP2_2_EHS_Pos) /*!< SCU SFSP2_2: EHS Mask */ #define SCU_SFSP2_2_EZI_Pos 6 /*!< SCU SFSP2_2: EZI Position */ #define SCU_SFSP2_2_EZI_Msk (0x01UL << SCU_SFSP2_2_EZI_Pos) /*!< SCU SFSP2_2: EZI Mask */ #define SCU_SFSP2_2_ZIF_Pos 7 /*!< SCU SFSP2_2: ZIF Position */ #define SCU_SFSP2_2_ZIF_Msk (0x01UL << SCU_SFSP2_2_ZIF_Pos) /*!< SCU SFSP2_2: ZIF Mask */ /* --------------------------------- SCU_SFSP2_3 -------------------------------- */ #define SCU_SFSP2_3_MODE_Pos 0 /*!< SCU SFSP2_3: MODE Position */ #define SCU_SFSP2_3_MODE_Msk (0x07UL << SCU_SFSP2_3_MODE_Pos) /*!< SCU SFSP2_3: MODE Mask */ #define SCU_SFSP2_3_EPD_Pos 3 /*!< SCU SFSP2_3: EPD Position */ #define SCU_SFSP2_3_EPD_Msk (0x01UL << SCU_SFSP2_3_EPD_Pos) /*!< SCU SFSP2_3: EPD Mask */ #define SCU_SFSP2_3_EPUN_Pos 4 /*!< SCU SFSP2_3: EPUN Position */ #define SCU_SFSP2_3_EPUN_Msk (0x01UL << SCU_SFSP2_3_EPUN_Pos) /*!< SCU SFSP2_3: EPUN Mask */ #define SCU_SFSP2_3_EZI_Pos 6 /*!< SCU SFSP2_3: EZI Position */ #define SCU_SFSP2_3_EZI_Msk (0x01UL << SCU_SFSP2_3_EZI_Pos) /*!< SCU SFSP2_3: EZI Mask */ #define SCU_SFSP2_3_ZIF_Pos 7 /*!< SCU SFSP2_3: ZIF Position */ #define SCU_SFSP2_3_ZIF_Msk (0x01UL << SCU_SFSP2_3_ZIF_Pos) /*!< SCU SFSP2_3: ZIF Mask */ #define SCU_SFSP2_3_EHD_Pos 8 /*!< SCU SFSP2_3: EHD Position */ #define SCU_SFSP2_3_EHD_Msk (0x03UL << SCU_SFSP2_3_EHD_Pos) /*!< SCU SFSP2_3: EHD Mask */ /* --------------------------------- SCU_SFSP2_4 -------------------------------- */ #define SCU_SFSP2_4_MODE_Pos 0 /*!< SCU SFSP2_4: MODE Position */ #define SCU_SFSP2_4_MODE_Msk (0x07UL << SCU_SFSP2_4_MODE_Pos) /*!< SCU SFSP2_4: MODE Mask */ #define SCU_SFSP2_4_EPD_Pos 3 /*!< SCU SFSP2_4: EPD Position */ #define SCU_SFSP2_4_EPD_Msk (0x01UL << SCU_SFSP2_4_EPD_Pos) /*!< SCU SFSP2_4: EPD Mask */ #define SCU_SFSP2_4_EPUN_Pos 4 /*!< SCU SFSP2_4: EPUN Position */ #define SCU_SFSP2_4_EPUN_Msk (0x01UL << SCU_SFSP2_4_EPUN_Pos) /*!< SCU SFSP2_4: EPUN Mask */ #define SCU_SFSP2_4_EZI_Pos 6 /*!< SCU SFSP2_4: EZI Position */ #define SCU_SFSP2_4_EZI_Msk (0x01UL << SCU_SFSP2_4_EZI_Pos) /*!< SCU SFSP2_4: EZI Mask */ #define SCU_SFSP2_4_ZIF_Pos 7 /*!< SCU SFSP2_4: ZIF Position */ #define SCU_SFSP2_4_ZIF_Msk (0x01UL << SCU_SFSP2_4_ZIF_Pos) /*!< SCU SFSP2_4: ZIF Mask */ #define SCU_SFSP2_4_EHD_Pos 8 /*!< SCU SFSP2_4: EHD Position */ #define SCU_SFSP2_4_EHD_Msk (0x03UL << SCU_SFSP2_4_EHD_Pos) /*!< SCU SFSP2_4: EHD Mask */ /* --------------------------------- SCU_SFSP2_5 -------------------------------- */ #define SCU_SFSP2_5_MODE_Pos 0 /*!< SCU SFSP2_5: MODE Position */ #define SCU_SFSP2_5_MODE_Msk (0x07UL << SCU_SFSP2_5_MODE_Pos) /*!< SCU SFSP2_5: MODE Mask */ #define SCU_SFSP2_5_EPD_Pos 3 /*!< SCU SFSP2_5: EPD Position */ #define SCU_SFSP2_5_EPD_Msk (0x01UL << SCU_SFSP2_5_EPD_Pos) /*!< SCU SFSP2_5: EPD Mask */ #define SCU_SFSP2_5_EPUN_Pos 4 /*!< SCU SFSP2_5: EPUN Position */ #define SCU_SFSP2_5_EPUN_Msk (0x01UL << SCU_SFSP2_5_EPUN_Pos) /*!< SCU SFSP2_5: EPUN Mask */ #define SCU_SFSP2_5_EZI_Pos 6 /*!< SCU SFSP2_5: EZI Position */ #define SCU_SFSP2_5_EZI_Msk (0x01UL << SCU_SFSP2_5_EZI_Pos) /*!< SCU SFSP2_5: EZI Mask */ #define SCU_SFSP2_5_ZIF_Pos 7 /*!< SCU SFSP2_5: ZIF Position */ #define SCU_SFSP2_5_ZIF_Msk (0x01UL << SCU_SFSP2_5_ZIF_Pos) /*!< SCU SFSP2_5: ZIF Mask */ #define SCU_SFSP2_5_EHD_Pos 8 /*!< SCU SFSP2_5: EHD Position */ #define SCU_SFSP2_5_EHD_Msk (0x03UL << SCU_SFSP2_5_EHD_Pos) /*!< SCU SFSP2_5: EHD Mask */ /* --------------------------------- SCU_SFSP2_6 -------------------------------- */ #define SCU_SFSP2_6_MODE_Pos 0 /*!< SCU SFSP2_6: MODE Position */ #define SCU_SFSP2_6_MODE_Msk (0x07UL << SCU_SFSP2_6_MODE_Pos) /*!< SCU SFSP2_6: MODE Mask */ #define SCU_SFSP2_6_EPD_Pos 3 /*!< SCU SFSP2_6: EPD Position */ #define SCU_SFSP2_6_EPD_Msk (0x01UL << SCU_SFSP2_6_EPD_Pos) /*!< SCU SFSP2_6: EPD Mask */ #define SCU_SFSP2_6_EPUN_Pos 4 /*!< SCU SFSP2_6: EPUN Position */ #define SCU_SFSP2_6_EPUN_Msk (0x01UL << SCU_SFSP2_6_EPUN_Pos) /*!< SCU SFSP2_6: EPUN Mask */ #define SCU_SFSP2_6_EHS_Pos 5 /*!< SCU SFSP2_6: EHS Position */ #define SCU_SFSP2_6_EHS_Msk (0x01UL << SCU_SFSP2_6_EHS_Pos) /*!< SCU SFSP2_6: EHS Mask */ #define SCU_SFSP2_6_EZI_Pos 6 /*!< SCU SFSP2_6: EZI Position */ #define SCU_SFSP2_6_EZI_Msk (0x01UL << SCU_SFSP2_6_EZI_Pos) /*!< SCU SFSP2_6: EZI Mask */ #define SCU_SFSP2_6_ZIF_Pos 7 /*!< SCU SFSP2_6: ZIF Position */ #define SCU_SFSP2_6_ZIF_Msk (0x01UL << SCU_SFSP2_6_ZIF_Pos) /*!< SCU SFSP2_6: ZIF Mask */ /* --------------------------------- SCU_SFSP2_7 -------------------------------- */ #define SCU_SFSP2_7_MODE_Pos 0 /*!< SCU SFSP2_7: MODE Position */ #define SCU_SFSP2_7_MODE_Msk (0x07UL << SCU_SFSP2_7_MODE_Pos) /*!< SCU SFSP2_7: MODE Mask */ #define SCU_SFSP2_7_EPD_Pos 3 /*!< SCU SFSP2_7: EPD Position */ #define SCU_SFSP2_7_EPD_Msk (0x01UL << SCU_SFSP2_7_EPD_Pos) /*!< SCU SFSP2_7: EPD Mask */ #define SCU_SFSP2_7_EPUN_Pos 4 /*!< SCU SFSP2_7: EPUN Position */ #define SCU_SFSP2_7_EPUN_Msk (0x01UL << SCU_SFSP2_7_EPUN_Pos) /*!< SCU SFSP2_7: EPUN Mask */ #define SCU_SFSP2_7_EHS_Pos 5 /*!< SCU SFSP2_7: EHS Position */ #define SCU_SFSP2_7_EHS_Msk (0x01UL << SCU_SFSP2_7_EHS_Pos) /*!< SCU SFSP2_7: EHS Mask */ #define SCU_SFSP2_7_EZI_Pos 6 /*!< SCU SFSP2_7: EZI Position */ #define SCU_SFSP2_7_EZI_Msk (0x01UL << SCU_SFSP2_7_EZI_Pos) /*!< SCU SFSP2_7: EZI Mask */ #define SCU_SFSP2_7_ZIF_Pos 7 /*!< SCU SFSP2_7: ZIF Position */ #define SCU_SFSP2_7_ZIF_Msk (0x01UL << SCU_SFSP2_7_ZIF_Pos) /*!< SCU SFSP2_7: ZIF Mask */ /* --------------------------------- SCU_SFSP2_8 -------------------------------- */ #define SCU_SFSP2_8_MODE_Pos 0 /*!< SCU SFSP2_8: MODE Position */ #define SCU_SFSP2_8_MODE_Msk (0x07UL << SCU_SFSP2_8_MODE_Pos) /*!< SCU SFSP2_8: MODE Mask */ #define SCU_SFSP2_8_EPD_Pos 3 /*!< SCU SFSP2_8: EPD Position */ #define SCU_SFSP2_8_EPD_Msk (0x01UL << SCU_SFSP2_8_EPD_Pos) /*!< SCU SFSP2_8: EPD Mask */ #define SCU_SFSP2_8_EPUN_Pos 4 /*!< SCU SFSP2_8: EPUN Position */ #define SCU_SFSP2_8_EPUN_Msk (0x01UL << SCU_SFSP2_8_EPUN_Pos) /*!< SCU SFSP2_8: EPUN Mask */ #define SCU_SFSP2_8_EHS_Pos 5 /*!< SCU SFSP2_8: EHS Position */ #define SCU_SFSP2_8_EHS_Msk (0x01UL << SCU_SFSP2_8_EHS_Pos) /*!< SCU SFSP2_8: EHS Mask */ #define SCU_SFSP2_8_EZI_Pos 6 /*!< SCU SFSP2_8: EZI Position */ #define SCU_SFSP2_8_EZI_Msk (0x01UL << SCU_SFSP2_8_EZI_Pos) /*!< SCU SFSP2_8: EZI Mask */ #define SCU_SFSP2_8_ZIF_Pos 7 /*!< SCU SFSP2_8: ZIF Position */ #define SCU_SFSP2_8_ZIF_Msk (0x01UL << SCU_SFSP2_8_ZIF_Pos) /*!< SCU SFSP2_8: ZIF Mask */ /* --------------------------------- SCU_SFSP2_9 -------------------------------- */ #define SCU_SFSP2_9_MODE_Pos 0 /*!< SCU SFSP2_9: MODE Position */ #define SCU_SFSP2_9_MODE_Msk (0x07UL << SCU_SFSP2_9_MODE_Pos) /*!< SCU SFSP2_9: MODE Mask */ #define SCU_SFSP2_9_EPD_Pos 3 /*!< SCU SFSP2_9: EPD Position */ #define SCU_SFSP2_9_EPD_Msk (0x01UL << SCU_SFSP2_9_EPD_Pos) /*!< SCU SFSP2_9: EPD Mask */ #define SCU_SFSP2_9_EPUN_Pos 4 /*!< SCU SFSP2_9: EPUN Position */ #define SCU_SFSP2_9_EPUN_Msk (0x01UL << SCU_SFSP2_9_EPUN_Pos) /*!< SCU SFSP2_9: EPUN Mask */ #define SCU_SFSP2_9_EHS_Pos 5 /*!< SCU SFSP2_9: EHS Position */ #define SCU_SFSP2_9_EHS_Msk (0x01UL << SCU_SFSP2_9_EHS_Pos) /*!< SCU SFSP2_9: EHS Mask */ #define SCU_SFSP2_9_EZI_Pos 6 /*!< SCU SFSP2_9: EZI Position */ #define SCU_SFSP2_9_EZI_Msk (0x01UL << SCU_SFSP2_9_EZI_Pos) /*!< SCU SFSP2_9: EZI Mask */ #define SCU_SFSP2_9_ZIF_Pos 7 /*!< SCU SFSP2_9: ZIF Position */ #define SCU_SFSP2_9_ZIF_Msk (0x01UL << SCU_SFSP2_9_ZIF_Pos) /*!< SCU SFSP2_9: ZIF Mask */ /* -------------------------------- SCU_SFSP2_10 -------------------------------- */ #define SCU_SFSP2_10_MODE_Pos 0 /*!< SCU SFSP2_10: MODE Position */ #define SCU_SFSP2_10_MODE_Msk (0x07UL << SCU_SFSP2_10_MODE_Pos) /*!< SCU SFSP2_10: MODE Mask */ #define SCU_SFSP2_10_EPD_Pos 3 /*!< SCU SFSP2_10: EPD Position */ #define SCU_SFSP2_10_EPD_Msk (0x01UL << SCU_SFSP2_10_EPD_Pos) /*!< SCU SFSP2_10: EPD Mask */ #define SCU_SFSP2_10_EPUN_Pos 4 /*!< SCU SFSP2_10: EPUN Position */ #define SCU_SFSP2_10_EPUN_Msk (0x01UL << SCU_SFSP2_10_EPUN_Pos) /*!< SCU SFSP2_10: EPUN Mask */ #define SCU_SFSP2_10_EHS_Pos 5 /*!< SCU SFSP2_10: EHS Position */ #define SCU_SFSP2_10_EHS_Msk (0x01UL << SCU_SFSP2_10_EHS_Pos) /*!< SCU SFSP2_10: EHS Mask */ #define SCU_SFSP2_10_EZI_Pos 6 /*!< SCU SFSP2_10: EZI Position */ #define SCU_SFSP2_10_EZI_Msk (0x01UL << SCU_SFSP2_10_EZI_Pos) /*!< SCU SFSP2_10: EZI Mask */ #define SCU_SFSP2_10_ZIF_Pos 7 /*!< SCU SFSP2_10: ZIF Position */ #define SCU_SFSP2_10_ZIF_Msk (0x01UL << SCU_SFSP2_10_ZIF_Pos) /*!< SCU SFSP2_10: ZIF Mask */ /* -------------------------------- SCU_SFSP2_11 -------------------------------- */ #define SCU_SFSP2_11_MODE_Pos 0 /*!< SCU SFSP2_11: MODE Position */ #define SCU_SFSP2_11_MODE_Msk (0x07UL << SCU_SFSP2_11_MODE_Pos) /*!< SCU SFSP2_11: MODE Mask */ #define SCU_SFSP2_11_EPD_Pos 3 /*!< SCU SFSP2_11: EPD Position */ #define SCU_SFSP2_11_EPD_Msk (0x01UL << SCU_SFSP2_11_EPD_Pos) /*!< SCU SFSP2_11: EPD Mask */ #define SCU_SFSP2_11_EPUN_Pos 4 /*!< SCU SFSP2_11: EPUN Position */ #define SCU_SFSP2_11_EPUN_Msk (0x01UL << SCU_SFSP2_11_EPUN_Pos) /*!< SCU SFSP2_11: EPUN Mask */ #define SCU_SFSP2_11_EHS_Pos 5 /*!< SCU SFSP2_11: EHS Position */ #define SCU_SFSP2_11_EHS_Msk (0x01UL << SCU_SFSP2_11_EHS_Pos) /*!< SCU SFSP2_11: EHS Mask */ #define SCU_SFSP2_11_EZI_Pos 6 /*!< SCU SFSP2_11: EZI Position */ #define SCU_SFSP2_11_EZI_Msk (0x01UL << SCU_SFSP2_11_EZI_Pos) /*!< SCU SFSP2_11: EZI Mask */ #define SCU_SFSP2_11_ZIF_Pos 7 /*!< SCU SFSP2_11: ZIF Position */ #define SCU_SFSP2_11_ZIF_Msk (0x01UL << SCU_SFSP2_11_ZIF_Pos) /*!< SCU SFSP2_11: ZIF Mask */ /* -------------------------------- SCU_SFSP2_12 -------------------------------- */ #define SCU_SFSP2_12_MODE_Pos 0 /*!< SCU SFSP2_12: MODE Position */ #define SCU_SFSP2_12_MODE_Msk (0x07UL << SCU_SFSP2_12_MODE_Pos) /*!< SCU SFSP2_12: MODE Mask */ #define SCU_SFSP2_12_EPD_Pos 3 /*!< SCU SFSP2_12: EPD Position */ #define SCU_SFSP2_12_EPD_Msk (0x01UL << SCU_SFSP2_12_EPD_Pos) /*!< SCU SFSP2_12: EPD Mask */ #define SCU_SFSP2_12_EPUN_Pos 4 /*!< SCU SFSP2_12: EPUN Position */ #define SCU_SFSP2_12_EPUN_Msk (0x01UL << SCU_SFSP2_12_EPUN_Pos) /*!< SCU SFSP2_12: EPUN Mask */ #define SCU_SFSP2_12_EHS_Pos 5 /*!< SCU SFSP2_12: EHS Position */ #define SCU_SFSP2_12_EHS_Msk (0x01UL << SCU_SFSP2_12_EHS_Pos) /*!< SCU SFSP2_12: EHS Mask */ #define SCU_SFSP2_12_EZI_Pos 6 /*!< SCU SFSP2_12: EZI Position */ #define SCU_SFSP2_12_EZI_Msk (0x01UL << SCU_SFSP2_12_EZI_Pos) /*!< SCU SFSP2_12: EZI Mask */ #define SCU_SFSP2_12_ZIF_Pos 7 /*!< SCU SFSP2_12: ZIF Position */ #define SCU_SFSP2_12_ZIF_Msk (0x01UL << SCU_SFSP2_12_ZIF_Pos) /*!< SCU SFSP2_12: ZIF Mask */ /* -------------------------------- SCU_SFSP2_13 -------------------------------- */ #define SCU_SFSP2_13_MODE_Pos 0 /*!< SCU SFSP2_13: MODE Position */ #define SCU_SFSP2_13_MODE_Msk (0x07UL << SCU_SFSP2_13_MODE_Pos) /*!< SCU SFSP2_13: MODE Mask */ #define SCU_SFSP2_13_EPD_Pos 3 /*!< SCU SFSP2_13: EPD Position */ #define SCU_SFSP2_13_EPD_Msk (0x01UL << SCU_SFSP2_13_EPD_Pos) /*!< SCU SFSP2_13: EPD Mask */ #define SCU_SFSP2_13_EPUN_Pos 4 /*!< SCU SFSP2_13: EPUN Position */ #define SCU_SFSP2_13_EPUN_Msk (0x01UL << SCU_SFSP2_13_EPUN_Pos) /*!< SCU SFSP2_13: EPUN Mask */ #define SCU_SFSP2_13_EHS_Pos 5 /*!< SCU SFSP2_13: EHS Position */ #define SCU_SFSP2_13_EHS_Msk (0x01UL << SCU_SFSP2_13_EHS_Pos) /*!< SCU SFSP2_13: EHS Mask */ #define SCU_SFSP2_13_EZI_Pos 6 /*!< SCU SFSP2_13: EZI Position */ #define SCU_SFSP2_13_EZI_Msk (0x01UL << SCU_SFSP2_13_EZI_Pos) /*!< SCU SFSP2_13: EZI Mask */ #define SCU_SFSP2_13_ZIF_Pos 7 /*!< SCU SFSP2_13: ZIF Position */ #define SCU_SFSP2_13_ZIF_Msk (0x01UL << SCU_SFSP2_13_ZIF_Pos) /*!< SCU SFSP2_13: ZIF Mask */ /* --------------------------------- SCU_SFSP3_0 -------------------------------- */ #define SCU_SFSP3_0_MODE_Pos 0 /*!< SCU SFSP3_0: MODE Position */ #define SCU_SFSP3_0_MODE_Msk (0x07UL << SCU_SFSP3_0_MODE_Pos) /*!< SCU SFSP3_0: MODE Mask */ #define SCU_SFSP3_0_EPD_Pos 3 /*!< SCU SFSP3_0: EPD Position */ #define SCU_SFSP3_0_EPD_Msk (0x01UL << SCU_SFSP3_0_EPD_Pos) /*!< SCU SFSP3_0: EPD Mask */ #define SCU_SFSP3_0_EPUN_Pos 4 /*!< SCU SFSP3_0: EPUN Position */ #define SCU_SFSP3_0_EPUN_Msk (0x01UL << SCU_SFSP3_0_EPUN_Pos) /*!< SCU SFSP3_0: EPUN Mask */ #define SCU_SFSP3_0_EHS_Pos 5 /*!< SCU SFSP3_0: EHS Position */ #define SCU_SFSP3_0_EHS_Msk (0x01UL << SCU_SFSP3_0_EHS_Pos) /*!< SCU SFSP3_0: EHS Mask */ #define SCU_SFSP3_0_EZI_Pos 6 /*!< SCU SFSP3_0: EZI Position */ #define SCU_SFSP3_0_EZI_Msk (0x01UL << SCU_SFSP3_0_EZI_Pos) /*!< SCU SFSP3_0: EZI Mask */ #define SCU_SFSP3_0_ZIF_Pos 7 /*!< SCU SFSP3_0: ZIF Position */ #define SCU_SFSP3_0_ZIF_Msk (0x01UL << SCU_SFSP3_0_ZIF_Pos) /*!< SCU SFSP3_0: ZIF Mask */ /* --------------------------------- SCU_SFSP3_1 -------------------------------- */ #define SCU_SFSP3_1_MODE_Pos 0 /*!< SCU SFSP3_1: MODE Position */ #define SCU_SFSP3_1_MODE_Msk (0x07UL << SCU_SFSP3_1_MODE_Pos) /*!< SCU SFSP3_1: MODE Mask */ #define SCU_SFSP3_1_EPD_Pos 3 /*!< SCU SFSP3_1: EPD Position */ #define SCU_SFSP3_1_EPD_Msk (0x01UL << SCU_SFSP3_1_EPD_Pos) /*!< SCU SFSP3_1: EPD Mask */ #define SCU_SFSP3_1_EPUN_Pos 4 /*!< SCU SFSP3_1: EPUN Position */ #define SCU_SFSP3_1_EPUN_Msk (0x01UL << SCU_SFSP3_1_EPUN_Pos) /*!< SCU SFSP3_1: EPUN Mask */ #define SCU_SFSP3_1_EHS_Pos 5 /*!< SCU SFSP3_1: EHS Position */ #define SCU_SFSP3_1_EHS_Msk (0x01UL << SCU_SFSP3_1_EHS_Pos) /*!< SCU SFSP3_1: EHS Mask */ #define SCU_SFSP3_1_EZI_Pos 6 /*!< SCU SFSP3_1: EZI Position */ #define SCU_SFSP3_1_EZI_Msk (0x01UL << SCU_SFSP3_1_EZI_Pos) /*!< SCU SFSP3_1: EZI Mask */ #define SCU_SFSP3_1_ZIF_Pos 7 /*!< SCU SFSP3_1: ZIF Position */ #define SCU_SFSP3_1_ZIF_Msk (0x01UL << SCU_SFSP3_1_ZIF_Pos) /*!< SCU SFSP3_1: ZIF Mask */ /* --------------------------------- SCU_SFSP3_2 -------------------------------- */ #define SCU_SFSP3_2_MODE_Pos 0 /*!< SCU SFSP3_2: MODE Position */ #define SCU_SFSP3_2_MODE_Msk (0x07UL << SCU_SFSP3_2_MODE_Pos) /*!< SCU SFSP3_2: MODE Mask */ #define SCU_SFSP3_2_EPD_Pos 3 /*!< SCU SFSP3_2: EPD Position */ #define SCU_SFSP3_2_EPD_Msk (0x01UL << SCU_SFSP3_2_EPD_Pos) /*!< SCU SFSP3_2: EPD Mask */ #define SCU_SFSP3_2_EPUN_Pos 4 /*!< SCU SFSP3_2: EPUN Position */ #define SCU_SFSP3_2_EPUN_Msk (0x01UL << SCU_SFSP3_2_EPUN_Pos) /*!< SCU SFSP3_2: EPUN Mask */ #define SCU_SFSP3_2_EHS_Pos 5 /*!< SCU SFSP3_2: EHS Position */ #define SCU_SFSP3_2_EHS_Msk (0x01UL << SCU_SFSP3_2_EHS_Pos) /*!< SCU SFSP3_2: EHS Mask */ #define SCU_SFSP3_2_EZI_Pos 6 /*!< SCU SFSP3_2: EZI Position */ #define SCU_SFSP3_2_EZI_Msk (0x01UL << SCU_SFSP3_2_EZI_Pos) /*!< SCU SFSP3_2: EZI Mask */ #define SCU_SFSP3_2_ZIF_Pos 7 /*!< SCU SFSP3_2: ZIF Position */ #define SCU_SFSP3_2_ZIF_Msk (0x01UL << SCU_SFSP3_2_ZIF_Pos) /*!< SCU SFSP3_2: ZIF Mask */ /* --------------------------------- SCU_SFSP3_3 -------------------------------- */ #define SCU_SFSP3_3_MODE_Pos 0 /*!< SCU SFSP3_3: MODE Position */ #define SCU_SFSP3_3_MODE_Msk (0x07UL << SCU_SFSP3_3_MODE_Pos) /*!< SCU SFSP3_3: MODE Mask */ #define SCU_SFSP3_3_EPD_Pos 3 /*!< SCU SFSP3_3: EPD Position */ #define SCU_SFSP3_3_EPD_Msk (0x01UL << SCU_SFSP3_3_EPD_Pos) /*!< SCU SFSP3_3: EPD Mask */ #define SCU_SFSP3_3_EPUN_Pos 4 /*!< SCU SFSP3_3: EPUN Position */ #define SCU_SFSP3_3_EPUN_Msk (0x01UL << SCU_SFSP3_3_EPUN_Pos) /*!< SCU SFSP3_3: EPUN Mask */ #define SCU_SFSP3_3_EHS_Pos 5 /*!< SCU SFSP3_3: EHS Position */ #define SCU_SFSP3_3_EHS_Msk (0x01UL << SCU_SFSP3_3_EHS_Pos) /*!< SCU SFSP3_3: EHS Mask */ #define SCU_SFSP3_3_EZI_Pos 6 /*!< SCU SFSP3_3: EZI Position */ #define SCU_SFSP3_3_EZI_Msk (0x01UL << SCU_SFSP3_3_EZI_Pos) /*!< SCU SFSP3_3: EZI Mask */ #define SCU_SFSP3_3_ZIF_Pos 7 /*!< SCU SFSP3_3: ZIF Position */ #define SCU_SFSP3_3_ZIF_Msk (0x01UL << SCU_SFSP3_3_ZIF_Pos) /*!< SCU SFSP3_3: ZIF Mask */ /* --------------------------------- SCU_SFSP3_4 -------------------------------- */ #define SCU_SFSP3_4_MODE_Pos 0 /*!< SCU SFSP3_4: MODE Position */ #define SCU_SFSP3_4_MODE_Msk (0x07UL << SCU_SFSP3_4_MODE_Pos) /*!< SCU SFSP3_4: MODE Mask */ #define SCU_SFSP3_4_EPD_Pos 3 /*!< SCU SFSP3_4: EPD Position */ #define SCU_SFSP3_4_EPD_Msk (0x01UL << SCU_SFSP3_4_EPD_Pos) /*!< SCU SFSP3_4: EPD Mask */ #define SCU_SFSP3_4_EPUN_Pos 4 /*!< SCU SFSP3_4: EPUN Position */ #define SCU_SFSP3_4_EPUN_Msk (0x01UL << SCU_SFSP3_4_EPUN_Pos) /*!< SCU SFSP3_4: EPUN Mask */ #define SCU_SFSP3_4_EHS_Pos 5 /*!< SCU SFSP3_4: EHS Position */ #define SCU_SFSP3_4_EHS_Msk (0x01UL << SCU_SFSP3_4_EHS_Pos) /*!< SCU SFSP3_4: EHS Mask */ #define SCU_SFSP3_4_EZI_Pos 6 /*!< SCU SFSP3_4: EZI Position */ #define SCU_SFSP3_4_EZI_Msk (0x01UL << SCU_SFSP3_4_EZI_Pos) /*!< SCU SFSP3_4: EZI Mask */ #define SCU_SFSP3_4_ZIF_Pos 7 /*!< SCU SFSP3_4: ZIF Position */ #define SCU_SFSP3_4_ZIF_Msk (0x01UL << SCU_SFSP3_4_ZIF_Pos) /*!< SCU SFSP3_4: ZIF Mask */ /* --------------------------------- SCU_SFSP3_5 -------------------------------- */ #define SCU_SFSP3_5_MODE_Pos 0 /*!< SCU SFSP3_5: MODE Position */ #define SCU_SFSP3_5_MODE_Msk (0x07UL << SCU_SFSP3_5_MODE_Pos) /*!< SCU SFSP3_5: MODE Mask */ #define SCU_SFSP3_5_EPD_Pos 3 /*!< SCU SFSP3_5: EPD Position */ #define SCU_SFSP3_5_EPD_Msk (0x01UL << SCU_SFSP3_5_EPD_Pos) /*!< SCU SFSP3_5: EPD Mask */ #define SCU_SFSP3_5_EPUN_Pos 4 /*!< SCU SFSP3_5: EPUN Position */ #define SCU_SFSP3_5_EPUN_Msk (0x01UL << SCU_SFSP3_5_EPUN_Pos) /*!< SCU SFSP3_5: EPUN Mask */ #define SCU_SFSP3_5_EHS_Pos 5 /*!< SCU SFSP3_5: EHS Position */ #define SCU_SFSP3_5_EHS_Msk (0x01UL << SCU_SFSP3_5_EHS_Pos) /*!< SCU SFSP3_5: EHS Mask */ #define SCU_SFSP3_5_EZI_Pos 6 /*!< SCU SFSP3_5: EZI Position */ #define SCU_SFSP3_5_EZI_Msk (0x01UL << SCU_SFSP3_5_EZI_Pos) /*!< SCU SFSP3_5: EZI Mask */ #define SCU_SFSP3_5_ZIF_Pos 7 /*!< SCU SFSP3_5: ZIF Position */ #define SCU_SFSP3_5_ZIF_Msk (0x01UL << SCU_SFSP3_5_ZIF_Pos) /*!< SCU SFSP3_5: ZIF Mask */ /* --------------------------------- SCU_SFSP3_6 -------------------------------- */ #define SCU_SFSP3_6_MODE_Pos 0 /*!< SCU SFSP3_6: MODE Position */ #define SCU_SFSP3_6_MODE_Msk (0x07UL << SCU_SFSP3_6_MODE_Pos) /*!< SCU SFSP3_6: MODE Mask */ #define SCU_SFSP3_6_EPD_Pos 3 /*!< SCU SFSP3_6: EPD Position */ #define SCU_SFSP3_6_EPD_Msk (0x01UL << SCU_SFSP3_6_EPD_Pos) /*!< SCU SFSP3_6: EPD Mask */ #define SCU_SFSP3_6_EPUN_Pos 4 /*!< SCU SFSP3_6: EPUN Position */ #define SCU_SFSP3_6_EPUN_Msk (0x01UL << SCU_SFSP3_6_EPUN_Pos) /*!< SCU SFSP3_6: EPUN Mask */ #define SCU_SFSP3_6_EHS_Pos 5 /*!< SCU SFSP3_6: EHS Position */ #define SCU_SFSP3_6_EHS_Msk (0x01UL << SCU_SFSP3_6_EHS_Pos) /*!< SCU SFSP3_6: EHS Mask */ #define SCU_SFSP3_6_EZI_Pos 6 /*!< SCU SFSP3_6: EZI Position */ #define SCU_SFSP3_6_EZI_Msk (0x01UL << SCU_SFSP3_6_EZI_Pos) /*!< SCU SFSP3_6: EZI Mask */ #define SCU_SFSP3_6_ZIF_Pos 7 /*!< SCU SFSP3_6: ZIF Position */ #define SCU_SFSP3_6_ZIF_Msk (0x01UL << SCU_SFSP3_6_ZIF_Pos) /*!< SCU SFSP3_6: ZIF Mask */ /* --------------------------------- SCU_SFSP3_7 -------------------------------- */ #define SCU_SFSP3_7_MODE_Pos 0 /*!< SCU SFSP3_7: MODE Position */ #define SCU_SFSP3_7_MODE_Msk (0x07UL << SCU_SFSP3_7_MODE_Pos) /*!< SCU SFSP3_7: MODE Mask */ #define SCU_SFSP3_7_EPD_Pos 3 /*!< SCU SFSP3_7: EPD Position */ #define SCU_SFSP3_7_EPD_Msk (0x01UL << SCU_SFSP3_7_EPD_Pos) /*!< SCU SFSP3_7: EPD Mask */ #define SCU_SFSP3_7_EPUN_Pos 4 /*!< SCU SFSP3_7: EPUN Position */ #define SCU_SFSP3_7_EPUN_Msk (0x01UL << SCU_SFSP3_7_EPUN_Pos) /*!< SCU SFSP3_7: EPUN Mask */ #define SCU_SFSP3_7_EHS_Pos 5 /*!< SCU SFSP3_7: EHS Position */ #define SCU_SFSP3_7_EHS_Msk (0x01UL << SCU_SFSP3_7_EHS_Pos) /*!< SCU SFSP3_7: EHS Mask */ #define SCU_SFSP3_7_EZI_Pos 6 /*!< SCU SFSP3_7: EZI Position */ #define SCU_SFSP3_7_EZI_Msk (0x01UL << SCU_SFSP3_7_EZI_Pos) /*!< SCU SFSP3_7: EZI Mask */ #define SCU_SFSP3_7_ZIF_Pos 7 /*!< SCU SFSP3_7: ZIF Position */ #define SCU_SFSP3_7_ZIF_Msk (0x01UL << SCU_SFSP3_7_ZIF_Pos) /*!< SCU SFSP3_7: ZIF Mask */ /* --------------------------------- SCU_SFSP3_8 -------------------------------- */ #define SCU_SFSP3_8_MODE_Pos 0 /*!< SCU SFSP3_8: MODE Position */ #define SCU_SFSP3_8_MODE_Msk (0x07UL << SCU_SFSP3_8_MODE_Pos) /*!< SCU SFSP3_8: MODE Mask */ #define SCU_SFSP3_8_EPD_Pos 3 /*!< SCU SFSP3_8: EPD Position */ #define SCU_SFSP3_8_EPD_Msk (0x01UL << SCU_SFSP3_8_EPD_Pos) /*!< SCU SFSP3_8: EPD Mask */ #define SCU_SFSP3_8_EPUN_Pos 4 /*!< SCU SFSP3_8: EPUN Position */ #define SCU_SFSP3_8_EPUN_Msk (0x01UL << SCU_SFSP3_8_EPUN_Pos) /*!< SCU SFSP3_8: EPUN Mask */ #define SCU_SFSP3_8_EHS_Pos 5 /*!< SCU SFSP3_8: EHS Position */ #define SCU_SFSP3_8_EHS_Msk (0x01UL << SCU_SFSP3_8_EHS_Pos) /*!< SCU SFSP3_8: EHS Mask */ #define SCU_SFSP3_8_EZI_Pos 6 /*!< SCU SFSP3_8: EZI Position */ #define SCU_SFSP3_8_EZI_Msk (0x01UL << SCU_SFSP3_8_EZI_Pos) /*!< SCU SFSP3_8: EZI Mask */ #define SCU_SFSP3_8_ZIF_Pos 7 /*!< SCU SFSP3_8: ZIF Position */ #define SCU_SFSP3_8_ZIF_Msk (0x01UL << SCU_SFSP3_8_ZIF_Pos) /*!< SCU SFSP3_8: ZIF Mask */ /* --------------------------------- SCU_SFSP4_0 -------------------------------- */ #define SCU_SFSP4_0_MODE_Pos 0 /*!< SCU SFSP4_0: MODE Position */ #define SCU_SFSP4_0_MODE_Msk (0x07UL << SCU_SFSP4_0_MODE_Pos) /*!< SCU SFSP4_0: MODE Mask */ #define SCU_SFSP4_0_EPD_Pos 3 /*!< SCU SFSP4_0: EPD Position */ #define SCU_SFSP4_0_EPD_Msk (0x01UL << SCU_SFSP4_0_EPD_Pos) /*!< SCU SFSP4_0: EPD Mask */ #define SCU_SFSP4_0_EPUN_Pos 4 /*!< SCU SFSP4_0: EPUN Position */ #define SCU_SFSP4_0_EPUN_Msk (0x01UL << SCU_SFSP4_0_EPUN_Pos) /*!< SCU SFSP4_0: EPUN Mask */ #define SCU_SFSP4_0_EHS_Pos 5 /*!< SCU SFSP4_0: EHS Position */ #define SCU_SFSP4_0_EHS_Msk (0x01UL << SCU_SFSP4_0_EHS_Pos) /*!< SCU SFSP4_0: EHS Mask */ #define SCU_SFSP4_0_EZI_Pos 6 /*!< SCU SFSP4_0: EZI Position */ #define SCU_SFSP4_0_EZI_Msk (0x01UL << SCU_SFSP4_0_EZI_Pos) /*!< SCU SFSP4_0: EZI Mask */ #define SCU_SFSP4_0_ZIF_Pos 7 /*!< SCU SFSP4_0: ZIF Position */ #define SCU_SFSP4_0_ZIF_Msk (0x01UL << SCU_SFSP4_0_ZIF_Pos) /*!< SCU SFSP4_0: ZIF Mask */ /* --------------------------------- SCU_SFSP4_1 -------------------------------- */ #define SCU_SFSP4_1_MODE_Pos 0 /*!< SCU SFSP4_1: MODE Position */ #define SCU_SFSP4_1_MODE_Msk (0x07UL << SCU_SFSP4_1_MODE_Pos) /*!< SCU SFSP4_1: MODE Mask */ #define SCU_SFSP4_1_EPD_Pos 3 /*!< SCU SFSP4_1: EPD Position */ #define SCU_SFSP4_1_EPD_Msk (0x01UL << SCU_SFSP4_1_EPD_Pos) /*!< SCU SFSP4_1: EPD Mask */ #define SCU_SFSP4_1_EPUN_Pos 4 /*!< SCU SFSP4_1: EPUN Position */ #define SCU_SFSP4_1_EPUN_Msk (0x01UL << SCU_SFSP4_1_EPUN_Pos) /*!< SCU SFSP4_1: EPUN Mask */ #define SCU_SFSP4_1_EHS_Pos 5 /*!< SCU SFSP4_1: EHS Position */ #define SCU_SFSP4_1_EHS_Msk (0x01UL << SCU_SFSP4_1_EHS_Pos) /*!< SCU SFSP4_1: EHS Mask */ #define SCU_SFSP4_1_EZI_Pos 6 /*!< SCU SFSP4_1: EZI Position */ #define SCU_SFSP4_1_EZI_Msk (0x01UL << SCU_SFSP4_1_EZI_Pos) /*!< SCU SFSP4_1: EZI Mask */ #define SCU_SFSP4_1_ZIF_Pos 7 /*!< SCU SFSP4_1: ZIF Position */ #define SCU_SFSP4_1_ZIF_Msk (0x01UL << SCU_SFSP4_1_ZIF_Pos) /*!< SCU SFSP4_1: ZIF Mask */ /* --------------------------------- SCU_SFSP4_2 -------------------------------- */ #define SCU_SFSP4_2_MODE_Pos 0 /*!< SCU SFSP4_2: MODE Position */ #define SCU_SFSP4_2_MODE_Msk (0x07UL << SCU_SFSP4_2_MODE_Pos) /*!< SCU SFSP4_2: MODE Mask */ #define SCU_SFSP4_2_EPD_Pos 3 /*!< SCU SFSP4_2: EPD Position */ #define SCU_SFSP4_2_EPD_Msk (0x01UL << SCU_SFSP4_2_EPD_Pos) /*!< SCU SFSP4_2: EPD Mask */ #define SCU_SFSP4_2_EPUN_Pos 4 /*!< SCU SFSP4_2: EPUN Position */ #define SCU_SFSP4_2_EPUN_Msk (0x01UL << SCU_SFSP4_2_EPUN_Pos) /*!< SCU SFSP4_2: EPUN Mask */ #define SCU_SFSP4_2_EHS_Pos 5 /*!< SCU SFSP4_2: EHS Position */ #define SCU_SFSP4_2_EHS_Msk (0x01UL << SCU_SFSP4_2_EHS_Pos) /*!< SCU SFSP4_2: EHS Mask */ #define SCU_SFSP4_2_EZI_Pos 6 /*!< SCU SFSP4_2: EZI Position */ #define SCU_SFSP4_2_EZI_Msk (0x01UL << SCU_SFSP4_2_EZI_Pos) /*!< SCU SFSP4_2: EZI Mask */ #define SCU_SFSP4_2_ZIF_Pos 7 /*!< SCU SFSP4_2: ZIF Position */ #define SCU_SFSP4_2_ZIF_Msk (0x01UL << SCU_SFSP4_2_ZIF_Pos) /*!< SCU SFSP4_2: ZIF Mask */ /* --------------------------------- SCU_SFSP4_3 -------------------------------- */ #define SCU_SFSP4_3_MODE_Pos 0 /*!< SCU SFSP4_3: MODE Position */ #define SCU_SFSP4_3_MODE_Msk (0x07UL << SCU_SFSP4_3_MODE_Pos) /*!< SCU SFSP4_3: MODE Mask */ #define SCU_SFSP4_3_EPD_Pos 3 /*!< SCU SFSP4_3: EPD Position */ #define SCU_SFSP4_3_EPD_Msk (0x01UL << SCU_SFSP4_3_EPD_Pos) /*!< SCU SFSP4_3: EPD Mask */ #define SCU_SFSP4_3_EPUN_Pos 4 /*!< SCU SFSP4_3: EPUN Position */ #define SCU_SFSP4_3_EPUN_Msk (0x01UL << SCU_SFSP4_3_EPUN_Pos) /*!< SCU SFSP4_3: EPUN Mask */ #define SCU_SFSP4_3_EHS_Pos 5 /*!< SCU SFSP4_3: EHS Position */ #define SCU_SFSP4_3_EHS_Msk (0x01UL << SCU_SFSP4_3_EHS_Pos) /*!< SCU SFSP4_3: EHS Mask */ #define SCU_SFSP4_3_EZI_Pos 6 /*!< SCU SFSP4_3: EZI Position */ #define SCU_SFSP4_3_EZI_Msk (0x01UL << SCU_SFSP4_3_EZI_Pos) /*!< SCU SFSP4_3: EZI Mask */ #define SCU_SFSP4_3_ZIF_Pos 7 /*!< SCU SFSP4_3: ZIF Position */ #define SCU_SFSP4_3_ZIF_Msk (0x01UL << SCU_SFSP4_3_ZIF_Pos) /*!< SCU SFSP4_3: ZIF Mask */ /* --------------------------------- SCU_SFSP4_4 -------------------------------- */ #define SCU_SFSP4_4_MODE_Pos 0 /*!< SCU SFSP4_4: MODE Position */ #define SCU_SFSP4_4_MODE_Msk (0x07UL << SCU_SFSP4_4_MODE_Pos) /*!< SCU SFSP4_4: MODE Mask */ #define SCU_SFSP4_4_EPD_Pos 3 /*!< SCU SFSP4_4: EPD Position */ #define SCU_SFSP4_4_EPD_Msk (0x01UL << SCU_SFSP4_4_EPD_Pos) /*!< SCU SFSP4_4: EPD Mask */ #define SCU_SFSP4_4_EPUN_Pos 4 /*!< SCU SFSP4_4: EPUN Position */ #define SCU_SFSP4_4_EPUN_Msk (0x01UL << SCU_SFSP4_4_EPUN_Pos) /*!< SCU SFSP4_4: EPUN Mask */ #define SCU_SFSP4_4_EHS_Pos 5 /*!< SCU SFSP4_4: EHS Position */ #define SCU_SFSP4_4_EHS_Msk (0x01UL << SCU_SFSP4_4_EHS_Pos) /*!< SCU SFSP4_4: EHS Mask */ #define SCU_SFSP4_4_EZI_Pos 6 /*!< SCU SFSP4_4: EZI Position */ #define SCU_SFSP4_4_EZI_Msk (0x01UL << SCU_SFSP4_4_EZI_Pos) /*!< SCU SFSP4_4: EZI Mask */ #define SCU_SFSP4_4_ZIF_Pos 7 /*!< SCU SFSP4_4: ZIF Position */ #define SCU_SFSP4_4_ZIF_Msk (0x01UL << SCU_SFSP4_4_ZIF_Pos) /*!< SCU SFSP4_4: ZIF Mask */ /* --------------------------------- SCU_SFSP4_5 -------------------------------- */ #define SCU_SFSP4_5_MODE_Pos 0 /*!< SCU SFSP4_5: MODE Position */ #define SCU_SFSP4_5_MODE_Msk (0x07UL << SCU_SFSP4_5_MODE_Pos) /*!< SCU SFSP4_5: MODE Mask */ #define SCU_SFSP4_5_EPD_Pos 3 /*!< SCU SFSP4_5: EPD Position */ #define SCU_SFSP4_5_EPD_Msk (0x01UL << SCU_SFSP4_5_EPD_Pos) /*!< SCU SFSP4_5: EPD Mask */ #define SCU_SFSP4_5_EPUN_Pos 4 /*!< SCU SFSP4_5: EPUN Position */ #define SCU_SFSP4_5_EPUN_Msk (0x01UL << SCU_SFSP4_5_EPUN_Pos) /*!< SCU SFSP4_5: EPUN Mask */ #define SCU_SFSP4_5_EHS_Pos 5 /*!< SCU SFSP4_5: EHS Position */ #define SCU_SFSP4_5_EHS_Msk (0x01UL << SCU_SFSP4_5_EHS_Pos) /*!< SCU SFSP4_5: EHS Mask */ #define SCU_SFSP4_5_EZI_Pos 6 /*!< SCU SFSP4_5: EZI Position */ #define SCU_SFSP4_5_EZI_Msk (0x01UL << SCU_SFSP4_5_EZI_Pos) /*!< SCU SFSP4_5: EZI Mask */ #define SCU_SFSP4_5_ZIF_Pos 7 /*!< SCU SFSP4_5: ZIF Position */ #define SCU_SFSP4_5_ZIF_Msk (0x01UL << SCU_SFSP4_5_ZIF_Pos) /*!< SCU SFSP4_5: ZIF Mask */ /* --------------------------------- SCU_SFSP4_6 -------------------------------- */ #define SCU_SFSP4_6_MODE_Pos 0 /*!< SCU SFSP4_6: MODE Position */ #define SCU_SFSP4_6_MODE_Msk (0x07UL << SCU_SFSP4_6_MODE_Pos) /*!< SCU SFSP4_6: MODE Mask */ #define SCU_SFSP4_6_EPD_Pos 3 /*!< SCU SFSP4_6: EPD Position */ #define SCU_SFSP4_6_EPD_Msk (0x01UL << SCU_SFSP4_6_EPD_Pos) /*!< SCU SFSP4_6: EPD Mask */ #define SCU_SFSP4_6_EPUN_Pos 4 /*!< SCU SFSP4_6: EPUN Position */ #define SCU_SFSP4_6_EPUN_Msk (0x01UL << SCU_SFSP4_6_EPUN_Pos) /*!< SCU SFSP4_6: EPUN Mask */ #define SCU_SFSP4_6_EHS_Pos 5 /*!< SCU SFSP4_6: EHS Position */ #define SCU_SFSP4_6_EHS_Msk (0x01UL << SCU_SFSP4_6_EHS_Pos) /*!< SCU SFSP4_6: EHS Mask */ #define SCU_SFSP4_6_EZI_Pos 6 /*!< SCU SFSP4_6: EZI Position */ #define SCU_SFSP4_6_EZI_Msk (0x01UL << SCU_SFSP4_6_EZI_Pos) /*!< SCU SFSP4_6: EZI Mask */ #define SCU_SFSP4_6_ZIF_Pos 7 /*!< SCU SFSP4_6: ZIF Position */ #define SCU_SFSP4_6_ZIF_Msk (0x01UL << SCU_SFSP4_6_ZIF_Pos) /*!< SCU SFSP4_6: ZIF Mask */ /* --------------------------------- SCU_SFSP4_7 -------------------------------- */ #define SCU_SFSP4_7_MODE_Pos 0 /*!< SCU SFSP4_7: MODE Position */ #define SCU_SFSP4_7_MODE_Msk (0x07UL << SCU_SFSP4_7_MODE_Pos) /*!< SCU SFSP4_7: MODE Mask */ #define SCU_SFSP4_7_EPD_Pos 3 /*!< SCU SFSP4_7: EPD Position */ #define SCU_SFSP4_7_EPD_Msk (0x01UL << SCU_SFSP4_7_EPD_Pos) /*!< SCU SFSP4_7: EPD Mask */ #define SCU_SFSP4_7_EPUN_Pos 4 /*!< SCU SFSP4_7: EPUN Position */ #define SCU_SFSP4_7_EPUN_Msk (0x01UL << SCU_SFSP4_7_EPUN_Pos) /*!< SCU SFSP4_7: EPUN Mask */ #define SCU_SFSP4_7_EHS_Pos 5 /*!< SCU SFSP4_7: EHS Position */ #define SCU_SFSP4_7_EHS_Msk (0x01UL << SCU_SFSP4_7_EHS_Pos) /*!< SCU SFSP4_7: EHS Mask */ #define SCU_SFSP4_7_EZI_Pos 6 /*!< SCU SFSP4_7: EZI Position */ #define SCU_SFSP4_7_EZI_Msk (0x01UL << SCU_SFSP4_7_EZI_Pos) /*!< SCU SFSP4_7: EZI Mask */ #define SCU_SFSP4_7_ZIF_Pos 7 /*!< SCU SFSP4_7: ZIF Position */ #define SCU_SFSP4_7_ZIF_Msk (0x01UL << SCU_SFSP4_7_ZIF_Pos) /*!< SCU SFSP4_7: ZIF Mask */ /* --------------------------------- SCU_SFSP4_8 -------------------------------- */ #define SCU_SFSP4_8_MODE_Pos 0 /*!< SCU SFSP4_8: MODE Position */ #define SCU_SFSP4_8_MODE_Msk (0x07UL << SCU_SFSP4_8_MODE_Pos) /*!< SCU SFSP4_8: MODE Mask */ #define SCU_SFSP4_8_EPD_Pos 3 /*!< SCU SFSP4_8: EPD Position */ #define SCU_SFSP4_8_EPD_Msk (0x01UL << SCU_SFSP4_8_EPD_Pos) /*!< SCU SFSP4_8: EPD Mask */ #define SCU_SFSP4_8_EPUN_Pos 4 /*!< SCU SFSP4_8: EPUN Position */ #define SCU_SFSP4_8_EPUN_Msk (0x01UL << SCU_SFSP4_8_EPUN_Pos) /*!< SCU SFSP4_8: EPUN Mask */ #define SCU_SFSP4_8_EHS_Pos 5 /*!< SCU SFSP4_8: EHS Position */ #define SCU_SFSP4_8_EHS_Msk (0x01UL << SCU_SFSP4_8_EHS_Pos) /*!< SCU SFSP4_8: EHS Mask */ #define SCU_SFSP4_8_EZI_Pos 6 /*!< SCU SFSP4_8: EZI Position */ #define SCU_SFSP4_8_EZI_Msk (0x01UL << SCU_SFSP4_8_EZI_Pos) /*!< SCU SFSP4_8: EZI Mask */ #define SCU_SFSP4_8_ZIF_Pos 7 /*!< SCU SFSP4_8: ZIF Position */ #define SCU_SFSP4_8_ZIF_Msk (0x01UL << SCU_SFSP4_8_ZIF_Pos) /*!< SCU SFSP4_8: ZIF Mask */ /* --------------------------------- SCU_SFSP4_9 -------------------------------- */ #define SCU_SFSP4_9_MODE_Pos 0 /*!< SCU SFSP4_9: MODE Position */ #define SCU_SFSP4_9_MODE_Msk (0x07UL << SCU_SFSP4_9_MODE_Pos) /*!< SCU SFSP4_9: MODE Mask */ #define SCU_SFSP4_9_EPD_Pos 3 /*!< SCU SFSP4_9: EPD Position */ #define SCU_SFSP4_9_EPD_Msk (0x01UL << SCU_SFSP4_9_EPD_Pos) /*!< SCU SFSP4_9: EPD Mask */ #define SCU_SFSP4_9_EPUN_Pos 4 /*!< SCU SFSP4_9: EPUN Position */ #define SCU_SFSP4_9_EPUN_Msk (0x01UL << SCU_SFSP4_9_EPUN_Pos) /*!< SCU SFSP4_9: EPUN Mask */ #define SCU_SFSP4_9_EHS_Pos 5 /*!< SCU SFSP4_9: EHS Position */ #define SCU_SFSP4_9_EHS_Msk (0x01UL << SCU_SFSP4_9_EHS_Pos) /*!< SCU SFSP4_9: EHS Mask */ #define SCU_SFSP4_9_EZI_Pos 6 /*!< SCU SFSP4_9: EZI Position */ #define SCU_SFSP4_9_EZI_Msk (0x01UL << SCU_SFSP4_9_EZI_Pos) /*!< SCU SFSP4_9: EZI Mask */ #define SCU_SFSP4_9_ZIF_Pos 7 /*!< SCU SFSP4_9: ZIF Position */ #define SCU_SFSP4_9_ZIF_Msk (0x01UL << SCU_SFSP4_9_ZIF_Pos) /*!< SCU SFSP4_9: ZIF Mask */ /* -------------------------------- SCU_SFSP4_10 -------------------------------- */ #define SCU_SFSP4_10_MODE_Pos 0 /*!< SCU SFSP4_10: MODE Position */ #define SCU_SFSP4_10_MODE_Msk (0x07UL << SCU_SFSP4_10_MODE_Pos) /*!< SCU SFSP4_10: MODE Mask */ #define SCU_SFSP4_10_EPD_Pos 3 /*!< SCU SFSP4_10: EPD Position */ #define SCU_SFSP4_10_EPD_Msk (0x01UL << SCU_SFSP4_10_EPD_Pos) /*!< SCU SFSP4_10: EPD Mask */ #define SCU_SFSP4_10_EPUN_Pos 4 /*!< SCU SFSP4_10: EPUN Position */ #define SCU_SFSP4_10_EPUN_Msk (0x01UL << SCU_SFSP4_10_EPUN_Pos) /*!< SCU SFSP4_10: EPUN Mask */ #define SCU_SFSP4_10_EHS_Pos 5 /*!< SCU SFSP4_10: EHS Position */ #define SCU_SFSP4_10_EHS_Msk (0x01UL << SCU_SFSP4_10_EHS_Pos) /*!< SCU SFSP4_10: EHS Mask */ #define SCU_SFSP4_10_EZI_Pos 6 /*!< SCU SFSP4_10: EZI Position */ #define SCU_SFSP4_10_EZI_Msk (0x01UL << SCU_SFSP4_10_EZI_Pos) /*!< SCU SFSP4_10: EZI Mask */ #define SCU_SFSP4_10_ZIF_Pos 7 /*!< SCU SFSP4_10: ZIF Position */ #define SCU_SFSP4_10_ZIF_Msk (0x01UL << SCU_SFSP4_10_ZIF_Pos) /*!< SCU SFSP4_10: ZIF Mask */ /* --------------------------------- SCU_SFSP5_0 -------------------------------- */ #define SCU_SFSP5_0_MODE_Pos 0 /*!< SCU SFSP5_0: MODE Position */ #define SCU_SFSP5_0_MODE_Msk (0x07UL << SCU_SFSP5_0_MODE_Pos) /*!< SCU SFSP5_0: MODE Mask */ #define SCU_SFSP5_0_EPD_Pos 3 /*!< SCU SFSP5_0: EPD Position */ #define SCU_SFSP5_0_EPD_Msk (0x01UL << SCU_SFSP5_0_EPD_Pos) /*!< SCU SFSP5_0: EPD Mask */ #define SCU_SFSP5_0_EPUN_Pos 4 /*!< SCU SFSP5_0: EPUN Position */ #define SCU_SFSP5_0_EPUN_Msk (0x01UL << SCU_SFSP5_0_EPUN_Pos) /*!< SCU SFSP5_0: EPUN Mask */ #define SCU_SFSP5_0_EHS_Pos 5 /*!< SCU SFSP5_0: EHS Position */ #define SCU_SFSP5_0_EHS_Msk (0x01UL << SCU_SFSP5_0_EHS_Pos) /*!< SCU SFSP5_0: EHS Mask */ #define SCU_SFSP5_0_EZI_Pos 6 /*!< SCU SFSP5_0: EZI Position */ #define SCU_SFSP5_0_EZI_Msk (0x01UL << SCU_SFSP5_0_EZI_Pos) /*!< SCU SFSP5_0: EZI Mask */ #define SCU_SFSP5_0_ZIF_Pos 7 /*!< SCU SFSP5_0: ZIF Position */ #define SCU_SFSP5_0_ZIF_Msk (0x01UL << SCU_SFSP5_0_ZIF_Pos) /*!< SCU SFSP5_0: ZIF Mask */ /* --------------------------------- SCU_SFSP5_1 -------------------------------- */ #define SCU_SFSP5_1_MODE_Pos 0 /*!< SCU SFSP5_1: MODE Position */ #define SCU_SFSP5_1_MODE_Msk (0x07UL << SCU_SFSP5_1_MODE_Pos) /*!< SCU SFSP5_1: MODE Mask */ #define SCU_SFSP5_1_EPD_Pos 3 /*!< SCU SFSP5_1: EPD Position */ #define SCU_SFSP5_1_EPD_Msk (0x01UL << SCU_SFSP5_1_EPD_Pos) /*!< SCU SFSP5_1: EPD Mask */ #define SCU_SFSP5_1_EPUN_Pos 4 /*!< SCU SFSP5_1: EPUN Position */ #define SCU_SFSP5_1_EPUN_Msk (0x01UL << SCU_SFSP5_1_EPUN_Pos) /*!< SCU SFSP5_1: EPUN Mask */ #define SCU_SFSP5_1_EHS_Pos 5 /*!< SCU SFSP5_1: EHS Position */ #define SCU_SFSP5_1_EHS_Msk (0x01UL << SCU_SFSP5_1_EHS_Pos) /*!< SCU SFSP5_1: EHS Mask */ #define SCU_SFSP5_1_EZI_Pos 6 /*!< SCU SFSP5_1: EZI Position */ #define SCU_SFSP5_1_EZI_Msk (0x01UL << SCU_SFSP5_1_EZI_Pos) /*!< SCU SFSP5_1: EZI Mask */ #define SCU_SFSP5_1_ZIF_Pos 7 /*!< SCU SFSP5_1: ZIF Position */ #define SCU_SFSP5_1_ZIF_Msk (0x01UL << SCU_SFSP5_1_ZIF_Pos) /*!< SCU SFSP5_1: ZIF Mask */ /* --------------------------------- SCU_SFSP5_2 -------------------------------- */ #define SCU_SFSP5_2_MODE_Pos 0 /*!< SCU SFSP5_2: MODE Position */ #define SCU_SFSP5_2_MODE_Msk (0x07UL << SCU_SFSP5_2_MODE_Pos) /*!< SCU SFSP5_2: MODE Mask */ #define SCU_SFSP5_2_EPD_Pos 3 /*!< SCU SFSP5_2: EPD Position */ #define SCU_SFSP5_2_EPD_Msk (0x01UL << SCU_SFSP5_2_EPD_Pos) /*!< SCU SFSP5_2: EPD Mask */ #define SCU_SFSP5_2_EPUN_Pos 4 /*!< SCU SFSP5_2: EPUN Position */ #define SCU_SFSP5_2_EPUN_Msk (0x01UL << SCU_SFSP5_2_EPUN_Pos) /*!< SCU SFSP5_2: EPUN Mask */ #define SCU_SFSP5_2_EHS_Pos 5 /*!< SCU SFSP5_2: EHS Position */ #define SCU_SFSP5_2_EHS_Msk (0x01UL << SCU_SFSP5_2_EHS_Pos) /*!< SCU SFSP5_2: EHS Mask */ #define SCU_SFSP5_2_EZI_Pos 6 /*!< SCU SFSP5_2: EZI Position */ #define SCU_SFSP5_2_EZI_Msk (0x01UL << SCU_SFSP5_2_EZI_Pos) /*!< SCU SFSP5_2: EZI Mask */ #define SCU_SFSP5_2_ZIF_Pos 7 /*!< SCU SFSP5_2: ZIF Position */ #define SCU_SFSP5_2_ZIF_Msk (0x01UL << SCU_SFSP5_2_ZIF_Pos) /*!< SCU SFSP5_2: ZIF Mask */ /* --------------------------------- SCU_SFSP5_3 -------------------------------- */ #define SCU_SFSP5_3_MODE_Pos 0 /*!< SCU SFSP5_3: MODE Position */ #define SCU_SFSP5_3_MODE_Msk (0x07UL << SCU_SFSP5_3_MODE_Pos) /*!< SCU SFSP5_3: MODE Mask */ #define SCU_SFSP5_3_EPD_Pos 3 /*!< SCU SFSP5_3: EPD Position */ #define SCU_SFSP5_3_EPD_Msk (0x01UL << SCU_SFSP5_3_EPD_Pos) /*!< SCU SFSP5_3: EPD Mask */ #define SCU_SFSP5_3_EPUN_Pos 4 /*!< SCU SFSP5_3: EPUN Position */ #define SCU_SFSP5_3_EPUN_Msk (0x01UL << SCU_SFSP5_3_EPUN_Pos) /*!< SCU SFSP5_3: EPUN Mask */ #define SCU_SFSP5_3_EHS_Pos 5 /*!< SCU SFSP5_3: EHS Position */ #define SCU_SFSP5_3_EHS_Msk (0x01UL << SCU_SFSP5_3_EHS_Pos) /*!< SCU SFSP5_3: EHS Mask */ #define SCU_SFSP5_3_EZI_Pos 6 /*!< SCU SFSP5_3: EZI Position */ #define SCU_SFSP5_3_EZI_Msk (0x01UL << SCU_SFSP5_3_EZI_Pos) /*!< SCU SFSP5_3: EZI Mask */ #define SCU_SFSP5_3_ZIF_Pos 7 /*!< SCU SFSP5_3: ZIF Position */ #define SCU_SFSP5_3_ZIF_Msk (0x01UL << SCU_SFSP5_3_ZIF_Pos) /*!< SCU SFSP5_3: ZIF Mask */ /* --------------------------------- SCU_SFSP5_4 -------------------------------- */ #define SCU_SFSP5_4_MODE_Pos 0 /*!< SCU SFSP5_4: MODE Position */ #define SCU_SFSP5_4_MODE_Msk (0x07UL << SCU_SFSP5_4_MODE_Pos) /*!< SCU SFSP5_4: MODE Mask */ #define SCU_SFSP5_4_EPD_Pos 3 /*!< SCU SFSP5_4: EPD Position */ #define SCU_SFSP5_4_EPD_Msk (0x01UL << SCU_SFSP5_4_EPD_Pos) /*!< SCU SFSP5_4: EPD Mask */ #define SCU_SFSP5_4_EPUN_Pos 4 /*!< SCU SFSP5_4: EPUN Position */ #define SCU_SFSP5_4_EPUN_Msk (0x01UL << SCU_SFSP5_4_EPUN_Pos) /*!< SCU SFSP5_4: EPUN Mask */ #define SCU_SFSP5_4_EHS_Pos 5 /*!< SCU SFSP5_4: EHS Position */ #define SCU_SFSP5_4_EHS_Msk (0x01UL << SCU_SFSP5_4_EHS_Pos) /*!< SCU SFSP5_4: EHS Mask */ #define SCU_SFSP5_4_EZI_Pos 6 /*!< SCU SFSP5_4: EZI Position */ #define SCU_SFSP5_4_EZI_Msk (0x01UL << SCU_SFSP5_4_EZI_Pos) /*!< SCU SFSP5_4: EZI Mask */ #define SCU_SFSP5_4_ZIF_Pos 7 /*!< SCU SFSP5_4: ZIF Position */ #define SCU_SFSP5_4_ZIF_Msk (0x01UL << SCU_SFSP5_4_ZIF_Pos) /*!< SCU SFSP5_4: ZIF Mask */ /* --------------------------------- SCU_SFSP5_5 -------------------------------- */ #define SCU_SFSP5_5_MODE_Pos 0 /*!< SCU SFSP5_5: MODE Position */ #define SCU_SFSP5_5_MODE_Msk (0x07UL << SCU_SFSP5_5_MODE_Pos) /*!< SCU SFSP5_5: MODE Mask */ #define SCU_SFSP5_5_EPD_Pos 3 /*!< SCU SFSP5_5: EPD Position */ #define SCU_SFSP5_5_EPD_Msk (0x01UL << SCU_SFSP5_5_EPD_Pos) /*!< SCU SFSP5_5: EPD Mask */ #define SCU_SFSP5_5_EPUN_Pos 4 /*!< SCU SFSP5_5: EPUN Position */ #define SCU_SFSP5_5_EPUN_Msk (0x01UL << SCU_SFSP5_5_EPUN_Pos) /*!< SCU SFSP5_5: EPUN Mask */ #define SCU_SFSP5_5_EHS_Pos 5 /*!< SCU SFSP5_5: EHS Position */ #define SCU_SFSP5_5_EHS_Msk (0x01UL << SCU_SFSP5_5_EHS_Pos) /*!< SCU SFSP5_5: EHS Mask */ #define SCU_SFSP5_5_EZI_Pos 6 /*!< SCU SFSP5_5: EZI Position */ #define SCU_SFSP5_5_EZI_Msk (0x01UL << SCU_SFSP5_5_EZI_Pos) /*!< SCU SFSP5_5: EZI Mask */ #define SCU_SFSP5_5_ZIF_Pos 7 /*!< SCU SFSP5_5: ZIF Position */ #define SCU_SFSP5_5_ZIF_Msk (0x01UL << SCU_SFSP5_5_ZIF_Pos) /*!< SCU SFSP5_5: ZIF Mask */ /* --------------------------------- SCU_SFSP5_6 -------------------------------- */ #define SCU_SFSP5_6_MODE_Pos 0 /*!< SCU SFSP5_6: MODE Position */ #define SCU_SFSP5_6_MODE_Msk (0x07UL << SCU_SFSP5_6_MODE_Pos) /*!< SCU SFSP5_6: MODE Mask */ #define SCU_SFSP5_6_EPD_Pos 3 /*!< SCU SFSP5_6: EPD Position */ #define SCU_SFSP5_6_EPD_Msk (0x01UL << SCU_SFSP5_6_EPD_Pos) /*!< SCU SFSP5_6: EPD Mask */ #define SCU_SFSP5_6_EPUN_Pos 4 /*!< SCU SFSP5_6: EPUN Position */ #define SCU_SFSP5_6_EPUN_Msk (0x01UL << SCU_SFSP5_6_EPUN_Pos) /*!< SCU SFSP5_6: EPUN Mask */ #define SCU_SFSP5_6_EHS_Pos 5 /*!< SCU SFSP5_6: EHS Position */ #define SCU_SFSP5_6_EHS_Msk (0x01UL << SCU_SFSP5_6_EHS_Pos) /*!< SCU SFSP5_6: EHS Mask */ #define SCU_SFSP5_6_EZI_Pos 6 /*!< SCU SFSP5_6: EZI Position */ #define SCU_SFSP5_6_EZI_Msk (0x01UL << SCU_SFSP5_6_EZI_Pos) /*!< SCU SFSP5_6: EZI Mask */ #define SCU_SFSP5_6_ZIF_Pos 7 /*!< SCU SFSP5_6: ZIF Position */ #define SCU_SFSP5_6_ZIF_Msk (0x01UL << SCU_SFSP5_6_ZIF_Pos) /*!< SCU SFSP5_6: ZIF Mask */ /* --------------------------------- SCU_SFSP5_7 -------------------------------- */ #define SCU_SFSP5_7_MODE_Pos 0 /*!< SCU SFSP5_7: MODE Position */ #define SCU_SFSP5_7_MODE_Msk (0x07UL << SCU_SFSP5_7_MODE_Pos) /*!< SCU SFSP5_7: MODE Mask */ #define SCU_SFSP5_7_EPD_Pos 3 /*!< SCU SFSP5_7: EPD Position */ #define SCU_SFSP5_7_EPD_Msk (0x01UL << SCU_SFSP5_7_EPD_Pos) /*!< SCU SFSP5_7: EPD Mask */ #define SCU_SFSP5_7_EPUN_Pos 4 /*!< SCU SFSP5_7: EPUN Position */ #define SCU_SFSP5_7_EPUN_Msk (0x01UL << SCU_SFSP5_7_EPUN_Pos) /*!< SCU SFSP5_7: EPUN Mask */ #define SCU_SFSP5_7_EHS_Pos 5 /*!< SCU SFSP5_7: EHS Position */ #define SCU_SFSP5_7_EHS_Msk (0x01UL << SCU_SFSP5_7_EHS_Pos) /*!< SCU SFSP5_7: EHS Mask */ #define SCU_SFSP5_7_EZI_Pos 6 /*!< SCU SFSP5_7: EZI Position */ #define SCU_SFSP5_7_EZI_Msk (0x01UL << SCU_SFSP5_7_EZI_Pos) /*!< SCU SFSP5_7: EZI Mask */ #define SCU_SFSP5_7_ZIF_Pos 7 /*!< SCU SFSP5_7: ZIF Position */ #define SCU_SFSP5_7_ZIF_Msk (0x01UL << SCU_SFSP5_7_ZIF_Pos) /*!< SCU SFSP5_7: ZIF Mask */ /* --------------------------------- SCU_SFSP6_0 -------------------------------- */ #define SCU_SFSP6_0_MODE_Pos 0 /*!< SCU SFSP6_0: MODE Position */ #define SCU_SFSP6_0_MODE_Msk (0x07UL << SCU_SFSP6_0_MODE_Pos) /*!< SCU SFSP6_0: MODE Mask */ #define SCU_SFSP6_0_EPD_Pos 3 /*!< SCU SFSP6_0: EPD Position */ #define SCU_SFSP6_0_EPD_Msk (0x01UL << SCU_SFSP6_0_EPD_Pos) /*!< SCU SFSP6_0: EPD Mask */ #define SCU_SFSP6_0_EPUN_Pos 4 /*!< SCU SFSP6_0: EPUN Position */ #define SCU_SFSP6_0_EPUN_Msk (0x01UL << SCU_SFSP6_0_EPUN_Pos) /*!< SCU SFSP6_0: EPUN Mask */ #define SCU_SFSP6_0_EHS_Pos 5 /*!< SCU SFSP6_0: EHS Position */ #define SCU_SFSP6_0_EHS_Msk (0x01UL << SCU_SFSP6_0_EHS_Pos) /*!< SCU SFSP6_0: EHS Mask */ #define SCU_SFSP6_0_EZI_Pos 6 /*!< SCU SFSP6_0: EZI Position */ #define SCU_SFSP6_0_EZI_Msk (0x01UL << SCU_SFSP6_0_EZI_Pos) /*!< SCU SFSP6_0: EZI Mask */ #define SCU_SFSP6_0_ZIF_Pos 7 /*!< SCU SFSP6_0: ZIF Position */ #define SCU_SFSP6_0_ZIF_Msk (0x01UL << SCU_SFSP6_0_ZIF_Pos) /*!< SCU SFSP6_0: ZIF Mask */ /* --------------------------------- SCU_SFSP6_1 -------------------------------- */ #define SCU_SFSP6_1_MODE_Pos 0 /*!< SCU SFSP6_1: MODE Position */ #define SCU_SFSP6_1_MODE_Msk (0x07UL << SCU_SFSP6_1_MODE_Pos) /*!< SCU SFSP6_1: MODE Mask */ #define SCU_SFSP6_1_EPD_Pos 3 /*!< SCU SFSP6_1: EPD Position */ #define SCU_SFSP6_1_EPD_Msk (0x01UL << SCU_SFSP6_1_EPD_Pos) /*!< SCU SFSP6_1: EPD Mask */ #define SCU_SFSP6_1_EPUN_Pos 4 /*!< SCU SFSP6_1: EPUN Position */ #define SCU_SFSP6_1_EPUN_Msk (0x01UL << SCU_SFSP6_1_EPUN_Pos) /*!< SCU SFSP6_1: EPUN Mask */ #define SCU_SFSP6_1_EHS_Pos 5 /*!< SCU SFSP6_1: EHS Position */ #define SCU_SFSP6_1_EHS_Msk (0x01UL << SCU_SFSP6_1_EHS_Pos) /*!< SCU SFSP6_1: EHS Mask */ #define SCU_SFSP6_1_EZI_Pos 6 /*!< SCU SFSP6_1: EZI Position */ #define SCU_SFSP6_1_EZI_Msk (0x01UL << SCU_SFSP6_1_EZI_Pos) /*!< SCU SFSP6_1: EZI Mask */ #define SCU_SFSP6_1_ZIF_Pos 7 /*!< SCU SFSP6_1: ZIF Position */ #define SCU_SFSP6_1_ZIF_Msk (0x01UL << SCU_SFSP6_1_ZIF_Pos) /*!< SCU SFSP6_1: ZIF Mask */ /* --------------------------------- SCU_SFSP6_2 -------------------------------- */ #define SCU_SFSP6_2_MODE_Pos 0 /*!< SCU SFSP6_2: MODE Position */ #define SCU_SFSP6_2_MODE_Msk (0x07UL << SCU_SFSP6_2_MODE_Pos) /*!< SCU SFSP6_2: MODE Mask */ #define SCU_SFSP6_2_EPD_Pos 3 /*!< SCU SFSP6_2: EPD Position */ #define SCU_SFSP6_2_EPD_Msk (0x01UL << SCU_SFSP6_2_EPD_Pos) /*!< SCU SFSP6_2: EPD Mask */ #define SCU_SFSP6_2_EPUN_Pos 4 /*!< SCU SFSP6_2: EPUN Position */ #define SCU_SFSP6_2_EPUN_Msk (0x01UL << SCU_SFSP6_2_EPUN_Pos) /*!< SCU SFSP6_2: EPUN Mask */ #define SCU_SFSP6_2_EHS_Pos 5 /*!< SCU SFSP6_2: EHS Position */ #define SCU_SFSP6_2_EHS_Msk (0x01UL << SCU_SFSP6_2_EHS_Pos) /*!< SCU SFSP6_2: EHS Mask */ #define SCU_SFSP6_2_EZI_Pos 6 /*!< SCU SFSP6_2: EZI Position */ #define SCU_SFSP6_2_EZI_Msk (0x01UL << SCU_SFSP6_2_EZI_Pos) /*!< SCU SFSP6_2: EZI Mask */ #define SCU_SFSP6_2_ZIF_Pos 7 /*!< SCU SFSP6_2: ZIF Position */ #define SCU_SFSP6_2_ZIF_Msk (0x01UL << SCU_SFSP6_2_ZIF_Pos) /*!< SCU SFSP6_2: ZIF Mask */ /* --------------------------------- SCU_SFSP6_3 -------------------------------- */ #define SCU_SFSP6_3_MODE_Pos 0 /*!< SCU SFSP6_3: MODE Position */ #define SCU_SFSP6_3_MODE_Msk (0x07UL << SCU_SFSP6_3_MODE_Pos) /*!< SCU SFSP6_3: MODE Mask */ #define SCU_SFSP6_3_EPD_Pos 3 /*!< SCU SFSP6_3: EPD Position */ #define SCU_SFSP6_3_EPD_Msk (0x01UL << SCU_SFSP6_3_EPD_Pos) /*!< SCU SFSP6_3: EPD Mask */ #define SCU_SFSP6_3_EPUN_Pos 4 /*!< SCU SFSP6_3: EPUN Position */ #define SCU_SFSP6_3_EPUN_Msk (0x01UL << SCU_SFSP6_3_EPUN_Pos) /*!< SCU SFSP6_3: EPUN Mask */ #define SCU_SFSP6_3_EHS_Pos 5 /*!< SCU SFSP6_3: EHS Position */ #define SCU_SFSP6_3_EHS_Msk (0x01UL << SCU_SFSP6_3_EHS_Pos) /*!< SCU SFSP6_3: EHS Mask */ #define SCU_SFSP6_3_EZI_Pos 6 /*!< SCU SFSP6_3: EZI Position */ #define SCU_SFSP6_3_EZI_Msk (0x01UL << SCU_SFSP6_3_EZI_Pos) /*!< SCU SFSP6_3: EZI Mask */ #define SCU_SFSP6_3_ZIF_Pos 7 /*!< SCU SFSP6_3: ZIF Position */ #define SCU_SFSP6_3_ZIF_Msk (0x01UL << SCU_SFSP6_3_ZIF_Pos) /*!< SCU SFSP6_3: ZIF Mask */ /* --------------------------------- SCU_SFSP6_4 -------------------------------- */ #define SCU_SFSP6_4_MODE_Pos 0 /*!< SCU SFSP6_4: MODE Position */ #define SCU_SFSP6_4_MODE_Msk (0x07UL << SCU_SFSP6_4_MODE_Pos) /*!< SCU SFSP6_4: MODE Mask */ #define SCU_SFSP6_4_EPD_Pos 3 /*!< SCU SFSP6_4: EPD Position */ #define SCU_SFSP6_4_EPD_Msk (0x01UL << SCU_SFSP6_4_EPD_Pos) /*!< SCU SFSP6_4: EPD Mask */ #define SCU_SFSP6_4_EPUN_Pos 4 /*!< SCU SFSP6_4: EPUN Position */ #define SCU_SFSP6_4_EPUN_Msk (0x01UL << SCU_SFSP6_4_EPUN_Pos) /*!< SCU SFSP6_4: EPUN Mask */ #define SCU_SFSP6_4_EHS_Pos 5 /*!< SCU SFSP6_4: EHS Position */ #define SCU_SFSP6_4_EHS_Msk (0x01UL << SCU_SFSP6_4_EHS_Pos) /*!< SCU SFSP6_4: EHS Mask */ #define SCU_SFSP6_4_EZI_Pos 6 /*!< SCU SFSP6_4: EZI Position */ #define SCU_SFSP6_4_EZI_Msk (0x01UL << SCU_SFSP6_4_EZI_Pos) /*!< SCU SFSP6_4: EZI Mask */ #define SCU_SFSP6_4_ZIF_Pos 7 /*!< SCU SFSP6_4: ZIF Position */ #define SCU_SFSP6_4_ZIF_Msk (0x01UL << SCU_SFSP6_4_ZIF_Pos) /*!< SCU SFSP6_4: ZIF Mask */ /* --------------------------------- SCU_SFSP6_5 -------------------------------- */ #define SCU_SFSP6_5_MODE_Pos 0 /*!< SCU SFSP6_5: MODE Position */ #define SCU_SFSP6_5_MODE_Msk (0x07UL << SCU_SFSP6_5_MODE_Pos) /*!< SCU SFSP6_5: MODE Mask */ #define SCU_SFSP6_5_EPD_Pos 3 /*!< SCU SFSP6_5: EPD Position */ #define SCU_SFSP6_5_EPD_Msk (0x01UL << SCU_SFSP6_5_EPD_Pos) /*!< SCU SFSP6_5: EPD Mask */ #define SCU_SFSP6_5_EPUN_Pos 4 /*!< SCU SFSP6_5: EPUN Position */ #define SCU_SFSP6_5_EPUN_Msk (0x01UL << SCU_SFSP6_5_EPUN_Pos) /*!< SCU SFSP6_5: EPUN Mask */ #define SCU_SFSP6_5_EHS_Pos 5 /*!< SCU SFSP6_5: EHS Position */ #define SCU_SFSP6_5_EHS_Msk (0x01UL << SCU_SFSP6_5_EHS_Pos) /*!< SCU SFSP6_5: EHS Mask */ #define SCU_SFSP6_5_EZI_Pos 6 /*!< SCU SFSP6_5: EZI Position */ #define SCU_SFSP6_5_EZI_Msk (0x01UL << SCU_SFSP6_5_EZI_Pos) /*!< SCU SFSP6_5: EZI Mask */ #define SCU_SFSP6_5_ZIF_Pos 7 /*!< SCU SFSP6_5: ZIF Position */ #define SCU_SFSP6_5_ZIF_Msk (0x01UL << SCU_SFSP6_5_ZIF_Pos) /*!< SCU SFSP6_5: ZIF Mask */ /* --------------------------------- SCU_SFSP6_6 -------------------------------- */ #define SCU_SFSP6_6_MODE_Pos 0 /*!< SCU SFSP6_6: MODE Position */ #define SCU_SFSP6_6_MODE_Msk (0x07UL << SCU_SFSP6_6_MODE_Pos) /*!< SCU SFSP6_6: MODE Mask */ #define SCU_SFSP6_6_EPD_Pos 3 /*!< SCU SFSP6_6: EPD Position */ #define SCU_SFSP6_6_EPD_Msk (0x01UL << SCU_SFSP6_6_EPD_Pos) /*!< SCU SFSP6_6: EPD Mask */ #define SCU_SFSP6_6_EPUN_Pos 4 /*!< SCU SFSP6_6: EPUN Position */ #define SCU_SFSP6_6_EPUN_Msk (0x01UL << SCU_SFSP6_6_EPUN_Pos) /*!< SCU SFSP6_6: EPUN Mask */ #define SCU_SFSP6_6_EHS_Pos 5 /*!< SCU SFSP6_6: EHS Position */ #define SCU_SFSP6_6_EHS_Msk (0x01UL << SCU_SFSP6_6_EHS_Pos) /*!< SCU SFSP6_6: EHS Mask */ #define SCU_SFSP6_6_EZI_Pos 6 /*!< SCU SFSP6_6: EZI Position */ #define SCU_SFSP6_6_EZI_Msk (0x01UL << SCU_SFSP6_6_EZI_Pos) /*!< SCU SFSP6_6: EZI Mask */ #define SCU_SFSP6_6_ZIF_Pos 7 /*!< SCU SFSP6_6: ZIF Position */ #define SCU_SFSP6_6_ZIF_Msk (0x01UL << SCU_SFSP6_6_ZIF_Pos) /*!< SCU SFSP6_6: ZIF Mask */ /* --------------------------------- SCU_SFSP6_7 -------------------------------- */ #define SCU_SFSP6_7_MODE_Pos 0 /*!< SCU SFSP6_7: MODE Position */ #define SCU_SFSP6_7_MODE_Msk (0x07UL << SCU_SFSP6_7_MODE_Pos) /*!< SCU SFSP6_7: MODE Mask */ #define SCU_SFSP6_7_EPD_Pos 3 /*!< SCU SFSP6_7: EPD Position */ #define SCU_SFSP6_7_EPD_Msk (0x01UL << SCU_SFSP6_7_EPD_Pos) /*!< SCU SFSP6_7: EPD Mask */ #define SCU_SFSP6_7_EPUN_Pos 4 /*!< SCU SFSP6_7: EPUN Position */ #define SCU_SFSP6_7_EPUN_Msk (0x01UL << SCU_SFSP6_7_EPUN_Pos) /*!< SCU SFSP6_7: EPUN Mask */ #define SCU_SFSP6_7_EHS_Pos 5 /*!< SCU SFSP6_7: EHS Position */ #define SCU_SFSP6_7_EHS_Msk (0x01UL << SCU_SFSP6_7_EHS_Pos) /*!< SCU SFSP6_7: EHS Mask */ #define SCU_SFSP6_7_EZI_Pos 6 /*!< SCU SFSP6_7: EZI Position */ #define SCU_SFSP6_7_EZI_Msk (0x01UL << SCU_SFSP6_7_EZI_Pos) /*!< SCU SFSP6_7: EZI Mask */ #define SCU_SFSP6_7_ZIF_Pos 7 /*!< SCU SFSP6_7: ZIF Position */ #define SCU_SFSP6_7_ZIF_Msk (0x01UL << SCU_SFSP6_7_ZIF_Pos) /*!< SCU SFSP6_7: ZIF Mask */ /* --------------------------------- SCU_SFSP6_8 -------------------------------- */ #define SCU_SFSP6_8_MODE_Pos 0 /*!< SCU SFSP6_8: MODE Position */ #define SCU_SFSP6_8_MODE_Msk (0x07UL << SCU_SFSP6_8_MODE_Pos) /*!< SCU SFSP6_8: MODE Mask */ #define SCU_SFSP6_8_EPD_Pos 3 /*!< SCU SFSP6_8: EPD Position */ #define SCU_SFSP6_8_EPD_Msk (0x01UL << SCU_SFSP6_8_EPD_Pos) /*!< SCU SFSP6_8: EPD Mask */ #define SCU_SFSP6_8_EPUN_Pos 4 /*!< SCU SFSP6_8: EPUN Position */ #define SCU_SFSP6_8_EPUN_Msk (0x01UL << SCU_SFSP6_8_EPUN_Pos) /*!< SCU SFSP6_8: EPUN Mask */ #define SCU_SFSP6_8_EHS_Pos 5 /*!< SCU SFSP6_8: EHS Position */ #define SCU_SFSP6_8_EHS_Msk (0x01UL << SCU_SFSP6_8_EHS_Pos) /*!< SCU SFSP6_8: EHS Mask */ #define SCU_SFSP6_8_EZI_Pos 6 /*!< SCU SFSP6_8: EZI Position */ #define SCU_SFSP6_8_EZI_Msk (0x01UL << SCU_SFSP6_8_EZI_Pos) /*!< SCU SFSP6_8: EZI Mask */ #define SCU_SFSP6_8_ZIF_Pos 7 /*!< SCU SFSP6_8: ZIF Position */ #define SCU_SFSP6_8_ZIF_Msk (0x01UL << SCU_SFSP6_8_ZIF_Pos) /*!< SCU SFSP6_8: ZIF Mask */ /* --------------------------------- SCU_SFSP6_9 -------------------------------- */ #define SCU_SFSP6_9_MODE_Pos 0 /*!< SCU SFSP6_9: MODE Position */ #define SCU_SFSP6_9_MODE_Msk (0x07UL << SCU_SFSP6_9_MODE_Pos) /*!< SCU SFSP6_9: MODE Mask */ #define SCU_SFSP6_9_EPD_Pos 3 /*!< SCU SFSP6_9: EPD Position */ #define SCU_SFSP6_9_EPD_Msk (0x01UL << SCU_SFSP6_9_EPD_Pos) /*!< SCU SFSP6_9: EPD Mask */ #define SCU_SFSP6_9_EPUN_Pos 4 /*!< SCU SFSP6_9: EPUN Position */ #define SCU_SFSP6_9_EPUN_Msk (0x01UL << SCU_SFSP6_9_EPUN_Pos) /*!< SCU SFSP6_9: EPUN Mask */ #define SCU_SFSP6_9_EHS_Pos 5 /*!< SCU SFSP6_9: EHS Position */ #define SCU_SFSP6_9_EHS_Msk (0x01UL << SCU_SFSP6_9_EHS_Pos) /*!< SCU SFSP6_9: EHS Mask */ #define SCU_SFSP6_9_EZI_Pos 6 /*!< SCU SFSP6_9: EZI Position */ #define SCU_SFSP6_9_EZI_Msk (0x01UL << SCU_SFSP6_9_EZI_Pos) /*!< SCU SFSP6_9: EZI Mask */ #define SCU_SFSP6_9_ZIF_Pos 7 /*!< SCU SFSP6_9: ZIF Position */ #define SCU_SFSP6_9_ZIF_Msk (0x01UL << SCU_SFSP6_9_ZIF_Pos) /*!< SCU SFSP6_9: ZIF Mask */ /* -------------------------------- SCU_SFSP6_10 -------------------------------- */ #define SCU_SFSP6_10_MODE_Pos 0 /*!< SCU SFSP6_10: MODE Position */ #define SCU_SFSP6_10_MODE_Msk (0x07UL << SCU_SFSP6_10_MODE_Pos) /*!< SCU SFSP6_10: MODE Mask */ #define SCU_SFSP6_10_EPD_Pos 3 /*!< SCU SFSP6_10: EPD Position */ #define SCU_SFSP6_10_EPD_Msk (0x01UL << SCU_SFSP6_10_EPD_Pos) /*!< SCU SFSP6_10: EPD Mask */ #define SCU_SFSP6_10_EPUN_Pos 4 /*!< SCU SFSP6_10: EPUN Position */ #define SCU_SFSP6_10_EPUN_Msk (0x01UL << SCU_SFSP6_10_EPUN_Pos) /*!< SCU SFSP6_10: EPUN Mask */ #define SCU_SFSP6_10_EHS_Pos 5 /*!< SCU SFSP6_10: EHS Position */ #define SCU_SFSP6_10_EHS_Msk (0x01UL << SCU_SFSP6_10_EHS_Pos) /*!< SCU SFSP6_10: EHS Mask */ #define SCU_SFSP6_10_EZI_Pos 6 /*!< SCU SFSP6_10: EZI Position */ #define SCU_SFSP6_10_EZI_Msk (0x01UL << SCU_SFSP6_10_EZI_Pos) /*!< SCU SFSP6_10: EZI Mask */ #define SCU_SFSP6_10_ZIF_Pos 7 /*!< SCU SFSP6_10: ZIF Position */ #define SCU_SFSP6_10_ZIF_Msk (0x01UL << SCU_SFSP6_10_ZIF_Pos) /*!< SCU SFSP6_10: ZIF Mask */ /* -------------------------------- SCU_SFSP6_11 -------------------------------- */ #define SCU_SFSP6_11_MODE_Pos 0 /*!< SCU SFSP6_11: MODE Position */ #define SCU_SFSP6_11_MODE_Msk (0x07UL << SCU_SFSP6_11_MODE_Pos) /*!< SCU SFSP6_11: MODE Mask */ #define SCU_SFSP6_11_EPD_Pos 3 /*!< SCU SFSP6_11: EPD Position */ #define SCU_SFSP6_11_EPD_Msk (0x01UL << SCU_SFSP6_11_EPD_Pos) /*!< SCU SFSP6_11: EPD Mask */ #define SCU_SFSP6_11_EPUN_Pos 4 /*!< SCU SFSP6_11: EPUN Position */ #define SCU_SFSP6_11_EPUN_Msk (0x01UL << SCU_SFSP6_11_EPUN_Pos) /*!< SCU SFSP6_11: EPUN Mask */ #define SCU_SFSP6_11_EHS_Pos 5 /*!< SCU SFSP6_11: EHS Position */ #define SCU_SFSP6_11_EHS_Msk (0x01UL << SCU_SFSP6_11_EHS_Pos) /*!< SCU SFSP6_11: EHS Mask */ #define SCU_SFSP6_11_EZI_Pos 6 /*!< SCU SFSP6_11: EZI Position */ #define SCU_SFSP6_11_EZI_Msk (0x01UL << SCU_SFSP6_11_EZI_Pos) /*!< SCU SFSP6_11: EZI Mask */ #define SCU_SFSP6_11_ZIF_Pos 7 /*!< SCU SFSP6_11: ZIF Position */ #define SCU_SFSP6_11_ZIF_Msk (0x01UL << SCU_SFSP6_11_ZIF_Pos) /*!< SCU SFSP6_11: ZIF Mask */ /* -------------------------------- SCU_SFSP6_12 -------------------------------- */ #define SCU_SFSP6_12_MODE_Pos 0 /*!< SCU SFSP6_12: MODE Position */ #define SCU_SFSP6_12_MODE_Msk (0x07UL << SCU_SFSP6_12_MODE_Pos) /*!< SCU SFSP6_12: MODE Mask */ #define SCU_SFSP6_12_EPD_Pos 3 /*!< SCU SFSP6_12: EPD Position */ #define SCU_SFSP6_12_EPD_Msk (0x01UL << SCU_SFSP6_12_EPD_Pos) /*!< SCU SFSP6_12: EPD Mask */ #define SCU_SFSP6_12_EPUN_Pos 4 /*!< SCU SFSP6_12: EPUN Position */ #define SCU_SFSP6_12_EPUN_Msk (0x01UL << SCU_SFSP6_12_EPUN_Pos) /*!< SCU SFSP6_12: EPUN Mask */ #define SCU_SFSP6_12_EHS_Pos 5 /*!< SCU SFSP6_12: EHS Position */ #define SCU_SFSP6_12_EHS_Msk (0x01UL << SCU_SFSP6_12_EHS_Pos) /*!< SCU SFSP6_12: EHS Mask */ #define SCU_SFSP6_12_EZI_Pos 6 /*!< SCU SFSP6_12: EZI Position */ #define SCU_SFSP6_12_EZI_Msk (0x01UL << SCU_SFSP6_12_EZI_Pos) /*!< SCU SFSP6_12: EZI Mask */ #define SCU_SFSP6_12_ZIF_Pos 7 /*!< SCU SFSP6_12: ZIF Position */ #define SCU_SFSP6_12_ZIF_Msk (0x01UL << SCU_SFSP6_12_ZIF_Pos) /*!< SCU SFSP6_12: ZIF Mask */ /* --------------------------------- SCU_SFSP7_0 -------------------------------- */ #define SCU_SFSP7_0_MODE_Pos 0 /*!< SCU SFSP7_0: MODE Position */ #define SCU_SFSP7_0_MODE_Msk (0x07UL << SCU_SFSP7_0_MODE_Pos) /*!< SCU SFSP7_0: MODE Mask */ #define SCU_SFSP7_0_EPD_Pos 3 /*!< SCU SFSP7_0: EPD Position */ #define SCU_SFSP7_0_EPD_Msk (0x01UL << SCU_SFSP7_0_EPD_Pos) /*!< SCU SFSP7_0: EPD Mask */ #define SCU_SFSP7_0_EPUN_Pos 4 /*!< SCU SFSP7_0: EPUN Position */ #define SCU_SFSP7_0_EPUN_Msk (0x01UL << SCU_SFSP7_0_EPUN_Pos) /*!< SCU SFSP7_0: EPUN Mask */ #define SCU_SFSP7_0_EHS_Pos 5 /*!< SCU SFSP7_0: EHS Position */ #define SCU_SFSP7_0_EHS_Msk (0x01UL << SCU_SFSP7_0_EHS_Pos) /*!< SCU SFSP7_0: EHS Mask */ #define SCU_SFSP7_0_EZI_Pos 6 /*!< SCU SFSP7_0: EZI Position */ #define SCU_SFSP7_0_EZI_Msk (0x01UL << SCU_SFSP7_0_EZI_Pos) /*!< SCU SFSP7_0: EZI Mask */ #define SCU_SFSP7_0_ZIF_Pos 7 /*!< SCU SFSP7_0: ZIF Position */ #define SCU_SFSP7_0_ZIF_Msk (0x01UL << SCU_SFSP7_0_ZIF_Pos) /*!< SCU SFSP7_0: ZIF Mask */ /* --------------------------------- SCU_SFSP7_1 -------------------------------- */ #define SCU_SFSP7_1_MODE_Pos 0 /*!< SCU SFSP7_1: MODE Position */ #define SCU_SFSP7_1_MODE_Msk (0x07UL << SCU_SFSP7_1_MODE_Pos) /*!< SCU SFSP7_1: MODE Mask */ #define SCU_SFSP7_1_EPD_Pos 3 /*!< SCU SFSP7_1: EPD Position */ #define SCU_SFSP7_1_EPD_Msk (0x01UL << SCU_SFSP7_1_EPD_Pos) /*!< SCU SFSP7_1: EPD Mask */ #define SCU_SFSP7_1_EPUN_Pos 4 /*!< SCU SFSP7_1: EPUN Position */ #define SCU_SFSP7_1_EPUN_Msk (0x01UL << SCU_SFSP7_1_EPUN_Pos) /*!< SCU SFSP7_1: EPUN Mask */ #define SCU_SFSP7_1_EHS_Pos 5 /*!< SCU SFSP7_1: EHS Position */ #define SCU_SFSP7_1_EHS_Msk (0x01UL << SCU_SFSP7_1_EHS_Pos) /*!< SCU SFSP7_1: EHS Mask */ #define SCU_SFSP7_1_EZI_Pos 6 /*!< SCU SFSP7_1: EZI Position */ #define SCU_SFSP7_1_EZI_Msk (0x01UL << SCU_SFSP7_1_EZI_Pos) /*!< SCU SFSP7_1: EZI Mask */ #define SCU_SFSP7_1_ZIF_Pos 7 /*!< SCU SFSP7_1: ZIF Position */ #define SCU_SFSP7_1_ZIF_Msk (0x01UL << SCU_SFSP7_1_ZIF_Pos) /*!< SCU SFSP7_1: ZIF Mask */ /* --------------------------------- SCU_SFSP7_2 -------------------------------- */ #define SCU_SFSP7_2_MODE_Pos 0 /*!< SCU SFSP7_2: MODE Position */ #define SCU_SFSP7_2_MODE_Msk (0x07UL << SCU_SFSP7_2_MODE_Pos) /*!< SCU SFSP7_2: MODE Mask */ #define SCU_SFSP7_2_EPD_Pos 3 /*!< SCU SFSP7_2: EPD Position */ #define SCU_SFSP7_2_EPD_Msk (0x01UL << SCU_SFSP7_2_EPD_Pos) /*!< SCU SFSP7_2: EPD Mask */ #define SCU_SFSP7_2_EPUN_Pos 4 /*!< SCU SFSP7_2: EPUN Position */ #define SCU_SFSP7_2_EPUN_Msk (0x01UL << SCU_SFSP7_2_EPUN_Pos) /*!< SCU SFSP7_2: EPUN Mask */ #define SCU_SFSP7_2_EHS_Pos 5 /*!< SCU SFSP7_2: EHS Position */ #define SCU_SFSP7_2_EHS_Msk (0x01UL << SCU_SFSP7_2_EHS_Pos) /*!< SCU SFSP7_2: EHS Mask */ #define SCU_SFSP7_2_EZI_Pos 6 /*!< SCU SFSP7_2: EZI Position */ #define SCU_SFSP7_2_EZI_Msk (0x01UL << SCU_SFSP7_2_EZI_Pos) /*!< SCU SFSP7_2: EZI Mask */ #define SCU_SFSP7_2_ZIF_Pos 7 /*!< SCU SFSP7_2: ZIF Position */ #define SCU_SFSP7_2_ZIF_Msk (0x01UL << SCU_SFSP7_2_ZIF_Pos) /*!< SCU SFSP7_2: ZIF Mask */ /* --------------------------------- SCU_SFSP7_3 -------------------------------- */ #define SCU_SFSP7_3_MODE_Pos 0 /*!< SCU SFSP7_3: MODE Position */ #define SCU_SFSP7_3_MODE_Msk (0x07UL << SCU_SFSP7_3_MODE_Pos) /*!< SCU SFSP7_3: MODE Mask */ #define SCU_SFSP7_3_EPD_Pos 3 /*!< SCU SFSP7_3: EPD Position */ #define SCU_SFSP7_3_EPD_Msk (0x01UL << SCU_SFSP7_3_EPD_Pos) /*!< SCU SFSP7_3: EPD Mask */ #define SCU_SFSP7_3_EPUN_Pos 4 /*!< SCU SFSP7_3: EPUN Position */ #define SCU_SFSP7_3_EPUN_Msk (0x01UL << SCU_SFSP7_3_EPUN_Pos) /*!< SCU SFSP7_3: EPUN Mask */ #define SCU_SFSP7_3_EHS_Pos 5 /*!< SCU SFSP7_3: EHS Position */ #define SCU_SFSP7_3_EHS_Msk (0x01UL << SCU_SFSP7_3_EHS_Pos) /*!< SCU SFSP7_3: EHS Mask */ #define SCU_SFSP7_3_EZI_Pos 6 /*!< SCU SFSP7_3: EZI Position */ #define SCU_SFSP7_3_EZI_Msk (0x01UL << SCU_SFSP7_3_EZI_Pos) /*!< SCU SFSP7_3: EZI Mask */ #define SCU_SFSP7_3_ZIF_Pos 7 /*!< SCU SFSP7_3: ZIF Position */ #define SCU_SFSP7_3_ZIF_Msk (0x01UL << SCU_SFSP7_3_ZIF_Pos) /*!< SCU SFSP7_3: ZIF Mask */ /* --------------------------------- SCU_SFSP7_4 -------------------------------- */ #define SCU_SFSP7_4_MODE_Pos 0 /*!< SCU SFSP7_4: MODE Position */ #define SCU_SFSP7_4_MODE_Msk (0x07UL << SCU_SFSP7_4_MODE_Pos) /*!< SCU SFSP7_4: MODE Mask */ #define SCU_SFSP7_4_EPD_Pos 3 /*!< SCU SFSP7_4: EPD Position */ #define SCU_SFSP7_4_EPD_Msk (0x01UL << SCU_SFSP7_4_EPD_Pos) /*!< SCU SFSP7_4: EPD Mask */ #define SCU_SFSP7_4_EPUN_Pos 4 /*!< SCU SFSP7_4: EPUN Position */ #define SCU_SFSP7_4_EPUN_Msk (0x01UL << SCU_SFSP7_4_EPUN_Pos) /*!< SCU SFSP7_4: EPUN Mask */ #define SCU_SFSP7_4_EHS_Pos 5 /*!< SCU SFSP7_4: EHS Position */ #define SCU_SFSP7_4_EHS_Msk (0x01UL << SCU_SFSP7_4_EHS_Pos) /*!< SCU SFSP7_4: EHS Mask */ #define SCU_SFSP7_4_EZI_Pos 6 /*!< SCU SFSP7_4: EZI Position */ #define SCU_SFSP7_4_EZI_Msk (0x01UL << SCU_SFSP7_4_EZI_Pos) /*!< SCU SFSP7_4: EZI Mask */ #define SCU_SFSP7_4_ZIF_Pos 7 /*!< SCU SFSP7_4: ZIF Position */ #define SCU_SFSP7_4_ZIF_Msk (0x01UL << SCU_SFSP7_4_ZIF_Pos) /*!< SCU SFSP7_4: ZIF Mask */ /* --------------------------------- SCU_SFSP7_5 -------------------------------- */ #define SCU_SFSP7_5_MODE_Pos 0 /*!< SCU SFSP7_5: MODE Position */ #define SCU_SFSP7_5_MODE_Msk (0x07UL << SCU_SFSP7_5_MODE_Pos) /*!< SCU SFSP7_5: MODE Mask */ #define SCU_SFSP7_5_EPD_Pos 3 /*!< SCU SFSP7_5: EPD Position */ #define SCU_SFSP7_5_EPD_Msk (0x01UL << SCU_SFSP7_5_EPD_Pos) /*!< SCU SFSP7_5: EPD Mask */ #define SCU_SFSP7_5_EPUN_Pos 4 /*!< SCU SFSP7_5: EPUN Position */ #define SCU_SFSP7_5_EPUN_Msk (0x01UL << SCU_SFSP7_5_EPUN_Pos) /*!< SCU SFSP7_5: EPUN Mask */ #define SCU_SFSP7_5_EHS_Pos 5 /*!< SCU SFSP7_5: EHS Position */ #define SCU_SFSP7_5_EHS_Msk (0x01UL << SCU_SFSP7_5_EHS_Pos) /*!< SCU SFSP7_5: EHS Mask */ #define SCU_SFSP7_5_EZI_Pos 6 /*!< SCU SFSP7_5: EZI Position */ #define SCU_SFSP7_5_EZI_Msk (0x01UL << SCU_SFSP7_5_EZI_Pos) /*!< SCU SFSP7_5: EZI Mask */ #define SCU_SFSP7_5_ZIF_Pos 7 /*!< SCU SFSP7_5: ZIF Position */ #define SCU_SFSP7_5_ZIF_Msk (0x01UL << SCU_SFSP7_5_ZIF_Pos) /*!< SCU SFSP7_5: ZIF Mask */ /* --------------------------------- SCU_SFSP7_6 -------------------------------- */ #define SCU_SFSP7_6_MODE_Pos 0 /*!< SCU SFSP7_6: MODE Position */ #define SCU_SFSP7_6_MODE_Msk (0x07UL << SCU_SFSP7_6_MODE_Pos) /*!< SCU SFSP7_6: MODE Mask */ #define SCU_SFSP7_6_EPD_Pos 3 /*!< SCU SFSP7_6: EPD Position */ #define SCU_SFSP7_6_EPD_Msk (0x01UL << SCU_SFSP7_6_EPD_Pos) /*!< SCU SFSP7_6: EPD Mask */ #define SCU_SFSP7_6_EPUN_Pos 4 /*!< SCU SFSP7_6: EPUN Position */ #define SCU_SFSP7_6_EPUN_Msk (0x01UL << SCU_SFSP7_6_EPUN_Pos) /*!< SCU SFSP7_6: EPUN Mask */ #define SCU_SFSP7_6_EHS_Pos 5 /*!< SCU SFSP7_6: EHS Position */ #define SCU_SFSP7_6_EHS_Msk (0x01UL << SCU_SFSP7_6_EHS_Pos) /*!< SCU SFSP7_6: EHS Mask */ #define SCU_SFSP7_6_EZI_Pos 6 /*!< SCU SFSP7_6: EZI Position */ #define SCU_SFSP7_6_EZI_Msk (0x01UL << SCU_SFSP7_6_EZI_Pos) /*!< SCU SFSP7_6: EZI Mask */ #define SCU_SFSP7_6_ZIF_Pos 7 /*!< SCU SFSP7_6: ZIF Position */ #define SCU_SFSP7_6_ZIF_Msk (0x01UL << SCU_SFSP7_6_ZIF_Pos) /*!< SCU SFSP7_6: ZIF Mask */ /* --------------------------------- SCU_SFSP7_7 -------------------------------- */ #define SCU_SFSP7_7_MODE_Pos 0 /*!< SCU SFSP7_7: MODE Position */ #define SCU_SFSP7_7_MODE_Msk (0x07UL << SCU_SFSP7_7_MODE_Pos) /*!< SCU SFSP7_7: MODE Mask */ #define SCU_SFSP7_7_EPD_Pos 3 /*!< SCU SFSP7_7: EPD Position */ #define SCU_SFSP7_7_EPD_Msk (0x01UL << SCU_SFSP7_7_EPD_Pos) /*!< SCU SFSP7_7: EPD Mask */ #define SCU_SFSP7_7_EPUN_Pos 4 /*!< SCU SFSP7_7: EPUN Position */ #define SCU_SFSP7_7_EPUN_Msk (0x01UL << SCU_SFSP7_7_EPUN_Pos) /*!< SCU SFSP7_7: EPUN Mask */ #define SCU_SFSP7_7_EHS_Pos 5 /*!< SCU SFSP7_7: EHS Position */ #define SCU_SFSP7_7_EHS_Msk (0x01UL << SCU_SFSP7_7_EHS_Pos) /*!< SCU SFSP7_7: EHS Mask */ #define SCU_SFSP7_7_EZI_Pos 6 /*!< SCU SFSP7_7: EZI Position */ #define SCU_SFSP7_7_EZI_Msk (0x01UL << SCU_SFSP7_7_EZI_Pos) /*!< SCU SFSP7_7: EZI Mask */ #define SCU_SFSP7_7_ZIF_Pos 7 /*!< SCU SFSP7_7: ZIF Position */ #define SCU_SFSP7_7_ZIF_Msk (0x01UL << SCU_SFSP7_7_ZIF_Pos) /*!< SCU SFSP7_7: ZIF Mask */ /* --------------------------------- SCU_SFSP8_0 -------------------------------- */ #define SCU_SFSP8_0_MODE_Pos 0 /*!< SCU SFSP8_0: MODE Position */ #define SCU_SFSP8_0_MODE_Msk (0x07UL << SCU_SFSP8_0_MODE_Pos) /*!< SCU SFSP8_0: MODE Mask */ #define SCU_SFSP8_0_EPD_Pos 3 /*!< SCU SFSP8_0: EPD Position */ #define SCU_SFSP8_0_EPD_Msk (0x01UL << SCU_SFSP8_0_EPD_Pos) /*!< SCU SFSP8_0: EPD Mask */ #define SCU_SFSP8_0_EPUN_Pos 4 /*!< SCU SFSP8_0: EPUN Position */ #define SCU_SFSP8_0_EPUN_Msk (0x01UL << SCU_SFSP8_0_EPUN_Pos) /*!< SCU SFSP8_0: EPUN Mask */ #define SCU_SFSP8_0_EHS_Pos 5 /*!< SCU SFSP8_0: EHS Position */ #define SCU_SFSP8_0_EHS_Msk (0x01UL << SCU_SFSP8_0_EHS_Pos) /*!< SCU SFSP8_0: EHS Mask */ #define SCU_SFSP8_0_EZI_Pos 6 /*!< SCU SFSP8_0: EZI Position */ #define SCU_SFSP8_0_EZI_Msk (0x01UL << SCU_SFSP8_0_EZI_Pos) /*!< SCU SFSP8_0: EZI Mask */ #define SCU_SFSP8_0_ZIF_Pos 7 /*!< SCU SFSP8_0: ZIF Position */ #define SCU_SFSP8_0_ZIF_Msk (0x01UL << SCU_SFSP8_0_ZIF_Pos) /*!< SCU SFSP8_0: ZIF Mask */ /* --------------------------------- SCU_SFSP8_1 -------------------------------- */ #define SCU_SFSP8_1_MODE_Pos 0 /*!< SCU SFSP8_1: MODE Position */ #define SCU_SFSP8_1_MODE_Msk (0x07UL << SCU_SFSP8_1_MODE_Pos) /*!< SCU SFSP8_1: MODE Mask */ #define SCU_SFSP8_1_EPD_Pos 3 /*!< SCU SFSP8_1: EPD Position */ #define SCU_SFSP8_1_EPD_Msk (0x01UL << SCU_SFSP8_1_EPD_Pos) /*!< SCU SFSP8_1: EPD Mask */ #define SCU_SFSP8_1_EPUN_Pos 4 /*!< SCU SFSP8_1: EPUN Position */ #define SCU_SFSP8_1_EPUN_Msk (0x01UL << SCU_SFSP8_1_EPUN_Pos) /*!< SCU SFSP8_1: EPUN Mask */ #define SCU_SFSP8_1_EHS_Pos 5 /*!< SCU SFSP8_1: EHS Position */ #define SCU_SFSP8_1_EHS_Msk (0x01UL << SCU_SFSP8_1_EHS_Pos) /*!< SCU SFSP8_1: EHS Mask */ #define SCU_SFSP8_1_EZI_Pos 6 /*!< SCU SFSP8_1: EZI Position */ #define SCU_SFSP8_1_EZI_Msk (0x01UL << SCU_SFSP8_1_EZI_Pos) /*!< SCU SFSP8_1: EZI Mask */ #define SCU_SFSP8_1_ZIF_Pos 7 /*!< SCU SFSP8_1: ZIF Position */ #define SCU_SFSP8_1_ZIF_Msk (0x01UL << SCU_SFSP8_1_ZIF_Pos) /*!< SCU SFSP8_1: ZIF Mask */ /* --------------------------------- SCU_SFSP8_2 -------------------------------- */ #define SCU_SFSP8_2_MODE_Pos 0 /*!< SCU SFSP8_2: MODE Position */ #define SCU_SFSP8_2_MODE_Msk (0x07UL << SCU_SFSP8_2_MODE_Pos) /*!< SCU SFSP8_2: MODE Mask */ #define SCU_SFSP8_2_EPD_Pos 3 /*!< SCU SFSP8_2: EPD Position */ #define SCU_SFSP8_2_EPD_Msk (0x01UL << SCU_SFSP8_2_EPD_Pos) /*!< SCU SFSP8_2: EPD Mask */ #define SCU_SFSP8_2_EPUN_Pos 4 /*!< SCU SFSP8_2: EPUN Position */ #define SCU_SFSP8_2_EPUN_Msk (0x01UL << SCU_SFSP8_2_EPUN_Pos) /*!< SCU SFSP8_2: EPUN Mask */ #define SCU_SFSP8_2_EHS_Pos 5 /*!< SCU SFSP8_2: EHS Position */ #define SCU_SFSP8_2_EHS_Msk (0x01UL << SCU_SFSP8_2_EHS_Pos) /*!< SCU SFSP8_2: EHS Mask */ #define SCU_SFSP8_2_EZI_Pos 6 /*!< SCU SFSP8_2: EZI Position */ #define SCU_SFSP8_2_EZI_Msk (0x01UL << SCU_SFSP8_2_EZI_Pos) /*!< SCU SFSP8_2: EZI Mask */ #define SCU_SFSP8_2_ZIF_Pos 7 /*!< SCU SFSP8_2: ZIF Position */ #define SCU_SFSP8_2_ZIF_Msk (0x01UL << SCU_SFSP8_2_ZIF_Pos) /*!< SCU SFSP8_2: ZIF Mask */ /* --------------------------------- SCU_SFSP8_3 -------------------------------- */ #define SCU_SFSP8_3_MODE_Pos 0 /*!< SCU SFSP8_3: MODE Position */ #define SCU_SFSP8_3_MODE_Msk (0x07UL << SCU_SFSP8_3_MODE_Pos) /*!< SCU SFSP8_3: MODE Mask */ #define SCU_SFSP8_3_EPD_Pos 3 /*!< SCU SFSP8_3: EPD Position */ #define SCU_SFSP8_3_EPD_Msk (0x01UL << SCU_SFSP8_3_EPD_Pos) /*!< SCU SFSP8_3: EPD Mask */ #define SCU_SFSP8_3_EPUN_Pos 4 /*!< SCU SFSP8_3: EPUN Position */ #define SCU_SFSP8_3_EPUN_Msk (0x01UL << SCU_SFSP8_3_EPUN_Pos) /*!< SCU SFSP8_3: EPUN Mask */ #define SCU_SFSP8_3_EHS_Pos 5 /*!< SCU SFSP8_3: EHS Position */ #define SCU_SFSP8_3_EHS_Msk (0x01UL << SCU_SFSP8_3_EHS_Pos) /*!< SCU SFSP8_3: EHS Mask */ #define SCU_SFSP8_3_EZI_Pos 6 /*!< SCU SFSP8_3: EZI Position */ #define SCU_SFSP8_3_EZI_Msk (0x01UL << SCU_SFSP8_3_EZI_Pos) /*!< SCU SFSP8_3: EZI Mask */ #define SCU_SFSP8_3_ZIF_Pos 7 /*!< SCU SFSP8_3: ZIF Position */ #define SCU_SFSP8_3_ZIF_Msk (0x01UL << SCU_SFSP8_3_ZIF_Pos) /*!< SCU SFSP8_3: ZIF Mask */ /* --------------------------------- SCU_SFSP8_4 -------------------------------- */ #define SCU_SFSP8_4_MODE_Pos 0 /*!< SCU SFSP8_4: MODE Position */ #define SCU_SFSP8_4_MODE_Msk (0x07UL << SCU_SFSP8_4_MODE_Pos) /*!< SCU SFSP8_4: MODE Mask */ #define SCU_SFSP8_4_EPD_Pos 3 /*!< SCU SFSP8_4: EPD Position */ #define SCU_SFSP8_4_EPD_Msk (0x01UL << SCU_SFSP8_4_EPD_Pos) /*!< SCU SFSP8_4: EPD Mask */ #define SCU_SFSP8_4_EPUN_Pos 4 /*!< SCU SFSP8_4: EPUN Position */ #define SCU_SFSP8_4_EPUN_Msk (0x01UL << SCU_SFSP8_4_EPUN_Pos) /*!< SCU SFSP8_4: EPUN Mask */ #define SCU_SFSP8_4_EHS_Pos 5 /*!< SCU SFSP8_4: EHS Position */ #define SCU_SFSP8_4_EHS_Msk (0x01UL << SCU_SFSP8_4_EHS_Pos) /*!< SCU SFSP8_4: EHS Mask */ #define SCU_SFSP8_4_EZI_Pos 6 /*!< SCU SFSP8_4: EZI Position */ #define SCU_SFSP8_4_EZI_Msk (0x01UL << SCU_SFSP8_4_EZI_Pos) /*!< SCU SFSP8_4: EZI Mask */ #define SCU_SFSP8_4_ZIF_Pos 7 /*!< SCU SFSP8_4: ZIF Position */ #define SCU_SFSP8_4_ZIF_Msk (0x01UL << SCU_SFSP8_4_ZIF_Pos) /*!< SCU SFSP8_4: ZIF Mask */ /* --------------------------------- SCU_SFSP8_5 -------------------------------- */ #define SCU_SFSP8_5_MODE_Pos 0 /*!< SCU SFSP8_5: MODE Position */ #define SCU_SFSP8_5_MODE_Msk (0x07UL << SCU_SFSP8_5_MODE_Pos) /*!< SCU SFSP8_5: MODE Mask */ #define SCU_SFSP8_5_EPD_Pos 3 /*!< SCU SFSP8_5: EPD Position */ #define SCU_SFSP8_5_EPD_Msk (0x01UL << SCU_SFSP8_5_EPD_Pos) /*!< SCU SFSP8_5: EPD Mask */ #define SCU_SFSP8_5_EPUN_Pos 4 /*!< SCU SFSP8_5: EPUN Position */ #define SCU_SFSP8_5_EPUN_Msk (0x01UL << SCU_SFSP8_5_EPUN_Pos) /*!< SCU SFSP8_5: EPUN Mask */ #define SCU_SFSP8_5_EHS_Pos 5 /*!< SCU SFSP8_5: EHS Position */ #define SCU_SFSP8_5_EHS_Msk (0x01UL << SCU_SFSP8_5_EHS_Pos) /*!< SCU SFSP8_5: EHS Mask */ #define SCU_SFSP8_5_EZI_Pos 6 /*!< SCU SFSP8_5: EZI Position */ #define SCU_SFSP8_5_EZI_Msk (0x01UL << SCU_SFSP8_5_EZI_Pos) /*!< SCU SFSP8_5: EZI Mask */ #define SCU_SFSP8_5_ZIF_Pos 7 /*!< SCU SFSP8_5: ZIF Position */ #define SCU_SFSP8_5_ZIF_Msk (0x01UL << SCU_SFSP8_5_ZIF_Pos) /*!< SCU SFSP8_5: ZIF Mask */ /* --------------------------------- SCU_SFSP8_6 -------------------------------- */ #define SCU_SFSP8_6_MODE_Pos 0 /*!< SCU SFSP8_6: MODE Position */ #define SCU_SFSP8_6_MODE_Msk (0x07UL << SCU_SFSP8_6_MODE_Pos) /*!< SCU SFSP8_6: MODE Mask */ #define SCU_SFSP8_6_EPD_Pos 3 /*!< SCU SFSP8_6: EPD Position */ #define SCU_SFSP8_6_EPD_Msk (0x01UL << SCU_SFSP8_6_EPD_Pos) /*!< SCU SFSP8_6: EPD Mask */ #define SCU_SFSP8_6_EPUN_Pos 4 /*!< SCU SFSP8_6: EPUN Position */ #define SCU_SFSP8_6_EPUN_Msk (0x01UL << SCU_SFSP8_6_EPUN_Pos) /*!< SCU SFSP8_6: EPUN Mask */ #define SCU_SFSP8_6_EHS_Pos 5 /*!< SCU SFSP8_6: EHS Position */ #define SCU_SFSP8_6_EHS_Msk (0x01UL << SCU_SFSP8_6_EHS_Pos) /*!< SCU SFSP8_6: EHS Mask */ #define SCU_SFSP8_6_EZI_Pos 6 /*!< SCU SFSP8_6: EZI Position */ #define SCU_SFSP8_6_EZI_Msk (0x01UL << SCU_SFSP8_6_EZI_Pos) /*!< SCU SFSP8_6: EZI Mask */ #define SCU_SFSP8_6_ZIF_Pos 7 /*!< SCU SFSP8_6: ZIF Position */ #define SCU_SFSP8_6_ZIF_Msk (0x01UL << SCU_SFSP8_6_ZIF_Pos) /*!< SCU SFSP8_6: ZIF Mask */ /* --------------------------------- SCU_SFSP8_7 -------------------------------- */ #define SCU_SFSP8_7_MODE_Pos 0 /*!< SCU SFSP8_7: MODE Position */ #define SCU_SFSP8_7_MODE_Msk (0x07UL << SCU_SFSP8_7_MODE_Pos) /*!< SCU SFSP8_7: MODE Mask */ #define SCU_SFSP8_7_EPD_Pos 3 /*!< SCU SFSP8_7: EPD Position */ #define SCU_SFSP8_7_EPD_Msk (0x01UL << SCU_SFSP8_7_EPD_Pos) /*!< SCU SFSP8_7: EPD Mask */ #define SCU_SFSP8_7_EPUN_Pos 4 /*!< SCU SFSP8_7: EPUN Position */ #define SCU_SFSP8_7_EPUN_Msk (0x01UL << SCU_SFSP8_7_EPUN_Pos) /*!< SCU SFSP8_7: EPUN Mask */ #define SCU_SFSP8_7_EHS_Pos 5 /*!< SCU SFSP8_7: EHS Position */ #define SCU_SFSP8_7_EHS_Msk (0x01UL << SCU_SFSP8_7_EHS_Pos) /*!< SCU SFSP8_7: EHS Mask */ #define SCU_SFSP8_7_EZI_Pos 6 /*!< SCU SFSP8_7: EZI Position */ #define SCU_SFSP8_7_EZI_Msk (0x01UL << SCU_SFSP8_7_EZI_Pos) /*!< SCU SFSP8_7: EZI Mask */ #define SCU_SFSP8_7_ZIF_Pos 7 /*!< SCU SFSP8_7: ZIF Position */ #define SCU_SFSP8_7_ZIF_Msk (0x01UL << SCU_SFSP8_7_ZIF_Pos) /*!< SCU SFSP8_7: ZIF Mask */ /* --------------------------------- SCU_SFSP8_8 -------------------------------- */ #define SCU_SFSP8_8_MODE_Pos 0 /*!< SCU SFSP8_8: MODE Position */ #define SCU_SFSP8_8_MODE_Msk (0x07UL << SCU_SFSP8_8_MODE_Pos) /*!< SCU SFSP8_8: MODE Mask */ #define SCU_SFSP8_8_EPD_Pos 3 /*!< SCU SFSP8_8: EPD Position */ #define SCU_SFSP8_8_EPD_Msk (0x01UL << SCU_SFSP8_8_EPD_Pos) /*!< SCU SFSP8_8: EPD Mask */ #define SCU_SFSP8_8_EPUN_Pos 4 /*!< SCU SFSP8_8: EPUN Position */ #define SCU_SFSP8_8_EPUN_Msk (0x01UL << SCU_SFSP8_8_EPUN_Pos) /*!< SCU SFSP8_8: EPUN Mask */ #define SCU_SFSP8_8_EHS_Pos 5 /*!< SCU SFSP8_8: EHS Position */ #define SCU_SFSP8_8_EHS_Msk (0x01UL << SCU_SFSP8_8_EHS_Pos) /*!< SCU SFSP8_8: EHS Mask */ #define SCU_SFSP8_8_EZI_Pos 6 /*!< SCU SFSP8_8: EZI Position */ #define SCU_SFSP8_8_EZI_Msk (0x01UL << SCU_SFSP8_8_EZI_Pos) /*!< SCU SFSP8_8: EZI Mask */ #define SCU_SFSP8_8_ZIF_Pos 7 /*!< SCU SFSP8_8: ZIF Position */ #define SCU_SFSP8_8_ZIF_Msk (0x01UL << SCU_SFSP8_8_ZIF_Pos) /*!< SCU SFSP8_8: ZIF Mask */ /* --------------------------------- SCU_SFSP9_0 -------------------------------- */ #define SCU_SFSP9_0_MODE_Pos 0 /*!< SCU SFSP9_0: MODE Position */ #define SCU_SFSP9_0_MODE_Msk (0x07UL << SCU_SFSP9_0_MODE_Pos) /*!< SCU SFSP9_0: MODE Mask */ #define SCU_SFSP9_0_EPD_Pos 3 /*!< SCU SFSP9_0: EPD Position */ #define SCU_SFSP9_0_EPD_Msk (0x01UL << SCU_SFSP9_0_EPD_Pos) /*!< SCU SFSP9_0: EPD Mask */ #define SCU_SFSP9_0_EPUN_Pos 4 /*!< SCU SFSP9_0: EPUN Position */ #define SCU_SFSP9_0_EPUN_Msk (0x01UL << SCU_SFSP9_0_EPUN_Pos) /*!< SCU SFSP9_0: EPUN Mask */ #define SCU_SFSP9_0_EHS_Pos 5 /*!< SCU SFSP9_0: EHS Position */ #define SCU_SFSP9_0_EHS_Msk (0x01UL << SCU_SFSP9_0_EHS_Pos) /*!< SCU SFSP9_0: EHS Mask */ #define SCU_SFSP9_0_EZI_Pos 6 /*!< SCU SFSP9_0: EZI Position */ #define SCU_SFSP9_0_EZI_Msk (0x01UL << SCU_SFSP9_0_EZI_Pos) /*!< SCU SFSP9_0: EZI Mask */ #define SCU_SFSP9_0_EHD_Pos 8 /*!< SCU SFSP9_0: EHD Position */ #define SCU_SFSP9_0_EHD_Msk (0x03UL << SCU_SFSP9_0_EHD_Pos) /*!< SCU SFSP9_0: EHD Mask */ /* --------------------------------- SCU_SFSP9_1 -------------------------------- */ #define SCU_SFSP9_1_MODE_Pos 0 /*!< SCU SFSP9_1: MODE Position */ #define SCU_SFSP9_1_MODE_Msk (0x07UL << SCU_SFSP9_1_MODE_Pos) /*!< SCU SFSP9_1: MODE Mask */ #define SCU_SFSP9_1_EPD_Pos 3 /*!< SCU SFSP9_1: EPD Position */ #define SCU_SFSP9_1_EPD_Msk (0x01UL << SCU_SFSP9_1_EPD_Pos) /*!< SCU SFSP9_1: EPD Mask */ #define SCU_SFSP9_1_EPUN_Pos 4 /*!< SCU SFSP9_1: EPUN Position */ #define SCU_SFSP9_1_EPUN_Msk (0x01UL << SCU_SFSP9_1_EPUN_Pos) /*!< SCU SFSP9_1: EPUN Mask */ #define SCU_SFSP9_1_EHS_Pos 5 /*!< SCU SFSP9_1: EHS Position */ #define SCU_SFSP9_1_EHS_Msk (0x01UL << SCU_SFSP9_1_EHS_Pos) /*!< SCU SFSP9_1: EHS Mask */ #define SCU_SFSP9_1_EZI_Pos 6 /*!< SCU SFSP9_1: EZI Position */ #define SCU_SFSP9_1_EZI_Msk (0x01UL << SCU_SFSP9_1_EZI_Pos) /*!< SCU SFSP9_1: EZI Mask */ #define SCU_SFSP9_1_EHD_Pos 8 /*!< SCU SFSP9_1: EHD Position */ #define SCU_SFSP9_1_EHD_Msk (0x03UL << SCU_SFSP9_1_EHD_Pos) /*!< SCU SFSP9_1: EHD Mask */ /* --------------------------------- SCU_SFSP9_2 -------------------------------- */ #define SCU_SFSP9_2_MODE_Pos 0 /*!< SCU SFSP9_2: MODE Position */ #define SCU_SFSP9_2_MODE_Msk (0x07UL << SCU_SFSP9_2_MODE_Pos) /*!< SCU SFSP9_2: MODE Mask */ #define SCU_SFSP9_2_EPD_Pos 3 /*!< SCU SFSP9_2: EPD Position */ #define SCU_SFSP9_2_EPD_Msk (0x01UL << SCU_SFSP9_2_EPD_Pos) /*!< SCU SFSP9_2: EPD Mask */ #define SCU_SFSP9_2_EPUN_Pos 4 /*!< SCU SFSP9_2: EPUN Position */ #define SCU_SFSP9_2_EPUN_Msk (0x01UL << SCU_SFSP9_2_EPUN_Pos) /*!< SCU SFSP9_2: EPUN Mask */ #define SCU_SFSP9_2_EHS_Pos 5 /*!< SCU SFSP9_2: EHS Position */ #define SCU_SFSP9_2_EHS_Msk (0x01UL << SCU_SFSP9_2_EHS_Pos) /*!< SCU SFSP9_2: EHS Mask */ #define SCU_SFSP9_2_EZI_Pos 6 /*!< SCU SFSP9_2: EZI Position */ #define SCU_SFSP9_2_EZI_Msk (0x01UL << SCU_SFSP9_2_EZI_Pos) /*!< SCU SFSP9_2: EZI Mask */ #define SCU_SFSP9_2_EHD_Pos 8 /*!< SCU SFSP9_2: EHD Position */ #define SCU_SFSP9_2_EHD_Msk (0x03UL << SCU_SFSP9_2_EHD_Pos) /*!< SCU SFSP9_2: EHD Mask */ /* --------------------------------- SCU_SFSP9_3 -------------------------------- */ #define SCU_SFSP9_3_MODE_Pos 0 /*!< SCU SFSP9_3: MODE Position */ #define SCU_SFSP9_3_MODE_Msk (0x07UL << SCU_SFSP9_3_MODE_Pos) /*!< SCU SFSP9_3: MODE Mask */ #define SCU_SFSP9_3_EPD_Pos 3 /*!< SCU SFSP9_3: EPD Position */ #define SCU_SFSP9_3_EPD_Msk (0x01UL << SCU_SFSP9_3_EPD_Pos) /*!< SCU SFSP9_3: EPD Mask */ #define SCU_SFSP9_3_EPUN_Pos 4 /*!< SCU SFSP9_3: EPUN Position */ #define SCU_SFSP9_3_EPUN_Msk (0x01UL << SCU_SFSP9_3_EPUN_Pos) /*!< SCU SFSP9_3: EPUN Mask */ #define SCU_SFSP9_3_EHS_Pos 5 /*!< SCU SFSP9_3: EHS Position */ #define SCU_SFSP9_3_EHS_Msk (0x01UL << SCU_SFSP9_3_EHS_Pos) /*!< SCU SFSP9_3: EHS Mask */ #define SCU_SFSP9_3_EZI_Pos 6 /*!< SCU SFSP9_3: EZI Position */ #define SCU_SFSP9_3_EZI_Msk (0x01UL << SCU_SFSP9_3_EZI_Pos) /*!< SCU SFSP9_3: EZI Mask */ #define SCU_SFSP9_3_EHD_Pos 8 /*!< SCU SFSP9_3: EHD Position */ #define SCU_SFSP9_3_EHD_Msk (0x03UL << SCU_SFSP9_3_EHD_Pos) /*!< SCU SFSP9_3: EHD Mask */ /* --------------------------------- SCU_SFSP9_4 -------------------------------- */ #define SCU_SFSP9_4_MODE_Pos 0 /*!< SCU SFSP9_4: MODE Position */ #define SCU_SFSP9_4_MODE_Msk (0x07UL << SCU_SFSP9_4_MODE_Pos) /*!< SCU SFSP9_4: MODE Mask */ #define SCU_SFSP9_4_EPD_Pos 3 /*!< SCU SFSP9_4: EPD Position */ #define SCU_SFSP9_4_EPD_Msk (0x01UL << SCU_SFSP9_4_EPD_Pos) /*!< SCU SFSP9_4: EPD Mask */ #define SCU_SFSP9_4_EPUN_Pos 4 /*!< SCU SFSP9_4: EPUN Position */ #define SCU_SFSP9_4_EPUN_Msk (0x01UL << SCU_SFSP9_4_EPUN_Pos) /*!< SCU SFSP9_4: EPUN Mask */ #define SCU_SFSP9_4_EHS_Pos 5 /*!< SCU SFSP9_4: EHS Position */ #define SCU_SFSP9_4_EHS_Msk (0x01UL << SCU_SFSP9_4_EHS_Pos) /*!< SCU SFSP9_4: EHS Mask */ #define SCU_SFSP9_4_EZI_Pos 6 /*!< SCU SFSP9_4: EZI Position */ #define SCU_SFSP9_4_EZI_Msk (0x01UL << SCU_SFSP9_4_EZI_Pos) /*!< SCU SFSP9_4: EZI Mask */ #define SCU_SFSP9_4_EHD_Pos 8 /*!< SCU SFSP9_4: EHD Position */ #define SCU_SFSP9_4_EHD_Msk (0x03UL << SCU_SFSP9_4_EHD_Pos) /*!< SCU SFSP9_4: EHD Mask */ /* --------------------------------- SCU_SFSP9_5 -------------------------------- */ #define SCU_SFSP9_5_MODE_Pos 0 /*!< SCU SFSP9_5: MODE Position */ #define SCU_SFSP9_5_MODE_Msk (0x07UL << SCU_SFSP9_5_MODE_Pos) /*!< SCU SFSP9_5: MODE Mask */ #define SCU_SFSP9_5_EPD_Pos 3 /*!< SCU SFSP9_5: EPD Position */ #define SCU_SFSP9_5_EPD_Msk (0x01UL << SCU_SFSP9_5_EPD_Pos) /*!< SCU SFSP9_5: EPD Mask */ #define SCU_SFSP9_5_EPUN_Pos 4 /*!< SCU SFSP9_5: EPUN Position */ #define SCU_SFSP9_5_EPUN_Msk (0x01UL << SCU_SFSP9_5_EPUN_Pos) /*!< SCU SFSP9_5: EPUN Mask */ #define SCU_SFSP9_5_EHS_Pos 5 /*!< SCU SFSP9_5: EHS Position */ #define SCU_SFSP9_5_EHS_Msk (0x01UL << SCU_SFSP9_5_EHS_Pos) /*!< SCU SFSP9_5: EHS Mask */ #define SCU_SFSP9_5_EZI_Pos 6 /*!< SCU SFSP9_5: EZI Position */ #define SCU_SFSP9_5_EZI_Msk (0x01UL << SCU_SFSP9_5_EZI_Pos) /*!< SCU SFSP9_5: EZI Mask */ #define SCU_SFSP9_5_EHD_Pos 8 /*!< SCU SFSP9_5: EHD Position */ #define SCU_SFSP9_5_EHD_Msk (0x03UL << SCU_SFSP9_5_EHD_Pos) /*!< SCU SFSP9_5: EHD Mask */ /* --------------------------------- SCU_SFSP9_6 -------------------------------- */ #define SCU_SFSP9_6_MODE_Pos 0 /*!< SCU SFSP9_6: MODE Position */ #define SCU_SFSP9_6_MODE_Msk (0x07UL << SCU_SFSP9_6_MODE_Pos) /*!< SCU SFSP9_6: MODE Mask */ #define SCU_SFSP9_6_EPD_Pos 3 /*!< SCU SFSP9_6: EPD Position */ #define SCU_SFSP9_6_EPD_Msk (0x01UL << SCU_SFSP9_6_EPD_Pos) /*!< SCU SFSP9_6: EPD Mask */ #define SCU_SFSP9_6_EPUN_Pos 4 /*!< SCU SFSP9_6: EPUN Position */ #define SCU_SFSP9_6_EPUN_Msk (0x01UL << SCU_SFSP9_6_EPUN_Pos) /*!< SCU SFSP9_6: EPUN Mask */ #define SCU_SFSP9_6_EHS_Pos 5 /*!< SCU SFSP9_6: EHS Position */ #define SCU_SFSP9_6_EHS_Msk (0x01UL << SCU_SFSP9_6_EHS_Pos) /*!< SCU SFSP9_6: EHS Mask */ #define SCU_SFSP9_6_EZI_Pos 6 /*!< SCU SFSP9_6: EZI Position */ #define SCU_SFSP9_6_EZI_Msk (0x01UL << SCU_SFSP9_6_EZI_Pos) /*!< SCU SFSP9_6: EZI Mask */ #define SCU_SFSP9_6_EHD_Pos 8 /*!< SCU SFSP9_6: EHD Position */ #define SCU_SFSP9_6_EHD_Msk (0x03UL << SCU_SFSP9_6_EHD_Pos) /*!< SCU SFSP9_6: EHD Mask */ /* --------------------------------- SCU_SFSPA_0 -------------------------------- */ #define SCU_SFSPA_0_MODE_Pos 0 /*!< SCU SFSPA_0: MODE Position */ #define SCU_SFSPA_0_MODE_Msk (0x07UL << SCU_SFSPA_0_MODE_Pos) /*!< SCU SFSPA_0: MODE Mask */ #define SCU_SFSPA_0_EPD_Pos 3 /*!< SCU SFSPA_0: EPD Position */ #define SCU_SFSPA_0_EPD_Msk (0x01UL << SCU_SFSPA_0_EPD_Pos) /*!< SCU SFSPA_0: EPD Mask */ #define SCU_SFSPA_0_EPUN_Pos 4 /*!< SCU SFSPA_0: EPUN Position */ #define SCU_SFSPA_0_EPUN_Msk (0x01UL << SCU_SFSPA_0_EPUN_Pos) /*!< SCU SFSPA_0: EPUN Mask */ #define SCU_SFSPA_0_EHS_Pos 5 /*!< SCU SFSPA_0: EHS Position */ #define SCU_SFSPA_0_EHS_Msk (0x01UL << SCU_SFSPA_0_EHS_Pos) /*!< SCU SFSPA_0: EHS Mask */ #define SCU_SFSPA_0_EZI_Pos 6 /*!< SCU SFSPA_0: EZI Position */ #define SCU_SFSPA_0_EZI_Msk (0x01UL << SCU_SFSPA_0_EZI_Pos) /*!< SCU SFSPA_0: EZI Mask */ #define SCU_SFSPA_0_ZIF_Pos 7 /*!< SCU SFSPA_0: ZIF Position */ #define SCU_SFSPA_0_ZIF_Msk (0x01UL << SCU_SFSPA_0_ZIF_Pos) /*!< SCU SFSPA_0: ZIF Mask */ /* --------------------------------- SCU_SFSPA_1 -------------------------------- */ #define SCU_SFSPA_1_MODE_Pos 0 /*!< SCU SFSPA_1: MODE Position */ #define SCU_SFSPA_1_MODE_Msk (0x07UL << SCU_SFSPA_1_MODE_Pos) /*!< SCU SFSPA_1: MODE Mask */ #define SCU_SFSPA_1_EPD_Pos 3 /*!< SCU SFSPA_1: EPD Position */ #define SCU_SFSPA_1_EPD_Msk (0x01UL << SCU_SFSPA_1_EPD_Pos) /*!< SCU SFSPA_1: EPD Mask */ #define SCU_SFSPA_1_EPUN_Pos 4 /*!< SCU SFSPA_1: EPUN Position */ #define SCU_SFSPA_1_EPUN_Msk (0x01UL << SCU_SFSPA_1_EPUN_Pos) /*!< SCU SFSPA_1: EPUN Mask */ #define SCU_SFSPA_1_EZI_Pos 6 /*!< SCU SFSPA_1: EZI Position */ #define SCU_SFSPA_1_EZI_Msk (0x01UL << SCU_SFSPA_1_EZI_Pos) /*!< SCU SFSPA_1: EZI Mask */ #define SCU_SFSPA_1_ZIF_Pos 7 /*!< SCU SFSPA_1: ZIF Position */ #define SCU_SFSPA_1_ZIF_Msk (0x01UL << SCU_SFSPA_1_ZIF_Pos) /*!< SCU SFSPA_1: ZIF Mask */ #define SCU_SFSPA_1_EHD_Pos 8 /*!< SCU SFSPA_1: EHD Position */ #define SCU_SFSPA_1_EHD_Msk (0x03UL << SCU_SFSPA_1_EHD_Pos) /*!< SCU SFSPA_1: EHD Mask */ /* --------------------------------- SCU_SFSPA_2 -------------------------------- */ #define SCU_SFSPA_2_MODE_Pos 0 /*!< SCU SFSPA_2: MODE Position */ #define SCU_SFSPA_2_MODE_Msk (0x07UL << SCU_SFSPA_2_MODE_Pos) /*!< SCU SFSPA_2: MODE Mask */ #define SCU_SFSPA_2_EPD_Pos 3 /*!< SCU SFSPA_2: EPD Position */ #define SCU_SFSPA_2_EPD_Msk (0x01UL << SCU_SFSPA_2_EPD_Pos) /*!< SCU SFSPA_2: EPD Mask */ #define SCU_SFSPA_2_EPUN_Pos 4 /*!< SCU SFSPA_2: EPUN Position */ #define SCU_SFSPA_2_EPUN_Msk (0x01UL << SCU_SFSPA_2_EPUN_Pos) /*!< SCU SFSPA_2: EPUN Mask */ #define SCU_SFSPA_2_EZI_Pos 6 /*!< SCU SFSPA_2: EZI Position */ #define SCU_SFSPA_2_EZI_Msk (0x01UL << SCU_SFSPA_2_EZI_Pos) /*!< SCU SFSPA_2: EZI Mask */ #define SCU_SFSPA_2_ZIF_Pos 7 /*!< SCU SFSPA_2: ZIF Position */ #define SCU_SFSPA_2_ZIF_Msk (0x01UL << SCU_SFSPA_2_ZIF_Pos) /*!< SCU SFSPA_2: ZIF Mask */ #define SCU_SFSPA_2_EHD_Pos 8 /*!< SCU SFSPA_2: EHD Position */ #define SCU_SFSPA_2_EHD_Msk (0x03UL << SCU_SFSPA_2_EHD_Pos) /*!< SCU SFSPA_2: EHD Mask */ /* --------------------------------- SCU_SFSPA_3 -------------------------------- */ #define SCU_SFSPA_3_MODE_Pos 0 /*!< SCU SFSPA_3: MODE Position */ #define SCU_SFSPA_3_MODE_Msk (0x07UL << SCU_SFSPA_3_MODE_Pos) /*!< SCU SFSPA_3: MODE Mask */ #define SCU_SFSPA_3_EPD_Pos 3 /*!< SCU SFSPA_3: EPD Position */ #define SCU_SFSPA_3_EPD_Msk (0x01UL << SCU_SFSPA_3_EPD_Pos) /*!< SCU SFSPA_3: EPD Mask */ #define SCU_SFSPA_3_EPUN_Pos 4 /*!< SCU SFSPA_3: EPUN Position */ #define SCU_SFSPA_3_EPUN_Msk (0x01UL << SCU_SFSPA_3_EPUN_Pos) /*!< SCU SFSPA_3: EPUN Mask */ #define SCU_SFSPA_3_EZI_Pos 6 /*!< SCU SFSPA_3: EZI Position */ #define SCU_SFSPA_3_EZI_Msk (0x01UL << SCU_SFSPA_3_EZI_Pos) /*!< SCU SFSPA_3: EZI Mask */ #define SCU_SFSPA_3_ZIF_Pos 7 /*!< SCU SFSPA_3: ZIF Position */ #define SCU_SFSPA_3_ZIF_Msk (0x01UL << SCU_SFSPA_3_ZIF_Pos) /*!< SCU SFSPA_3: ZIF Mask */ #define SCU_SFSPA_3_EHD_Pos 8 /*!< SCU SFSPA_3: EHD Position */ #define SCU_SFSPA_3_EHD_Msk (0x03UL << SCU_SFSPA_3_EHD_Pos) /*!< SCU SFSPA_3: EHD Mask */ /* --------------------------------- SCU_SFSPA_4 -------------------------------- */ #define SCU_SFSPA_4_MODE_Pos 0 /*!< SCU SFSPA_4: MODE Position */ #define SCU_SFSPA_4_MODE_Msk (0x07UL << SCU_SFSPA_4_MODE_Pos) /*!< SCU SFSPA_4: MODE Mask */ #define SCU_SFSPA_4_EPD_Pos 3 /*!< SCU SFSPA_4: EPD Position */ #define SCU_SFSPA_4_EPD_Msk (0x01UL << SCU_SFSPA_4_EPD_Pos) /*!< SCU SFSPA_4: EPD Mask */ #define SCU_SFSPA_4_EPUN_Pos 4 /*!< SCU SFSPA_4: EPUN Position */ #define SCU_SFSPA_4_EPUN_Msk (0x01UL << SCU_SFSPA_4_EPUN_Pos) /*!< SCU SFSPA_4: EPUN Mask */ #define SCU_SFSPA_4_EHS_Pos 5 /*!< SCU SFSPA_4: EHS Position */ #define SCU_SFSPA_4_EHS_Msk (0x01UL << SCU_SFSPA_4_EHS_Pos) /*!< SCU SFSPA_4: EHS Mask */ #define SCU_SFSPA_4_EZI_Pos 6 /*!< SCU SFSPA_4: EZI Position */ #define SCU_SFSPA_4_EZI_Msk (0x01UL << SCU_SFSPA_4_EZI_Pos) /*!< SCU SFSPA_4: EZI Mask */ #define SCU_SFSPA_4_ZIF_Pos 7 /*!< SCU SFSPA_4: ZIF Position */ #define SCU_SFSPA_4_ZIF_Msk (0x01UL << SCU_SFSPA_4_ZIF_Pos) /*!< SCU SFSPA_4: ZIF Mask */ /* --------------------------------- SCU_SFSPB_0 -------------------------------- */ #define SCU_SFSPB_0_MODE_Pos 0 /*!< SCU SFSPB_0: MODE Position */ #define SCU_SFSPB_0_MODE_Msk (0x07UL << SCU_SFSPB_0_MODE_Pos) /*!< SCU SFSPB_0: MODE Mask */ #define SCU_SFSPB_0_EPD_Pos 3 /*!< SCU SFSPB_0: EPD Position */ #define SCU_SFSPB_0_EPD_Msk (0x01UL << SCU_SFSPB_0_EPD_Pos) /*!< SCU SFSPB_0: EPD Mask */ #define SCU_SFSPB_0_EPUN_Pos 4 /*!< SCU SFSPB_0: EPUN Position */ #define SCU_SFSPB_0_EPUN_Msk (0x01UL << SCU_SFSPB_0_EPUN_Pos) /*!< SCU SFSPB_0: EPUN Mask */ #define SCU_SFSPB_0_EHS_Pos 5 /*!< SCU SFSPB_0: EHS Position */ #define SCU_SFSPB_0_EHS_Msk (0x01UL << SCU_SFSPB_0_EHS_Pos) /*!< SCU SFSPB_0: EHS Mask */ #define SCU_SFSPB_0_EZI_Pos 6 /*!< SCU SFSPB_0: EZI Position */ #define SCU_SFSPB_0_EZI_Msk (0x01UL << SCU_SFSPB_0_EZI_Pos) /*!< SCU SFSPB_0: EZI Mask */ #define SCU_SFSPB_0_ZIF_Pos 7 /*!< SCU SFSPB_0: ZIF Position */ #define SCU_SFSPB_0_ZIF_Msk (0x01UL << SCU_SFSPB_0_ZIF_Pos) /*!< SCU SFSPB_0: ZIF Mask */ /* --------------------------------- SCU_SFSPB_1 -------------------------------- */ #define SCU_SFSPB_1_MODE_Pos 0 /*!< SCU SFSPB_1: MODE Position */ #define SCU_SFSPB_1_MODE_Msk (0x07UL << SCU_SFSPB_1_MODE_Pos) /*!< SCU SFSPB_1: MODE Mask */ #define SCU_SFSPB_1_EPD_Pos 3 /*!< SCU SFSPB_1: EPD Position */ #define SCU_SFSPB_1_EPD_Msk (0x01UL << SCU_SFSPB_1_EPD_Pos) /*!< SCU SFSPB_1: EPD Mask */ #define SCU_SFSPB_1_EPUN_Pos 4 /*!< SCU SFSPB_1: EPUN Position */ #define SCU_SFSPB_1_EPUN_Msk (0x01UL << SCU_SFSPB_1_EPUN_Pos) /*!< SCU SFSPB_1: EPUN Mask */ #define SCU_SFSPB_1_EHS_Pos 5 /*!< SCU SFSPB_1: EHS Position */ #define SCU_SFSPB_1_EHS_Msk (0x01UL << SCU_SFSPB_1_EHS_Pos) /*!< SCU SFSPB_1: EHS Mask */ #define SCU_SFSPB_1_EZI_Pos 6 /*!< SCU SFSPB_1: EZI Position */ #define SCU_SFSPB_1_EZI_Msk (0x01UL << SCU_SFSPB_1_EZI_Pos) /*!< SCU SFSPB_1: EZI Mask */ #define SCU_SFSPB_1_ZIF_Pos 7 /*!< SCU SFSPB_1: ZIF Position */ #define SCU_SFSPB_1_ZIF_Msk (0x01UL << SCU_SFSPB_1_ZIF_Pos) /*!< SCU SFSPB_1: ZIF Mask */ /* --------------------------------- SCU_SFSPB_2 -------------------------------- */ #define SCU_SFSPB_2_MODE_Pos 0 /*!< SCU SFSPB_2: MODE Position */ #define SCU_SFSPB_2_MODE_Msk (0x07UL << SCU_SFSPB_2_MODE_Pos) /*!< SCU SFSPB_2: MODE Mask */ #define SCU_SFSPB_2_EPD_Pos 3 /*!< SCU SFSPB_2: EPD Position */ #define SCU_SFSPB_2_EPD_Msk (0x01UL << SCU_SFSPB_2_EPD_Pos) /*!< SCU SFSPB_2: EPD Mask */ #define SCU_SFSPB_2_EPUN_Pos 4 /*!< SCU SFSPB_2: EPUN Position */ #define SCU_SFSPB_2_EPUN_Msk (0x01UL << SCU_SFSPB_2_EPUN_Pos) /*!< SCU SFSPB_2: EPUN Mask */ #define SCU_SFSPB_2_EHS_Pos 5 /*!< SCU SFSPB_2: EHS Position */ #define SCU_SFSPB_2_EHS_Msk (0x01UL << SCU_SFSPB_2_EHS_Pos) /*!< SCU SFSPB_2: EHS Mask */ #define SCU_SFSPB_2_EZI_Pos 6 /*!< SCU SFSPB_2: EZI Position */ #define SCU_SFSPB_2_EZI_Msk (0x01UL << SCU_SFSPB_2_EZI_Pos) /*!< SCU SFSPB_2: EZI Mask */ #define SCU_SFSPB_2_ZIF_Pos 7 /*!< SCU SFSPB_2: ZIF Position */ #define SCU_SFSPB_2_ZIF_Msk (0x01UL << SCU_SFSPB_2_ZIF_Pos) /*!< SCU SFSPB_2: ZIF Mask */ /* --------------------------------- SCU_SFSPB_3 -------------------------------- */ #define SCU_SFSPB_3_MODE_Pos 0 /*!< SCU SFSPB_3: MODE Position */ #define SCU_SFSPB_3_MODE_Msk (0x07UL << SCU_SFSPB_3_MODE_Pos) /*!< SCU SFSPB_3: MODE Mask */ #define SCU_SFSPB_3_EPD_Pos 3 /*!< SCU SFSPB_3: EPD Position */ #define SCU_SFSPB_3_EPD_Msk (0x01UL << SCU_SFSPB_3_EPD_Pos) /*!< SCU SFSPB_3: EPD Mask */ #define SCU_SFSPB_3_EPUN_Pos 4 /*!< SCU SFSPB_3: EPUN Position */ #define SCU_SFSPB_3_EPUN_Msk (0x01UL << SCU_SFSPB_3_EPUN_Pos) /*!< SCU SFSPB_3: EPUN Mask */ #define SCU_SFSPB_3_EHS_Pos 5 /*!< SCU SFSPB_3: EHS Position */ #define SCU_SFSPB_3_EHS_Msk (0x01UL << SCU_SFSPB_3_EHS_Pos) /*!< SCU SFSPB_3: EHS Mask */ #define SCU_SFSPB_3_EZI_Pos 6 /*!< SCU SFSPB_3: EZI Position */ #define SCU_SFSPB_3_EZI_Msk (0x01UL << SCU_SFSPB_3_EZI_Pos) /*!< SCU SFSPB_3: EZI Mask */ #define SCU_SFSPB_3_ZIF_Pos 7 /*!< SCU SFSPB_3: ZIF Position */ #define SCU_SFSPB_3_ZIF_Msk (0x01UL << SCU_SFSPB_3_ZIF_Pos) /*!< SCU SFSPB_3: ZIF Mask */ /* --------------------------------- SCU_SFSPB_4 -------------------------------- */ #define SCU_SFSPB_4_MODE_Pos 0 /*!< SCU SFSPB_4: MODE Position */ #define SCU_SFSPB_4_MODE_Msk (0x07UL << SCU_SFSPB_4_MODE_Pos) /*!< SCU SFSPB_4: MODE Mask */ #define SCU_SFSPB_4_EPD_Pos 3 /*!< SCU SFSPB_4: EPD Position */ #define SCU_SFSPB_4_EPD_Msk (0x01UL << SCU_SFSPB_4_EPD_Pos) /*!< SCU SFSPB_4: EPD Mask */ #define SCU_SFSPB_4_EPUN_Pos 4 /*!< SCU SFSPB_4: EPUN Position */ #define SCU_SFSPB_4_EPUN_Msk (0x01UL << SCU_SFSPB_4_EPUN_Pos) /*!< SCU SFSPB_4: EPUN Mask */ #define SCU_SFSPB_4_EHS_Pos 5 /*!< SCU SFSPB_4: EHS Position */ #define SCU_SFSPB_4_EHS_Msk (0x01UL << SCU_SFSPB_4_EHS_Pos) /*!< SCU SFSPB_4: EHS Mask */ #define SCU_SFSPB_4_EZI_Pos 6 /*!< SCU SFSPB_4: EZI Position */ #define SCU_SFSPB_4_EZI_Msk (0x01UL << SCU_SFSPB_4_EZI_Pos) /*!< SCU SFSPB_4: EZI Mask */ #define SCU_SFSPB_4_ZIF_Pos 7 /*!< SCU SFSPB_4: ZIF Position */ #define SCU_SFSPB_4_ZIF_Msk (0x01UL << SCU_SFSPB_4_ZIF_Pos) /*!< SCU SFSPB_4: ZIF Mask */ /* --------------------------------- SCU_SFSPB_5 -------------------------------- */ #define SCU_SFSPB_5_MODE_Pos 0 /*!< SCU SFSPB_5: MODE Position */ #define SCU_SFSPB_5_MODE_Msk (0x07UL << SCU_SFSPB_5_MODE_Pos) /*!< SCU SFSPB_5: MODE Mask */ #define SCU_SFSPB_5_EPD_Pos 3 /*!< SCU SFSPB_5: EPD Position */ #define SCU_SFSPB_5_EPD_Msk (0x01UL << SCU_SFSPB_5_EPD_Pos) /*!< SCU SFSPB_5: EPD Mask */ #define SCU_SFSPB_5_EPUN_Pos 4 /*!< SCU SFSPB_5: EPUN Position */ #define SCU_SFSPB_5_EPUN_Msk (0x01UL << SCU_SFSPB_5_EPUN_Pos) /*!< SCU SFSPB_5: EPUN Mask */ #define SCU_SFSPB_5_EHS_Pos 5 /*!< SCU SFSPB_5: EHS Position */ #define SCU_SFSPB_5_EHS_Msk (0x01UL << SCU_SFSPB_5_EHS_Pos) /*!< SCU SFSPB_5: EHS Mask */ #define SCU_SFSPB_5_EZI_Pos 6 /*!< SCU SFSPB_5: EZI Position */ #define SCU_SFSPB_5_EZI_Msk (0x01UL << SCU_SFSPB_5_EZI_Pos) /*!< SCU SFSPB_5: EZI Mask */ #define SCU_SFSPB_5_ZIF_Pos 7 /*!< SCU SFSPB_5: ZIF Position */ #define SCU_SFSPB_5_ZIF_Msk (0x01UL << SCU_SFSPB_5_ZIF_Pos) /*!< SCU SFSPB_5: ZIF Mask */ /* --------------------------------- SCU_SFSPB_6 -------------------------------- */ #define SCU_SFSPB_6_MODE_Pos 0 /*!< SCU SFSPB_6: MODE Position */ #define SCU_SFSPB_6_MODE_Msk (0x07UL << SCU_SFSPB_6_MODE_Pos) /*!< SCU SFSPB_6: MODE Mask */ #define SCU_SFSPB_6_EPD_Pos 3 /*!< SCU SFSPB_6: EPD Position */ #define SCU_SFSPB_6_EPD_Msk (0x01UL << SCU_SFSPB_6_EPD_Pos) /*!< SCU SFSPB_6: EPD Mask */ #define SCU_SFSPB_6_EPUN_Pos 4 /*!< SCU SFSPB_6: EPUN Position */ #define SCU_SFSPB_6_EPUN_Msk (0x01UL << SCU_SFSPB_6_EPUN_Pos) /*!< SCU SFSPB_6: EPUN Mask */ #define SCU_SFSPB_6_EHS_Pos 5 /*!< SCU SFSPB_6: EHS Position */ #define SCU_SFSPB_6_EHS_Msk (0x01UL << SCU_SFSPB_6_EHS_Pos) /*!< SCU SFSPB_6: EHS Mask */ #define SCU_SFSPB_6_EZI_Pos 6 /*!< SCU SFSPB_6: EZI Position */ #define SCU_SFSPB_6_EZI_Msk (0x01UL << SCU_SFSPB_6_EZI_Pos) /*!< SCU SFSPB_6: EZI Mask */ #define SCU_SFSPB_6_ZIF_Pos 7 /*!< SCU SFSPB_6: ZIF Position */ #define SCU_SFSPB_6_ZIF_Msk (0x01UL << SCU_SFSPB_6_ZIF_Pos) /*!< SCU SFSPB_6: ZIF Mask */ /* --------------------------------- SCU_SFSPC_0 -------------------------------- */ #define SCU_SFSPC_0_MODE_Pos 0 /*!< SCU SFSPC_0: MODE Position */ #define SCU_SFSPC_0_MODE_Msk (0x07UL << SCU_SFSPC_0_MODE_Pos) /*!< SCU SFSPC_0: MODE Mask */ #define SCU_SFSPC_0_EPD_Pos 3 /*!< SCU SFSPC_0: EPD Position */ #define SCU_SFSPC_0_EPD_Msk (0x01UL << SCU_SFSPC_0_EPD_Pos) /*!< SCU SFSPC_0: EPD Mask */ #define SCU_SFSPC_0_EPUN_Pos 4 /*!< SCU SFSPC_0: EPUN Position */ #define SCU_SFSPC_0_EPUN_Msk (0x01UL << SCU_SFSPC_0_EPUN_Pos) /*!< SCU SFSPC_0: EPUN Mask */ #define SCU_SFSPC_0_EHS_Pos 5 /*!< SCU SFSPC_0: EHS Position */ #define SCU_SFSPC_0_EHS_Msk (0x01UL << SCU_SFSPC_0_EHS_Pos) /*!< SCU SFSPC_0: EHS Mask */ #define SCU_SFSPC_0_EZI_Pos 6 /*!< SCU SFSPC_0: EZI Position */ #define SCU_SFSPC_0_EZI_Msk (0x01UL << SCU_SFSPC_0_EZI_Pos) /*!< SCU SFSPC_0: EZI Mask */ #define SCU_SFSPC_0_ZIF_Pos 7 /*!< SCU SFSPC_0: ZIF Position */ #define SCU_SFSPC_0_ZIF_Msk (0x01UL << SCU_SFSPC_0_ZIF_Pos) /*!< SCU SFSPC_0: ZIF Mask */ /* --------------------------------- SCU_SFSPC_1 -------------------------------- */ #define SCU_SFSPC_1_MODE_Pos 0 /*!< SCU SFSPC_1: MODE Position */ #define SCU_SFSPC_1_MODE_Msk (0x07UL << SCU_SFSPC_1_MODE_Pos) /*!< SCU SFSPC_1: MODE Mask */ #define SCU_SFSPC_1_EPD_Pos 3 /*!< SCU SFSPC_1: EPD Position */ #define SCU_SFSPC_1_EPD_Msk (0x01UL << SCU_SFSPC_1_EPD_Pos) /*!< SCU SFSPC_1: EPD Mask */ #define SCU_SFSPC_1_EPUN_Pos 4 /*!< SCU SFSPC_1: EPUN Position */ #define SCU_SFSPC_1_EPUN_Msk (0x01UL << SCU_SFSPC_1_EPUN_Pos) /*!< SCU SFSPC_1: EPUN Mask */ #define SCU_SFSPC_1_EHS_Pos 5 /*!< SCU SFSPC_1: EHS Position */ #define SCU_SFSPC_1_EHS_Msk (0x01UL << SCU_SFSPC_1_EHS_Pos) /*!< SCU SFSPC_1: EHS Mask */ #define SCU_SFSPC_1_EZI_Pos 6 /*!< SCU SFSPC_1: EZI Position */ #define SCU_SFSPC_1_EZI_Msk (0x01UL << SCU_SFSPC_1_EZI_Pos) /*!< SCU SFSPC_1: EZI Mask */ #define SCU_SFSPC_1_ZIF_Pos 7 /*!< SCU SFSPC_1: ZIF Position */ #define SCU_SFSPC_1_ZIF_Msk (0x01UL << SCU_SFSPC_1_ZIF_Pos) /*!< SCU SFSPC_1: ZIF Mask */ /* --------------------------------- SCU_SFSPC_2 -------------------------------- */ #define SCU_SFSPC_2_MODE_Pos 0 /*!< SCU SFSPC_2: MODE Position */ #define SCU_SFSPC_2_MODE_Msk (0x07UL << SCU_SFSPC_2_MODE_Pos) /*!< SCU SFSPC_2: MODE Mask */ #define SCU_SFSPC_2_EPD_Pos 3 /*!< SCU SFSPC_2: EPD Position */ #define SCU_SFSPC_2_EPD_Msk (0x01UL << SCU_SFSPC_2_EPD_Pos) /*!< SCU SFSPC_2: EPD Mask */ #define SCU_SFSPC_2_EPUN_Pos 4 /*!< SCU SFSPC_2: EPUN Position */ #define SCU_SFSPC_2_EPUN_Msk (0x01UL << SCU_SFSPC_2_EPUN_Pos) /*!< SCU SFSPC_2: EPUN Mask */ #define SCU_SFSPC_2_EHS_Pos 5 /*!< SCU SFSPC_2: EHS Position */ #define SCU_SFSPC_2_EHS_Msk (0x01UL << SCU_SFSPC_2_EHS_Pos) /*!< SCU SFSPC_2: EHS Mask */ #define SCU_SFSPC_2_EZI_Pos 6 /*!< SCU SFSPC_2: EZI Position */ #define SCU_SFSPC_2_EZI_Msk (0x01UL << SCU_SFSPC_2_EZI_Pos) /*!< SCU SFSPC_2: EZI Mask */ #define SCU_SFSPC_2_ZIF_Pos 7 /*!< SCU SFSPC_2: ZIF Position */ #define SCU_SFSPC_2_ZIF_Msk (0x01UL << SCU_SFSPC_2_ZIF_Pos) /*!< SCU SFSPC_2: ZIF Mask */ /* --------------------------------- SCU_SFSPC_3 -------------------------------- */ #define SCU_SFSPC_3_MODE_Pos 0 /*!< SCU SFSPC_3: MODE Position */ #define SCU_SFSPC_3_MODE_Msk (0x07UL << SCU_SFSPC_3_MODE_Pos) /*!< SCU SFSPC_3: MODE Mask */ #define SCU_SFSPC_3_EPD_Pos 3 /*!< SCU SFSPC_3: EPD Position */ #define SCU_SFSPC_3_EPD_Msk (0x01UL << SCU_SFSPC_3_EPD_Pos) /*!< SCU SFSPC_3: EPD Mask */ #define SCU_SFSPC_3_EPUN_Pos 4 /*!< SCU SFSPC_3: EPUN Position */ #define SCU_SFSPC_3_EPUN_Msk (0x01UL << SCU_SFSPC_3_EPUN_Pos) /*!< SCU SFSPC_3: EPUN Mask */ #define SCU_SFSPC_3_EHS_Pos 5 /*!< SCU SFSPC_3: EHS Position */ #define SCU_SFSPC_3_EHS_Msk (0x01UL << SCU_SFSPC_3_EHS_Pos) /*!< SCU SFSPC_3: EHS Mask */ #define SCU_SFSPC_3_EZI_Pos 6 /*!< SCU SFSPC_3: EZI Position */ #define SCU_SFSPC_3_EZI_Msk (0x01UL << SCU_SFSPC_3_EZI_Pos) /*!< SCU SFSPC_3: EZI Mask */ #define SCU_SFSPC_3_ZIF_Pos 7 /*!< SCU SFSPC_3: ZIF Position */ #define SCU_SFSPC_3_ZIF_Msk (0x01UL << SCU_SFSPC_3_ZIF_Pos) /*!< SCU SFSPC_3: ZIF Mask */ /* --------------------------------- SCU_SFSPC_4 -------------------------------- */ #define SCU_SFSPC_4_MODE_Pos 0 /*!< SCU SFSPC_4: MODE Position */ #define SCU_SFSPC_4_MODE_Msk (0x07UL << SCU_SFSPC_4_MODE_Pos) /*!< SCU SFSPC_4: MODE Mask */ #define SCU_SFSPC_4_EPD_Pos 3 /*!< SCU SFSPC_4: EPD Position */ #define SCU_SFSPC_4_EPD_Msk (0x01UL << SCU_SFSPC_4_EPD_Pos) /*!< SCU SFSPC_4: EPD Mask */ #define SCU_SFSPC_4_EPUN_Pos 4 /*!< SCU SFSPC_4: EPUN Position */ #define SCU_SFSPC_4_EPUN_Msk (0x01UL << SCU_SFSPC_4_EPUN_Pos) /*!< SCU SFSPC_4: EPUN Mask */ #define SCU_SFSPC_4_EHS_Pos 5 /*!< SCU SFSPC_4: EHS Position */ #define SCU_SFSPC_4_EHS_Msk (0x01UL << SCU_SFSPC_4_EHS_Pos) /*!< SCU SFSPC_4: EHS Mask */ #define SCU_SFSPC_4_EZI_Pos 6 /*!< SCU SFSPC_4: EZI Position */ #define SCU_SFSPC_4_EZI_Msk (0x01UL << SCU_SFSPC_4_EZI_Pos) /*!< SCU SFSPC_4: EZI Mask */ #define SCU_SFSPC_4_ZIF_Pos 7 /*!< SCU SFSPC_4: ZIF Position */ #define SCU_SFSPC_4_ZIF_Msk (0x01UL << SCU_SFSPC_4_ZIF_Pos) /*!< SCU SFSPC_4: ZIF Mask */ /* --------------------------------- SCU_SFSPC_5 -------------------------------- */ #define SCU_SFSPC_5_MODE_Pos 0 /*!< SCU SFSPC_5: MODE Position */ #define SCU_SFSPC_5_MODE_Msk (0x07UL << SCU_SFSPC_5_MODE_Pos) /*!< SCU SFSPC_5: MODE Mask */ #define SCU_SFSPC_5_EPD_Pos 3 /*!< SCU SFSPC_5: EPD Position */ #define SCU_SFSPC_5_EPD_Msk (0x01UL << SCU_SFSPC_5_EPD_Pos) /*!< SCU SFSPC_5: EPD Mask */ #define SCU_SFSPC_5_EPUN_Pos 4 /*!< SCU SFSPC_5: EPUN Position */ #define SCU_SFSPC_5_EPUN_Msk (0x01UL << SCU_SFSPC_5_EPUN_Pos) /*!< SCU SFSPC_5: EPUN Mask */ #define SCU_SFSPC_5_EHS_Pos 5 /*!< SCU SFSPC_5: EHS Position */ #define SCU_SFSPC_5_EHS_Msk (0x01UL << SCU_SFSPC_5_EHS_Pos) /*!< SCU SFSPC_5: EHS Mask */ #define SCU_SFSPC_5_EZI_Pos 6 /*!< SCU SFSPC_5: EZI Position */ #define SCU_SFSPC_5_EZI_Msk (0x01UL << SCU_SFSPC_5_EZI_Pos) /*!< SCU SFSPC_5: EZI Mask */ #define SCU_SFSPC_5_ZIF_Pos 7 /*!< SCU SFSPC_5: ZIF Position */ #define SCU_SFSPC_5_ZIF_Msk (0x01UL << SCU_SFSPC_5_ZIF_Pos) /*!< SCU SFSPC_5: ZIF Mask */ /* --------------------------------- SCU_SFSPC_6 -------------------------------- */ #define SCU_SFSPC_6_MODE_Pos 0 /*!< SCU SFSPC_6: MODE Position */ #define SCU_SFSPC_6_MODE_Msk (0x07UL << SCU_SFSPC_6_MODE_Pos) /*!< SCU SFSPC_6: MODE Mask */ #define SCU_SFSPC_6_EPD_Pos 3 /*!< SCU SFSPC_6: EPD Position */ #define SCU_SFSPC_6_EPD_Msk (0x01UL << SCU_SFSPC_6_EPD_Pos) /*!< SCU SFSPC_6: EPD Mask */ #define SCU_SFSPC_6_EPUN_Pos 4 /*!< SCU SFSPC_6: EPUN Position */ #define SCU_SFSPC_6_EPUN_Msk (0x01UL << SCU_SFSPC_6_EPUN_Pos) /*!< SCU SFSPC_6: EPUN Mask */ #define SCU_SFSPC_6_EHS_Pos 5 /*!< SCU SFSPC_6: EHS Position */ #define SCU_SFSPC_6_EHS_Msk (0x01UL << SCU_SFSPC_6_EHS_Pos) /*!< SCU SFSPC_6: EHS Mask */ #define SCU_SFSPC_6_EZI_Pos 6 /*!< SCU SFSPC_6: EZI Position */ #define SCU_SFSPC_6_EZI_Msk (0x01UL << SCU_SFSPC_6_EZI_Pos) /*!< SCU SFSPC_6: EZI Mask */ #define SCU_SFSPC_6_ZIF_Pos 7 /*!< SCU SFSPC_6: ZIF Position */ #define SCU_SFSPC_6_ZIF_Msk (0x01UL << SCU_SFSPC_6_ZIF_Pos) /*!< SCU SFSPC_6: ZIF Mask */ /* --------------------------------- SCU_SFSPC_7 -------------------------------- */ #define SCU_SFSPC_7_MODE_Pos 0 /*!< SCU SFSPC_7: MODE Position */ #define SCU_SFSPC_7_MODE_Msk (0x07UL << SCU_SFSPC_7_MODE_Pos) /*!< SCU SFSPC_7: MODE Mask */ #define SCU_SFSPC_7_EPD_Pos 3 /*!< SCU SFSPC_7: EPD Position */ #define SCU_SFSPC_7_EPD_Msk (0x01UL << SCU_SFSPC_7_EPD_Pos) /*!< SCU SFSPC_7: EPD Mask */ #define SCU_SFSPC_7_EPUN_Pos 4 /*!< SCU SFSPC_7: EPUN Position */ #define SCU_SFSPC_7_EPUN_Msk (0x01UL << SCU_SFSPC_7_EPUN_Pos) /*!< SCU SFSPC_7: EPUN Mask */ #define SCU_SFSPC_7_EHS_Pos 5 /*!< SCU SFSPC_7: EHS Position */ #define SCU_SFSPC_7_EHS_Msk (0x01UL << SCU_SFSPC_7_EHS_Pos) /*!< SCU SFSPC_7: EHS Mask */ #define SCU_SFSPC_7_EZI_Pos 6 /*!< SCU SFSPC_7: EZI Position */ #define SCU_SFSPC_7_EZI_Msk (0x01UL << SCU_SFSPC_7_EZI_Pos) /*!< SCU SFSPC_7: EZI Mask */ #define SCU_SFSPC_7_ZIF_Pos 7 /*!< SCU SFSPC_7: ZIF Position */ #define SCU_SFSPC_7_ZIF_Msk (0x01UL << SCU_SFSPC_7_ZIF_Pos) /*!< SCU SFSPC_7: ZIF Mask */ /* --------------------------------- SCU_SFSPC_8 -------------------------------- */ #define SCU_SFSPC_8_MODE_Pos 0 /*!< SCU SFSPC_8: MODE Position */ #define SCU_SFSPC_8_MODE_Msk (0x07UL << SCU_SFSPC_8_MODE_Pos) /*!< SCU SFSPC_8: MODE Mask */ #define SCU_SFSPC_8_EPD_Pos 3 /*!< SCU SFSPC_8: EPD Position */ #define SCU_SFSPC_8_EPD_Msk (0x01UL << SCU_SFSPC_8_EPD_Pos) /*!< SCU SFSPC_8: EPD Mask */ #define SCU_SFSPC_8_EPUN_Pos 4 /*!< SCU SFSPC_8: EPUN Position */ #define SCU_SFSPC_8_EPUN_Msk (0x01UL << SCU_SFSPC_8_EPUN_Pos) /*!< SCU SFSPC_8: EPUN Mask */ #define SCU_SFSPC_8_EHS_Pos 5 /*!< SCU SFSPC_8: EHS Position */ #define SCU_SFSPC_8_EHS_Msk (0x01UL << SCU_SFSPC_8_EHS_Pos) /*!< SCU SFSPC_8: EHS Mask */ #define SCU_SFSPC_8_EZI_Pos 6 /*!< SCU SFSPC_8: EZI Position */ #define SCU_SFSPC_8_EZI_Msk (0x01UL << SCU_SFSPC_8_EZI_Pos) /*!< SCU SFSPC_8: EZI Mask */ #define SCU_SFSPC_8_ZIF_Pos 7 /*!< SCU SFSPC_8: ZIF Position */ #define SCU_SFSPC_8_ZIF_Msk (0x01UL << SCU_SFSPC_8_ZIF_Pos) /*!< SCU SFSPC_8: ZIF Mask */ /* --------------------------------- SCU_SFSPC_9 -------------------------------- */ #define SCU_SFSPC_9_MODE_Pos 0 /*!< SCU SFSPC_9: MODE Position */ #define SCU_SFSPC_9_MODE_Msk (0x07UL << SCU_SFSPC_9_MODE_Pos) /*!< SCU SFSPC_9: MODE Mask */ #define SCU_SFSPC_9_EPD_Pos 3 /*!< SCU SFSPC_9: EPD Position */ #define SCU_SFSPC_9_EPD_Msk (0x01UL << SCU_SFSPC_9_EPD_Pos) /*!< SCU SFSPC_9: EPD Mask */ #define SCU_SFSPC_9_EPUN_Pos 4 /*!< SCU SFSPC_9: EPUN Position */ #define SCU_SFSPC_9_EPUN_Msk (0x01UL << SCU_SFSPC_9_EPUN_Pos) /*!< SCU SFSPC_9: EPUN Mask */ #define SCU_SFSPC_9_EHS_Pos 5 /*!< SCU SFSPC_9: EHS Position */ #define SCU_SFSPC_9_EHS_Msk (0x01UL << SCU_SFSPC_9_EHS_Pos) /*!< SCU SFSPC_9: EHS Mask */ #define SCU_SFSPC_9_EZI_Pos 6 /*!< SCU SFSPC_9: EZI Position */ #define SCU_SFSPC_9_EZI_Msk (0x01UL << SCU_SFSPC_9_EZI_Pos) /*!< SCU SFSPC_9: EZI Mask */ #define SCU_SFSPC_9_ZIF_Pos 7 /*!< SCU SFSPC_9: ZIF Position */ #define SCU_SFSPC_9_ZIF_Msk (0x01UL << SCU_SFSPC_9_ZIF_Pos) /*!< SCU SFSPC_9: ZIF Mask */ /* -------------------------------- SCU_SFSPC_10 -------------------------------- */ #define SCU_SFSPC_10_MODE_Pos 0 /*!< SCU SFSPC_10: MODE Position */ #define SCU_SFSPC_10_MODE_Msk (0x07UL << SCU_SFSPC_10_MODE_Pos) /*!< SCU SFSPC_10: MODE Mask */ #define SCU_SFSPC_10_EPD_Pos 3 /*!< SCU SFSPC_10: EPD Position */ #define SCU_SFSPC_10_EPD_Msk (0x01UL << SCU_SFSPC_10_EPD_Pos) /*!< SCU SFSPC_10: EPD Mask */ #define SCU_SFSPC_10_EPUN_Pos 4 /*!< SCU SFSPC_10: EPUN Position */ #define SCU_SFSPC_10_EPUN_Msk (0x01UL << SCU_SFSPC_10_EPUN_Pos) /*!< SCU SFSPC_10: EPUN Mask */ #define SCU_SFSPC_10_EHS_Pos 5 /*!< SCU SFSPC_10: EHS Position */ #define SCU_SFSPC_10_EHS_Msk (0x01UL << SCU_SFSPC_10_EHS_Pos) /*!< SCU SFSPC_10: EHS Mask */ #define SCU_SFSPC_10_EZI_Pos 6 /*!< SCU SFSPC_10: EZI Position */ #define SCU_SFSPC_10_EZI_Msk (0x01UL << SCU_SFSPC_10_EZI_Pos) /*!< SCU SFSPC_10: EZI Mask */ #define SCU_SFSPC_10_ZIF_Pos 7 /*!< SCU SFSPC_10: ZIF Position */ #define SCU_SFSPC_10_ZIF_Msk (0x01UL << SCU_SFSPC_10_ZIF_Pos) /*!< SCU SFSPC_10: ZIF Mask */ /* -------------------------------- SCU_SFSPC_11 -------------------------------- */ #define SCU_SFSPC_11_MODE_Pos 0 /*!< SCU SFSPC_11: MODE Position */ #define SCU_SFSPC_11_MODE_Msk (0x07UL << SCU_SFSPC_11_MODE_Pos) /*!< SCU SFSPC_11: MODE Mask */ #define SCU_SFSPC_11_EPD_Pos 3 /*!< SCU SFSPC_11: EPD Position */ #define SCU_SFSPC_11_EPD_Msk (0x01UL << SCU_SFSPC_11_EPD_Pos) /*!< SCU SFSPC_11: EPD Mask */ #define SCU_SFSPC_11_EPUN_Pos 4 /*!< SCU SFSPC_11: EPUN Position */ #define SCU_SFSPC_11_EPUN_Msk (0x01UL << SCU_SFSPC_11_EPUN_Pos) /*!< SCU SFSPC_11: EPUN Mask */ #define SCU_SFSPC_11_EHS_Pos 5 /*!< SCU SFSPC_11: EHS Position */ #define SCU_SFSPC_11_EHS_Msk (0x01UL << SCU_SFSPC_11_EHS_Pos) /*!< SCU SFSPC_11: EHS Mask */ #define SCU_SFSPC_11_EZI_Pos 6 /*!< SCU SFSPC_11: EZI Position */ #define SCU_SFSPC_11_EZI_Msk (0x01UL << SCU_SFSPC_11_EZI_Pos) /*!< SCU SFSPC_11: EZI Mask */ #define SCU_SFSPC_11_ZIF_Pos 7 /*!< SCU SFSPC_11: ZIF Position */ #define SCU_SFSPC_11_ZIF_Msk (0x01UL << SCU_SFSPC_11_ZIF_Pos) /*!< SCU SFSPC_11: ZIF Mask */ /* -------------------------------- SCU_SFSPC_12 -------------------------------- */ #define SCU_SFSPC_12_MODE_Pos 0 /*!< SCU SFSPC_12: MODE Position */ #define SCU_SFSPC_12_MODE_Msk (0x07UL << SCU_SFSPC_12_MODE_Pos) /*!< SCU SFSPC_12: MODE Mask */ #define SCU_SFSPC_12_EPD_Pos 3 /*!< SCU SFSPC_12: EPD Position */ #define SCU_SFSPC_12_EPD_Msk (0x01UL << SCU_SFSPC_12_EPD_Pos) /*!< SCU SFSPC_12: EPD Mask */ #define SCU_SFSPC_12_EPUN_Pos 4 /*!< SCU SFSPC_12: EPUN Position */ #define SCU_SFSPC_12_EPUN_Msk (0x01UL << SCU_SFSPC_12_EPUN_Pos) /*!< SCU SFSPC_12: EPUN Mask */ #define SCU_SFSPC_12_EHS_Pos 5 /*!< SCU SFSPC_12: EHS Position */ #define SCU_SFSPC_12_EHS_Msk (0x01UL << SCU_SFSPC_12_EHS_Pos) /*!< SCU SFSPC_12: EHS Mask */ #define SCU_SFSPC_12_EZI_Pos 6 /*!< SCU SFSPC_12: EZI Position */ #define SCU_SFSPC_12_EZI_Msk (0x01UL << SCU_SFSPC_12_EZI_Pos) /*!< SCU SFSPC_12: EZI Mask */ #define SCU_SFSPC_12_ZIF_Pos 7 /*!< SCU SFSPC_12: ZIF Position */ #define SCU_SFSPC_12_ZIF_Msk (0x01UL << SCU_SFSPC_12_ZIF_Pos) /*!< SCU SFSPC_12: ZIF Mask */ /* -------------------------------- SCU_SFSPC_13 -------------------------------- */ #define SCU_SFSPC_13_MODE_Pos 0 /*!< SCU SFSPC_13: MODE Position */ #define SCU_SFSPC_13_MODE_Msk (0x07UL << SCU_SFSPC_13_MODE_Pos) /*!< SCU SFSPC_13: MODE Mask */ #define SCU_SFSPC_13_EPD_Pos 3 /*!< SCU SFSPC_13: EPD Position */ #define SCU_SFSPC_13_EPD_Msk (0x01UL << SCU_SFSPC_13_EPD_Pos) /*!< SCU SFSPC_13: EPD Mask */ #define SCU_SFSPC_13_EPUN_Pos 4 /*!< SCU SFSPC_13: EPUN Position */ #define SCU_SFSPC_13_EPUN_Msk (0x01UL << SCU_SFSPC_13_EPUN_Pos) /*!< SCU SFSPC_13: EPUN Mask */ #define SCU_SFSPC_13_EHS_Pos 5 /*!< SCU SFSPC_13: EHS Position */ #define SCU_SFSPC_13_EHS_Msk (0x01UL << SCU_SFSPC_13_EHS_Pos) /*!< SCU SFSPC_13: EHS Mask */ #define SCU_SFSPC_13_EZI_Pos 6 /*!< SCU SFSPC_13: EZI Position */ #define SCU_SFSPC_13_EZI_Msk (0x01UL << SCU_SFSPC_13_EZI_Pos) /*!< SCU SFSPC_13: EZI Mask */ #define SCU_SFSPC_13_ZIF_Pos 7 /*!< SCU SFSPC_13: ZIF Position */ #define SCU_SFSPC_13_ZIF_Msk (0x01UL << SCU_SFSPC_13_ZIF_Pos) /*!< SCU SFSPC_13: ZIF Mask */ /* -------------------------------- SCU_SFSPC_14 -------------------------------- */ #define SCU_SFSPC_14_MODE_Pos 0 /*!< SCU SFSPC_14: MODE Position */ #define SCU_SFSPC_14_MODE_Msk (0x07UL << SCU_SFSPC_14_MODE_Pos) /*!< SCU SFSPC_14: MODE Mask */ #define SCU_SFSPC_14_EPD_Pos 3 /*!< SCU SFSPC_14: EPD Position */ #define SCU_SFSPC_14_EPD_Msk (0x01UL << SCU_SFSPC_14_EPD_Pos) /*!< SCU SFSPC_14: EPD Mask */ #define SCU_SFSPC_14_EPUN_Pos 4 /*!< SCU SFSPC_14: EPUN Position */ #define SCU_SFSPC_14_EPUN_Msk (0x01UL << SCU_SFSPC_14_EPUN_Pos) /*!< SCU SFSPC_14: EPUN Mask */ #define SCU_SFSPC_14_EHS_Pos 5 /*!< SCU SFSPC_14: EHS Position */ #define SCU_SFSPC_14_EHS_Msk (0x01UL << SCU_SFSPC_14_EHS_Pos) /*!< SCU SFSPC_14: EHS Mask */ #define SCU_SFSPC_14_EZI_Pos 6 /*!< SCU SFSPC_14: EZI Position */ #define SCU_SFSPC_14_EZI_Msk (0x01UL << SCU_SFSPC_14_EZI_Pos) /*!< SCU SFSPC_14: EZI Mask */ #define SCU_SFSPC_14_ZIF_Pos 7 /*!< SCU SFSPC_14: ZIF Position */ #define SCU_SFSPC_14_ZIF_Msk (0x01UL << SCU_SFSPC_14_ZIF_Pos) /*!< SCU SFSPC_14: ZIF Mask */ /* --------------------------------- SCU_SFSPD_0 -------------------------------- */ #define SCU_SFSPD_0_MODE_Pos 0 /*!< SCU SFSPD_0: MODE Position */ #define SCU_SFSPD_0_MODE_Msk (0x07UL << SCU_SFSPD_0_MODE_Pos) /*!< SCU SFSPD_0: MODE Mask */ #define SCU_SFSPD_0_EPD_Pos 3 /*!< SCU SFSPD_0: EPD Position */ #define SCU_SFSPD_0_EPD_Msk (0x01UL << SCU_SFSPD_0_EPD_Pos) /*!< SCU SFSPD_0: EPD Mask */ #define SCU_SFSPD_0_EPUN_Pos 4 /*!< SCU SFSPD_0: EPUN Position */ #define SCU_SFSPD_0_EPUN_Msk (0x01UL << SCU_SFSPD_0_EPUN_Pos) /*!< SCU SFSPD_0: EPUN Mask */ #define SCU_SFSPD_0_EHS_Pos 5 /*!< SCU SFSPD_0: EHS Position */ #define SCU_SFSPD_0_EHS_Msk (0x01UL << SCU_SFSPD_0_EHS_Pos) /*!< SCU SFSPD_0: EHS Mask */ #define SCU_SFSPD_0_EZI_Pos 6 /*!< SCU SFSPD_0: EZI Position */ #define SCU_SFSPD_0_EZI_Msk (0x01UL << SCU_SFSPD_0_EZI_Pos) /*!< SCU SFSPD_0: EZI Mask */ #define SCU_SFSPD_0_ZIF_Pos 7 /*!< SCU SFSPD_0: ZIF Position */ #define SCU_SFSPD_0_ZIF_Msk (0x01UL << SCU_SFSPD_0_ZIF_Pos) /*!< SCU SFSPD_0: ZIF Mask */ /* --------------------------------- SCU_SFSPD_1 -------------------------------- */ #define SCU_SFSPD_1_MODE_Pos 0 /*!< SCU SFSPD_1: MODE Position */ #define SCU_SFSPD_1_MODE_Msk (0x07UL << SCU_SFSPD_1_MODE_Pos) /*!< SCU SFSPD_1: MODE Mask */ #define SCU_SFSPD_1_EPD_Pos 3 /*!< SCU SFSPD_1: EPD Position */ #define SCU_SFSPD_1_EPD_Msk (0x01UL << SCU_SFSPD_1_EPD_Pos) /*!< SCU SFSPD_1: EPD Mask */ #define SCU_SFSPD_1_EPUN_Pos 4 /*!< SCU SFSPD_1: EPUN Position */ #define SCU_SFSPD_1_EPUN_Msk (0x01UL << SCU_SFSPD_1_EPUN_Pos) /*!< SCU SFSPD_1: EPUN Mask */ #define SCU_SFSPD_1_EHS_Pos 5 /*!< SCU SFSPD_1: EHS Position */ #define SCU_SFSPD_1_EHS_Msk (0x01UL << SCU_SFSPD_1_EHS_Pos) /*!< SCU SFSPD_1: EHS Mask */ #define SCU_SFSPD_1_EZI_Pos 6 /*!< SCU SFSPD_1: EZI Position */ #define SCU_SFSPD_1_EZI_Msk (0x01UL << SCU_SFSPD_1_EZI_Pos) /*!< SCU SFSPD_1: EZI Mask */ #define SCU_SFSPD_1_ZIF_Pos 7 /*!< SCU SFSPD_1: ZIF Position */ #define SCU_SFSPD_1_ZIF_Msk (0x01UL << SCU_SFSPD_1_ZIF_Pos) /*!< SCU SFSPD_1: ZIF Mask */ /* --------------------------------- SCU_SFSPD_2 -------------------------------- */ #define SCU_SFSPD_2_MODE_Pos 0 /*!< SCU SFSPD_2: MODE Position */ #define SCU_SFSPD_2_MODE_Msk (0x07UL << SCU_SFSPD_2_MODE_Pos) /*!< SCU SFSPD_2: MODE Mask */ #define SCU_SFSPD_2_EPD_Pos 3 /*!< SCU SFSPD_2: EPD Position */ #define SCU_SFSPD_2_EPD_Msk (0x01UL << SCU_SFSPD_2_EPD_Pos) /*!< SCU SFSPD_2: EPD Mask */ #define SCU_SFSPD_2_EPUN_Pos 4 /*!< SCU SFSPD_2: EPUN Position */ #define SCU_SFSPD_2_EPUN_Msk (0x01UL << SCU_SFSPD_2_EPUN_Pos) /*!< SCU SFSPD_2: EPUN Mask */ #define SCU_SFSPD_2_EHS_Pos 5 /*!< SCU SFSPD_2: EHS Position */ #define SCU_SFSPD_2_EHS_Msk (0x01UL << SCU_SFSPD_2_EHS_Pos) /*!< SCU SFSPD_2: EHS Mask */ #define SCU_SFSPD_2_EZI_Pos 6 /*!< SCU SFSPD_2: EZI Position */ #define SCU_SFSPD_2_EZI_Msk (0x01UL << SCU_SFSPD_2_EZI_Pos) /*!< SCU SFSPD_2: EZI Mask */ #define SCU_SFSPD_2_ZIF_Pos 7 /*!< SCU SFSPD_2: ZIF Position */ #define SCU_SFSPD_2_ZIF_Msk (0x01UL << SCU_SFSPD_2_ZIF_Pos) /*!< SCU SFSPD_2: ZIF Mask */ /* --------------------------------- SCU_SFSPD_3 -------------------------------- */ #define SCU_SFSPD_3_MODE_Pos 0 /*!< SCU SFSPD_3: MODE Position */ #define SCU_SFSPD_3_MODE_Msk (0x07UL << SCU_SFSPD_3_MODE_Pos) /*!< SCU SFSPD_3: MODE Mask */ #define SCU_SFSPD_3_EPD_Pos 3 /*!< SCU SFSPD_3: EPD Position */ #define SCU_SFSPD_3_EPD_Msk (0x01UL << SCU_SFSPD_3_EPD_Pos) /*!< SCU SFSPD_3: EPD Mask */ #define SCU_SFSPD_3_EPUN_Pos 4 /*!< SCU SFSPD_3: EPUN Position */ #define SCU_SFSPD_3_EPUN_Msk (0x01UL << SCU_SFSPD_3_EPUN_Pos) /*!< SCU SFSPD_3: EPUN Mask */ #define SCU_SFSPD_3_EHS_Pos 5 /*!< SCU SFSPD_3: EHS Position */ #define SCU_SFSPD_3_EHS_Msk (0x01UL << SCU_SFSPD_3_EHS_Pos) /*!< SCU SFSPD_3: EHS Mask */ #define SCU_SFSPD_3_EZI_Pos 6 /*!< SCU SFSPD_3: EZI Position */ #define SCU_SFSPD_3_EZI_Msk (0x01UL << SCU_SFSPD_3_EZI_Pos) /*!< SCU SFSPD_3: EZI Mask */ #define SCU_SFSPD_3_ZIF_Pos 7 /*!< SCU SFSPD_3: ZIF Position */ #define SCU_SFSPD_3_ZIF_Msk (0x01UL << SCU_SFSPD_3_ZIF_Pos) /*!< SCU SFSPD_3: ZIF Mask */ /* --------------------------------- SCU_SFSPD_4 -------------------------------- */ #define SCU_SFSPD_4_MODE_Pos 0 /*!< SCU SFSPD_4: MODE Position */ #define SCU_SFSPD_4_MODE_Msk (0x07UL << SCU_SFSPD_4_MODE_Pos) /*!< SCU SFSPD_4: MODE Mask */ #define SCU_SFSPD_4_EPD_Pos 3 /*!< SCU SFSPD_4: EPD Position */ #define SCU_SFSPD_4_EPD_Msk (0x01UL << SCU_SFSPD_4_EPD_Pos) /*!< SCU SFSPD_4: EPD Mask */ #define SCU_SFSPD_4_EPUN_Pos 4 /*!< SCU SFSPD_4: EPUN Position */ #define SCU_SFSPD_4_EPUN_Msk (0x01UL << SCU_SFSPD_4_EPUN_Pos) /*!< SCU SFSPD_4: EPUN Mask */ #define SCU_SFSPD_4_EHS_Pos 5 /*!< SCU SFSPD_4: EHS Position */ #define SCU_SFSPD_4_EHS_Msk (0x01UL << SCU_SFSPD_4_EHS_Pos) /*!< SCU SFSPD_4: EHS Mask */ #define SCU_SFSPD_4_EZI_Pos 6 /*!< SCU SFSPD_4: EZI Position */ #define SCU_SFSPD_4_EZI_Msk (0x01UL << SCU_SFSPD_4_EZI_Pos) /*!< SCU SFSPD_4: EZI Mask */ #define SCU_SFSPD_4_ZIF_Pos 7 /*!< SCU SFSPD_4: ZIF Position */ #define SCU_SFSPD_4_ZIF_Msk (0x01UL << SCU_SFSPD_4_ZIF_Pos) /*!< SCU SFSPD_4: ZIF Mask */ /* --------------------------------- SCU_SFSPD_5 -------------------------------- */ #define SCU_SFSPD_5_MODE_Pos 0 /*!< SCU SFSPD_5: MODE Position */ #define SCU_SFSPD_5_MODE_Msk (0x07UL << SCU_SFSPD_5_MODE_Pos) /*!< SCU SFSPD_5: MODE Mask */ #define SCU_SFSPD_5_EPD_Pos 3 /*!< SCU SFSPD_5: EPD Position */ #define SCU_SFSPD_5_EPD_Msk (0x01UL << SCU_SFSPD_5_EPD_Pos) /*!< SCU SFSPD_5: EPD Mask */ #define SCU_SFSPD_5_EPUN_Pos 4 /*!< SCU SFSPD_5: EPUN Position */ #define SCU_SFSPD_5_EPUN_Msk (0x01UL << SCU_SFSPD_5_EPUN_Pos) /*!< SCU SFSPD_5: EPUN Mask */ #define SCU_SFSPD_5_EHS_Pos 5 /*!< SCU SFSPD_5: EHS Position */ #define SCU_SFSPD_5_EHS_Msk (0x01UL << SCU_SFSPD_5_EHS_Pos) /*!< SCU SFSPD_5: EHS Mask */ #define SCU_SFSPD_5_EZI_Pos 6 /*!< SCU SFSPD_5: EZI Position */ #define SCU_SFSPD_5_EZI_Msk (0x01UL << SCU_SFSPD_5_EZI_Pos) /*!< SCU SFSPD_5: EZI Mask */ #define SCU_SFSPD_5_ZIF_Pos 7 /*!< SCU SFSPD_5: ZIF Position */ #define SCU_SFSPD_5_ZIF_Msk (0x01UL << SCU_SFSPD_5_ZIF_Pos) /*!< SCU SFSPD_5: ZIF Mask */ /* --------------------------------- SCU_SFSPD_6 -------------------------------- */ #define SCU_SFSPD_6_MODE_Pos 0 /*!< SCU SFSPD_6: MODE Position */ #define SCU_SFSPD_6_MODE_Msk (0x07UL << SCU_SFSPD_6_MODE_Pos) /*!< SCU SFSPD_6: MODE Mask */ #define SCU_SFSPD_6_EPD_Pos 3 /*!< SCU SFSPD_6: EPD Position */ #define SCU_SFSPD_6_EPD_Msk (0x01UL << SCU_SFSPD_6_EPD_Pos) /*!< SCU SFSPD_6: EPD Mask */ #define SCU_SFSPD_6_EPUN_Pos 4 /*!< SCU SFSPD_6: EPUN Position */ #define SCU_SFSPD_6_EPUN_Msk (0x01UL << SCU_SFSPD_6_EPUN_Pos) /*!< SCU SFSPD_6: EPUN Mask */ #define SCU_SFSPD_6_EHS_Pos 5 /*!< SCU SFSPD_6: EHS Position */ #define SCU_SFSPD_6_EHS_Msk (0x01UL << SCU_SFSPD_6_EHS_Pos) /*!< SCU SFSPD_6: EHS Mask */ #define SCU_SFSPD_6_EZI_Pos 6 /*!< SCU SFSPD_6: EZI Position */ #define SCU_SFSPD_6_EZI_Msk (0x01UL << SCU_SFSPD_6_EZI_Pos) /*!< SCU SFSPD_6: EZI Mask */ #define SCU_SFSPD_6_ZIF_Pos 7 /*!< SCU SFSPD_6: ZIF Position */ #define SCU_SFSPD_6_ZIF_Msk (0x01UL << SCU_SFSPD_6_ZIF_Pos) /*!< SCU SFSPD_6: ZIF Mask */ /* --------------------------------- SCU_SFSPD_7 -------------------------------- */ #define SCU_SFSPD_7_MODE_Pos 0 /*!< SCU SFSPD_7: MODE Position */ #define SCU_SFSPD_7_MODE_Msk (0x07UL << SCU_SFSPD_7_MODE_Pos) /*!< SCU SFSPD_7: MODE Mask */ #define SCU_SFSPD_7_EPD_Pos 3 /*!< SCU SFSPD_7: EPD Position */ #define SCU_SFSPD_7_EPD_Msk (0x01UL << SCU_SFSPD_7_EPD_Pos) /*!< SCU SFSPD_7: EPD Mask */ #define SCU_SFSPD_7_EPUN_Pos 4 /*!< SCU SFSPD_7: EPUN Position */ #define SCU_SFSPD_7_EPUN_Msk (0x01UL << SCU_SFSPD_7_EPUN_Pos) /*!< SCU SFSPD_7: EPUN Mask */ #define SCU_SFSPD_7_EHS_Pos 5 /*!< SCU SFSPD_7: EHS Position */ #define SCU_SFSPD_7_EHS_Msk (0x01UL << SCU_SFSPD_7_EHS_Pos) /*!< SCU SFSPD_7: EHS Mask */ #define SCU_SFSPD_7_EZI_Pos 6 /*!< SCU SFSPD_7: EZI Position */ #define SCU_SFSPD_7_EZI_Msk (0x01UL << SCU_SFSPD_7_EZI_Pos) /*!< SCU SFSPD_7: EZI Mask */ #define SCU_SFSPD_7_ZIF_Pos 7 /*!< SCU SFSPD_7: ZIF Position */ #define SCU_SFSPD_7_ZIF_Msk (0x01UL << SCU_SFSPD_7_ZIF_Pos) /*!< SCU SFSPD_7: ZIF Mask */ /* --------------------------------- SCU_SFSPD_8 -------------------------------- */ #define SCU_SFSPD_8_MODE_Pos 0 /*!< SCU SFSPD_8: MODE Position */ #define SCU_SFSPD_8_MODE_Msk (0x07UL << SCU_SFSPD_8_MODE_Pos) /*!< SCU SFSPD_8: MODE Mask */ #define SCU_SFSPD_8_EPD_Pos 3 /*!< SCU SFSPD_8: EPD Position */ #define SCU_SFSPD_8_EPD_Msk (0x01UL << SCU_SFSPD_8_EPD_Pos) /*!< SCU SFSPD_8: EPD Mask */ #define SCU_SFSPD_8_EPUN_Pos 4 /*!< SCU SFSPD_8: EPUN Position */ #define SCU_SFSPD_8_EPUN_Msk (0x01UL << SCU_SFSPD_8_EPUN_Pos) /*!< SCU SFSPD_8: EPUN Mask */ #define SCU_SFSPD_8_EHS_Pos 5 /*!< SCU SFSPD_8: EHS Position */ #define SCU_SFSPD_8_EHS_Msk (0x01UL << SCU_SFSPD_8_EHS_Pos) /*!< SCU SFSPD_8: EHS Mask */ #define SCU_SFSPD_8_EZI_Pos 6 /*!< SCU SFSPD_8: EZI Position */ #define SCU_SFSPD_8_EZI_Msk (0x01UL << SCU_SFSPD_8_EZI_Pos) /*!< SCU SFSPD_8: EZI Mask */ #define SCU_SFSPD_8_ZIF_Pos 7 /*!< SCU SFSPD_8: ZIF Position */ #define SCU_SFSPD_8_ZIF_Msk (0x01UL << SCU_SFSPD_8_ZIF_Pos) /*!< SCU SFSPD_8: ZIF Mask */ /* --------------------------------- SCU_SFSPD_9 -------------------------------- */ #define SCU_SFSPD_9_MODE_Pos 0 /*!< SCU SFSPD_9: MODE Position */ #define SCU_SFSPD_9_MODE_Msk (0x07UL << SCU_SFSPD_9_MODE_Pos) /*!< SCU SFSPD_9: MODE Mask */ #define SCU_SFSPD_9_EPD_Pos 3 /*!< SCU SFSPD_9: EPD Position */ #define SCU_SFSPD_9_EPD_Msk (0x01UL << SCU_SFSPD_9_EPD_Pos) /*!< SCU SFSPD_9: EPD Mask */ #define SCU_SFSPD_9_EPUN_Pos 4 /*!< SCU SFSPD_9: EPUN Position */ #define SCU_SFSPD_9_EPUN_Msk (0x01UL << SCU_SFSPD_9_EPUN_Pos) /*!< SCU SFSPD_9: EPUN Mask */ #define SCU_SFSPD_9_EHS_Pos 5 /*!< SCU SFSPD_9: EHS Position */ #define SCU_SFSPD_9_EHS_Msk (0x01UL << SCU_SFSPD_9_EHS_Pos) /*!< SCU SFSPD_9: EHS Mask */ #define SCU_SFSPD_9_EZI_Pos 6 /*!< SCU SFSPD_9: EZI Position */ #define SCU_SFSPD_9_EZI_Msk (0x01UL << SCU_SFSPD_9_EZI_Pos) /*!< SCU SFSPD_9: EZI Mask */ #define SCU_SFSPD_9_ZIF_Pos 7 /*!< SCU SFSPD_9: ZIF Position */ #define SCU_SFSPD_9_ZIF_Msk (0x01UL << SCU_SFSPD_9_ZIF_Pos) /*!< SCU SFSPD_9: ZIF Mask */ /* -------------------------------- SCU_SFSPD_10 -------------------------------- */ #define SCU_SFSPD_10_MODE_Pos 0 /*!< SCU SFSPD_10: MODE Position */ #define SCU_SFSPD_10_MODE_Msk (0x07UL << SCU_SFSPD_10_MODE_Pos) /*!< SCU SFSPD_10: MODE Mask */ #define SCU_SFSPD_10_EPD_Pos 3 /*!< SCU SFSPD_10: EPD Position */ #define SCU_SFSPD_10_EPD_Msk (0x01UL << SCU_SFSPD_10_EPD_Pos) /*!< SCU SFSPD_10: EPD Mask */ #define SCU_SFSPD_10_EPUN_Pos 4 /*!< SCU SFSPD_10: EPUN Position */ #define SCU_SFSPD_10_EPUN_Msk (0x01UL << SCU_SFSPD_10_EPUN_Pos) /*!< SCU SFSPD_10: EPUN Mask */ #define SCU_SFSPD_10_EHS_Pos 5 /*!< SCU SFSPD_10: EHS Position */ #define SCU_SFSPD_10_EHS_Msk (0x01UL << SCU_SFSPD_10_EHS_Pos) /*!< SCU SFSPD_10: EHS Mask */ #define SCU_SFSPD_10_EZI_Pos 6 /*!< SCU SFSPD_10: EZI Position */ #define SCU_SFSPD_10_EZI_Msk (0x01UL << SCU_SFSPD_10_EZI_Pos) /*!< SCU SFSPD_10: EZI Mask */ #define SCU_SFSPD_10_ZIF_Pos 7 /*!< SCU SFSPD_10: ZIF Position */ #define SCU_SFSPD_10_ZIF_Msk (0x01UL << SCU_SFSPD_10_ZIF_Pos) /*!< SCU SFSPD_10: ZIF Mask */ /* -------------------------------- SCU_SFSPD_11 -------------------------------- */ #define SCU_SFSPD_11_MODE_Pos 0 /*!< SCU SFSPD_11: MODE Position */ #define SCU_SFSPD_11_MODE_Msk (0x07UL << SCU_SFSPD_11_MODE_Pos) /*!< SCU SFSPD_11: MODE Mask */ #define SCU_SFSPD_11_EPD_Pos 3 /*!< SCU SFSPD_11: EPD Position */ #define SCU_SFSPD_11_EPD_Msk (0x01UL << SCU_SFSPD_11_EPD_Pos) /*!< SCU SFSPD_11: EPD Mask */ #define SCU_SFSPD_11_EPUN_Pos 4 /*!< SCU SFSPD_11: EPUN Position */ #define SCU_SFSPD_11_EPUN_Msk (0x01UL << SCU_SFSPD_11_EPUN_Pos) /*!< SCU SFSPD_11: EPUN Mask */ #define SCU_SFSPD_11_EHS_Pos 5 /*!< SCU SFSPD_11: EHS Position */ #define SCU_SFSPD_11_EHS_Msk (0x01UL << SCU_SFSPD_11_EHS_Pos) /*!< SCU SFSPD_11: EHS Mask */ #define SCU_SFSPD_11_EZI_Pos 6 /*!< SCU SFSPD_11: EZI Position */ #define SCU_SFSPD_11_EZI_Msk (0x01UL << SCU_SFSPD_11_EZI_Pos) /*!< SCU SFSPD_11: EZI Mask */ #define SCU_SFSPD_11_ZIF_Pos 7 /*!< SCU SFSPD_11: ZIF Position */ #define SCU_SFSPD_11_ZIF_Msk (0x01UL << SCU_SFSPD_11_ZIF_Pos) /*!< SCU SFSPD_11: ZIF Mask */ /* -------------------------------- SCU_SFSPD_12 -------------------------------- */ #define SCU_SFSPD_12_MODE_Pos 0 /*!< SCU SFSPD_12: MODE Position */ #define SCU_SFSPD_12_MODE_Msk (0x07UL << SCU_SFSPD_12_MODE_Pos) /*!< SCU SFSPD_12: MODE Mask */ #define SCU_SFSPD_12_EPD_Pos 3 /*!< SCU SFSPD_12: EPD Position */ #define SCU_SFSPD_12_EPD_Msk (0x01UL << SCU_SFSPD_12_EPD_Pos) /*!< SCU SFSPD_12: EPD Mask */ #define SCU_SFSPD_12_EPUN_Pos 4 /*!< SCU SFSPD_12: EPUN Position */ #define SCU_SFSPD_12_EPUN_Msk (0x01UL << SCU_SFSPD_12_EPUN_Pos) /*!< SCU SFSPD_12: EPUN Mask */ #define SCU_SFSPD_12_EHS_Pos 5 /*!< SCU SFSPD_12: EHS Position */ #define SCU_SFSPD_12_EHS_Msk (0x01UL << SCU_SFSPD_12_EHS_Pos) /*!< SCU SFSPD_12: EHS Mask */ #define SCU_SFSPD_12_EZI_Pos 6 /*!< SCU SFSPD_12: EZI Position */ #define SCU_SFSPD_12_EZI_Msk (0x01UL << SCU_SFSPD_12_EZI_Pos) /*!< SCU SFSPD_12: EZI Mask */ #define SCU_SFSPD_12_ZIF_Pos 7 /*!< SCU SFSPD_12: ZIF Position */ #define SCU_SFSPD_12_ZIF_Msk (0x01UL << SCU_SFSPD_12_ZIF_Pos) /*!< SCU SFSPD_12: ZIF Mask */ /* -------------------------------- SCU_SFSPD_13 -------------------------------- */ #define SCU_SFSPD_13_MODE_Pos 0 /*!< SCU SFSPD_13: MODE Position */ #define SCU_SFSPD_13_MODE_Msk (0x07UL << SCU_SFSPD_13_MODE_Pos) /*!< SCU SFSPD_13: MODE Mask */ #define SCU_SFSPD_13_EPD_Pos 3 /*!< SCU SFSPD_13: EPD Position */ #define SCU_SFSPD_13_EPD_Msk (0x01UL << SCU_SFSPD_13_EPD_Pos) /*!< SCU SFSPD_13: EPD Mask */ #define SCU_SFSPD_13_EPUN_Pos 4 /*!< SCU SFSPD_13: EPUN Position */ #define SCU_SFSPD_13_EPUN_Msk (0x01UL << SCU_SFSPD_13_EPUN_Pos) /*!< SCU SFSPD_13: EPUN Mask */ #define SCU_SFSPD_13_EHS_Pos 5 /*!< SCU SFSPD_13: EHS Position */ #define SCU_SFSPD_13_EHS_Msk (0x01UL << SCU_SFSPD_13_EHS_Pos) /*!< SCU SFSPD_13: EHS Mask */ #define SCU_SFSPD_13_EZI_Pos 6 /*!< SCU SFSPD_13: EZI Position */ #define SCU_SFSPD_13_EZI_Msk (0x01UL << SCU_SFSPD_13_EZI_Pos) /*!< SCU SFSPD_13: EZI Mask */ #define SCU_SFSPD_13_ZIF_Pos 7 /*!< SCU SFSPD_13: ZIF Position */ #define SCU_SFSPD_13_ZIF_Msk (0x01UL << SCU_SFSPD_13_ZIF_Pos) /*!< SCU SFSPD_13: ZIF Mask */ /* -------------------------------- SCU_SFSPD_14 -------------------------------- */ #define SCU_SFSPD_14_MODE_Pos 0 /*!< SCU SFSPD_14: MODE Position */ #define SCU_SFSPD_14_MODE_Msk (0x07UL << SCU_SFSPD_14_MODE_Pos) /*!< SCU SFSPD_14: MODE Mask */ #define SCU_SFSPD_14_EPD_Pos 3 /*!< SCU SFSPD_14: EPD Position */ #define SCU_SFSPD_14_EPD_Msk (0x01UL << SCU_SFSPD_14_EPD_Pos) /*!< SCU SFSPD_14: EPD Mask */ #define SCU_SFSPD_14_EPUN_Pos 4 /*!< SCU SFSPD_14: EPUN Position */ #define SCU_SFSPD_14_EPUN_Msk (0x01UL << SCU_SFSPD_14_EPUN_Pos) /*!< SCU SFSPD_14: EPUN Mask */ #define SCU_SFSPD_14_EHS_Pos 5 /*!< SCU SFSPD_14: EHS Position */ #define SCU_SFSPD_14_EHS_Msk (0x01UL << SCU_SFSPD_14_EHS_Pos) /*!< SCU SFSPD_14: EHS Mask */ #define SCU_SFSPD_14_EZI_Pos 6 /*!< SCU SFSPD_14: EZI Position */ #define SCU_SFSPD_14_EZI_Msk (0x01UL << SCU_SFSPD_14_EZI_Pos) /*!< SCU SFSPD_14: EZI Mask */ #define SCU_SFSPD_14_ZIF_Pos 7 /*!< SCU SFSPD_14: ZIF Position */ #define SCU_SFSPD_14_ZIF_Msk (0x01UL << SCU_SFSPD_14_ZIF_Pos) /*!< SCU SFSPD_14: ZIF Mask */ /* -------------------------------- SCU_SFSPD_15 -------------------------------- */ #define SCU_SFSPD_15_MODE_Pos 0 /*!< SCU SFSPD_15: MODE Position */ #define SCU_SFSPD_15_MODE_Msk (0x07UL << SCU_SFSPD_15_MODE_Pos) /*!< SCU SFSPD_15: MODE Mask */ #define SCU_SFSPD_15_EPD_Pos 3 /*!< SCU SFSPD_15: EPD Position */ #define SCU_SFSPD_15_EPD_Msk (0x01UL << SCU_SFSPD_15_EPD_Pos) /*!< SCU SFSPD_15: EPD Mask */ #define SCU_SFSPD_15_EPUN_Pos 4 /*!< SCU SFSPD_15: EPUN Position */ #define SCU_SFSPD_15_EPUN_Msk (0x01UL << SCU_SFSPD_15_EPUN_Pos) /*!< SCU SFSPD_15: EPUN Mask */ #define SCU_SFSPD_15_EHS_Pos 5 /*!< SCU SFSPD_15: EHS Position */ #define SCU_SFSPD_15_EHS_Msk (0x01UL << SCU_SFSPD_15_EHS_Pos) /*!< SCU SFSPD_15: EHS Mask */ #define SCU_SFSPD_15_EZI_Pos 6 /*!< SCU SFSPD_15: EZI Position */ #define SCU_SFSPD_15_EZI_Msk (0x01UL << SCU_SFSPD_15_EZI_Pos) /*!< SCU SFSPD_15: EZI Mask */ #define SCU_SFSPD_15_ZIF_Pos 7 /*!< SCU SFSPD_15: ZIF Position */ #define SCU_SFSPD_15_ZIF_Msk (0x01UL << SCU_SFSPD_15_ZIF_Pos) /*!< SCU SFSPD_15: ZIF Mask */ /* -------------------------------- SCU_SFSPD_16 -------------------------------- */ #define SCU_SFSPD_16_MODE_Pos 0 /*!< SCU SFSPD_16: MODE Position */ #define SCU_SFSPD_16_MODE_Msk (0x07UL << SCU_SFSPD_16_MODE_Pos) /*!< SCU SFSPD_16: MODE Mask */ #define SCU_SFSPD_16_EPD_Pos 3 /*!< SCU SFSPD_16: EPD Position */ #define SCU_SFSPD_16_EPD_Msk (0x01UL << SCU_SFSPD_16_EPD_Pos) /*!< SCU SFSPD_16: EPD Mask */ #define SCU_SFSPD_16_EPUN_Pos 4 /*!< SCU SFSPD_16: EPUN Position */ #define SCU_SFSPD_16_EPUN_Msk (0x01UL << SCU_SFSPD_16_EPUN_Pos) /*!< SCU SFSPD_16: EPUN Mask */ #define SCU_SFSPD_16_EHS_Pos 5 /*!< SCU SFSPD_16: EHS Position */ #define SCU_SFSPD_16_EHS_Msk (0x01UL << SCU_SFSPD_16_EHS_Pos) /*!< SCU SFSPD_16: EHS Mask */ #define SCU_SFSPD_16_EZI_Pos 6 /*!< SCU SFSPD_16: EZI Position */ #define SCU_SFSPD_16_EZI_Msk (0x01UL << SCU_SFSPD_16_EZI_Pos) /*!< SCU SFSPD_16: EZI Mask */ #define SCU_SFSPD_16_ZIF_Pos 7 /*!< SCU SFSPD_16: ZIF Position */ #define SCU_SFSPD_16_ZIF_Msk (0x01UL << SCU_SFSPD_16_ZIF_Pos) /*!< SCU SFSPD_16: ZIF Mask */ /* --------------------------------- SCU_SFSPE_0 -------------------------------- */ #define SCU_SFSPE_0_MODE_Pos 0 /*!< SCU SFSPE_0: MODE Position */ #define SCU_SFSPE_0_MODE_Msk (0x07UL << SCU_SFSPE_0_MODE_Pos) /*!< SCU SFSPE_0: MODE Mask */ #define SCU_SFSPE_0_EPD_Pos 3 /*!< SCU SFSPE_0: EPD Position */ #define SCU_SFSPE_0_EPD_Msk (0x01UL << SCU_SFSPE_0_EPD_Pos) /*!< SCU SFSPE_0: EPD Mask */ #define SCU_SFSPE_0_EPUN_Pos 4 /*!< SCU SFSPE_0: EPUN Position */ #define SCU_SFSPE_0_EPUN_Msk (0x01UL << SCU_SFSPE_0_EPUN_Pos) /*!< SCU SFSPE_0: EPUN Mask */ #define SCU_SFSPE_0_EHS_Pos 5 /*!< SCU SFSPE_0: EHS Position */ #define SCU_SFSPE_0_EHS_Msk (0x01UL << SCU_SFSPE_0_EHS_Pos) /*!< SCU SFSPE_0: EHS Mask */ #define SCU_SFSPE_0_EZI_Pos 6 /*!< SCU SFSPE_0: EZI Position */ #define SCU_SFSPE_0_EZI_Msk (0x01UL << SCU_SFSPE_0_EZI_Pos) /*!< SCU SFSPE_0: EZI Mask */ #define SCU_SFSPE_0_ZIF_Pos 7 /*!< SCU SFSPE_0: ZIF Position */ #define SCU_SFSPE_0_ZIF_Msk (0x01UL << SCU_SFSPE_0_ZIF_Pos) /*!< SCU SFSPE_0: ZIF Mask */ /* --------------------------------- SCU_SFSPE_1 -------------------------------- */ #define SCU_SFSPE_1_MODE_Pos 0 /*!< SCU SFSPE_1: MODE Position */ #define SCU_SFSPE_1_MODE_Msk (0x07UL << SCU_SFSPE_1_MODE_Pos) /*!< SCU SFSPE_1: MODE Mask */ #define SCU_SFSPE_1_EPD_Pos 3 /*!< SCU SFSPE_1: EPD Position */ #define SCU_SFSPE_1_EPD_Msk (0x01UL << SCU_SFSPE_1_EPD_Pos) /*!< SCU SFSPE_1: EPD Mask */ #define SCU_SFSPE_1_EPUN_Pos 4 /*!< SCU SFSPE_1: EPUN Position */ #define SCU_SFSPE_1_EPUN_Msk (0x01UL << SCU_SFSPE_1_EPUN_Pos) /*!< SCU SFSPE_1: EPUN Mask */ #define SCU_SFSPE_1_EHS_Pos 5 /*!< SCU SFSPE_1: EHS Position */ #define SCU_SFSPE_1_EHS_Msk (0x01UL << SCU_SFSPE_1_EHS_Pos) /*!< SCU SFSPE_1: EHS Mask */ #define SCU_SFSPE_1_EZI_Pos 6 /*!< SCU SFSPE_1: EZI Position */ #define SCU_SFSPE_1_EZI_Msk (0x01UL << SCU_SFSPE_1_EZI_Pos) /*!< SCU SFSPE_1: EZI Mask */ #define SCU_SFSPE_1_ZIF_Pos 7 /*!< SCU SFSPE_1: ZIF Position */ #define SCU_SFSPE_1_ZIF_Msk (0x01UL << SCU_SFSPE_1_ZIF_Pos) /*!< SCU SFSPE_1: ZIF Mask */ /* --------------------------------- SCU_SFSPE_2 -------------------------------- */ #define SCU_SFSPE_2_MODE_Pos 0 /*!< SCU SFSPE_2: MODE Position */ #define SCU_SFSPE_2_MODE_Msk (0x07UL << SCU_SFSPE_2_MODE_Pos) /*!< SCU SFSPE_2: MODE Mask */ #define SCU_SFSPE_2_EPD_Pos 3 /*!< SCU SFSPE_2: EPD Position */ #define SCU_SFSPE_2_EPD_Msk (0x01UL << SCU_SFSPE_2_EPD_Pos) /*!< SCU SFSPE_2: EPD Mask */ #define SCU_SFSPE_2_EPUN_Pos 4 /*!< SCU SFSPE_2: EPUN Position */ #define SCU_SFSPE_2_EPUN_Msk (0x01UL << SCU_SFSPE_2_EPUN_Pos) /*!< SCU SFSPE_2: EPUN Mask */ #define SCU_SFSPE_2_EHS_Pos 5 /*!< SCU SFSPE_2: EHS Position */ #define SCU_SFSPE_2_EHS_Msk (0x01UL << SCU_SFSPE_2_EHS_Pos) /*!< SCU SFSPE_2: EHS Mask */ #define SCU_SFSPE_2_EZI_Pos 6 /*!< SCU SFSPE_2: EZI Position */ #define SCU_SFSPE_2_EZI_Msk (0x01UL << SCU_SFSPE_2_EZI_Pos) /*!< SCU SFSPE_2: EZI Mask */ #define SCU_SFSPE_2_ZIF_Pos 7 /*!< SCU SFSPE_2: ZIF Position */ #define SCU_SFSPE_2_ZIF_Msk (0x01UL << SCU_SFSPE_2_ZIF_Pos) /*!< SCU SFSPE_2: ZIF Mask */ /* --------------------------------- SCU_SFSPE_3 -------------------------------- */ #define SCU_SFSPE_3_MODE_Pos 0 /*!< SCU SFSPE_3: MODE Position */ #define SCU_SFSPE_3_MODE_Msk (0x07UL << SCU_SFSPE_3_MODE_Pos) /*!< SCU SFSPE_3: MODE Mask */ #define SCU_SFSPE_3_EPD_Pos 3 /*!< SCU SFSPE_3: EPD Position */ #define SCU_SFSPE_3_EPD_Msk (0x01UL << SCU_SFSPE_3_EPD_Pos) /*!< SCU SFSPE_3: EPD Mask */ #define SCU_SFSPE_3_EPUN_Pos 4 /*!< SCU SFSPE_3: EPUN Position */ #define SCU_SFSPE_3_EPUN_Msk (0x01UL << SCU_SFSPE_3_EPUN_Pos) /*!< SCU SFSPE_3: EPUN Mask */ #define SCU_SFSPE_3_EHS_Pos 5 /*!< SCU SFSPE_3: EHS Position */ #define SCU_SFSPE_3_EHS_Msk (0x01UL << SCU_SFSPE_3_EHS_Pos) /*!< SCU SFSPE_3: EHS Mask */ #define SCU_SFSPE_3_EZI_Pos 6 /*!< SCU SFSPE_3: EZI Position */ #define SCU_SFSPE_3_EZI_Msk (0x01UL << SCU_SFSPE_3_EZI_Pos) /*!< SCU SFSPE_3: EZI Mask */ #define SCU_SFSPE_3_ZIF_Pos 7 /*!< SCU SFSPE_3: ZIF Position */ #define SCU_SFSPE_3_ZIF_Msk (0x01UL << SCU_SFSPE_3_ZIF_Pos) /*!< SCU SFSPE_3: ZIF Mask */ /* --------------------------------- SCU_SFSPE_4 -------------------------------- */ #define SCU_SFSPE_4_MODE_Pos 0 /*!< SCU SFSPE_4: MODE Position */ #define SCU_SFSPE_4_MODE_Msk (0x07UL << SCU_SFSPE_4_MODE_Pos) /*!< SCU SFSPE_4: MODE Mask */ #define SCU_SFSPE_4_EPD_Pos 3 /*!< SCU SFSPE_4: EPD Position */ #define SCU_SFSPE_4_EPD_Msk (0x01UL << SCU_SFSPE_4_EPD_Pos) /*!< SCU SFSPE_4: EPD Mask */ #define SCU_SFSPE_4_EPUN_Pos 4 /*!< SCU SFSPE_4: EPUN Position */ #define SCU_SFSPE_4_EPUN_Msk (0x01UL << SCU_SFSPE_4_EPUN_Pos) /*!< SCU SFSPE_4: EPUN Mask */ #define SCU_SFSPE_4_EHS_Pos 5 /*!< SCU SFSPE_4: EHS Position */ #define SCU_SFSPE_4_EHS_Msk (0x01UL << SCU_SFSPE_4_EHS_Pos) /*!< SCU SFSPE_4: EHS Mask */ #define SCU_SFSPE_4_EZI_Pos 6 /*!< SCU SFSPE_4: EZI Position */ #define SCU_SFSPE_4_EZI_Msk (0x01UL << SCU_SFSPE_4_EZI_Pos) /*!< SCU SFSPE_4: EZI Mask */ #define SCU_SFSPE_4_ZIF_Pos 7 /*!< SCU SFSPE_4: ZIF Position */ #define SCU_SFSPE_4_ZIF_Msk (0x01UL << SCU_SFSPE_4_ZIF_Pos) /*!< SCU SFSPE_4: ZIF Mask */ /* --------------------------------- SCU_SFSPE_5 -------------------------------- */ #define SCU_SFSPE_5_MODE_Pos 0 /*!< SCU SFSPE_5: MODE Position */ #define SCU_SFSPE_5_MODE_Msk (0x07UL << SCU_SFSPE_5_MODE_Pos) /*!< SCU SFSPE_5: MODE Mask */ #define SCU_SFSPE_5_EPD_Pos 3 /*!< SCU SFSPE_5: EPD Position */ #define SCU_SFSPE_5_EPD_Msk (0x01UL << SCU_SFSPE_5_EPD_Pos) /*!< SCU SFSPE_5: EPD Mask */ #define SCU_SFSPE_5_EPUN_Pos 4 /*!< SCU SFSPE_5: EPUN Position */ #define SCU_SFSPE_5_EPUN_Msk (0x01UL << SCU_SFSPE_5_EPUN_Pos) /*!< SCU SFSPE_5: EPUN Mask */ #define SCU_SFSPE_5_EHS_Pos 5 /*!< SCU SFSPE_5: EHS Position */ #define SCU_SFSPE_5_EHS_Msk (0x01UL << SCU_SFSPE_5_EHS_Pos) /*!< SCU SFSPE_5: EHS Mask */ #define SCU_SFSPE_5_EZI_Pos 6 /*!< SCU SFSPE_5: EZI Position */ #define SCU_SFSPE_5_EZI_Msk (0x01UL << SCU_SFSPE_5_EZI_Pos) /*!< SCU SFSPE_5: EZI Mask */ #define SCU_SFSPE_5_ZIF_Pos 7 /*!< SCU SFSPE_5: ZIF Position */ #define SCU_SFSPE_5_ZIF_Msk (0x01UL << SCU_SFSPE_5_ZIF_Pos) /*!< SCU SFSPE_5: ZIF Mask */ /* --------------------------------- SCU_SFSPE_6 -------------------------------- */ #define SCU_SFSPE_6_MODE_Pos 0 /*!< SCU SFSPE_6: MODE Position */ #define SCU_SFSPE_6_MODE_Msk (0x07UL << SCU_SFSPE_6_MODE_Pos) /*!< SCU SFSPE_6: MODE Mask */ #define SCU_SFSPE_6_EPD_Pos 3 /*!< SCU SFSPE_6: EPD Position */ #define SCU_SFSPE_6_EPD_Msk (0x01UL << SCU_SFSPE_6_EPD_Pos) /*!< SCU SFSPE_6: EPD Mask */ #define SCU_SFSPE_6_EPUN_Pos 4 /*!< SCU SFSPE_6: EPUN Position */ #define SCU_SFSPE_6_EPUN_Msk (0x01UL << SCU_SFSPE_6_EPUN_Pos) /*!< SCU SFSPE_6: EPUN Mask */ #define SCU_SFSPE_6_EHS_Pos 5 /*!< SCU SFSPE_6: EHS Position */ #define SCU_SFSPE_6_EHS_Msk (0x01UL << SCU_SFSPE_6_EHS_Pos) /*!< SCU SFSPE_6: EHS Mask */ #define SCU_SFSPE_6_EZI_Pos 6 /*!< SCU SFSPE_6: EZI Position */ #define SCU_SFSPE_6_EZI_Msk (0x01UL << SCU_SFSPE_6_EZI_Pos) /*!< SCU SFSPE_6: EZI Mask */ #define SCU_SFSPE_6_ZIF_Pos 7 /*!< SCU SFSPE_6: ZIF Position */ #define SCU_SFSPE_6_ZIF_Msk (0x01UL << SCU_SFSPE_6_ZIF_Pos) /*!< SCU SFSPE_6: ZIF Mask */ /* --------------------------------- SCU_SFSPE_7 -------------------------------- */ #define SCU_SFSPE_7_MODE_Pos 0 /*!< SCU SFSPE_7: MODE Position */ #define SCU_SFSPE_7_MODE_Msk (0x07UL << SCU_SFSPE_7_MODE_Pos) /*!< SCU SFSPE_7: MODE Mask */ #define SCU_SFSPE_7_EPD_Pos 3 /*!< SCU SFSPE_7: EPD Position */ #define SCU_SFSPE_7_EPD_Msk (0x01UL << SCU_SFSPE_7_EPD_Pos) /*!< SCU SFSPE_7: EPD Mask */ #define SCU_SFSPE_7_EPUN_Pos 4 /*!< SCU SFSPE_7: EPUN Position */ #define SCU_SFSPE_7_EPUN_Msk (0x01UL << SCU_SFSPE_7_EPUN_Pos) /*!< SCU SFSPE_7: EPUN Mask */ #define SCU_SFSPE_7_EHS_Pos 5 /*!< SCU SFSPE_7: EHS Position */ #define SCU_SFSPE_7_EHS_Msk (0x01UL << SCU_SFSPE_7_EHS_Pos) /*!< SCU SFSPE_7: EHS Mask */ #define SCU_SFSPE_7_EZI_Pos 6 /*!< SCU SFSPE_7: EZI Position */ #define SCU_SFSPE_7_EZI_Msk (0x01UL << SCU_SFSPE_7_EZI_Pos) /*!< SCU SFSPE_7: EZI Mask */ #define SCU_SFSPE_7_ZIF_Pos 7 /*!< SCU SFSPE_7: ZIF Position */ #define SCU_SFSPE_7_ZIF_Msk (0x01UL << SCU_SFSPE_7_ZIF_Pos) /*!< SCU SFSPE_7: ZIF Mask */ /* --------------------------------- SCU_SFSPE_8 -------------------------------- */ #define SCU_SFSPE_8_MODE_Pos 0 /*!< SCU SFSPE_8: MODE Position */ #define SCU_SFSPE_8_MODE_Msk (0x07UL << SCU_SFSPE_8_MODE_Pos) /*!< SCU SFSPE_8: MODE Mask */ #define SCU_SFSPE_8_EPD_Pos 3 /*!< SCU SFSPE_8: EPD Position */ #define SCU_SFSPE_8_EPD_Msk (0x01UL << SCU_SFSPE_8_EPD_Pos) /*!< SCU SFSPE_8: EPD Mask */ #define SCU_SFSPE_8_EPUN_Pos 4 /*!< SCU SFSPE_8: EPUN Position */ #define SCU_SFSPE_8_EPUN_Msk (0x01UL << SCU_SFSPE_8_EPUN_Pos) /*!< SCU SFSPE_8: EPUN Mask */ #define SCU_SFSPE_8_EHS_Pos 5 /*!< SCU SFSPE_8: EHS Position */ #define SCU_SFSPE_8_EHS_Msk (0x01UL << SCU_SFSPE_8_EHS_Pos) /*!< SCU SFSPE_8: EHS Mask */ #define SCU_SFSPE_8_EZI_Pos 6 /*!< SCU SFSPE_8: EZI Position */ #define SCU_SFSPE_8_EZI_Msk (0x01UL << SCU_SFSPE_8_EZI_Pos) /*!< SCU SFSPE_8: EZI Mask */ #define SCU_SFSPE_8_ZIF_Pos 7 /*!< SCU SFSPE_8: ZIF Position */ #define SCU_SFSPE_8_ZIF_Msk (0x01UL << SCU_SFSPE_8_ZIF_Pos) /*!< SCU SFSPE_8: ZIF Mask */ /* --------------------------------- SCU_SFSPE_9 -------------------------------- */ #define SCU_SFSPE_9_MODE_Pos 0 /*!< SCU SFSPE_9: MODE Position */ #define SCU_SFSPE_9_MODE_Msk (0x07UL << SCU_SFSPE_9_MODE_Pos) /*!< SCU SFSPE_9: MODE Mask */ #define SCU_SFSPE_9_EPD_Pos 3 /*!< SCU SFSPE_9: EPD Position */ #define SCU_SFSPE_9_EPD_Msk (0x01UL << SCU_SFSPE_9_EPD_Pos) /*!< SCU SFSPE_9: EPD Mask */ #define SCU_SFSPE_9_EPUN_Pos 4 /*!< SCU SFSPE_9: EPUN Position */ #define SCU_SFSPE_9_EPUN_Msk (0x01UL << SCU_SFSPE_9_EPUN_Pos) /*!< SCU SFSPE_9: EPUN Mask */ #define SCU_SFSPE_9_EHS_Pos 5 /*!< SCU SFSPE_9: EHS Position */ #define SCU_SFSPE_9_EHS_Msk (0x01UL << SCU_SFSPE_9_EHS_Pos) /*!< SCU SFSPE_9: EHS Mask */ #define SCU_SFSPE_9_EZI_Pos 6 /*!< SCU SFSPE_9: EZI Position */ #define SCU_SFSPE_9_EZI_Msk (0x01UL << SCU_SFSPE_9_EZI_Pos) /*!< SCU SFSPE_9: EZI Mask */ #define SCU_SFSPE_9_ZIF_Pos 7 /*!< SCU SFSPE_9: ZIF Position */ #define SCU_SFSPE_9_ZIF_Msk (0x01UL << SCU_SFSPE_9_ZIF_Pos) /*!< SCU SFSPE_9: ZIF Mask */ /* -------------------------------- SCU_SFSPE_10 -------------------------------- */ #define SCU_SFSPE_10_MODE_Pos 0 /*!< SCU SFSPE_10: MODE Position */ #define SCU_SFSPE_10_MODE_Msk (0x07UL << SCU_SFSPE_10_MODE_Pos) /*!< SCU SFSPE_10: MODE Mask */ #define SCU_SFSPE_10_EPD_Pos 3 /*!< SCU SFSPE_10: EPD Position */ #define SCU_SFSPE_10_EPD_Msk (0x01UL << SCU_SFSPE_10_EPD_Pos) /*!< SCU SFSPE_10: EPD Mask */ #define SCU_SFSPE_10_EPUN_Pos 4 /*!< SCU SFSPE_10: EPUN Position */ #define SCU_SFSPE_10_EPUN_Msk (0x01UL << SCU_SFSPE_10_EPUN_Pos) /*!< SCU SFSPE_10: EPUN Mask */ #define SCU_SFSPE_10_EHS_Pos 5 /*!< SCU SFSPE_10: EHS Position */ #define SCU_SFSPE_10_EHS_Msk (0x01UL << SCU_SFSPE_10_EHS_Pos) /*!< SCU SFSPE_10: EHS Mask */ #define SCU_SFSPE_10_EZI_Pos 6 /*!< SCU SFSPE_10: EZI Position */ #define SCU_SFSPE_10_EZI_Msk (0x01UL << SCU_SFSPE_10_EZI_Pos) /*!< SCU SFSPE_10: EZI Mask */ #define SCU_SFSPE_10_ZIF_Pos 7 /*!< SCU SFSPE_10: ZIF Position */ #define SCU_SFSPE_10_ZIF_Msk (0x01UL << SCU_SFSPE_10_ZIF_Pos) /*!< SCU SFSPE_10: ZIF Mask */ /* -------------------------------- SCU_SFSPE_11 -------------------------------- */ #define SCU_SFSPE_11_MODE_Pos 0 /*!< SCU SFSPE_11: MODE Position */ #define SCU_SFSPE_11_MODE_Msk (0x07UL << SCU_SFSPE_11_MODE_Pos) /*!< SCU SFSPE_11: MODE Mask */ #define SCU_SFSPE_11_EPD_Pos 3 /*!< SCU SFSPE_11: EPD Position */ #define SCU_SFSPE_11_EPD_Msk (0x01UL << SCU_SFSPE_11_EPD_Pos) /*!< SCU SFSPE_11: EPD Mask */ #define SCU_SFSPE_11_EPUN_Pos 4 /*!< SCU SFSPE_11: EPUN Position */ #define SCU_SFSPE_11_EPUN_Msk (0x01UL << SCU_SFSPE_11_EPUN_Pos) /*!< SCU SFSPE_11: EPUN Mask */ #define SCU_SFSPE_11_EHS_Pos 5 /*!< SCU SFSPE_11: EHS Position */ #define SCU_SFSPE_11_EHS_Msk (0x01UL << SCU_SFSPE_11_EHS_Pos) /*!< SCU SFSPE_11: EHS Mask */ #define SCU_SFSPE_11_EZI_Pos 6 /*!< SCU SFSPE_11: EZI Position */ #define SCU_SFSPE_11_EZI_Msk (0x01UL << SCU_SFSPE_11_EZI_Pos) /*!< SCU SFSPE_11: EZI Mask */ #define SCU_SFSPE_11_ZIF_Pos 7 /*!< SCU SFSPE_11: ZIF Position */ #define SCU_SFSPE_11_ZIF_Msk (0x01UL << SCU_SFSPE_11_ZIF_Pos) /*!< SCU SFSPE_11: ZIF Mask */ /* -------------------------------- SCU_SFSPE_12 -------------------------------- */ #define SCU_SFSPE_12_MODE_Pos 0 /*!< SCU SFSPE_12: MODE Position */ #define SCU_SFSPE_12_MODE_Msk (0x07UL << SCU_SFSPE_12_MODE_Pos) /*!< SCU SFSPE_12: MODE Mask */ #define SCU_SFSPE_12_EPD_Pos 3 /*!< SCU SFSPE_12: EPD Position */ #define SCU_SFSPE_12_EPD_Msk (0x01UL << SCU_SFSPE_12_EPD_Pos) /*!< SCU SFSPE_12: EPD Mask */ #define SCU_SFSPE_12_EPUN_Pos 4 /*!< SCU SFSPE_12: EPUN Position */ #define SCU_SFSPE_12_EPUN_Msk (0x01UL << SCU_SFSPE_12_EPUN_Pos) /*!< SCU SFSPE_12: EPUN Mask */ #define SCU_SFSPE_12_EHS_Pos 5 /*!< SCU SFSPE_12: EHS Position */ #define SCU_SFSPE_12_EHS_Msk (0x01UL << SCU_SFSPE_12_EHS_Pos) /*!< SCU SFSPE_12: EHS Mask */ #define SCU_SFSPE_12_EZI_Pos 6 /*!< SCU SFSPE_12: EZI Position */ #define SCU_SFSPE_12_EZI_Msk (0x01UL << SCU_SFSPE_12_EZI_Pos) /*!< SCU SFSPE_12: EZI Mask */ #define SCU_SFSPE_12_ZIF_Pos 7 /*!< SCU SFSPE_12: ZIF Position */ #define SCU_SFSPE_12_ZIF_Msk (0x01UL << SCU_SFSPE_12_ZIF_Pos) /*!< SCU SFSPE_12: ZIF Mask */ /* -------------------------------- SCU_SFSPE_13 -------------------------------- */ #define SCU_SFSPE_13_MODE_Pos 0 /*!< SCU SFSPE_13: MODE Position */ #define SCU_SFSPE_13_MODE_Msk (0x07UL << SCU_SFSPE_13_MODE_Pos) /*!< SCU SFSPE_13: MODE Mask */ #define SCU_SFSPE_13_EPD_Pos 3 /*!< SCU SFSPE_13: EPD Position */ #define SCU_SFSPE_13_EPD_Msk (0x01UL << SCU_SFSPE_13_EPD_Pos) /*!< SCU SFSPE_13: EPD Mask */ #define SCU_SFSPE_13_EPUN_Pos 4 /*!< SCU SFSPE_13: EPUN Position */ #define SCU_SFSPE_13_EPUN_Msk (0x01UL << SCU_SFSPE_13_EPUN_Pos) /*!< SCU SFSPE_13: EPUN Mask */ #define SCU_SFSPE_13_EHS_Pos 5 /*!< SCU SFSPE_13: EHS Position */ #define SCU_SFSPE_13_EHS_Msk (0x01UL << SCU_SFSPE_13_EHS_Pos) /*!< SCU SFSPE_13: EHS Mask */ #define SCU_SFSPE_13_EZI_Pos 6 /*!< SCU SFSPE_13: EZI Position */ #define SCU_SFSPE_13_EZI_Msk (0x01UL << SCU_SFSPE_13_EZI_Pos) /*!< SCU SFSPE_13: EZI Mask */ #define SCU_SFSPE_13_ZIF_Pos 7 /*!< SCU SFSPE_13: ZIF Position */ #define SCU_SFSPE_13_ZIF_Msk (0x01UL << SCU_SFSPE_13_ZIF_Pos) /*!< SCU SFSPE_13: ZIF Mask */ /* -------------------------------- SCU_SFSPE_14 -------------------------------- */ #define SCU_SFSPE_14_MODE_Pos 0 /*!< SCU SFSPE_14: MODE Position */ #define SCU_SFSPE_14_MODE_Msk (0x07UL << SCU_SFSPE_14_MODE_Pos) /*!< SCU SFSPE_14: MODE Mask */ #define SCU_SFSPE_14_EPD_Pos 3 /*!< SCU SFSPE_14: EPD Position */ #define SCU_SFSPE_14_EPD_Msk (0x01UL << SCU_SFSPE_14_EPD_Pos) /*!< SCU SFSPE_14: EPD Mask */ #define SCU_SFSPE_14_EPUN_Pos 4 /*!< SCU SFSPE_14: EPUN Position */ #define SCU_SFSPE_14_EPUN_Msk (0x01UL << SCU_SFSPE_14_EPUN_Pos) /*!< SCU SFSPE_14: EPUN Mask */ #define SCU_SFSPE_14_EHS_Pos 5 /*!< SCU SFSPE_14: EHS Position */ #define SCU_SFSPE_14_EHS_Msk (0x01UL << SCU_SFSPE_14_EHS_Pos) /*!< SCU SFSPE_14: EHS Mask */ #define SCU_SFSPE_14_EZI_Pos 6 /*!< SCU SFSPE_14: EZI Position */ #define SCU_SFSPE_14_EZI_Msk (0x01UL << SCU_SFSPE_14_EZI_Pos) /*!< SCU SFSPE_14: EZI Mask */ #define SCU_SFSPE_14_ZIF_Pos 7 /*!< SCU SFSPE_14: ZIF Position */ #define SCU_SFSPE_14_ZIF_Msk (0x01UL << SCU_SFSPE_14_ZIF_Pos) /*!< SCU SFSPE_14: ZIF Mask */ /* -------------------------------- SCU_SFSPE_15 -------------------------------- */ #define SCU_SFSPE_15_MODE_Pos 0 /*!< SCU SFSPE_15: MODE Position */ #define SCU_SFSPE_15_MODE_Msk (0x07UL << SCU_SFSPE_15_MODE_Pos) /*!< SCU SFSPE_15: MODE Mask */ #define SCU_SFSPE_15_EPD_Pos 3 /*!< SCU SFSPE_15: EPD Position */ #define SCU_SFSPE_15_EPD_Msk (0x01UL << SCU_SFSPE_15_EPD_Pos) /*!< SCU SFSPE_15: EPD Mask */ #define SCU_SFSPE_15_EPUN_Pos 4 /*!< SCU SFSPE_15: EPUN Position */ #define SCU_SFSPE_15_EPUN_Msk (0x01UL << SCU_SFSPE_15_EPUN_Pos) /*!< SCU SFSPE_15: EPUN Mask */ #define SCU_SFSPE_15_EHS_Pos 5 /*!< SCU SFSPE_15: EHS Position */ #define SCU_SFSPE_15_EHS_Msk (0x01UL << SCU_SFSPE_15_EHS_Pos) /*!< SCU SFSPE_15: EHS Mask */ #define SCU_SFSPE_15_EZI_Pos 6 /*!< SCU SFSPE_15: EZI Position */ #define SCU_SFSPE_15_EZI_Msk (0x01UL << SCU_SFSPE_15_EZI_Pos) /*!< SCU SFSPE_15: EZI Mask */ #define SCU_SFSPE_15_ZIF_Pos 7 /*!< SCU SFSPE_15: ZIF Position */ #define SCU_SFSPE_15_ZIF_Msk (0x01UL << SCU_SFSPE_15_ZIF_Pos) /*!< SCU SFSPE_15: ZIF Mask */ /* --------------------------------- SCU_SFSPF_0 -------------------------------- */ #define SCU_SFSPF_0_MODE_Pos 0 /*!< SCU SFSPF_0: MODE Position */ #define SCU_SFSPF_0_MODE_Msk (0x07UL << SCU_SFSPF_0_MODE_Pos) /*!< SCU SFSPF_0: MODE Mask */ #define SCU_SFSPF_0_EPD_Pos 3 /*!< SCU SFSPF_0: EPD Position */ #define SCU_SFSPF_0_EPD_Msk (0x01UL << SCU_SFSPF_0_EPD_Pos) /*!< SCU SFSPF_0: EPD Mask */ #define SCU_SFSPF_0_EPUN_Pos 4 /*!< SCU SFSPF_0: EPUN Position */ #define SCU_SFSPF_0_EPUN_Msk (0x01UL << SCU_SFSPF_0_EPUN_Pos) /*!< SCU SFSPF_0: EPUN Mask */ #define SCU_SFSPF_0_EHS_Pos 5 /*!< SCU SFSPF_0: EHS Position */ #define SCU_SFSPF_0_EHS_Msk (0x01UL << SCU_SFSPF_0_EHS_Pos) /*!< SCU SFSPF_0: EHS Mask */ #define SCU_SFSPF_0_EZI_Pos 6 /*!< SCU SFSPF_0: EZI Position */ #define SCU_SFSPF_0_EZI_Msk (0x01UL << SCU_SFSPF_0_EZI_Pos) /*!< SCU SFSPF_0: EZI Mask */ #define SCU_SFSPF_0_ZIF_Pos 7 /*!< SCU SFSPF_0: ZIF Position */ #define SCU_SFSPF_0_ZIF_Msk (0x01UL << SCU_SFSPF_0_ZIF_Pos) /*!< SCU SFSPF_0: ZIF Mask */ /* --------------------------------- SCU_SFSPF_1 -------------------------------- */ #define SCU_SFSPF_1_MODE_Pos 0 /*!< SCU SFSPF_1: MODE Position */ #define SCU_SFSPF_1_MODE_Msk (0x07UL << SCU_SFSPF_1_MODE_Pos) /*!< SCU SFSPF_1: MODE Mask */ #define SCU_SFSPF_1_EPD_Pos 3 /*!< SCU SFSPF_1: EPD Position */ #define SCU_SFSPF_1_EPD_Msk (0x01UL << SCU_SFSPF_1_EPD_Pos) /*!< SCU SFSPF_1: EPD Mask */ #define SCU_SFSPF_1_EPUN_Pos 4 /*!< SCU SFSPF_1: EPUN Position */ #define SCU_SFSPF_1_EPUN_Msk (0x01UL << SCU_SFSPF_1_EPUN_Pos) /*!< SCU SFSPF_1: EPUN Mask */ #define SCU_SFSPF_1_EHS_Pos 5 /*!< SCU SFSPF_1: EHS Position */ #define SCU_SFSPF_1_EHS_Msk (0x01UL << SCU_SFSPF_1_EHS_Pos) /*!< SCU SFSPF_1: EHS Mask */ #define SCU_SFSPF_1_EZI_Pos 6 /*!< SCU SFSPF_1: EZI Position */ #define SCU_SFSPF_1_EZI_Msk (0x01UL << SCU_SFSPF_1_EZI_Pos) /*!< SCU SFSPF_1: EZI Mask */ #define SCU_SFSPF_1_ZIF_Pos 7 /*!< SCU SFSPF_1: ZIF Position */ #define SCU_SFSPF_1_ZIF_Msk (0x01UL << SCU_SFSPF_1_ZIF_Pos) /*!< SCU SFSPF_1: ZIF Mask */ /* --------------------------------- SCU_SFSPF_2 -------------------------------- */ #define SCU_SFSPF_2_MODE_Pos 0 /*!< SCU SFSPF_2: MODE Position */ #define SCU_SFSPF_2_MODE_Msk (0x07UL << SCU_SFSPF_2_MODE_Pos) /*!< SCU SFSPF_2: MODE Mask */ #define SCU_SFSPF_2_EPD_Pos 3 /*!< SCU SFSPF_2: EPD Position */ #define SCU_SFSPF_2_EPD_Msk (0x01UL << SCU_SFSPF_2_EPD_Pos) /*!< SCU SFSPF_2: EPD Mask */ #define SCU_SFSPF_2_EPUN_Pos 4 /*!< SCU SFSPF_2: EPUN Position */ #define SCU_SFSPF_2_EPUN_Msk (0x01UL << SCU_SFSPF_2_EPUN_Pos) /*!< SCU SFSPF_2: EPUN Mask */ #define SCU_SFSPF_2_EHS_Pos 5 /*!< SCU SFSPF_2: EHS Position */ #define SCU_SFSPF_2_EHS_Msk (0x01UL << SCU_SFSPF_2_EHS_Pos) /*!< SCU SFSPF_2: EHS Mask */ #define SCU_SFSPF_2_EZI_Pos 6 /*!< SCU SFSPF_2: EZI Position */ #define SCU_SFSPF_2_EZI_Msk (0x01UL << SCU_SFSPF_2_EZI_Pos) /*!< SCU SFSPF_2: EZI Mask */ #define SCU_SFSPF_2_ZIF_Pos 7 /*!< SCU SFSPF_2: ZIF Position */ #define SCU_SFSPF_2_ZIF_Msk (0x01UL << SCU_SFSPF_2_ZIF_Pos) /*!< SCU SFSPF_2: ZIF Mask */ /* --------------------------------- SCU_SFSPF_3 -------------------------------- */ #define SCU_SFSPF_3_MODE_Pos 0 /*!< SCU SFSPF_3: MODE Position */ #define SCU_SFSPF_3_MODE_Msk (0x07UL << SCU_SFSPF_3_MODE_Pos) /*!< SCU SFSPF_3: MODE Mask */ #define SCU_SFSPF_3_EPD_Pos 3 /*!< SCU SFSPF_3: EPD Position */ #define SCU_SFSPF_3_EPD_Msk (0x01UL << SCU_SFSPF_3_EPD_Pos) /*!< SCU SFSPF_3: EPD Mask */ #define SCU_SFSPF_3_EPUN_Pos 4 /*!< SCU SFSPF_3: EPUN Position */ #define SCU_SFSPF_3_EPUN_Msk (0x01UL << SCU_SFSPF_3_EPUN_Pos) /*!< SCU SFSPF_3: EPUN Mask */ #define SCU_SFSPF_3_EHS_Pos 5 /*!< SCU SFSPF_3: EHS Position */ #define SCU_SFSPF_3_EHS_Msk (0x01UL << SCU_SFSPF_3_EHS_Pos) /*!< SCU SFSPF_3: EHS Mask */ #define SCU_SFSPF_3_EZI_Pos 6 /*!< SCU SFSPF_3: EZI Position */ #define SCU_SFSPF_3_EZI_Msk (0x01UL << SCU_SFSPF_3_EZI_Pos) /*!< SCU SFSPF_3: EZI Mask */ #define SCU_SFSPF_3_ZIF_Pos 7 /*!< SCU SFSPF_3: ZIF Position */ #define SCU_SFSPF_3_ZIF_Msk (0x01UL << SCU_SFSPF_3_ZIF_Pos) /*!< SCU SFSPF_3: ZIF Mask */ /* --------------------------------- SCU_SFSPF_4 -------------------------------- */ #define SCU_SFSPF_4_MODE_Pos 0 /*!< SCU SFSPF_4: MODE Position */ #define SCU_SFSPF_4_MODE_Msk (0x07UL << SCU_SFSPF_4_MODE_Pos) /*!< SCU SFSPF_4: MODE Mask */ #define SCU_SFSPF_4_EPD_Pos 3 /*!< SCU SFSPF_4: EPD Position */ #define SCU_SFSPF_4_EPD_Msk (0x01UL << SCU_SFSPF_4_EPD_Pos) /*!< SCU SFSPF_4: EPD Mask */ #define SCU_SFSPF_4_EPUN_Pos 4 /*!< SCU SFSPF_4: EPUN Position */ #define SCU_SFSPF_4_EPUN_Msk (0x01UL << SCU_SFSPF_4_EPUN_Pos) /*!< SCU SFSPF_4: EPUN Mask */ #define SCU_SFSPF_4_EHS_Pos 5 /*!< SCU SFSPF_4: EHS Position */ #define SCU_SFSPF_4_EHS_Msk (0x01UL << SCU_SFSPF_4_EHS_Pos) /*!< SCU SFSPF_4: EHS Mask */ #define SCU_SFSPF_4_EZI_Pos 6 /*!< SCU SFSPF_4: EZI Position */ #define SCU_SFSPF_4_EZI_Msk (0x01UL << SCU_SFSPF_4_EZI_Pos) /*!< SCU SFSPF_4: EZI Mask */ #define SCU_SFSPF_4_ZIF_Pos 7 /*!< SCU SFSPF_4: ZIF Position */ #define SCU_SFSPF_4_ZIF_Msk (0x01UL << SCU_SFSPF_4_ZIF_Pos) /*!< SCU SFSPF_4: ZIF Mask */ /* --------------------------------- SCU_SFSPF_5 -------------------------------- */ #define SCU_SFSPF_5_MODE_Pos 0 /*!< SCU SFSPF_5: MODE Position */ #define SCU_SFSPF_5_MODE_Msk (0x07UL << SCU_SFSPF_5_MODE_Pos) /*!< SCU SFSPF_5: MODE Mask */ #define SCU_SFSPF_5_EPD_Pos 3 /*!< SCU SFSPF_5: EPD Position */ #define SCU_SFSPF_5_EPD_Msk (0x01UL << SCU_SFSPF_5_EPD_Pos) /*!< SCU SFSPF_5: EPD Mask */ #define SCU_SFSPF_5_EPUN_Pos 4 /*!< SCU SFSPF_5: EPUN Position */ #define SCU_SFSPF_5_EPUN_Msk (0x01UL << SCU_SFSPF_5_EPUN_Pos) /*!< SCU SFSPF_5: EPUN Mask */ #define SCU_SFSPF_5_EHS_Pos 5 /*!< SCU SFSPF_5: EHS Position */ #define SCU_SFSPF_5_EHS_Msk (0x01UL << SCU_SFSPF_5_EHS_Pos) /*!< SCU SFSPF_5: EHS Mask */ #define SCU_SFSPF_5_EZI_Pos 6 /*!< SCU SFSPF_5: EZI Position */ #define SCU_SFSPF_5_EZI_Msk (0x01UL << SCU_SFSPF_5_EZI_Pos) /*!< SCU SFSPF_5: EZI Mask */ #define SCU_SFSPF_5_ZIF_Pos 7 /*!< SCU SFSPF_5: ZIF Position */ #define SCU_SFSPF_5_ZIF_Msk (0x01UL << SCU_SFSPF_5_ZIF_Pos) /*!< SCU SFSPF_5: ZIF Mask */ /* --------------------------------- SCU_SFSPF_6 -------------------------------- */ #define SCU_SFSPF_6_MODE_Pos 0 /*!< SCU SFSPF_6: MODE Position */ #define SCU_SFSPF_6_MODE_Msk (0x07UL << SCU_SFSPF_6_MODE_Pos) /*!< SCU SFSPF_6: MODE Mask */ #define SCU_SFSPF_6_EPD_Pos 3 /*!< SCU SFSPF_6: EPD Position */ #define SCU_SFSPF_6_EPD_Msk (0x01UL << SCU_SFSPF_6_EPD_Pos) /*!< SCU SFSPF_6: EPD Mask */ #define SCU_SFSPF_6_EPUN_Pos 4 /*!< SCU SFSPF_6: EPUN Position */ #define SCU_SFSPF_6_EPUN_Msk (0x01UL << SCU_SFSPF_6_EPUN_Pos) /*!< SCU SFSPF_6: EPUN Mask */ #define SCU_SFSPF_6_EHS_Pos 5 /*!< SCU SFSPF_6: EHS Position */ #define SCU_SFSPF_6_EHS_Msk (0x01UL << SCU_SFSPF_6_EHS_Pos) /*!< SCU SFSPF_6: EHS Mask */ #define SCU_SFSPF_6_EZI_Pos 6 /*!< SCU SFSPF_6: EZI Position */ #define SCU_SFSPF_6_EZI_Msk (0x01UL << SCU_SFSPF_6_EZI_Pos) /*!< SCU SFSPF_6: EZI Mask */ #define SCU_SFSPF_6_ZIF_Pos 7 /*!< SCU SFSPF_6: ZIF Position */ #define SCU_SFSPF_6_ZIF_Msk (0x01UL << SCU_SFSPF_6_ZIF_Pos) /*!< SCU SFSPF_6: ZIF Mask */ /* --------------------------------- SCU_SFSPF_7 -------------------------------- */ #define SCU_SFSPF_7_MODE_Pos 0 /*!< SCU SFSPF_7: MODE Position */ #define SCU_SFSPF_7_MODE_Msk (0x07UL << SCU_SFSPF_7_MODE_Pos) /*!< SCU SFSPF_7: MODE Mask */ #define SCU_SFSPF_7_EPD_Pos 3 /*!< SCU SFSPF_7: EPD Position */ #define SCU_SFSPF_7_EPD_Msk (0x01UL << SCU_SFSPF_7_EPD_Pos) /*!< SCU SFSPF_7: EPD Mask */ #define SCU_SFSPF_7_EPUN_Pos 4 /*!< SCU SFSPF_7: EPUN Position */ #define SCU_SFSPF_7_EPUN_Msk (0x01UL << SCU_SFSPF_7_EPUN_Pos) /*!< SCU SFSPF_7: EPUN Mask */ #define SCU_SFSPF_7_EHS_Pos 5 /*!< SCU SFSPF_7: EHS Position */ #define SCU_SFSPF_7_EHS_Msk (0x01UL << SCU_SFSPF_7_EHS_Pos) /*!< SCU SFSPF_7: EHS Mask */ #define SCU_SFSPF_7_EZI_Pos 6 /*!< SCU SFSPF_7: EZI Position */ #define SCU_SFSPF_7_EZI_Msk (0x01UL << SCU_SFSPF_7_EZI_Pos) /*!< SCU SFSPF_7: EZI Mask */ #define SCU_SFSPF_7_ZIF_Pos 7 /*!< SCU SFSPF_7: ZIF Position */ #define SCU_SFSPF_7_ZIF_Msk (0x01UL << SCU_SFSPF_7_ZIF_Pos) /*!< SCU SFSPF_7: ZIF Mask */ /* --------------------------------- SCU_SFSPF_8 -------------------------------- */ #define SCU_SFSPF_8_MODE_Pos 0 /*!< SCU SFSPF_8: MODE Position */ #define SCU_SFSPF_8_MODE_Msk (0x07UL << SCU_SFSPF_8_MODE_Pos) /*!< SCU SFSPF_8: MODE Mask */ #define SCU_SFSPF_8_EPD_Pos 3 /*!< SCU SFSPF_8: EPD Position */ #define SCU_SFSPF_8_EPD_Msk (0x01UL << SCU_SFSPF_8_EPD_Pos) /*!< SCU SFSPF_8: EPD Mask */ #define SCU_SFSPF_8_EPUN_Pos 4 /*!< SCU SFSPF_8: EPUN Position */ #define SCU_SFSPF_8_EPUN_Msk (0x01UL << SCU_SFSPF_8_EPUN_Pos) /*!< SCU SFSPF_8: EPUN Mask */ #define SCU_SFSPF_8_EHS_Pos 5 /*!< SCU SFSPF_8: EHS Position */ #define SCU_SFSPF_8_EHS_Msk (0x01UL << SCU_SFSPF_8_EHS_Pos) /*!< SCU SFSPF_8: EHS Mask */ #define SCU_SFSPF_8_EZI_Pos 6 /*!< SCU SFSPF_8: EZI Position */ #define SCU_SFSPF_8_EZI_Msk (0x01UL << SCU_SFSPF_8_EZI_Pos) /*!< SCU SFSPF_8: EZI Mask */ #define SCU_SFSPF_8_ZIF_Pos 7 /*!< SCU SFSPF_8: ZIF Position */ #define SCU_SFSPF_8_ZIF_Msk (0x01UL << SCU_SFSPF_8_ZIF_Pos) /*!< SCU SFSPF_8: ZIF Mask */ /* --------------------------------- SCU_SFSPF_9 -------------------------------- */ #define SCU_SFSPF_9_MODE_Pos 0 /*!< SCU SFSPF_9: MODE Position */ #define SCU_SFSPF_9_MODE_Msk (0x07UL << SCU_SFSPF_9_MODE_Pos) /*!< SCU SFSPF_9: MODE Mask */ #define SCU_SFSPF_9_EPD_Pos 3 /*!< SCU SFSPF_9: EPD Position */ #define SCU_SFSPF_9_EPD_Msk (0x01UL << SCU_SFSPF_9_EPD_Pos) /*!< SCU SFSPF_9: EPD Mask */ #define SCU_SFSPF_9_EPUN_Pos 4 /*!< SCU SFSPF_9: EPUN Position */ #define SCU_SFSPF_9_EPUN_Msk (0x01UL << SCU_SFSPF_9_EPUN_Pos) /*!< SCU SFSPF_9: EPUN Mask */ #define SCU_SFSPF_9_EHS_Pos 5 /*!< SCU SFSPF_9: EHS Position */ #define SCU_SFSPF_9_EHS_Msk (0x01UL << SCU_SFSPF_9_EHS_Pos) /*!< SCU SFSPF_9: EHS Mask */ #define SCU_SFSPF_9_EZI_Pos 6 /*!< SCU SFSPF_9: EZI Position */ #define SCU_SFSPF_9_EZI_Msk (0x01UL << SCU_SFSPF_9_EZI_Pos) /*!< SCU SFSPF_9: EZI Mask */ #define SCU_SFSPF_9_ZIF_Pos 7 /*!< SCU SFSPF_9: ZIF Position */ #define SCU_SFSPF_9_ZIF_Msk (0x01UL << SCU_SFSPF_9_ZIF_Pos) /*!< SCU SFSPF_9: ZIF Mask */ /* -------------------------------- SCU_SFSPF_10 -------------------------------- */ #define SCU_SFSPF_10_MODE_Pos 0 /*!< SCU SFSPF_10: MODE Position */ #define SCU_SFSPF_10_MODE_Msk (0x07UL << SCU_SFSPF_10_MODE_Pos) /*!< SCU SFSPF_10: MODE Mask */ #define SCU_SFSPF_10_EPD_Pos 3 /*!< SCU SFSPF_10: EPD Position */ #define SCU_SFSPF_10_EPD_Msk (0x01UL << SCU_SFSPF_10_EPD_Pos) /*!< SCU SFSPF_10: EPD Mask */ #define SCU_SFSPF_10_EPUN_Pos 4 /*!< SCU SFSPF_10: EPUN Position */ #define SCU_SFSPF_10_EPUN_Msk (0x01UL << SCU_SFSPF_10_EPUN_Pos) /*!< SCU SFSPF_10: EPUN Mask */ #define SCU_SFSPF_10_EHS_Pos 5 /*!< SCU SFSPF_10: EHS Position */ #define SCU_SFSPF_10_EHS_Msk (0x01UL << SCU_SFSPF_10_EHS_Pos) /*!< SCU SFSPF_10: EHS Mask */ #define SCU_SFSPF_10_EZI_Pos 6 /*!< SCU SFSPF_10: EZI Position */ #define SCU_SFSPF_10_EZI_Msk (0x01UL << SCU_SFSPF_10_EZI_Pos) /*!< SCU SFSPF_10: EZI Mask */ #define SCU_SFSPF_10_ZIF_Pos 7 /*!< SCU SFSPF_10: ZIF Position */ #define SCU_SFSPF_10_ZIF_Msk (0x01UL << SCU_SFSPF_10_ZIF_Pos) /*!< SCU SFSPF_10: ZIF Mask */ /* -------------------------------- SCU_SFSPF_11 -------------------------------- */ #define SCU_SFSPF_11_MODE_Pos 0 /*!< SCU SFSPF_11: MODE Position */ #define SCU_SFSPF_11_MODE_Msk (0x07UL << SCU_SFSPF_11_MODE_Pos) /*!< SCU SFSPF_11: MODE Mask */ #define SCU_SFSPF_11_EPD_Pos 3 /*!< SCU SFSPF_11: EPD Position */ #define SCU_SFSPF_11_EPD_Msk (0x01UL << SCU_SFSPF_11_EPD_Pos) /*!< SCU SFSPF_11: EPD Mask */ #define SCU_SFSPF_11_EPUN_Pos 4 /*!< SCU SFSPF_11: EPUN Position */ #define SCU_SFSPF_11_EPUN_Msk (0x01UL << SCU_SFSPF_11_EPUN_Pos) /*!< SCU SFSPF_11: EPUN Mask */ #define SCU_SFSPF_11_EHS_Pos 5 /*!< SCU SFSPF_11: EHS Position */ #define SCU_SFSPF_11_EHS_Msk (0x01UL << SCU_SFSPF_11_EHS_Pos) /*!< SCU SFSPF_11: EHS Mask */ #define SCU_SFSPF_11_EZI_Pos 6 /*!< SCU SFSPF_11: EZI Position */ #define SCU_SFSPF_11_EZI_Msk (0x01UL << SCU_SFSPF_11_EZI_Pos) /*!< SCU SFSPF_11: EZI Mask */ #define SCU_SFSPF_11_ZIF_Pos 7 /*!< SCU SFSPF_11: ZIF Position */ #define SCU_SFSPF_11_ZIF_Msk (0x01UL << SCU_SFSPF_11_ZIF_Pos) /*!< SCU SFSPF_11: ZIF Mask */ /* -------------------------------- SCU_SFSCLK_0 -------------------------------- */ #define SCU_SFSCLK_0_MODE_Pos 0 /*!< SCU SFSCLK_0: MODE Position */ #define SCU_SFSCLK_0_MODE_Msk (0x07UL << SCU_SFSCLK_0_MODE_Pos) /*!< SCU SFSCLK_0: MODE Mask */ #define SCU_SFSCLK_0_EPD_Pos 3 /*!< SCU SFSCLK_0: EPD Position */ #define SCU_SFSCLK_0_EPD_Msk (0x01UL << SCU_SFSCLK_0_EPD_Pos) /*!< SCU SFSCLK_0: EPD Mask */ #define SCU_SFSCLK_0_EPUN_Pos 4 /*!< SCU SFSCLK_0: EPUN Position */ #define SCU_SFSCLK_0_EPUN_Msk (0x01UL << SCU_SFSCLK_0_EPUN_Pos) /*!< SCU SFSCLK_0: EPUN Mask */ #define SCU_SFSCLK_0_EHS_Pos 5 /*!< SCU SFSCLK_0: EHS Position */ #define SCU_SFSCLK_0_EHS_Msk (0x01UL << SCU_SFSCLK_0_EHS_Pos) /*!< SCU SFSCLK_0: EHS Mask */ #define SCU_SFSCLK_0_EZI_Pos 6 /*!< SCU SFSCLK_0: EZI Position */ #define SCU_SFSCLK_0_EZI_Msk (0x01UL << SCU_SFSCLK_0_EZI_Pos) /*!< SCU SFSCLK_0: EZI Mask */ #define SCU_SFSCLK_0_ZIF_Pos 7 /*!< SCU SFSCLK_0: ZIF Position */ #define SCU_SFSCLK_0_ZIF_Msk (0x01UL << SCU_SFSCLK_0_ZIF_Pos) /*!< SCU SFSCLK_0: ZIF Mask */ /* -------------------------------- SCU_SFSCLK_1 -------------------------------- */ #define SCU_SFSCLK_1_MODE_Pos 0 /*!< SCU SFSCLK_1: MODE Position */ #define SCU_SFSCLK_1_MODE_Msk (0x07UL << SCU_SFSCLK_1_MODE_Pos) /*!< SCU SFSCLK_1: MODE Mask */ #define SCU_SFSCLK_1_EPD_Pos 3 /*!< SCU SFSCLK_1: EPD Position */ #define SCU_SFSCLK_1_EPD_Msk (0x01UL << SCU_SFSCLK_1_EPD_Pos) /*!< SCU SFSCLK_1: EPD Mask */ #define SCU_SFSCLK_1_EPUN_Pos 4 /*!< SCU SFSCLK_1: EPUN Position */ #define SCU_SFSCLK_1_EPUN_Msk (0x01UL << SCU_SFSCLK_1_EPUN_Pos) /*!< SCU SFSCLK_1: EPUN Mask */ #define SCU_SFSCLK_1_EHS_Pos 5 /*!< SCU SFSCLK_1: EHS Position */ #define SCU_SFSCLK_1_EHS_Msk (0x01UL << SCU_SFSCLK_1_EHS_Pos) /*!< SCU SFSCLK_1: EHS Mask */ #define SCU_SFSCLK_1_EZI_Pos 6 /*!< SCU SFSCLK_1: EZI Position */ #define SCU_SFSCLK_1_EZI_Msk (0x01UL << SCU_SFSCLK_1_EZI_Pos) /*!< SCU SFSCLK_1: EZI Mask */ #define SCU_SFSCLK_1_ZIF_Pos 7 /*!< SCU SFSCLK_1: ZIF Position */ #define SCU_SFSCLK_1_ZIF_Msk (0x01UL << SCU_SFSCLK_1_ZIF_Pos) /*!< SCU SFSCLK_1: ZIF Mask */ /* -------------------------------- SCU_SFSCLK_2 -------------------------------- */ #define SCU_SFSCLK_2_MODE_Pos 0 /*!< SCU SFSCLK_2: MODE Position */ #define SCU_SFSCLK_2_MODE_Msk (0x07UL << SCU_SFSCLK_2_MODE_Pos) /*!< SCU SFSCLK_2: MODE Mask */ #define SCU_SFSCLK_2_EPD_Pos 3 /*!< SCU SFSCLK_2: EPD Position */ #define SCU_SFSCLK_2_EPD_Msk (0x01UL << SCU_SFSCLK_2_EPD_Pos) /*!< SCU SFSCLK_2: EPD Mask */ #define SCU_SFSCLK_2_EPUN_Pos 4 /*!< SCU SFSCLK_2: EPUN Position */ #define SCU_SFSCLK_2_EPUN_Msk (0x01UL << SCU_SFSCLK_2_EPUN_Pos) /*!< SCU SFSCLK_2: EPUN Mask */ #define SCU_SFSCLK_2_EHS_Pos 5 /*!< SCU SFSCLK_2: EHS Position */ #define SCU_SFSCLK_2_EHS_Msk (0x01UL << SCU_SFSCLK_2_EHS_Pos) /*!< SCU SFSCLK_2: EHS Mask */ #define SCU_SFSCLK_2_EZI_Pos 6 /*!< SCU SFSCLK_2: EZI Position */ #define SCU_SFSCLK_2_EZI_Msk (0x01UL << SCU_SFSCLK_2_EZI_Pos) /*!< SCU SFSCLK_2: EZI Mask */ #define SCU_SFSCLK_2_ZIF_Pos 7 /*!< SCU SFSCLK_2: ZIF Position */ #define SCU_SFSCLK_2_ZIF_Msk (0x01UL << SCU_SFSCLK_2_ZIF_Pos) /*!< SCU SFSCLK_2: ZIF Mask */ /* -------------------------------- SCU_SFSCLK_3 -------------------------------- */ #define SCU_SFSCLK_3_MODE_Pos 0 /*!< SCU SFSCLK_3: MODE Position */ #define SCU_SFSCLK_3_MODE_Msk (0x07UL << SCU_SFSCLK_3_MODE_Pos) /*!< SCU SFSCLK_3: MODE Mask */ #define SCU_SFSCLK_3_EPD_Pos 3 /*!< SCU SFSCLK_3: EPD Position */ #define SCU_SFSCLK_3_EPD_Msk (0x01UL << SCU_SFSCLK_3_EPD_Pos) /*!< SCU SFSCLK_3: EPD Mask */ #define SCU_SFSCLK_3_EPUN_Pos 4 /*!< SCU SFSCLK_3: EPUN Position */ #define SCU_SFSCLK_3_EPUN_Msk (0x01UL << SCU_SFSCLK_3_EPUN_Pos) /*!< SCU SFSCLK_3: EPUN Mask */ #define SCU_SFSCLK_3_EHS_Pos 5 /*!< SCU SFSCLK_3: EHS Position */ #define SCU_SFSCLK_3_EHS_Msk (0x01UL << SCU_SFSCLK_3_EHS_Pos) /*!< SCU SFSCLK_3: EHS Mask */ #define SCU_SFSCLK_3_EZI_Pos 6 /*!< SCU SFSCLK_3: EZI Position */ #define SCU_SFSCLK_3_EZI_Msk (0x01UL << SCU_SFSCLK_3_EZI_Pos) /*!< SCU SFSCLK_3: EZI Mask */ #define SCU_SFSCLK_3_ZIF_Pos 7 /*!< SCU SFSCLK_3: ZIF Position */ #define SCU_SFSCLK_3_ZIF_Msk (0x01UL << SCU_SFSCLK_3_ZIF_Pos) /*!< SCU SFSCLK_3: ZIF Mask */ /* --------------------------------- SCU_SFSUSB --------------------------------- */ #define SCU_SFSUSB_USB_AIM_Pos 0 /*!< SCU SFSUSB: USB_AIM Position */ #define SCU_SFSUSB_USB_AIM_Msk (0x01UL << SCU_SFSUSB_USB_AIM_Pos) /*!< SCU SFSUSB: USB_AIM Mask */ #define SCU_SFSUSB_USB_ESEA_Pos 1 /*!< SCU SFSUSB: USB_ESEA Position */ #define SCU_SFSUSB_USB_ESEA_Msk (0x01UL << SCU_SFSUSB_USB_ESEA_Pos) /*!< SCU SFSUSB: USB_ESEA Mask */ #define SCU_SFSUSB_USB_EPD_Pos 2 /*!< SCU SFSUSB: USB_EPD Position */ #define SCU_SFSUSB_USB_EPD_Msk (0x01UL << SCU_SFSUSB_USB_EPD_Pos) /*!< SCU SFSUSB: USB_EPD Mask */ #define SCU_SFSUSB_USB_EPWR_Pos 4 /*!< SCU SFSUSB: USB_EPWR Position */ #define SCU_SFSUSB_USB_EPWR_Msk (0x01UL << SCU_SFSUSB_USB_EPWR_Pos) /*!< SCU SFSUSB: USB_EPWR Mask */ #define SCU_SFSUSB_USB_VBUS_Pos 5 /*!< SCU SFSUSB: USB_VBUS Position */ #define SCU_SFSUSB_USB_VBUS_Msk (0x01UL << SCU_SFSUSB_USB_VBUS_Pos) /*!< SCU SFSUSB: USB_VBUS Mask */ /* --------------------------------- SCU_SFSI2C0 -------------------------------- */ #define SCU_SFSI2C0_SCL_EFP_Pos 0 /*!< SCU SFSI2C0: SCL_EFP Position */ #define SCU_SFSI2C0_SCL_EFP_Msk (0x01UL << SCU_SFSI2C0_SCL_EFP_Pos) /*!< SCU SFSI2C0: SCL_EFP Mask */ #define SCU_SFSI2C0_SCL_EHD_Pos 2 /*!< SCU SFSI2C0: SCL_EHD Position */ #define SCU_SFSI2C0_SCL_EHD_Msk (0x01UL << SCU_SFSI2C0_SCL_EHD_Pos) /*!< SCU SFSI2C0: SCL_EHD Mask */ #define SCU_SFSI2C0_SCL_EZI_Pos 3 /*!< SCU SFSI2C0: SCL_EZI Position */ #define SCU_SFSI2C0_SCL_EZI_Msk (0x01UL << SCU_SFSI2C0_SCL_EZI_Pos) /*!< SCU SFSI2C0: SCL_EZI Mask */ #define SCU_SFSI2C0_SCL_ZIF_Pos 7 /*!< SCU SFSI2C0: SCL_ZIF Position */ #define SCU_SFSI2C0_SCL_ZIF_Msk (0x01UL << SCU_SFSI2C0_SCL_ZIF_Pos) /*!< SCU SFSI2C0: SCL_ZIF Mask */ #define SCU_SFSI2C0_SDA_EFP_Pos 8 /*!< SCU SFSI2C0: SDA_EFP Position */ #define SCU_SFSI2C0_SDA_EFP_Msk (0x01UL << SCU_SFSI2C0_SDA_EFP_Pos) /*!< SCU SFSI2C0: SDA_EFP Mask */ #define SCU_SFSI2C0_SDA_EHD_Pos 10 /*!< SCU SFSI2C0: SDA_EHD Position */ #define SCU_SFSI2C0_SDA_EHD_Msk (0x01UL << SCU_SFSI2C0_SDA_EHD_Pos) /*!< SCU SFSI2C0: SDA_EHD Mask */ #define SCU_SFSI2C0_SDA_EZI_Pos 11 /*!< SCU SFSI2C0: SDA_EZI Position */ #define SCU_SFSI2C0_SDA_EZI_Msk (0x01UL << SCU_SFSI2C0_SDA_EZI_Pos) /*!< SCU SFSI2C0: SDA_EZI Mask */ #define SCU_SFSI2C0_SDA_ZIF_Pos 15 /*!< SCU SFSI2C0: SDA_ZIF Position */ #define SCU_SFSI2C0_SDA_ZIF_Msk (0x01UL << SCU_SFSI2C0_SDA_ZIF_Pos) /*!< SCU SFSI2C0: SDA_ZIF Mask */ /* --------------------------------- SCU_ENAIO0 --------------------------------- */ #define SCU_ENAIO0_ADC0_0_Pos 0 /*!< SCU ENAIO0: ADC0_0 Position */ #define SCU_ENAIO0_ADC0_0_Msk (0x01UL << SCU_ENAIO0_ADC0_0_Pos) /*!< SCU ENAIO0: ADC0_0 Mask */ #define SCU_ENAIO0_ADC0_1_Pos 1 /*!< SCU ENAIO0: ADC0_1 Position */ #define SCU_ENAIO0_ADC0_1_Msk (0x01UL << SCU_ENAIO0_ADC0_1_Pos) /*!< SCU ENAIO0: ADC0_1 Mask */ #define SCU_ENAIO0_ADC0_2_Pos 2 /*!< SCU ENAIO0: ADC0_2 Position */ #define SCU_ENAIO0_ADC0_2_Msk (0x01UL << SCU_ENAIO0_ADC0_2_Pos) /*!< SCU ENAIO0: ADC0_2 Mask */ #define SCU_ENAIO0_ADC0_3_Pos 3 /*!< SCU ENAIO0: ADC0_3 Position */ #define SCU_ENAIO0_ADC0_3_Msk (0x01UL << SCU_ENAIO0_ADC0_3_Pos) /*!< SCU ENAIO0: ADC0_3 Mask */ #define SCU_ENAIO0_ADC0_4_Pos 4 /*!< SCU ENAIO0: ADC0_4 Position */ #define SCU_ENAIO0_ADC0_4_Msk (0x01UL << SCU_ENAIO0_ADC0_4_Pos) /*!< SCU ENAIO0: ADC0_4 Mask */ #define SCU_ENAIO0_ADC0_5_Pos 5 /*!< SCU ENAIO0: ADC0_5 Position */ #define SCU_ENAIO0_ADC0_5_Msk (0x01UL << SCU_ENAIO0_ADC0_5_Pos) /*!< SCU ENAIO0: ADC0_5 Mask */ #define SCU_ENAIO0_ADC0_6_Pos 6 /*!< SCU ENAIO0: ADC0_6 Position */ #define SCU_ENAIO0_ADC0_6_Msk (0x01UL << SCU_ENAIO0_ADC0_6_Pos) /*!< SCU ENAIO0: ADC0_6 Mask */ /* --------------------------------- SCU_ENAIO1 --------------------------------- */ #define SCU_ENAIO1_ADC1_0_Pos 0 /*!< SCU ENAIO1: ADC1_0 Position */ #define SCU_ENAIO1_ADC1_0_Msk (0x01UL << SCU_ENAIO1_ADC1_0_Pos) /*!< SCU ENAIO1: ADC1_0 Mask */ #define SCU_ENAIO1_ADC1_1_Pos 1 /*!< SCU ENAIO1: ADC1_1 Position */ #define SCU_ENAIO1_ADC1_1_Msk (0x01UL << SCU_ENAIO1_ADC1_1_Pos) /*!< SCU ENAIO1: ADC1_1 Mask */ #define SCU_ENAIO1_ADC1_2_Pos 2 /*!< SCU ENAIO1: ADC1_2 Position */ #define SCU_ENAIO1_ADC1_2_Msk (0x01UL << SCU_ENAIO1_ADC1_2_Pos) /*!< SCU ENAIO1: ADC1_2 Mask */ #define SCU_ENAIO1_ADC1_3_Pos 3 /*!< SCU ENAIO1: ADC1_3 Position */ #define SCU_ENAIO1_ADC1_3_Msk (0x01UL << SCU_ENAIO1_ADC1_3_Pos) /*!< SCU ENAIO1: ADC1_3 Mask */ #define SCU_ENAIO1_ADC1_4_Pos 4 /*!< SCU ENAIO1: ADC1_4 Position */ #define SCU_ENAIO1_ADC1_4_Msk (0x01UL << SCU_ENAIO1_ADC1_4_Pos) /*!< SCU ENAIO1: ADC1_4 Mask */ #define SCU_ENAIO1_ADC1_5_Pos 5 /*!< SCU ENAIO1: ADC1_5 Position */ #define SCU_ENAIO1_ADC1_5_Msk (0x01UL << SCU_ENAIO1_ADC1_5_Pos) /*!< SCU ENAIO1: ADC1_5 Mask */ #define SCU_ENAIO1_ADC1_6_Pos 6 /*!< SCU ENAIO1: ADC1_6 Position */ #define SCU_ENAIO1_ADC1_6_Msk (0x01UL << SCU_ENAIO1_ADC1_6_Pos) /*!< SCU ENAIO1: ADC1_6 Mask */ #define SCU_ENAIO1_ADC1_7_Pos 7 /*!< SCU ENAIO1: ADC1_7 Position */ #define SCU_ENAIO1_ADC1_7_Msk (0x01UL << SCU_ENAIO1_ADC1_7_Pos) /*!< SCU ENAIO1: ADC1_7 Mask */ /* --------------------------------- SCU_ENAIO2 --------------------------------- */ #define SCU_ENAIO2_DAC_Pos 0 /*!< SCU ENAIO2: DAC Position */ #define SCU_ENAIO2_DAC_Msk (0x01UL << SCU_ENAIO2_DAC_Pos) /*!< SCU ENAIO2: DAC Mask */ #define SCU_ENAIO2_BG_Pos 4 /*!< SCU ENAIO2: BG Position */ #define SCU_ENAIO2_BG_Msk (0x01UL << SCU_ENAIO2_BG_Pos) /*!< SCU ENAIO2: BG Mask */ /* ------------------------------- SCU_EMCDELAYCLK ------------------------------ */ #define SCU_EMCDELAYCLK_CLK_DELAY_Pos 0 /*!< SCU EMCDELAYCLK: CLK_DELAY Position */ #define SCU_EMCDELAYCLK_CLK_DELAY_Msk (0x0000ffffUL << SCU_EMCDELAYCLK_CLK_DELAY_Pos) /*!< SCU EMCDELAYCLK: CLK_DELAY Mask */ /* --------------------------------- SCU_SDDELAY -------------------------------- */ #define SCU_SDDELAY_SAMPLE_DELAY_Pos 0 /*!< SCU SDDELAY: SAMPLE_DELAY Position */ #define SCU_SDDELAY_SAMPLE_DELAY_Msk (0x0fUL << SCU_SDDELAY_SAMPLE_DELAY_Pos) /*!< SCU SDDELAY: SAMPLE_DELAY Mask */ #define SCU_SDDELAY_DRV_DELAY_Pos 8 /*!< SCU SDDELAY: DRV_DELAY Position */ #define SCU_SDDELAY_DRV_DELAY_Msk (0x0fUL << SCU_SDDELAY_DRV_DELAY_Pos) /*!< SCU SDDELAY: DRV_DELAY Mask */ /* -------------------------------- SCU_PINTSEL0 -------------------------------- */ #define SCU_PINTSEL0_INTPIN0_Pos 0 /*!< SCU PINTSEL0: INTPIN0 Position */ #define SCU_PINTSEL0_INTPIN0_Msk (0x1fUL << SCU_PINTSEL0_INTPIN0_Pos) /*!< SCU PINTSEL0: INTPIN0 Mask */ #define SCU_PINTSEL0_PORTSEL0_Pos 5 /*!< SCU PINTSEL0: PORTSEL0 Position */ #define SCU_PINTSEL0_PORTSEL0_Msk (0x07UL << SCU_PINTSEL0_PORTSEL0_Pos) /*!< SCU PINTSEL0: PORTSEL0 Mask */ #define SCU_PINTSEL0_INTPIN1_Pos 8 /*!< SCU PINTSEL0: INTPIN1 Position */ #define SCU_PINTSEL0_INTPIN1_Msk (0x1fUL << SCU_PINTSEL0_INTPIN1_Pos) /*!< SCU PINTSEL0: INTPIN1 Mask */ #define SCU_PINTSEL0_PORTSEL1_Pos 13 /*!< SCU PINTSEL0: PORTSEL1 Position */ #define SCU_PINTSEL0_PORTSEL1_Msk (0x07UL << SCU_PINTSEL0_PORTSEL1_Pos) /*!< SCU PINTSEL0: PORTSEL1 Mask */ #define SCU_PINTSEL0_INTPIN2_Pos 16 /*!< SCU PINTSEL0: INTPIN2 Position */ #define SCU_PINTSEL0_INTPIN2_Msk (0x1fUL << SCU_PINTSEL0_INTPIN2_Pos) /*!< SCU PINTSEL0: INTPIN2 Mask */ #define SCU_PINTSEL0_PORTSEL2_Pos 21 /*!< SCU PINTSEL0: PORTSEL2 Position */ #define SCU_PINTSEL0_PORTSEL2_Msk (0x07UL << SCU_PINTSEL0_PORTSEL2_Pos) /*!< SCU PINTSEL0: PORTSEL2 Mask */ #define SCU_PINTSEL0_INTPIN3_Pos 24 /*!< SCU PINTSEL0: INTPIN3 Position */ #define SCU_PINTSEL0_INTPIN3_Msk (0x1fUL << SCU_PINTSEL0_INTPIN3_Pos) /*!< SCU PINTSEL0: INTPIN3 Mask */ #define SCU_PINTSEL0_PORTSEL3_Pos 29 /*!< SCU PINTSEL0: PORTSEL3 Position */ #define SCU_PINTSEL0_PORTSEL3_Msk (0x07UL << SCU_PINTSEL0_PORTSEL3_Pos) /*!< SCU PINTSEL0: PORTSEL3 Mask */ /* -------------------------------- SCU_PINTSEL1 -------------------------------- */ #define SCU_PINTSEL1_INTPIN4_Pos 0 /*!< SCU PINTSEL1: INTPIN4 Position */ #define SCU_PINTSEL1_INTPIN4_Msk (0x1fUL << SCU_PINTSEL1_INTPIN4_Pos) /*!< SCU PINTSEL1: INTPIN4 Mask */ #define SCU_PINTSEL1_PORTSEL4_Pos 5 /*!< SCU PINTSEL1: PORTSEL4 Position */ #define SCU_PINTSEL1_PORTSEL4_Msk (0x07UL << SCU_PINTSEL1_PORTSEL4_Pos) /*!< SCU PINTSEL1: PORTSEL4 Mask */ #define SCU_PINTSEL1_INTPIN5_Pos 8 /*!< SCU PINTSEL1: INTPIN5 Position */ #define SCU_PINTSEL1_INTPIN5_Msk (0x1fUL << SCU_PINTSEL1_INTPIN5_Pos) /*!< SCU PINTSEL1: INTPIN5 Mask */ #define SCU_PINTSEL1_PORTSEL5_Pos 13 /*!< SCU PINTSEL1: PORTSEL5 Position */ #define SCU_PINTSEL1_PORTSEL5_Msk (0x07UL << SCU_PINTSEL1_PORTSEL5_Pos) /*!< SCU PINTSEL1: PORTSEL5 Mask */ #define SCU_PINTSEL1_INTPIN6_Pos 16 /*!< SCU PINTSEL1: INTPIN6 Position */ #define SCU_PINTSEL1_INTPIN6_Msk (0x1fUL << SCU_PINTSEL1_INTPIN6_Pos) /*!< SCU PINTSEL1: INTPIN6 Mask */ #define SCU_PINTSEL1_PORTSEL6_Pos 21 /*!< SCU PINTSEL1: PORTSEL6 Position */ #define SCU_PINTSEL1_PORTSEL6_Msk (0x07UL << SCU_PINTSEL1_PORTSEL6_Pos) /*!< SCU PINTSEL1: PORTSEL6 Mask */ #define SCU_PINTSEL1_INTPIN7_Pos 24 /*!< SCU PINTSEL1: INTPIN7 Position */ #define SCU_PINTSEL1_INTPIN7_Msk (0x1fUL << SCU_PINTSEL1_INTPIN7_Pos) /*!< SCU PINTSEL1: INTPIN7 Mask */ #define SCU_PINTSEL1_PORTSEL7_Pos 29 /*!< SCU PINTSEL1: PORTSEL7 Position */ #define SCU_PINTSEL1_PORTSEL7_Msk (0x07UL << SCU_PINTSEL1_PORTSEL7_Pos) /*!< SCU PINTSEL1: PORTSEL7 Mask */ /* ================================================================================ */ /* ================ struct 'GPIO_PIN_INT' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------ GPIO_PIN_INT_ISEL ----------------------------- */ #define GPIO_PIN_INT_ISEL_PMODE0_Pos 0 /*!< GPIO_PIN_INT ISEL: PMODE0 Position */ #define GPIO_PIN_INT_ISEL_PMODE0_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE0_Pos) /*!< GPIO_PIN_INT ISEL: PMODE0 Mask */ #define GPIO_PIN_INT_ISEL_PMODE1_Pos 1 /*!< GPIO_PIN_INT ISEL: PMODE1 Position */ #define GPIO_PIN_INT_ISEL_PMODE1_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE1_Pos) /*!< GPIO_PIN_INT ISEL: PMODE1 Mask */ #define GPIO_PIN_INT_ISEL_PMODE2_Pos 2 /*!< GPIO_PIN_INT ISEL: PMODE2 Position */ #define GPIO_PIN_INT_ISEL_PMODE2_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE2_Pos) /*!< GPIO_PIN_INT ISEL: PMODE2 Mask */ #define GPIO_PIN_INT_ISEL_PMODE3_Pos 3 /*!< GPIO_PIN_INT ISEL: PMODE3 Position */ #define GPIO_PIN_INT_ISEL_PMODE3_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE3_Pos) /*!< GPIO_PIN_INT ISEL: PMODE3 Mask */ #define GPIO_PIN_INT_ISEL_PMODE4_Pos 4 /*!< GPIO_PIN_INT ISEL: PMODE4 Position */ #define GPIO_PIN_INT_ISEL_PMODE4_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE4_Pos) /*!< GPIO_PIN_INT ISEL: PMODE4 Mask */ #define GPIO_PIN_INT_ISEL_PMODE5_Pos 5 /*!< GPIO_PIN_INT ISEL: PMODE5 Position */ #define GPIO_PIN_INT_ISEL_PMODE5_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE5_Pos) /*!< GPIO_PIN_INT ISEL: PMODE5 Mask */ #define GPIO_PIN_INT_ISEL_PMODE6_Pos 6 /*!< GPIO_PIN_INT ISEL: PMODE6 Position */ #define GPIO_PIN_INT_ISEL_PMODE6_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE6_Pos) /*!< GPIO_PIN_INT ISEL: PMODE6 Mask */ #define GPIO_PIN_INT_ISEL_PMODE7_Pos 7 /*!< GPIO_PIN_INT ISEL: PMODE7 Position */ #define GPIO_PIN_INT_ISEL_PMODE7_Msk (0x01UL << GPIO_PIN_INT_ISEL_PMODE7_Pos) /*!< GPIO_PIN_INT ISEL: PMODE7 Mask */ /* ------------------------------ GPIO_PIN_INT_IENR ----------------------------- */ #define GPIO_PIN_INT_IENR_ENRL0_Pos 0 /*!< GPIO_PIN_INT IENR: ENRL0 Position */ #define GPIO_PIN_INT_IENR_ENRL0_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL0_Pos) /*!< GPIO_PIN_INT IENR: ENRL0 Mask */ #define GPIO_PIN_INT_IENR_ENRL1_Pos 1 /*!< GPIO_PIN_INT IENR: ENRL1 Position */ #define GPIO_PIN_INT_IENR_ENRL1_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL1_Pos) /*!< GPIO_PIN_INT IENR: ENRL1 Mask */ #define GPIO_PIN_INT_IENR_ENRL2_Pos 2 /*!< GPIO_PIN_INT IENR: ENRL2 Position */ #define GPIO_PIN_INT_IENR_ENRL2_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL2_Pos) /*!< GPIO_PIN_INT IENR: ENRL2 Mask */ #define GPIO_PIN_INT_IENR_ENRL3_Pos 3 /*!< GPIO_PIN_INT IENR: ENRL3 Position */ #define GPIO_PIN_INT_IENR_ENRL3_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL3_Pos) /*!< GPIO_PIN_INT IENR: ENRL3 Mask */ #define GPIO_PIN_INT_IENR_ENRL4_Pos 4 /*!< GPIO_PIN_INT IENR: ENRL4 Position */ #define GPIO_PIN_INT_IENR_ENRL4_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL4_Pos) /*!< GPIO_PIN_INT IENR: ENRL4 Mask */ #define GPIO_PIN_INT_IENR_ENRL5_Pos 5 /*!< GPIO_PIN_INT IENR: ENRL5 Position */ #define GPIO_PIN_INT_IENR_ENRL5_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL5_Pos) /*!< GPIO_PIN_INT IENR: ENRL5 Mask */ #define GPIO_PIN_INT_IENR_ENRL6_Pos 6 /*!< GPIO_PIN_INT IENR: ENRL6 Position */ #define GPIO_PIN_INT_IENR_ENRL6_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL6_Pos) /*!< GPIO_PIN_INT IENR: ENRL6 Mask */ #define GPIO_PIN_INT_IENR_ENRL7_Pos 7 /*!< GPIO_PIN_INT IENR: ENRL7 Position */ #define GPIO_PIN_INT_IENR_ENRL7_Msk (0x01UL << GPIO_PIN_INT_IENR_ENRL7_Pos) /*!< GPIO_PIN_INT IENR: ENRL7 Mask */ /* ----------------------------- GPIO_PIN_INT_SIENR ----------------------------- */ #define GPIO_PIN_INT_SIENR_SETENRL0_Pos 0 /*!< GPIO_PIN_INT SIENR: SETENRL0 Position */ #define GPIO_PIN_INT_SIENR_SETENRL0_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL0_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL0 Mask */ #define GPIO_PIN_INT_SIENR_SETENRL1_Pos 1 /*!< GPIO_PIN_INT SIENR: SETENRL1 Position */ #define GPIO_PIN_INT_SIENR_SETENRL1_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL1_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL1 Mask */ #define GPIO_PIN_INT_SIENR_SETENRL2_Pos 2 /*!< GPIO_PIN_INT SIENR: SETENRL2 Position */ #define GPIO_PIN_INT_SIENR_SETENRL2_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL2_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL2 Mask */ #define GPIO_PIN_INT_SIENR_SETENRL3_Pos 3 /*!< GPIO_PIN_INT SIENR: SETENRL3 Position */ #define GPIO_PIN_INT_SIENR_SETENRL3_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL3_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL3 Mask */ #define GPIO_PIN_INT_SIENR_SETENRL4_Pos 4 /*!< GPIO_PIN_INT SIENR: SETENRL4 Position */ #define GPIO_PIN_INT_SIENR_SETENRL4_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL4_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL4 Mask */ #define GPIO_PIN_INT_SIENR_SETENRL5_Pos 5 /*!< GPIO_PIN_INT SIENR: SETENRL5 Position */ #define GPIO_PIN_INT_SIENR_SETENRL5_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL5_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL5 Mask */ #define GPIO_PIN_INT_SIENR_SETENRL6_Pos 6 /*!< GPIO_PIN_INT SIENR: SETENRL6 Position */ #define GPIO_PIN_INT_SIENR_SETENRL6_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL6_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL6 Mask */ #define GPIO_PIN_INT_SIENR_SETENRL7_Pos 7 /*!< GPIO_PIN_INT SIENR: SETENRL7 Position */ #define GPIO_PIN_INT_SIENR_SETENRL7_Msk (0x01UL << GPIO_PIN_INT_SIENR_SETENRL7_Pos) /*!< GPIO_PIN_INT SIENR: SETENRL7 Mask */ /* ----------------------------- GPIO_PIN_INT_CIENR ----------------------------- */ #define GPIO_PIN_INT_CIENR_CENRL0_Pos 0 /*!< GPIO_PIN_INT CIENR: CENRL0 Position */ #define GPIO_PIN_INT_CIENR_CENRL0_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL0_Pos) /*!< GPIO_PIN_INT CIENR: CENRL0 Mask */ #define GPIO_PIN_INT_CIENR_CENRL1_Pos 1 /*!< GPIO_PIN_INT CIENR: CENRL1 Position */ #define GPIO_PIN_INT_CIENR_CENRL1_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL1_Pos) /*!< GPIO_PIN_INT CIENR: CENRL1 Mask */ #define GPIO_PIN_INT_CIENR_CENRL2_Pos 2 /*!< GPIO_PIN_INT CIENR: CENRL2 Position */ #define GPIO_PIN_INT_CIENR_CENRL2_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL2_Pos) /*!< GPIO_PIN_INT CIENR: CENRL2 Mask */ #define GPIO_PIN_INT_CIENR_CENRL3_Pos 3 /*!< GPIO_PIN_INT CIENR: CENRL3 Position */ #define GPIO_PIN_INT_CIENR_CENRL3_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL3_Pos) /*!< GPIO_PIN_INT CIENR: CENRL3 Mask */ #define GPIO_PIN_INT_CIENR_CENRL4_Pos 4 /*!< GPIO_PIN_INT CIENR: CENRL4 Position */ #define GPIO_PIN_INT_CIENR_CENRL4_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL4_Pos) /*!< GPIO_PIN_INT CIENR: CENRL4 Mask */ #define GPIO_PIN_INT_CIENR_CENRL5_Pos 5 /*!< GPIO_PIN_INT CIENR: CENRL5 Position */ #define GPIO_PIN_INT_CIENR_CENRL5_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL5_Pos) /*!< GPIO_PIN_INT CIENR: CENRL5 Mask */ #define GPIO_PIN_INT_CIENR_CENRL6_Pos 6 /*!< GPIO_PIN_INT CIENR: CENRL6 Position */ #define GPIO_PIN_INT_CIENR_CENRL6_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL6_Pos) /*!< GPIO_PIN_INT CIENR: CENRL6 Mask */ #define GPIO_PIN_INT_CIENR_CENRL7_Pos 7 /*!< GPIO_PIN_INT CIENR: CENRL7 Position */ #define GPIO_PIN_INT_CIENR_CENRL7_Msk (0x01UL << GPIO_PIN_INT_CIENR_CENRL7_Pos) /*!< GPIO_PIN_INT CIENR: CENRL7 Mask */ /* ------------------------------ GPIO_PIN_INT_IENF ----------------------------- */ #define GPIO_PIN_INT_IENF_ENAF0_Pos 0 /*!< GPIO_PIN_INT IENF: ENAF0 Position */ #define GPIO_PIN_INT_IENF_ENAF0_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF0_Pos) /*!< GPIO_PIN_INT IENF: ENAF0 Mask */ #define GPIO_PIN_INT_IENF_ENAF1_Pos 1 /*!< GPIO_PIN_INT IENF: ENAF1 Position */ #define GPIO_PIN_INT_IENF_ENAF1_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF1_Pos) /*!< GPIO_PIN_INT IENF: ENAF1 Mask */ #define GPIO_PIN_INT_IENF_ENAF2_Pos 2 /*!< GPIO_PIN_INT IENF: ENAF2 Position */ #define GPIO_PIN_INT_IENF_ENAF2_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF2_Pos) /*!< GPIO_PIN_INT IENF: ENAF2 Mask */ #define GPIO_PIN_INT_IENF_ENAF3_Pos 3 /*!< GPIO_PIN_INT IENF: ENAF3 Position */ #define GPIO_PIN_INT_IENF_ENAF3_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF3_Pos) /*!< GPIO_PIN_INT IENF: ENAF3 Mask */ #define GPIO_PIN_INT_IENF_ENAF4_Pos 4 /*!< GPIO_PIN_INT IENF: ENAF4 Position */ #define GPIO_PIN_INT_IENF_ENAF4_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF4_Pos) /*!< GPIO_PIN_INT IENF: ENAF4 Mask */ #define GPIO_PIN_INT_IENF_ENAF5_Pos 5 /*!< GPIO_PIN_INT IENF: ENAF5 Position */ #define GPIO_PIN_INT_IENF_ENAF5_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF5_Pos) /*!< GPIO_PIN_INT IENF: ENAF5 Mask */ #define GPIO_PIN_INT_IENF_ENAF6_Pos 6 /*!< GPIO_PIN_INT IENF: ENAF6 Position */ #define GPIO_PIN_INT_IENF_ENAF6_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF6_Pos) /*!< GPIO_PIN_INT IENF: ENAF6 Mask */ #define GPIO_PIN_INT_IENF_ENAF7_Pos 7 /*!< GPIO_PIN_INT IENF: ENAF7 Position */ #define GPIO_PIN_INT_IENF_ENAF7_Msk (0x01UL << GPIO_PIN_INT_IENF_ENAF7_Pos) /*!< GPIO_PIN_INT IENF: ENAF7 Mask */ /* ----------------------------- GPIO_PIN_INT_SIENF ----------------------------- */ #define GPIO_PIN_INT_SIENF_SETENAF0_Pos 0 /*!< GPIO_PIN_INT SIENF: SETENAF0 Position */ #define GPIO_PIN_INT_SIENF_SETENAF0_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF0_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF0 Mask */ #define GPIO_PIN_INT_SIENF_SETENAF1_Pos 1 /*!< GPIO_PIN_INT SIENF: SETENAF1 Position */ #define GPIO_PIN_INT_SIENF_SETENAF1_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF1_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF1 Mask */ #define GPIO_PIN_INT_SIENF_SETENAF2_Pos 2 /*!< GPIO_PIN_INT SIENF: SETENAF2 Position */ #define GPIO_PIN_INT_SIENF_SETENAF2_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF2_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF2 Mask */ #define GPIO_PIN_INT_SIENF_SETENAF3_Pos 3 /*!< GPIO_PIN_INT SIENF: SETENAF3 Position */ #define GPIO_PIN_INT_SIENF_SETENAF3_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF3_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF3 Mask */ #define GPIO_PIN_INT_SIENF_SETENAF4_Pos 4 /*!< GPIO_PIN_INT SIENF: SETENAF4 Position */ #define GPIO_PIN_INT_SIENF_SETENAF4_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF4_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF4 Mask */ #define GPIO_PIN_INT_SIENF_SETENAF5_Pos 5 /*!< GPIO_PIN_INT SIENF: SETENAF5 Position */ #define GPIO_PIN_INT_SIENF_SETENAF5_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF5_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF5 Mask */ #define GPIO_PIN_INT_SIENF_SETENAF6_Pos 6 /*!< GPIO_PIN_INT SIENF: SETENAF6 Position */ #define GPIO_PIN_INT_SIENF_SETENAF6_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF6_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF6 Mask */ #define GPIO_PIN_INT_SIENF_SETENAF7_Pos 7 /*!< GPIO_PIN_INT SIENF: SETENAF7 Position */ #define GPIO_PIN_INT_SIENF_SETENAF7_Msk (0x01UL << GPIO_PIN_INT_SIENF_SETENAF7_Pos) /*!< GPIO_PIN_INT SIENF: SETENAF7 Mask */ /* ----------------------------- GPIO_PIN_INT_CIENF ----------------------------- */ #define GPIO_PIN_INT_CIENF_CENAF0_Pos 0 /*!< GPIO_PIN_INT CIENF: CENAF0 Position */ #define GPIO_PIN_INT_CIENF_CENAF0_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF0_Pos) /*!< GPIO_PIN_INT CIENF: CENAF0 Mask */ #define GPIO_PIN_INT_CIENF_CENAF1_Pos 1 /*!< GPIO_PIN_INT CIENF: CENAF1 Position */ #define GPIO_PIN_INT_CIENF_CENAF1_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF1_Pos) /*!< GPIO_PIN_INT CIENF: CENAF1 Mask */ #define GPIO_PIN_INT_CIENF_CENAF2_Pos 2 /*!< GPIO_PIN_INT CIENF: CENAF2 Position */ #define GPIO_PIN_INT_CIENF_CENAF2_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF2_Pos) /*!< GPIO_PIN_INT CIENF: CENAF2 Mask */ #define GPIO_PIN_INT_CIENF_CENAF3_Pos 3 /*!< GPIO_PIN_INT CIENF: CENAF3 Position */ #define GPIO_PIN_INT_CIENF_CENAF3_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF3_Pos) /*!< GPIO_PIN_INT CIENF: CENAF3 Mask */ #define GPIO_PIN_INT_CIENF_CENAF4_Pos 4 /*!< GPIO_PIN_INT CIENF: CENAF4 Position */ #define GPIO_PIN_INT_CIENF_CENAF4_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF4_Pos) /*!< GPIO_PIN_INT CIENF: CENAF4 Mask */ #define GPIO_PIN_INT_CIENF_CENAF5_Pos 5 /*!< GPIO_PIN_INT CIENF: CENAF5 Position */ #define GPIO_PIN_INT_CIENF_CENAF5_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF5_Pos) /*!< GPIO_PIN_INT CIENF: CENAF5 Mask */ #define GPIO_PIN_INT_CIENF_CENAF6_Pos 6 /*!< GPIO_PIN_INT CIENF: CENAF6 Position */ #define GPIO_PIN_INT_CIENF_CENAF6_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF6_Pos) /*!< GPIO_PIN_INT CIENF: CENAF6 Mask */ #define GPIO_PIN_INT_CIENF_CENAF7_Pos 7 /*!< GPIO_PIN_INT CIENF: CENAF7 Position */ #define GPIO_PIN_INT_CIENF_CENAF7_Msk (0x01UL << GPIO_PIN_INT_CIENF_CENAF7_Pos) /*!< GPIO_PIN_INT CIENF: CENAF7 Mask */ /* ------------------------------ GPIO_PIN_INT_RISE ----------------------------- */ #define GPIO_PIN_INT_RISE_RDET0_Pos 0 /*!< GPIO_PIN_INT RISE: RDET0 Position */ #define GPIO_PIN_INT_RISE_RDET0_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET0_Pos) /*!< GPIO_PIN_INT RISE: RDET0 Mask */ #define GPIO_PIN_INT_RISE_RDET1_Pos 1 /*!< GPIO_PIN_INT RISE: RDET1 Position */ #define GPIO_PIN_INT_RISE_RDET1_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET1_Pos) /*!< GPIO_PIN_INT RISE: RDET1 Mask */ #define GPIO_PIN_INT_RISE_RDET2_Pos 2 /*!< GPIO_PIN_INT RISE: RDET2 Position */ #define GPIO_PIN_INT_RISE_RDET2_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET2_Pos) /*!< GPIO_PIN_INT RISE: RDET2 Mask */ #define GPIO_PIN_INT_RISE_RDET3_Pos 3 /*!< GPIO_PIN_INT RISE: RDET3 Position */ #define GPIO_PIN_INT_RISE_RDET3_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET3_Pos) /*!< GPIO_PIN_INT RISE: RDET3 Mask */ #define GPIO_PIN_INT_RISE_RDET4_Pos 4 /*!< GPIO_PIN_INT RISE: RDET4 Position */ #define GPIO_PIN_INT_RISE_RDET4_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET4_Pos) /*!< GPIO_PIN_INT RISE: RDET4 Mask */ #define GPIO_PIN_INT_RISE_RDET5_Pos 5 /*!< GPIO_PIN_INT RISE: RDET5 Position */ #define GPIO_PIN_INT_RISE_RDET5_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET5_Pos) /*!< GPIO_PIN_INT RISE: RDET5 Mask */ #define GPIO_PIN_INT_RISE_RDET6_Pos 6 /*!< GPIO_PIN_INT RISE: RDET6 Position */ #define GPIO_PIN_INT_RISE_RDET6_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET6_Pos) /*!< GPIO_PIN_INT RISE: RDET6 Mask */ #define GPIO_PIN_INT_RISE_RDET7_Pos 7 /*!< GPIO_PIN_INT RISE: RDET7 Position */ #define GPIO_PIN_INT_RISE_RDET7_Msk (0x01UL << GPIO_PIN_INT_RISE_RDET7_Pos) /*!< GPIO_PIN_INT RISE: RDET7 Mask */ /* ------------------------------ GPIO_PIN_INT_FALL ----------------------------- */ #define GPIO_PIN_INT_FALL_FDET0_Pos 0 /*!< GPIO_PIN_INT FALL: FDET0 Position */ #define GPIO_PIN_INT_FALL_FDET0_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET0_Pos) /*!< GPIO_PIN_INT FALL: FDET0 Mask */ #define GPIO_PIN_INT_FALL_FDET1_Pos 1 /*!< GPIO_PIN_INT FALL: FDET1 Position */ #define GPIO_PIN_INT_FALL_FDET1_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET1_Pos) /*!< GPIO_PIN_INT FALL: FDET1 Mask */ #define GPIO_PIN_INT_FALL_FDET2_Pos 2 /*!< GPIO_PIN_INT FALL: FDET2 Position */ #define GPIO_PIN_INT_FALL_FDET2_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET2_Pos) /*!< GPIO_PIN_INT FALL: FDET2 Mask */ #define GPIO_PIN_INT_FALL_FDET3_Pos 3 /*!< GPIO_PIN_INT FALL: FDET3 Position */ #define GPIO_PIN_INT_FALL_FDET3_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET3_Pos) /*!< GPIO_PIN_INT FALL: FDET3 Mask */ #define GPIO_PIN_INT_FALL_FDET4_Pos 4 /*!< GPIO_PIN_INT FALL: FDET4 Position */ #define GPIO_PIN_INT_FALL_FDET4_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET4_Pos) /*!< GPIO_PIN_INT FALL: FDET4 Mask */ #define GPIO_PIN_INT_FALL_FDET5_Pos 5 /*!< GPIO_PIN_INT FALL: FDET5 Position */ #define GPIO_PIN_INT_FALL_FDET5_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET5_Pos) /*!< GPIO_PIN_INT FALL: FDET5 Mask */ #define GPIO_PIN_INT_FALL_FDET6_Pos 6 /*!< GPIO_PIN_INT FALL: FDET6 Position */ #define GPIO_PIN_INT_FALL_FDET6_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET6_Pos) /*!< GPIO_PIN_INT FALL: FDET6 Mask */ #define GPIO_PIN_INT_FALL_FDET7_Pos 7 /*!< GPIO_PIN_INT FALL: FDET7 Position */ #define GPIO_PIN_INT_FALL_FDET7_Msk (0x01UL << GPIO_PIN_INT_FALL_FDET7_Pos) /*!< GPIO_PIN_INT FALL: FDET7 Mask */ /* ------------------------------ GPIO_PIN_INT_IST ------------------------------ */ #define GPIO_PIN_INT_IST_PSTAT0_Pos 0 /*!< GPIO_PIN_INT IST: PSTAT0 Position */ #define GPIO_PIN_INT_IST_PSTAT0_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT0_Pos) /*!< GPIO_PIN_INT IST: PSTAT0 Mask */ #define GPIO_PIN_INT_IST_PSTAT1_Pos 1 /*!< GPIO_PIN_INT IST: PSTAT1 Position */ #define GPIO_PIN_INT_IST_PSTAT1_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT1_Pos) /*!< GPIO_PIN_INT IST: PSTAT1 Mask */ #define GPIO_PIN_INT_IST_PSTAT2_Pos 2 /*!< GPIO_PIN_INT IST: PSTAT2 Position */ #define GPIO_PIN_INT_IST_PSTAT2_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT2_Pos) /*!< GPIO_PIN_INT IST: PSTAT2 Mask */ #define GPIO_PIN_INT_IST_PSTAT3_Pos 3 /*!< GPIO_PIN_INT IST: PSTAT3 Position */ #define GPIO_PIN_INT_IST_PSTAT3_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT3_Pos) /*!< GPIO_PIN_INT IST: PSTAT3 Mask */ #define GPIO_PIN_INT_IST_PSTAT4_Pos 4 /*!< GPIO_PIN_INT IST: PSTAT4 Position */ #define GPIO_PIN_INT_IST_PSTAT4_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT4_Pos) /*!< GPIO_PIN_INT IST: PSTAT4 Mask */ #define GPIO_PIN_INT_IST_PSTAT5_Pos 5 /*!< GPIO_PIN_INT IST: PSTAT5 Position */ #define GPIO_PIN_INT_IST_PSTAT5_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT5_Pos) /*!< GPIO_PIN_INT IST: PSTAT5 Mask */ #define GPIO_PIN_INT_IST_PSTAT6_Pos 6 /*!< GPIO_PIN_INT IST: PSTAT6 Position */ #define GPIO_PIN_INT_IST_PSTAT6_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT6_Pos) /*!< GPIO_PIN_INT IST: PSTAT6 Mask */ #define GPIO_PIN_INT_IST_PSTAT7_Pos 7 /*!< GPIO_PIN_INT IST: PSTAT7 Position */ #define GPIO_PIN_INT_IST_PSTAT7_Msk (0x01UL << GPIO_PIN_INT_IST_PSTAT7_Pos) /*!< GPIO_PIN_INT IST: PSTAT7 Mask */ /* ================================================================================ */ /* ================ Group 'GPIO_GROUP_INTn' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------- GPIO_GROUP_INTn_CTRL ---------------------------- */ #define GPIO_GROUP_INTn_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INTn CTRL: INT Position */ #define GPIO_GROUP_INTn_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_INT_Pos) /*!< GPIO_GROUP_INTn CTRL: INT Mask */ #define GPIO_GROUP_INTn_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INTn CTRL: COMB Position */ #define GPIO_GROUP_INTn_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_COMB_Pos) /*!< GPIO_GROUP_INTn CTRL: COMB Mask */ #define GPIO_GROUP_INTn_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INTn CTRL: TRIG Position */ #define GPIO_GROUP_INTn_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INTn_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INTn CTRL: TRIG Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_POL0 ------------------------- */ #define GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_0 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_1 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_2 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_3 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_4 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_5 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_6 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_7 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_8 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_9 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_10 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_11 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_12 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_13 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_14 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_15 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_16 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_17 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_18 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_19 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_20 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_21 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_22 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_23 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_24 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_25 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_26 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_27 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_28 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_29 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_30 Mask */ #define GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Position */ #define GPIO_GROUP_INTn_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL0: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_POL1 ------------------------- */ #define GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_0 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_1 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_2 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_3 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_4 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_5 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_6 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_7 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_8 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_9 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_10 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_11 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_12 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_13 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_14 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_15 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_16 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_17 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_18 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_19 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_20 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_21 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_22 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_23 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_24 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_25 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_26 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_27 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_28 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_29 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_30 Mask */ #define GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Position */ #define GPIO_GROUP_INTn_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL1: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_POL2 ------------------------- */ #define GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_0 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_1 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_2 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_3 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_4 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_5 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_6 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_7 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_8 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_9 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_10 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_11 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_12 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_13 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_14 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_15 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_16 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_17 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_18 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_19 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_20 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_21 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_22 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_23 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_24 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_25 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_26 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_27 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_28 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_29 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_30 Mask */ #define GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Position */ #define GPIO_GROUP_INTn_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL2: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_POL3 ------------------------- */ #define GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_0 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_1 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_2 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_3 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_4 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_5 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_6 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_7 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_8 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_9 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_10 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_11 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_12 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_13 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_14 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_15 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_16 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_17 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_18 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_19 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_20 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_21 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_22 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_23 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_24 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_25 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_26 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_27 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_28 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_29 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_30 Mask */ #define GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Position */ #define GPIO_GROUP_INTn_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL3: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_POL4 ------------------------- */ #define GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_0 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_1 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_2 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_3 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_4 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_5 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_6 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_7 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_8 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_9 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_10 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_11 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_12 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_13 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_14 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_15 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_16 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_17 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_18 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_19 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_20 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_21 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_22 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_23 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_24 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_25 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_26 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_27 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_28 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_29 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_30 Mask */ #define GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Position */ #define GPIO_GROUP_INTn_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL4: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_POL5 ------------------------- */ #define GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_0 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_1 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_2 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_3 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_4 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_5 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_6 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_7 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_8 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_9 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_10 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_11 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_12 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_13 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_14 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_15 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_16 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_17 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_18 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_19 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_20 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_21 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_22 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_23 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_24 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_25 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_26 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_27 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_28 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_29 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_30 Mask */ #define GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Position */ #define GPIO_GROUP_INTn_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL5: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_POL6 ------------------------- */ #define GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_0 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_1 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_2 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_3 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_4 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_5 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_6 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_7 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_8 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_9 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_10 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_11 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_12 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_13 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_14 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_15 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_16 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_17 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_18 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_19 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_20 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_21 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_22 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_23 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_24 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_25 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_26 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_27 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_28 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_29 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_30 Mask */ #define GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Position */ #define GPIO_GROUP_INTn_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL6: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_POL7 ------------------------- */ #define GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_0 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_1 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_2 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_3 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_4 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_5 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_6 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_7 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_8 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_9 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_10 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_11 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_12 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_13 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_14 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_15 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_16 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_17 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_18 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_19 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_20 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_21 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_22 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_23 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_24 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_25 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_26 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_27 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_28 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_29 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_30 Mask */ #define GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Position */ #define GPIO_GROUP_INTn_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INTn PORT_POL7: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_ENA0 ------------------------- */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_0 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_1 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_2 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_3 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_4 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_5 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_6 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_7 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_8 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_9 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_10 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_11 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_12 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_13 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_14 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_15 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_16 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_17 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_18 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_19 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_20 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_21 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_22 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_23 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_24 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_25 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_26 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_27 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_28 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_29 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_30 Mask */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Position */ #define GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA0: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_ENA1 ------------------------- */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_0 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_1 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_2 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_3 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_4 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_5 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_6 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_7 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_8 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_9 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_10 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_11 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_12 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_13 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_14 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_15 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_16 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_17 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_18 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_19 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_20 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_21 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_22 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_23 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_24 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_25 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_26 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_27 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_28 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_29 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_30 Mask */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Position */ #define GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA1: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_ENA2 ------------------------- */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_0 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_1 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_2 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_3 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_4 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_5 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_6 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_7 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_8 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_9 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_10 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_11 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_12 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_13 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_14 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_15 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_16 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_17 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_18 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_19 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_20 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_21 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_22 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_23 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_24 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_25 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_26 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_27 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_28 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_29 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_30 Mask */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Position */ #define GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA2: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_ENA3 ------------------------- */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_0 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_1 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_2 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_3 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_4 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_5 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_6 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_7 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_8 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_9 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_10 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_11 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_12 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_13 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_14 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_15 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_16 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_17 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_18 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_19 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_20 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_21 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_22 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_23 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_24 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_25 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_26 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_27 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_28 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_29 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_30 Mask */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Position */ #define GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA3: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_ENA4 ------------------------- */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_0 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_1 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_2 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_3 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_4 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_5 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_6 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_7 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_8 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_9 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_10 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_11 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_12 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_13 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_14 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_15 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_16 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_17 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_18 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_19 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_20 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_21 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_22 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_23 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_24 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_25 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_26 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_27 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_28 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_29 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_30 Mask */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Position */ #define GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA4: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_ENA5 ------------------------- */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_0 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_1 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_2 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_3 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_4 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_5 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_6 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_7 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_8 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_9 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_10 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_11 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_12 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_13 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_14 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_15 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_16 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_17 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_18 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_19 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_20 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_21 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_22 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_23 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_24 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_25 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_26 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_27 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_28 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_29 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_30 Mask */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Position */ #define GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA5: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_ENA6 ------------------------- */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_0 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_1 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_2 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_3 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_4 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_5 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_6 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_7 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_8 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_9 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_10 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_11 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_12 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_13 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_14 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_15 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_16 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_17 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_18 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_19 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_20 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_21 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_22 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_23 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_24 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_25 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_26 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_27 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_28 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_29 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_30 Mask */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Position */ #define GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA6: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INTn_PORT_ENA7 ------------------------- */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_0 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_1 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_2 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_3 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_4 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_5 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_6 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_7 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_8 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_9 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_10 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_11 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_12 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_13 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_14 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_15 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_16 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_17 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_18 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_19 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_20 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_21 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_22 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_23 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_24 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_25 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_26 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_27 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_28 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_29 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_30 Mask */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Position */ #define GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INTn_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INTn PORT_ENA7: ENA_31 Mask */ /* ================================================================================ */ /* ================ struct 'GPIO_GROUP_INT0' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------- GPIO_GROUP_INT0_CTRL ---------------------------- */ #define GPIO_GROUP_INT0_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT0 CTRL: INT Position */ #define GPIO_GROUP_INT0_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT0_CTRL_INT_Pos) /*!< GPIO_GROUP_INT0 CTRL: INT Mask */ #define GPIO_GROUP_INT0_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT0 CTRL: COMB Position */ #define GPIO_GROUP_INT0_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT0_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT0 CTRL: COMB Mask */ #define GPIO_GROUP_INT0_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT0 CTRL: TRIG Position */ #define GPIO_GROUP_INT0_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT0_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT0 CTRL: TRIG Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_POL0 ------------------------- */ #define GPIO_GROUP_INT0_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_0 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_0 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_1 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_1 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_2 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_2 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_3 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_3 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_4 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_4 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_5 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_5 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_6 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_6 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_7 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_7 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_8 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_8 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_9 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_9 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_10 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_10 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_11 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_11 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_12 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_12 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_13 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_13 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_14 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_14 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_15 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_15 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_16 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_16 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_17 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_17 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_18 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_18 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_19 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_19 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_20 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_20 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_21 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_21 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_22 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_22 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_23 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_23 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_24 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_24 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_25 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_25 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_26 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_26 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_27 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_27 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_28 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_28 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_29 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_29 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_30 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_30 Mask */ #define GPIO_GROUP_INT0_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL0: POL_31 Position */ #define GPIO_GROUP_INT0_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL0: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_POL1 ------------------------- */ #define GPIO_GROUP_INT0_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_0 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_0 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_1 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_1 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_2 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_2 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_3 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_3 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_4 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_4 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_5 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_5 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_6 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_6 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_7 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_7 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_8 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_8 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_9 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_9 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_10 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_10 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_11 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_11 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_12 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_12 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_13 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_13 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_14 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_14 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_15 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_15 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_16 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_16 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_17 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_17 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_18 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_18 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_19 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_19 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_20 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_20 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_21 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_21 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_22 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_22 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_23 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_23 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_24 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_24 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_25 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_25 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_26 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_26 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_27 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_27 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_28 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_28 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_29 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_29 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_30 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_30 Mask */ #define GPIO_GROUP_INT0_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL1: POL_31 Position */ #define GPIO_GROUP_INT0_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL1: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_POL2 ------------------------- */ #define GPIO_GROUP_INT0_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_0 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_0 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_1 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_1 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_2 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_2 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_3 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_3 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_4 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_4 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_5 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_5 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_6 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_6 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_7 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_7 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_8 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_8 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_9 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_9 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_10 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_10 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_11 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_11 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_12 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_12 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_13 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_13 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_14 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_14 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_15 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_15 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_16 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_16 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_17 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_17 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_18 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_18 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_19 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_19 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_20 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_20 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_21 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_21 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_22 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_22 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_23 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_23 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_24 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_24 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_25 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_25 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_26 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_26 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_27 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_27 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_28 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_28 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_29 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_29 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_30 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_30 Mask */ #define GPIO_GROUP_INT0_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL2: POL_31 Position */ #define GPIO_GROUP_INT0_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL2: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_POL3 ------------------------- */ #define GPIO_GROUP_INT0_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_0 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_0 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_1 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_1 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_2 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_2 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_3 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_3 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_4 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_4 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_5 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_5 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_6 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_6 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_7 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_7 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_8 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_8 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_9 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_9 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_10 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_10 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_11 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_11 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_12 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_12 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_13 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_13 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_14 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_14 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_15 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_15 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_16 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_16 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_17 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_17 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_18 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_18 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_19 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_19 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_20 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_20 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_21 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_21 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_22 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_22 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_23 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_23 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_24 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_24 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_25 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_25 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_26 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_26 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_27 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_27 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_28 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_28 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_29 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_29 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_30 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_30 Mask */ #define GPIO_GROUP_INT0_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL3: POL_31 Position */ #define GPIO_GROUP_INT0_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL3: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_POL4 ------------------------- */ #define GPIO_GROUP_INT0_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_0 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_0 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_1 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_1 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_2 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_2 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_3 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_3 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_4 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_4 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_5 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_5 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_6 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_6 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_7 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_7 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_8 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_8 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_9 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_9 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_10 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_10 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_11 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_11 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_12 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_12 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_13 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_13 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_14 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_14 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_15 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_15 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_16 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_16 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_17 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_17 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_18 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_18 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_19 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_19 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_20 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_20 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_21 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_21 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_22 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_22 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_23 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_23 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_24 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_24 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_25 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_25 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_26 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_26 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_27 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_27 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_28 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_28 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_29 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_29 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_30 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_30 Mask */ #define GPIO_GROUP_INT0_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL4: POL_31 Position */ #define GPIO_GROUP_INT0_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL4: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_POL5 ------------------------- */ #define GPIO_GROUP_INT0_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_0 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_0 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_1 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_1 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_2 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_2 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_3 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_3 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_4 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_4 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_5 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_5 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_6 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_6 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_7 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_7 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_8 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_8 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_9 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_9 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_10 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_10 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_11 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_11 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_12 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_12 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_13 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_13 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_14 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_14 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_15 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_15 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_16 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_16 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_17 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_17 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_18 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_18 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_19 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_19 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_20 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_20 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_21 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_21 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_22 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_22 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_23 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_23 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_24 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_24 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_25 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_25 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_26 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_26 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_27 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_27 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_28 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_28 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_29 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_29 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_30 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_30 Mask */ #define GPIO_GROUP_INT0_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL5: POL_31 Position */ #define GPIO_GROUP_INT0_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL5: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_POL6 ------------------------- */ #define GPIO_GROUP_INT0_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_0 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_0 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_1 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_1 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_2 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_2 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_3 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_3 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_4 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_4 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_5 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_5 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_6 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_6 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_7 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_7 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_8 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_8 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_9 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_9 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_10 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_10 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_11 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_11 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_12 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_12 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_13 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_13 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_14 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_14 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_15 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_15 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_16 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_16 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_17 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_17 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_18 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_18 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_19 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_19 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_20 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_20 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_21 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_21 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_22 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_22 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_23 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_23 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_24 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_24 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_25 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_25 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_26 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_26 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_27 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_27 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_28 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_28 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_29 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_29 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_30 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_30 Mask */ #define GPIO_GROUP_INT0_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL6: POL_31 Position */ #define GPIO_GROUP_INT0_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL6: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_POL7 ------------------------- */ #define GPIO_GROUP_INT0_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_0 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_0 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_1 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_1 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_2 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_2 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_3 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_3 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_4 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_4 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_5 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_5 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_6 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_6 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_7 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_7 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_8 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_8 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_9 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_9 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_10 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_10 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_11 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_11 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_12 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_12 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_13 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_13 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_14 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_14 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_15 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_15 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_16 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_16 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_17 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_17 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_18 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_18 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_19 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_19 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_20 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_20 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_21 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_21 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_22 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_22 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_23 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_23 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_24 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_24 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_25 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_25 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_26 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_26 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_27 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_27 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_28 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_28 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_29 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_29 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_30 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_30 Mask */ #define GPIO_GROUP_INT0_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_POL7: POL_31 Position */ #define GPIO_GROUP_INT0_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT0 PORT_POL7: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_ENA0 ------------------------- */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_0 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_0 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_1 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_1 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_2 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_2 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_3 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_3 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_4 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_4 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_5 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_5 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_6 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_6 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_7 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_7 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_8 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_8 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_9 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_9 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_10 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_10 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_11 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_11 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_12 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_12 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_13 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_13 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_14 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_14 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_15 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_15 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_16 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_16 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_17 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_17 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_18 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_18 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_19 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_19 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_20 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_20 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_21 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_21 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_22 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_22 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_23 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_23 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_24 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_24 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_25 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_25 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_26 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_26 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_27 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_27 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_28 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_28 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_29 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_29 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_30 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_30 Mask */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_31 Position */ #define GPIO_GROUP_INT0_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA0: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_ENA1 ------------------------- */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_0 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_0 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_1 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_1 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_2 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_2 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_3 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_3 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_4 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_4 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_5 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_5 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_6 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_6 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_7 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_7 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_8 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_8 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_9 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_9 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_10 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_10 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_11 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_11 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_12 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_12 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_13 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_13 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_14 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_14 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_15 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_15 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_16 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_16 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_17 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_17 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_18 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_18 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_19 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_19 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_20 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_20 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_21 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_21 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_22 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_22 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_23 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_23 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_24 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_24 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_25 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_25 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_26 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_26 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_27 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_27 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_28 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_28 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_29 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_29 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_30 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_30 Mask */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_31 Position */ #define GPIO_GROUP_INT0_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA1: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_ENA2 ------------------------- */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_0 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_0 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_1 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_1 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_2 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_2 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_3 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_3 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_4 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_4 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_5 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_5 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_6 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_6 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_7 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_7 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_8 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_8 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_9 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_9 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_10 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_10 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_11 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_11 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_12 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_12 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_13 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_13 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_14 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_14 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_15 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_15 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_16 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_16 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_17 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_17 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_18 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_18 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_19 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_19 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_20 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_20 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_21 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_21 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_22 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_22 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_23 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_23 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_24 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_24 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_25 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_25 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_26 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_26 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_27 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_27 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_28 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_28 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_29 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_29 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_30 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_30 Mask */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_31 Position */ #define GPIO_GROUP_INT0_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA2: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_ENA3 ------------------------- */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_0 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_0 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_1 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_1 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_2 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_2 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_3 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_3 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_4 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_4 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_5 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_5 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_6 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_6 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_7 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_7 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_8 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_8 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_9 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_9 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_10 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_10 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_11 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_11 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_12 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_12 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_13 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_13 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_14 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_14 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_15 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_15 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_16 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_16 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_17 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_17 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_18 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_18 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_19 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_19 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_20 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_20 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_21 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_21 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_22 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_22 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_23 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_23 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_24 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_24 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_25 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_25 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_26 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_26 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_27 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_27 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_28 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_28 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_29 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_29 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_30 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_30 Mask */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_31 Position */ #define GPIO_GROUP_INT0_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA3: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_ENA4 ------------------------- */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_0 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_0 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_1 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_1 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_2 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_2 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_3 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_3 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_4 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_4 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_5 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_5 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_6 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_6 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_7 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_7 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_8 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_8 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_9 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_9 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_10 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_10 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_11 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_11 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_12 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_12 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_13 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_13 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_14 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_14 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_15 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_15 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_16 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_16 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_17 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_17 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_18 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_18 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_19 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_19 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_20 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_20 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_21 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_21 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_22 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_22 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_23 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_23 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_24 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_24 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_25 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_25 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_26 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_26 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_27 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_27 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_28 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_28 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_29 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_29 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_30 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_30 Mask */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_31 Position */ #define GPIO_GROUP_INT0_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA4: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_ENA5 ------------------------- */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_0 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_0 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_1 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_1 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_2 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_2 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_3 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_3 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_4 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_4 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_5 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_5 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_6 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_6 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_7 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_7 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_8 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_8 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_9 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_9 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_10 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_10 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_11 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_11 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_12 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_12 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_13 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_13 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_14 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_14 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_15 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_15 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_16 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_16 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_17 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_17 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_18 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_18 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_19 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_19 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_20 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_20 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_21 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_21 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_22 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_22 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_23 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_23 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_24 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_24 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_25 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_25 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_26 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_26 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_27 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_27 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_28 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_28 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_29 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_29 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_30 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_30 Mask */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_31 Position */ #define GPIO_GROUP_INT0_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA5: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_ENA6 ------------------------- */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_0 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_0 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_1 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_1 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_2 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_2 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_3 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_3 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_4 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_4 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_5 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_5 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_6 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_6 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_7 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_7 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_8 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_8 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_9 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_9 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_10 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_10 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_11 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_11 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_12 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_12 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_13 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_13 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_14 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_14 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_15 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_15 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_16 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_16 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_17 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_17 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_18 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_18 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_19 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_19 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_20 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_20 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_21 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_21 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_22 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_22 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_23 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_23 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_24 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_24 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_25 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_25 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_26 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_26 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_27 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_27 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_28 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_28 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_29 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_29 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_30 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_30 Mask */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_31 Position */ #define GPIO_GROUP_INT0_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA6: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT0_PORT_ENA7 ------------------------- */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_0 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_0 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_1 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_1 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_2 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_2 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_3 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_3 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_4 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_4 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_5 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_5 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_6 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_6 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_7 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_7 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_8 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_8 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_9 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_9 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_10 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_10 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_11 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_11 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_12 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_12 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_13 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_13 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_14 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_14 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_15 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_15 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_16 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_16 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_17 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_17 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_18 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_18 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_19 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_19 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_20 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_20 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_21 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_21 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_22 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_22 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_23 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_23 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_24 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_24 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_25 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_25 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_26 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_26 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_27 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_27 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_28 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_28 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_29 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_29 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_30 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_30 Mask */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_31 Position */ #define GPIO_GROUP_INT0_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INT0_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INT0 PORT_ENA7: ENA_31 Mask */ /* ================================================================================ */ /* ================ struct 'GPIO_GROUP_INT1' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------- GPIO_GROUP_INT1_CTRL ---------------------------- */ #define GPIO_GROUP_INT1_CTRL_INT_Pos 0 /*!< GPIO_GROUP_INT1 CTRL: INT Position */ #define GPIO_GROUP_INT1_CTRL_INT_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_INT_Pos) /*!< GPIO_GROUP_INT1 CTRL: INT Mask */ #define GPIO_GROUP_INT1_CTRL_COMB_Pos 1 /*!< GPIO_GROUP_INT1 CTRL: COMB Position */ #define GPIO_GROUP_INT1_CTRL_COMB_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_COMB_Pos) /*!< GPIO_GROUP_INT1 CTRL: COMB Mask */ #define GPIO_GROUP_INT1_CTRL_TRIG_Pos 2 /*!< GPIO_GROUP_INT1 CTRL: TRIG Position */ #define GPIO_GROUP_INT1_CTRL_TRIG_Msk (0x01UL << GPIO_GROUP_INT1_CTRL_TRIG_Pos) /*!< GPIO_GROUP_INT1 CTRL: TRIG Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_POL0 ------------------------- */ #define GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_0 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_1 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_2 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_3 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_4 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_5 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_6 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_7 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_8 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_9 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_10 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_11 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_12 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_13 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_14 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_15 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_16 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_17 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_18 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_19 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_20 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_21 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_22 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_23 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_24 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_25 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_26 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_27 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_28 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_29 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_30 Mask */ #define GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Position */ #define GPIO_GROUP_INT1_PORT_POL0_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL0_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL0: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_POL1 ------------------------- */ #define GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_0 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_1 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_2 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_3 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_4 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_5 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_6 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_7 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_8 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_9 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_10 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_11 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_12 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_13 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_14 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_15 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_16 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_17 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_18 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_19 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_20 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_21 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_22 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_23 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_24 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_25 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_26 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_27 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_28 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_29 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_30 Mask */ #define GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Position */ #define GPIO_GROUP_INT1_PORT_POL1_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL1_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL1: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_POL2 ------------------------- */ #define GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_0 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_1 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_2 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_3 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_4 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_5 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_6 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_7 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_8 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_9 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_10 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_11 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_12 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_13 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_14 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_15 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_16 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_17 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_18 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_19 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_20 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_21 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_22 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_23 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_24 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_25 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_26 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_27 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_28 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_29 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_30 Mask */ #define GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Position */ #define GPIO_GROUP_INT1_PORT_POL2_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL2_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL2: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_POL3 ------------------------- */ #define GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_0 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_1 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_2 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_3 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_4 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_5 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_6 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_7 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_8 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_9 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_10 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_11 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_12 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_13 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_14 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_15 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_16 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_17 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_18 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_19 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_20 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_21 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_22 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_23 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_24 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_25 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_26 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_27 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_28 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_29 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_30 Mask */ #define GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Position */ #define GPIO_GROUP_INT1_PORT_POL3_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL3_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL3: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_POL4 ------------------------- */ #define GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_0 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_1 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_2 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_3 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_4 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_5 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_6 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_7 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_8 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_9 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_10 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_11 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_12 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_13 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_14 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_15 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_16 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_17 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_18 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_19 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_20 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_21 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_22 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_23 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_24 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_25 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_26 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_27 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_28 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_29 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_30 Mask */ #define GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Position */ #define GPIO_GROUP_INT1_PORT_POL4_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL4_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL4: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_POL5 ------------------------- */ #define GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_0 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_1 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_2 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_3 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_4 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_5 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_6 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_7 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_8 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_9 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_10 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_11 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_12 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_13 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_14 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_15 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_16 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_17 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_18 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_19 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_20 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_21 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_22 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_23 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_24 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_25 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_26 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_27 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_28 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_29 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_30 Mask */ #define GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Position */ #define GPIO_GROUP_INT1_PORT_POL5_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL5_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL5: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_POL6 ------------------------- */ #define GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_0 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_1 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_2 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_3 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_4 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_5 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_6 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_7 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_8 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_9 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_10 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_11 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_12 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_13 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_14 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_15 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_16 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_17 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_18 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_19 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_20 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_21 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_22 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_23 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_24 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_25 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_26 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_27 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_28 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_29 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_30 Mask */ #define GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Position */ #define GPIO_GROUP_INT1_PORT_POL6_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL6_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL6: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_POL7 ------------------------- */ #define GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_0_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_0 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_1_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_1 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_2_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_2 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_3_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_3 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_4_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_4 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_5_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_5 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_6_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_6 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_7_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_7 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_8_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_8 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_9_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_9 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_10_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_10 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_11_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_11 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_12_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_12 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_13_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_13 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_14_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_14 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_15_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_15 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_16_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_16 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_17_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_17 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_18_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_18 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_19_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_19 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_20_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_20 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_21_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_21 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_22_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_22 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_23_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_23 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_24_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_24 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_25_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_25 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_26_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_26 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_27_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_27 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_28_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_28 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_29_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_29 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_30_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_30 Mask */ #define GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Position */ #define GPIO_GROUP_INT1_PORT_POL7_POL_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_POL7_POL_31_Pos) /*!< GPIO_GROUP_INT1 PORT_POL7: POL_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_ENA0 ------------------------- */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_0 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_1 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_2 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_3 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_4 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_5 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_6 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_7 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_8 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_9 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_10 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_11 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_12 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_13 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_14 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_15 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_16 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_17 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_18 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_19 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_20 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_21 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_22 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_23 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_24 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_25 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_26 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_27 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_28 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_29 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_30 Mask */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Position */ #define GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA0_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA0: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_ENA1 ------------------------- */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_0 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_1 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_2 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_3 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_4 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_5 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_6 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_7 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_8 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_9 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_10 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_11 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_12 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_13 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_14 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_15 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_16 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_17 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_18 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_19 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_20 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_21 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_22 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_23 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_24 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_25 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_26 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_27 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_28 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_29 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_30 Mask */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Position */ #define GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA1_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA1: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_ENA2 ------------------------- */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_0 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_1 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_2 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_3 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_4 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_5 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_6 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_7 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_8 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_9 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_10 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_11 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_12 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_13 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_14 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_15 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_16 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_17 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_18 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_19 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_20 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_21 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_22 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_23 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_24 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_25 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_26 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_27 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_28 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_29 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_30 Mask */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Position */ #define GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA2_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA2: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_ENA3 ------------------------- */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_0 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_1 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_2 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_3 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_4 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_5 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_6 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_7 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_8 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_9 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_10 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_11 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_12 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_13 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_14 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_15 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_16 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_17 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_18 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_19 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_20 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_21 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_22 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_23 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_24 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_25 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_26 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_27 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_28 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_29 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_30 Mask */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Position */ #define GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA3_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA3: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_ENA4 ------------------------- */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_0 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_1 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_2 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_3 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_4 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_5 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_6 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_7 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_8 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_9 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_10 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_11 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_12 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_13 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_14 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_15 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_16 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_17 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_18 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_19 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_20 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_21 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_22 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_23 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_24 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_25 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_26 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_27 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_28 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_29 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_30 Mask */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Position */ #define GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA4_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA4: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_ENA5 ------------------------- */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_0 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_1 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_2 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_3 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_4 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_5 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_6 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_7 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_8 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_9 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_10 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_11 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_12 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_13 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_14 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_15 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_16 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_17 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_18 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_19 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_20 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_21 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_22 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_23 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_24 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_25 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_26 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_27 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_28 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_29 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_30 Mask */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Position */ #define GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA5_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA5: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_ENA6 ------------------------- */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_0 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_1 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_2 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_3 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_4 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_5 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_6 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_7 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_8 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_9 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_10 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_11 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_12 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_13 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_14 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_15 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_16 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_17 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_18 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_19 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_20 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_21 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_22 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_23 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_24 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_25 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_26 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_27 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_28 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_29 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_30 Mask */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Position */ #define GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA6_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA6: ENA_31 Mask */ /* -------------------------- GPIO_GROUP_INT1_PORT_ENA7 ------------------------- */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos 0 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_0_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_0 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos 1 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_1_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_1 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos 2 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_2_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_2 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos 3 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_3_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_3 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos 4 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_4_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_4 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos 5 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_5_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_5 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos 6 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_6_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_6 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos 7 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_7_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_7 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos 8 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_8_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_8 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos 9 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_9_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_9 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos 10 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_10_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_10 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos 11 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_11_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_11 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos 12 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_12_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_12 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos 13 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_13_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_13 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos 14 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_14_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_14 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos 15 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_15_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_15 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos 16 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_16_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_16 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos 17 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_17_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_17 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos 18 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_18_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_18 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos 19 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_19_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_19 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos 20 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_20_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_20 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos 21 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_21_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_21 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos 22 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_22_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_22 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos 23 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_23_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_23 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos 24 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_24_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_24 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos 25 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_25_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_25 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos 26 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_26_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_26 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos 27 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_27_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_27 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos 28 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_28_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_28 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos 29 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_29_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_29 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos 30 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_30_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_30 Mask */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos 31 /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Position */ #define GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Msk (0x01UL << GPIO_GROUP_INT1_PORT_ENA7_ENA_31_Pos) /*!< GPIO_GROUP_INT1 PORT_ENA7: ENA_31 Mask */ /* ================================================================================ */ /* ================ struct 'MCPWM' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- MCPWM_CON --------------------------------- */ #define MCPWM_CON_RUN0_Pos 0 /*!< MCPWM CON: RUN0 Position */ #define MCPWM_CON_RUN0_Msk (0x01UL << MCPWM_CON_RUN0_Pos) /*!< MCPWM CON: RUN0 Mask */ #define MCPWM_CON_CENTER0_Pos 1 /*!< MCPWM CON: CENTER0 Position */ #define MCPWM_CON_CENTER0_Msk (0x01UL << MCPWM_CON_CENTER0_Pos) /*!< MCPWM CON: CENTER0 Mask */ #define MCPWM_CON_POLA0_Pos 2 /*!< MCPWM CON: POLA0 Position */ #define MCPWM_CON_POLA0_Msk (0x01UL << MCPWM_CON_POLA0_Pos) /*!< MCPWM CON: POLA0 Mask */ #define MCPWM_CON_DTE0_Pos 3 /*!< MCPWM CON: DTE0 Position */ #define MCPWM_CON_DTE0_Msk (0x01UL << MCPWM_CON_DTE0_Pos) /*!< MCPWM CON: DTE0 Mask */ #define MCPWM_CON_DISUP0_Pos 4 /*!< MCPWM CON: DISUP0 Position */ #define MCPWM_CON_DISUP0_Msk (0x01UL << MCPWM_CON_DISUP0_Pos) /*!< MCPWM CON: DISUP0 Mask */ #define MCPWM_CON_RUN1_Pos 8 /*!< MCPWM CON: RUN1 Position */ #define MCPWM_CON_RUN1_Msk (0x01UL << MCPWM_CON_RUN1_Pos) /*!< MCPWM CON: RUN1 Mask */ #define MCPWM_CON_CENTER1_Pos 9 /*!< MCPWM CON: CENTER1 Position */ #define MCPWM_CON_CENTER1_Msk (0x01UL << MCPWM_CON_CENTER1_Pos) /*!< MCPWM CON: CENTER1 Mask */ #define MCPWM_CON_POLA1_Pos 10 /*!< MCPWM CON: POLA1 Position */ #define MCPWM_CON_POLA1_Msk (0x01UL << MCPWM_CON_POLA1_Pos) /*!< MCPWM CON: POLA1 Mask */ #define MCPWM_CON_DTE1_Pos 11 /*!< MCPWM CON: DTE1 Position */ #define MCPWM_CON_DTE1_Msk (0x01UL << MCPWM_CON_DTE1_Pos) /*!< MCPWM CON: DTE1 Mask */ #define MCPWM_CON_DISUP1_Pos 12 /*!< MCPWM CON: DISUP1 Position */ #define MCPWM_CON_DISUP1_Msk (0x01UL << MCPWM_CON_DISUP1_Pos) /*!< MCPWM CON: DISUP1 Mask */ #define MCPWM_CON_RUN2_Pos 16 /*!< MCPWM CON: RUN2 Position */ #define MCPWM_CON_RUN2_Msk (0x01UL << MCPWM_CON_RUN2_Pos) /*!< MCPWM CON: RUN2 Mask */ #define MCPWM_CON_CENTER2_Pos 17 /*!< MCPWM CON: CENTER2 Position */ #define MCPWM_CON_CENTER2_Msk (0x01UL << MCPWM_CON_CENTER2_Pos) /*!< MCPWM CON: CENTER2 Mask */ #define MCPWM_CON_POLA2_Pos 18 /*!< MCPWM CON: POLA2 Position */ #define MCPWM_CON_POLA2_Msk (0x01UL << MCPWM_CON_POLA2_Pos) /*!< MCPWM CON: POLA2 Mask */ #define MCPWM_CON_DTE2_Pos 19 /*!< MCPWM CON: DTE2 Position */ #define MCPWM_CON_DTE2_Msk (0x01UL << MCPWM_CON_DTE2_Pos) /*!< MCPWM CON: DTE2 Mask */ #define MCPWM_CON_DISUP2_Pos 20 /*!< MCPWM CON: DISUP2 Position */ #define MCPWM_CON_DISUP2_Msk (0x01UL << MCPWM_CON_DISUP2_Pos) /*!< MCPWM CON: DISUP2 Mask */ #define MCPWM_CON_INVBDC_Pos 29 /*!< MCPWM CON: INVBDC Position */ #define MCPWM_CON_INVBDC_Msk (0x01UL << MCPWM_CON_INVBDC_Pos) /*!< MCPWM CON: INVBDC Mask */ #define MCPWM_CON_ACMODE_Pos 30 /*!< MCPWM CON: ACMODE Position */ #define MCPWM_CON_ACMODE_Msk (0x01UL << MCPWM_CON_ACMODE_Pos) /*!< MCPWM CON: ACMODE Mask */ #define MCPWM_CON_DCMODE_Pos 31 /*!< MCPWM CON: DCMODE Position */ #define MCPWM_CON_DCMODE_Msk (0x01UL << MCPWM_CON_DCMODE_Pos) /*!< MCPWM CON: DCMODE Mask */ /* -------------------------------- MCPWM_CON_SET ------------------------------- */ #define MCPWM_CON_SET_RUN0_SET_Pos 0 /*!< MCPWM CON_SET: RUN0_SET Position */ #define MCPWM_CON_SET_RUN0_SET_Msk (0x01UL << MCPWM_CON_SET_RUN0_SET_Pos) /*!< MCPWM CON_SET: RUN0_SET Mask */ #define MCPWM_CON_SET_CENTER0_SET_Pos 1 /*!< MCPWM CON_SET: CENTER0_SET Position */ #define MCPWM_CON_SET_CENTER0_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER0_SET_Pos) /*!< MCPWM CON_SET: CENTER0_SET Mask */ #define MCPWM_CON_SET_POLA0_SET_Pos 2 /*!< MCPWM CON_SET: POLA0_SET Position */ #define MCPWM_CON_SET_POLA0_SET_Msk (0x01UL << MCPWM_CON_SET_POLA0_SET_Pos) /*!< MCPWM CON_SET: POLA0_SET Mask */ #define MCPWM_CON_SET_DTE0_SET_Pos 3 /*!< MCPWM CON_SET: DTE0_SET Position */ #define MCPWM_CON_SET_DTE0_SET_Msk (0x01UL << MCPWM_CON_SET_DTE0_SET_Pos) /*!< MCPWM CON_SET: DTE0_SET Mask */ #define MCPWM_CON_SET_DISUP0_SET_Pos 4 /*!< MCPWM CON_SET: DISUP0_SET Position */ #define MCPWM_CON_SET_DISUP0_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP0_SET_Pos) /*!< MCPWM CON_SET: DISUP0_SET Mask */ #define MCPWM_CON_SET_RUN1_SET_Pos 8 /*!< MCPWM CON_SET: RUN1_SET Position */ #define MCPWM_CON_SET_RUN1_SET_Msk (0x01UL << MCPWM_CON_SET_RUN1_SET_Pos) /*!< MCPWM CON_SET: RUN1_SET Mask */ #define MCPWM_CON_SET_CENTER1_SET_Pos 9 /*!< MCPWM CON_SET: CENTER1_SET Position */ #define MCPWM_CON_SET_CENTER1_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER1_SET_Pos) /*!< MCPWM CON_SET: CENTER1_SET Mask */ #define MCPWM_CON_SET_POLA1_SET_Pos 10 /*!< MCPWM CON_SET: POLA1_SET Position */ #define MCPWM_CON_SET_POLA1_SET_Msk (0x01UL << MCPWM_CON_SET_POLA1_SET_Pos) /*!< MCPWM CON_SET: POLA1_SET Mask */ #define MCPWM_CON_SET_DTE1_SET_Pos 11 /*!< MCPWM CON_SET: DTE1_SET Position */ #define MCPWM_CON_SET_DTE1_SET_Msk (0x01UL << MCPWM_CON_SET_DTE1_SET_Pos) /*!< MCPWM CON_SET: DTE1_SET Mask */ #define MCPWM_CON_SET_DISUP1_SET_Pos 12 /*!< MCPWM CON_SET: DISUP1_SET Position */ #define MCPWM_CON_SET_DISUP1_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP1_SET_Pos) /*!< MCPWM CON_SET: DISUP1_SET Mask */ #define MCPWM_CON_SET_RUN2_SET_Pos 16 /*!< MCPWM CON_SET: RUN2_SET Position */ #define MCPWM_CON_SET_RUN2_SET_Msk (0x01UL << MCPWM_CON_SET_RUN2_SET_Pos) /*!< MCPWM CON_SET: RUN2_SET Mask */ #define MCPWM_CON_SET_CENTER2_SET_Pos 17 /*!< MCPWM CON_SET: CENTER2_SET Position */ #define MCPWM_CON_SET_CENTER2_SET_Msk (0x01UL << MCPWM_CON_SET_CENTER2_SET_Pos) /*!< MCPWM CON_SET: CENTER2_SET Mask */ #define MCPWM_CON_SET_POLA2_SET_Pos 18 /*!< MCPWM CON_SET: POLA2_SET Position */ #define MCPWM_CON_SET_POLA2_SET_Msk (0x01UL << MCPWM_CON_SET_POLA2_SET_Pos) /*!< MCPWM CON_SET: POLA2_SET Mask */ #define MCPWM_CON_SET_DTE2_SET_Pos 19 /*!< MCPWM CON_SET: DTE2_SET Position */ #define MCPWM_CON_SET_DTE2_SET_Msk (0x01UL << MCPWM_CON_SET_DTE2_SET_Pos) /*!< MCPWM CON_SET: DTE2_SET Mask */ #define MCPWM_CON_SET_DISUP2_SET_Pos 20 /*!< MCPWM CON_SET: DISUP2_SET Position */ #define MCPWM_CON_SET_DISUP2_SET_Msk (0x01UL << MCPWM_CON_SET_DISUP2_SET_Pos) /*!< MCPWM CON_SET: DISUP2_SET Mask */ #define MCPWM_CON_SET_INVBDC_SET_Pos 29 /*!< MCPWM CON_SET: INVBDC_SET Position */ #define MCPWM_CON_SET_INVBDC_SET_Msk (0x01UL << MCPWM_CON_SET_INVBDC_SET_Pos) /*!< MCPWM CON_SET: INVBDC_SET Mask */ #define MCPWM_CON_SET_ACMODE_SET_Pos 30 /*!< MCPWM CON_SET: ACMODE_SET Position */ #define MCPWM_CON_SET_ACMODE_SET_Msk (0x01UL << MCPWM_CON_SET_ACMODE_SET_Pos) /*!< MCPWM CON_SET: ACMODE_SET Mask */ #define MCPWM_CON_SET_DCMODE_SET_Pos 31 /*!< MCPWM CON_SET: DCMODE_SET Position */ #define MCPWM_CON_SET_DCMODE_SET_Msk (0x01UL << MCPWM_CON_SET_DCMODE_SET_Pos) /*!< MCPWM CON_SET: DCMODE_SET Mask */ /* -------------------------------- MCPWM_CON_CLR ------------------------------- */ #define MCPWM_CON_CLR_RUN0_CLR_Pos 0 /*!< MCPWM CON_CLR: RUN0_CLR Position */ #define MCPWM_CON_CLR_RUN0_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN0_CLR_Pos) /*!< MCPWM CON_CLR: RUN0_CLR Mask */ #define MCPWM_CON_CLR_CENTER0_CLR_Pos 1 /*!< MCPWM CON_CLR: CENTER0_CLR Position */ #define MCPWM_CON_CLR_CENTER0_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER0_CLR_Pos) /*!< MCPWM CON_CLR: CENTER0_CLR Mask */ #define MCPWM_CON_CLR_POLA0_CLR_Pos 2 /*!< MCPWM CON_CLR: POLA0_CLR Position */ #define MCPWM_CON_CLR_POLA0_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA0_CLR_Pos) /*!< MCPWM CON_CLR: POLA0_CLR Mask */ #define MCPWM_CON_CLR_DTE0_CLR_Pos 3 /*!< MCPWM CON_CLR: DTE0_CLR Position */ #define MCPWM_CON_CLR_DTE0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE0_CLR_Pos) /*!< MCPWM CON_CLR: DTE0_CLR Mask */ #define MCPWM_CON_CLR_DISUP0_CLR_Pos 4 /*!< MCPWM CON_CLR: DISUP0_CLR Position */ #define MCPWM_CON_CLR_DISUP0_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP0_CLR_Pos) /*!< MCPWM CON_CLR: DISUP0_CLR Mask */ #define MCPWM_CON_CLR_RUN1_CLR_Pos 8 /*!< MCPWM CON_CLR: RUN1_CLR Position */ #define MCPWM_CON_CLR_RUN1_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN1_CLR_Pos) /*!< MCPWM CON_CLR: RUN1_CLR Mask */ #define MCPWM_CON_CLR_CENTER1_CLR_Pos 9 /*!< MCPWM CON_CLR: CENTER1_CLR Position */ #define MCPWM_CON_CLR_CENTER1_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER1_CLR_Pos) /*!< MCPWM CON_CLR: CENTER1_CLR Mask */ #define MCPWM_CON_CLR_POLA1_CLR_Pos 10 /*!< MCPWM CON_CLR: POLA1_CLR Position */ #define MCPWM_CON_CLR_POLA1_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA1_CLR_Pos) /*!< MCPWM CON_CLR: POLA1_CLR Mask */ #define MCPWM_CON_CLR_DTE1_CLR_Pos 11 /*!< MCPWM CON_CLR: DTE1_CLR Position */ #define MCPWM_CON_CLR_DTE1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE1_CLR_Pos) /*!< MCPWM CON_CLR: DTE1_CLR Mask */ #define MCPWM_CON_CLR_DISUP1_CLR_Pos 12 /*!< MCPWM CON_CLR: DISUP1_CLR Position */ #define MCPWM_CON_CLR_DISUP1_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP1_CLR_Pos) /*!< MCPWM CON_CLR: DISUP1_CLR Mask */ #define MCPWM_CON_CLR_RUN2_CLR_Pos 16 /*!< MCPWM CON_CLR: RUN2_CLR Position */ #define MCPWM_CON_CLR_RUN2_CLR_Msk (0x01UL << MCPWM_CON_CLR_RUN2_CLR_Pos) /*!< MCPWM CON_CLR: RUN2_CLR Mask */ #define MCPWM_CON_CLR_CENTER2_CLR_Pos 17 /*!< MCPWM CON_CLR: CENTER2_CLR Position */ #define MCPWM_CON_CLR_CENTER2_CLR_Msk (0x01UL << MCPWM_CON_CLR_CENTER2_CLR_Pos) /*!< MCPWM CON_CLR: CENTER2_CLR Mask */ #define MCPWM_CON_CLR_POLA2_CLR_Pos 18 /*!< MCPWM CON_CLR: POLA2_CLR Position */ #define MCPWM_CON_CLR_POLA2_CLR_Msk (0x01UL << MCPWM_CON_CLR_POLA2_CLR_Pos) /*!< MCPWM CON_CLR: POLA2_CLR Mask */ #define MCPWM_CON_CLR_DTE2_CLR_Pos 19 /*!< MCPWM CON_CLR: DTE2_CLR Position */ #define MCPWM_CON_CLR_DTE2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DTE2_CLR_Pos) /*!< MCPWM CON_CLR: DTE2_CLR Mask */ #define MCPWM_CON_CLR_DISUP2_CLR_Pos 20 /*!< MCPWM CON_CLR: DISUP2_CLR Position */ #define MCPWM_CON_CLR_DISUP2_CLR_Msk (0x01UL << MCPWM_CON_CLR_DISUP2_CLR_Pos) /*!< MCPWM CON_CLR: DISUP2_CLR Mask */ #define MCPWM_CON_CLR_INVBDC_CLR_Pos 29 /*!< MCPWM CON_CLR: INVBDC_CLR Position */ #define MCPWM_CON_CLR_INVBDC_CLR_Msk (0x01UL << MCPWM_CON_CLR_INVBDC_CLR_Pos) /*!< MCPWM CON_CLR: INVBDC_CLR Mask */ #define MCPWM_CON_CLR_ACMOD_CLR_Pos 30 /*!< MCPWM CON_CLR: ACMOD_CLR Position */ #define MCPWM_CON_CLR_ACMOD_CLR_Msk (0x01UL << MCPWM_CON_CLR_ACMOD_CLR_Pos) /*!< MCPWM CON_CLR: ACMOD_CLR Mask */ #define MCPWM_CON_CLR_DCMODE_CLR_Pos 31 /*!< MCPWM CON_CLR: DCMODE_CLR Position */ #define MCPWM_CON_CLR_DCMODE_CLR_Msk (0x01UL << MCPWM_CON_CLR_DCMODE_CLR_Pos) /*!< MCPWM CON_CLR: DCMODE_CLR Mask */ /* -------------------------------- MCPWM_CAPCON -------------------------------- */ #define MCPWM_CAPCON_CAP0MCI0_RE_Pos 0 /*!< MCPWM CAPCON: CAP0MCI0_RE Position */ #define MCPWM_CAPCON_CAP0MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_RE Mask */ #define MCPWM_CAPCON_CAP0MCI0_FE_Pos 1 /*!< MCPWM CAPCON: CAP0MCI0_FE Position */ #define MCPWM_CAPCON_CAP0MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI0_FE Mask */ #define MCPWM_CAPCON_CAP0MCI1_RE_Pos 2 /*!< MCPWM CAPCON: CAP0MCI1_RE Position */ #define MCPWM_CAPCON_CAP0MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_RE Mask */ #define MCPWM_CAPCON_CAP0MCI1_FE_Pos 3 /*!< MCPWM CAPCON: CAP0MCI1_FE Position */ #define MCPWM_CAPCON_CAP0MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI1_FE Mask */ #define MCPWM_CAPCON_CAP0MCI2_RE_Pos 4 /*!< MCPWM CAPCON: CAP0MCI2_RE Position */ #define MCPWM_CAPCON_CAP0MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_RE Mask */ #define MCPWM_CAPCON_CAP0MCI2_FE_Pos 5 /*!< MCPWM CAPCON: CAP0MCI2_FE Position */ #define MCPWM_CAPCON_CAP0MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP0MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP0MCI2_FE Mask */ #define MCPWM_CAPCON_CAP1MCI0_RE_Pos 6 /*!< MCPWM CAPCON: CAP1MCI0_RE Position */ #define MCPWM_CAPCON_CAP1MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_RE Mask */ #define MCPWM_CAPCON_CAP1MCI0_FE_Pos 7 /*!< MCPWM CAPCON: CAP1MCI0_FE Position */ #define MCPWM_CAPCON_CAP1MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI0_FE Mask */ #define MCPWM_CAPCON_CAP1MCI1_RE_Pos 8 /*!< MCPWM CAPCON: CAP1MCI1_RE Position */ #define MCPWM_CAPCON_CAP1MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_RE Mask */ #define MCPWM_CAPCON_CAP1MCI1_FE_Pos 9 /*!< MCPWM CAPCON: CAP1MCI1_FE Position */ #define MCPWM_CAPCON_CAP1MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI1_FE Mask */ #define MCPWM_CAPCON_CAP1MCI2_RE_Pos 10 /*!< MCPWM CAPCON: CAP1MCI2_RE Position */ #define MCPWM_CAPCON_CAP1MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_RE Mask */ #define MCPWM_CAPCON_CAP1MCI2_FE_Pos 11 /*!< MCPWM CAPCON: CAP1MCI2_FE Position */ #define MCPWM_CAPCON_CAP1MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP1MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP1MCI2_FE Mask */ #define MCPWM_CAPCON_CAP2MCI0_RE_Pos 12 /*!< MCPWM CAPCON: CAP2MCI0_RE Position */ #define MCPWM_CAPCON_CAP2MCI0_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_RE Mask */ #define MCPWM_CAPCON_CAP2MCI0_FE_Pos 13 /*!< MCPWM CAPCON: CAP2MCI0_FE Position */ #define MCPWM_CAPCON_CAP2MCI0_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI0_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI0_FE Mask */ #define MCPWM_CAPCON_CAP2MCI1_RE_Pos 14 /*!< MCPWM CAPCON: CAP2MCI1_RE Position */ #define MCPWM_CAPCON_CAP2MCI1_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_RE Mask */ #define MCPWM_CAPCON_CAP2MCI1_FE_Pos 15 /*!< MCPWM CAPCON: CAP2MCI1_FE Position */ #define MCPWM_CAPCON_CAP2MCI1_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI1_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI1_FE Mask */ #define MCPWM_CAPCON_CAP2MCI2_RE_Pos 16 /*!< MCPWM CAPCON: CAP2MCI2_RE Position */ #define MCPWM_CAPCON_CAP2MCI2_RE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_RE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_RE Mask */ #define MCPWM_CAPCON_CAP2MCI2_FE_Pos 17 /*!< MCPWM CAPCON: CAP2MCI2_FE Position */ #define MCPWM_CAPCON_CAP2MCI2_FE_Msk (0x01UL << MCPWM_CAPCON_CAP2MCI2_FE_Pos) /*!< MCPWM CAPCON: CAP2MCI2_FE Mask */ #define MCPWM_CAPCON_RT0_Pos 18 /*!< MCPWM CAPCON: RT0 Position */ #define MCPWM_CAPCON_RT0_Msk (0x01UL << MCPWM_CAPCON_RT0_Pos) /*!< MCPWM CAPCON: RT0 Mask */ #define MCPWM_CAPCON_RT1_Pos 19 /*!< MCPWM CAPCON: RT1 Position */ #define MCPWM_CAPCON_RT1_Msk (0x01UL << MCPWM_CAPCON_RT1_Pos) /*!< MCPWM CAPCON: RT1 Mask */ #define MCPWM_CAPCON_RT2_Pos 20 /*!< MCPWM CAPCON: RT2 Position */ #define MCPWM_CAPCON_RT2_Msk (0x01UL << MCPWM_CAPCON_RT2_Pos) /*!< MCPWM CAPCON: RT2 Mask */ /* ------------------------------ MCPWM_CAPCON_SET ------------------------------ */ #define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos 0 /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos 1 /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI0_FE_SET Mask */ #define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos 2 /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos 3 /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI1_FE_SET Mask */ #define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos 4 /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos 5 /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP0MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP0MCI2_FE_SET Mask */ #define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos 6 /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos 7 /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI0_FE_SET Mask */ #define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos 8 /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos 9 /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI1_FE_SET Mask */ #define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos 10 /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos 11 /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP1MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP1MCI2_FE_SET Mask */ #define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos 12 /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos 13 /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI0_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI0_FE_SET Mask */ #define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos 14 /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos 15 /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI1_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI1_FE_SET Mask */ #define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos 16 /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Position */ #define MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_RE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_RE_SET Mask */ #define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos 17 /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Position */ #define MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Msk (0x01UL << MCPWM_CAPCON_SET_CAP2MCI2_FE_SET_Pos) /*!< MCPWM CAPCON_SET: CAP2MCI2_FE_SET Mask */ #define MCPWM_CAPCON_SET_RT0_SET_Pos 18 /*!< MCPWM CAPCON_SET: RT0_SET Position */ #define MCPWM_CAPCON_SET_RT0_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT0_SET_Pos) /*!< MCPWM CAPCON_SET: RT0_SET Mask */ #define MCPWM_CAPCON_SET_RT1_SET_Pos 19 /*!< MCPWM CAPCON_SET: RT1_SET Position */ #define MCPWM_CAPCON_SET_RT1_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT1_SET_Pos) /*!< MCPWM CAPCON_SET: RT1_SET Mask */ #define MCPWM_CAPCON_SET_RT2_SET_Pos 20 /*!< MCPWM CAPCON_SET: RT2_SET Position */ #define MCPWM_CAPCON_SET_RT2_SET_Msk (0x01UL << MCPWM_CAPCON_SET_RT2_SET_Pos) /*!< MCPWM CAPCON_SET: RT2_SET Mask */ /* ------------------------------ MCPWM_CAPCON_CLR ------------------------------ */ #define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos 0 /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos 1 /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI0_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos 2 /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos 3 /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI1_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos 4 /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos 5 /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP0MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP0MCI2_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos 6 /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos 7 /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI0_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos 8 /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos 9 /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI1_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos 10 /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos 11 /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP1MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP1MCI2_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos 12 /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos 13 /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI0_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI0_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos 14 /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos 15 /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI1_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI1_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos 16 /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_RE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_RE_CLR Mask */ #define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos 17 /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Position */ #define MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_CAP2MCI2_FE_CLR_Pos) /*!< MCPWM CAPCON_CLR: CAP2MCI2_FE_CLR Mask */ #define MCPWM_CAPCON_CLR_RT0_CLR_Pos 18 /*!< MCPWM CAPCON_CLR: RT0_CLR Position */ #define MCPWM_CAPCON_CLR_RT0_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT0_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT0_CLR Mask */ #define MCPWM_CAPCON_CLR_RT1_CLR_Pos 19 /*!< MCPWM CAPCON_CLR: RT1_CLR Position */ #define MCPWM_CAPCON_CLR_RT1_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT1_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT1_CLR Mask */ #define MCPWM_CAPCON_CLR_RT2_CLR_Pos 20 /*!< MCPWM CAPCON_CLR: RT2_CLR Position */ #define MCPWM_CAPCON_CLR_RT2_CLR_Msk (0x01UL << MCPWM_CAPCON_CLR_RT2_CLR_Pos) /*!< MCPWM CAPCON_CLR: RT2_CLR Mask */ /* ---------------------------------- MCPWM_TC0 --------------------------------- */ #define MCPWM_TC0_MCTC_Pos 0 /*!< MCPWM TC0: MCTC Position */ #define MCPWM_TC0_MCTC_Msk (0xffffffffUL << MCPWM_TC0_MCTC_Pos) /*!< MCPWM TC0: MCTC Mask */ /* ---------------------------------- MCPWM_TC1 --------------------------------- */ #define MCPWM_TC1_MCTC_Pos 0 /*!< MCPWM TC1: MCTC Position */ #define MCPWM_TC1_MCTC_Msk (0xffffffffUL << MCPWM_TC1_MCTC_Pos) /*!< MCPWM TC1: MCTC Mask */ /* ---------------------------------- MCPWM_TC2 --------------------------------- */ #define MCPWM_TC2_MCTC_Pos 0 /*!< MCPWM TC2: MCTC Position */ #define MCPWM_TC2_MCTC_Msk (0xffffffffUL << MCPWM_TC2_MCTC_Pos) /*!< MCPWM TC2: MCTC Mask */ /* --------------------------------- MCPWM_LIM0 --------------------------------- */ #define MCPWM_LIM0_MCLIM_Pos 0 /*!< MCPWM LIM0: MCLIM Position */ #define MCPWM_LIM0_MCLIM_Msk (0xffffffffUL << MCPWM_LIM0_MCLIM_Pos) /*!< MCPWM LIM0: MCLIM Mask */ /* --------------------------------- MCPWM_LIM1 --------------------------------- */ #define MCPWM_LIM1_MCLIM_Pos 0 /*!< MCPWM LIM1: MCLIM Position */ #define MCPWM_LIM1_MCLIM_Msk (0xffffffffUL << MCPWM_LIM1_MCLIM_Pos) /*!< MCPWM LIM1: MCLIM Mask */ /* --------------------------------- MCPWM_LIM2 --------------------------------- */ #define MCPWM_LIM2_MCLIM_Pos 0 /*!< MCPWM LIM2: MCLIM Position */ #define MCPWM_LIM2_MCLIM_Msk (0xffffffffUL << MCPWM_LIM2_MCLIM_Pos) /*!< MCPWM LIM2: MCLIM Mask */ /* --------------------------------- MCPWM_MAT0 --------------------------------- */ #define MCPWM_MAT0_MCMAT_Pos 0 /*!< MCPWM MAT0: MCMAT Position */ #define MCPWM_MAT0_MCMAT_Msk (0xffffffffUL << MCPWM_MAT0_MCMAT_Pos) /*!< MCPWM MAT0: MCMAT Mask */ /* --------------------------------- MCPWM_MAT1 --------------------------------- */ #define MCPWM_MAT1_MCMAT_Pos 0 /*!< MCPWM MAT1: MCMAT Position */ #define MCPWM_MAT1_MCMAT_Msk (0xffffffffUL << MCPWM_MAT1_MCMAT_Pos) /*!< MCPWM MAT1: MCMAT Mask */ /* --------------------------------- MCPWM_MAT2 --------------------------------- */ #define MCPWM_MAT2_MCMAT_Pos 0 /*!< MCPWM MAT2: MCMAT Position */ #define MCPWM_MAT2_MCMAT_Msk (0xffffffffUL << MCPWM_MAT2_MCMAT_Pos) /*!< MCPWM MAT2: MCMAT Mask */ /* ---------------------------------- MCPWM_DT ---------------------------------- */ #define MCPWM_DT_DT0_Pos 0 /*!< MCPWM DT: DT0 Position */ #define MCPWM_DT_DT0_Msk (0x000003ffUL << MCPWM_DT_DT0_Pos) /*!< MCPWM DT: DT0 Mask */ #define MCPWM_DT_DT1_Pos 10 /*!< MCPWM DT: DT1 Position */ #define MCPWM_DT_DT1_Msk (0x000003ffUL << MCPWM_DT_DT1_Pos) /*!< MCPWM DT: DT1 Mask */ #define MCPWM_DT_DT2_Pos 20 /*!< MCPWM DT: DT2 Position */ #define MCPWM_DT_DT2_Msk (0x000003ffUL << MCPWM_DT_DT2_Pos) /*!< MCPWM DT: DT2 Mask */ /* ---------------------------------- MCPWM_CCP --------------------------------- */ #define MCPWM_CCP_CCPA0_Pos 0 /*!< MCPWM CCP: CCPA0 Position */ #define MCPWM_CCP_CCPA0_Msk (0x01UL << MCPWM_CCP_CCPA0_Pos) /*!< MCPWM CCP: CCPA0 Mask */ #define MCPWM_CCP_CCPB0_Pos 1 /*!< MCPWM CCP: CCPB0 Position */ #define MCPWM_CCP_CCPB0_Msk (0x01UL << MCPWM_CCP_CCPB0_Pos) /*!< MCPWM CCP: CCPB0 Mask */ #define MCPWM_CCP_CCPA1_Pos 2 /*!< MCPWM CCP: CCPA1 Position */ #define MCPWM_CCP_CCPA1_Msk (0x01UL << MCPWM_CCP_CCPA1_Pos) /*!< MCPWM CCP: CCPA1 Mask */ #define MCPWM_CCP_CCPB1_Pos 3 /*!< MCPWM CCP: CCPB1 Position */ #define MCPWM_CCP_CCPB1_Msk (0x01UL << MCPWM_CCP_CCPB1_Pos) /*!< MCPWM CCP: CCPB1 Mask */ #define MCPWM_CCP_CCPA2_Pos 4 /*!< MCPWM CCP: CCPA2 Position */ #define MCPWM_CCP_CCPA2_Msk (0x01UL << MCPWM_CCP_CCPA2_Pos) /*!< MCPWM CCP: CCPA2 Mask */ #define MCPWM_CCP_CCPB2_Pos 5 /*!< MCPWM CCP: CCPB2 Position */ #define MCPWM_CCP_CCPB2_Msk (0x01UL << MCPWM_CCP_CCPB2_Pos) /*!< MCPWM CCP: CCPB2 Mask */ /* --------------------------------- MCPWM_CAP0 --------------------------------- */ #define MCPWM_CAP0_CAP_Pos 0 /*!< MCPWM CAP0: CAP Position */ #define MCPWM_CAP0_CAP_Msk (0xffffffffUL << MCPWM_CAP0_CAP_Pos) /*!< MCPWM CAP0: CAP Mask */ /* --------------------------------- MCPWM_CAP1 --------------------------------- */ #define MCPWM_CAP1_CAP_Pos 0 /*!< MCPWM CAP1: CAP Position */ #define MCPWM_CAP1_CAP_Msk (0xffffffffUL << MCPWM_CAP1_CAP_Pos) /*!< MCPWM CAP1: CAP Mask */ /* --------------------------------- MCPWM_CAP2 --------------------------------- */ #define MCPWM_CAP2_CAP_Pos 0 /*!< MCPWM CAP2: CAP Position */ #define MCPWM_CAP2_CAP_Msk (0xffffffffUL << MCPWM_CAP2_CAP_Pos) /*!< MCPWM CAP2: CAP Mask */ /* --------------------------------- MCPWM_INTEN -------------------------------- */ #define MCPWM_INTEN_ILIM0_Pos 0 /*!< MCPWM INTEN: ILIM0 Position */ #define MCPWM_INTEN_ILIM0_Msk (0x01UL << MCPWM_INTEN_ILIM0_Pos) /*!< MCPWM INTEN: ILIM0 Mask */ #define MCPWM_INTEN_IMAT0_Pos 1 /*!< MCPWM INTEN: IMAT0 Position */ #define MCPWM_INTEN_IMAT0_Msk (0x01UL << MCPWM_INTEN_IMAT0_Pos) /*!< MCPWM INTEN: IMAT0 Mask */ #define MCPWM_INTEN_ICAP0_Pos 2 /*!< MCPWM INTEN: ICAP0 Position */ #define MCPWM_INTEN_ICAP0_Msk (0x01UL << MCPWM_INTEN_ICAP0_Pos) /*!< MCPWM INTEN: ICAP0 Mask */ #define MCPWM_INTEN_ILIM1_Pos 4 /*!< MCPWM INTEN: ILIM1 Position */ #define MCPWM_INTEN_ILIM1_Msk (0x01UL << MCPWM_INTEN_ILIM1_Pos) /*!< MCPWM INTEN: ILIM1 Mask */ #define MCPWM_INTEN_IMAT1_Pos 5 /*!< MCPWM INTEN: IMAT1 Position */ #define MCPWM_INTEN_IMAT1_Msk (0x01UL << MCPWM_INTEN_IMAT1_Pos) /*!< MCPWM INTEN: IMAT1 Mask */ #define MCPWM_INTEN_ICAP1_Pos 6 /*!< MCPWM INTEN: ICAP1 Position */ #define MCPWM_INTEN_ICAP1_Msk (0x01UL << MCPWM_INTEN_ICAP1_Pos) /*!< MCPWM INTEN: ICAP1 Mask */ #define MCPWM_INTEN_ILIM2_Pos 8 /*!< MCPWM INTEN: ILIM2 Position */ #define MCPWM_INTEN_ILIM2_Msk (0x01UL << MCPWM_INTEN_ILIM2_Pos) /*!< MCPWM INTEN: ILIM2 Mask */ #define MCPWM_INTEN_IMAT2_Pos 9 /*!< MCPWM INTEN: IMAT2 Position */ #define MCPWM_INTEN_IMAT2_Msk (0x01UL << MCPWM_INTEN_IMAT2_Pos) /*!< MCPWM INTEN: IMAT2 Mask */ #define MCPWM_INTEN_ICAP2_Pos 10 /*!< MCPWM INTEN: ICAP2 Position */ #define MCPWM_INTEN_ICAP2_Msk (0x01UL << MCPWM_INTEN_ICAP2_Pos) /*!< MCPWM INTEN: ICAP2 Mask */ #define MCPWM_INTEN_ABORT_Pos 15 /*!< MCPWM INTEN: ABORT Position */ #define MCPWM_INTEN_ABORT_Msk (0x01UL << MCPWM_INTEN_ABORT_Pos) /*!< MCPWM INTEN: ABORT Mask */ /* ------------------------------- MCPWM_INTEN_SET ------------------------------ */ #define MCPWM_INTEN_SET_ILIM0_SET_Pos 0 /*!< MCPWM INTEN_SET: ILIM0_SET Position */ #define MCPWM_INTEN_SET_ILIM0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM0_SET_Pos) /*!< MCPWM INTEN_SET: ILIM0_SET Mask */ #define MCPWM_INTEN_SET_IMAT0_SET_Pos 1 /*!< MCPWM INTEN_SET: IMAT0_SET Position */ #define MCPWM_INTEN_SET_IMAT0_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT0_SET_Pos) /*!< MCPWM INTEN_SET: IMAT0_SET Mask */ #define MCPWM_INTEN_SET_ICAP0_SET_Pos 2 /*!< MCPWM INTEN_SET: ICAP0_SET Position */ #define MCPWM_INTEN_SET_ICAP0_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP0_SET_Pos) /*!< MCPWM INTEN_SET: ICAP0_SET Mask */ #define MCPWM_INTEN_SET_ILIM1_SET_Pos 4 /*!< MCPWM INTEN_SET: ILIM1_SET Position */ #define MCPWM_INTEN_SET_ILIM1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM1_SET_Pos) /*!< MCPWM INTEN_SET: ILIM1_SET Mask */ #define MCPWM_INTEN_SET_IMAT1_SET_Pos 5 /*!< MCPWM INTEN_SET: IMAT1_SET Position */ #define MCPWM_INTEN_SET_IMAT1_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT1_SET_Pos) /*!< MCPWM INTEN_SET: IMAT1_SET Mask */ #define MCPWM_INTEN_SET_ICAP1_SET_Pos 6 /*!< MCPWM INTEN_SET: ICAP1_SET Position */ #define MCPWM_INTEN_SET_ICAP1_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP1_SET_Pos) /*!< MCPWM INTEN_SET: ICAP1_SET Mask */ #define MCPWM_INTEN_SET_ILIM2_SET_Pos 9 /*!< MCPWM INTEN_SET: ILIM2_SET Position */ #define MCPWM_INTEN_SET_ILIM2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ILIM2_SET_Pos) /*!< MCPWM INTEN_SET: ILIM2_SET Mask */ #define MCPWM_INTEN_SET_IMAT2_SET_Pos 10 /*!< MCPWM INTEN_SET: IMAT2_SET Position */ #define MCPWM_INTEN_SET_IMAT2_SET_Msk (0x01UL << MCPWM_INTEN_SET_IMAT2_SET_Pos) /*!< MCPWM INTEN_SET: IMAT2_SET Mask */ #define MCPWM_INTEN_SET_ICAP2_SET_Pos 11 /*!< MCPWM INTEN_SET: ICAP2_SET Position */ #define MCPWM_INTEN_SET_ICAP2_SET_Msk (0x01UL << MCPWM_INTEN_SET_ICAP2_SET_Pos) /*!< MCPWM INTEN_SET: ICAP2_SET Mask */ #define MCPWM_INTEN_SET_ABORT_SET_Pos 15 /*!< MCPWM INTEN_SET: ABORT_SET Position */ #define MCPWM_INTEN_SET_ABORT_SET_Msk (0x01UL << MCPWM_INTEN_SET_ABORT_SET_Pos) /*!< MCPWM INTEN_SET: ABORT_SET Mask */ /* ------------------------------- MCPWM_INTEN_CLR ------------------------------ */ #define MCPWM_INTEN_CLR_ILIM0_CLR_Pos 0 /*!< MCPWM INTEN_CLR: ILIM0_CLR Position */ #define MCPWM_INTEN_CLR_ILIM0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM0_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM0_CLR Mask */ #define MCPWM_INTEN_CLR_IMAT0_CLR_Pos 1 /*!< MCPWM INTEN_CLR: IMAT0_CLR Position */ #define MCPWM_INTEN_CLR_IMAT0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT0_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT0_CLR Mask */ #define MCPWM_INTEN_CLR_ICAP0_CLR_Pos 2 /*!< MCPWM INTEN_CLR: ICAP0_CLR Position */ #define MCPWM_INTEN_CLR_ICAP0_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP0_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP0_CLR Mask */ #define MCPWM_INTEN_CLR_ILIM1_CLR_Pos 4 /*!< MCPWM INTEN_CLR: ILIM1_CLR Position */ #define MCPWM_INTEN_CLR_ILIM1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM1_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM1_CLR Mask */ #define MCPWM_INTEN_CLR_IMAT1_CLR_Pos 5 /*!< MCPWM INTEN_CLR: IMAT1_CLR Position */ #define MCPWM_INTEN_CLR_IMAT1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT1_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT1_CLR Mask */ #define MCPWM_INTEN_CLR_ICAP1_CLR_Pos 6 /*!< MCPWM INTEN_CLR: ICAP1_CLR Position */ #define MCPWM_INTEN_CLR_ICAP1_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP1_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP1_CLR Mask */ #define MCPWM_INTEN_CLR_ILIM2_CLR_Pos 8 /*!< MCPWM INTEN_CLR: ILIM2_CLR Position */ #define MCPWM_INTEN_CLR_ILIM2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ILIM2_CLR_Pos) /*!< MCPWM INTEN_CLR: ILIM2_CLR Mask */ #define MCPWM_INTEN_CLR_IMAT2_CLR_Pos 9 /*!< MCPWM INTEN_CLR: IMAT2_CLR Position */ #define MCPWM_INTEN_CLR_IMAT2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_IMAT2_CLR_Pos) /*!< MCPWM INTEN_CLR: IMAT2_CLR Mask */ #define MCPWM_INTEN_CLR_ICAP2_CLR_Pos 10 /*!< MCPWM INTEN_CLR: ICAP2_CLR Position */ #define MCPWM_INTEN_CLR_ICAP2_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ICAP2_CLR_Pos) /*!< MCPWM INTEN_CLR: ICAP2_CLR Mask */ #define MCPWM_INTEN_CLR_ABORT_CLR_Pos 15 /*!< MCPWM INTEN_CLR: ABORT_CLR Position */ #define MCPWM_INTEN_CLR_ABORT_CLR_Msk (0x01UL << MCPWM_INTEN_CLR_ABORT_CLR_Pos) /*!< MCPWM INTEN_CLR: ABORT_CLR Mask */ /* -------------------------------- MCPWM_CNTCON -------------------------------- */ #define MCPWM_CNTCON_TC0MCI0_RE_Pos 0 /*!< MCPWM CNTCON: TC0MCI0_RE Position */ #define MCPWM_CNTCON_TC0MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_RE_Pos) /*!< MCPWM CNTCON: TC0MCI0_RE Mask */ #define MCPWM_CNTCON_TC0MCI0_FE_Pos 1 /*!< MCPWM CNTCON: TC0MCI0_FE Position */ #define MCPWM_CNTCON_TC0MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI0_FE_Pos) /*!< MCPWM CNTCON: TC0MCI0_FE Mask */ #define MCPWM_CNTCON_TC0MCI1_RE_Pos 2 /*!< MCPWM CNTCON: TC0MCI1_RE Position */ #define MCPWM_CNTCON_TC0MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_RE_Pos) /*!< MCPWM CNTCON: TC0MCI1_RE Mask */ #define MCPWM_CNTCON_TC0MCI1_FE_Pos 3 /*!< MCPWM CNTCON: TC0MCI1_FE Position */ #define MCPWM_CNTCON_TC0MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI1_FE_Pos) /*!< MCPWM CNTCON: TC0MCI1_FE Mask */ #define MCPWM_CNTCON_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON: TC0MCI2_RE Position */ #define MCPWM_CNTCON_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON: TC0MCI2_RE Mask */ #define MCPWM_CNTCON_TC0MCI2_FE_Pos 5 /*!< MCPWM CNTCON: TC0MCI2_FE Position */ #define MCPWM_CNTCON_TC0MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC0MCI2_FE_Pos) /*!< MCPWM CNTCON: TC0MCI2_FE Mask */ #define MCPWM_CNTCON_TC1MCI0_RE_Pos 6 /*!< MCPWM CNTCON: TC1MCI0_RE Position */ #define MCPWM_CNTCON_TC1MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_RE_Pos) /*!< MCPWM CNTCON: TC1MCI0_RE Mask */ #define MCPWM_CNTCON_TC1MCI0_FE_Pos 7 /*!< MCPWM CNTCON: TC1MCI0_FE Position */ #define MCPWM_CNTCON_TC1MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI0_FE_Pos) /*!< MCPWM CNTCON: TC1MCI0_FE Mask */ #define MCPWM_CNTCON_TC1MCI1_RE_Pos 8 /*!< MCPWM CNTCON: TC1MCI1_RE Position */ #define MCPWM_CNTCON_TC1MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_RE_Pos) /*!< MCPWM CNTCON: TC1MCI1_RE Mask */ #define MCPWM_CNTCON_TC1MCI1_FE_Pos 9 /*!< MCPWM CNTCON: TC1MCI1_FE Position */ #define MCPWM_CNTCON_TC1MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI1_FE_Pos) /*!< MCPWM CNTCON: TC1MCI1_FE Mask */ #define MCPWM_CNTCON_TC1MCI2_RE_Pos 10 /*!< MCPWM CNTCON: TC1MCI2_RE Position */ #define MCPWM_CNTCON_TC1MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_RE_Pos) /*!< MCPWM CNTCON: TC1MCI2_RE Mask */ #define MCPWM_CNTCON_TC1MCI2_FE_Pos 11 /*!< MCPWM CNTCON: TC1MCI2_FE Position */ #define MCPWM_CNTCON_TC1MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC1MCI2_FE_Pos) /*!< MCPWM CNTCON: TC1MCI2_FE Mask */ #define MCPWM_CNTCON_TC2MCI0_RE_Pos 12 /*!< MCPWM CNTCON: TC2MCI0_RE Position */ #define MCPWM_CNTCON_TC2MCI0_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_RE_Pos) /*!< MCPWM CNTCON: TC2MCI0_RE Mask */ #define MCPWM_CNTCON_TC2MCI0_FE_Pos 13 /*!< MCPWM CNTCON: TC2MCI0_FE Position */ #define MCPWM_CNTCON_TC2MCI0_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI0_FE_Pos) /*!< MCPWM CNTCON: TC2MCI0_FE Mask */ #define MCPWM_CNTCON_TC2MCI1_RE_Pos 14 /*!< MCPWM CNTCON: TC2MCI1_RE Position */ #define MCPWM_CNTCON_TC2MCI1_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_RE_Pos) /*!< MCPWM CNTCON: TC2MCI1_RE Mask */ #define MCPWM_CNTCON_TC2MCI1_FE_Pos 15 /*!< MCPWM CNTCON: TC2MCI1_FE Position */ #define MCPWM_CNTCON_TC2MCI1_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI1_FE_Pos) /*!< MCPWM CNTCON: TC2MCI1_FE Mask */ #define MCPWM_CNTCON_TC2MCI2_RE_Pos 16 /*!< MCPWM CNTCON: TC2MCI2_RE Position */ #define MCPWM_CNTCON_TC2MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_RE_Pos) /*!< MCPWM CNTCON: TC2MCI2_RE Mask */ #define MCPWM_CNTCON_TC2MCI2_FE_Pos 17 /*!< MCPWM CNTCON: TC2MCI2_FE Position */ #define MCPWM_CNTCON_TC2MCI2_FE_Msk (0x01UL << MCPWM_CNTCON_TC2MCI2_FE_Pos) /*!< MCPWM CNTCON: TC2MCI2_FE Mask */ #define MCPWM_CNTCON_CNTR0_Pos 29 /*!< MCPWM CNTCON: CNTR0 Position */ #define MCPWM_CNTCON_CNTR0_Msk (0x01UL << MCPWM_CNTCON_CNTR0_Pos) /*!< MCPWM CNTCON: CNTR0 Mask */ #define MCPWM_CNTCON_CNTR1_Pos 30 /*!< MCPWM CNTCON: CNTR1 Position */ #define MCPWM_CNTCON_CNTR1_Msk (0x01UL << MCPWM_CNTCON_CNTR1_Pos) /*!< MCPWM CNTCON: CNTR1 Mask */ #define MCPWM_CNTCON_CNTR2_Pos 31 /*!< MCPWM CNTCON: CNTR2 Position */ #define MCPWM_CNTCON_CNTR2_Msk (0x01UL << MCPWM_CNTCON_CNTR2_Pos) /*!< MCPWM CNTCON: CNTR2 Mask */ /* ------------------------------ MCPWM_CNTCON_SET ------------------------------ */ #define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos 0 /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Position */ #define MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos 1 /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Position */ #define MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI0_FE_SET Mask */ #define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos 2 /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Position */ #define MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos 3 /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Position */ #define MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI1_FE_SET Mask */ #define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos 4 /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Position */ #define MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos 5 /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Position */ #define MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC0MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC0MCI2_FE_SET Mask */ #define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos 6 /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Position */ #define MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos 7 /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Position */ #define MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI0_FE_SET Mask */ #define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos 8 /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Position */ #define MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos 9 /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Position */ #define MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI1_FE_SET Mask */ #define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos 10 /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Position */ #define MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos 11 /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Position */ #define MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC1MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC1MCI2_FE_SET Mask */ #define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos 12 /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Position */ #define MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos 13 /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Position */ #define MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI0_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI0_FE_SET Mask */ #define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos 14 /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Position */ #define MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos 15 /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Position */ #define MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI1_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI1_FE_SET Mask */ #define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos 16 /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Position */ #define MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_RE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_RE_SET Mask */ #define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos 17 /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Position */ #define MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Msk (0x01UL << MCPWM_CNTCON_SET_TC2MCI2_FE_SET_Pos) /*!< MCPWM CNTCON_SET: TC2MCI2_FE_SET Mask */ #define MCPWM_CNTCON_SET_CNTR0_SET_Pos 29 /*!< MCPWM CNTCON_SET: CNTR0_SET Position */ #define MCPWM_CNTCON_SET_CNTR0_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR0_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR0_SET Mask */ #define MCPWM_CNTCON_SET_CNTR1_SET_Pos 30 /*!< MCPWM CNTCON_SET: CNTR1_SET Position */ #define MCPWM_CNTCON_SET_CNTR1_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR1_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR1_SET Mask */ #define MCPWM_CNTCON_SET_CNTR2_SET_Pos 31 /*!< MCPWM CNTCON_SET: CNTR2_SET Position */ #define MCPWM_CNTCON_SET_CNTR2_SET_Msk (0x01UL << MCPWM_CNTCON_SET_CNTR2_SET_Pos) /*!< MCPWM CNTCON_SET: CNTR2_SET Mask */ /* ------------------------------ MCPWM_CNTCON_CLR ------------------------------ */ #define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos 0 /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Position */ #define MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_RE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos 1 /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI0_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos 2 /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Position */ #define MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_RE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos 3 /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI1_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos 4 /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Position */ #define MCPWM_CNTCON_CLR_TC0MCI2_RE_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_RE_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_RE Mask */ #define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos 5 /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC0MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC0MCI2_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos 6 /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Position */ #define MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_RE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos 7 /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI0_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos 8 /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Position */ #define MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_RE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos 9 /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI1_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos 10 /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Position */ #define MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_RE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos 11 /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC1MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC1MCI2_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos 12 /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Position */ #define MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_RE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos 13 /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI0_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI0_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos 14 /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Position */ #define MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_RE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos 15 /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI1_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI1_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos 16 /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Position */ #define MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_RE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_RE_CLR Mask */ #define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos 17 /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Position */ #define MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_TC2MCI2_FE_CLR_Pos) /*!< MCPWM CNTCON_CLR: TC2MCI2_FE_CLR Mask */ #define MCPWM_CNTCON_CLR_CNTR0_CLR_Pos 29 /*!< MCPWM CNTCON_CLR: CNTR0_CLR Position */ #define MCPWM_CNTCON_CLR_CNTR0_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR0_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR0_CLR Mask */ #define MCPWM_CNTCON_CLR_CNTR1_CLR_Pos 30 /*!< MCPWM CNTCON_CLR: CNTR1_CLR Position */ #define MCPWM_CNTCON_CLR_CNTR1_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR1_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR1_CLR Mask */ #define MCPWM_CNTCON_CLR_CNTR2_CLR_Pos 31 /*!< MCPWM CNTCON_CLR: CNTR2_CLR Position */ #define MCPWM_CNTCON_CLR_CNTR2_CLR_Msk (0x01UL << MCPWM_CNTCON_CLR_CNTR2_CLR_Pos) /*!< MCPWM CNTCON_CLR: CNTR2_CLR Mask */ /* --------------------------------- MCPWM_INTF --------------------------------- */ #define MCPWM_INTF_ILIM0_F_Pos 0 /*!< MCPWM INTF: ILIM0_F Position */ #define MCPWM_INTF_ILIM0_F_Msk (0x01UL << MCPWM_INTF_ILIM0_F_Pos) /*!< MCPWM INTF: ILIM0_F Mask */ #define MCPWM_INTF_IMAT0_F_Pos 1 /*!< MCPWM INTF: IMAT0_F Position */ #define MCPWM_INTF_IMAT0_F_Msk (0x01UL << MCPWM_INTF_IMAT0_F_Pos) /*!< MCPWM INTF: IMAT0_F Mask */ #define MCPWM_INTF_ICAP0_F_Pos 2 /*!< MCPWM INTF: ICAP0_F Position */ #define MCPWM_INTF_ICAP0_F_Msk (0x01UL << MCPWM_INTF_ICAP0_F_Pos) /*!< MCPWM INTF: ICAP0_F Mask */ #define MCPWM_INTF_ILIM1_F_Pos 4 /*!< MCPWM INTF: ILIM1_F Position */ #define MCPWM_INTF_ILIM1_F_Msk (0x01UL << MCPWM_INTF_ILIM1_F_Pos) /*!< MCPWM INTF: ILIM1_F Mask */ #define MCPWM_INTF_IMAT1_F_Pos 5 /*!< MCPWM INTF: IMAT1_F Position */ #define MCPWM_INTF_IMAT1_F_Msk (0x01UL << MCPWM_INTF_IMAT1_F_Pos) /*!< MCPWM INTF: IMAT1_F Mask */ #define MCPWM_INTF_ICAP1_F_Pos 6 /*!< MCPWM INTF: ICAP1_F Position */ #define MCPWM_INTF_ICAP1_F_Msk (0x01UL << MCPWM_INTF_ICAP1_F_Pos) /*!< MCPWM INTF: ICAP1_F Mask */ #define MCPWM_INTF_ILIM2_F_Pos 8 /*!< MCPWM INTF: ILIM2_F Position */ #define MCPWM_INTF_ILIM2_F_Msk (0x01UL << MCPWM_INTF_ILIM2_F_Pos) /*!< MCPWM INTF: ILIM2_F Mask */ #define MCPWM_INTF_IMAT2_F_Pos 9 /*!< MCPWM INTF: IMAT2_F Position */ #define MCPWM_INTF_IMAT2_F_Msk (0x01UL << MCPWM_INTF_IMAT2_F_Pos) /*!< MCPWM INTF: IMAT2_F Mask */ #define MCPWM_INTF_ICAP2_F_Pos 10 /*!< MCPWM INTF: ICAP2_F Position */ #define MCPWM_INTF_ICAP2_F_Msk (0x01UL << MCPWM_INTF_ICAP2_F_Pos) /*!< MCPWM INTF: ICAP2_F Mask */ #define MCPWM_INTF_ABORT_F_Pos 15 /*!< MCPWM INTF: ABORT_F Position */ #define MCPWM_INTF_ABORT_F_Msk (0x01UL << MCPWM_INTF_ABORT_F_Pos) /*!< MCPWM INTF: ABORT_F Mask */ /* ------------------------------- MCPWM_INTF_SET ------------------------------- */ #define MCPWM_INTF_SET_ILIM0_F_SET_Pos 0 /*!< MCPWM INTF_SET: ILIM0_F_SET Position */ #define MCPWM_INTF_SET_ILIM0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM0_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM0_F_SET Mask */ #define MCPWM_INTF_SET_IMAT0_F_SET_Pos 1 /*!< MCPWM INTF_SET: IMAT0_F_SET Position */ #define MCPWM_INTF_SET_IMAT0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT0_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT0_F_SET Mask */ #define MCPWM_INTF_SET_ICAP0_F_SET_Pos 2 /*!< MCPWM INTF_SET: ICAP0_F_SET Position */ #define MCPWM_INTF_SET_ICAP0_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP0_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP0_F_SET Mask */ #define MCPWM_INTF_SET_ILIM1_F_SET_Pos 4 /*!< MCPWM INTF_SET: ILIM1_F_SET Position */ #define MCPWM_INTF_SET_ILIM1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM1_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM1_F_SET Mask */ #define MCPWM_INTF_SET_IMAT1_F_SET_Pos 5 /*!< MCPWM INTF_SET: IMAT1_F_SET Position */ #define MCPWM_INTF_SET_IMAT1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT1_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT1_F_SET Mask */ #define MCPWM_INTF_SET_ICAP1_F_SET_Pos 6 /*!< MCPWM INTF_SET: ICAP1_F_SET Position */ #define MCPWM_INTF_SET_ICAP1_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP1_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP1_F_SET Mask */ #define MCPWM_INTF_SET_ILIM2_F_SET_Pos 8 /*!< MCPWM INTF_SET: ILIM2_F_SET Position */ #define MCPWM_INTF_SET_ILIM2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ILIM2_F_SET_Pos) /*!< MCPWM INTF_SET: ILIM2_F_SET Mask */ #define MCPWM_INTF_SET_IMAT2_F_SET_Pos 9 /*!< MCPWM INTF_SET: IMAT2_F_SET Position */ #define MCPWM_INTF_SET_IMAT2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_IMAT2_F_SET_Pos) /*!< MCPWM INTF_SET: IMAT2_F_SET Mask */ #define MCPWM_INTF_SET_ICAP2_F_SET_Pos 10 /*!< MCPWM INTF_SET: ICAP2_F_SET Position */ #define MCPWM_INTF_SET_ICAP2_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ICAP2_F_SET_Pos) /*!< MCPWM INTF_SET: ICAP2_F_SET Mask */ #define MCPWM_INTF_SET_ABORT_F_SET_Pos 15 /*!< MCPWM INTF_SET: ABORT_F_SET Position */ #define MCPWM_INTF_SET_ABORT_F_SET_Msk (0x01UL << MCPWM_INTF_SET_ABORT_F_SET_Pos) /*!< MCPWM INTF_SET: ABORT_F_SET Mask */ /* ------------------------------- MCPWM_INTF_CLR ------------------------------- */ #define MCPWM_INTF_CLR_ILIM0_F_CLR_Pos 0 /*!< MCPWM INTF_CLR: ILIM0_F_CLR Position */ #define MCPWM_INTF_CLR_ILIM0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM0_F_CLR Mask */ #define MCPWM_INTF_CLR_IMAT0_F_CLR_Pos 1 /*!< MCPWM INTF_CLR: IMAT0_F_CLR Position */ #define MCPWM_INTF_CLR_IMAT0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT0_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT0_F_CLR Mask */ #define MCPWM_INTF_CLR_ICAP0_F_CLR_Pos 2 /*!< MCPWM INTF_CLR: ICAP0_F_CLR Position */ #define MCPWM_INTF_CLR_ICAP0_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP0_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP0_F_CLR Mask */ #define MCPWM_INTF_CLR_ILIM1_F_CLR_Pos 4 /*!< MCPWM INTF_CLR: ILIM1_F_CLR Position */ #define MCPWM_INTF_CLR_ILIM1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM1_F_CLR Mask */ #define MCPWM_INTF_CLR_IMAT1_F_CLR_Pos 5 /*!< MCPWM INTF_CLR: IMAT1_F_CLR Position */ #define MCPWM_INTF_CLR_IMAT1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT1_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT1_F_CLR Mask */ #define MCPWM_INTF_CLR_ICAP1_F_CLR_Pos 6 /*!< MCPWM INTF_CLR: ICAP1_F_CLR Position */ #define MCPWM_INTF_CLR_ICAP1_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP1_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP1_F_CLR Mask */ #define MCPWM_INTF_CLR_ILIM2_F_CLR_Pos 8 /*!< MCPWM INTF_CLR: ILIM2_F_CLR Position */ #define MCPWM_INTF_CLR_ILIM2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ILIM2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ILIM2_F_CLR Mask */ #define MCPWM_INTF_CLR_IMAT2_F_CLR_Pos 9 /*!< MCPWM INTF_CLR: IMAT2_F_CLR Position */ #define MCPWM_INTF_CLR_IMAT2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_IMAT2_F_CLR_Pos) /*!< MCPWM INTF_CLR: IMAT2_F_CLR Mask */ #define MCPWM_INTF_CLR_ICAP2_F_CLR_Pos 10 /*!< MCPWM INTF_CLR: ICAP2_F_CLR Position */ #define MCPWM_INTF_CLR_ICAP2_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ICAP2_F_CLR_Pos) /*!< MCPWM INTF_CLR: ICAP2_F_CLR Mask */ #define MCPWM_INTF_CLR_ABORT_F_CLR_Pos 15 /*!< MCPWM INTF_CLR: ABORT_F_CLR Position */ #define MCPWM_INTF_CLR_ABORT_F_CLR_Msk (0x01UL << MCPWM_INTF_CLR_ABORT_F_CLR_Pos) /*!< MCPWM INTF_CLR: ABORT_F_CLR Mask */ /* -------------------------------- MCPWM_CAP_CLR ------------------------------- */ #define MCPWM_CAP_CLR_CAP_CLR0_Pos 0 /*!< MCPWM CAP_CLR: CAP_CLR0 Position */ #define MCPWM_CAP_CLR_CAP_CLR0_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR0_Pos) /*!< MCPWM CAP_CLR: CAP_CLR0 Mask */ #define MCPWM_CAP_CLR_CAP_CLR1_Pos 1 /*!< MCPWM CAP_CLR: CAP_CLR1 Position */ #define MCPWM_CAP_CLR_CAP_CLR1_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR1_Pos) /*!< MCPWM CAP_CLR: CAP_CLR1 Mask */ #define MCPWM_CAP_CLR_CAP_CLR2_Pos 2 /*!< MCPWM CAP_CLR: CAP_CLR2 Position */ #define MCPWM_CAP_CLR_CAP_CLR2_Msk (0x01UL << MCPWM_CAP_CLR_CAP_CLR2_Pos) /*!< MCPWM CAP_CLR: CAP_CLR2 Mask */ /* ================================================================================ */ /* ================ Group 'I2Cn' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- I2Cn_CONSET -------------------------------- */ #define I2Cn_CONSET_AA_Pos 2 /*!< I2Cn CONSET: AA Position */ #define I2Cn_CONSET_AA_Msk (0x01UL << I2Cn_CONSET_AA_Pos) /*!< I2Cn CONSET: AA Mask */ #define I2Cn_CONSET_SI_Pos 3 /*!< I2Cn CONSET: SI Position */ #define I2Cn_CONSET_SI_Msk (0x01UL << I2Cn_CONSET_SI_Pos) /*!< I2Cn CONSET: SI Mask */ #define I2Cn_CONSET_STO_Pos 4 /*!< I2Cn CONSET: STO Position */ #define I2Cn_CONSET_STO_Msk (0x01UL << I2Cn_CONSET_STO_Pos) /*!< I2Cn CONSET: STO Mask */ #define I2Cn_CONSET_STA_Pos 5 /*!< I2Cn CONSET: STA Position */ #define I2Cn_CONSET_STA_Msk (0x01UL << I2Cn_CONSET_STA_Pos) /*!< I2Cn CONSET: STA Mask */ #define I2Cn_CONSET_I2EN_Pos 6 /*!< I2Cn CONSET: I2EN Position */ #define I2Cn_CONSET_I2EN_Msk (0x01UL << I2Cn_CONSET_I2EN_Pos) /*!< I2Cn CONSET: I2EN Mask */ /* ---------------------------------- I2Cn_STAT --------------------------------- */ #define I2Cn_STAT_Status_Pos 3 /*!< I2Cn STAT: Status Position */ #define I2Cn_STAT_Status_Msk (0x1fUL << I2Cn_STAT_Status_Pos) /*!< I2Cn STAT: Status Mask */ /* ---------------------------------- I2Cn_DAT ---------------------------------- */ #define I2Cn_DAT_Data_Pos 0 /*!< I2Cn DAT: Data Position */ #define I2Cn_DAT_Data_Msk (0x000000ffUL << I2Cn_DAT_Data_Pos) /*!< I2Cn DAT: Data Mask */ /* ---------------------------------- I2Cn_ADR0 --------------------------------- */ #define I2Cn_ADR0_GC_Pos 0 /*!< I2Cn ADR0: GC Position */ #define I2Cn_ADR0_GC_Msk (0x01UL << I2Cn_ADR0_GC_Pos) /*!< I2Cn ADR0: GC Mask */ #define I2Cn_ADR0_Address_Pos 1 /*!< I2Cn ADR0: Address Position */ #define I2Cn_ADR0_Address_Msk (0x7fUL << I2Cn_ADR0_Address_Pos) /*!< I2Cn ADR0: Address Mask */ /* ---------------------------------- I2Cn_SCLH --------------------------------- */ #define I2Cn_SCLH_SCLH_Pos 0 /*!< I2Cn SCLH: SCLH Position */ #define I2Cn_SCLH_SCLH_Msk (0x0000ffffUL << I2Cn_SCLH_SCLH_Pos) /*!< I2Cn SCLH: SCLH Mask */ /* ---------------------------------- I2Cn_SCLL --------------------------------- */ #define I2Cn_SCLL_SCLL_Pos 0 /*!< I2Cn SCLL: SCLL Position */ #define I2Cn_SCLL_SCLL_Msk (0x0000ffffUL << I2Cn_SCLL_SCLL_Pos) /*!< I2Cn SCLL: SCLL Mask */ /* --------------------------------- I2Cn_CONCLR -------------------------------- */ #define I2Cn_CONCLR_AAC_Pos 2 /*!< I2Cn CONCLR: AAC Position */ #define I2Cn_CONCLR_AAC_Msk (0x01UL << I2Cn_CONCLR_AAC_Pos) /*!< I2Cn CONCLR: AAC Mask */ #define I2Cn_CONCLR_SIC_Pos 3 /*!< I2Cn CONCLR: SIC Position */ #define I2Cn_CONCLR_SIC_Msk (0x01UL << I2Cn_CONCLR_SIC_Pos) /*!< I2Cn CONCLR: SIC Mask */ #define I2Cn_CONCLR_STAC_Pos 5 /*!< I2Cn CONCLR: STAC Position */ #define I2Cn_CONCLR_STAC_Msk (0x01UL << I2Cn_CONCLR_STAC_Pos) /*!< I2Cn CONCLR: STAC Mask */ #define I2Cn_CONCLR_I2ENC_Pos 6 /*!< I2Cn CONCLR: I2ENC Position */ #define I2Cn_CONCLR_I2ENC_Msk (0x01UL << I2Cn_CONCLR_I2ENC_Pos) /*!< I2Cn CONCLR: I2ENC Mask */ /* --------------------------------- I2Cn_MMCTRL -------------------------------- */ #define I2Cn_MMCTRL_MM_ENA_Pos 0 /*!< I2Cn MMCTRL: MM_ENA Position */ #define I2Cn_MMCTRL_MM_ENA_Msk (0x01UL << I2Cn_MMCTRL_MM_ENA_Pos) /*!< I2Cn MMCTRL: MM_ENA Mask */ #define I2Cn_MMCTRL_ENA_SCL_Pos 1 /*!< I2Cn MMCTRL: ENA_SCL Position */ #define I2Cn_MMCTRL_ENA_SCL_Msk (0x01UL << I2Cn_MMCTRL_ENA_SCL_Pos) /*!< I2Cn MMCTRL: ENA_SCL Mask */ #define I2Cn_MMCTRL_MATCH_ALL_Pos 2 /*!< I2Cn MMCTRL: MATCH_ALL Position */ #define I2Cn_MMCTRL_MATCH_ALL_Msk (0x01UL << I2Cn_MMCTRL_MATCH_ALL_Pos) /*!< I2Cn MMCTRL: MATCH_ALL Mask */ /* ---------------------------------- I2Cn_ADR1 --------------------------------- */ #define I2Cn_ADR1_GC_Pos 0 /*!< I2Cn ADR1: GC Position */ #define I2Cn_ADR1_GC_Msk (0x01UL << I2Cn_ADR1_GC_Pos) /*!< I2Cn ADR1: GC Mask */ #define I2Cn_ADR1_Address_Pos 1 /*!< I2Cn ADR1: Address Position */ #define I2Cn_ADR1_Address_Msk (0x7fUL << I2Cn_ADR1_Address_Pos) /*!< I2Cn ADR1: Address Mask */ /* ---------------------------------- I2Cn_ADR2 --------------------------------- */ #define I2Cn_ADR2_GC_Pos 0 /*!< I2Cn ADR2: GC Position */ #define I2Cn_ADR2_GC_Msk (0x01UL << I2Cn_ADR2_GC_Pos) /*!< I2Cn ADR2: GC Mask */ #define I2Cn_ADR2_Address_Pos 1 /*!< I2Cn ADR2: Address Position */ #define I2Cn_ADR2_Address_Msk (0x7fUL << I2Cn_ADR2_Address_Pos) /*!< I2Cn ADR2: Address Mask */ /* ---------------------------------- I2Cn_ADR3 --------------------------------- */ #define I2Cn_ADR3_GC_Pos 0 /*!< I2Cn ADR3: GC Position */ #define I2Cn_ADR3_GC_Msk (0x01UL << I2Cn_ADR3_GC_Pos) /*!< I2Cn ADR3: GC Mask */ #define I2Cn_ADR3_Address_Pos 1 /*!< I2Cn ADR3: Address Position */ #define I2Cn_ADR3_Address_Msk (0x7fUL << I2Cn_ADR3_Address_Pos) /*!< I2Cn ADR3: Address Mask */ /* ------------------------------ I2Cn_DATA_BUFFER ------------------------------ */ #define I2Cn_DATA_BUFFER_Data_Pos 0 /*!< I2Cn DATA_BUFFER: Data Position */ #define I2Cn_DATA_BUFFER_Data_Msk (0x000000ffUL << I2Cn_DATA_BUFFER_Data_Pos) /*!< I2Cn DATA_BUFFER: Data Mask */ /* --------------------------------- I2Cn_MASK0 --------------------------------- */ #define I2Cn_MASK0_MASK_Pos 1 /*!< I2Cn MASK0: MASK Position */ #define I2Cn_MASK0_MASK_Msk (0x7fUL << I2Cn_MASK0_MASK_Pos) /*!< I2Cn MASK0: MASK Mask */ /* --------------------------------- I2Cn_MASK1 --------------------------------- */ #define I2Cn_MASK1_MASK_Pos 1 /*!< I2Cn MASK1: MASK Position */ #define I2Cn_MASK1_MASK_Msk (0x7fUL << I2Cn_MASK1_MASK_Pos) /*!< I2Cn MASK1: MASK Mask */ /* --------------------------------- I2Cn_MASK2 --------------------------------- */ #define I2Cn_MASK2_MASK_Pos 1 /*!< I2Cn MASK2: MASK Position */ #define I2Cn_MASK2_MASK_Msk (0x7fUL << I2Cn_MASK2_MASK_Pos) /*!< I2Cn MASK2: MASK Mask */ /* --------------------------------- I2Cn_MASK3 --------------------------------- */ #define I2Cn_MASK3_MASK_Pos 1 /*!< I2Cn MASK3: MASK Position */ #define I2Cn_MASK3_MASK_Msk (0x7fUL << I2Cn_MASK3_MASK_Pos) /*!< I2Cn MASK3: MASK Mask */ /* ================================================================================ */ /* ================ struct 'I2C0' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- I2C0_CONSET -------------------------------- */ #define I2C0_CONSET_AA_Pos 2 /*!< I2C0 CONSET: AA Position */ #define I2C0_CONSET_AA_Msk (0x01UL << I2C0_CONSET_AA_Pos) /*!< I2C0 CONSET: AA Mask */ #define I2C0_CONSET_SI_Pos 3 /*!< I2C0 CONSET: SI Position */ #define I2C0_CONSET_SI_Msk (0x01UL << I2C0_CONSET_SI_Pos) /*!< I2C0 CONSET: SI Mask */ #define I2C0_CONSET_STO_Pos 4 /*!< I2C0 CONSET: STO Position */ #define I2C0_CONSET_STO_Msk (0x01UL << I2C0_CONSET_STO_Pos) /*!< I2C0 CONSET: STO Mask */ #define I2C0_CONSET_STA_Pos 5 /*!< I2C0 CONSET: STA Position */ #define I2C0_CONSET_STA_Msk (0x01UL << I2C0_CONSET_STA_Pos) /*!< I2C0 CONSET: STA Mask */ #define I2C0_CONSET_I2EN_Pos 6 /*!< I2C0 CONSET: I2EN Position */ #define I2C0_CONSET_I2EN_Msk (0x01UL << I2C0_CONSET_I2EN_Pos) /*!< I2C0 CONSET: I2EN Mask */ /* ---------------------------------- I2C0_STAT --------------------------------- */ #define I2C0_STAT_Status_Pos 3 /*!< I2C0 STAT: Status Position */ #define I2C0_STAT_Status_Msk (0x1fUL << I2C0_STAT_Status_Pos) /*!< I2C0 STAT: Status Mask */ /* ---------------------------------- I2C0_DAT ---------------------------------- */ #define I2C0_DAT_Data_Pos 0 /*!< I2C0 DAT: Data Position */ #define I2C0_DAT_Data_Msk (0x000000ffUL << I2C0_DAT_Data_Pos) /*!< I2C0 DAT: Data Mask */ /* ---------------------------------- I2C0_ADR0 --------------------------------- */ #define I2C0_ADR0_GC_Pos 0 /*!< I2C0 ADR0: GC Position */ #define I2C0_ADR0_GC_Msk (0x01UL << I2C0_ADR0_GC_Pos) /*!< I2C0 ADR0: GC Mask */ #define I2C0_ADR0_Address_Pos 1 /*!< I2C0 ADR0: Address Position */ #define I2C0_ADR0_Address_Msk (0x7fUL << I2C0_ADR0_Address_Pos) /*!< I2C0 ADR0: Address Mask */ /* ---------------------------------- I2C0_SCLH --------------------------------- */ #define I2C0_SCLH_SCLH_Pos 0 /*!< I2C0 SCLH: SCLH Position */ #define I2C0_SCLH_SCLH_Msk (0x0000ffffUL << I2C0_SCLH_SCLH_Pos) /*!< I2C0 SCLH: SCLH Mask */ /* ---------------------------------- I2C0_SCLL --------------------------------- */ #define I2C0_SCLL_SCLL_Pos 0 /*!< I2C0 SCLL: SCLL Position */ #define I2C0_SCLL_SCLL_Msk (0x0000ffffUL << I2C0_SCLL_SCLL_Pos) /*!< I2C0 SCLL: SCLL Mask */ /* --------------------------------- I2C0_CONCLR -------------------------------- */ #define I2C0_CONCLR_AAC_Pos 2 /*!< I2C0 CONCLR: AAC Position */ #define I2C0_CONCLR_AAC_Msk (0x01UL << I2C0_CONCLR_AAC_Pos) /*!< I2C0 CONCLR: AAC Mask */ #define I2C0_CONCLR_SIC_Pos 3 /*!< I2C0 CONCLR: SIC Position */ #define I2C0_CONCLR_SIC_Msk (0x01UL << I2C0_CONCLR_SIC_Pos) /*!< I2C0 CONCLR: SIC Mask */ #define I2C0_CONCLR_STAC_Pos 5 /*!< I2C0 CONCLR: STAC Position */ #define I2C0_CONCLR_STAC_Msk (0x01UL << I2C0_CONCLR_STAC_Pos) /*!< I2C0 CONCLR: STAC Mask */ #define I2C0_CONCLR_I2ENC_Pos 6 /*!< I2C0 CONCLR: I2ENC Position */ #define I2C0_CONCLR_I2ENC_Msk (0x01UL << I2C0_CONCLR_I2ENC_Pos) /*!< I2C0 CONCLR: I2ENC Mask */ /* --------------------------------- I2C0_MMCTRL -------------------------------- */ #define I2C0_MMCTRL_MM_ENA_Pos 0 /*!< I2C0 MMCTRL: MM_ENA Position */ #define I2C0_MMCTRL_MM_ENA_Msk (0x01UL << I2C0_MMCTRL_MM_ENA_Pos) /*!< I2C0 MMCTRL: MM_ENA Mask */ #define I2C0_MMCTRL_ENA_SCL_Pos 1 /*!< I2C0 MMCTRL: ENA_SCL Position */ #define I2C0_MMCTRL_ENA_SCL_Msk (0x01UL << I2C0_MMCTRL_ENA_SCL_Pos) /*!< I2C0 MMCTRL: ENA_SCL Mask */ #define I2C0_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C0 MMCTRL: MATCH_ALL Position */ #define I2C0_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C0_MMCTRL_MATCH_ALL_Pos) /*!< I2C0 MMCTRL: MATCH_ALL Mask */ /* ---------------------------------- I2C0_ADR1 --------------------------------- */ #define I2C0_ADR1_GC_Pos 0 /*!< I2C0 ADR1: GC Position */ #define I2C0_ADR1_GC_Msk (0x01UL << I2C0_ADR1_GC_Pos) /*!< I2C0 ADR1: GC Mask */ #define I2C0_ADR1_Address_Pos 1 /*!< I2C0 ADR1: Address Position */ #define I2C0_ADR1_Address_Msk (0x7fUL << I2C0_ADR1_Address_Pos) /*!< I2C0 ADR1: Address Mask */ /* ---------------------------------- I2C0_ADR2 --------------------------------- */ #define I2C0_ADR2_GC_Pos 0 /*!< I2C0 ADR2: GC Position */ #define I2C0_ADR2_GC_Msk (0x01UL << I2C0_ADR2_GC_Pos) /*!< I2C0 ADR2: GC Mask */ #define I2C0_ADR2_Address_Pos 1 /*!< I2C0 ADR2: Address Position */ #define I2C0_ADR2_Address_Msk (0x7fUL << I2C0_ADR2_Address_Pos) /*!< I2C0 ADR2: Address Mask */ /* ---------------------------------- I2C0_ADR3 --------------------------------- */ #define I2C0_ADR3_GC_Pos 0 /*!< I2C0 ADR3: GC Position */ #define I2C0_ADR3_GC_Msk (0x01UL << I2C0_ADR3_GC_Pos) /*!< I2C0 ADR3: GC Mask */ #define I2C0_ADR3_Address_Pos 1 /*!< I2C0 ADR3: Address Position */ #define I2C0_ADR3_Address_Msk (0x7fUL << I2C0_ADR3_Address_Pos) /*!< I2C0 ADR3: Address Mask */ /* ------------------------------ I2C0_DATA_BUFFER ------------------------------ */ #define I2C0_DATA_BUFFER_Data_Pos 0 /*!< I2C0 DATA_BUFFER: Data Position */ #define I2C0_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C0_DATA_BUFFER_Data_Pos) /*!< I2C0 DATA_BUFFER: Data Mask */ /* --------------------------------- I2C0_MASK0 --------------------------------- */ #define I2C0_MASK0_MASK_Pos 1 /*!< I2C0 MASK0: MASK Position */ #define I2C0_MASK0_MASK_Msk (0x7fUL << I2C0_MASK0_MASK_Pos) /*!< I2C0 MASK0: MASK Mask */ /* --------------------------------- I2C0_MASK1 --------------------------------- */ #define I2C0_MASK1_MASK_Pos 1 /*!< I2C0 MASK1: MASK Position */ #define I2C0_MASK1_MASK_Msk (0x7fUL << I2C0_MASK1_MASK_Pos) /*!< I2C0 MASK1: MASK Mask */ /* --------------------------------- I2C0_MASK2 --------------------------------- */ #define I2C0_MASK2_MASK_Pos 1 /*!< I2C0 MASK2: MASK Position */ #define I2C0_MASK2_MASK_Msk (0x7fUL << I2C0_MASK2_MASK_Pos) /*!< I2C0 MASK2: MASK Mask */ /* --------------------------------- I2C0_MASK3 --------------------------------- */ #define I2C0_MASK3_MASK_Pos 1 /*!< I2C0 MASK3: MASK Position */ #define I2C0_MASK3_MASK_Msk (0x7fUL << I2C0_MASK3_MASK_Pos) /*!< I2C0 MASK3: MASK Mask */ /* ================================================================================ */ /* ================ struct 'I2C1' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- I2C1_CONSET -------------------------------- */ #define I2C1_CONSET_AA_Pos 2 /*!< I2C1 CONSET: AA Position */ #define I2C1_CONSET_AA_Msk (0x01UL << I2C1_CONSET_AA_Pos) /*!< I2C1 CONSET: AA Mask */ #define I2C1_CONSET_SI_Pos 3 /*!< I2C1 CONSET: SI Position */ #define I2C1_CONSET_SI_Msk (0x01UL << I2C1_CONSET_SI_Pos) /*!< I2C1 CONSET: SI Mask */ #define I2C1_CONSET_STO_Pos 4 /*!< I2C1 CONSET: STO Position */ #define I2C1_CONSET_STO_Msk (0x01UL << I2C1_CONSET_STO_Pos) /*!< I2C1 CONSET: STO Mask */ #define I2C1_CONSET_STA_Pos 5 /*!< I2C1 CONSET: STA Position */ #define I2C1_CONSET_STA_Msk (0x01UL << I2C1_CONSET_STA_Pos) /*!< I2C1 CONSET: STA Mask */ #define I2C1_CONSET_I2EN_Pos 6 /*!< I2C1 CONSET: I2EN Position */ #define I2C1_CONSET_I2EN_Msk (0x01UL << I2C1_CONSET_I2EN_Pos) /*!< I2C1 CONSET: I2EN Mask */ /* ---------------------------------- I2C1_STAT --------------------------------- */ #define I2C1_STAT_Status_Pos 3 /*!< I2C1 STAT: Status Position */ #define I2C1_STAT_Status_Msk (0x1fUL << I2C1_STAT_Status_Pos) /*!< I2C1 STAT: Status Mask */ /* ---------------------------------- I2C1_DAT ---------------------------------- */ #define I2C1_DAT_Data_Pos 0 /*!< I2C1 DAT: Data Position */ #define I2C1_DAT_Data_Msk (0x000000ffUL << I2C1_DAT_Data_Pos) /*!< I2C1 DAT: Data Mask */ /* ---------------------------------- I2C1_ADR0 --------------------------------- */ #define I2C1_ADR0_GC_Pos 0 /*!< I2C1 ADR0: GC Position */ #define I2C1_ADR0_GC_Msk (0x01UL << I2C1_ADR0_GC_Pos) /*!< I2C1 ADR0: GC Mask */ #define I2C1_ADR0_Address_Pos 1 /*!< I2C1 ADR0: Address Position */ #define I2C1_ADR0_Address_Msk (0x7fUL << I2C1_ADR0_Address_Pos) /*!< I2C1 ADR0: Address Mask */ /* ---------------------------------- I2C1_SCLH --------------------------------- */ #define I2C1_SCLH_SCLH_Pos 0 /*!< I2C1 SCLH: SCLH Position */ #define I2C1_SCLH_SCLH_Msk (0x0000ffffUL << I2C1_SCLH_SCLH_Pos) /*!< I2C1 SCLH: SCLH Mask */ /* ---------------------------------- I2C1_SCLL --------------------------------- */ #define I2C1_SCLL_SCLL_Pos 0 /*!< I2C1 SCLL: SCLL Position */ #define I2C1_SCLL_SCLL_Msk (0x0000ffffUL << I2C1_SCLL_SCLL_Pos) /*!< I2C1 SCLL: SCLL Mask */ /* --------------------------------- I2C1_CONCLR -------------------------------- */ #define I2C1_CONCLR_AAC_Pos 2 /*!< I2C1 CONCLR: AAC Position */ #define I2C1_CONCLR_AAC_Msk (0x01UL << I2C1_CONCLR_AAC_Pos) /*!< I2C1 CONCLR: AAC Mask */ #define I2C1_CONCLR_SIC_Pos 3 /*!< I2C1 CONCLR: SIC Position */ #define I2C1_CONCLR_SIC_Msk (0x01UL << I2C1_CONCLR_SIC_Pos) /*!< I2C1 CONCLR: SIC Mask */ #define I2C1_CONCLR_STAC_Pos 5 /*!< I2C1 CONCLR: STAC Position */ #define I2C1_CONCLR_STAC_Msk (0x01UL << I2C1_CONCLR_STAC_Pos) /*!< I2C1 CONCLR: STAC Mask */ #define I2C1_CONCLR_I2ENC_Pos 6 /*!< I2C1 CONCLR: I2ENC Position */ #define I2C1_CONCLR_I2ENC_Msk (0x01UL << I2C1_CONCLR_I2ENC_Pos) /*!< I2C1 CONCLR: I2ENC Mask */ /* --------------------------------- I2C1_MMCTRL -------------------------------- */ #define I2C1_MMCTRL_MM_ENA_Pos 0 /*!< I2C1 MMCTRL: MM_ENA Position */ #define I2C1_MMCTRL_MM_ENA_Msk (0x01UL << I2C1_MMCTRL_MM_ENA_Pos) /*!< I2C1 MMCTRL: MM_ENA Mask */ #define I2C1_MMCTRL_ENA_SCL_Pos 1 /*!< I2C1 MMCTRL: ENA_SCL Position */ #define I2C1_MMCTRL_ENA_SCL_Msk (0x01UL << I2C1_MMCTRL_ENA_SCL_Pos) /*!< I2C1 MMCTRL: ENA_SCL Mask */ #define I2C1_MMCTRL_MATCH_ALL_Pos 2 /*!< I2C1 MMCTRL: MATCH_ALL Position */ #define I2C1_MMCTRL_MATCH_ALL_Msk (0x01UL << I2C1_MMCTRL_MATCH_ALL_Pos) /*!< I2C1 MMCTRL: MATCH_ALL Mask */ /* ---------------------------------- I2C1_ADR1 --------------------------------- */ #define I2C1_ADR1_GC_Pos 0 /*!< I2C1 ADR1: GC Position */ #define I2C1_ADR1_GC_Msk (0x01UL << I2C1_ADR1_GC_Pos) /*!< I2C1 ADR1: GC Mask */ #define I2C1_ADR1_Address_Pos 1 /*!< I2C1 ADR1: Address Position */ #define I2C1_ADR1_Address_Msk (0x7fUL << I2C1_ADR1_Address_Pos) /*!< I2C1 ADR1: Address Mask */ /* ---------------------------------- I2C1_ADR2 --------------------------------- */ #define I2C1_ADR2_GC_Pos 0 /*!< I2C1 ADR2: GC Position */ #define I2C1_ADR2_GC_Msk (0x01UL << I2C1_ADR2_GC_Pos) /*!< I2C1 ADR2: GC Mask */ #define I2C1_ADR2_Address_Pos 1 /*!< I2C1 ADR2: Address Position */ #define I2C1_ADR2_Address_Msk (0x7fUL << I2C1_ADR2_Address_Pos) /*!< I2C1 ADR2: Address Mask */ /* ---------------------------------- I2C1_ADR3 --------------------------------- */ #define I2C1_ADR3_GC_Pos 0 /*!< I2C1 ADR3: GC Position */ #define I2C1_ADR3_GC_Msk (0x01UL << I2C1_ADR3_GC_Pos) /*!< I2C1 ADR3: GC Mask */ #define I2C1_ADR3_Address_Pos 1 /*!< I2C1 ADR3: Address Position */ #define I2C1_ADR3_Address_Msk (0x7fUL << I2C1_ADR3_Address_Pos) /*!< I2C1 ADR3: Address Mask */ /* ------------------------------ I2C1_DATA_BUFFER ------------------------------ */ #define I2C1_DATA_BUFFER_Data_Pos 0 /*!< I2C1 DATA_BUFFER: Data Position */ #define I2C1_DATA_BUFFER_Data_Msk (0x000000ffUL << I2C1_DATA_BUFFER_Data_Pos) /*!< I2C1 DATA_BUFFER: Data Mask */ /* --------------------------------- I2C1_MASK0 --------------------------------- */ #define I2C1_MASK0_MASK_Pos 1 /*!< I2C1 MASK0: MASK Position */ #define I2C1_MASK0_MASK_Msk (0x7fUL << I2C1_MASK0_MASK_Pos) /*!< I2C1 MASK0: MASK Mask */ /* --------------------------------- I2C1_MASK1 --------------------------------- */ #define I2C1_MASK1_MASK_Pos 1 /*!< I2C1 MASK1: MASK Position */ #define I2C1_MASK1_MASK_Msk (0x7fUL << I2C1_MASK1_MASK_Pos) /*!< I2C1 MASK1: MASK Mask */ /* --------------------------------- I2C1_MASK2 --------------------------------- */ #define I2C1_MASK2_MASK_Pos 1 /*!< I2C1 MASK2: MASK Position */ #define I2C1_MASK2_MASK_Msk (0x7fUL << I2C1_MASK2_MASK_Pos) /*!< I2C1 MASK2: MASK Mask */ /* --------------------------------- I2C1_MASK3 --------------------------------- */ #define I2C1_MASK3_MASK_Pos 1 /*!< I2C1 MASK3: MASK Position */ #define I2C1_MASK3_MASK_Msk (0x7fUL << I2C1_MASK3_MASK_Pos) /*!< I2C1 MASK3: MASK Mask */ /* ================================================================================ */ /* ================ Group 'I2Sn' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- I2Sn_DAO ---------------------------------- */ #define I2Sn_DAO_WORDWIDTH_Pos 0 /*!< I2Sn DAO: WORDWIDTH Position */ #define I2Sn_DAO_WORDWIDTH_Msk (0x03UL << I2Sn_DAO_WORDWIDTH_Pos) /*!< I2Sn DAO: WORDWIDTH Mask */ #define I2Sn_DAO_MONO_Pos 2 /*!< I2Sn DAO: MONO Position */ #define I2Sn_DAO_MONO_Msk (0x01UL << I2Sn_DAO_MONO_Pos) /*!< I2Sn DAO: MONO Mask */ #define I2Sn_DAO_STOP_Pos 3 /*!< I2Sn DAO: STOP Position */ #define I2Sn_DAO_STOP_Msk (0x01UL << I2Sn_DAO_STOP_Pos) /*!< I2Sn DAO: STOP Mask */ #define I2Sn_DAO_RESET_Pos 4 /*!< I2Sn DAO: RESET Position */ #define I2Sn_DAO_RESET_Msk (0x01UL << I2Sn_DAO_RESET_Pos) /*!< I2Sn DAO: RESET Mask */ #define I2Sn_DAO_WS_SEL_Pos 5 /*!< I2Sn DAO: WS_SEL Position */ #define I2Sn_DAO_WS_SEL_Msk (0x01UL << I2Sn_DAO_WS_SEL_Pos) /*!< I2Sn DAO: WS_SEL Mask */ #define I2Sn_DAO_WS_HALFPERIOD_Pos 6 /*!< I2Sn DAO: WS_HALFPERIOD Position */ #define I2Sn_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2Sn_DAO_WS_HALFPERIOD_Pos) /*!< I2Sn DAO: WS_HALFPERIOD Mask */ #define I2Sn_DAO_MUTE_Pos 15 /*!< I2Sn DAO: MUTE Position */ #define I2Sn_DAO_MUTE_Msk (0x01UL << I2Sn_DAO_MUTE_Pos) /*!< I2Sn DAO: MUTE Mask */ /* ---------------------------------- I2Sn_DAI ---------------------------------- */ #define I2Sn_DAI_WORDWIDTH_Pos 0 /*!< I2Sn DAI: WORDWIDTH Position */ #define I2Sn_DAI_WORDWIDTH_Msk (0x03UL << I2Sn_DAI_WORDWIDTH_Pos) /*!< I2Sn DAI: WORDWIDTH Mask */ #define I2Sn_DAI_MONO_Pos 2 /*!< I2Sn DAI: MONO Position */ #define I2Sn_DAI_MONO_Msk (0x01UL << I2Sn_DAI_MONO_Pos) /*!< I2Sn DAI: MONO Mask */ #define I2Sn_DAI_STOP_Pos 3 /*!< I2Sn DAI: STOP Position */ #define I2Sn_DAI_STOP_Msk (0x01UL << I2Sn_DAI_STOP_Pos) /*!< I2Sn DAI: STOP Mask */ #define I2Sn_DAI_RESET_Pos 4 /*!< I2Sn DAI: RESET Position */ #define I2Sn_DAI_RESET_Msk (0x01UL << I2Sn_DAI_RESET_Pos) /*!< I2Sn DAI: RESET Mask */ #define I2Sn_DAI_WS_SEL_Pos 5 /*!< I2Sn DAI: WS_SEL Position */ #define I2Sn_DAI_WS_SEL_Msk (0x01UL << I2Sn_DAI_WS_SEL_Pos) /*!< I2Sn DAI: WS_SEL Mask */ #define I2Sn_DAI_WS_HALFPERIOD_Pos 6 /*!< I2Sn DAI: WS_HALFPERIOD Position */ #define I2Sn_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2Sn_DAI_WS_HALFPERIOD_Pos) /*!< I2Sn DAI: WS_HALFPERIOD Mask */ /* --------------------------------- I2Sn_TXFIFO -------------------------------- */ #define I2Sn_TXFIFO_I2STXFIFO_Pos 0 /*!< I2Sn TXFIFO: I2STXFIFO Position */ #define I2Sn_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2Sn_TXFIFO_I2STXFIFO_Pos) /*!< I2Sn TXFIFO: I2STXFIFO Mask */ /* --------------------------------- I2Sn_RXFIFO -------------------------------- */ #define I2Sn_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2Sn RXFIFO: I2SRXFIFO Position */ #define I2Sn_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2Sn_RXFIFO_I2SRXFIFO_Pos) /*!< I2Sn RXFIFO: I2SRXFIFO Mask */ /* --------------------------------- I2Sn_STATE --------------------------------- */ #define I2Sn_STATE_IRQ_Pos 0 /*!< I2Sn STATE: IRQ Position */ #define I2Sn_STATE_IRQ_Msk (0x01UL << I2Sn_STATE_IRQ_Pos) /*!< I2Sn STATE: IRQ Mask */ #define I2Sn_STATE_DMAREQ1_Pos 1 /*!< I2Sn STATE: DMAREQ1 Position */ #define I2Sn_STATE_DMAREQ1_Msk (0x01UL << I2Sn_STATE_DMAREQ1_Pos) /*!< I2Sn STATE: DMAREQ1 Mask */ #define I2Sn_STATE_DMAREQ2_Pos 2 /*!< I2Sn STATE: DMAREQ2 Position */ #define I2Sn_STATE_DMAREQ2_Msk (0x01UL << I2Sn_STATE_DMAREQ2_Pos) /*!< I2Sn STATE: DMAREQ2 Mask */ #define I2Sn_STATE_RX_LEVEL_Pos 8 /*!< I2Sn STATE: RX_LEVEL Position */ #define I2Sn_STATE_RX_LEVEL_Msk (0x0fUL << I2Sn_STATE_RX_LEVEL_Pos) /*!< I2Sn STATE: RX_LEVEL Mask */ #define I2Sn_STATE_TX_LEVEL_Pos 16 /*!< I2Sn STATE: TX_LEVEL Position */ #define I2Sn_STATE_TX_LEVEL_Msk (0x0fUL << I2Sn_STATE_TX_LEVEL_Pos) /*!< I2Sn STATE: TX_LEVEL Mask */ /* ---------------------------------- I2Sn_DMA1 --------------------------------- */ #define I2Sn_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2Sn DMA1: RX_DMA1_ENABLE Position */ #define I2Sn_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2Sn_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2Sn DMA1: RX_DMA1_ENABLE Mask */ #define I2Sn_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2Sn DMA1: TX_DMA1_ENABLE Position */ #define I2Sn_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2Sn_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2Sn DMA1: TX_DMA1_ENABLE Mask */ #define I2Sn_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2Sn DMA1: RX_DEPTH_DMA1 Position */ #define I2Sn_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2Sn_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2Sn DMA1: RX_DEPTH_DMA1 Mask */ #define I2Sn_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2Sn DMA1: TX_DEPTH_DMA1 Position */ #define I2Sn_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2Sn_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2Sn DMA1: TX_DEPTH_DMA1 Mask */ /* ---------------------------------- I2Sn_DMA2 --------------------------------- */ #define I2Sn_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2Sn DMA2: RX_DMA2_ENABLE Position */ #define I2Sn_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2Sn_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2Sn DMA2: RX_DMA2_ENABLE Mask */ #define I2Sn_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2Sn DMA2: TX_DMA2_ENABLE Position */ #define I2Sn_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2Sn_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2Sn DMA2: TX_DMA2_ENABLE Mask */ #define I2Sn_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2Sn DMA2: RX_DEPTH_DMA2 Position */ #define I2Sn_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2Sn_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2Sn DMA2: RX_DEPTH_DMA2 Mask */ #define I2Sn_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2Sn DMA2: TX_DEPTH_DMA2 Position */ #define I2Sn_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2Sn_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2Sn DMA2: TX_DEPTH_DMA2 Mask */ /* ---------------------------------- I2Sn_IRQ ---------------------------------- */ #define I2Sn_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2Sn IRQ: RX_IRQ_ENABLE Position */ #define I2Sn_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2Sn_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2Sn IRQ: RX_IRQ_ENABLE Mask */ #define I2Sn_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2Sn IRQ: TX_IRQ_ENABLE Position */ #define I2Sn_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2Sn_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2Sn IRQ: TX_IRQ_ENABLE Mask */ #define I2Sn_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2Sn IRQ: RX_DEPTH_IRQ Position */ #define I2Sn_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2Sn_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2Sn IRQ: RX_DEPTH_IRQ Mask */ #define I2Sn_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2Sn IRQ: TX_DEPTH_IRQ Position */ #define I2Sn_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2Sn_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2Sn IRQ: TX_DEPTH_IRQ Mask */ /* --------------------------------- I2Sn_TXRATE -------------------------------- */ #define I2Sn_TXRATE_Y_DIVIDER_Pos 0 /*!< I2Sn TXRATE: Y_DIVIDER Position */ #define I2Sn_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2Sn_TXRATE_Y_DIVIDER_Pos) /*!< I2Sn TXRATE: Y_DIVIDER Mask */ #define I2Sn_TXRATE_X_DIVIDER_Pos 8 /*!< I2Sn TXRATE: X_DIVIDER Position */ #define I2Sn_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2Sn_TXRATE_X_DIVIDER_Pos) /*!< I2Sn TXRATE: X_DIVIDER Mask */ /* --------------------------------- I2Sn_RXRATE -------------------------------- */ #define I2Sn_RXRATE_Y_DIVIDER_Pos 0 /*!< I2Sn RXRATE: Y_DIVIDER Position */ #define I2Sn_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2Sn_RXRATE_Y_DIVIDER_Pos) /*!< I2Sn RXRATE: Y_DIVIDER Mask */ #define I2Sn_RXRATE_X_DIVIDER_Pos 8 /*!< I2Sn RXRATE: X_DIVIDER Position */ #define I2Sn_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2Sn_RXRATE_X_DIVIDER_Pos) /*!< I2Sn RXRATE: X_DIVIDER Mask */ /* ------------------------------- I2Sn_TXBITRATE ------------------------------- */ #define I2Sn_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2Sn TXBITRATE: TX_BITRATE Position */ #define I2Sn_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2Sn_TXBITRATE_TX_BITRATE_Pos) /*!< I2Sn TXBITRATE: TX_BITRATE Mask */ /* ------------------------------- I2Sn_RXBITRATE ------------------------------- */ #define I2Sn_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2Sn RXBITRATE: RX_BITRATE Position */ #define I2Sn_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2Sn_RXBITRATE_RX_BITRATE_Pos) /*!< I2Sn RXBITRATE: RX_BITRATE Mask */ /* --------------------------------- I2Sn_TXMODE -------------------------------- */ #define I2Sn_TXMODE_TXCLKSEL_Pos 0 /*!< I2Sn TXMODE: TXCLKSEL Position */ #define I2Sn_TXMODE_TXCLKSEL_Msk (0x03UL << I2Sn_TXMODE_TXCLKSEL_Pos) /*!< I2Sn TXMODE: TXCLKSEL Mask */ #define I2Sn_TXMODE_TX4PIN_Pos 2 /*!< I2Sn TXMODE: TX4PIN Position */ #define I2Sn_TXMODE_TX4PIN_Msk (0x01UL << I2Sn_TXMODE_TX4PIN_Pos) /*!< I2Sn TXMODE: TX4PIN Mask */ #define I2Sn_TXMODE_TXMCENA_Pos 3 /*!< I2Sn TXMODE: TXMCENA Position */ #define I2Sn_TXMODE_TXMCENA_Msk (0x01UL << I2Sn_TXMODE_TXMCENA_Pos) /*!< I2Sn TXMODE: TXMCENA Mask */ /* --------------------------------- I2Sn_RXMODE -------------------------------- */ #define I2Sn_RXMODE_RXCLKSEL_Pos 0 /*!< I2Sn RXMODE: RXCLKSEL Position */ #define I2Sn_RXMODE_RXCLKSEL_Msk (0x03UL << I2Sn_RXMODE_RXCLKSEL_Pos) /*!< I2Sn RXMODE: RXCLKSEL Mask */ #define I2Sn_RXMODE_RX4PIN_Pos 2 /*!< I2Sn RXMODE: RX4PIN Position */ #define I2Sn_RXMODE_RX4PIN_Msk (0x01UL << I2Sn_RXMODE_RX4PIN_Pos) /*!< I2Sn RXMODE: RX4PIN Mask */ #define I2Sn_RXMODE_RXMCENA_Pos 3 /*!< I2Sn RXMODE: RXMCENA Position */ #define I2Sn_RXMODE_RXMCENA_Msk (0x01UL << I2Sn_RXMODE_RXMCENA_Pos) /*!< I2Sn RXMODE: RXMCENA Mask */ /* ================================================================================ */ /* ================ struct 'I2S0' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- I2S0_DAO ---------------------------------- */ #define I2S0_DAO_WORDWIDTH_Pos 0 /*!< I2S0 DAO: WORDWIDTH Position */ #define I2S0_DAO_WORDWIDTH_Msk (0x03UL << I2S0_DAO_WORDWIDTH_Pos) /*!< I2S0 DAO: WORDWIDTH Mask */ #define I2S0_DAO_MONO_Pos 2 /*!< I2S0 DAO: MONO Position */ #define I2S0_DAO_MONO_Msk (0x01UL << I2S0_DAO_MONO_Pos) /*!< I2S0 DAO: MONO Mask */ #define I2S0_DAO_STOP_Pos 3 /*!< I2S0 DAO: STOP Position */ #define I2S0_DAO_STOP_Msk (0x01UL << I2S0_DAO_STOP_Pos) /*!< I2S0 DAO: STOP Mask */ #define I2S0_DAO_RESET_Pos 4 /*!< I2S0 DAO: RESET Position */ #define I2S0_DAO_RESET_Msk (0x01UL << I2S0_DAO_RESET_Pos) /*!< I2S0 DAO: RESET Mask */ #define I2S0_DAO_WS_SEL_Pos 5 /*!< I2S0 DAO: WS_SEL Position */ #define I2S0_DAO_WS_SEL_Msk (0x01UL << I2S0_DAO_WS_SEL_Pos) /*!< I2S0 DAO: WS_SEL Mask */ #define I2S0_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAO: WS_HALFPERIOD Position */ #define I2S0_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAO_WS_HALFPERIOD_Pos) /*!< I2S0 DAO: WS_HALFPERIOD Mask */ #define I2S0_DAO_MUTE_Pos 15 /*!< I2S0 DAO: MUTE Position */ #define I2S0_DAO_MUTE_Msk (0x01UL << I2S0_DAO_MUTE_Pos) /*!< I2S0 DAO: MUTE Mask */ /* ---------------------------------- I2S0_DAI ---------------------------------- */ #define I2S0_DAI_WORDWIDTH_Pos 0 /*!< I2S0 DAI: WORDWIDTH Position */ #define I2S0_DAI_WORDWIDTH_Msk (0x03UL << I2S0_DAI_WORDWIDTH_Pos) /*!< I2S0 DAI: WORDWIDTH Mask */ #define I2S0_DAI_MONO_Pos 2 /*!< I2S0 DAI: MONO Position */ #define I2S0_DAI_MONO_Msk (0x01UL << I2S0_DAI_MONO_Pos) /*!< I2S0 DAI: MONO Mask */ #define I2S0_DAI_STOP_Pos 3 /*!< I2S0 DAI: STOP Position */ #define I2S0_DAI_STOP_Msk (0x01UL << I2S0_DAI_STOP_Pos) /*!< I2S0 DAI: STOP Mask */ #define I2S0_DAI_RESET_Pos 4 /*!< I2S0 DAI: RESET Position */ #define I2S0_DAI_RESET_Msk (0x01UL << I2S0_DAI_RESET_Pos) /*!< I2S0 DAI: RESET Mask */ #define I2S0_DAI_WS_SEL_Pos 5 /*!< I2S0 DAI: WS_SEL Position */ #define I2S0_DAI_WS_SEL_Msk (0x01UL << I2S0_DAI_WS_SEL_Pos) /*!< I2S0 DAI: WS_SEL Mask */ #define I2S0_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S0 DAI: WS_HALFPERIOD Position */ #define I2S0_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S0_DAI_WS_HALFPERIOD_Pos) /*!< I2S0 DAI: WS_HALFPERIOD Mask */ /* --------------------------------- I2S0_TXFIFO -------------------------------- */ #define I2S0_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S0 TXFIFO: I2STXFIFO Position */ #define I2S0_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S0_TXFIFO_I2STXFIFO_Pos) /*!< I2S0 TXFIFO: I2STXFIFO Mask */ /* --------------------------------- I2S0_RXFIFO -------------------------------- */ #define I2S0_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S0 RXFIFO: I2SRXFIFO Position */ #define I2S0_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S0_RXFIFO_I2SRXFIFO_Pos) /*!< I2S0 RXFIFO: I2SRXFIFO Mask */ /* --------------------------------- I2S0_STATE --------------------------------- */ #define I2S0_STATE_IRQ_Pos 0 /*!< I2S0 STATE: IRQ Position */ #define I2S0_STATE_IRQ_Msk (0x01UL << I2S0_STATE_IRQ_Pos) /*!< I2S0 STATE: IRQ Mask */ #define I2S0_STATE_DMAREQ1_Pos 1 /*!< I2S0 STATE: DMAREQ1 Position */ #define I2S0_STATE_DMAREQ1_Msk (0x01UL << I2S0_STATE_DMAREQ1_Pos) /*!< I2S0 STATE: DMAREQ1 Mask */ #define I2S0_STATE_DMAREQ2_Pos 2 /*!< I2S0 STATE: DMAREQ2 Position */ #define I2S0_STATE_DMAREQ2_Msk (0x01UL << I2S0_STATE_DMAREQ2_Pos) /*!< I2S0 STATE: DMAREQ2 Mask */ #define I2S0_STATE_RX_LEVEL_Pos 8 /*!< I2S0 STATE: RX_LEVEL Position */ #define I2S0_STATE_RX_LEVEL_Msk (0x0fUL << I2S0_STATE_RX_LEVEL_Pos) /*!< I2S0 STATE: RX_LEVEL Mask */ #define I2S0_STATE_TX_LEVEL_Pos 16 /*!< I2S0 STATE: TX_LEVEL Position */ #define I2S0_STATE_TX_LEVEL_Msk (0x0fUL << I2S0_STATE_TX_LEVEL_Pos) /*!< I2S0 STATE: TX_LEVEL Mask */ /* ---------------------------------- I2S0_DMA1 --------------------------------- */ #define I2S0_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S0 DMA1: RX_DMA1_ENABLE Position */ #define I2S0_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: RX_DMA1_ENABLE Mask */ #define I2S0_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S0 DMA1: TX_DMA1_ENABLE Position */ #define I2S0_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S0_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S0 DMA1: TX_DMA1_ENABLE Mask */ #define I2S0_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S0 DMA1: RX_DEPTH_DMA1 Position */ #define I2S0_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: RX_DEPTH_DMA1 Mask */ #define I2S0_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S0 DMA1: TX_DEPTH_DMA1 Position */ #define I2S0_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S0_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S0 DMA1: TX_DEPTH_DMA1 Mask */ /* ---------------------------------- I2S0_DMA2 --------------------------------- */ #define I2S0_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S0 DMA2: RX_DMA2_ENABLE Position */ #define I2S0_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: RX_DMA2_ENABLE Mask */ #define I2S0_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S0 DMA2: TX_DMA2_ENABLE Position */ #define I2S0_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S0_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S0 DMA2: TX_DMA2_ENABLE Mask */ #define I2S0_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S0 DMA2: RX_DEPTH_DMA2 Position */ #define I2S0_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: RX_DEPTH_DMA2 Mask */ #define I2S0_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S0 DMA2: TX_DEPTH_DMA2 Position */ #define I2S0_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S0_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S0 DMA2: TX_DEPTH_DMA2 Mask */ /* ---------------------------------- I2S0_IRQ ---------------------------------- */ #define I2S0_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S0 IRQ: RX_IRQ_ENABLE Position */ #define I2S0_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: RX_IRQ_ENABLE Mask */ #define I2S0_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S0 IRQ: TX_IRQ_ENABLE Position */ #define I2S0_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S0_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S0 IRQ: TX_IRQ_ENABLE Mask */ #define I2S0_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S0 IRQ: RX_DEPTH_IRQ Position */ #define I2S0_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: RX_DEPTH_IRQ Mask */ #define I2S0_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S0 IRQ: TX_DEPTH_IRQ Position */ #define I2S0_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S0_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S0 IRQ: TX_DEPTH_IRQ Mask */ /* --------------------------------- I2S0_TXRATE -------------------------------- */ #define I2S0_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 TXRATE: Y_DIVIDER Position */ #define I2S0_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_Y_DIVIDER_Pos) /*!< I2S0 TXRATE: Y_DIVIDER Mask */ #define I2S0_TXRATE_X_DIVIDER_Pos 8 /*!< I2S0 TXRATE: X_DIVIDER Position */ #define I2S0_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_TXRATE_X_DIVIDER_Pos) /*!< I2S0 TXRATE: X_DIVIDER Mask */ /* --------------------------------- I2S0_RXRATE -------------------------------- */ #define I2S0_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S0 RXRATE: Y_DIVIDER Position */ #define I2S0_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_Y_DIVIDER_Pos) /*!< I2S0 RXRATE: Y_DIVIDER Mask */ #define I2S0_RXRATE_X_DIVIDER_Pos 8 /*!< I2S0 RXRATE: X_DIVIDER Position */ #define I2S0_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S0_RXRATE_X_DIVIDER_Pos) /*!< I2S0 RXRATE: X_DIVIDER Mask */ /* ------------------------------- I2S0_TXBITRATE ------------------------------- */ #define I2S0_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S0 TXBITRATE: TX_BITRATE Position */ #define I2S0_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S0_TXBITRATE_TX_BITRATE_Pos) /*!< I2S0 TXBITRATE: TX_BITRATE Mask */ /* ------------------------------- I2S0_RXBITRATE ------------------------------- */ #define I2S0_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S0 RXBITRATE: RX_BITRATE Position */ #define I2S0_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S0_RXBITRATE_RX_BITRATE_Pos) /*!< I2S0 RXBITRATE: RX_BITRATE Mask */ /* --------------------------------- I2S0_TXMODE -------------------------------- */ #define I2S0_TXMODE_TXCLKSEL_Pos 0 /*!< I2S0 TXMODE: TXCLKSEL Position */ #define I2S0_TXMODE_TXCLKSEL_Msk (0x03UL << I2S0_TXMODE_TXCLKSEL_Pos) /*!< I2S0 TXMODE: TXCLKSEL Mask */ #define I2S0_TXMODE_TX4PIN_Pos 2 /*!< I2S0 TXMODE: TX4PIN Position */ #define I2S0_TXMODE_TX4PIN_Msk (0x01UL << I2S0_TXMODE_TX4PIN_Pos) /*!< I2S0 TXMODE: TX4PIN Mask */ #define I2S0_TXMODE_TXMCENA_Pos 3 /*!< I2S0 TXMODE: TXMCENA Position */ #define I2S0_TXMODE_TXMCENA_Msk (0x01UL << I2S0_TXMODE_TXMCENA_Pos) /*!< I2S0 TXMODE: TXMCENA Mask */ /* --------------------------------- I2S0_RXMODE -------------------------------- */ #define I2S0_RXMODE_RXCLKSEL_Pos 0 /*!< I2S0 RXMODE: RXCLKSEL Position */ #define I2S0_RXMODE_RXCLKSEL_Msk (0x03UL << I2S0_RXMODE_RXCLKSEL_Pos) /*!< I2S0 RXMODE: RXCLKSEL Mask */ #define I2S0_RXMODE_RX4PIN_Pos 2 /*!< I2S0 RXMODE: RX4PIN Position */ #define I2S0_RXMODE_RX4PIN_Msk (0x01UL << I2S0_RXMODE_RX4PIN_Pos) /*!< I2S0 RXMODE: RX4PIN Mask */ #define I2S0_RXMODE_RXMCENA_Pos 3 /*!< I2S0 RXMODE: RXMCENA Position */ #define I2S0_RXMODE_RXMCENA_Msk (0x01UL << I2S0_RXMODE_RXMCENA_Pos) /*!< I2S0 RXMODE: RXMCENA Mask */ /* ================================================================================ */ /* ================ struct 'I2S1' Position & Mask ================ */ /* ================================================================================ */ /* ---------------------------------- I2S1_DAO ---------------------------------- */ #define I2S1_DAO_WORDWIDTH_Pos 0 /*!< I2S1 DAO: WORDWIDTH Position */ #define I2S1_DAO_WORDWIDTH_Msk (0x03UL << I2S1_DAO_WORDWIDTH_Pos) /*!< I2S1 DAO: WORDWIDTH Mask */ #define I2S1_DAO_MONO_Pos 2 /*!< I2S1 DAO: MONO Position */ #define I2S1_DAO_MONO_Msk (0x01UL << I2S1_DAO_MONO_Pos) /*!< I2S1 DAO: MONO Mask */ #define I2S1_DAO_STOP_Pos 3 /*!< I2S1 DAO: STOP Position */ #define I2S1_DAO_STOP_Msk (0x01UL << I2S1_DAO_STOP_Pos) /*!< I2S1 DAO: STOP Mask */ #define I2S1_DAO_RESET_Pos 4 /*!< I2S1 DAO: RESET Position */ #define I2S1_DAO_RESET_Msk (0x01UL << I2S1_DAO_RESET_Pos) /*!< I2S1 DAO: RESET Mask */ #define I2S1_DAO_WS_SEL_Pos 5 /*!< I2S1 DAO: WS_SEL Position */ #define I2S1_DAO_WS_SEL_Msk (0x01UL << I2S1_DAO_WS_SEL_Pos) /*!< I2S1 DAO: WS_SEL Mask */ #define I2S1_DAO_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAO: WS_HALFPERIOD Position */ #define I2S1_DAO_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAO_WS_HALFPERIOD_Pos) /*!< I2S1 DAO: WS_HALFPERIOD Mask */ #define I2S1_DAO_MUTE_Pos 15 /*!< I2S1 DAO: MUTE Position */ #define I2S1_DAO_MUTE_Msk (0x01UL << I2S1_DAO_MUTE_Pos) /*!< I2S1 DAO: MUTE Mask */ /* ---------------------------------- I2S1_DAI ---------------------------------- */ #define I2S1_DAI_WORDWIDTH_Pos 0 /*!< I2S1 DAI: WORDWIDTH Position */ #define I2S1_DAI_WORDWIDTH_Msk (0x03UL << I2S1_DAI_WORDWIDTH_Pos) /*!< I2S1 DAI: WORDWIDTH Mask */ #define I2S1_DAI_MONO_Pos 2 /*!< I2S1 DAI: MONO Position */ #define I2S1_DAI_MONO_Msk (0x01UL << I2S1_DAI_MONO_Pos) /*!< I2S1 DAI: MONO Mask */ #define I2S1_DAI_STOP_Pos 3 /*!< I2S1 DAI: STOP Position */ #define I2S1_DAI_STOP_Msk (0x01UL << I2S1_DAI_STOP_Pos) /*!< I2S1 DAI: STOP Mask */ #define I2S1_DAI_RESET_Pos 4 /*!< I2S1 DAI: RESET Position */ #define I2S1_DAI_RESET_Msk (0x01UL << I2S1_DAI_RESET_Pos) /*!< I2S1 DAI: RESET Mask */ #define I2S1_DAI_WS_SEL_Pos 5 /*!< I2S1 DAI: WS_SEL Position */ #define I2S1_DAI_WS_SEL_Msk (0x01UL << I2S1_DAI_WS_SEL_Pos) /*!< I2S1 DAI: WS_SEL Mask */ #define I2S1_DAI_WS_HALFPERIOD_Pos 6 /*!< I2S1 DAI: WS_HALFPERIOD Position */ #define I2S1_DAI_WS_HALFPERIOD_Msk (0x000001ffUL << I2S1_DAI_WS_HALFPERIOD_Pos) /*!< I2S1 DAI: WS_HALFPERIOD Mask */ /* --------------------------------- I2S1_TXFIFO -------------------------------- */ #define I2S1_TXFIFO_I2STXFIFO_Pos 0 /*!< I2S1 TXFIFO: I2STXFIFO Position */ #define I2S1_TXFIFO_I2STXFIFO_Msk (0xffffffffUL << I2S1_TXFIFO_I2STXFIFO_Pos) /*!< I2S1 TXFIFO: I2STXFIFO Mask */ /* --------------------------------- I2S1_RXFIFO -------------------------------- */ #define I2S1_RXFIFO_I2SRXFIFO_Pos 0 /*!< I2S1 RXFIFO: I2SRXFIFO Position */ #define I2S1_RXFIFO_I2SRXFIFO_Msk (0xffffffffUL << I2S1_RXFIFO_I2SRXFIFO_Pos) /*!< I2S1 RXFIFO: I2SRXFIFO Mask */ /* --------------------------------- I2S1_STATE --------------------------------- */ #define I2S1_STATE_IRQ_Pos 0 /*!< I2S1 STATE: IRQ Position */ #define I2S1_STATE_IRQ_Msk (0x01UL << I2S1_STATE_IRQ_Pos) /*!< I2S1 STATE: IRQ Mask */ #define I2S1_STATE_DMAREQ1_Pos 1 /*!< I2S1 STATE: DMAREQ1 Position */ #define I2S1_STATE_DMAREQ1_Msk (0x01UL << I2S1_STATE_DMAREQ1_Pos) /*!< I2S1 STATE: DMAREQ1 Mask */ #define I2S1_STATE_DMAREQ2_Pos 2 /*!< I2S1 STATE: DMAREQ2 Position */ #define I2S1_STATE_DMAREQ2_Msk (0x01UL << I2S1_STATE_DMAREQ2_Pos) /*!< I2S1 STATE: DMAREQ2 Mask */ #define I2S1_STATE_RX_LEVEL_Pos 8 /*!< I2S1 STATE: RX_LEVEL Position */ #define I2S1_STATE_RX_LEVEL_Msk (0x0fUL << I2S1_STATE_RX_LEVEL_Pos) /*!< I2S1 STATE: RX_LEVEL Mask */ #define I2S1_STATE_TX_LEVEL_Pos 16 /*!< I2S1 STATE: TX_LEVEL Position */ #define I2S1_STATE_TX_LEVEL_Msk (0x0fUL << I2S1_STATE_TX_LEVEL_Pos) /*!< I2S1 STATE: TX_LEVEL Mask */ /* ---------------------------------- I2S1_DMA1 --------------------------------- */ #define I2S1_DMA1_RX_DMA1_ENABLE_Pos 0 /*!< I2S1 DMA1: RX_DMA1_ENABLE Position */ #define I2S1_DMA1_RX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_RX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: RX_DMA1_ENABLE Mask */ #define I2S1_DMA1_TX_DMA1_ENABLE_Pos 1 /*!< I2S1 DMA1: TX_DMA1_ENABLE Position */ #define I2S1_DMA1_TX_DMA1_ENABLE_Msk (0x01UL << I2S1_DMA1_TX_DMA1_ENABLE_Pos) /*!< I2S1 DMA1: TX_DMA1_ENABLE Mask */ #define I2S1_DMA1_RX_DEPTH_DMA1_Pos 8 /*!< I2S1 DMA1: RX_DEPTH_DMA1 Position */ #define I2S1_DMA1_RX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_RX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: RX_DEPTH_DMA1 Mask */ #define I2S1_DMA1_TX_DEPTH_DMA1_Pos 16 /*!< I2S1 DMA1: TX_DEPTH_DMA1 Position */ #define I2S1_DMA1_TX_DEPTH_DMA1_Msk (0x0fUL << I2S1_DMA1_TX_DEPTH_DMA1_Pos) /*!< I2S1 DMA1: TX_DEPTH_DMA1 Mask */ /* ---------------------------------- I2S1_DMA2 --------------------------------- */ #define I2S1_DMA2_RX_DMA2_ENABLE_Pos 0 /*!< I2S1 DMA2: RX_DMA2_ENABLE Position */ #define I2S1_DMA2_RX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_RX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: RX_DMA2_ENABLE Mask */ #define I2S1_DMA2_TX_DMA2_ENABLE_Pos 1 /*!< I2S1 DMA2: TX_DMA2_ENABLE Position */ #define I2S1_DMA2_TX_DMA2_ENABLE_Msk (0x01UL << I2S1_DMA2_TX_DMA2_ENABLE_Pos) /*!< I2S1 DMA2: TX_DMA2_ENABLE Mask */ #define I2S1_DMA2_RX_DEPTH_DMA2_Pos 8 /*!< I2S1 DMA2: RX_DEPTH_DMA2 Position */ #define I2S1_DMA2_RX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_RX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: RX_DEPTH_DMA2 Mask */ #define I2S1_DMA2_TX_DEPTH_DMA2_Pos 16 /*!< I2S1 DMA2: TX_DEPTH_DMA2 Position */ #define I2S1_DMA2_TX_DEPTH_DMA2_Msk (0x0fUL << I2S1_DMA2_TX_DEPTH_DMA2_Pos) /*!< I2S1 DMA2: TX_DEPTH_DMA2 Mask */ /* ---------------------------------- I2S1_IRQ ---------------------------------- */ #define I2S1_IRQ_RX_IRQ_ENABLE_Pos 0 /*!< I2S1 IRQ: RX_IRQ_ENABLE Position */ #define I2S1_IRQ_RX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_RX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: RX_IRQ_ENABLE Mask */ #define I2S1_IRQ_TX_IRQ_ENABLE_Pos 1 /*!< I2S1 IRQ: TX_IRQ_ENABLE Position */ #define I2S1_IRQ_TX_IRQ_ENABLE_Msk (0x01UL << I2S1_IRQ_TX_IRQ_ENABLE_Pos) /*!< I2S1 IRQ: TX_IRQ_ENABLE Mask */ #define I2S1_IRQ_RX_DEPTH_IRQ_Pos 8 /*!< I2S1 IRQ: RX_DEPTH_IRQ Position */ #define I2S1_IRQ_RX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_RX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: RX_DEPTH_IRQ Mask */ #define I2S1_IRQ_TX_DEPTH_IRQ_Pos 16 /*!< I2S1 IRQ: TX_DEPTH_IRQ Position */ #define I2S1_IRQ_TX_DEPTH_IRQ_Msk (0x0fUL << I2S1_IRQ_TX_DEPTH_IRQ_Pos) /*!< I2S1 IRQ: TX_DEPTH_IRQ Mask */ /* --------------------------------- I2S1_TXRATE -------------------------------- */ #define I2S1_TXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 TXRATE: Y_DIVIDER Position */ #define I2S1_TXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_Y_DIVIDER_Pos) /*!< I2S1 TXRATE: Y_DIVIDER Mask */ #define I2S1_TXRATE_X_DIVIDER_Pos 8 /*!< I2S1 TXRATE: X_DIVIDER Position */ #define I2S1_TXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_TXRATE_X_DIVIDER_Pos) /*!< I2S1 TXRATE: X_DIVIDER Mask */ /* --------------------------------- I2S1_RXRATE -------------------------------- */ #define I2S1_RXRATE_Y_DIVIDER_Pos 0 /*!< I2S1 RXRATE: Y_DIVIDER Position */ #define I2S1_RXRATE_Y_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_Y_DIVIDER_Pos) /*!< I2S1 RXRATE: Y_DIVIDER Mask */ #define I2S1_RXRATE_X_DIVIDER_Pos 8 /*!< I2S1 RXRATE: X_DIVIDER Position */ #define I2S1_RXRATE_X_DIVIDER_Msk (0x000000ffUL << I2S1_RXRATE_X_DIVIDER_Pos) /*!< I2S1 RXRATE: X_DIVIDER Mask */ /* ------------------------------- I2S1_TXBITRATE ------------------------------- */ #define I2S1_TXBITRATE_TX_BITRATE_Pos 0 /*!< I2S1 TXBITRATE: TX_BITRATE Position */ #define I2S1_TXBITRATE_TX_BITRATE_Msk (0x3fUL << I2S1_TXBITRATE_TX_BITRATE_Pos) /*!< I2S1 TXBITRATE: TX_BITRATE Mask */ /* ------------------------------- I2S1_RXBITRATE ------------------------------- */ #define I2S1_RXBITRATE_RX_BITRATE_Pos 0 /*!< I2S1 RXBITRATE: RX_BITRATE Position */ #define I2S1_RXBITRATE_RX_BITRATE_Msk (0x3fUL << I2S1_RXBITRATE_RX_BITRATE_Pos) /*!< I2S1 RXBITRATE: RX_BITRATE Mask */ /* --------------------------------- I2S1_TXMODE -------------------------------- */ #define I2S1_TXMODE_TXCLKSEL_Pos 0 /*!< I2S1 TXMODE: TXCLKSEL Position */ #define I2S1_TXMODE_TXCLKSEL_Msk (0x03UL << I2S1_TXMODE_TXCLKSEL_Pos) /*!< I2S1 TXMODE: TXCLKSEL Mask */ #define I2S1_TXMODE_TX4PIN_Pos 2 /*!< I2S1 TXMODE: TX4PIN Position */ #define I2S1_TXMODE_TX4PIN_Msk (0x01UL << I2S1_TXMODE_TX4PIN_Pos) /*!< I2S1 TXMODE: TX4PIN Mask */ #define I2S1_TXMODE_TXMCENA_Pos 3 /*!< I2S1 TXMODE: TXMCENA Position */ #define I2S1_TXMODE_TXMCENA_Msk (0x01UL << I2S1_TXMODE_TXMCENA_Pos) /*!< I2S1 TXMODE: TXMCENA Mask */ /* --------------------------------- I2S1_RXMODE -------------------------------- */ #define I2S1_RXMODE_RXCLKSEL_Pos 0 /*!< I2S1 RXMODE: RXCLKSEL Position */ #define I2S1_RXMODE_RXCLKSEL_Msk (0x03UL << I2S1_RXMODE_RXCLKSEL_Pos) /*!< I2S1 RXMODE: RXCLKSEL Mask */ #define I2S1_RXMODE_RX4PIN_Pos 2 /*!< I2S1 RXMODE: RX4PIN Position */ #define I2S1_RXMODE_RX4PIN_Msk (0x01UL << I2S1_RXMODE_RX4PIN_Pos) /*!< I2S1 RXMODE: RX4PIN Mask */ #define I2S1_RXMODE_RXMCENA_Pos 3 /*!< I2S1 RXMODE: RXMCENA Position */ #define I2S1_RXMODE_RXMCENA_Msk (0x01UL << I2S1_RXMODE_RXMCENA_Pos) /*!< I2S1 RXMODE: RXMCENA Mask */ /* ================================================================================ */ /* ================ Group 'C_CANn' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- C_CANn_CNTL -------------------------------- */ #define C_CANn_CNTL_INIT_Pos 0 /*!< C_CANn CNTL: INIT Position */ #define C_CANn_CNTL_INIT_Msk (0x01UL << C_CANn_CNTL_INIT_Pos) /*!< C_CANn CNTL: INIT Mask */ #define C_CANn_CNTL_IE_Pos 1 /*!< C_CANn CNTL: IE Position */ #define C_CANn_CNTL_IE_Msk (0x01UL << C_CANn_CNTL_IE_Pos) /*!< C_CANn CNTL: IE Mask */ #define C_CANn_CNTL_SIE_Pos 2 /*!< C_CANn CNTL: SIE Position */ #define C_CANn_CNTL_SIE_Msk (0x01UL << C_CANn_CNTL_SIE_Pos) /*!< C_CANn CNTL: SIE Mask */ #define C_CANn_CNTL_EIE_Pos 3 /*!< C_CANn CNTL: EIE Position */ #define C_CANn_CNTL_EIE_Msk (0x01UL << C_CANn_CNTL_EIE_Pos) /*!< C_CANn CNTL: EIE Mask */ #define C_CANn_CNTL_DAR_Pos 5 /*!< C_CANn CNTL: DAR Position */ #define C_CANn_CNTL_DAR_Msk (0x01UL << C_CANn_CNTL_DAR_Pos) /*!< C_CANn CNTL: DAR Mask */ #define C_CANn_CNTL_CCE_Pos 6 /*!< C_CANn CNTL: CCE Position */ #define C_CANn_CNTL_CCE_Msk (0x01UL << C_CANn_CNTL_CCE_Pos) /*!< C_CANn CNTL: CCE Mask */ #define C_CANn_CNTL_TEST_Pos 7 /*!< C_CANn CNTL: TEST Position */ #define C_CANn_CNTL_TEST_Msk (0x01UL << C_CANn_CNTL_TEST_Pos) /*!< C_CANn CNTL: TEST Mask */ /* --------------------------------- C_CANn_STAT -------------------------------- */ #define C_CANn_STAT_LEC_Pos 0 /*!< C_CANn STAT: LEC Position */ #define C_CANn_STAT_LEC_Msk (0x07UL << C_CANn_STAT_LEC_Pos) /*!< C_CANn STAT: LEC Mask */ #define C_CANn_STAT_TXOK_Pos 3 /*!< C_CANn STAT: TXOK Position */ #define C_CANn_STAT_TXOK_Msk (0x01UL << C_CANn_STAT_TXOK_Pos) /*!< C_CANn STAT: TXOK Mask */ #define C_CANn_STAT_RXOK_Pos 4 /*!< C_CANn STAT: RXOK Position */ #define C_CANn_STAT_RXOK_Msk (0x01UL << C_CANn_STAT_RXOK_Pos) /*!< C_CANn STAT: RXOK Mask */ #define C_CANn_STAT_EPASS_Pos 5 /*!< C_CANn STAT: EPASS Position */ #define C_CANn_STAT_EPASS_Msk (0x01UL << C_CANn_STAT_EPASS_Pos) /*!< C_CANn STAT: EPASS Mask */ #define C_CANn_STAT_EWARN_Pos 6 /*!< C_CANn STAT: EWARN Position */ #define C_CANn_STAT_EWARN_Msk (0x01UL << C_CANn_STAT_EWARN_Pos) /*!< C_CANn STAT: EWARN Mask */ #define C_CANn_STAT_BOFF_Pos 7 /*!< C_CANn STAT: BOFF Position */ #define C_CANn_STAT_BOFF_Msk (0x01UL << C_CANn_STAT_BOFF_Pos) /*!< C_CANn STAT: BOFF Mask */ /* ---------------------------------- C_CANn_EC --------------------------------- */ #define C_CANn_EC_TEC_7_0_Pos 0 /*!< C_CANn EC: TEC_7_0 Position */ #define C_CANn_EC_TEC_7_0_Msk (0x000000ffUL << C_CANn_EC_TEC_7_0_Pos) /*!< C_CANn EC: TEC_7_0 Mask */ #define C_CANn_EC_REC_6_0_Pos 8 /*!< C_CANn EC: REC_6_0 Position */ #define C_CANn_EC_REC_6_0_Msk (0x7fUL << C_CANn_EC_REC_6_0_Pos) /*!< C_CANn EC: REC_6_0 Mask */ #define C_CANn_EC_RP_Pos 15 /*!< C_CANn EC: RP Position */ #define C_CANn_EC_RP_Msk (0x01UL << C_CANn_EC_RP_Pos) /*!< C_CANn EC: RP Mask */ /* ---------------------------------- C_CANn_BT --------------------------------- */ #define C_CANn_BT_BRP_Pos 0 /*!< C_CANn BT: BRP Position */ #define C_CANn_BT_BRP_Msk (0x3fUL << C_CANn_BT_BRP_Pos) /*!< C_CANn BT: BRP Mask */ #define C_CANn_BT_SJW_Pos 6 /*!< C_CANn BT: SJW Position */ #define C_CANn_BT_SJW_Msk (0x03UL << C_CANn_BT_SJW_Pos) /*!< C_CANn BT: SJW Mask */ #define C_CANn_BT_TSEG1_Pos 8 /*!< C_CANn BT: TSEG1 Position */ #define C_CANn_BT_TSEG1_Msk (0x0fUL << C_CANn_BT_TSEG1_Pos) /*!< C_CANn BT: TSEG1 Mask */ #define C_CANn_BT_TSEG2_Pos 12 /*!< C_CANn BT: TSEG2 Position */ #define C_CANn_BT_TSEG2_Msk (0x07UL << C_CANn_BT_TSEG2_Pos) /*!< C_CANn BT: TSEG2 Mask */ /* --------------------------------- C_CANn_INT --------------------------------- */ #define C_CANn_INT_INTID15_0_Pos 0 /*!< C_CANn INT: INTID15_0 Position */ #define C_CANn_INT_INTID15_0_Msk (0x0000ffffUL << C_CANn_INT_INTID15_0_Pos) /*!< C_CANn INT: INTID15_0 Mask */ /* --------------------------------- C_CANn_TEST -------------------------------- */ #define C_CANn_TEST_BASIC_Pos 2 /*!< C_CANn TEST: BASIC Position */ #define C_CANn_TEST_BASIC_Msk (0x01UL << C_CANn_TEST_BASIC_Pos) /*!< C_CANn TEST: BASIC Mask */ #define C_CANn_TEST_SILENT_Pos 3 /*!< C_CANn TEST: SILENT Position */ #define C_CANn_TEST_SILENT_Msk (0x01UL << C_CANn_TEST_SILENT_Pos) /*!< C_CANn TEST: SILENT Mask */ #define C_CANn_TEST_LBACK_Pos 4 /*!< C_CANn TEST: LBACK Position */ #define C_CANn_TEST_LBACK_Msk (0x01UL << C_CANn_TEST_LBACK_Pos) /*!< C_CANn TEST: LBACK Mask */ #define C_CANn_TEST_TX1_0_Pos 5 /*!< C_CANn TEST: TX1_0 Position */ #define C_CANn_TEST_TX1_0_Msk (0x03UL << C_CANn_TEST_TX1_0_Pos) /*!< C_CANn TEST: TX1_0 Mask */ #define C_CANn_TEST_RX_Pos 7 /*!< C_CANn TEST: RX Position */ #define C_CANn_TEST_RX_Msk (0x01UL << C_CANn_TEST_RX_Pos) /*!< C_CANn TEST: RX Mask */ /* --------------------------------- C_CANn_BRPE -------------------------------- */ #define C_CANn_BRPE_BRPE_Pos 0 /*!< C_CANn BRPE: BRPE Position */ #define C_CANn_BRPE_BRPE_Msk (0x0fUL << C_CANn_BRPE_BRPE_Pos) /*!< C_CANn BRPE: BRPE Mask */ /* ------------------------------ C_CANn_IF1_CMDREQ ----------------------------- */ #define C_CANn_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CANn IF1_CMDREQ: MESSNUM Position */ #define C_CANn_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CANn_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CANn IF1_CMDREQ: MESSNUM Mask */ #define C_CANn_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CANn IF1_CMDREQ: BUSY Position */ #define C_CANn_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CANn_IF1_CMDREQ_BUSY_Pos) /*!< C_CANn IF1_CMDREQ: BUSY Mask */ /* ----------------------------- C_CANn_IF1_CMDMSK_W ---------------------------- */ #define C_CANn_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CANn IF1_CMDMSK_W: DATA_B Position */ #define C_CANn_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CANn IF1_CMDMSK_W: DATA_B Mask */ #define C_CANn_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CANn IF1_CMDMSK_W: DATA_A Position */ #define C_CANn_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CANn IF1_CMDMSK_W: DATA_A Mask */ #define C_CANn_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CANn IF1_CMDMSK_W: TXRQST Position */ #define C_CANn_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CANn IF1_CMDMSK_W: TXRQST Mask */ #define C_CANn_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CANn IF1_CMDMSK_W: CLRINTPND Position */ #define C_CANn_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CANn IF1_CMDMSK_W: CLRINTPND Mask */ #define C_CANn_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CANn IF1_CMDMSK_W: CTRL Position */ #define C_CANn_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CANn IF1_CMDMSK_W: CTRL Mask */ #define C_CANn_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CANn IF1_CMDMSK_W: ARB Position */ #define C_CANn_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_ARB_Pos) /*!< C_CANn IF1_CMDMSK_W: ARB Mask */ #define C_CANn_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CANn IF1_CMDMSK_W: MASK Position */ #define C_CANn_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_MASK_Pos) /*!< C_CANn IF1_CMDMSK_W: MASK Mask */ #define C_CANn_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CANn IF1_CMDMSK_W: WR_RD Position */ #define C_CANn_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CANn_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CANn IF1_CMDMSK_W: WR_RD Mask */ /* ----------------------------- C_CANn_IF1_CMDMSK_R ---------------------------- */ #define C_CANn_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CANn IF1_CMDMSK_R: DATA_B Position */ #define C_CANn_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CANn IF1_CMDMSK_R: DATA_B Mask */ #define C_CANn_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CANn IF1_CMDMSK_R: DATA_A Position */ #define C_CANn_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CANn IF1_CMDMSK_R: DATA_A Mask */ #define C_CANn_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CANn IF1_CMDMSK_R: NEWDAT Position */ #define C_CANn_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CANn IF1_CMDMSK_R: NEWDAT Mask */ #define C_CANn_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CANn IF1_CMDMSK_R: CLRINTPND Position */ #define C_CANn_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CANn IF1_CMDMSK_R: CLRINTPND Mask */ #define C_CANn_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CANn IF1_CMDMSK_R: CTRL Position */ #define C_CANn_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CANn IF1_CMDMSK_R: CTRL Mask */ #define C_CANn_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CANn IF1_CMDMSK_R: ARB Position */ #define C_CANn_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_ARB_Pos) /*!< C_CANn IF1_CMDMSK_R: ARB Mask */ #define C_CANn_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CANn IF1_CMDMSK_R: MASK Position */ #define C_CANn_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_MASK_Pos) /*!< C_CANn IF1_CMDMSK_R: MASK Mask */ #define C_CANn_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CANn IF1_CMDMSK_R: WR_RD Position */ #define C_CANn_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CANn_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CANn IF1_CMDMSK_R: WR_RD Mask */ /* ------------------------------- C_CANn_IF1_MSK1 ------------------------------ */ #define C_CANn_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CANn IF1_MSK1: MSK15_0 Position */ #define C_CANn_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CANn_IF1_MSK1_MSK15_0_Pos) /*!< C_CANn IF1_MSK1: MSK15_0 Mask */ /* ------------------------------- C_CANn_IF1_MSK2 ------------------------------ */ #define C_CANn_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CANn IF1_MSK2: MSK28_16 Position */ #define C_CANn_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CANn_IF1_MSK2_MSK28_16_Pos) /*!< C_CANn IF1_MSK2: MSK28_16 Mask */ #define C_CANn_IF1_MSK2_MDIR_Pos 14 /*!< C_CANn IF1_MSK2: MDIR Position */ #define C_CANn_IF1_MSK2_MDIR_Msk (0x01UL << C_CANn_IF1_MSK2_MDIR_Pos) /*!< C_CANn IF1_MSK2: MDIR Mask */ #define C_CANn_IF1_MSK2_MXTD_Pos 15 /*!< C_CANn IF1_MSK2: MXTD Position */ #define C_CANn_IF1_MSK2_MXTD_Msk (0x01UL << C_CANn_IF1_MSK2_MXTD_Pos) /*!< C_CANn IF1_MSK2: MXTD Mask */ /* ------------------------------- C_CANn_IF1_ARB1 ------------------------------ */ #define C_CANn_IF1_ARB1_ID15_0_Pos 0 /*!< C_CANn IF1_ARB1: ID15_0 Position */ #define C_CANn_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CANn_IF1_ARB1_ID15_0_Pos) /*!< C_CANn IF1_ARB1: ID15_0 Mask */ /* ------------------------------- C_CANn_IF1_ARB2 ------------------------------ */ #define C_CANn_IF1_ARB2_ID28_16_Pos 0 /*!< C_CANn IF1_ARB2: ID28_16 Position */ #define C_CANn_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CANn_IF1_ARB2_ID28_16_Pos) /*!< C_CANn IF1_ARB2: ID28_16 Mask */ #define C_CANn_IF1_ARB2_DIR_Pos 13 /*!< C_CANn IF1_ARB2: DIR Position */ #define C_CANn_IF1_ARB2_DIR_Msk (0x01UL << C_CANn_IF1_ARB2_DIR_Pos) /*!< C_CANn IF1_ARB2: DIR Mask */ #define C_CANn_IF1_ARB2_XTD_Pos 14 /*!< C_CANn IF1_ARB2: XTD Position */ #define C_CANn_IF1_ARB2_XTD_Msk (0x01UL << C_CANn_IF1_ARB2_XTD_Pos) /*!< C_CANn IF1_ARB2: XTD Mask */ #define C_CANn_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CANn IF1_ARB2: MSGVAL Position */ #define C_CANn_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CANn_IF1_ARB2_MSGVAL_Pos) /*!< C_CANn IF1_ARB2: MSGVAL Mask */ /* ------------------------------ C_CANn_IF1_MCTRL ------------------------------ */ #define C_CANn_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CANn IF1_MCTRL: DLC3_0 Position */ #define C_CANn_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CANn_IF1_MCTRL_DLC3_0_Pos) /*!< C_CANn IF1_MCTRL: DLC3_0 Mask */ #define C_CANn_IF1_MCTRL_EOB_Pos 7 /*!< C_CANn IF1_MCTRL: EOB Position */ #define C_CANn_IF1_MCTRL_EOB_Msk (0x01UL << C_CANn_IF1_MCTRL_EOB_Pos) /*!< C_CANn IF1_MCTRL: EOB Mask */ #define C_CANn_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CANn IF1_MCTRL: TXRQST Position */ #define C_CANn_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CANn_IF1_MCTRL_TXRQST_Pos) /*!< C_CANn IF1_MCTRL: TXRQST Mask */ #define C_CANn_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CANn IF1_MCTRL: RMTEN Position */ #define C_CANn_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CANn_IF1_MCTRL_RMTEN_Pos) /*!< C_CANn IF1_MCTRL: RMTEN Mask */ #define C_CANn_IF1_MCTRL_RXIE_Pos 10 /*!< C_CANn IF1_MCTRL: RXIE Position */ #define C_CANn_IF1_MCTRL_RXIE_Msk (0x01UL << C_CANn_IF1_MCTRL_RXIE_Pos) /*!< C_CANn IF1_MCTRL: RXIE Mask */ #define C_CANn_IF1_MCTRL_TXIE_Pos 11 /*!< C_CANn IF1_MCTRL: TXIE Position */ #define C_CANn_IF1_MCTRL_TXIE_Msk (0x01UL << C_CANn_IF1_MCTRL_TXIE_Pos) /*!< C_CANn IF1_MCTRL: TXIE Mask */ #define C_CANn_IF1_MCTRL_UMASK_Pos 12 /*!< C_CANn IF1_MCTRL: UMASK Position */ #define C_CANn_IF1_MCTRL_UMASK_Msk (0x01UL << C_CANn_IF1_MCTRL_UMASK_Pos) /*!< C_CANn IF1_MCTRL: UMASK Mask */ #define C_CANn_IF1_MCTRL_INTPND_Pos 13 /*!< C_CANn IF1_MCTRL: INTPND Position */ #define C_CANn_IF1_MCTRL_INTPND_Msk (0x01UL << C_CANn_IF1_MCTRL_INTPND_Pos) /*!< C_CANn IF1_MCTRL: INTPND Mask */ #define C_CANn_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CANn IF1_MCTRL: MSGLST Position */ #define C_CANn_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CANn_IF1_MCTRL_MSGLST_Pos) /*!< C_CANn IF1_MCTRL: MSGLST Mask */ #define C_CANn_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CANn IF1_MCTRL: NEWDAT Position */ #define C_CANn_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CANn_IF1_MCTRL_NEWDAT_Pos) /*!< C_CANn IF1_MCTRL: NEWDAT Mask */ /* ------------------------------- C_CANn_IF1_DA1 ------------------------------- */ #define C_CANn_IF1_DA1_DATA0_Pos 0 /*!< C_CANn IF1_DA1: DATA0 Position */ #define C_CANn_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CANn_IF1_DA1_DATA0_Pos) /*!< C_CANn IF1_DA1: DATA0 Mask */ #define C_CANn_IF1_DA1_DATA1_Pos 8 /*!< C_CANn IF1_DA1: DATA1 Position */ #define C_CANn_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CANn_IF1_DA1_DATA1_Pos) /*!< C_CANn IF1_DA1: DATA1 Mask */ /* ------------------------------- C_CANn_IF1_DA2 ------------------------------- */ #define C_CANn_IF1_DA2_DATA2_Pos 0 /*!< C_CANn IF1_DA2: DATA2 Position */ #define C_CANn_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CANn_IF1_DA2_DATA2_Pos) /*!< C_CANn IF1_DA2: DATA2 Mask */ #define C_CANn_IF1_DA2_DATA3_Pos 8 /*!< C_CANn IF1_DA2: DATA3 Position */ #define C_CANn_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CANn_IF1_DA2_DATA3_Pos) /*!< C_CANn IF1_DA2: DATA3 Mask */ /* ------------------------------- C_CANn_IF1_DB1 ------------------------------- */ #define C_CANn_IF1_DB1_DATA4_Pos 0 /*!< C_CANn IF1_DB1: DATA4 Position */ #define C_CANn_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CANn_IF1_DB1_DATA4_Pos) /*!< C_CANn IF1_DB1: DATA4 Mask */ #define C_CANn_IF1_DB1_DATA5_Pos 8 /*!< C_CANn IF1_DB1: DATA5 Position */ #define C_CANn_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CANn_IF1_DB1_DATA5_Pos) /*!< C_CANn IF1_DB1: DATA5 Mask */ /* ------------------------------- C_CANn_IF1_DB2 ------------------------------- */ #define C_CANn_IF1_DB2_DATA6_Pos 0 /*!< C_CANn IF1_DB2: DATA6 Position */ #define C_CANn_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CANn_IF1_DB2_DATA6_Pos) /*!< C_CANn IF1_DB2: DATA6 Mask */ #define C_CANn_IF1_DB2_DATA7_Pos 8 /*!< C_CANn IF1_DB2: DATA7 Position */ #define C_CANn_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CANn_IF1_DB2_DATA7_Pos) /*!< C_CANn IF1_DB2: DATA7 Mask */ /* ------------------------------ C_CANn_IF2_CMDREQ ----------------------------- */ #define C_CANn_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CANn IF2_CMDREQ: MESSNUM Position */ #define C_CANn_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CANn_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CANn IF2_CMDREQ: MESSNUM Mask */ #define C_CANn_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CANn IF2_CMDREQ: BUSY Position */ #define C_CANn_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CANn_IF2_CMDREQ_BUSY_Pos) /*!< C_CANn IF2_CMDREQ: BUSY Mask */ /* ----------------------------- C_CANn_IF2_CMDMSK_W ---------------------------- */ #define C_CANn_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CANn IF2_CMDMSK_W: DATA_B Position */ #define C_CANn_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CANn IF2_CMDMSK_W: DATA_B Mask */ #define C_CANn_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CANn IF2_CMDMSK_W: DATA_A Position */ #define C_CANn_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CANn IF2_CMDMSK_W: DATA_A Mask */ #define C_CANn_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CANn IF2_CMDMSK_W: TXRQST Position */ #define C_CANn_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CANn IF2_CMDMSK_W: TXRQST Mask */ #define C_CANn_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CANn IF2_CMDMSK_W: CLRINTPND Position */ #define C_CANn_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CANn IF2_CMDMSK_W: CLRINTPND Mask */ #define C_CANn_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CANn IF2_CMDMSK_W: CTRL Position */ #define C_CANn_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CANn IF2_CMDMSK_W: CTRL Mask */ #define C_CANn_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CANn IF2_CMDMSK_W: ARB Position */ #define C_CANn_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_ARB_Pos) /*!< C_CANn IF2_CMDMSK_W: ARB Mask */ #define C_CANn_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CANn IF2_CMDMSK_W: MASK Position */ #define C_CANn_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_MASK_Pos) /*!< C_CANn IF2_CMDMSK_W: MASK Mask */ #define C_CANn_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CANn IF2_CMDMSK_W: WR_RD Position */ #define C_CANn_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CANn_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CANn IF2_CMDMSK_W: WR_RD Mask */ /* ----------------------------- C_CANn_IF2_CMDMSK_R ---------------------------- */ #define C_CANn_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CANn IF2_CMDMSK_R: DATA_B Position */ #define C_CANn_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CANn IF2_CMDMSK_R: DATA_B Mask */ #define C_CANn_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CANn IF2_CMDMSK_R: DATA_A Position */ #define C_CANn_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CANn IF2_CMDMSK_R: DATA_A Mask */ #define C_CANn_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CANn IF2_CMDMSK_R: NEWDAT Position */ #define C_CANn_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CANn IF2_CMDMSK_R: NEWDAT Mask */ #define C_CANn_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CANn IF2_CMDMSK_R: CLRINTPND Position */ #define C_CANn_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CANn IF2_CMDMSK_R: CLRINTPND Mask */ #define C_CANn_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CANn IF2_CMDMSK_R: CTRL Position */ #define C_CANn_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CANn IF2_CMDMSK_R: CTRL Mask */ #define C_CANn_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CANn IF2_CMDMSK_R: ARB Position */ #define C_CANn_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_ARB_Pos) /*!< C_CANn IF2_CMDMSK_R: ARB Mask */ #define C_CANn_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CANn IF2_CMDMSK_R: MASK Position */ #define C_CANn_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_MASK_Pos) /*!< C_CANn IF2_CMDMSK_R: MASK Mask */ #define C_CANn_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CANn IF2_CMDMSK_R: WR_RD Position */ #define C_CANn_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CANn_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CANn IF2_CMDMSK_R: WR_RD Mask */ /* ------------------------------- C_CANn_IF2_MSK1 ------------------------------ */ #define C_CANn_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CANn IF2_MSK1: MSK15_0 Position */ #define C_CANn_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CANn_IF2_MSK1_MSK15_0_Pos) /*!< C_CANn IF2_MSK1: MSK15_0 Mask */ /* ------------------------------- C_CANn_IF2_MSK2 ------------------------------ */ #define C_CANn_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CANn IF2_MSK2: MSK28_16 Position */ #define C_CANn_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CANn_IF2_MSK2_MSK28_16_Pos) /*!< C_CANn IF2_MSK2: MSK28_16 Mask */ #define C_CANn_IF2_MSK2_MDIR_Pos 14 /*!< C_CANn IF2_MSK2: MDIR Position */ #define C_CANn_IF2_MSK2_MDIR_Msk (0x01UL << C_CANn_IF2_MSK2_MDIR_Pos) /*!< C_CANn IF2_MSK2: MDIR Mask */ #define C_CANn_IF2_MSK2_MXTD_Pos 15 /*!< C_CANn IF2_MSK2: MXTD Position */ #define C_CANn_IF2_MSK2_MXTD_Msk (0x01UL << C_CANn_IF2_MSK2_MXTD_Pos) /*!< C_CANn IF2_MSK2: MXTD Mask */ /* ------------------------------- C_CANn_IF2_ARB1 ------------------------------ */ #define C_CANn_IF2_ARB1_ID15_0_Pos 0 /*!< C_CANn IF2_ARB1: ID15_0 Position */ #define C_CANn_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CANn_IF2_ARB1_ID15_0_Pos) /*!< C_CANn IF2_ARB1: ID15_0 Mask */ /* ------------------------------- C_CANn_IF2_ARB2 ------------------------------ */ #define C_CANn_IF2_ARB2_ID28_16_Pos 0 /*!< C_CANn IF2_ARB2: ID28_16 Position */ #define C_CANn_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CANn_IF2_ARB2_ID28_16_Pos) /*!< C_CANn IF2_ARB2: ID28_16 Mask */ #define C_CANn_IF2_ARB2_DIR_Pos 13 /*!< C_CANn IF2_ARB2: DIR Position */ #define C_CANn_IF2_ARB2_DIR_Msk (0x01UL << C_CANn_IF2_ARB2_DIR_Pos) /*!< C_CANn IF2_ARB2: DIR Mask */ #define C_CANn_IF2_ARB2_XTD_Pos 14 /*!< C_CANn IF2_ARB2: XTD Position */ #define C_CANn_IF2_ARB2_XTD_Msk (0x01UL << C_CANn_IF2_ARB2_XTD_Pos) /*!< C_CANn IF2_ARB2: XTD Mask */ #define C_CANn_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CANn IF2_ARB2: MSGVAL Position */ #define C_CANn_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CANn_IF2_ARB2_MSGVAL_Pos) /*!< C_CANn IF2_ARB2: MSGVAL Mask */ /* ------------------------------ C_CANn_IF2_MCTRL ------------------------------ */ #define C_CANn_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CANn IF2_MCTRL: DLC3_0 Position */ #define C_CANn_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CANn_IF2_MCTRL_DLC3_0_Pos) /*!< C_CANn IF2_MCTRL: DLC3_0 Mask */ #define C_CANn_IF2_MCTRL_EOB_Pos 7 /*!< C_CANn IF2_MCTRL: EOB Position */ #define C_CANn_IF2_MCTRL_EOB_Msk (0x01UL << C_CANn_IF2_MCTRL_EOB_Pos) /*!< C_CANn IF2_MCTRL: EOB Mask */ #define C_CANn_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CANn IF2_MCTRL: TXRQST Position */ #define C_CANn_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CANn_IF2_MCTRL_TXRQST_Pos) /*!< C_CANn IF2_MCTRL: TXRQST Mask */ #define C_CANn_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CANn IF2_MCTRL: RMTEN Position */ #define C_CANn_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CANn_IF2_MCTRL_RMTEN_Pos) /*!< C_CANn IF2_MCTRL: RMTEN Mask */ #define C_CANn_IF2_MCTRL_RXIE_Pos 10 /*!< C_CANn IF2_MCTRL: RXIE Position */ #define C_CANn_IF2_MCTRL_RXIE_Msk (0x01UL << C_CANn_IF2_MCTRL_RXIE_Pos) /*!< C_CANn IF2_MCTRL: RXIE Mask */ #define C_CANn_IF2_MCTRL_TXIE_Pos 11 /*!< C_CANn IF2_MCTRL: TXIE Position */ #define C_CANn_IF2_MCTRL_TXIE_Msk (0x01UL << C_CANn_IF2_MCTRL_TXIE_Pos) /*!< C_CANn IF2_MCTRL: TXIE Mask */ #define C_CANn_IF2_MCTRL_UMASK_Pos 12 /*!< C_CANn IF2_MCTRL: UMASK Position */ #define C_CANn_IF2_MCTRL_UMASK_Msk (0x01UL << C_CANn_IF2_MCTRL_UMASK_Pos) /*!< C_CANn IF2_MCTRL: UMASK Mask */ #define C_CANn_IF2_MCTRL_INTPND_Pos 13 /*!< C_CANn IF2_MCTRL: INTPND Position */ #define C_CANn_IF2_MCTRL_INTPND_Msk (0x01UL << C_CANn_IF2_MCTRL_INTPND_Pos) /*!< C_CANn IF2_MCTRL: INTPND Mask */ #define C_CANn_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CANn IF2_MCTRL: MSGLST Position */ #define C_CANn_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CANn_IF2_MCTRL_MSGLST_Pos) /*!< C_CANn IF2_MCTRL: MSGLST Mask */ #define C_CANn_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CANn IF2_MCTRL: NEWDAT Position */ #define C_CANn_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CANn_IF2_MCTRL_NEWDAT_Pos) /*!< C_CANn IF2_MCTRL: NEWDAT Mask */ /* ------------------------------- C_CANn_IF2_DA1 ------------------------------- */ #define C_CANn_IF2_DA1_DATA0_Pos 0 /*!< C_CANn IF2_DA1: DATA0 Position */ #define C_CANn_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CANn_IF2_DA1_DATA0_Pos) /*!< C_CANn IF2_DA1: DATA0 Mask */ #define C_CANn_IF2_DA1_DATA1_Pos 8 /*!< C_CANn IF2_DA1: DATA1 Position */ #define C_CANn_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CANn_IF2_DA1_DATA1_Pos) /*!< C_CANn IF2_DA1: DATA1 Mask */ /* ------------------------------- C_CANn_IF2_DA2 ------------------------------- */ #define C_CANn_IF2_DA2_DATA2_Pos 0 /*!< C_CANn IF2_DA2: DATA2 Position */ #define C_CANn_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CANn_IF2_DA2_DATA2_Pos) /*!< C_CANn IF2_DA2: DATA2 Mask */ #define C_CANn_IF2_DA2_DATA3_Pos 8 /*!< C_CANn IF2_DA2: DATA3 Position */ #define C_CANn_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CANn_IF2_DA2_DATA3_Pos) /*!< C_CANn IF2_DA2: DATA3 Mask */ /* ------------------------------- C_CANn_IF2_DB1 ------------------------------- */ #define C_CANn_IF2_DB1_DATA4_Pos 0 /*!< C_CANn IF2_DB1: DATA4 Position */ #define C_CANn_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CANn_IF2_DB1_DATA4_Pos) /*!< C_CANn IF2_DB1: DATA4 Mask */ #define C_CANn_IF2_DB1_DATA5_Pos 8 /*!< C_CANn IF2_DB1: DATA5 Position */ #define C_CANn_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CANn_IF2_DB1_DATA5_Pos) /*!< C_CANn IF2_DB1: DATA5 Mask */ /* ------------------------------- C_CANn_IF2_DB2 ------------------------------- */ #define C_CANn_IF2_DB2_DATA6_Pos 0 /*!< C_CANn IF2_DB2: DATA6 Position */ #define C_CANn_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CANn_IF2_DB2_DATA6_Pos) /*!< C_CANn IF2_DB2: DATA6 Mask */ #define C_CANn_IF2_DB2_DATA7_Pos 8 /*!< C_CANn IF2_DB2: DATA7 Position */ #define C_CANn_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CANn_IF2_DB2_DATA7_Pos) /*!< C_CANn IF2_DB2: DATA7 Mask */ /* -------------------------------- C_CANn_TXREQ1 ------------------------------- */ #define C_CANn_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CANn TXREQ1: TXRQST16_1 Position */ #define C_CANn_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CANn_TXREQ1_TXRQST16_1_Pos) /*!< C_CANn TXREQ1: TXRQST16_1 Mask */ /* -------------------------------- C_CANn_TXREQ2 ------------------------------- */ #define C_CANn_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CANn TXREQ2: TXRQST32_17 Position */ #define C_CANn_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CANn_TXREQ2_TXRQST32_17_Pos) /*!< C_CANn TXREQ2: TXRQST32_17 Mask */ /* --------------------------------- C_CANn_ND1 --------------------------------- */ #define C_CANn_ND1_NEWDAT16_1_Pos 0 /*!< C_CANn ND1: NEWDAT16_1 Position */ #define C_CANn_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CANn_ND1_NEWDAT16_1_Pos) /*!< C_CANn ND1: NEWDAT16_1 Mask */ /* --------------------------------- C_CANn_ND2 --------------------------------- */ #define C_CANn_ND2_NEWDAT32_17_Pos 0 /*!< C_CANn ND2: NEWDAT32_17 Position */ #define C_CANn_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CANn_ND2_NEWDAT32_17_Pos) /*!< C_CANn ND2: NEWDAT32_17 Mask */ /* --------------------------------- C_CANn_IR1 --------------------------------- */ #define C_CANn_IR1_INTPND16_1_Pos 0 /*!< C_CANn IR1: INTPND16_1 Position */ #define C_CANn_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CANn_IR1_INTPND16_1_Pos) /*!< C_CANn IR1: INTPND16_1 Mask */ /* --------------------------------- C_CANn_IR2 --------------------------------- */ #define C_CANn_IR2_INTPND32_17_Pos 0 /*!< C_CANn IR2: INTPND32_17 Position */ #define C_CANn_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CANn_IR2_INTPND32_17_Pos) /*!< C_CANn IR2: INTPND32_17 Mask */ /* -------------------------------- C_CANn_MSGV1 -------------------------------- */ #define C_CANn_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CANn MSGV1: MSGVAL16_1 Position */ #define C_CANn_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CANn_MSGV1_MSGVAL16_1_Pos) /*!< C_CANn MSGV1: MSGVAL16_1 Mask */ /* -------------------------------- C_CANn_MSGV2 -------------------------------- */ #define C_CANn_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CANn MSGV2: MSGVAL32_17 Position */ #define C_CANn_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CANn_MSGV2_MSGVAL32_17_Pos) /*!< C_CANn MSGV2: MSGVAL32_17 Mask */ /* -------------------------------- C_CANn_CLKDIV ------------------------------- */ #define C_CANn_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CANn CLKDIV: CLKDIVVAL Position */ #define C_CANn_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CANn_CLKDIV_CLKDIVVAL_Pos) /*!< C_CANn CLKDIV: CLKDIVVAL Mask */ /* ================================================================================ */ /* ================ struct 'C_CAN1' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- C_CAN1_CNTL -------------------------------- */ #define C_CAN1_CNTL_INIT_Pos 0 /*!< C_CAN1 CNTL: INIT Position */ #define C_CAN1_CNTL_INIT_Msk (0x01UL << C_CAN1_CNTL_INIT_Pos) /*!< C_CAN1 CNTL: INIT Mask */ #define C_CAN1_CNTL_IE_Pos 1 /*!< C_CAN1 CNTL: IE Position */ #define C_CAN1_CNTL_IE_Msk (0x01UL << C_CAN1_CNTL_IE_Pos) /*!< C_CAN1 CNTL: IE Mask */ #define C_CAN1_CNTL_SIE_Pos 2 /*!< C_CAN1 CNTL: SIE Position */ #define C_CAN1_CNTL_SIE_Msk (0x01UL << C_CAN1_CNTL_SIE_Pos) /*!< C_CAN1 CNTL: SIE Mask */ #define C_CAN1_CNTL_EIE_Pos 3 /*!< C_CAN1 CNTL: EIE Position */ #define C_CAN1_CNTL_EIE_Msk (0x01UL << C_CAN1_CNTL_EIE_Pos) /*!< C_CAN1 CNTL: EIE Mask */ #define C_CAN1_CNTL_DAR_Pos 5 /*!< C_CAN1 CNTL: DAR Position */ #define C_CAN1_CNTL_DAR_Msk (0x01UL << C_CAN1_CNTL_DAR_Pos) /*!< C_CAN1 CNTL: DAR Mask */ #define C_CAN1_CNTL_CCE_Pos 6 /*!< C_CAN1 CNTL: CCE Position */ #define C_CAN1_CNTL_CCE_Msk (0x01UL << C_CAN1_CNTL_CCE_Pos) /*!< C_CAN1 CNTL: CCE Mask */ #define C_CAN1_CNTL_TEST_Pos 7 /*!< C_CAN1 CNTL: TEST Position */ #define C_CAN1_CNTL_TEST_Msk (0x01UL << C_CAN1_CNTL_TEST_Pos) /*!< C_CAN1 CNTL: TEST Mask */ /* --------------------------------- C_CAN1_STAT -------------------------------- */ #define C_CAN1_STAT_LEC_Pos 0 /*!< C_CAN1 STAT: LEC Position */ #define C_CAN1_STAT_LEC_Msk (0x07UL << C_CAN1_STAT_LEC_Pos) /*!< C_CAN1 STAT: LEC Mask */ #define C_CAN1_STAT_TXOK_Pos 3 /*!< C_CAN1 STAT: TXOK Position */ #define C_CAN1_STAT_TXOK_Msk (0x01UL << C_CAN1_STAT_TXOK_Pos) /*!< C_CAN1 STAT: TXOK Mask */ #define C_CAN1_STAT_RXOK_Pos 4 /*!< C_CAN1 STAT: RXOK Position */ #define C_CAN1_STAT_RXOK_Msk (0x01UL << C_CAN1_STAT_RXOK_Pos) /*!< C_CAN1 STAT: RXOK Mask */ #define C_CAN1_STAT_EPASS_Pos 5 /*!< C_CAN1 STAT: EPASS Position */ #define C_CAN1_STAT_EPASS_Msk (0x01UL << C_CAN1_STAT_EPASS_Pos) /*!< C_CAN1 STAT: EPASS Mask */ #define C_CAN1_STAT_EWARN_Pos 6 /*!< C_CAN1 STAT: EWARN Position */ #define C_CAN1_STAT_EWARN_Msk (0x01UL << C_CAN1_STAT_EWARN_Pos) /*!< C_CAN1 STAT: EWARN Mask */ #define C_CAN1_STAT_BOFF_Pos 7 /*!< C_CAN1 STAT: BOFF Position */ #define C_CAN1_STAT_BOFF_Msk (0x01UL << C_CAN1_STAT_BOFF_Pos) /*!< C_CAN1 STAT: BOFF Mask */ /* ---------------------------------- C_CAN1_EC --------------------------------- */ #define C_CAN1_EC_TEC_7_0_Pos 0 /*!< C_CAN1 EC: TEC_7_0 Position */ #define C_CAN1_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN1_EC_TEC_7_0_Pos) /*!< C_CAN1 EC: TEC_7_0 Mask */ #define C_CAN1_EC_REC_6_0_Pos 8 /*!< C_CAN1 EC: REC_6_0 Position */ #define C_CAN1_EC_REC_6_0_Msk (0x7fUL << C_CAN1_EC_REC_6_0_Pos) /*!< C_CAN1 EC: REC_6_0 Mask */ #define C_CAN1_EC_RP_Pos 15 /*!< C_CAN1 EC: RP Position */ #define C_CAN1_EC_RP_Msk (0x01UL << C_CAN1_EC_RP_Pos) /*!< C_CAN1 EC: RP Mask */ /* ---------------------------------- C_CAN1_BT --------------------------------- */ #define C_CAN1_BT_BRP_Pos 0 /*!< C_CAN1 BT: BRP Position */ #define C_CAN1_BT_BRP_Msk (0x3fUL << C_CAN1_BT_BRP_Pos) /*!< C_CAN1 BT: BRP Mask */ #define C_CAN1_BT_SJW_Pos 6 /*!< C_CAN1 BT: SJW Position */ #define C_CAN1_BT_SJW_Msk (0x03UL << C_CAN1_BT_SJW_Pos) /*!< C_CAN1 BT: SJW Mask */ #define C_CAN1_BT_TSEG1_Pos 8 /*!< C_CAN1 BT: TSEG1 Position */ #define C_CAN1_BT_TSEG1_Msk (0x0fUL << C_CAN1_BT_TSEG1_Pos) /*!< C_CAN1 BT: TSEG1 Mask */ #define C_CAN1_BT_TSEG2_Pos 12 /*!< C_CAN1 BT: TSEG2 Position */ #define C_CAN1_BT_TSEG2_Msk (0x07UL << C_CAN1_BT_TSEG2_Pos) /*!< C_CAN1 BT: TSEG2 Mask */ /* --------------------------------- C_CAN1_INT --------------------------------- */ #define C_CAN1_INT_INTID15_0_Pos 0 /*!< C_CAN1 INT: INTID15_0 Position */ #define C_CAN1_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN1_INT_INTID15_0_Pos) /*!< C_CAN1 INT: INTID15_0 Mask */ /* --------------------------------- C_CAN1_TEST -------------------------------- */ #define C_CAN1_TEST_BASIC_Pos 2 /*!< C_CAN1 TEST: BASIC Position */ #define C_CAN1_TEST_BASIC_Msk (0x01UL << C_CAN1_TEST_BASIC_Pos) /*!< C_CAN1 TEST: BASIC Mask */ #define C_CAN1_TEST_SILENT_Pos 3 /*!< C_CAN1 TEST: SILENT Position */ #define C_CAN1_TEST_SILENT_Msk (0x01UL << C_CAN1_TEST_SILENT_Pos) /*!< C_CAN1 TEST: SILENT Mask */ #define C_CAN1_TEST_LBACK_Pos 4 /*!< C_CAN1 TEST: LBACK Position */ #define C_CAN1_TEST_LBACK_Msk (0x01UL << C_CAN1_TEST_LBACK_Pos) /*!< C_CAN1 TEST: LBACK Mask */ #define C_CAN1_TEST_TX1_0_Pos 5 /*!< C_CAN1 TEST: TX1_0 Position */ #define C_CAN1_TEST_TX1_0_Msk (0x03UL << C_CAN1_TEST_TX1_0_Pos) /*!< C_CAN1 TEST: TX1_0 Mask */ #define C_CAN1_TEST_RX_Pos 7 /*!< C_CAN1 TEST: RX Position */ #define C_CAN1_TEST_RX_Msk (0x01UL << C_CAN1_TEST_RX_Pos) /*!< C_CAN1 TEST: RX Mask */ /* --------------------------------- C_CAN1_BRPE -------------------------------- */ #define C_CAN1_BRPE_BRPE_Pos 0 /*!< C_CAN1 BRPE: BRPE Position */ #define C_CAN1_BRPE_BRPE_Msk (0x0fUL << C_CAN1_BRPE_BRPE_Pos) /*!< C_CAN1 BRPE: BRPE Mask */ /* ------------------------------ C_CAN1_IF1_CMDREQ ----------------------------- */ #define C_CAN1_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF1_CMDREQ: MESSNUM Position */ #define C_CAN1_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF1_CMDREQ: MESSNUM Mask */ #define C_CAN1_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF1_CMDREQ: BUSY Position */ #define C_CAN1_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF1_CMDREQ: BUSY Mask */ /* ----------------------------- C_CAN1_IF1_CMDMSK_W ---------------------------- */ #define C_CAN1_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Position */ #define C_CAN1_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_B Mask */ #define C_CAN1_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Position */ #define C_CAN1_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_W: DATA_A Mask */ #define C_CAN1_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Position */ #define C_CAN1_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF1_CMDMSK_W: TXRQST Mask */ #define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Position */ #define C_CAN1_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CLRINTPND Mask */ #define C_CAN1_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_W: CTRL Position */ #define C_CAN1_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_W: CTRL Mask */ #define C_CAN1_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_W: ARB Position */ #define C_CAN1_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_W: ARB Mask */ #define C_CAN1_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_W: MASK Position */ #define C_CAN1_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_W: MASK Mask */ #define C_CAN1_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Position */ #define C_CAN1_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_W: WR_RD Mask */ /* ----------------------------- C_CAN1_IF1_CMDMSK_R ---------------------------- */ #define C_CAN1_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Position */ #define C_CAN1_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_B Mask */ #define C_CAN1_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Position */ #define C_CAN1_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF1_CMDMSK_R: DATA_A Mask */ #define C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Position */ #define C_CAN1_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF1_CMDMSK_R: NEWDAT Mask */ #define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Position */ #define C_CAN1_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CLRINTPND Mask */ #define C_CAN1_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF1_CMDMSK_R: CTRL Position */ #define C_CAN1_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF1_CMDMSK_R: CTRL Mask */ #define C_CAN1_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF1_CMDMSK_R: ARB Position */ #define C_CAN1_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF1_CMDMSK_R: ARB Mask */ #define C_CAN1_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF1_CMDMSK_R: MASK Position */ #define C_CAN1_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF1_CMDMSK_R: MASK Mask */ #define C_CAN1_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Position */ #define C_CAN1_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF1_CMDMSK_R: WR_RD Mask */ /* ------------------------------- C_CAN1_IF1_MSK1 ------------------------------ */ #define C_CAN1_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF1_MSK1: MSK15_0 Position */ #define C_CAN1_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF1_MSK1: MSK15_0 Mask */ /* ------------------------------- C_CAN1_IF1_MSK2 ------------------------------ */ #define C_CAN1_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF1_MSK2: MSK28_16 Position */ #define C_CAN1_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF1_MSK2: MSK28_16 Mask */ #define C_CAN1_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF1_MSK2: MDIR Position */ #define C_CAN1_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF1_MSK2_MDIR_Pos) /*!< C_CAN1 IF1_MSK2: MDIR Mask */ #define C_CAN1_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF1_MSK2: MXTD Position */ #define C_CAN1_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF1_MSK2_MXTD_Pos) /*!< C_CAN1 IF1_MSK2: MXTD Mask */ /* ------------------------------- C_CAN1_IF1_ARB1 ------------------------------ */ #define C_CAN1_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF1_ARB1: ID15_0 Position */ #define C_CAN1_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF1_ARB1_ID15_0_Pos) /*!< C_CAN1 IF1_ARB1: ID15_0 Mask */ /* ------------------------------- C_CAN1_IF1_ARB2 ------------------------------ */ #define C_CAN1_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF1_ARB2: ID28_16 Position */ #define C_CAN1_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF1_ARB2_ID28_16_Pos) /*!< C_CAN1 IF1_ARB2: ID28_16 Mask */ #define C_CAN1_IF1_ARB2_DIR_Pos 13 /*!< C_CAN1 IF1_ARB2: DIR Position */ #define C_CAN1_IF1_ARB2_DIR_Msk (0x01UL << C_CAN1_IF1_ARB2_DIR_Pos) /*!< C_CAN1 IF1_ARB2: DIR Mask */ #define C_CAN1_IF1_ARB2_XTD_Pos 14 /*!< C_CAN1 IF1_ARB2: XTD Position */ #define C_CAN1_IF1_ARB2_XTD_Msk (0x01UL << C_CAN1_IF1_ARB2_XTD_Pos) /*!< C_CAN1 IF1_ARB2: XTD Mask */ #define C_CAN1_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF1_ARB2: MSGVAL Position */ #define C_CAN1_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF1_ARB2: MSGVAL Mask */ /* ------------------------------ C_CAN1_IF1_MCTRL ------------------------------ */ #define C_CAN1_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF1_MCTRL: DLC3_0 Position */ #define C_CAN1_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF1_MCTRL: DLC3_0 Mask */ #define C_CAN1_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF1_MCTRL: EOB Position */ #define C_CAN1_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF1_MCTRL_EOB_Pos) /*!< C_CAN1 IF1_MCTRL: EOB Mask */ #define C_CAN1_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF1_MCTRL: TXRQST Position */ #define C_CAN1_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF1_MCTRL: TXRQST Mask */ #define C_CAN1_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF1_MCTRL: RMTEN Position */ #define C_CAN1_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF1_MCTRL: RMTEN Mask */ #define C_CAN1_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF1_MCTRL: RXIE Position */ #define C_CAN1_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_RXIE_Pos) /*!< C_CAN1 IF1_MCTRL: RXIE Mask */ #define C_CAN1_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF1_MCTRL: TXIE Position */ #define C_CAN1_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF1_MCTRL_TXIE_Pos) /*!< C_CAN1 IF1_MCTRL: TXIE Mask */ #define C_CAN1_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF1_MCTRL: UMASK Position */ #define C_CAN1_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF1_MCTRL_UMASK_Pos) /*!< C_CAN1 IF1_MCTRL: UMASK Mask */ #define C_CAN1_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF1_MCTRL: INTPND Position */ #define C_CAN1_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF1_MCTRL_INTPND_Pos) /*!< C_CAN1 IF1_MCTRL: INTPND Mask */ #define C_CAN1_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF1_MCTRL: MSGLST Position */ #define C_CAN1_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF1_MCTRL: MSGLST Mask */ #define C_CAN1_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF1_MCTRL: NEWDAT Position */ #define C_CAN1_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF1_MCTRL: NEWDAT Mask */ /* ------------------------------- C_CAN1_IF1_DA1 ------------------------------- */ #define C_CAN1_IF1_DA1_DATA0_Pos 0 /*!< C_CAN1 IF1_DA1: DATA0 Position */ #define C_CAN1_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA0_Pos) /*!< C_CAN1 IF1_DA1: DATA0 Mask */ #define C_CAN1_IF1_DA1_DATA1_Pos 8 /*!< C_CAN1 IF1_DA1: DATA1 Position */ #define C_CAN1_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF1_DA1_DATA1_Pos) /*!< C_CAN1 IF1_DA1: DATA1 Mask */ /* ------------------------------- C_CAN1_IF1_DA2 ------------------------------- */ #define C_CAN1_IF1_DA2_DATA2_Pos 0 /*!< C_CAN1 IF1_DA2: DATA2 Position */ #define C_CAN1_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA2_Pos) /*!< C_CAN1 IF1_DA2: DATA2 Mask */ #define C_CAN1_IF1_DA2_DATA3_Pos 8 /*!< C_CAN1 IF1_DA2: DATA3 Position */ #define C_CAN1_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF1_DA2_DATA3_Pos) /*!< C_CAN1 IF1_DA2: DATA3 Mask */ /* ------------------------------- C_CAN1_IF1_DB1 ------------------------------- */ #define C_CAN1_IF1_DB1_DATA4_Pos 0 /*!< C_CAN1 IF1_DB1: DATA4 Position */ #define C_CAN1_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA4_Pos) /*!< C_CAN1 IF1_DB1: DATA4 Mask */ #define C_CAN1_IF1_DB1_DATA5_Pos 8 /*!< C_CAN1 IF1_DB1: DATA5 Position */ #define C_CAN1_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF1_DB1_DATA5_Pos) /*!< C_CAN1 IF1_DB1: DATA5 Mask */ /* ------------------------------- C_CAN1_IF1_DB2 ------------------------------- */ #define C_CAN1_IF1_DB2_DATA6_Pos 0 /*!< C_CAN1 IF1_DB2: DATA6 Position */ #define C_CAN1_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA6_Pos) /*!< C_CAN1 IF1_DB2: DATA6 Mask */ #define C_CAN1_IF1_DB2_DATA7_Pos 8 /*!< C_CAN1 IF1_DB2: DATA7 Position */ #define C_CAN1_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF1_DB2_DATA7_Pos) /*!< C_CAN1 IF1_DB2: DATA7 Mask */ /* ------------------------------ C_CAN1_IF2_CMDREQ ----------------------------- */ #define C_CAN1_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN1 IF2_CMDREQ: MESSNUM Position */ #define C_CAN1_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN1_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN1 IF2_CMDREQ: MESSNUM Mask */ #define C_CAN1_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN1 IF2_CMDREQ: BUSY Position */ #define C_CAN1_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN1_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN1 IF2_CMDREQ: BUSY Mask */ /* ----------------------------- C_CAN1_IF2_CMDMSK_W ---------------------------- */ #define C_CAN1_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Position */ #define C_CAN1_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_B Mask */ #define C_CAN1_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Position */ #define C_CAN1_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_W: DATA_A Mask */ #define C_CAN1_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Position */ #define C_CAN1_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN1 IF2_CMDMSK_W: TXRQST Mask */ #define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Position */ #define C_CAN1_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CLRINTPND Mask */ #define C_CAN1_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_W: CTRL Position */ #define C_CAN1_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_W: CTRL Mask */ #define C_CAN1_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_W: ARB Position */ #define C_CAN1_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_W: ARB Mask */ #define C_CAN1_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_W: MASK Position */ #define C_CAN1_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_W: MASK Mask */ #define C_CAN1_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Position */ #define C_CAN1_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_W: WR_RD Mask */ /* ----------------------------- C_CAN1_IF2_CMDMSK_R ---------------------------- */ #define C_CAN1_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Position */ #define C_CAN1_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_B Mask */ #define C_CAN1_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Position */ #define C_CAN1_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN1 IF2_CMDMSK_R: DATA_A Mask */ #define C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Position */ #define C_CAN1_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN1 IF2_CMDMSK_R: NEWDAT Mask */ #define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Position */ #define C_CAN1_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CLRINTPND Mask */ #define C_CAN1_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN1 IF2_CMDMSK_R: CTRL Position */ #define C_CAN1_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN1 IF2_CMDMSK_R: CTRL Mask */ #define C_CAN1_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN1 IF2_CMDMSK_R: ARB Position */ #define C_CAN1_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN1 IF2_CMDMSK_R: ARB Mask */ #define C_CAN1_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN1 IF2_CMDMSK_R: MASK Position */ #define C_CAN1_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN1 IF2_CMDMSK_R: MASK Mask */ #define C_CAN1_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Position */ #define C_CAN1_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN1_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN1 IF2_CMDMSK_R: WR_RD Mask */ /* ------------------------------- C_CAN1_IF2_MSK1 ------------------------------ */ #define C_CAN1_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN1 IF2_MSK1: MSK15_0 Position */ #define C_CAN1_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN1_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN1 IF2_MSK1: MSK15_0 Mask */ /* ------------------------------- C_CAN1_IF2_MSK2 ------------------------------ */ #define C_CAN1_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN1 IF2_MSK2: MSK28_16 Position */ #define C_CAN1_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN1_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN1 IF2_MSK2: MSK28_16 Mask */ #define C_CAN1_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN1 IF2_MSK2: MDIR Position */ #define C_CAN1_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN1_IF2_MSK2_MDIR_Pos) /*!< C_CAN1 IF2_MSK2: MDIR Mask */ #define C_CAN1_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN1 IF2_MSK2: MXTD Position */ #define C_CAN1_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN1_IF2_MSK2_MXTD_Pos) /*!< C_CAN1 IF2_MSK2: MXTD Mask */ /* ------------------------------- C_CAN1_IF2_ARB1 ------------------------------ */ #define C_CAN1_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN1 IF2_ARB1: ID15_0 Position */ #define C_CAN1_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN1_IF2_ARB1_ID15_0_Pos) /*!< C_CAN1 IF2_ARB1: ID15_0 Mask */ /* ------------------------------- C_CAN1_IF2_ARB2 ------------------------------ */ #define C_CAN1_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN1 IF2_ARB2: ID28_16 Position */ #define C_CAN1_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN1_IF2_ARB2_ID28_16_Pos) /*!< C_CAN1 IF2_ARB2: ID28_16 Mask */ #define C_CAN1_IF2_ARB2_DIR_Pos 13 /*!< C_CAN1 IF2_ARB2: DIR Position */ #define C_CAN1_IF2_ARB2_DIR_Msk (0x01UL << C_CAN1_IF2_ARB2_DIR_Pos) /*!< C_CAN1 IF2_ARB2: DIR Mask */ #define C_CAN1_IF2_ARB2_XTD_Pos 14 /*!< C_CAN1 IF2_ARB2: XTD Position */ #define C_CAN1_IF2_ARB2_XTD_Msk (0x01UL << C_CAN1_IF2_ARB2_XTD_Pos) /*!< C_CAN1 IF2_ARB2: XTD Mask */ #define C_CAN1_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN1 IF2_ARB2: MSGVAL Position */ #define C_CAN1_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN1_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN1 IF2_ARB2: MSGVAL Mask */ /* ------------------------------ C_CAN1_IF2_MCTRL ------------------------------ */ #define C_CAN1_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN1 IF2_MCTRL: DLC3_0 Position */ #define C_CAN1_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN1_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN1 IF2_MCTRL: DLC3_0 Mask */ #define C_CAN1_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN1 IF2_MCTRL: EOB Position */ #define C_CAN1_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN1_IF2_MCTRL_EOB_Pos) /*!< C_CAN1 IF2_MCTRL: EOB Mask */ #define C_CAN1_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN1 IF2_MCTRL: TXRQST Position */ #define C_CAN1_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN1 IF2_MCTRL: TXRQST Mask */ #define C_CAN1_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN1 IF2_MCTRL: RMTEN Position */ #define C_CAN1_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN1_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN1 IF2_MCTRL: RMTEN Mask */ #define C_CAN1_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN1 IF2_MCTRL: RXIE Position */ #define C_CAN1_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_RXIE_Pos) /*!< C_CAN1 IF2_MCTRL: RXIE Mask */ #define C_CAN1_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN1 IF2_MCTRL: TXIE Position */ #define C_CAN1_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN1_IF2_MCTRL_TXIE_Pos) /*!< C_CAN1 IF2_MCTRL: TXIE Mask */ #define C_CAN1_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN1 IF2_MCTRL: UMASK Position */ #define C_CAN1_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN1_IF2_MCTRL_UMASK_Pos) /*!< C_CAN1 IF2_MCTRL: UMASK Mask */ #define C_CAN1_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN1 IF2_MCTRL: INTPND Position */ #define C_CAN1_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN1_IF2_MCTRL_INTPND_Pos) /*!< C_CAN1 IF2_MCTRL: INTPND Mask */ #define C_CAN1_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN1 IF2_MCTRL: MSGLST Position */ #define C_CAN1_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN1_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN1 IF2_MCTRL: MSGLST Mask */ #define C_CAN1_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN1 IF2_MCTRL: NEWDAT Position */ #define C_CAN1_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN1_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN1 IF2_MCTRL: NEWDAT Mask */ /* ------------------------------- C_CAN1_IF2_DA1 ------------------------------- */ #define C_CAN1_IF2_DA1_DATA0_Pos 0 /*!< C_CAN1 IF2_DA1: DATA0 Position */ #define C_CAN1_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA0_Pos) /*!< C_CAN1 IF2_DA1: DATA0 Mask */ #define C_CAN1_IF2_DA1_DATA1_Pos 8 /*!< C_CAN1 IF2_DA1: DATA1 Position */ #define C_CAN1_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN1_IF2_DA1_DATA1_Pos) /*!< C_CAN1 IF2_DA1: DATA1 Mask */ /* ------------------------------- C_CAN1_IF2_DA2 ------------------------------- */ #define C_CAN1_IF2_DA2_DATA2_Pos 0 /*!< C_CAN1 IF2_DA2: DATA2 Position */ #define C_CAN1_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA2_Pos) /*!< C_CAN1 IF2_DA2: DATA2 Mask */ #define C_CAN1_IF2_DA2_DATA3_Pos 8 /*!< C_CAN1 IF2_DA2: DATA3 Position */ #define C_CAN1_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN1_IF2_DA2_DATA3_Pos) /*!< C_CAN1 IF2_DA2: DATA3 Mask */ /* ------------------------------- C_CAN1_IF2_DB1 ------------------------------- */ #define C_CAN1_IF2_DB1_DATA4_Pos 0 /*!< C_CAN1 IF2_DB1: DATA4 Position */ #define C_CAN1_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA4_Pos) /*!< C_CAN1 IF2_DB1: DATA4 Mask */ #define C_CAN1_IF2_DB1_DATA5_Pos 8 /*!< C_CAN1 IF2_DB1: DATA5 Position */ #define C_CAN1_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN1_IF2_DB1_DATA5_Pos) /*!< C_CAN1 IF2_DB1: DATA5 Mask */ /* ------------------------------- C_CAN1_IF2_DB2 ------------------------------- */ #define C_CAN1_IF2_DB2_DATA6_Pos 0 /*!< C_CAN1 IF2_DB2: DATA6 Position */ #define C_CAN1_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA6_Pos) /*!< C_CAN1 IF2_DB2: DATA6 Mask */ #define C_CAN1_IF2_DB2_DATA7_Pos 8 /*!< C_CAN1 IF2_DB2: DATA7 Position */ #define C_CAN1_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN1_IF2_DB2_DATA7_Pos) /*!< C_CAN1 IF2_DB2: DATA7 Mask */ /* -------------------------------- C_CAN1_TXREQ1 ------------------------------- */ #define C_CAN1_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN1 TXREQ1: TXRQST16_1 Position */ #define C_CAN1_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN1_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN1 TXREQ1: TXRQST16_1 Mask */ /* -------------------------------- C_CAN1_TXREQ2 ------------------------------- */ #define C_CAN1_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN1 TXREQ2: TXRQST32_17 Position */ #define C_CAN1_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN1_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN1 TXREQ2: TXRQST32_17 Mask */ /* --------------------------------- C_CAN1_ND1 --------------------------------- */ #define C_CAN1_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN1 ND1: NEWDAT16_1 Position */ #define C_CAN1_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN1_ND1_NEWDAT16_1_Pos) /*!< C_CAN1 ND1: NEWDAT16_1 Mask */ /* --------------------------------- C_CAN1_ND2 --------------------------------- */ #define C_CAN1_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN1 ND2: NEWDAT32_17 Position */ #define C_CAN1_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN1_ND2_NEWDAT32_17_Pos) /*!< C_CAN1 ND2: NEWDAT32_17 Mask */ /* --------------------------------- C_CAN1_IR1 --------------------------------- */ #define C_CAN1_IR1_INTPND16_1_Pos 0 /*!< C_CAN1 IR1: INTPND16_1 Position */ #define C_CAN1_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN1_IR1_INTPND16_1_Pos) /*!< C_CAN1 IR1: INTPND16_1 Mask */ /* --------------------------------- C_CAN1_IR2 --------------------------------- */ #define C_CAN1_IR2_INTPND32_17_Pos 0 /*!< C_CAN1 IR2: INTPND32_17 Position */ #define C_CAN1_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN1_IR2_INTPND32_17_Pos) /*!< C_CAN1 IR2: INTPND32_17 Mask */ /* -------------------------------- C_CAN1_MSGV1 -------------------------------- */ #define C_CAN1_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN1 MSGV1: MSGVAL16_1 Position */ #define C_CAN1_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN1_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN1 MSGV1: MSGVAL16_1 Mask */ /* -------------------------------- C_CAN1_MSGV2 -------------------------------- */ #define C_CAN1_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN1 MSGV2: MSGVAL32_17 Position */ #define C_CAN1_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN1_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN1 MSGV2: MSGVAL32_17 Mask */ /* -------------------------------- C_CAN1_CLKDIV ------------------------------- */ #define C_CAN1_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN1 CLKDIV: CLKDIVVAL Position */ #define C_CAN1_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN1_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN1 CLKDIV: CLKDIVVAL Mask */ /* ================================================================================ */ /* ================ struct 'RITIMER' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------- RITIMER_COMPVAL ------------------------------ */ #define RITIMER_COMPVAL_RICOMP_Pos 0 /*!< RITIMER COMPVAL: RICOMP Position */ #define RITIMER_COMPVAL_RICOMP_Msk (0xffffffffUL << RITIMER_COMPVAL_RICOMP_Pos) /*!< RITIMER COMPVAL: RICOMP Mask */ /* -------------------------------- RITIMER_MASK -------------------------------- */ #define RITIMER_MASK_RIMASK_Pos 0 /*!< RITIMER MASK: RIMASK Position */ #define RITIMER_MASK_RIMASK_Msk (0xffffffffUL << RITIMER_MASK_RIMASK_Pos) /*!< RITIMER MASK: RIMASK Mask */ /* -------------------------------- RITIMER_CTRL -------------------------------- */ #define RITIMER_CTRL_RITINT_Pos 0 /*!< RITIMER CTRL: RITINT Position */ #define RITIMER_CTRL_RITINT_Msk (0x01UL << RITIMER_CTRL_RITINT_Pos) /*!< RITIMER CTRL: RITINT Mask */ #define RITIMER_CTRL_RITENCLR_Pos 1 /*!< RITIMER CTRL: RITENCLR Position */ #define RITIMER_CTRL_RITENCLR_Msk (0x01UL << RITIMER_CTRL_RITENCLR_Pos) /*!< RITIMER CTRL: RITENCLR Mask */ #define RITIMER_CTRL_RITENBR_Pos 2 /*!< RITIMER CTRL: RITENBR Position */ #define RITIMER_CTRL_RITENBR_Msk (0x01UL << RITIMER_CTRL_RITENBR_Pos) /*!< RITIMER CTRL: RITENBR Mask */ #define RITIMER_CTRL_RITEN_Pos 3 /*!< RITIMER CTRL: RITEN Position */ #define RITIMER_CTRL_RITEN_Msk (0x01UL << RITIMER_CTRL_RITEN_Pos) /*!< RITIMER CTRL: RITEN Mask */ /* ------------------------------- RITIMER_COUNTER ------------------------------ */ #define RITIMER_COUNTER_RICOUNTER_Pos 0 /*!< RITIMER COUNTER: RICOUNTER Position */ #define RITIMER_COUNTER_RICOUNTER_Msk (0xffffffffUL << RITIMER_COUNTER_RICOUNTER_Pos) /*!< RITIMER COUNTER: RICOUNTER Mask */ /* ================================================================================ */ /* ================ struct 'QEI' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- QEI_CON ---------------------------------- */ #define QEI_CON_RESP_Pos 0 /*!< QEI CON: RESP Position */ #define QEI_CON_RESP_Msk (0x01UL << QEI_CON_RESP_Pos) /*!< QEI CON: RESP Mask */ #define QEI_CON_RESPI_Pos 1 /*!< QEI CON: RESPI Position */ #define QEI_CON_RESPI_Msk (0x01UL << QEI_CON_RESPI_Pos) /*!< QEI CON: RESPI Mask */ #define QEI_CON_RESV_Pos 2 /*!< QEI CON: RESV Position */ #define QEI_CON_RESV_Msk (0x01UL << QEI_CON_RESV_Pos) /*!< QEI CON: RESV Mask */ #define QEI_CON_RESI_Pos 3 /*!< QEI CON: RESI Position */ #define QEI_CON_RESI_Msk (0x01UL << QEI_CON_RESI_Pos) /*!< QEI CON: RESI Mask */ /* ---------------------------------- QEI_STAT ---------------------------------- */ #define QEI_STAT_DIR_Pos 0 /*!< QEI STAT: DIR Position */ #define QEI_STAT_DIR_Msk (0x01UL << QEI_STAT_DIR_Pos) /*!< QEI STAT: DIR Mask */ /* ---------------------------------- QEI_CONF ---------------------------------- */ #define QEI_CONF_DIRINV_Pos 0 /*!< QEI CONF: DIRINV Position */ #define QEI_CONF_DIRINV_Msk (0x01UL << QEI_CONF_DIRINV_Pos) /*!< QEI CONF: DIRINV Mask */ #define QEI_CONF_SIGMODE_Pos 1 /*!< QEI CONF: SIGMODE Position */ #define QEI_CONF_SIGMODE_Msk (0x01UL << QEI_CONF_SIGMODE_Pos) /*!< QEI CONF: SIGMODE Mask */ #define QEI_CONF_CAPMODE_Pos 2 /*!< QEI CONF: CAPMODE Position */ #define QEI_CONF_CAPMODE_Msk (0x01UL << QEI_CONF_CAPMODE_Pos) /*!< QEI CONF: CAPMODE Mask */ #define QEI_CONF_INVINX_Pos 3 /*!< QEI CONF: INVINX Position */ #define QEI_CONF_INVINX_Msk (0x01UL << QEI_CONF_INVINX_Pos) /*!< QEI CONF: INVINX Mask */ #define QEI_CONF_CRESPI_Pos 4 /*!< QEI CONF: CRESPI Position */ #define QEI_CONF_CRESPI_Msk (0x01UL << QEI_CONF_CRESPI_Pos) /*!< QEI CONF: CRESPI Mask */ #define QEI_CONF_INXGATE_Pos 16 /*!< QEI CONF: INXGATE Position */ #define QEI_CONF_INXGATE_Msk (0x0fUL << QEI_CONF_INXGATE_Pos) /*!< QEI CONF: INXGATE Mask */ /* ----------------------------------- QEI_POS ---------------------------------- */ #define QEI_POS_POS_Pos 0 /*!< QEI POS: POS Position */ #define QEI_POS_POS_Msk (0xffffffffUL << QEI_POS_POS_Pos) /*!< QEI POS: POS Mask */ /* --------------------------------- QEI_MAXPOS --------------------------------- */ #define QEI_MAXPOS_MAXPOS_Pos 0 /*!< QEI MAXPOS: MAXPOS Position */ #define QEI_MAXPOS_MAXPOS_Msk (0xffffffffUL << QEI_MAXPOS_MAXPOS_Pos) /*!< QEI MAXPOS: MAXPOS Mask */ /* --------------------------------- QEI_CMPOS0 --------------------------------- */ #define QEI_CMPOS0_PCMP0_Pos 0 /*!< QEI CMPOS0: PCMP0 Position */ #define QEI_CMPOS0_PCMP0_Msk (0xffffffffUL << QEI_CMPOS0_PCMP0_Pos) /*!< QEI CMPOS0: PCMP0 Mask */ /* --------------------------------- QEI_CMPOS1 --------------------------------- */ #define QEI_CMPOS1_PCMP1_Pos 0 /*!< QEI CMPOS1: PCMP1 Position */ #define QEI_CMPOS1_PCMP1_Msk (0xffffffffUL << QEI_CMPOS1_PCMP1_Pos) /*!< QEI CMPOS1: PCMP1 Mask */ /* --------------------------------- QEI_CMPOS2 --------------------------------- */ #define QEI_CMPOS2_PCMP2_Pos 0 /*!< QEI CMPOS2: PCMP2 Position */ #define QEI_CMPOS2_PCMP2_Msk (0xffffffffUL << QEI_CMPOS2_PCMP2_Pos) /*!< QEI CMPOS2: PCMP2 Mask */ /* --------------------------------- QEI_INXCNT --------------------------------- */ #define QEI_INXCNT_ENCPOS_Pos 0 /*!< QEI INXCNT: ENCPOS Position */ #define QEI_INXCNT_ENCPOS_Msk (0xffffffffUL << QEI_INXCNT_ENCPOS_Pos) /*!< QEI INXCNT: ENCPOS Mask */ /* --------------------------------- QEI_INXCMP0 -------------------------------- */ #define QEI_INXCMP0_ICMP0_Pos 0 /*!< QEI INXCMP0: ICMP0 Position */ #define QEI_INXCMP0_ICMP0_Msk (0xffffffffUL << QEI_INXCMP0_ICMP0_Pos) /*!< QEI INXCMP0: ICMP0 Mask */ /* ---------------------------------- QEI_LOAD ---------------------------------- */ #define QEI_LOAD_VELLOAD_Pos 0 /*!< QEI LOAD: VELLOAD Position */ #define QEI_LOAD_VELLOAD_Msk (0xffffffffUL << QEI_LOAD_VELLOAD_Pos) /*!< QEI LOAD: VELLOAD Mask */ /* ---------------------------------- QEI_TIME ---------------------------------- */ #define QEI_TIME_VELVAL_Pos 0 /*!< QEI TIME: VELVAL Position */ #define QEI_TIME_VELVAL_Msk (0xffffffffUL << QEI_TIME_VELVAL_Pos) /*!< QEI TIME: VELVAL Mask */ /* ----------------------------------- QEI_VEL ---------------------------------- */ #define QEI_VEL_VELPC_Pos 0 /*!< QEI VEL: VELPC Position */ #define QEI_VEL_VELPC_Msk (0xffffffffUL << QEI_VEL_VELPC_Pos) /*!< QEI VEL: VELPC Mask */ /* ----------------------------------- QEI_CAP ---------------------------------- */ #define QEI_CAP_VELCAP_Pos 0 /*!< QEI CAP: VELCAP Position */ #define QEI_CAP_VELCAP_Msk (0xffffffffUL << QEI_CAP_VELCAP_Pos) /*!< QEI CAP: VELCAP Mask */ /* --------------------------------- QEI_VELCOMP -------------------------------- */ #define QEI_VELCOMP_VELCMP_Pos 0 /*!< QEI VELCOMP: VELCMP Position */ #define QEI_VELCOMP_VELCMP_Msk (0xffffffffUL << QEI_VELCOMP_VELCMP_Pos) /*!< QEI VELCOMP: VELCMP Mask */ /* -------------------------------- QEI_FILTERPHA ------------------------------- */ #define QEI_FILTERPHA_FILTA_Pos 0 /*!< QEI FILTERPHA: FILTA Position */ #define QEI_FILTERPHA_FILTA_Msk (0xffffffffUL << QEI_FILTERPHA_FILTA_Pos) /*!< QEI FILTERPHA: FILTA Mask */ /* -------------------------------- QEI_FILTERPHB ------------------------------- */ #define QEI_FILTERPHB_FILTB_Pos 0 /*!< QEI FILTERPHB: FILTB Position */ #define QEI_FILTERPHB_FILTB_Msk (0xffffffffUL << QEI_FILTERPHB_FILTB_Pos) /*!< QEI FILTERPHB: FILTB Mask */ /* -------------------------------- QEI_FILTERINX ------------------------------- */ #define QEI_FILTERINX_FITLINX_Pos 0 /*!< QEI FILTERINX: FITLINX Position */ #define QEI_FILTERINX_FITLINX_Msk (0xffffffffUL << QEI_FILTERINX_FITLINX_Pos) /*!< QEI FILTERINX: FITLINX Mask */ /* --------------------------------- QEI_WINDOW --------------------------------- */ #define QEI_WINDOW_WINDOW_Pos 0 /*!< QEI WINDOW: WINDOW Position */ #define QEI_WINDOW_WINDOW_Msk (0xffffffffUL << QEI_WINDOW_WINDOW_Pos) /*!< QEI WINDOW: WINDOW Mask */ /* --------------------------------- QEI_INXCMP1 -------------------------------- */ #define QEI_INXCMP1_ICMP1_Pos 0 /*!< QEI INXCMP1: ICMP1 Position */ #define QEI_INXCMP1_ICMP1_Msk (0xffffffffUL << QEI_INXCMP1_ICMP1_Pos) /*!< QEI INXCMP1: ICMP1 Mask */ /* --------------------------------- QEI_INXCMP2 -------------------------------- */ #define QEI_INXCMP2_ICMP2_Pos 0 /*!< QEI INXCMP2: ICMP2 Position */ #define QEI_INXCMP2_ICMP2_Msk (0xffffffffUL << QEI_INXCMP2_ICMP2_Pos) /*!< QEI INXCMP2: ICMP2 Mask */ /* ----------------------------------- QEI_IEC ---------------------------------- */ #define QEI_IEC_INX_EN_Pos 0 /*!< QEI IEC: INX_EN Position */ #define QEI_IEC_INX_EN_Msk (0x01UL << QEI_IEC_INX_EN_Pos) /*!< QEI IEC: INX_EN Mask */ #define QEI_IEC_TIM_EN_Pos 1 /*!< QEI IEC: TIM_EN Position */ #define QEI_IEC_TIM_EN_Msk (0x01UL << QEI_IEC_TIM_EN_Pos) /*!< QEI IEC: TIM_EN Mask */ #define QEI_IEC_VELC_EN_Pos 2 /*!< QEI IEC: VELC_EN Position */ #define QEI_IEC_VELC_EN_Msk (0x01UL << QEI_IEC_VELC_EN_Pos) /*!< QEI IEC: VELC_EN Mask */ #define QEI_IEC_DIR_EN_Pos 3 /*!< QEI IEC: DIR_EN Position */ #define QEI_IEC_DIR_EN_Msk (0x01UL << QEI_IEC_DIR_EN_Pos) /*!< QEI IEC: DIR_EN Mask */ #define QEI_IEC_ERR_EN_Pos 4 /*!< QEI IEC: ERR_EN Position */ #define QEI_IEC_ERR_EN_Msk (0x01UL << QEI_IEC_ERR_EN_Pos) /*!< QEI IEC: ERR_EN Mask */ #define QEI_IEC_ENCLK_EN_Pos 5 /*!< QEI IEC: ENCLK_EN Position */ #define QEI_IEC_ENCLK_EN_Msk (0x01UL << QEI_IEC_ENCLK_EN_Pos) /*!< QEI IEC: ENCLK_EN Mask */ #define QEI_IEC_POS0_Int_Pos 6 /*!< QEI IEC: POS0_Int Position */ #define QEI_IEC_POS0_Int_Msk (0x01UL << QEI_IEC_POS0_Int_Pos) /*!< QEI IEC: POS0_Int Mask */ #define QEI_IEC_POS1_Int_Pos 7 /*!< QEI IEC: POS1_Int Position */ #define QEI_IEC_POS1_Int_Msk (0x01UL << QEI_IEC_POS1_Int_Pos) /*!< QEI IEC: POS1_Int Mask */ #define QEI_IEC_POS2_Int_Pos 8 /*!< QEI IEC: POS2_Int Position */ #define QEI_IEC_POS2_Int_Msk (0x01UL << QEI_IEC_POS2_Int_Pos) /*!< QEI IEC: POS2_Int Mask */ #define QEI_IEC_REV_Int_Pos 9 /*!< QEI IEC: REV_Int Position */ #define QEI_IEC_REV_Int_Msk (0x01UL << QEI_IEC_REV_Int_Pos) /*!< QEI IEC: REV_Int Mask */ #define QEI_IEC_POS0REV_Int_Pos 10 /*!< QEI IEC: POS0REV_Int Position */ #define QEI_IEC_POS0REV_Int_Msk (0x01UL << QEI_IEC_POS0REV_Int_Pos) /*!< QEI IEC: POS0REV_Int Mask */ #define QEI_IEC_POS1REV_Int_Pos 11 /*!< QEI IEC: POS1REV_Int Position */ #define QEI_IEC_POS1REV_Int_Msk (0x01UL << QEI_IEC_POS1REV_Int_Pos) /*!< QEI IEC: POS1REV_Int Mask */ #define QEI_IEC_POS2REV_Int_Pos 12 /*!< QEI IEC: POS2REV_Int Position */ #define QEI_IEC_POS2REV_Int_Msk (0x01UL << QEI_IEC_POS2REV_Int_Pos) /*!< QEI IEC: POS2REV_Int Mask */ #define QEI_IEC_REV1_Int_Pos 13 /*!< QEI IEC: REV1_Int Position */ #define QEI_IEC_REV1_Int_Msk (0x01UL << QEI_IEC_REV1_Int_Pos) /*!< QEI IEC: REV1_Int Mask */ #define QEI_IEC_REV2_Int_Pos 14 /*!< QEI IEC: REV2_Int Position */ #define QEI_IEC_REV2_Int_Msk (0x01UL << QEI_IEC_REV2_Int_Pos) /*!< QEI IEC: REV2_Int Mask */ #define QEI_IEC_MAXPOS_Int_Pos 15 /*!< QEI IEC: MAXPOS_Int Position */ #define QEI_IEC_MAXPOS_Int_Msk (0x01UL << QEI_IEC_MAXPOS_Int_Pos) /*!< QEI IEC: MAXPOS_Int Mask */ /* ----------------------------------- QEI_IES ---------------------------------- */ #define QEI_IES_INX_EN_Pos 0 /*!< QEI IES: INX_EN Position */ #define QEI_IES_INX_EN_Msk (0x01UL << QEI_IES_INX_EN_Pos) /*!< QEI IES: INX_EN Mask */ #define QEI_IES_TIM_EN_Pos 1 /*!< QEI IES: TIM_EN Position */ #define QEI_IES_TIM_EN_Msk (0x01UL << QEI_IES_TIM_EN_Pos) /*!< QEI IES: TIM_EN Mask */ #define QEI_IES_VELC_EN_Pos 2 /*!< QEI IES: VELC_EN Position */ #define QEI_IES_VELC_EN_Msk (0x01UL << QEI_IES_VELC_EN_Pos) /*!< QEI IES: VELC_EN Mask */ #define QEI_IES_DIR_EN_Pos 3 /*!< QEI IES: DIR_EN Position */ #define QEI_IES_DIR_EN_Msk (0x01UL << QEI_IES_DIR_EN_Pos) /*!< QEI IES: DIR_EN Mask */ #define QEI_IES_ERR_EN_Pos 4 /*!< QEI IES: ERR_EN Position */ #define QEI_IES_ERR_EN_Msk (0x01UL << QEI_IES_ERR_EN_Pos) /*!< QEI IES: ERR_EN Mask */ #define QEI_IES_ENCLK_EN_Pos 5 /*!< QEI IES: ENCLK_EN Position */ #define QEI_IES_ENCLK_EN_Msk (0x01UL << QEI_IES_ENCLK_EN_Pos) /*!< QEI IES: ENCLK_EN Mask */ #define QEI_IES_POS0_Int_Pos 6 /*!< QEI IES: POS0_Int Position */ #define QEI_IES_POS0_Int_Msk (0x01UL << QEI_IES_POS0_Int_Pos) /*!< QEI IES: POS0_Int Mask */ #define QEI_IES_POS1_Int_Pos 7 /*!< QEI IES: POS1_Int Position */ #define QEI_IES_POS1_Int_Msk (0x01UL << QEI_IES_POS1_Int_Pos) /*!< QEI IES: POS1_Int Mask */ #define QEI_IES_POS2_Int_Pos 8 /*!< QEI IES: POS2_Int Position */ #define QEI_IES_POS2_Int_Msk (0x01UL << QEI_IES_POS2_Int_Pos) /*!< QEI IES: POS2_Int Mask */ #define QEI_IES_REV_Int_Pos 9 /*!< QEI IES: REV_Int Position */ #define QEI_IES_REV_Int_Msk (0x01UL << QEI_IES_REV_Int_Pos) /*!< QEI IES: REV_Int Mask */ #define QEI_IES_POS0REV_Int_Pos 10 /*!< QEI IES: POS0REV_Int Position */ #define QEI_IES_POS0REV_Int_Msk (0x01UL << QEI_IES_POS0REV_Int_Pos) /*!< QEI IES: POS0REV_Int Mask */ #define QEI_IES_POS1REV_Int_Pos 11 /*!< QEI IES: POS1REV_Int Position */ #define QEI_IES_POS1REV_Int_Msk (0x01UL << QEI_IES_POS1REV_Int_Pos) /*!< QEI IES: POS1REV_Int Mask */ #define QEI_IES_POS2REV_Int_Pos 12 /*!< QEI IES: POS2REV_Int Position */ #define QEI_IES_POS2REV_Int_Msk (0x01UL << QEI_IES_POS2REV_Int_Pos) /*!< QEI IES: POS2REV_Int Mask */ #define QEI_IES_REV1_Int_Pos 13 /*!< QEI IES: REV1_Int Position */ #define QEI_IES_REV1_Int_Msk (0x01UL << QEI_IES_REV1_Int_Pos) /*!< QEI IES: REV1_Int Mask */ #define QEI_IES_REV2_Int_Pos 14 /*!< QEI IES: REV2_Int Position */ #define QEI_IES_REV2_Int_Msk (0x01UL << QEI_IES_REV2_Int_Pos) /*!< QEI IES: REV2_Int Mask */ #define QEI_IES_MAXPOS_Int_Pos 15 /*!< QEI IES: MAXPOS_Int Position */ #define QEI_IES_MAXPOS_Int_Msk (0x01UL << QEI_IES_MAXPOS_Int_Pos) /*!< QEI IES: MAXPOS_Int Mask */ /* --------------------------------- QEI_INTSTAT -------------------------------- */ #define QEI_INTSTAT_INX_Int_Pos 0 /*!< QEI INTSTAT: INX_Int Position */ #define QEI_INTSTAT_INX_Int_Msk (0x01UL << QEI_INTSTAT_INX_Int_Pos) /*!< QEI INTSTAT: INX_Int Mask */ #define QEI_INTSTAT_TIM_Int_Pos 1 /*!< QEI INTSTAT: TIM_Int Position */ #define QEI_INTSTAT_TIM_Int_Msk (0x01UL << QEI_INTSTAT_TIM_Int_Pos) /*!< QEI INTSTAT: TIM_Int Mask */ #define QEI_INTSTAT_VELC_Int_Pos 2 /*!< QEI INTSTAT: VELC_Int Position */ #define QEI_INTSTAT_VELC_Int_Msk (0x01UL << QEI_INTSTAT_VELC_Int_Pos) /*!< QEI INTSTAT: VELC_Int Mask */ #define QEI_INTSTAT_DIR_Int_Pos 3 /*!< QEI INTSTAT: DIR_Int Position */ #define QEI_INTSTAT_DIR_Int_Msk (0x01UL << QEI_INTSTAT_DIR_Int_Pos) /*!< QEI INTSTAT: DIR_Int Mask */ #define QEI_INTSTAT_ERR_Int_Pos 4 /*!< QEI INTSTAT: ERR_Int Position */ #define QEI_INTSTAT_ERR_Int_Msk (0x01UL << QEI_INTSTAT_ERR_Int_Pos) /*!< QEI INTSTAT: ERR_Int Mask */ #define QEI_INTSTAT_ENCLK_Int_Pos 5 /*!< QEI INTSTAT: ENCLK_Int Position */ #define QEI_INTSTAT_ENCLK_Int_Msk (0x01UL << QEI_INTSTAT_ENCLK_Int_Pos) /*!< QEI INTSTAT: ENCLK_Int Mask */ #define QEI_INTSTAT_POS0_Int_Pos 6 /*!< QEI INTSTAT: POS0_Int Position */ #define QEI_INTSTAT_POS0_Int_Msk (0x01UL << QEI_INTSTAT_POS0_Int_Pos) /*!< QEI INTSTAT: POS0_Int Mask */ #define QEI_INTSTAT_POS1_Int_Pos 7 /*!< QEI INTSTAT: POS1_Int Position */ #define QEI_INTSTAT_POS1_Int_Msk (0x01UL << QEI_INTSTAT_POS1_Int_Pos) /*!< QEI INTSTAT: POS1_Int Mask */ #define QEI_INTSTAT_POS2_Int_Pos 8 /*!< QEI INTSTAT: POS2_Int Position */ #define QEI_INTSTAT_POS2_Int_Msk (0x01UL << QEI_INTSTAT_POS2_Int_Pos) /*!< QEI INTSTAT: POS2_Int Mask */ #define QEI_INTSTAT_REV_Int_Pos 9 /*!< QEI INTSTAT: REV_Int Position */ #define QEI_INTSTAT_REV_Int_Msk (0x01UL << QEI_INTSTAT_REV_Int_Pos) /*!< QEI INTSTAT: REV_Int Mask */ #define QEI_INTSTAT_POS0REV_Int_Pos 10 /*!< QEI INTSTAT: POS0REV_Int Position */ #define QEI_INTSTAT_POS0REV_Int_Msk (0x01UL << QEI_INTSTAT_POS0REV_Int_Pos) /*!< QEI INTSTAT: POS0REV_Int Mask */ #define QEI_INTSTAT_POS1REV_Int_Pos 11 /*!< QEI INTSTAT: POS1REV_Int Position */ #define QEI_INTSTAT_POS1REV_Int_Msk (0x01UL << QEI_INTSTAT_POS1REV_Int_Pos) /*!< QEI INTSTAT: POS1REV_Int Mask */ #define QEI_INTSTAT_POS2REV_Int_Pos 12 /*!< QEI INTSTAT: POS2REV_Int Position */ #define QEI_INTSTAT_POS2REV_Int_Msk (0x01UL << QEI_INTSTAT_POS2REV_Int_Pos) /*!< QEI INTSTAT: POS2REV_Int Mask */ #define QEI_INTSTAT_REV1_Int_Pos 13 /*!< QEI INTSTAT: REV1_Int Position */ #define QEI_INTSTAT_REV1_Int_Msk (0x01UL << QEI_INTSTAT_REV1_Int_Pos) /*!< QEI INTSTAT: REV1_Int Mask */ #define QEI_INTSTAT_REV2_Int_Pos 14 /*!< QEI INTSTAT: REV2_Int Position */ #define QEI_INTSTAT_REV2_Int_Msk (0x01UL << QEI_INTSTAT_REV2_Int_Pos) /*!< QEI INTSTAT: REV2_Int Mask */ #define QEI_INTSTAT_MAXPOS_Int_Pos 15 /*!< QEI INTSTAT: MAXPOS_Int Position */ #define QEI_INTSTAT_MAXPOS_Int_Msk (0x01UL << QEI_INTSTAT_MAXPOS_Int_Pos) /*!< QEI INTSTAT: MAXPOS_Int Mask */ /* ----------------------------------- QEI_IE ----------------------------------- */ #define QEI_IE_INX_Int_Pos 0 /*!< QEI IE: INX_Int Position */ #define QEI_IE_INX_Int_Msk (0x01UL << QEI_IE_INX_Int_Pos) /*!< QEI IE: INX_Int Mask */ #define QEI_IE_TIM_Int_Pos 1 /*!< QEI IE: TIM_Int Position */ #define QEI_IE_TIM_Int_Msk (0x01UL << QEI_IE_TIM_Int_Pos) /*!< QEI IE: TIM_Int Mask */ #define QEI_IE_VELC_Int_Pos 2 /*!< QEI IE: VELC_Int Position */ #define QEI_IE_VELC_Int_Msk (0x01UL << QEI_IE_VELC_Int_Pos) /*!< QEI IE: VELC_Int Mask */ #define QEI_IE_DIR_Int_Pos 3 /*!< QEI IE: DIR_Int Position */ #define QEI_IE_DIR_Int_Msk (0x01UL << QEI_IE_DIR_Int_Pos) /*!< QEI IE: DIR_Int Mask */ #define QEI_IE_ERR_Int_Pos 4 /*!< QEI IE: ERR_Int Position */ #define QEI_IE_ERR_Int_Msk (0x01UL << QEI_IE_ERR_Int_Pos) /*!< QEI IE: ERR_Int Mask */ #define QEI_IE_ENCLK_Int_Pos 5 /*!< QEI IE: ENCLK_Int Position */ #define QEI_IE_ENCLK_Int_Msk (0x01UL << QEI_IE_ENCLK_Int_Pos) /*!< QEI IE: ENCLK_Int Mask */ #define QEI_IE_POS0_Int_Pos 6 /*!< QEI IE: POS0_Int Position */ #define QEI_IE_POS0_Int_Msk (0x01UL << QEI_IE_POS0_Int_Pos) /*!< QEI IE: POS0_Int Mask */ #define QEI_IE_POS1_Int_Pos 7 /*!< QEI IE: POS1_Int Position */ #define QEI_IE_POS1_Int_Msk (0x01UL << QEI_IE_POS1_Int_Pos) /*!< QEI IE: POS1_Int Mask */ #define QEI_IE_POS2_Int_Pos 8 /*!< QEI IE: POS2_Int Position */ #define QEI_IE_POS2_Int_Msk (0x01UL << QEI_IE_POS2_Int_Pos) /*!< QEI IE: POS2_Int Mask */ #define QEI_IE_REV_Int_Pos 9 /*!< QEI IE: REV_Int Position */ #define QEI_IE_REV_Int_Msk (0x01UL << QEI_IE_REV_Int_Pos) /*!< QEI IE: REV_Int Mask */ #define QEI_IE_POS0REV_Int_Pos 10 /*!< QEI IE: POS0REV_Int Position */ #define QEI_IE_POS0REV_Int_Msk (0x01UL << QEI_IE_POS0REV_Int_Pos) /*!< QEI IE: POS0REV_Int Mask */ #define QEI_IE_POS1REV_Int_Pos 11 /*!< QEI IE: POS1REV_Int Position */ #define QEI_IE_POS1REV_Int_Msk (0x01UL << QEI_IE_POS1REV_Int_Pos) /*!< QEI IE: POS1REV_Int Mask */ #define QEI_IE_POS2REV_Int_Pos 12 /*!< QEI IE: POS2REV_Int Position */ #define QEI_IE_POS2REV_Int_Msk (0x01UL << QEI_IE_POS2REV_Int_Pos) /*!< QEI IE: POS2REV_Int Mask */ #define QEI_IE_REV1_Int_Pos 13 /*!< QEI IE: REV1_Int Position */ #define QEI_IE_REV1_Int_Msk (0x01UL << QEI_IE_REV1_Int_Pos) /*!< QEI IE: REV1_Int Mask */ #define QEI_IE_REV2_Int_Pos 14 /*!< QEI IE: REV2_Int Position */ #define QEI_IE_REV2_Int_Msk (0x01UL << QEI_IE_REV2_Int_Pos) /*!< QEI IE: REV2_Int Mask */ #define QEI_IE_MAXPOS_Int_Pos 15 /*!< QEI IE: MAXPOS_Int Position */ #define QEI_IE_MAXPOS_Int_Msk (0x01UL << QEI_IE_MAXPOS_Int_Pos) /*!< QEI IE: MAXPOS_Int Mask */ /* ----------------------------------- QEI_CLR ---------------------------------- */ #define QEI_CLR_INX_Int_Pos 0 /*!< QEI CLR: INX_Int Position */ #define QEI_CLR_INX_Int_Msk (0x01UL << QEI_CLR_INX_Int_Pos) /*!< QEI CLR: INX_Int Mask */ #define QEI_CLR_TIM_Int_Pos 1 /*!< QEI CLR: TIM_Int Position */ #define QEI_CLR_TIM_Int_Msk (0x01UL << QEI_CLR_TIM_Int_Pos) /*!< QEI CLR: TIM_Int Mask */ #define QEI_CLR_VELC_Int_Pos 2 /*!< QEI CLR: VELC_Int Position */ #define QEI_CLR_VELC_Int_Msk (0x01UL << QEI_CLR_VELC_Int_Pos) /*!< QEI CLR: VELC_Int Mask */ #define QEI_CLR_DIR_Int_Pos 3 /*!< QEI CLR: DIR_Int Position */ #define QEI_CLR_DIR_Int_Msk (0x01UL << QEI_CLR_DIR_Int_Pos) /*!< QEI CLR: DIR_Int Mask */ #define QEI_CLR_ERR_Int_Pos 4 /*!< QEI CLR: ERR_Int Position */ #define QEI_CLR_ERR_Int_Msk (0x01UL << QEI_CLR_ERR_Int_Pos) /*!< QEI CLR: ERR_Int Mask */ #define QEI_CLR_ENCLK_Int_Pos 5 /*!< QEI CLR: ENCLK_Int Position */ #define QEI_CLR_ENCLK_Int_Msk (0x01UL << QEI_CLR_ENCLK_Int_Pos) /*!< QEI CLR: ENCLK_Int Mask */ #define QEI_CLR_POS0_Int_Pos 6 /*!< QEI CLR: POS0_Int Position */ #define QEI_CLR_POS0_Int_Msk (0x01UL << QEI_CLR_POS0_Int_Pos) /*!< QEI CLR: POS0_Int Mask */ #define QEI_CLR_POS1_Int_Pos 7 /*!< QEI CLR: POS1_Int Position */ #define QEI_CLR_POS1_Int_Msk (0x01UL << QEI_CLR_POS1_Int_Pos) /*!< QEI CLR: POS1_Int Mask */ #define QEI_CLR_POS2_Int_Pos 8 /*!< QEI CLR: POS2_Int Position */ #define QEI_CLR_POS2_Int_Msk (0x01UL << QEI_CLR_POS2_Int_Pos) /*!< QEI CLR: POS2_Int Mask */ #define QEI_CLR_REV_Int_Pos 9 /*!< QEI CLR: REV_Int Position */ #define QEI_CLR_REV_Int_Msk (0x01UL << QEI_CLR_REV_Int_Pos) /*!< QEI CLR: REV_Int Mask */ #define QEI_CLR_POS0REV_Int_Pos 10 /*!< QEI CLR: POS0REV_Int Position */ #define QEI_CLR_POS0REV_Int_Msk (0x01UL << QEI_CLR_POS0REV_Int_Pos) /*!< QEI CLR: POS0REV_Int Mask */ #define QEI_CLR_POS1REV_Int_Pos 11 /*!< QEI CLR: POS1REV_Int Position */ #define QEI_CLR_POS1REV_Int_Msk (0x01UL << QEI_CLR_POS1REV_Int_Pos) /*!< QEI CLR: POS1REV_Int Mask */ #define QEI_CLR_REV1_Int_Pos 13 /*!< QEI CLR: REV1_Int Position */ #define QEI_CLR_REV1_Int_Msk (0x01UL << QEI_CLR_REV1_Int_Pos) /*!< QEI CLR: REV1_Int Mask */ #define QEI_CLR_REV2_Int_Pos 14 /*!< QEI CLR: REV2_Int Position */ #define QEI_CLR_REV2_Int_Msk (0x01UL << QEI_CLR_REV2_Int_Pos) /*!< QEI CLR: REV2_Int Mask */ #define QEI_CLR_MAXPOS_Int_Pos 15 /*!< QEI CLR: MAXPOS_Int Position */ #define QEI_CLR_MAXPOS_Int_Msk (0x01UL << QEI_CLR_MAXPOS_Int_Pos) /*!< QEI CLR: MAXPOS_Int Mask */ /* ----------------------------------- QEI_SET ---------------------------------- */ #define QEI_SET_INX_Int_Pos 0 /*!< QEI SET: INX_Int Position */ #define QEI_SET_INX_Int_Msk (0x01UL << QEI_SET_INX_Int_Pos) /*!< QEI SET: INX_Int Mask */ #define QEI_SET_TIM_Int_Pos 1 /*!< QEI SET: TIM_Int Position */ #define QEI_SET_TIM_Int_Msk (0x01UL << QEI_SET_TIM_Int_Pos) /*!< QEI SET: TIM_Int Mask */ #define QEI_SET_VELC_Int_Pos 2 /*!< QEI SET: VELC_Int Position */ #define QEI_SET_VELC_Int_Msk (0x01UL << QEI_SET_VELC_Int_Pos) /*!< QEI SET: VELC_Int Mask */ #define QEI_SET_DIR_Int_Pos 3 /*!< QEI SET: DIR_Int Position */ #define QEI_SET_DIR_Int_Msk (0x01UL << QEI_SET_DIR_Int_Pos) /*!< QEI SET: DIR_Int Mask */ #define QEI_SET_ERR_Int_Pos 4 /*!< QEI SET: ERR_Int Position */ #define QEI_SET_ERR_Int_Msk (0x01UL << QEI_SET_ERR_Int_Pos) /*!< QEI SET: ERR_Int Mask */ #define QEI_SET_ENCLK_Int_Pos 5 /*!< QEI SET: ENCLK_Int Position */ #define QEI_SET_ENCLK_Int_Msk (0x01UL << QEI_SET_ENCLK_Int_Pos) /*!< QEI SET: ENCLK_Int Mask */ #define QEI_SET_POS0_Int_Pos 6 /*!< QEI SET: POS0_Int Position */ #define QEI_SET_POS0_Int_Msk (0x01UL << QEI_SET_POS0_Int_Pos) /*!< QEI SET: POS0_Int Mask */ #define QEI_SET_POS1_Int_Pos 7 /*!< QEI SET: POS1_Int Position */ #define QEI_SET_POS1_Int_Msk (0x01UL << QEI_SET_POS1_Int_Pos) /*!< QEI SET: POS1_Int Mask */ #define QEI_SET_POS2_Int_Pos 8 /*!< QEI SET: POS2_Int Position */ #define QEI_SET_POS2_Int_Msk (0x01UL << QEI_SET_POS2_Int_Pos) /*!< QEI SET: POS2_Int Mask */ #define QEI_SET_REV_Int_Pos 9 /*!< QEI SET: REV_Int Position */ #define QEI_SET_REV_Int_Msk (0x01UL << QEI_SET_REV_Int_Pos) /*!< QEI SET: REV_Int Mask */ #define QEI_SET_POS0REV_Int_Pos 10 /*!< QEI SET: POS0REV_Int Position */ #define QEI_SET_POS0REV_Int_Msk (0x01UL << QEI_SET_POS0REV_Int_Pos) /*!< QEI SET: POS0REV_Int Mask */ #define QEI_SET_POS1REV_Int_Pos 11 /*!< QEI SET: POS1REV_Int Position */ #define QEI_SET_POS1REV_Int_Msk (0x01UL << QEI_SET_POS1REV_Int_Pos) /*!< QEI SET: POS1REV_Int Mask */ #define QEI_SET_POS2REV_Int_Pos 12 /*!< QEI SET: POS2REV_Int Position */ #define QEI_SET_POS2REV_Int_Msk (0x01UL << QEI_SET_POS2REV_Int_Pos) /*!< QEI SET: POS2REV_Int Mask */ #define QEI_SET_REV1_Int_Pos 13 /*!< QEI SET: REV1_Int Position */ #define QEI_SET_REV1_Int_Msk (0x01UL << QEI_SET_REV1_Int_Pos) /*!< QEI SET: REV1_Int Mask */ #define QEI_SET_REV2_Int_Pos 14 /*!< QEI SET: REV2_Int Position */ #define QEI_SET_REV2_Int_Msk (0x01UL << QEI_SET_REV2_Int_Pos) /*!< QEI SET: REV2_Int Mask */ #define QEI_SET_MAXPOS_Int_Pos 15 /*!< QEI SET: MAXPOS_Int Position */ #define QEI_SET_MAXPOS_Int_Msk (0x01UL << QEI_SET_MAXPOS_Int_Pos) /*!< QEI SET: MAXPOS_Int Mask */ /* ================================================================================ */ /* ================ struct 'GIMA' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------- GIMA_CAP0_0_IN ------------------------------- */ #define GIMA_CAP0_0_IN_INV_Pos 0 /*!< GIMA CAP0_0_IN: INV Position */ #define GIMA_CAP0_0_IN_INV_Msk (0x01UL << GIMA_CAP0_0_IN_INV_Pos) /*!< GIMA CAP0_0_IN: INV Mask */ #define GIMA_CAP0_0_IN_EDGE_Pos 1 /*!< GIMA CAP0_0_IN: EDGE Position */ #define GIMA_CAP0_0_IN_EDGE_Msk (0x01UL << GIMA_CAP0_0_IN_EDGE_Pos) /*!< GIMA CAP0_0_IN: EDGE Mask */ #define GIMA_CAP0_0_IN_SYNCH_Pos 2 /*!< GIMA CAP0_0_IN: SYNCH Position */ #define GIMA_CAP0_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_0_IN_SYNCH_Pos) /*!< GIMA CAP0_0_IN: SYNCH Mask */ #define GIMA_CAP0_0_IN_PULSE_Pos 3 /*!< GIMA CAP0_0_IN: PULSE Position */ #define GIMA_CAP0_0_IN_PULSE_Msk (0x01UL << GIMA_CAP0_0_IN_PULSE_Pos) /*!< GIMA CAP0_0_IN: PULSE Mask */ #define GIMA_CAP0_0_IN_SELECT_Pos 4 /*!< GIMA CAP0_0_IN: SELECT Position */ #define GIMA_CAP0_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_0_IN_SELECT_Pos) /*!< GIMA CAP0_0_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP0_1_IN ------------------------------- */ #define GIMA_CAP0_1_IN_INV_Pos 0 /*!< GIMA CAP0_1_IN: INV Position */ #define GIMA_CAP0_1_IN_INV_Msk (0x01UL << GIMA_CAP0_1_IN_INV_Pos) /*!< GIMA CAP0_1_IN: INV Mask */ #define GIMA_CAP0_1_IN_EDGE_Pos 1 /*!< GIMA CAP0_1_IN: EDGE Position */ #define GIMA_CAP0_1_IN_EDGE_Msk (0x01UL << GIMA_CAP0_1_IN_EDGE_Pos) /*!< GIMA CAP0_1_IN: EDGE Mask */ #define GIMA_CAP0_1_IN_SYNCH_Pos 2 /*!< GIMA CAP0_1_IN: SYNCH Position */ #define GIMA_CAP0_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_1_IN_SYNCH_Pos) /*!< GIMA CAP0_1_IN: SYNCH Mask */ #define GIMA_CAP0_1_IN_PULSE_Pos 3 /*!< GIMA CAP0_1_IN: PULSE Position */ #define GIMA_CAP0_1_IN_PULSE_Msk (0x01UL << GIMA_CAP0_1_IN_PULSE_Pos) /*!< GIMA CAP0_1_IN: PULSE Mask */ #define GIMA_CAP0_1_IN_SELECT_Pos 4 /*!< GIMA CAP0_1_IN: SELECT Position */ #define GIMA_CAP0_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_1_IN_SELECT_Pos) /*!< GIMA CAP0_1_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP0_2_IN ------------------------------- */ #define GIMA_CAP0_2_IN_INV_Pos 0 /*!< GIMA CAP0_2_IN: INV Position */ #define GIMA_CAP0_2_IN_INV_Msk (0x01UL << GIMA_CAP0_2_IN_INV_Pos) /*!< GIMA CAP0_2_IN: INV Mask */ #define GIMA_CAP0_2_IN_EDGE_Pos 1 /*!< GIMA CAP0_2_IN: EDGE Position */ #define GIMA_CAP0_2_IN_EDGE_Msk (0x01UL << GIMA_CAP0_2_IN_EDGE_Pos) /*!< GIMA CAP0_2_IN: EDGE Mask */ #define GIMA_CAP0_2_IN_SYNCH_Pos 2 /*!< GIMA CAP0_2_IN: SYNCH Position */ #define GIMA_CAP0_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_2_IN_SYNCH_Pos) /*!< GIMA CAP0_2_IN: SYNCH Mask */ #define GIMA_CAP0_2_IN_PULSE_Pos 3 /*!< GIMA CAP0_2_IN: PULSE Position */ #define GIMA_CAP0_2_IN_PULSE_Msk (0x01UL << GIMA_CAP0_2_IN_PULSE_Pos) /*!< GIMA CAP0_2_IN: PULSE Mask */ #define GIMA_CAP0_2_IN_SELECT_Pos 4 /*!< GIMA CAP0_2_IN: SELECT Position */ #define GIMA_CAP0_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_2_IN_SELECT_Pos) /*!< GIMA CAP0_2_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP0_3_IN ------------------------------- */ #define GIMA_CAP0_3_IN_INV_Pos 0 /*!< GIMA CAP0_3_IN: INV Position */ #define GIMA_CAP0_3_IN_INV_Msk (0x01UL << GIMA_CAP0_3_IN_INV_Pos) /*!< GIMA CAP0_3_IN: INV Mask */ #define GIMA_CAP0_3_IN_EDGE_Pos 1 /*!< GIMA CAP0_3_IN: EDGE Position */ #define GIMA_CAP0_3_IN_EDGE_Msk (0x01UL << GIMA_CAP0_3_IN_EDGE_Pos) /*!< GIMA CAP0_3_IN: EDGE Mask */ #define GIMA_CAP0_3_IN_SYNCH_Pos 2 /*!< GIMA CAP0_3_IN: SYNCH Position */ #define GIMA_CAP0_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP0_3_IN_SYNCH_Pos) /*!< GIMA CAP0_3_IN: SYNCH Mask */ #define GIMA_CAP0_3_IN_PULSE_Pos 3 /*!< GIMA CAP0_3_IN: PULSE Position */ #define GIMA_CAP0_3_IN_PULSE_Msk (0x01UL << GIMA_CAP0_3_IN_PULSE_Pos) /*!< GIMA CAP0_3_IN: PULSE Mask */ #define GIMA_CAP0_3_IN_SELECT_Pos 4 /*!< GIMA CAP0_3_IN: SELECT Position */ #define GIMA_CAP0_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP0_3_IN_SELECT_Pos) /*!< GIMA CAP0_3_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP1_0_IN ------------------------------- */ #define GIMA_CAP1_0_IN_INV_Pos 0 /*!< GIMA CAP1_0_IN: INV Position */ #define GIMA_CAP1_0_IN_INV_Msk (0x01UL << GIMA_CAP1_0_IN_INV_Pos) /*!< GIMA CAP1_0_IN: INV Mask */ #define GIMA_CAP1_0_IN_EDGE_Pos 1 /*!< GIMA CAP1_0_IN: EDGE Position */ #define GIMA_CAP1_0_IN_EDGE_Msk (0x01UL << GIMA_CAP1_0_IN_EDGE_Pos) /*!< GIMA CAP1_0_IN: EDGE Mask */ #define GIMA_CAP1_0_IN_SYNCH_Pos 2 /*!< GIMA CAP1_0_IN: SYNCH Position */ #define GIMA_CAP1_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_0_IN_SYNCH_Pos) /*!< GIMA CAP1_0_IN: SYNCH Mask */ #define GIMA_CAP1_0_IN_PULSE_Pos 3 /*!< GIMA CAP1_0_IN: PULSE Position */ #define GIMA_CAP1_0_IN_PULSE_Msk (0x01UL << GIMA_CAP1_0_IN_PULSE_Pos) /*!< GIMA CAP1_0_IN: PULSE Mask */ #define GIMA_CAP1_0_IN_SELECT_Pos 4 /*!< GIMA CAP1_0_IN: SELECT Position */ #define GIMA_CAP1_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_0_IN_SELECT_Pos) /*!< GIMA CAP1_0_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP1_1_IN ------------------------------- */ #define GIMA_CAP1_1_IN_INV_Pos 0 /*!< GIMA CAP1_1_IN: INV Position */ #define GIMA_CAP1_1_IN_INV_Msk (0x01UL << GIMA_CAP1_1_IN_INV_Pos) /*!< GIMA CAP1_1_IN: INV Mask */ #define GIMA_CAP1_1_IN_EDGE_Pos 1 /*!< GIMA CAP1_1_IN: EDGE Position */ #define GIMA_CAP1_1_IN_EDGE_Msk (0x01UL << GIMA_CAP1_1_IN_EDGE_Pos) /*!< GIMA CAP1_1_IN: EDGE Mask */ #define GIMA_CAP1_1_IN_SYNCH_Pos 2 /*!< GIMA CAP1_1_IN: SYNCH Position */ #define GIMA_CAP1_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_1_IN_SYNCH_Pos) /*!< GIMA CAP1_1_IN: SYNCH Mask */ #define GIMA_CAP1_1_IN_PULSE_Pos 3 /*!< GIMA CAP1_1_IN: PULSE Position */ #define GIMA_CAP1_1_IN_PULSE_Msk (0x01UL << GIMA_CAP1_1_IN_PULSE_Pos) /*!< GIMA CAP1_1_IN: PULSE Mask */ #define GIMA_CAP1_1_IN_SELECT_Pos 4 /*!< GIMA CAP1_1_IN: SELECT Position */ #define GIMA_CAP1_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_1_IN_SELECT_Pos) /*!< GIMA CAP1_1_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP1_2_IN ------------------------------- */ #define GIMA_CAP1_2_IN_INV_Pos 0 /*!< GIMA CAP1_2_IN: INV Position */ #define GIMA_CAP1_2_IN_INV_Msk (0x01UL << GIMA_CAP1_2_IN_INV_Pos) /*!< GIMA CAP1_2_IN: INV Mask */ #define GIMA_CAP1_2_IN_EDGE_Pos 1 /*!< GIMA CAP1_2_IN: EDGE Position */ #define GIMA_CAP1_2_IN_EDGE_Msk (0x01UL << GIMA_CAP1_2_IN_EDGE_Pos) /*!< GIMA CAP1_2_IN: EDGE Mask */ #define GIMA_CAP1_2_IN_SYNCH_Pos 2 /*!< GIMA CAP1_2_IN: SYNCH Position */ #define GIMA_CAP1_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_2_IN_SYNCH_Pos) /*!< GIMA CAP1_2_IN: SYNCH Mask */ #define GIMA_CAP1_2_IN_PULSE_Pos 3 /*!< GIMA CAP1_2_IN: PULSE Position */ #define GIMA_CAP1_2_IN_PULSE_Msk (0x01UL << GIMA_CAP1_2_IN_PULSE_Pos) /*!< GIMA CAP1_2_IN: PULSE Mask */ #define GIMA_CAP1_2_IN_SELECT_Pos 4 /*!< GIMA CAP1_2_IN: SELECT Position */ #define GIMA_CAP1_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_2_IN_SELECT_Pos) /*!< GIMA CAP1_2_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP1_3_IN ------------------------------- */ #define GIMA_CAP1_3_IN_INV_Pos 0 /*!< GIMA CAP1_3_IN: INV Position */ #define GIMA_CAP1_3_IN_INV_Msk (0x01UL << GIMA_CAP1_3_IN_INV_Pos) /*!< GIMA CAP1_3_IN: INV Mask */ #define GIMA_CAP1_3_IN_EDGE_Pos 1 /*!< GIMA CAP1_3_IN: EDGE Position */ #define GIMA_CAP1_3_IN_EDGE_Msk (0x01UL << GIMA_CAP1_3_IN_EDGE_Pos) /*!< GIMA CAP1_3_IN: EDGE Mask */ #define GIMA_CAP1_3_IN_SYNCH_Pos 2 /*!< GIMA CAP1_3_IN: SYNCH Position */ #define GIMA_CAP1_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP1_3_IN_SYNCH_Pos) /*!< GIMA CAP1_3_IN: SYNCH Mask */ #define GIMA_CAP1_3_IN_PULSE_Pos 3 /*!< GIMA CAP1_3_IN: PULSE Position */ #define GIMA_CAP1_3_IN_PULSE_Msk (0x01UL << GIMA_CAP1_3_IN_PULSE_Pos) /*!< GIMA CAP1_3_IN: PULSE Mask */ #define GIMA_CAP1_3_IN_SELECT_Pos 4 /*!< GIMA CAP1_3_IN: SELECT Position */ #define GIMA_CAP1_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP1_3_IN_SELECT_Pos) /*!< GIMA CAP1_3_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP2_0_IN ------------------------------- */ #define GIMA_CAP2_0_IN_INV_Pos 0 /*!< GIMA CAP2_0_IN: INV Position */ #define GIMA_CAP2_0_IN_INV_Msk (0x01UL << GIMA_CAP2_0_IN_INV_Pos) /*!< GIMA CAP2_0_IN: INV Mask */ #define GIMA_CAP2_0_IN_EDGE_Pos 1 /*!< GIMA CAP2_0_IN: EDGE Position */ #define GIMA_CAP2_0_IN_EDGE_Msk (0x01UL << GIMA_CAP2_0_IN_EDGE_Pos) /*!< GIMA CAP2_0_IN: EDGE Mask */ #define GIMA_CAP2_0_IN_SYNCH_Pos 2 /*!< GIMA CAP2_0_IN: SYNCH Position */ #define GIMA_CAP2_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_0_IN_SYNCH_Pos) /*!< GIMA CAP2_0_IN: SYNCH Mask */ #define GIMA_CAP2_0_IN_PULSE_Pos 3 /*!< GIMA CAP2_0_IN: PULSE Position */ #define GIMA_CAP2_0_IN_PULSE_Msk (0x01UL << GIMA_CAP2_0_IN_PULSE_Pos) /*!< GIMA CAP2_0_IN: PULSE Mask */ #define GIMA_CAP2_0_IN_SELECT_Pos 4 /*!< GIMA CAP2_0_IN: SELECT Position */ #define GIMA_CAP2_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_0_IN_SELECT_Pos) /*!< GIMA CAP2_0_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP2_1_IN ------------------------------- */ #define GIMA_CAP2_1_IN_INV_Pos 0 /*!< GIMA CAP2_1_IN: INV Position */ #define GIMA_CAP2_1_IN_INV_Msk (0x01UL << GIMA_CAP2_1_IN_INV_Pos) /*!< GIMA CAP2_1_IN: INV Mask */ #define GIMA_CAP2_1_IN_EDGE_Pos 1 /*!< GIMA CAP2_1_IN: EDGE Position */ #define GIMA_CAP2_1_IN_EDGE_Msk (0x01UL << GIMA_CAP2_1_IN_EDGE_Pos) /*!< GIMA CAP2_1_IN: EDGE Mask */ #define GIMA_CAP2_1_IN_SYNCH_Pos 2 /*!< GIMA CAP2_1_IN: SYNCH Position */ #define GIMA_CAP2_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_1_IN_SYNCH_Pos) /*!< GIMA CAP2_1_IN: SYNCH Mask */ #define GIMA_CAP2_1_IN_PULSE_Pos 3 /*!< GIMA CAP2_1_IN: PULSE Position */ #define GIMA_CAP2_1_IN_PULSE_Msk (0x01UL << GIMA_CAP2_1_IN_PULSE_Pos) /*!< GIMA CAP2_1_IN: PULSE Mask */ #define GIMA_CAP2_1_IN_SELECT_Pos 4 /*!< GIMA CAP2_1_IN: SELECT Position */ #define GIMA_CAP2_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_1_IN_SELECT_Pos) /*!< GIMA CAP2_1_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP2_2_IN ------------------------------- */ #define GIMA_CAP2_2_IN_INV_Pos 0 /*!< GIMA CAP2_2_IN: INV Position */ #define GIMA_CAP2_2_IN_INV_Msk (0x01UL << GIMA_CAP2_2_IN_INV_Pos) /*!< GIMA CAP2_2_IN: INV Mask */ #define GIMA_CAP2_2_IN_EDGE_Pos 1 /*!< GIMA CAP2_2_IN: EDGE Position */ #define GIMA_CAP2_2_IN_EDGE_Msk (0x01UL << GIMA_CAP2_2_IN_EDGE_Pos) /*!< GIMA CAP2_2_IN: EDGE Mask */ #define GIMA_CAP2_2_IN_SYNCH_Pos 2 /*!< GIMA CAP2_2_IN: SYNCH Position */ #define GIMA_CAP2_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_2_IN_SYNCH_Pos) /*!< GIMA CAP2_2_IN: SYNCH Mask */ #define GIMA_CAP2_2_IN_PULSE_Pos 3 /*!< GIMA CAP2_2_IN: PULSE Position */ #define GIMA_CAP2_2_IN_PULSE_Msk (0x01UL << GIMA_CAP2_2_IN_PULSE_Pos) /*!< GIMA CAP2_2_IN: PULSE Mask */ #define GIMA_CAP2_2_IN_SELECT_Pos 4 /*!< GIMA CAP2_2_IN: SELECT Position */ #define GIMA_CAP2_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_2_IN_SELECT_Pos) /*!< GIMA CAP2_2_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP2_3_IN ------------------------------- */ #define GIMA_CAP2_3_IN_INV_Pos 0 /*!< GIMA CAP2_3_IN: INV Position */ #define GIMA_CAP2_3_IN_INV_Msk (0x01UL << GIMA_CAP2_3_IN_INV_Pos) /*!< GIMA CAP2_3_IN: INV Mask */ #define GIMA_CAP2_3_IN_EDGE_Pos 1 /*!< GIMA CAP2_3_IN: EDGE Position */ #define GIMA_CAP2_3_IN_EDGE_Msk (0x01UL << GIMA_CAP2_3_IN_EDGE_Pos) /*!< GIMA CAP2_3_IN: EDGE Mask */ #define GIMA_CAP2_3_IN_SYNCH_Pos 2 /*!< GIMA CAP2_3_IN: SYNCH Position */ #define GIMA_CAP2_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP2_3_IN_SYNCH_Pos) /*!< GIMA CAP2_3_IN: SYNCH Mask */ #define GIMA_CAP2_3_IN_PULSE_Pos 3 /*!< GIMA CAP2_3_IN: PULSE Position */ #define GIMA_CAP2_3_IN_PULSE_Msk (0x01UL << GIMA_CAP2_3_IN_PULSE_Pos) /*!< GIMA CAP2_3_IN: PULSE Mask */ #define GIMA_CAP2_3_IN_SELECT_Pos 4 /*!< GIMA CAP2_3_IN: SELECT Position */ #define GIMA_CAP2_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP2_3_IN_SELECT_Pos) /*!< GIMA CAP2_3_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP3_0_IN ------------------------------- */ #define GIMA_CAP3_0_IN_INV_Pos 0 /*!< GIMA CAP3_0_IN: INV Position */ #define GIMA_CAP3_0_IN_INV_Msk (0x01UL << GIMA_CAP3_0_IN_INV_Pos) /*!< GIMA CAP3_0_IN: INV Mask */ #define GIMA_CAP3_0_IN_EDGE_Pos 1 /*!< GIMA CAP3_0_IN: EDGE Position */ #define GIMA_CAP3_0_IN_EDGE_Msk (0x01UL << GIMA_CAP3_0_IN_EDGE_Pos) /*!< GIMA CAP3_0_IN: EDGE Mask */ #define GIMA_CAP3_0_IN_SYNCH_Pos 2 /*!< GIMA CAP3_0_IN: SYNCH Position */ #define GIMA_CAP3_0_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_0_IN_SYNCH_Pos) /*!< GIMA CAP3_0_IN: SYNCH Mask */ #define GIMA_CAP3_0_IN_PULSE_Pos 3 /*!< GIMA CAP3_0_IN: PULSE Position */ #define GIMA_CAP3_0_IN_PULSE_Msk (0x01UL << GIMA_CAP3_0_IN_PULSE_Pos) /*!< GIMA CAP3_0_IN: PULSE Mask */ #define GIMA_CAP3_0_IN_SELECT_Pos 4 /*!< GIMA CAP3_0_IN: SELECT Position */ #define GIMA_CAP3_0_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_0_IN_SELECT_Pos) /*!< GIMA CAP3_0_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP3_1_IN ------------------------------- */ #define GIMA_CAP3_1_IN_INV_Pos 0 /*!< GIMA CAP3_1_IN: INV Position */ #define GIMA_CAP3_1_IN_INV_Msk (0x01UL << GIMA_CAP3_1_IN_INV_Pos) /*!< GIMA CAP3_1_IN: INV Mask */ #define GIMA_CAP3_1_IN_EDGE_Pos 1 /*!< GIMA CAP3_1_IN: EDGE Position */ #define GIMA_CAP3_1_IN_EDGE_Msk (0x01UL << GIMA_CAP3_1_IN_EDGE_Pos) /*!< GIMA CAP3_1_IN: EDGE Mask */ #define GIMA_CAP3_1_IN_SYNCH_Pos 2 /*!< GIMA CAP3_1_IN: SYNCH Position */ #define GIMA_CAP3_1_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_1_IN_SYNCH_Pos) /*!< GIMA CAP3_1_IN: SYNCH Mask */ #define GIMA_CAP3_1_IN_PULSE_Pos 3 /*!< GIMA CAP3_1_IN: PULSE Position */ #define GIMA_CAP3_1_IN_PULSE_Msk (0x01UL << GIMA_CAP3_1_IN_PULSE_Pos) /*!< GIMA CAP3_1_IN: PULSE Mask */ #define GIMA_CAP3_1_IN_SELECT_Pos 4 /*!< GIMA CAP3_1_IN: SELECT Position */ #define GIMA_CAP3_1_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_1_IN_SELECT_Pos) /*!< GIMA CAP3_1_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP3_2_IN ------------------------------- */ #define GIMA_CAP3_2_IN_INV_Pos 0 /*!< GIMA CAP3_2_IN: INV Position */ #define GIMA_CAP3_2_IN_INV_Msk (0x01UL << GIMA_CAP3_2_IN_INV_Pos) /*!< GIMA CAP3_2_IN: INV Mask */ #define GIMA_CAP3_2_IN_EDGE_Pos 1 /*!< GIMA CAP3_2_IN: EDGE Position */ #define GIMA_CAP3_2_IN_EDGE_Msk (0x01UL << GIMA_CAP3_2_IN_EDGE_Pos) /*!< GIMA CAP3_2_IN: EDGE Mask */ #define GIMA_CAP3_2_IN_SYNCH_Pos 2 /*!< GIMA CAP3_2_IN: SYNCH Position */ #define GIMA_CAP3_2_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_2_IN_SYNCH_Pos) /*!< GIMA CAP3_2_IN: SYNCH Mask */ #define GIMA_CAP3_2_IN_PULSE_Pos 3 /*!< GIMA CAP3_2_IN: PULSE Position */ #define GIMA_CAP3_2_IN_PULSE_Msk (0x01UL << GIMA_CAP3_2_IN_PULSE_Pos) /*!< GIMA CAP3_2_IN: PULSE Mask */ #define GIMA_CAP3_2_IN_SELECT_Pos 4 /*!< GIMA CAP3_2_IN: SELECT Position */ #define GIMA_CAP3_2_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_2_IN_SELECT_Pos) /*!< GIMA CAP3_2_IN: SELECT Mask */ /* ------------------------------- GIMA_CAP3_3_IN ------------------------------- */ #define GIMA_CAP3_3_IN_INV_Pos 0 /*!< GIMA CAP3_3_IN: INV Position */ #define GIMA_CAP3_3_IN_INV_Msk (0x01UL << GIMA_CAP3_3_IN_INV_Pos) /*!< GIMA CAP3_3_IN: INV Mask */ #define GIMA_CAP3_3_IN_EDGE_Pos 1 /*!< GIMA CAP3_3_IN: EDGE Position */ #define GIMA_CAP3_3_IN_EDGE_Msk (0x01UL << GIMA_CAP3_3_IN_EDGE_Pos) /*!< GIMA CAP3_3_IN: EDGE Mask */ #define GIMA_CAP3_3_IN_SYNCH_Pos 2 /*!< GIMA CAP3_3_IN: SYNCH Position */ #define GIMA_CAP3_3_IN_SYNCH_Msk (0x01UL << GIMA_CAP3_3_IN_SYNCH_Pos) /*!< GIMA CAP3_3_IN: SYNCH Mask */ #define GIMA_CAP3_3_IN_PULSE_Pos 3 /*!< GIMA CAP3_3_IN: PULSE Position */ #define GIMA_CAP3_3_IN_PULSE_Msk (0x01UL << GIMA_CAP3_3_IN_PULSE_Pos) /*!< GIMA CAP3_3_IN: PULSE Mask */ #define GIMA_CAP3_3_IN_SELECT_Pos 4 /*!< GIMA CAP3_3_IN: SELECT Position */ #define GIMA_CAP3_3_IN_SELECT_Msk (0x0fUL << GIMA_CAP3_3_IN_SELECT_Pos) /*!< GIMA CAP3_3_IN: SELECT Mask */ /* ------------------------------- GIMA_CTIN_0_IN ------------------------------- */ #define GIMA_CTIN_0_IN_INV_Pos 0 /*!< GIMA CTIN_0_IN: INV Position */ #define GIMA_CTIN_0_IN_INV_Msk (0x01UL << GIMA_CTIN_0_IN_INV_Pos) /*!< GIMA CTIN_0_IN: INV Mask */ #define GIMA_CTIN_0_IN_EDGE_Pos 1 /*!< GIMA CTIN_0_IN: EDGE Position */ #define GIMA_CTIN_0_IN_EDGE_Msk (0x01UL << GIMA_CTIN_0_IN_EDGE_Pos) /*!< GIMA CTIN_0_IN: EDGE Mask */ #define GIMA_CTIN_0_IN_SYNCH_Pos 2 /*!< GIMA CTIN_0_IN: SYNCH Position */ #define GIMA_CTIN_0_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_0_IN_SYNCH_Pos) /*!< GIMA CTIN_0_IN: SYNCH Mask */ #define GIMA_CTIN_0_IN_PULSE_Pos 3 /*!< GIMA CTIN_0_IN: PULSE Position */ #define GIMA_CTIN_0_IN_PULSE_Msk (0x01UL << GIMA_CTIN_0_IN_PULSE_Pos) /*!< GIMA CTIN_0_IN: PULSE Mask */ #define GIMA_CTIN_0_IN_SELECT_Pos 4 /*!< GIMA CTIN_0_IN: SELECT Position */ #define GIMA_CTIN_0_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_0_IN_SELECT_Pos) /*!< GIMA CTIN_0_IN: SELECT Mask */ /* ------------------------------- GIMA_CTIN_1_IN ------------------------------- */ #define GIMA_CTIN_1_IN_INV_Pos 0 /*!< GIMA CTIN_1_IN: INV Position */ #define GIMA_CTIN_1_IN_INV_Msk (0x01UL << GIMA_CTIN_1_IN_INV_Pos) /*!< GIMA CTIN_1_IN: INV Mask */ #define GIMA_CTIN_1_IN_EDGE_Pos 1 /*!< GIMA CTIN_1_IN: EDGE Position */ #define GIMA_CTIN_1_IN_EDGE_Msk (0x01UL << GIMA_CTIN_1_IN_EDGE_Pos) /*!< GIMA CTIN_1_IN: EDGE Mask */ #define GIMA_CTIN_1_IN_SYNCH_Pos 2 /*!< GIMA CTIN_1_IN: SYNCH Position */ #define GIMA_CTIN_1_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_1_IN_SYNCH_Pos) /*!< GIMA CTIN_1_IN: SYNCH Mask */ #define GIMA_CTIN_1_IN_PULSE_Pos 3 /*!< GIMA CTIN_1_IN: PULSE Position */ #define GIMA_CTIN_1_IN_PULSE_Msk (0x01UL << GIMA_CTIN_1_IN_PULSE_Pos) /*!< GIMA CTIN_1_IN: PULSE Mask */ #define GIMA_CTIN_1_IN_SELECT_Pos 4 /*!< GIMA CTIN_1_IN: SELECT Position */ #define GIMA_CTIN_1_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_1_IN_SELECT_Pos) /*!< GIMA CTIN_1_IN: SELECT Mask */ /* ------------------------------- GIMA_CTIN_2_IN ------------------------------- */ #define GIMA_CTIN_2_IN_INV_Pos 0 /*!< GIMA CTIN_2_IN: INV Position */ #define GIMA_CTIN_2_IN_INV_Msk (0x01UL << GIMA_CTIN_2_IN_INV_Pos) /*!< GIMA CTIN_2_IN: INV Mask */ #define GIMA_CTIN_2_IN_EDGE_Pos 1 /*!< GIMA CTIN_2_IN: EDGE Position */ #define GIMA_CTIN_2_IN_EDGE_Msk (0x01UL << GIMA_CTIN_2_IN_EDGE_Pos) /*!< GIMA CTIN_2_IN: EDGE Mask */ #define GIMA_CTIN_2_IN_SYNCH_Pos 2 /*!< GIMA CTIN_2_IN: SYNCH Position */ #define GIMA_CTIN_2_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_2_IN_SYNCH_Pos) /*!< GIMA CTIN_2_IN: SYNCH Mask */ #define GIMA_CTIN_2_IN_PULSE_Pos 3 /*!< GIMA CTIN_2_IN: PULSE Position */ #define GIMA_CTIN_2_IN_PULSE_Msk (0x01UL << GIMA_CTIN_2_IN_PULSE_Pos) /*!< GIMA CTIN_2_IN: PULSE Mask */ #define GIMA_CTIN_2_IN_SELECT_Pos 4 /*!< GIMA CTIN_2_IN: SELECT Position */ #define GIMA_CTIN_2_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_2_IN_SELECT_Pos) /*!< GIMA CTIN_2_IN: SELECT Mask */ /* ------------------------------- GIMA_CTIN_3_IN ------------------------------- */ #define GIMA_CTIN_3_IN_INV_Pos 0 /*!< GIMA CTIN_3_IN: INV Position */ #define GIMA_CTIN_3_IN_INV_Msk (0x01UL << GIMA_CTIN_3_IN_INV_Pos) /*!< GIMA CTIN_3_IN: INV Mask */ #define GIMA_CTIN_3_IN_EDGE_Pos 1 /*!< GIMA CTIN_3_IN: EDGE Position */ #define GIMA_CTIN_3_IN_EDGE_Msk (0x01UL << GIMA_CTIN_3_IN_EDGE_Pos) /*!< GIMA CTIN_3_IN: EDGE Mask */ #define GIMA_CTIN_3_IN_SYNCH_Pos 2 /*!< GIMA CTIN_3_IN: SYNCH Position */ #define GIMA_CTIN_3_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_3_IN_SYNCH_Pos) /*!< GIMA CTIN_3_IN: SYNCH Mask */ #define GIMA_CTIN_3_IN_PULSE_Pos 3 /*!< GIMA CTIN_3_IN: PULSE Position */ #define GIMA_CTIN_3_IN_PULSE_Msk (0x01UL << GIMA_CTIN_3_IN_PULSE_Pos) /*!< GIMA CTIN_3_IN: PULSE Mask */ #define GIMA_CTIN_3_IN_SELECT_Pos 4 /*!< GIMA CTIN_3_IN: SELECT Position */ #define GIMA_CTIN_3_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_3_IN_SELECT_Pos) /*!< GIMA CTIN_3_IN: SELECT Mask */ /* ------------------------------- GIMA_CTIN_4_IN ------------------------------- */ #define GIMA_CTIN_4_IN_INV_Pos 0 /*!< GIMA CTIN_4_IN: INV Position */ #define GIMA_CTIN_4_IN_INV_Msk (0x01UL << GIMA_CTIN_4_IN_INV_Pos) /*!< GIMA CTIN_4_IN: INV Mask */ #define GIMA_CTIN_4_IN_EDGE_Pos 1 /*!< GIMA CTIN_4_IN: EDGE Position */ #define GIMA_CTIN_4_IN_EDGE_Msk (0x01UL << GIMA_CTIN_4_IN_EDGE_Pos) /*!< GIMA CTIN_4_IN: EDGE Mask */ #define GIMA_CTIN_4_IN_SYNCH_Pos 2 /*!< GIMA CTIN_4_IN: SYNCH Position */ #define GIMA_CTIN_4_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_4_IN_SYNCH_Pos) /*!< GIMA CTIN_4_IN: SYNCH Mask */ #define GIMA_CTIN_4_IN_PULSE_Pos 3 /*!< GIMA CTIN_4_IN: PULSE Position */ #define GIMA_CTIN_4_IN_PULSE_Msk (0x01UL << GIMA_CTIN_4_IN_PULSE_Pos) /*!< GIMA CTIN_4_IN: PULSE Mask */ #define GIMA_CTIN_4_IN_SELECT_Pos 4 /*!< GIMA CTIN_4_IN: SELECT Position */ #define GIMA_CTIN_4_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_4_IN_SELECT_Pos) /*!< GIMA CTIN_4_IN: SELECT Mask */ /* ------------------------------- GIMA_CTIN_5_IN ------------------------------- */ #define GIMA_CTIN_5_IN_INV_Pos 0 /*!< GIMA CTIN_5_IN: INV Position */ #define GIMA_CTIN_5_IN_INV_Msk (0x01UL << GIMA_CTIN_5_IN_INV_Pos) /*!< GIMA CTIN_5_IN: INV Mask */ #define GIMA_CTIN_5_IN_EDGE_Pos 1 /*!< GIMA CTIN_5_IN: EDGE Position */ #define GIMA_CTIN_5_IN_EDGE_Msk (0x01UL << GIMA_CTIN_5_IN_EDGE_Pos) /*!< GIMA CTIN_5_IN: EDGE Mask */ #define GIMA_CTIN_5_IN_SYNCH_Pos 2 /*!< GIMA CTIN_5_IN: SYNCH Position */ #define GIMA_CTIN_5_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_5_IN_SYNCH_Pos) /*!< GIMA CTIN_5_IN: SYNCH Mask */ #define GIMA_CTIN_5_IN_PULSE_Pos 3 /*!< GIMA CTIN_5_IN: PULSE Position */ #define GIMA_CTIN_5_IN_PULSE_Msk (0x01UL << GIMA_CTIN_5_IN_PULSE_Pos) /*!< GIMA CTIN_5_IN: PULSE Mask */ #define GIMA_CTIN_5_IN_SELECT_Pos 4 /*!< GIMA CTIN_5_IN: SELECT Position */ #define GIMA_CTIN_5_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_5_IN_SELECT_Pos) /*!< GIMA CTIN_5_IN: SELECT Mask */ /* ------------------------------- GIMA_CTIN_6_IN ------------------------------- */ #define GIMA_CTIN_6_IN_INV_Pos 0 /*!< GIMA CTIN_6_IN: INV Position */ #define GIMA_CTIN_6_IN_INV_Msk (0x01UL << GIMA_CTIN_6_IN_INV_Pos) /*!< GIMA CTIN_6_IN: INV Mask */ #define GIMA_CTIN_6_IN_EDGE_Pos 1 /*!< GIMA CTIN_6_IN: EDGE Position */ #define GIMA_CTIN_6_IN_EDGE_Msk (0x01UL << GIMA_CTIN_6_IN_EDGE_Pos) /*!< GIMA CTIN_6_IN: EDGE Mask */ #define GIMA_CTIN_6_IN_SYNCH_Pos 2 /*!< GIMA CTIN_6_IN: SYNCH Position */ #define GIMA_CTIN_6_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_6_IN_SYNCH_Pos) /*!< GIMA CTIN_6_IN: SYNCH Mask */ #define GIMA_CTIN_6_IN_PULSE_Pos 3 /*!< GIMA CTIN_6_IN: PULSE Position */ #define GIMA_CTIN_6_IN_PULSE_Msk (0x01UL << GIMA_CTIN_6_IN_PULSE_Pos) /*!< GIMA CTIN_6_IN: PULSE Mask */ #define GIMA_CTIN_6_IN_SELECT_Pos 4 /*!< GIMA CTIN_6_IN: SELECT Position */ #define GIMA_CTIN_6_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_6_IN_SELECT_Pos) /*!< GIMA CTIN_6_IN: SELECT Mask */ /* ------------------------------- GIMA_CTIN_7_IN ------------------------------- */ #define GIMA_CTIN_7_IN_INV_Pos 0 /*!< GIMA CTIN_7_IN: INV Position */ #define GIMA_CTIN_7_IN_INV_Msk (0x01UL << GIMA_CTIN_7_IN_INV_Pos) /*!< GIMA CTIN_7_IN: INV Mask */ #define GIMA_CTIN_7_IN_EDGE_Pos 1 /*!< GIMA CTIN_7_IN: EDGE Position */ #define GIMA_CTIN_7_IN_EDGE_Msk (0x01UL << GIMA_CTIN_7_IN_EDGE_Pos) /*!< GIMA CTIN_7_IN: EDGE Mask */ #define GIMA_CTIN_7_IN_SYNCH_Pos 2 /*!< GIMA CTIN_7_IN: SYNCH Position */ #define GIMA_CTIN_7_IN_SYNCH_Msk (0x01UL << GIMA_CTIN_7_IN_SYNCH_Pos) /*!< GIMA CTIN_7_IN: SYNCH Mask */ #define GIMA_CTIN_7_IN_PULSE_Pos 3 /*!< GIMA CTIN_7_IN: PULSE Position */ #define GIMA_CTIN_7_IN_PULSE_Msk (0x01UL << GIMA_CTIN_7_IN_PULSE_Pos) /*!< GIMA CTIN_7_IN: PULSE Mask */ #define GIMA_CTIN_7_IN_SELECT_Pos 4 /*!< GIMA CTIN_7_IN: SELECT Position */ #define GIMA_CTIN_7_IN_SELECT_Msk (0x0fUL << GIMA_CTIN_7_IN_SELECT_Pos) /*!< GIMA CTIN_7_IN: SELECT Mask */ /* ---------------------------- GIMA_ADCHS_TRIGGER_IN --------------------------- */ #define GIMA_ADCHS_TRIGGER_IN_INV_Pos 0 /*!< GIMA ADCHS_TRIGGER_IN: INV Position */ #define GIMA_ADCHS_TRIGGER_IN_INV_Msk (0x01UL << GIMA_ADCHS_TRIGGER_IN_INV_Pos) /*!< GIMA ADCHS_TRIGGER_IN: INV Mask */ #define GIMA_ADCHS_TRIGGER_IN_EDGE_Pos 1 /*!< GIMA ADCHS_TRIGGER_IN: EDGE Position */ #define GIMA_ADCHS_TRIGGER_IN_EDGE_Msk (0x01UL << GIMA_ADCHS_TRIGGER_IN_EDGE_Pos) /*!< GIMA ADCHS_TRIGGER_IN: EDGE Mask */ #define GIMA_ADCHS_TRIGGER_IN_SYNCH_Pos 2 /*!< GIMA ADCHS_TRIGGER_IN: SYNCH Position */ #define GIMA_ADCHS_TRIGGER_IN_SYNCH_Msk (0x01UL << GIMA_ADCHS_TRIGGER_IN_SYNCH_Pos) /*!< GIMA ADCHS_TRIGGER_IN: SYNCH Mask */ #define GIMA_ADCHS_TRIGGER_IN_PULSE_Pos 3 /*!< GIMA ADCHS_TRIGGER_IN: PULSE Position */ #define GIMA_ADCHS_TRIGGER_IN_PULSE_Msk (0x01UL << GIMA_ADCHS_TRIGGER_IN_PULSE_Pos) /*!< GIMA ADCHS_TRIGGER_IN: PULSE Mask */ #define GIMA_ADCHS_TRIGGER_IN_SELECT_Pos 4 /*!< GIMA ADCHS_TRIGGER_IN: SELECT Position */ #define GIMA_ADCHS_TRIGGER_IN_SELECT_Msk (0x0fUL << GIMA_ADCHS_TRIGGER_IN_SELECT_Pos) /*!< GIMA ADCHS_TRIGGER_IN: SELECT Mask */ /* --------------------------- GIMA_EVENTROUTER_13_IN --------------------------- */ #define GIMA_EVENTROUTER_13_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_13_IN: INV Position */ #define GIMA_EVENTROUTER_13_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_INV_Pos) /*!< GIMA EVENTROUTER_13_IN: INV Mask */ #define GIMA_EVENTROUTER_13_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_13_IN: EDGE Position */ #define GIMA_EVENTROUTER_13_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_13_IN: EDGE Mask */ #define GIMA_EVENTROUTER_13_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_13_IN: SYNCH Position */ #define GIMA_EVENTROUTER_13_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_13_IN: SYNCH Mask */ #define GIMA_EVENTROUTER_13_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_13_IN: PULSE Position */ #define GIMA_EVENTROUTER_13_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_13_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_13_IN: PULSE Mask */ #define GIMA_EVENTROUTER_13_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_13_IN: SELECT Position */ #define GIMA_EVENTROUTER_13_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_13_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_13_IN: SELECT Mask */ /* --------------------------- GIMA_EVENTROUTER_14_IN --------------------------- */ #define GIMA_EVENTROUTER_14_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_14_IN: INV Position */ #define GIMA_EVENTROUTER_14_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_INV_Pos) /*!< GIMA EVENTROUTER_14_IN: INV Mask */ #define GIMA_EVENTROUTER_14_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_14_IN: EDGE Position */ #define GIMA_EVENTROUTER_14_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_14_IN: EDGE Mask */ #define GIMA_EVENTROUTER_14_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_14_IN: SYNCH Position */ #define GIMA_EVENTROUTER_14_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_14_IN: SYNCH Mask */ #define GIMA_EVENTROUTER_14_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_14_IN: PULSE Position */ #define GIMA_EVENTROUTER_14_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_14_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_14_IN: PULSE Mask */ #define GIMA_EVENTROUTER_14_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_14_IN: SELECT Position */ #define GIMA_EVENTROUTER_14_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_14_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_14_IN: SELECT Mask */ /* --------------------------- GIMA_EVENTROUTER_16_IN --------------------------- */ #define GIMA_EVENTROUTER_16_IN_INV_Pos 0 /*!< GIMA EVENTROUTER_16_IN: INV Position */ #define GIMA_EVENTROUTER_16_IN_INV_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_INV_Pos) /*!< GIMA EVENTROUTER_16_IN: INV Mask */ #define GIMA_EVENTROUTER_16_IN_EDGE_Pos 1 /*!< GIMA EVENTROUTER_16_IN: EDGE Position */ #define GIMA_EVENTROUTER_16_IN_EDGE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_EDGE_Pos) /*!< GIMA EVENTROUTER_16_IN: EDGE Mask */ #define GIMA_EVENTROUTER_16_IN_SYNCH_Pos 2 /*!< GIMA EVENTROUTER_16_IN: SYNCH Position */ #define GIMA_EVENTROUTER_16_IN_SYNCH_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_SYNCH_Pos) /*!< GIMA EVENTROUTER_16_IN: SYNCH Mask */ #define GIMA_EVENTROUTER_16_IN_PULSE_Pos 3 /*!< GIMA EVENTROUTER_16_IN: PULSE Position */ #define GIMA_EVENTROUTER_16_IN_PULSE_Msk (0x01UL << GIMA_EVENTROUTER_16_IN_PULSE_Pos) /*!< GIMA EVENTROUTER_16_IN: PULSE Mask */ #define GIMA_EVENTROUTER_16_IN_SELECT_Pos 4 /*!< GIMA EVENTROUTER_16_IN: SELECT Position */ #define GIMA_EVENTROUTER_16_IN_SELECT_Msk (0x0fUL << GIMA_EVENTROUTER_16_IN_SELECT_Pos) /*!< GIMA EVENTROUTER_16_IN: SELECT Mask */ /* ------------------------------ GIMA_ADCSTART0_IN ----------------------------- */ #define GIMA_ADCSTART0_IN_INV_Pos 0 /*!< GIMA ADCSTART0_IN: INV Position */ #define GIMA_ADCSTART0_IN_INV_Msk (0x01UL << GIMA_ADCSTART0_IN_INV_Pos) /*!< GIMA ADCSTART0_IN: INV Mask */ #define GIMA_ADCSTART0_IN_EDGE_Pos 1 /*!< GIMA ADCSTART0_IN: EDGE Position */ #define GIMA_ADCSTART0_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART0_IN_EDGE_Pos) /*!< GIMA ADCSTART0_IN: EDGE Mask */ #define GIMA_ADCSTART0_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART0_IN: SYNCH Position */ #define GIMA_ADCSTART0_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART0_IN_SYNCH_Pos) /*!< GIMA ADCSTART0_IN: SYNCH Mask */ #define GIMA_ADCSTART0_IN_PULSE_Pos 3 /*!< GIMA ADCSTART0_IN: PULSE Position */ #define GIMA_ADCSTART0_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART0_IN_PULSE_Pos) /*!< GIMA ADCSTART0_IN: PULSE Mask */ #define GIMA_ADCSTART0_IN_SELECT_Pos 4 /*!< GIMA ADCSTART0_IN: SELECT Position */ #define GIMA_ADCSTART0_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART0_IN_SELECT_Pos) /*!< GIMA ADCSTART0_IN: SELECT Mask */ /* ------------------------------ GIMA_ADCSTART1_IN ----------------------------- */ #define GIMA_ADCSTART1_IN_INV_Pos 0 /*!< GIMA ADCSTART1_IN: INV Position */ #define GIMA_ADCSTART1_IN_INV_Msk (0x01UL << GIMA_ADCSTART1_IN_INV_Pos) /*!< GIMA ADCSTART1_IN: INV Mask */ #define GIMA_ADCSTART1_IN_EDGE_Pos 1 /*!< GIMA ADCSTART1_IN: EDGE Position */ #define GIMA_ADCSTART1_IN_EDGE_Msk (0x01UL << GIMA_ADCSTART1_IN_EDGE_Pos) /*!< GIMA ADCSTART1_IN: EDGE Mask */ #define GIMA_ADCSTART1_IN_SYNCH_Pos 2 /*!< GIMA ADCSTART1_IN: SYNCH Position */ #define GIMA_ADCSTART1_IN_SYNCH_Msk (0x01UL << GIMA_ADCSTART1_IN_SYNCH_Pos) /*!< GIMA ADCSTART1_IN: SYNCH Mask */ #define GIMA_ADCSTART1_IN_PULSE_Pos 3 /*!< GIMA ADCSTART1_IN: PULSE Position */ #define GIMA_ADCSTART1_IN_PULSE_Msk (0x01UL << GIMA_ADCSTART1_IN_PULSE_Pos) /*!< GIMA ADCSTART1_IN: PULSE Mask */ #define GIMA_ADCSTART1_IN_SELECT_Pos 4 /*!< GIMA ADCSTART1_IN: SELECT Position */ #define GIMA_ADCSTART1_IN_SELECT_Msk (0x0fUL << GIMA_ADCSTART1_IN_SELECT_Pos) /*!< GIMA ADCSTART1_IN: SELECT Mask */ /* ================================================================================ */ /* ================ struct 'DAC' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- DAC_CR ----------------------------------- */ #define DAC_CR_VALUE_Pos 6 /*!< DAC CR: VALUE Position */ #define DAC_CR_VALUE_Msk (0x000003ffUL << DAC_CR_VALUE_Pos) /*!< DAC CR: VALUE Mask */ #define DAC_CR_BIAS_Pos 16 /*!< DAC CR: BIAS Position */ #define DAC_CR_BIAS_Msk (0x01UL << DAC_CR_BIAS_Pos) /*!< DAC CR: BIAS Mask */ /* ---------------------------------- DAC_CTRL ---------------------------------- */ #define DAC_CTRL_INT_DMA_REQ_Pos 0 /*!< DAC CTRL: INT_DMA_REQ Position */ #define DAC_CTRL_INT_DMA_REQ_Msk (0x01UL << DAC_CTRL_INT_DMA_REQ_Pos) /*!< DAC CTRL: INT_DMA_REQ Mask */ #define DAC_CTRL_DBLBUF_ENA_Pos 1 /*!< DAC CTRL: DBLBUF_ENA Position */ #define DAC_CTRL_DBLBUF_ENA_Msk (0x01UL << DAC_CTRL_DBLBUF_ENA_Pos) /*!< DAC CTRL: DBLBUF_ENA Mask */ #define DAC_CTRL_CNT_ENA_Pos 2 /*!< DAC CTRL: CNT_ENA Position */ #define DAC_CTRL_CNT_ENA_Msk (0x01UL << DAC_CTRL_CNT_ENA_Pos) /*!< DAC CTRL: CNT_ENA Mask */ #define DAC_CTRL_DMA_ENA_Pos 3 /*!< DAC CTRL: DMA_ENA Position */ #define DAC_CTRL_DMA_ENA_Msk (0x01UL << DAC_CTRL_DMA_ENA_Pos) /*!< DAC CTRL: DMA_ENA Mask */ /* --------------------------------- DAC_CNTVAL --------------------------------- */ #define DAC_CNTVAL_VALUE_Pos 0 /*!< DAC CNTVAL: VALUE Position */ #define DAC_CNTVAL_VALUE_Msk (0x0000ffffUL << DAC_CNTVAL_VALUE_Pos) /*!< DAC CNTVAL: VALUE Mask */ /* ================================================================================ */ /* ================ struct 'C_CAN0' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- C_CAN0_CNTL -------------------------------- */ #define C_CAN0_CNTL_INIT_Pos 0 /*!< C_CAN0 CNTL: INIT Position */ #define C_CAN0_CNTL_INIT_Msk (0x01UL << C_CAN0_CNTL_INIT_Pos) /*!< C_CAN0 CNTL: INIT Mask */ #define C_CAN0_CNTL_IE_Pos 1 /*!< C_CAN0 CNTL: IE Position */ #define C_CAN0_CNTL_IE_Msk (0x01UL << C_CAN0_CNTL_IE_Pos) /*!< C_CAN0 CNTL: IE Mask */ #define C_CAN0_CNTL_SIE_Pos 2 /*!< C_CAN0 CNTL: SIE Position */ #define C_CAN0_CNTL_SIE_Msk (0x01UL << C_CAN0_CNTL_SIE_Pos) /*!< C_CAN0 CNTL: SIE Mask */ #define C_CAN0_CNTL_EIE_Pos 3 /*!< C_CAN0 CNTL: EIE Position */ #define C_CAN0_CNTL_EIE_Msk (0x01UL << C_CAN0_CNTL_EIE_Pos) /*!< C_CAN0 CNTL: EIE Mask */ #define C_CAN0_CNTL_DAR_Pos 5 /*!< C_CAN0 CNTL: DAR Position */ #define C_CAN0_CNTL_DAR_Msk (0x01UL << C_CAN0_CNTL_DAR_Pos) /*!< C_CAN0 CNTL: DAR Mask */ #define C_CAN0_CNTL_CCE_Pos 6 /*!< C_CAN0 CNTL: CCE Position */ #define C_CAN0_CNTL_CCE_Msk (0x01UL << C_CAN0_CNTL_CCE_Pos) /*!< C_CAN0 CNTL: CCE Mask */ #define C_CAN0_CNTL_TEST_Pos 7 /*!< C_CAN0 CNTL: TEST Position */ #define C_CAN0_CNTL_TEST_Msk (0x01UL << C_CAN0_CNTL_TEST_Pos) /*!< C_CAN0 CNTL: TEST Mask */ /* --------------------------------- C_CAN0_STAT -------------------------------- */ #define C_CAN0_STAT_LEC_Pos 0 /*!< C_CAN0 STAT: LEC Position */ #define C_CAN0_STAT_LEC_Msk (0x07UL << C_CAN0_STAT_LEC_Pos) /*!< C_CAN0 STAT: LEC Mask */ #define C_CAN0_STAT_TXOK_Pos 3 /*!< C_CAN0 STAT: TXOK Position */ #define C_CAN0_STAT_TXOK_Msk (0x01UL << C_CAN0_STAT_TXOK_Pos) /*!< C_CAN0 STAT: TXOK Mask */ #define C_CAN0_STAT_RXOK_Pos 4 /*!< C_CAN0 STAT: RXOK Position */ #define C_CAN0_STAT_RXOK_Msk (0x01UL << C_CAN0_STAT_RXOK_Pos) /*!< C_CAN0 STAT: RXOK Mask */ #define C_CAN0_STAT_EPASS_Pos 5 /*!< C_CAN0 STAT: EPASS Position */ #define C_CAN0_STAT_EPASS_Msk (0x01UL << C_CAN0_STAT_EPASS_Pos) /*!< C_CAN0 STAT: EPASS Mask */ #define C_CAN0_STAT_EWARN_Pos 6 /*!< C_CAN0 STAT: EWARN Position */ #define C_CAN0_STAT_EWARN_Msk (0x01UL << C_CAN0_STAT_EWARN_Pos) /*!< C_CAN0 STAT: EWARN Mask */ #define C_CAN0_STAT_BOFF_Pos 7 /*!< C_CAN0 STAT: BOFF Position */ #define C_CAN0_STAT_BOFF_Msk (0x01UL << C_CAN0_STAT_BOFF_Pos) /*!< C_CAN0 STAT: BOFF Mask */ /* ---------------------------------- C_CAN0_EC --------------------------------- */ #define C_CAN0_EC_TEC_7_0_Pos 0 /*!< C_CAN0 EC: TEC_7_0 Position */ #define C_CAN0_EC_TEC_7_0_Msk (0x000000ffUL << C_CAN0_EC_TEC_7_0_Pos) /*!< C_CAN0 EC: TEC_7_0 Mask */ #define C_CAN0_EC_REC_6_0_Pos 8 /*!< C_CAN0 EC: REC_6_0 Position */ #define C_CAN0_EC_REC_6_0_Msk (0x7fUL << C_CAN0_EC_REC_6_0_Pos) /*!< C_CAN0 EC: REC_6_0 Mask */ #define C_CAN0_EC_RP_Pos 15 /*!< C_CAN0 EC: RP Position */ #define C_CAN0_EC_RP_Msk (0x01UL << C_CAN0_EC_RP_Pos) /*!< C_CAN0 EC: RP Mask */ /* ---------------------------------- C_CAN0_BT --------------------------------- */ #define C_CAN0_BT_BRP_Pos 0 /*!< C_CAN0 BT: BRP Position */ #define C_CAN0_BT_BRP_Msk (0x3fUL << C_CAN0_BT_BRP_Pos) /*!< C_CAN0 BT: BRP Mask */ #define C_CAN0_BT_SJW_Pos 6 /*!< C_CAN0 BT: SJW Position */ #define C_CAN0_BT_SJW_Msk (0x03UL << C_CAN0_BT_SJW_Pos) /*!< C_CAN0 BT: SJW Mask */ #define C_CAN0_BT_TSEG1_Pos 8 /*!< C_CAN0 BT: TSEG1 Position */ #define C_CAN0_BT_TSEG1_Msk (0x0fUL << C_CAN0_BT_TSEG1_Pos) /*!< C_CAN0 BT: TSEG1 Mask */ #define C_CAN0_BT_TSEG2_Pos 12 /*!< C_CAN0 BT: TSEG2 Position */ #define C_CAN0_BT_TSEG2_Msk (0x07UL << C_CAN0_BT_TSEG2_Pos) /*!< C_CAN0 BT: TSEG2 Mask */ /* --------------------------------- C_CAN0_INT --------------------------------- */ #define C_CAN0_INT_INTID15_0_Pos 0 /*!< C_CAN0 INT: INTID15_0 Position */ #define C_CAN0_INT_INTID15_0_Msk (0x0000ffffUL << C_CAN0_INT_INTID15_0_Pos) /*!< C_CAN0 INT: INTID15_0 Mask */ /* --------------------------------- C_CAN0_TEST -------------------------------- */ #define C_CAN0_TEST_BASIC_Pos 2 /*!< C_CAN0 TEST: BASIC Position */ #define C_CAN0_TEST_BASIC_Msk (0x01UL << C_CAN0_TEST_BASIC_Pos) /*!< C_CAN0 TEST: BASIC Mask */ #define C_CAN0_TEST_SILENT_Pos 3 /*!< C_CAN0 TEST: SILENT Position */ #define C_CAN0_TEST_SILENT_Msk (0x01UL << C_CAN0_TEST_SILENT_Pos) /*!< C_CAN0 TEST: SILENT Mask */ #define C_CAN0_TEST_LBACK_Pos 4 /*!< C_CAN0 TEST: LBACK Position */ #define C_CAN0_TEST_LBACK_Msk (0x01UL << C_CAN0_TEST_LBACK_Pos) /*!< C_CAN0 TEST: LBACK Mask */ #define C_CAN0_TEST_TX1_0_Pos 5 /*!< C_CAN0 TEST: TX1_0 Position */ #define C_CAN0_TEST_TX1_0_Msk (0x03UL << C_CAN0_TEST_TX1_0_Pos) /*!< C_CAN0 TEST: TX1_0 Mask */ #define C_CAN0_TEST_RX_Pos 7 /*!< C_CAN0 TEST: RX Position */ #define C_CAN0_TEST_RX_Msk (0x01UL << C_CAN0_TEST_RX_Pos) /*!< C_CAN0 TEST: RX Mask */ /* --------------------------------- C_CAN0_BRPE -------------------------------- */ #define C_CAN0_BRPE_BRPE_Pos 0 /*!< C_CAN0 BRPE: BRPE Position */ #define C_CAN0_BRPE_BRPE_Msk (0x0fUL << C_CAN0_BRPE_BRPE_Pos) /*!< C_CAN0 BRPE: BRPE Mask */ /* ------------------------------ C_CAN0_IF1_CMDREQ ----------------------------- */ #define C_CAN0_IF1_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF1_CMDREQ: MESSNUM Position */ #define C_CAN0_IF1_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF1_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF1_CMDREQ: MESSNUM Mask */ #define C_CAN0_IF1_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF1_CMDREQ: BUSY Position */ #define C_CAN0_IF1_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF1_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF1_CMDREQ: BUSY Mask */ /* ----------------------------- C_CAN0_IF1_CMDMSK_R ---------------------------- */ #define C_CAN0_IF1_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Position */ #define C_CAN0_IF1_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_B Mask */ #define C_CAN0_IF1_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Position */ #define C_CAN0_IF1_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_R: DATA_A Mask */ #define C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Position */ #define C_CAN0_IF1_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF1_CMDMSK_R: NEWDAT Mask */ #define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Position */ #define C_CAN0_IF1_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CLRINTPND Mask */ #define C_CAN0_IF1_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_R: CTRL Position */ #define C_CAN0_IF1_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_R: CTRL Mask */ #define C_CAN0_IF1_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_R: ARB Position */ #define C_CAN0_IF1_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_R: ARB Mask */ #define C_CAN0_IF1_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_R: MASK Position */ #define C_CAN0_IF1_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_R: MASK Mask */ #define C_CAN0_IF1_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Position */ #define C_CAN0_IF1_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_R: WR_RD Mask */ /* ----------------------------- C_CAN0_IF1_CMDMSK_W ---------------------------- */ #define C_CAN0_IF1_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Position */ #define C_CAN0_IF1_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_B Mask */ #define C_CAN0_IF1_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Position */ #define C_CAN0_IF1_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF1_CMDMSK_W: DATA_A Mask */ #define C_CAN0_IF1_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Position */ #define C_CAN0_IF1_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF1_CMDMSK_W: TXRQST Mask */ #define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Position */ #define C_CAN0_IF1_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CLRINTPND Mask */ #define C_CAN0_IF1_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF1_CMDMSK_W: CTRL Position */ #define C_CAN0_IF1_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF1_CMDMSK_W: CTRL Mask */ #define C_CAN0_IF1_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF1_CMDMSK_W: ARB Position */ #define C_CAN0_IF1_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF1_CMDMSK_W: ARB Mask */ #define C_CAN0_IF1_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF1_CMDMSK_W: MASK Position */ #define C_CAN0_IF1_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF1_CMDMSK_W: MASK Mask */ #define C_CAN0_IF1_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Position */ #define C_CAN0_IF1_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF1_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF1_CMDMSK_W: WR_RD Mask */ /* ------------------------------- C_CAN0_IF1_MSK1 ------------------------------ */ #define C_CAN0_IF1_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF1_MSK1: MSK15_0 Position */ #define C_CAN0_IF1_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF1_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF1_MSK1: MSK15_0 Mask */ /* ------------------------------- C_CAN0_IF1_MSK2 ------------------------------ */ #define C_CAN0_IF1_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF1_MSK2: MSK28_16 Position */ #define C_CAN0_IF1_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF1_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF1_MSK2: MSK28_16 Mask */ #define C_CAN0_IF1_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF1_MSK2: MDIR Position */ #define C_CAN0_IF1_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF1_MSK2_MDIR_Pos) /*!< C_CAN0 IF1_MSK2: MDIR Mask */ #define C_CAN0_IF1_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF1_MSK2: MXTD Position */ #define C_CAN0_IF1_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF1_MSK2_MXTD_Pos) /*!< C_CAN0 IF1_MSK2: MXTD Mask */ /* ------------------------------- C_CAN0_IF1_ARB1 ------------------------------ */ #define C_CAN0_IF1_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF1_ARB1: ID15_0 Position */ #define C_CAN0_IF1_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF1_ARB1_ID15_0_Pos) /*!< C_CAN0 IF1_ARB1: ID15_0 Mask */ /* ------------------------------- C_CAN0_IF1_ARB2 ------------------------------ */ #define C_CAN0_IF1_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF1_ARB2: ID28_16 Position */ #define C_CAN0_IF1_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF1_ARB2_ID28_16_Pos) /*!< C_CAN0 IF1_ARB2: ID28_16 Mask */ #define C_CAN0_IF1_ARB2_DIR_Pos 13 /*!< C_CAN0 IF1_ARB2: DIR Position */ #define C_CAN0_IF1_ARB2_DIR_Msk (0x01UL << C_CAN0_IF1_ARB2_DIR_Pos) /*!< C_CAN0 IF1_ARB2: DIR Mask */ #define C_CAN0_IF1_ARB2_XTD_Pos 14 /*!< C_CAN0 IF1_ARB2: XTD Position */ #define C_CAN0_IF1_ARB2_XTD_Msk (0x01UL << C_CAN0_IF1_ARB2_XTD_Pos) /*!< C_CAN0 IF1_ARB2: XTD Mask */ #define C_CAN0_IF1_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF1_ARB2: MSGVAL Position */ #define C_CAN0_IF1_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF1_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF1_ARB2: MSGVAL Mask */ /* ------------------------------ C_CAN0_IF1_MCTRL ------------------------------ */ #define C_CAN0_IF1_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF1_MCTRL: DLC3_0 Position */ #define C_CAN0_IF1_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF1_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF1_MCTRL: DLC3_0 Mask */ #define C_CAN0_IF1_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF1_MCTRL: EOB Position */ #define C_CAN0_IF1_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF1_MCTRL_EOB_Pos) /*!< C_CAN0 IF1_MCTRL: EOB Mask */ #define C_CAN0_IF1_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF1_MCTRL: TXRQST Position */ #define C_CAN0_IF1_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF1_MCTRL: TXRQST Mask */ #define C_CAN0_IF1_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF1_MCTRL: RMTEN Position */ #define C_CAN0_IF1_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF1_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF1_MCTRL: RMTEN Mask */ #define C_CAN0_IF1_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF1_MCTRL: RXIE Position */ #define C_CAN0_IF1_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_RXIE_Pos) /*!< C_CAN0 IF1_MCTRL: RXIE Mask */ #define C_CAN0_IF1_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF1_MCTRL: TXIE Position */ #define C_CAN0_IF1_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF1_MCTRL_TXIE_Pos) /*!< C_CAN0 IF1_MCTRL: TXIE Mask */ #define C_CAN0_IF1_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF1_MCTRL: UMASK Position */ #define C_CAN0_IF1_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF1_MCTRL_UMASK_Pos) /*!< C_CAN0 IF1_MCTRL: UMASK Mask */ #define C_CAN0_IF1_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF1_MCTRL: INTPND Position */ #define C_CAN0_IF1_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF1_MCTRL_INTPND_Pos) /*!< C_CAN0 IF1_MCTRL: INTPND Mask */ #define C_CAN0_IF1_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF1_MCTRL: MSGLST Position */ #define C_CAN0_IF1_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF1_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF1_MCTRL: MSGLST Mask */ #define C_CAN0_IF1_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF1_MCTRL: NEWDAT Position */ #define C_CAN0_IF1_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF1_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF1_MCTRL: NEWDAT Mask */ /* ------------------------------- C_CAN0_IF1_DA1 ------------------------------- */ #define C_CAN0_IF1_DA1_DATA0_Pos 0 /*!< C_CAN0 IF1_DA1: DATA0 Position */ #define C_CAN0_IF1_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA0_Pos) /*!< C_CAN0 IF1_DA1: DATA0 Mask */ #define C_CAN0_IF1_DA1_DATA1_Pos 8 /*!< C_CAN0 IF1_DA1: DATA1 Position */ #define C_CAN0_IF1_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF1_DA1_DATA1_Pos) /*!< C_CAN0 IF1_DA1: DATA1 Mask */ /* ------------------------------- C_CAN0_IF1_DA2 ------------------------------- */ #define C_CAN0_IF1_DA2_DATA2_Pos 0 /*!< C_CAN0 IF1_DA2: DATA2 Position */ #define C_CAN0_IF1_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA2_Pos) /*!< C_CAN0 IF1_DA2: DATA2 Mask */ #define C_CAN0_IF1_DA2_DATA3_Pos 8 /*!< C_CAN0 IF1_DA2: DATA3 Position */ #define C_CAN0_IF1_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF1_DA2_DATA3_Pos) /*!< C_CAN0 IF1_DA2: DATA3 Mask */ /* ------------------------------- C_CAN0_IF1_DB1 ------------------------------- */ #define C_CAN0_IF1_DB1_DATA4_Pos 0 /*!< C_CAN0 IF1_DB1: DATA4 Position */ #define C_CAN0_IF1_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA4_Pos) /*!< C_CAN0 IF1_DB1: DATA4 Mask */ #define C_CAN0_IF1_DB1_DATA5_Pos 8 /*!< C_CAN0 IF1_DB1: DATA5 Position */ #define C_CAN0_IF1_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF1_DB1_DATA5_Pos) /*!< C_CAN0 IF1_DB1: DATA5 Mask */ /* ------------------------------- C_CAN0_IF1_DB2 ------------------------------- */ #define C_CAN0_IF1_DB2_DATA6_Pos 0 /*!< C_CAN0 IF1_DB2: DATA6 Position */ #define C_CAN0_IF1_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA6_Pos) /*!< C_CAN0 IF1_DB2: DATA6 Mask */ #define C_CAN0_IF1_DB2_DATA7_Pos 8 /*!< C_CAN0 IF1_DB2: DATA7 Position */ #define C_CAN0_IF1_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF1_DB2_DATA7_Pos) /*!< C_CAN0 IF1_DB2: DATA7 Mask */ /* ------------------------------ C_CAN0_IF2_CMDREQ ----------------------------- */ #define C_CAN0_IF2_CMDREQ_MESSNUM_Pos 0 /*!< C_CAN0 IF2_CMDREQ: MESSNUM Position */ #define C_CAN0_IF2_CMDREQ_MESSNUM_Msk (0x3fUL << C_CAN0_IF2_CMDREQ_MESSNUM_Pos) /*!< C_CAN0 IF2_CMDREQ: MESSNUM Mask */ #define C_CAN0_IF2_CMDREQ_BUSY_Pos 15 /*!< C_CAN0 IF2_CMDREQ: BUSY Position */ #define C_CAN0_IF2_CMDREQ_BUSY_Msk (0x01UL << C_CAN0_IF2_CMDREQ_BUSY_Pos) /*!< C_CAN0 IF2_CMDREQ: BUSY Mask */ /* ----------------------------- C_CAN0_IF2_CMDMSK_R ---------------------------- */ #define C_CAN0_IF2_CMDMSK_R_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Position */ #define C_CAN0_IF2_CMDMSK_R_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_B Mask */ #define C_CAN0_IF2_CMDMSK_R_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Position */ #define C_CAN0_IF2_CMDMSK_R_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_R: DATA_A Mask */ #define C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos 2 /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Position */ #define C_CAN0_IF2_CMDMSK_R_NEWDAT_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_NEWDAT_Pos) /*!< C_CAN0 IF2_CMDMSK_R: NEWDAT Mask */ #define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Position */ #define C_CAN0_IF2_CMDMSK_R_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CLRINTPND Mask */ #define C_CAN0_IF2_CMDMSK_R_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_R: CTRL Position */ #define C_CAN0_IF2_CMDMSK_R_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_R: CTRL Mask */ #define C_CAN0_IF2_CMDMSK_R_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_R: ARB Position */ #define C_CAN0_IF2_CMDMSK_R_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_R: ARB Mask */ #define C_CAN0_IF2_CMDMSK_R_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_R: MASK Position */ #define C_CAN0_IF2_CMDMSK_R_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_R: MASK Mask */ #define C_CAN0_IF2_CMDMSK_R_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Position */ #define C_CAN0_IF2_CMDMSK_R_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_R_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_R: WR_RD Mask */ /* ----------------------------- C_CAN0_IF2_CMDMSK_W ---------------------------- */ #define C_CAN0_IF2_CMDMSK_W_DATA_B_Pos 0 /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Position */ #define C_CAN0_IF2_CMDMSK_W_DATA_B_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_B_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_B Mask */ #define C_CAN0_IF2_CMDMSK_W_DATA_A_Pos 1 /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Position */ #define C_CAN0_IF2_CMDMSK_W_DATA_A_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_DATA_A_Pos) /*!< C_CAN0 IF2_CMDMSK_W: DATA_A Mask */ #define C_CAN0_IF2_CMDMSK_W_TXRQST_Pos 2 /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Position */ #define C_CAN0_IF2_CMDMSK_W_TXRQST_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_TXRQST_Pos) /*!< C_CAN0 IF2_CMDMSK_W: TXRQST Mask */ #define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos 3 /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Position */ #define C_CAN0_IF2_CMDMSK_W_CLRINTPND_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CLRINTPND_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CLRINTPND Mask */ #define C_CAN0_IF2_CMDMSK_W_CTRL_Pos 4 /*!< C_CAN0 IF2_CMDMSK_W: CTRL Position */ #define C_CAN0_IF2_CMDMSK_W_CTRL_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_CTRL_Pos) /*!< C_CAN0 IF2_CMDMSK_W: CTRL Mask */ #define C_CAN0_IF2_CMDMSK_W_ARB_Pos 5 /*!< C_CAN0 IF2_CMDMSK_W: ARB Position */ #define C_CAN0_IF2_CMDMSK_W_ARB_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_ARB_Pos) /*!< C_CAN0 IF2_CMDMSK_W: ARB Mask */ #define C_CAN0_IF2_CMDMSK_W_MASK_Pos 6 /*!< C_CAN0 IF2_CMDMSK_W: MASK Position */ #define C_CAN0_IF2_CMDMSK_W_MASK_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_MASK_Pos) /*!< C_CAN0 IF2_CMDMSK_W: MASK Mask */ #define C_CAN0_IF2_CMDMSK_W_WR_RD_Pos 7 /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Position */ #define C_CAN0_IF2_CMDMSK_W_WR_RD_Msk (0x01UL << C_CAN0_IF2_CMDMSK_W_WR_RD_Pos) /*!< C_CAN0 IF2_CMDMSK_W: WR_RD Mask */ /* ------------------------------- C_CAN0_IF2_MSK1 ------------------------------ */ #define C_CAN0_IF2_MSK1_MSK15_0_Pos 0 /*!< C_CAN0 IF2_MSK1: MSK15_0 Position */ #define C_CAN0_IF2_MSK1_MSK15_0_Msk (0x0000ffffUL << C_CAN0_IF2_MSK1_MSK15_0_Pos) /*!< C_CAN0 IF2_MSK1: MSK15_0 Mask */ /* ------------------------------- C_CAN0_IF2_MSK2 ------------------------------ */ #define C_CAN0_IF2_MSK2_MSK28_16_Pos 0 /*!< C_CAN0 IF2_MSK2: MSK28_16 Position */ #define C_CAN0_IF2_MSK2_MSK28_16_Msk (0x00001fffUL << C_CAN0_IF2_MSK2_MSK28_16_Pos) /*!< C_CAN0 IF2_MSK2: MSK28_16 Mask */ #define C_CAN0_IF2_MSK2_MDIR_Pos 14 /*!< C_CAN0 IF2_MSK2: MDIR Position */ #define C_CAN0_IF2_MSK2_MDIR_Msk (0x01UL << C_CAN0_IF2_MSK2_MDIR_Pos) /*!< C_CAN0 IF2_MSK2: MDIR Mask */ #define C_CAN0_IF2_MSK2_MXTD_Pos 15 /*!< C_CAN0 IF2_MSK2: MXTD Position */ #define C_CAN0_IF2_MSK2_MXTD_Msk (0x01UL << C_CAN0_IF2_MSK2_MXTD_Pos) /*!< C_CAN0 IF2_MSK2: MXTD Mask */ /* ------------------------------- C_CAN0_IF2_ARB1 ------------------------------ */ #define C_CAN0_IF2_ARB1_ID15_0_Pos 0 /*!< C_CAN0 IF2_ARB1: ID15_0 Position */ #define C_CAN0_IF2_ARB1_ID15_0_Msk (0x0000ffffUL << C_CAN0_IF2_ARB1_ID15_0_Pos) /*!< C_CAN0 IF2_ARB1: ID15_0 Mask */ /* ------------------------------- C_CAN0_IF2_ARB2 ------------------------------ */ #define C_CAN0_IF2_ARB2_ID28_16_Pos 0 /*!< C_CAN0 IF2_ARB2: ID28_16 Position */ #define C_CAN0_IF2_ARB2_ID28_16_Msk (0x00001fffUL << C_CAN0_IF2_ARB2_ID28_16_Pos) /*!< C_CAN0 IF2_ARB2: ID28_16 Mask */ #define C_CAN0_IF2_ARB2_DIR_Pos 13 /*!< C_CAN0 IF2_ARB2: DIR Position */ #define C_CAN0_IF2_ARB2_DIR_Msk (0x01UL << C_CAN0_IF2_ARB2_DIR_Pos) /*!< C_CAN0 IF2_ARB2: DIR Mask */ #define C_CAN0_IF2_ARB2_XTD_Pos 14 /*!< C_CAN0 IF2_ARB2: XTD Position */ #define C_CAN0_IF2_ARB2_XTD_Msk (0x01UL << C_CAN0_IF2_ARB2_XTD_Pos) /*!< C_CAN0 IF2_ARB2: XTD Mask */ #define C_CAN0_IF2_ARB2_MSGVAL_Pos 15 /*!< C_CAN0 IF2_ARB2: MSGVAL Position */ #define C_CAN0_IF2_ARB2_MSGVAL_Msk (0x01UL << C_CAN0_IF2_ARB2_MSGVAL_Pos) /*!< C_CAN0 IF2_ARB2: MSGVAL Mask */ /* ------------------------------ C_CAN0_IF2_MCTRL ------------------------------ */ #define C_CAN0_IF2_MCTRL_DLC3_0_Pos 0 /*!< C_CAN0 IF2_MCTRL: DLC3_0 Position */ #define C_CAN0_IF2_MCTRL_DLC3_0_Msk (0x0fUL << C_CAN0_IF2_MCTRL_DLC3_0_Pos) /*!< C_CAN0 IF2_MCTRL: DLC3_0 Mask */ #define C_CAN0_IF2_MCTRL_EOB_Pos 7 /*!< C_CAN0 IF2_MCTRL: EOB Position */ #define C_CAN0_IF2_MCTRL_EOB_Msk (0x01UL << C_CAN0_IF2_MCTRL_EOB_Pos) /*!< C_CAN0 IF2_MCTRL: EOB Mask */ #define C_CAN0_IF2_MCTRL_TXRQST_Pos 8 /*!< C_CAN0 IF2_MCTRL: TXRQST Position */ #define C_CAN0_IF2_MCTRL_TXRQST_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXRQST_Pos) /*!< C_CAN0 IF2_MCTRL: TXRQST Mask */ #define C_CAN0_IF2_MCTRL_RMTEN_Pos 9 /*!< C_CAN0 IF2_MCTRL: RMTEN Position */ #define C_CAN0_IF2_MCTRL_RMTEN_Msk (0x01UL << C_CAN0_IF2_MCTRL_RMTEN_Pos) /*!< C_CAN0 IF2_MCTRL: RMTEN Mask */ #define C_CAN0_IF2_MCTRL_RXIE_Pos 10 /*!< C_CAN0 IF2_MCTRL: RXIE Position */ #define C_CAN0_IF2_MCTRL_RXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_RXIE_Pos) /*!< C_CAN0 IF2_MCTRL: RXIE Mask */ #define C_CAN0_IF2_MCTRL_TXIE_Pos 11 /*!< C_CAN0 IF2_MCTRL: TXIE Position */ #define C_CAN0_IF2_MCTRL_TXIE_Msk (0x01UL << C_CAN0_IF2_MCTRL_TXIE_Pos) /*!< C_CAN0 IF2_MCTRL: TXIE Mask */ #define C_CAN0_IF2_MCTRL_UMASK_Pos 12 /*!< C_CAN0 IF2_MCTRL: UMASK Position */ #define C_CAN0_IF2_MCTRL_UMASK_Msk (0x01UL << C_CAN0_IF2_MCTRL_UMASK_Pos) /*!< C_CAN0 IF2_MCTRL: UMASK Mask */ #define C_CAN0_IF2_MCTRL_INTPND_Pos 13 /*!< C_CAN0 IF2_MCTRL: INTPND Position */ #define C_CAN0_IF2_MCTRL_INTPND_Msk (0x01UL << C_CAN0_IF2_MCTRL_INTPND_Pos) /*!< C_CAN0 IF2_MCTRL: INTPND Mask */ #define C_CAN0_IF2_MCTRL_MSGLST_Pos 14 /*!< C_CAN0 IF2_MCTRL: MSGLST Position */ #define C_CAN0_IF2_MCTRL_MSGLST_Msk (0x01UL << C_CAN0_IF2_MCTRL_MSGLST_Pos) /*!< C_CAN0 IF2_MCTRL: MSGLST Mask */ #define C_CAN0_IF2_MCTRL_NEWDAT_Pos 15 /*!< C_CAN0 IF2_MCTRL: NEWDAT Position */ #define C_CAN0_IF2_MCTRL_NEWDAT_Msk (0x01UL << C_CAN0_IF2_MCTRL_NEWDAT_Pos) /*!< C_CAN0 IF2_MCTRL: NEWDAT Mask */ /* ------------------------------- C_CAN0_IF2_DA1 ------------------------------- */ #define C_CAN0_IF2_DA1_DATA0_Pos 0 /*!< C_CAN0 IF2_DA1: DATA0 Position */ #define C_CAN0_IF2_DA1_DATA0_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA0_Pos) /*!< C_CAN0 IF2_DA1: DATA0 Mask */ #define C_CAN0_IF2_DA1_DATA1_Pos 8 /*!< C_CAN0 IF2_DA1: DATA1 Position */ #define C_CAN0_IF2_DA1_DATA1_Msk (0x000000ffUL << C_CAN0_IF2_DA1_DATA1_Pos) /*!< C_CAN0 IF2_DA1: DATA1 Mask */ /* ------------------------------- C_CAN0_IF2_DA2 ------------------------------- */ #define C_CAN0_IF2_DA2_DATA2_Pos 0 /*!< C_CAN0 IF2_DA2: DATA2 Position */ #define C_CAN0_IF2_DA2_DATA2_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA2_Pos) /*!< C_CAN0 IF2_DA2: DATA2 Mask */ #define C_CAN0_IF2_DA2_DATA3_Pos 8 /*!< C_CAN0 IF2_DA2: DATA3 Position */ #define C_CAN0_IF2_DA2_DATA3_Msk (0x000000ffUL << C_CAN0_IF2_DA2_DATA3_Pos) /*!< C_CAN0 IF2_DA2: DATA3 Mask */ /* ------------------------------- C_CAN0_IF2_DB1 ------------------------------- */ #define C_CAN0_IF2_DB1_DATA4_Pos 0 /*!< C_CAN0 IF2_DB1: DATA4 Position */ #define C_CAN0_IF2_DB1_DATA4_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA4_Pos) /*!< C_CAN0 IF2_DB1: DATA4 Mask */ #define C_CAN0_IF2_DB1_DATA5_Pos 8 /*!< C_CAN0 IF2_DB1: DATA5 Position */ #define C_CAN0_IF2_DB1_DATA5_Msk (0x000000ffUL << C_CAN0_IF2_DB1_DATA5_Pos) /*!< C_CAN0 IF2_DB1: DATA5 Mask */ /* ------------------------------- C_CAN0_IF2_DB2 ------------------------------- */ #define C_CAN0_IF2_DB2_DATA6_Pos 0 /*!< C_CAN0 IF2_DB2: DATA6 Position */ #define C_CAN0_IF2_DB2_DATA6_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA6_Pos) /*!< C_CAN0 IF2_DB2: DATA6 Mask */ #define C_CAN0_IF2_DB2_DATA7_Pos 8 /*!< C_CAN0 IF2_DB2: DATA7 Position */ #define C_CAN0_IF2_DB2_DATA7_Msk (0x000000ffUL << C_CAN0_IF2_DB2_DATA7_Pos) /*!< C_CAN0 IF2_DB2: DATA7 Mask */ /* -------------------------------- C_CAN0_TXREQ1 ------------------------------- */ #define C_CAN0_TXREQ1_TXRQST16_1_Pos 0 /*!< C_CAN0 TXREQ1: TXRQST16_1 Position */ #define C_CAN0_TXREQ1_TXRQST16_1_Msk (0x0000ffffUL << C_CAN0_TXREQ1_TXRQST16_1_Pos) /*!< C_CAN0 TXREQ1: TXRQST16_1 Mask */ /* -------------------------------- C_CAN0_TXREQ2 ------------------------------- */ #define C_CAN0_TXREQ2_TXRQST32_17_Pos 0 /*!< C_CAN0 TXREQ2: TXRQST32_17 Position */ #define C_CAN0_TXREQ2_TXRQST32_17_Msk (0x0000ffffUL << C_CAN0_TXREQ2_TXRQST32_17_Pos) /*!< C_CAN0 TXREQ2: TXRQST32_17 Mask */ /* --------------------------------- C_CAN0_ND1 --------------------------------- */ #define C_CAN0_ND1_NEWDAT16_1_Pos 0 /*!< C_CAN0 ND1: NEWDAT16_1 Position */ #define C_CAN0_ND1_NEWDAT16_1_Msk (0x0000ffffUL << C_CAN0_ND1_NEWDAT16_1_Pos) /*!< C_CAN0 ND1: NEWDAT16_1 Mask */ /* --------------------------------- C_CAN0_ND2 --------------------------------- */ #define C_CAN0_ND2_NEWDAT32_17_Pos 0 /*!< C_CAN0 ND2: NEWDAT32_17 Position */ #define C_CAN0_ND2_NEWDAT32_17_Msk (0x0000ffffUL << C_CAN0_ND2_NEWDAT32_17_Pos) /*!< C_CAN0 ND2: NEWDAT32_17 Mask */ /* --------------------------------- C_CAN0_IR1 --------------------------------- */ #define C_CAN0_IR1_INTPND16_1_Pos 0 /*!< C_CAN0 IR1: INTPND16_1 Position */ #define C_CAN0_IR1_INTPND16_1_Msk (0x0000ffffUL << C_CAN0_IR1_INTPND16_1_Pos) /*!< C_CAN0 IR1: INTPND16_1 Mask */ /* --------------------------------- C_CAN0_IR2 --------------------------------- */ #define C_CAN0_IR2_INTPND32_17_Pos 0 /*!< C_CAN0 IR2: INTPND32_17 Position */ #define C_CAN0_IR2_INTPND32_17_Msk (0x0000ffffUL << C_CAN0_IR2_INTPND32_17_Pos) /*!< C_CAN0 IR2: INTPND32_17 Mask */ /* -------------------------------- C_CAN0_MSGV1 -------------------------------- */ #define C_CAN0_MSGV1_MSGVAL16_1_Pos 0 /*!< C_CAN0 MSGV1: MSGVAL16_1 Position */ #define C_CAN0_MSGV1_MSGVAL16_1_Msk (0x0000ffffUL << C_CAN0_MSGV1_MSGVAL16_1_Pos) /*!< C_CAN0 MSGV1: MSGVAL16_1 Mask */ /* -------------------------------- C_CAN0_MSGV2 -------------------------------- */ #define C_CAN0_MSGV2_MSGVAL32_17_Pos 0 /*!< C_CAN0 MSGV2: MSGVAL32_17 Position */ #define C_CAN0_MSGV2_MSGVAL32_17_Msk (0x0000ffffUL << C_CAN0_MSGV2_MSGVAL32_17_Pos) /*!< C_CAN0 MSGV2: MSGVAL32_17 Mask */ /* -------------------------------- C_CAN0_CLKDIV ------------------------------- */ #define C_CAN0_CLKDIV_CLKDIVVAL_Pos 0 /*!< C_CAN0 CLKDIV: CLKDIVVAL Position */ #define C_CAN0_CLKDIV_CLKDIVVAL_Msk (0x0fUL << C_CAN0_CLKDIV_CLKDIVVAL_Pos) /*!< C_CAN0 CLKDIV: CLKDIVVAL Mask */ /* ================================================================================ */ /* ================ Group 'ADCn' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- ADCn_CR ---------------------------------- */ #define ADCn_CR_SEL_Pos 0 /*!< ADCn CR: SEL Position */ #define ADCn_CR_SEL_Msk (0x000000ffUL << ADCn_CR_SEL_Pos) /*!< ADCn CR: SEL Mask */ #define ADCn_CR_CLKDIV_Pos 8 /*!< ADCn CR: CLKDIV Position */ #define ADCn_CR_CLKDIV_Msk (0x000000ffUL << ADCn_CR_CLKDIV_Pos) /*!< ADCn CR: CLKDIV Mask */ #define ADCn_CR_BURST_Pos 16 /*!< ADCn CR: BURST Position */ #define ADCn_CR_BURST_Msk (0x01UL << ADCn_CR_BURST_Pos) /*!< ADCn CR: BURST Mask */ #define ADCn_CR_CLKS_Pos 17 /*!< ADCn CR: CLKS Position */ #define ADCn_CR_CLKS_Msk (0x07UL << ADCn_CR_CLKS_Pos) /*!< ADCn CR: CLKS Mask */ #define ADCn_CR_PDN_Pos 21 /*!< ADCn CR: PDN Position */ #define ADCn_CR_PDN_Msk (0x01UL << ADCn_CR_PDN_Pos) /*!< ADCn CR: PDN Mask */ #define ADCn_CR_START_Pos 24 /*!< ADCn CR: START Position */ #define ADCn_CR_START_Msk (0x07UL << ADCn_CR_START_Pos) /*!< ADCn CR: START Mask */ #define ADCn_CR_EDGE_Pos 27 /*!< ADCn CR: EDGE Position */ #define ADCn_CR_EDGE_Msk (0x01UL << ADCn_CR_EDGE_Pos) /*!< ADCn CR: EDGE Mask */ /* ---------------------------------- ADCn_GDR ---------------------------------- */ #define ADCn_GDR_V_VREF_Pos 6 /*!< ADCn GDR: V_VREF Position */ #define ADCn_GDR_V_VREF_Msk (0x000003ffUL << ADCn_GDR_V_VREF_Pos) /*!< ADCn GDR: V_VREF Mask */ #define ADCn_GDR_CHN_Pos 24 /*!< ADCn GDR: CHN Position */ #define ADCn_GDR_CHN_Msk (0x07UL << ADCn_GDR_CHN_Pos) /*!< ADCn GDR: CHN Mask */ #define ADCn_GDR_OVERRUN_Pos 30 /*!< ADCn GDR: OVERRUN Position */ #define ADCn_GDR_OVERRUN_Msk (0x01UL << ADCn_GDR_OVERRUN_Pos) /*!< ADCn GDR: OVERRUN Mask */ #define ADCn_GDR_DONE_Pos 31 /*!< ADCn GDR: DONE Position */ #define ADCn_GDR_DONE_Msk (0x01UL << ADCn_GDR_DONE_Pos) /*!< ADCn GDR: DONE Mask */ /* --------------------------------- ADCn_INTEN --------------------------------- */ #define ADCn_INTEN_ADINTEN_Pos 0 /*!< ADCn INTEN: ADINTEN Position */ #define ADCn_INTEN_ADINTEN_Msk (0x000000ffUL << ADCn_INTEN_ADINTEN_Pos) /*!< ADCn INTEN: ADINTEN Mask */ #define ADCn_INTEN_ADGINTEN_Pos 8 /*!< ADCn INTEN: ADGINTEN Position */ #define ADCn_INTEN_ADGINTEN_Msk (0x01UL << ADCn_INTEN_ADGINTEN_Pos) /*!< ADCn INTEN: ADGINTEN Mask */ /* ----------------------------------- ADCn_DR ---------------------------------- */ #define ADCn_DR_V_VREF_Pos 6 /*!< ADCn DR: V_VREF Position */ #define ADCn_DR_V_VREF_Msk (0x000003ffUL << ADCn_DR_V_VREF_Pos) /*!< ADCn DR: V_VREF Mask */ #define ADCn_DR_OVERRUN_Pos 30 /*!< ADCn DR: OVERRUN Position */ #define ADCn_DR_OVERRUN_Msk (0x01UL << ADCn_DR_OVERRUN_Pos) /*!< ADCn DR: OVERRUN Mask */ #define ADCn_DR_DONE_Pos 31 /*!< ADCn DR: DONE Position */ #define ADCn_DR_DONE_Msk (0x01UL << ADCn_DR_DONE_Pos) /*!< ADCn DR: DONE Mask */ /* ---------------------------------- ADCn_STAT --------------------------------- */ #define ADCn_STAT_DONE_Pos 0 /*!< ADCn STAT: DONE Position */ #define ADCn_STAT_DONE_Msk (0x000000ffUL << ADCn_STAT_DONE_Pos) /*!< ADCn STAT: DONE Mask */ #define ADCn_STAT_OVERUN_Pos 8 /*!< ADCn STAT: OVERUN Position */ #define ADCn_STAT_OVERUN_Msk (0x000000ffUL << ADCn_STAT_OVERUN_Pos) /*!< ADCn STAT: OVERUN Mask */ #define ADCn_STAT_ADINT_Pos 16 /*!< ADCn STAT: ADINT Position */ #define ADCn_STAT_ADINT_Msk (0x01UL << ADCn_STAT_ADINT_Pos) /*!< ADCn STAT: ADINT Mask */ /* ================================================================================ */ /* ================ struct 'ADC0' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- ADC0_CR ---------------------------------- */ #define ADC0_CR_SEL_Pos 0 /*!< ADC0 CR: SEL Position */ #define ADC0_CR_SEL_Msk (0x000000ffUL << ADC0_CR_SEL_Pos) /*!< ADC0 CR: SEL Mask */ #define ADC0_CR_CLKDIV_Pos 8 /*!< ADC0 CR: CLKDIV Position */ #define ADC0_CR_CLKDIV_Msk (0x000000ffUL << ADC0_CR_CLKDIV_Pos) /*!< ADC0 CR: CLKDIV Mask */ #define ADC0_CR_BURST_Pos 16 /*!< ADC0 CR: BURST Position */ #define ADC0_CR_BURST_Msk (0x01UL << ADC0_CR_BURST_Pos) /*!< ADC0 CR: BURST Mask */ #define ADC0_CR_CLKS_Pos 17 /*!< ADC0 CR: CLKS Position */ #define ADC0_CR_CLKS_Msk (0x07UL << ADC0_CR_CLKS_Pos) /*!< ADC0 CR: CLKS Mask */ #define ADC0_CR_PDN_Pos 21 /*!< ADC0 CR: PDN Position */ #define ADC0_CR_PDN_Msk (0x01UL << ADC0_CR_PDN_Pos) /*!< ADC0 CR: PDN Mask */ #define ADC0_CR_START_Pos 24 /*!< ADC0 CR: START Position */ #define ADC0_CR_START_Msk (0x07UL << ADC0_CR_START_Pos) /*!< ADC0 CR: START Mask */ #define ADC0_CR_EDGE_Pos 27 /*!< ADC0 CR: EDGE Position */ #define ADC0_CR_EDGE_Msk (0x01UL << ADC0_CR_EDGE_Pos) /*!< ADC0 CR: EDGE Mask */ /* ---------------------------------- ADC0_GDR ---------------------------------- */ #define ADC0_GDR_V_VREF_Pos 6 /*!< ADC0 GDR: V_VREF Position */ #define ADC0_GDR_V_VREF_Msk (0x000003ffUL << ADC0_GDR_V_VREF_Pos) /*!< ADC0 GDR: V_VREF Mask */ #define ADC0_GDR_CHN_Pos 24 /*!< ADC0 GDR: CHN Position */ #define ADC0_GDR_CHN_Msk (0x07UL << ADC0_GDR_CHN_Pos) /*!< ADC0 GDR: CHN Mask */ #define ADC0_GDR_OVERRUN_Pos 30 /*!< ADC0 GDR: OVERRUN Position */ #define ADC0_GDR_OVERRUN_Msk (0x01UL << ADC0_GDR_OVERRUN_Pos) /*!< ADC0 GDR: OVERRUN Mask */ #define ADC0_GDR_DONE_Pos 31 /*!< ADC0 GDR: DONE Position */ #define ADC0_GDR_DONE_Msk (0x01UL << ADC0_GDR_DONE_Pos) /*!< ADC0 GDR: DONE Mask */ /* --------------------------------- ADC0_INTEN --------------------------------- */ #define ADC0_INTEN_ADINTEN_Pos 0 /*!< ADC0 INTEN: ADINTEN Position */ #define ADC0_INTEN_ADINTEN_Msk (0x000000ffUL << ADC0_INTEN_ADINTEN_Pos) /*!< ADC0 INTEN: ADINTEN Mask */ #define ADC0_INTEN_ADGINTEN_Pos 8 /*!< ADC0 INTEN: ADGINTEN Position */ #define ADC0_INTEN_ADGINTEN_Msk (0x01UL << ADC0_INTEN_ADGINTEN_Pos) /*!< ADC0 INTEN: ADGINTEN Mask */ /* ----------------------------------- ADC0_DR ---------------------------------- */ #define ADC0_DR_V_VREF_Pos 6 /*!< ADC0 DR: V_VREF Position */ #define ADC0_DR_V_VREF_Msk (0x000003ffUL << ADC0_DR_V_VREF_Pos) /*!< ADC0 DR: V_VREF Mask */ #define ADC0_DR_OVERRUN_Pos 30 /*!< ADC0 DR: OVERRUN Position */ #define ADC0_DR_OVERRUN_Msk (0x01UL << ADC0_DR_OVERRUN_Pos) /*!< ADC0 DR: OVERRUN Mask */ #define ADC0_DR_DONE_Pos 31 /*!< ADC0 DR: DONE Position */ #define ADC0_DR_DONE_Msk (0x01UL << ADC0_DR_DONE_Pos) /*!< ADC0 DR: DONE Mask */ /* ---------------------------------- ADC0_STAT --------------------------------- */ #define ADC0_STAT_DONE_Pos 0 /*!< ADC0 STAT: DONE Position */ #define ADC0_STAT_DONE_Msk (0x000000ffUL << ADC0_STAT_DONE_Pos) /*!< ADC0 STAT: DONE Mask */ #define ADC0_STAT_OVERUN_Pos 8 /*!< ADC0 STAT: OVERUN Position */ #define ADC0_STAT_OVERUN_Msk (0x000000ffUL << ADC0_STAT_OVERUN_Pos) /*!< ADC0 STAT: OVERUN Mask */ #define ADC0_STAT_ADINT_Pos 16 /*!< ADC0 STAT: ADINT Position */ #define ADC0_STAT_ADINT_Msk (0x01UL << ADC0_STAT_ADINT_Pos) /*!< ADC0 STAT: ADINT Mask */ /* ================================================================================ */ /* ================ struct 'ADC1' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- ADC1_CR ---------------------------------- */ #define ADC1_CR_SEL_Pos 0 /*!< ADC1 CR: SEL Position */ #define ADC1_CR_SEL_Msk (0x000000ffUL << ADC1_CR_SEL_Pos) /*!< ADC1 CR: SEL Mask */ #define ADC1_CR_CLKDIV_Pos 8 /*!< ADC1 CR: CLKDIV Position */ #define ADC1_CR_CLKDIV_Msk (0x000000ffUL << ADC1_CR_CLKDIV_Pos) /*!< ADC1 CR: CLKDIV Mask */ #define ADC1_CR_BURST_Pos 16 /*!< ADC1 CR: BURST Position */ #define ADC1_CR_BURST_Msk (0x01UL << ADC1_CR_BURST_Pos) /*!< ADC1 CR: BURST Mask */ #define ADC1_CR_CLKS_Pos 17 /*!< ADC1 CR: CLKS Position */ #define ADC1_CR_CLKS_Msk (0x07UL << ADC1_CR_CLKS_Pos) /*!< ADC1 CR: CLKS Mask */ #define ADC1_CR_PDN_Pos 21 /*!< ADC1 CR: PDN Position */ #define ADC1_CR_PDN_Msk (0x01UL << ADC1_CR_PDN_Pos) /*!< ADC1 CR: PDN Mask */ #define ADC1_CR_START_Pos 24 /*!< ADC1 CR: START Position */ #define ADC1_CR_START_Msk (0x07UL << ADC1_CR_START_Pos) /*!< ADC1 CR: START Mask */ #define ADC1_CR_EDGE_Pos 27 /*!< ADC1 CR: EDGE Position */ #define ADC1_CR_EDGE_Msk (0x01UL << ADC1_CR_EDGE_Pos) /*!< ADC1 CR: EDGE Mask */ /* ---------------------------------- ADC1_GDR ---------------------------------- */ #define ADC1_GDR_V_VREF_Pos 6 /*!< ADC1 GDR: V_VREF Position */ #define ADC1_GDR_V_VREF_Msk (0x000003ffUL << ADC1_GDR_V_VREF_Pos) /*!< ADC1 GDR: V_VREF Mask */ #define ADC1_GDR_CHN_Pos 24 /*!< ADC1 GDR: CHN Position */ #define ADC1_GDR_CHN_Msk (0x07UL << ADC1_GDR_CHN_Pos) /*!< ADC1 GDR: CHN Mask */ #define ADC1_GDR_OVERRUN_Pos 30 /*!< ADC1 GDR: OVERRUN Position */ #define ADC1_GDR_OVERRUN_Msk (0x01UL << ADC1_GDR_OVERRUN_Pos) /*!< ADC1 GDR: OVERRUN Mask */ #define ADC1_GDR_DONE_Pos 31 /*!< ADC1 GDR: DONE Position */ #define ADC1_GDR_DONE_Msk (0x01UL << ADC1_GDR_DONE_Pos) /*!< ADC1 GDR: DONE Mask */ /* --------------------------------- ADC1_INTEN --------------------------------- */ #define ADC1_INTEN_ADINTEN_Pos 0 /*!< ADC1 INTEN: ADINTEN Position */ #define ADC1_INTEN_ADINTEN_Msk (0x000000ffUL << ADC1_INTEN_ADINTEN_Pos) /*!< ADC1 INTEN: ADINTEN Mask */ #define ADC1_INTEN_ADGINTEN_Pos 8 /*!< ADC1 INTEN: ADGINTEN Position */ #define ADC1_INTEN_ADGINTEN_Msk (0x01UL << ADC1_INTEN_ADGINTEN_Pos) /*!< ADC1 INTEN: ADGINTEN Mask */ /* ----------------------------------- ADC1_DR ---------------------------------- */ #define ADC1_DR_V_VREF_Pos 6 /*!< ADC1 DR: V_VREF Position */ #define ADC1_DR_V_VREF_Msk (0x000003ffUL << ADC1_DR_V_VREF_Pos) /*!< ADC1 DR: V_VREF Mask */ #define ADC1_DR_OVERRUN_Pos 30 /*!< ADC1 DR: OVERRUN Position */ #define ADC1_DR_OVERRUN_Msk (0x01UL << ADC1_DR_OVERRUN_Pos) /*!< ADC1 DR: OVERRUN Mask */ #define ADC1_DR_DONE_Pos 31 /*!< ADC1 DR: DONE Position */ #define ADC1_DR_DONE_Msk (0x01UL << ADC1_DR_DONE_Pos) /*!< ADC1 DR: DONE Mask */ /* ---------------------------------- ADC1_STAT --------------------------------- */ #define ADC1_STAT_DONE_Pos 0 /*!< ADC1 STAT: DONE Position */ #define ADC1_STAT_DONE_Msk (0x000000ffUL << ADC1_STAT_DONE_Pos) /*!< ADC1 STAT: DONE Mask */ #define ADC1_STAT_OVERUN_Pos 8 /*!< ADC1 STAT: OVERUN Position */ #define ADC1_STAT_OVERUN_Msk (0x000000ffUL << ADC1_STAT_OVERUN_Pos) /*!< ADC1 STAT: OVERUN Mask */ #define ADC1_STAT_ADINT_Pos 16 /*!< ADC1 STAT: ADINT Position */ #define ADC1_STAT_ADINT_Msk (0x01UL << ADC1_STAT_ADINT_Pos) /*!< ADC1 STAT: ADINT Mask */ /* ================================================================================ */ /* ================ struct 'ADCHS' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- ADCHS_FLUSH -------------------------------- */ #define ADCHS_FLUSH_FIFO_FLUSH_Pos 0 /*!< ADCHS FLUSH: FIFO_FLUSH Position */ #define ADCHS_FLUSH_FIFO_FLUSH_Msk (0x01UL << ADCHS_FLUSH_FIFO_FLUSH_Pos) /*!< ADCHS FLUSH: FIFO_FLUSH Mask */ /* -------------------------------- ADCHS_DMA_REQ ------------------------------- */ #define ADCHS_DMA_REQ_DMA_REQ_WR_Pos 0 /*!< ADCHS DMA_REQ: DMA_REQ_WR Position */ #define ADCHS_DMA_REQ_DMA_REQ_WR_Msk (0x01UL << ADCHS_DMA_REQ_DMA_REQ_WR_Pos) /*!< ADCHS DMA_REQ: DMA_REQ_WR Mask */ /* ------------------------------- ADCHS_FIFO_STS ------------------------------- */ #define ADCHS_FIFO_STS_LEVEL_Pos 0 /*!< ADCHS FIFO_STS: LEVEL Position */ #define ADCHS_FIFO_STS_LEVEL_Msk (0x1fUL << ADCHS_FIFO_STS_LEVEL_Pos) /*!< ADCHS FIFO_STS: LEVEL Mask */ /* ------------------------------- ADCHS_FIFO_CFG ------------------------------- */ #define ADCHS_FIFO_CFG_PACKED_READ_Pos 0 /*!< ADCHS FIFO_CFG: PACKED_READ Position */ #define ADCHS_FIFO_CFG_PACKED_READ_Msk (0x01UL << ADCHS_FIFO_CFG_PACKED_READ_Pos) /*!< ADCHS FIFO_CFG: PACKED_READ Mask */ #define ADCHS_FIFO_CFG_LEVEL_Pos 1 /*!< ADCHS FIFO_CFG: LEVEL Position */ #define ADCHS_FIFO_CFG_LEVEL_Msk (0x1fUL << ADCHS_FIFO_CFG_LEVEL_Pos) /*!< ADCHS FIFO_CFG: LEVEL Mask */ /* -------------------------------- ADCHS_TRIGGER ------------------------------- */ #define ADCHS_TRIGGER_SW_TRIGGER_Pos 0 /*!< ADCHS TRIGGER: SW_TRIGGER Position */ #define ADCHS_TRIGGER_SW_TRIGGER_Msk (0x01UL << ADCHS_TRIGGER_SW_TRIGGER_Pos) /*!< ADCHS TRIGGER: SW_TRIGGER Mask */ /* ------------------------------- ADCHS_DSCR_STS ------------------------------- */ #define ADCHS_DSCR_STS_ACT_TABLE_Pos 0 /*!< ADCHS DSCR_STS: ACT_TABLE Position */ #define ADCHS_DSCR_STS_ACT_TABLE_Msk (0x01UL << ADCHS_DSCR_STS_ACT_TABLE_Pos) /*!< ADCHS DSCR_STS: ACT_TABLE Mask */ #define ADCHS_DSCR_STS_ACT_DESCRIPTOR_Pos 1 /*!< ADCHS DSCR_STS: ACT_DESCRIPTOR Position */ #define ADCHS_DSCR_STS_ACT_DESCRIPTOR_Msk (0x07UL << ADCHS_DSCR_STS_ACT_DESCRIPTOR_Pos) /*!< ADCHS DSCR_STS: ACT_DESCRIPTOR Mask */ /* ------------------------------ ADCHS_POWER_DOWN ------------------------------ */ #define ADCHS_POWER_DOWN_PD_CTRL_Pos 0 /*!< ADCHS POWER_DOWN: PD_CTRL Position */ #define ADCHS_POWER_DOWN_PD_CTRL_Msk (0x01UL << ADCHS_POWER_DOWN_PD_CTRL_Pos) /*!< ADCHS POWER_DOWN: PD_CTRL Mask */ /* -------------------------------- ADCHS_CONFIG -------------------------------- */ #define ADCHS_CONFIG_TRIGGER__MASK_Pos 0 /*!< ADCHS CONFIG: TRIGGER__MASK Position */ #define ADCHS_CONFIG_TRIGGER__MASK_Msk (0x03UL << ADCHS_CONFIG_TRIGGER__MASK_Pos) /*!< ADCHS CONFIG: TRIGGER__MASK Mask */ #define ADCHS_CONFIG_TRIGGER_MODE_Pos 2 /*!< ADCHS CONFIG: TRIGGER_MODE Position */ #define ADCHS_CONFIG_TRIGGER_MODE_Msk (0x03UL << ADCHS_CONFIG_TRIGGER_MODE_Pos) /*!< ADCHS CONFIG: TRIGGER_MODE Mask */ #define ADCHS_CONFIG_TRIGGER_SYNC_Pos 4 /*!< ADCHS CONFIG: TRIGGER_SYNC Position */ #define ADCHS_CONFIG_TRIGGER_SYNC_Msk (0x01UL << ADCHS_CONFIG_TRIGGER_SYNC_Pos) /*!< ADCHS CONFIG: TRIGGER_SYNC Mask */ #define ADCHS_CONFIG_CHANNEL_ID_EN_Pos 5 /*!< ADCHS CONFIG: CHANNEL_ID_EN Position */ #define ADCHS_CONFIG_CHANNEL_ID_EN_Msk (0x01UL << ADCHS_CONFIG_CHANNEL_ID_EN_Pos) /*!< ADCHS CONFIG: CHANNEL_ID_EN Mask */ #define ADCHS_CONFIG_RECOVERY_TIME_Pos 6 /*!< ADCHS CONFIG: RECOVERY_TIME Position */ #define ADCHS_CONFIG_RECOVERY_TIME_Msk (0x000000ffUL << ADCHS_CONFIG_RECOVERY_TIME_Pos) /*!< ADCHS CONFIG: RECOVERY_TIME Mask */ /* --------------------------------- ADCHS_THR_A -------------------------------- */ #define ADCHS_THR_A_THR_LOW_A_Pos 0 /*!< ADCHS THR_A: THR_LOW_A Position */ #define ADCHS_THR_A_THR_LOW_A_Msk (0x00000fffUL << ADCHS_THR_A_THR_LOW_A_Pos) /*!< ADCHS THR_A: THR_LOW_A Mask */ #define ADCHS_THR_A_THR_HIGH_A_Pos 16 /*!< ADCHS THR_A: THR_HIGH_A Position */ #define ADCHS_THR_A_THR_HIGH_A_Msk (0x00000fffUL << ADCHS_THR_A_THR_HIGH_A_Pos) /*!< ADCHS THR_A: THR_HIGH_A Mask */ /* --------------------------------- ADCHS_THR_B -------------------------------- */ #define ADCHS_THR_B_THR_LOW_B_Pos 0 /*!< ADCHS THR_B: THR_LOW_B Position */ #define ADCHS_THR_B_THR_LOW_B_Msk (0x00000fffUL << ADCHS_THR_B_THR_LOW_B_Pos) /*!< ADCHS THR_B: THR_LOW_B Mask */ #define ADCHS_THR_B_THR_HIGH_B_Pos 16 /*!< ADCHS THR_B: THR_HIGH_B Position */ #define ADCHS_THR_B_THR_HIGH_B_Msk (0x00000fffUL << ADCHS_THR_B_THR_HIGH_B_Pos) /*!< ADCHS THR_B: THR_HIGH_B Mask */ /* ------------------------------ ADCHS_LAST_SAMPLE ----------------------------- */ #define ADCHS_LAST_SAMPLE_DONE_Pos 0 /*!< ADCHS LAST_SAMPLE: DONE Position */ #define ADCHS_LAST_SAMPLE_DONE_Msk (0x01UL << ADCHS_LAST_SAMPLE_DONE_Pos) /*!< ADCHS LAST_SAMPLE: DONE Mask */ #define ADCHS_LAST_SAMPLE_OVERRUN_Pos 1 /*!< ADCHS LAST_SAMPLE: OVERRUN Position */ #define ADCHS_LAST_SAMPLE_OVERRUN_Msk (0x01UL << ADCHS_LAST_SAMPLE_OVERRUN_Pos) /*!< ADCHS LAST_SAMPLE: OVERRUN Mask */ #define ADCHS_LAST_SAMPLE_THCMP_RANGE_Pos 2 /*!< ADCHS LAST_SAMPLE: THCMP_RANGE Position */ #define ADCHS_LAST_SAMPLE_THCMP_RANGE_Msk (0x03UL << ADCHS_LAST_SAMPLE_THCMP_RANGE_Pos) /*!< ADCHS LAST_SAMPLE: THCMP_RANGE Mask */ #define ADCHS_LAST_SAMPLE_THCMP_CROSS_Pos 4 /*!< ADCHS LAST_SAMPLE: THCMP_CROSS Position */ #define ADCHS_LAST_SAMPLE_THCMP_CROSS_Msk (0x03UL << ADCHS_LAST_SAMPLE_THCMP_CROSS_Pos) /*!< ADCHS LAST_SAMPLE: THCMP_CROSS Mask */ #define ADCHS_LAST_SAMPLE_SAMPLE_Pos 6 /*!< ADCHS LAST_SAMPLE: SAMPLE Position */ #define ADCHS_LAST_SAMPLE_SAMPLE_Msk (0x00000fffUL << ADCHS_LAST_SAMPLE_SAMPLE_Pos) /*!< ADCHS LAST_SAMPLE: SAMPLE Mask */ /* ------------------------------- ADCHS_ADC_SPEED ------------------------------ */ #define ADCHS_ADC_SPEED_DGEC0_Pos 0 /*!< ADCHS ADC_SPEED: DGEC0 Position */ #define ADCHS_ADC_SPEED_DGEC0_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC0_Pos) /*!< ADCHS ADC_SPEED: DGEC0 Mask */ #define ADCHS_ADC_SPEED_DGEC1_Pos 4 /*!< ADCHS ADC_SPEED: DGEC1 Position */ #define ADCHS_ADC_SPEED_DGEC1_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC1_Pos) /*!< ADCHS ADC_SPEED: DGEC1 Mask */ #define ADCHS_ADC_SPEED_DGEC2_Pos 8 /*!< ADCHS ADC_SPEED: DGEC2 Position */ #define ADCHS_ADC_SPEED_DGEC2_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC2_Pos) /*!< ADCHS ADC_SPEED: DGEC2 Mask */ #define ADCHS_ADC_SPEED_DGEC3_Pos 12 /*!< ADCHS ADC_SPEED: DGEC3 Position */ #define ADCHS_ADC_SPEED_DGEC3_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC3_Pos) /*!< ADCHS ADC_SPEED: DGEC3 Mask */ #define ADCHS_ADC_SPEED_DGEC4_Pos 16 /*!< ADCHS ADC_SPEED: DGEC4 Position */ #define ADCHS_ADC_SPEED_DGEC4_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC4_Pos) /*!< ADCHS ADC_SPEED: DGEC4 Mask */ #define ADCHS_ADC_SPEED_DGEC5_Pos 20 /*!< ADCHS ADC_SPEED: DGEC5 Position */ #define ADCHS_ADC_SPEED_DGEC5_Msk (0x0fUL << ADCHS_ADC_SPEED_DGEC5_Pos) /*!< ADCHS ADC_SPEED: DGEC5 Mask */ /* ----------------------------- ADCHS_POWER_CONTROL ---------------------------- */ #define ADCHS_POWER_CONTROL_CRS_Pos 0 /*!< ADCHS POWER_CONTROL: CRS Position */ #define ADCHS_POWER_CONTROL_CRS_Msk (0x0fUL << ADCHS_POWER_CONTROL_CRS_Pos) /*!< ADCHS POWER_CONTROL: CRS Mask */ #define ADCHS_POWER_CONTROL_DCINNEG_Pos 4 /*!< ADCHS POWER_CONTROL: DCINNEG Position */ #define ADCHS_POWER_CONTROL_DCINNEG_Msk (0x3fUL << ADCHS_POWER_CONTROL_DCINNEG_Pos) /*!< ADCHS POWER_CONTROL: DCINNEG Mask */ #define ADCHS_POWER_CONTROL_DCINPOS_Pos 10 /*!< ADCHS POWER_CONTROL: DCINPOS Position */ #define ADCHS_POWER_CONTROL_DCINPOS_Msk (0x3fUL << ADCHS_POWER_CONTROL_DCINPOS_Pos) /*!< ADCHS POWER_CONTROL: DCINPOS Mask */ #define ADCHS_POWER_CONTROL_TWOS_Pos 16 /*!< ADCHS POWER_CONTROL: TWOS Position */ #define ADCHS_POWER_CONTROL_TWOS_Msk (0x01UL << ADCHS_POWER_CONTROL_TWOS_Pos) /*!< ADCHS POWER_CONTROL: TWOS Mask */ #define ADCHS_POWER_CONTROL_POWER_SWITCH_Pos 17 /*!< ADCHS POWER_CONTROL: POWER_SWITCH Position */ #define ADCHS_POWER_CONTROL_POWER_SWITCH_Msk (0x01UL << ADCHS_POWER_CONTROL_POWER_SWITCH_Pos) /*!< ADCHS POWER_CONTROL: POWER_SWITCH Mask */ #define ADCHS_POWER_CONTROL_BGAP_SWITCH_Pos 18 /*!< ADCHS POWER_CONTROL: BGAP_SWITCH Position */ #define ADCHS_POWER_CONTROL_BGAP_SWITCH_Msk (0x01UL << ADCHS_POWER_CONTROL_BGAP_SWITCH_Pos) /*!< ADCHS POWER_CONTROL: BGAP_SWITCH Mask */ /* ------------------------------ ADCHS_FIFO_OUTPUT ----------------------------- */ #define ADCHS_FIFO_OUTPUT_SAMPLE_Pos 0 /*!< ADCHS FIFO_OUTPUT: SAMPLE Position */ #define ADCHS_FIFO_OUTPUT_SAMPLE_Msk (0x00000fffUL << ADCHS_FIFO_OUTPUT_SAMPLE_Pos) /*!< ADCHS FIFO_OUTPUT: SAMPLE Mask */ #define ADCHS_FIFO_OUTPUT_CHAN_ID_Pos 12 /*!< ADCHS FIFO_OUTPUT: CHAN_ID Position */ #define ADCHS_FIFO_OUTPUT_CHAN_ID_Msk (0x07UL << ADCHS_FIFO_OUTPUT_CHAN_ID_Pos) /*!< ADCHS FIFO_OUTPUT: CHAN_ID Mask */ #define ADCHS_FIFO_OUTPUT_EMPTY_Pos 15 /*!< ADCHS FIFO_OUTPUT: EMPTY Position */ #define ADCHS_FIFO_OUTPUT_EMPTY_Msk (0x01UL << ADCHS_FIFO_OUTPUT_EMPTY_Pos) /*!< ADCHS FIFO_OUTPUT: EMPTY Mask */ #define ADCHS_FIFO_OUTPUT_SAMPLE2_Pos 16 /*!< ADCHS FIFO_OUTPUT: SAMPLE2 Position */ #define ADCHS_FIFO_OUTPUT_SAMPLE2_Msk (0x00000fffUL << ADCHS_FIFO_OUTPUT_SAMPLE2_Pos) /*!< ADCHS FIFO_OUTPUT: SAMPLE2 Mask */ #define ADCHS_FIFO_OUTPUT_CHAN_ID2_Pos 28 /*!< ADCHS FIFO_OUTPUT: CHAN_ID2 Position */ #define ADCHS_FIFO_OUTPUT_CHAN_ID2_Msk (0x07UL << ADCHS_FIFO_OUTPUT_CHAN_ID2_Pos) /*!< ADCHS FIFO_OUTPUT: CHAN_ID2 Mask */ #define ADCHS_FIFO_OUTPUT_EMPTY2_Pos 31 /*!< ADCHS FIFO_OUTPUT: EMPTY2 Position */ #define ADCHS_FIFO_OUTPUT_EMPTY2_Msk (0x01UL << ADCHS_FIFO_OUTPUT_EMPTY2_Pos) /*!< ADCHS FIFO_OUTPUT: EMPTY2 Mask */ /* ----------------------------- ADCHS_DESCRIPTOR0_ ----------------------------- */ #define ADCHS_DESCRIPTOR0__CHANNEL_NR_Pos 0 /*!< ADCHS DESCRIPTOR0_: CHANNEL_NR Position */ #define ADCHS_DESCRIPTOR0__CHANNEL_NR_Msk (0x07UL << ADCHS_DESCRIPTOR0__CHANNEL_NR_Pos) /*!< ADCHS DESCRIPTOR0_: CHANNEL_NR Mask */ #define ADCHS_DESCRIPTOR0__HALT_Pos 3 /*!< ADCHS DESCRIPTOR0_: HALT Position */ #define ADCHS_DESCRIPTOR0__HALT_Msk (0x01UL << ADCHS_DESCRIPTOR0__HALT_Pos) /*!< ADCHS DESCRIPTOR0_: HALT Mask */ #define ADCHS_DESCRIPTOR0__INTERRUPT_Pos 4 /*!< ADCHS DESCRIPTOR0_: INTERRUPT Position */ #define ADCHS_DESCRIPTOR0__INTERRUPT_Msk (0x01UL << ADCHS_DESCRIPTOR0__INTERRUPT_Pos) /*!< ADCHS DESCRIPTOR0_: INTERRUPT Mask */ #define ADCHS_DESCRIPTOR0__POWER_DOWN_Pos 5 /*!< ADCHS DESCRIPTOR0_: POWER_DOWN Position */ #define ADCHS_DESCRIPTOR0__POWER_DOWN_Msk (0x01UL << ADCHS_DESCRIPTOR0__POWER_DOWN_Pos) /*!< ADCHS DESCRIPTOR0_: POWER_DOWN Mask */ #define ADCHS_DESCRIPTOR0__BRANCH_Pos 6 /*!< ADCHS DESCRIPTOR0_: BRANCH Position */ #define ADCHS_DESCRIPTOR0__BRANCH_Msk (0x03UL << ADCHS_DESCRIPTOR0__BRANCH_Pos) /*!< ADCHS DESCRIPTOR0_: BRANCH Mask */ #define ADCHS_DESCRIPTOR0__MATCH_VALUE_Pos 8 /*!< ADCHS DESCRIPTOR0_: MATCH_VALUE Position */ #define ADCHS_DESCRIPTOR0__MATCH_VALUE_Msk (0x00003fffUL << ADCHS_DESCRIPTOR0__MATCH_VALUE_Pos) /*!< ADCHS DESCRIPTOR0_: MATCH_VALUE Mask */ #define ADCHS_DESCRIPTOR0__THRESHOLD_SEL_Pos 22 /*!< ADCHS DESCRIPTOR0_: THRESHOLD_SEL Position */ #define ADCHS_DESCRIPTOR0__THRESHOLD_SEL_Msk (0x03UL << ADCHS_DESCRIPTOR0__THRESHOLD_SEL_Pos) /*!< ADCHS DESCRIPTOR0_: THRESHOLD_SEL Mask */ #define ADCHS_DESCRIPTOR0__RESET_TIMER_Pos 24 /*!< ADCHS DESCRIPTOR0_: RESET_TIMER Position */ #define ADCHS_DESCRIPTOR0__RESET_TIMER_Msk (0x01UL << ADCHS_DESCRIPTOR0__RESET_TIMER_Pos) /*!< ADCHS DESCRIPTOR0_: RESET_TIMER Mask */ #define ADCHS_DESCRIPTOR0__UPDATE_TABLE_Pos 31 /*!< ADCHS DESCRIPTOR0_: UPDATE_TABLE Position */ #define ADCHS_DESCRIPTOR0__UPDATE_TABLE_Msk (0x01UL << ADCHS_DESCRIPTOR0__UPDATE_TABLE_Pos) /*!< ADCHS DESCRIPTOR0_: UPDATE_TABLE Mask */ /* ----------------------------- ADCHS_DESCRIPTOR1_ ----------------------------- */ #define ADCHS_DESCRIPTOR1__CHANNEL_NR_Pos 0 /*!< ADCHS DESCRIPTOR1_: CHANNEL_NR Position */ #define ADCHS_DESCRIPTOR1__CHANNEL_NR_Msk (0x07UL << ADCHS_DESCRIPTOR1__CHANNEL_NR_Pos) /*!< ADCHS DESCRIPTOR1_: CHANNEL_NR Mask */ #define ADCHS_DESCRIPTOR1__HALT_Pos 3 /*!< ADCHS DESCRIPTOR1_: HALT Position */ #define ADCHS_DESCRIPTOR1__HALT_Msk (0x01UL << ADCHS_DESCRIPTOR1__HALT_Pos) /*!< ADCHS DESCRIPTOR1_: HALT Mask */ #define ADCHS_DESCRIPTOR1__INTERRUPT_Pos 4 /*!< ADCHS DESCRIPTOR1_: INTERRUPT Position */ #define ADCHS_DESCRIPTOR1__INTERRUPT_Msk (0x01UL << ADCHS_DESCRIPTOR1__INTERRUPT_Pos) /*!< ADCHS DESCRIPTOR1_: INTERRUPT Mask */ #define ADCHS_DESCRIPTOR1__POWER_DOWN_Pos 5 /*!< ADCHS DESCRIPTOR1_: POWER_DOWN Position */ #define ADCHS_DESCRIPTOR1__POWER_DOWN_Msk (0x01UL << ADCHS_DESCRIPTOR1__POWER_DOWN_Pos) /*!< ADCHS DESCRIPTOR1_: POWER_DOWN Mask */ #define ADCHS_DESCRIPTOR1__BRANCH_Pos 6 /*!< ADCHS DESCRIPTOR1_: BRANCH Position */ #define ADCHS_DESCRIPTOR1__BRANCH_Msk (0x03UL << ADCHS_DESCRIPTOR1__BRANCH_Pos) /*!< ADCHS DESCRIPTOR1_: BRANCH Mask */ #define ADCHS_DESCRIPTOR1__MATCH_VALUE_Pos 8 /*!< ADCHS DESCRIPTOR1_: MATCH_VALUE Position */ #define ADCHS_DESCRIPTOR1__MATCH_VALUE_Msk (0x00003fffUL << ADCHS_DESCRIPTOR1__MATCH_VALUE_Pos) /*!< ADCHS DESCRIPTOR1_: MATCH_VALUE Mask */ #define ADCHS_DESCRIPTOR1__THRESHOLD_SEL_Pos 22 /*!< ADCHS DESCRIPTOR1_: THRESHOLD_SEL Position */ #define ADCHS_DESCRIPTOR1__THRESHOLD_SEL_Msk (0x03UL << ADCHS_DESCRIPTOR1__THRESHOLD_SEL_Pos) /*!< ADCHS DESCRIPTOR1_: THRESHOLD_SEL Mask */ #define ADCHS_DESCRIPTOR1__RESET_TIMER_Pos 24 /*!< ADCHS DESCRIPTOR1_: RESET_TIMER Position */ #define ADCHS_DESCRIPTOR1__RESET_TIMER_Msk (0x01UL << ADCHS_DESCRIPTOR1__RESET_TIMER_Pos) /*!< ADCHS DESCRIPTOR1_: RESET_TIMER Mask */ #define ADCHS_DESCRIPTOR1__UPDATE_TABLE_Pos 31 /*!< ADCHS DESCRIPTOR1_: UPDATE_TABLE Position */ #define ADCHS_DESCRIPTOR1__UPDATE_TABLE_Msk (0x01UL << ADCHS_DESCRIPTOR1__UPDATE_TABLE_Pos) /*!< ADCHS DESCRIPTOR1_: UPDATE_TABLE Mask */ /* -------------------------------- ADCHS_CLR_EN0 ------------------------------- */ #define ADCHS_CLR_EN0_CEN0_Pos 0 /*!< ADCHS CLR_EN0: CEN0 Position */ #define ADCHS_CLR_EN0_CEN0_Msk (0x7fUL << ADCHS_CLR_EN0_CEN0_Pos) /*!< ADCHS CLR_EN0: CEN0 Mask */ /* -------------------------------- ADCHS_SET_EN0 ------------------------------- */ #define ADCHS_SET_EN0_SEN0_Pos 0 /*!< ADCHS SET_EN0: SEN0 Position */ #define ADCHS_SET_EN0_SEN0_Msk (0x7fUL << ADCHS_SET_EN0_SEN0_Pos) /*!< ADCHS SET_EN0: SEN0 Mask */ /* --------------------------------- ADCHS_MASK0 -------------------------------- */ #define ADCHS_MASK0_M0_Pos 0 /*!< ADCHS MASK0: M0 Position */ #define ADCHS_MASK0_M0_Msk (0x7fUL << ADCHS_MASK0_M0_Pos) /*!< ADCHS MASK0: M0 Mask */ /* -------------------------------- ADCHS_STATUS0 ------------------------------- */ #define ADCHS_STATUS0_FIFO_FULL_Pos 0 /*!< ADCHS STATUS0: FIFO_FULL Position */ #define ADCHS_STATUS0_FIFO_FULL_Msk (0x01UL << ADCHS_STATUS0_FIFO_FULL_Pos) /*!< ADCHS STATUS0: FIFO_FULL Mask */ #define ADCHS_STATUS0_FIFO_EMPTY_Pos 1 /*!< ADCHS STATUS0: FIFO_EMPTY Position */ #define ADCHS_STATUS0_FIFO_EMPTY_Msk (0x01UL << ADCHS_STATUS0_FIFO_EMPTY_Pos) /*!< ADCHS STATUS0: FIFO_EMPTY Mask */ #define ADCHS_STATUS0_FIFO_OVERFLOW_Pos 2 /*!< ADCHS STATUS0: FIFO_OVERFLOW Position */ #define ADCHS_STATUS0_FIFO_OVERFLOW_Msk (0x01UL << ADCHS_STATUS0_FIFO_OVERFLOW_Pos) /*!< ADCHS STATUS0: FIFO_OVERFLOW Mask */ #define ADCHS_STATUS0_DSCR_DONE_Pos 3 /*!< ADCHS STATUS0: DSCR_DONE Position */ #define ADCHS_STATUS0_DSCR_DONE_Msk (0x01UL << ADCHS_STATUS0_DSCR_DONE_Pos) /*!< ADCHS STATUS0: DSCR_DONE Mask */ #define ADCHS_STATUS0_DSCR_ERROR_Pos 4 /*!< ADCHS STATUS0: DSCR_ERROR Position */ #define ADCHS_STATUS0_DSCR_ERROR_Msk (0x01UL << ADCHS_STATUS0_DSCR_ERROR_Pos) /*!< ADCHS STATUS0: DSCR_ERROR Mask */ #define ADCHS_STATUS0_ADC_OVF_Pos 5 /*!< ADCHS STATUS0: ADC_OVF Position */ #define ADCHS_STATUS0_ADC_OVF_Msk (0x01UL << ADCHS_STATUS0_ADC_OVF_Pos) /*!< ADCHS STATUS0: ADC_OVF Mask */ #define ADCHS_STATUS0_ADC_UNF_Pos 6 /*!< ADCHS STATUS0: ADC_UNF Position */ #define ADCHS_STATUS0_ADC_UNF_Msk (0x01UL << ADCHS_STATUS0_ADC_UNF_Pos) /*!< ADCHS STATUS0: ADC_UNF Mask */ /* ------------------------------- ADCHS_CLR_STAT0 ------------------------------ */ #define ADCHS_CLR_STAT0_CSTAT0_Pos 0 /*!< ADCHS CLR_STAT0: CSTAT0 Position */ #define ADCHS_CLR_STAT0_CSTAT0_Msk (0x7fUL << ADCHS_CLR_STAT0_CSTAT0_Pos) /*!< ADCHS CLR_STAT0: CSTAT0 Mask */ /* ------------------------------- ADCHS_SET_STAT0 ------------------------------ */ #define ADCHS_SET_STAT0_SSTAT0_Pos 0 /*!< ADCHS SET_STAT0: SSTAT0 Position */ #define ADCHS_SET_STAT0_SSTAT0_Msk (0x7fUL << ADCHS_SET_STAT0_SSTAT0_Pos) /*!< ADCHS SET_STAT0: SSTAT0 Mask */ /* -------------------------------- ADCHS_CLR_EN1 ------------------------------- */ #define ADCHS_CLR_EN1_CEN1_Pos 0 /*!< ADCHS CLR_EN1: CEN1 Position */ #define ADCHS_CLR_EN1_CEN1_Msk (0x3fffffffUL << ADCHS_CLR_EN1_CEN1_Pos) /*!< ADCHS CLR_EN1: CEN1 Mask */ /* -------------------------------- ADCHS_SET_EN1 ------------------------------- */ #define ADCHS_SET_EN1_SEN1_Pos 0 /*!< ADCHS SET_EN1: SEN1 Position */ #define ADCHS_SET_EN1_SEN1_Msk (0x3fffffffUL << ADCHS_SET_EN1_SEN1_Pos) /*!< ADCHS SET_EN1: SEN1 Mask */ /* --------------------------------- ADCHS_MASK1 -------------------------------- */ #define ADCHS_MASK1_M1_Pos 0 /*!< ADCHS MASK1: M1 Position */ #define ADCHS_MASK1_M1_Msk (0x3fffffffUL << ADCHS_MASK1_M1_Pos) /*!< ADCHS MASK1: M1 Mask */ /* -------------------------------- ADCHS_STATUS1 ------------------------------- */ #define ADCHS_STATUS1_THCMP_BRANGE0_Pos 0 /*!< ADCHS STATUS1: THCMP_BRANGE0 Position */ #define ADCHS_STATUS1_THCMP_BRANGE0_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE0_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE0 Mask */ #define ADCHS_STATUS1_THCMP_ARANGE0_Pos 1 /*!< ADCHS STATUS1: THCMP_ARANGE0 Position */ #define ADCHS_STATUS1_THCMP_ARANGE0_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE0_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE0 Mask */ #define ADCHS_STATUS1_THCMP_DCROSS0_Pos 2 /*!< ADCHS STATUS1: THCMP_DCROSS0 Position */ #define ADCHS_STATUS1_THCMP_DCROSS0_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS0_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS0 Mask */ #define ADCHS_STATUS1_THCMP_UCROSS0_Pos 3 /*!< ADCHS STATUS1: THCMP_UCROSS0 Position */ #define ADCHS_STATUS1_THCMP_UCROSS0_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS0_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS0 Mask */ #define ADCHS_STATUS1_OVERRUN_0_Pos 4 /*!< ADCHS STATUS1: OVERRUN_0 Position */ #define ADCHS_STATUS1_OVERRUN_0_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_0_Pos) /*!< ADCHS STATUS1: OVERRUN_0 Mask */ #define ADCHS_STATUS1_THCMP_BRANGE1_Pos 5 /*!< ADCHS STATUS1: THCMP_BRANGE1 Position */ #define ADCHS_STATUS1_THCMP_BRANGE1_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE1_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE1 Mask */ #define ADCHS_STATUS1_THCMP_ARANGE1_Pos 6 /*!< ADCHS STATUS1: THCMP_ARANGE1 Position */ #define ADCHS_STATUS1_THCMP_ARANGE1_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE1_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE1 Mask */ #define ADCHS_STATUS1_THCMP_DCROSS1_Pos 7 /*!< ADCHS STATUS1: THCMP_DCROSS1 Position */ #define ADCHS_STATUS1_THCMP_DCROSS1_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS1_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS1 Mask */ #define ADCHS_STATUS1_THCMP_UCROSS1_Pos 8 /*!< ADCHS STATUS1: THCMP_UCROSS1 Position */ #define ADCHS_STATUS1_THCMP_UCROSS1_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS1_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS1 Mask */ #define ADCHS_STATUS1_OVERRUN_1_Pos 9 /*!< ADCHS STATUS1: OVERRUN_1 Position */ #define ADCHS_STATUS1_OVERRUN_1_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_1_Pos) /*!< ADCHS STATUS1: OVERRUN_1 Mask */ #define ADCHS_STATUS1_THCMP_BRANGE2_Pos 10 /*!< ADCHS STATUS1: THCMP_BRANGE2 Position */ #define ADCHS_STATUS1_THCMP_BRANGE2_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE2_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE2 Mask */ #define ADCHS_STATUS1_THCMP_ARANGE2_Pos 11 /*!< ADCHS STATUS1: THCMP_ARANGE2 Position */ #define ADCHS_STATUS1_THCMP_ARANGE2_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE2_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE2 Mask */ #define ADCHS_STATUS1_THCMP_DCROSS2_Pos 12 /*!< ADCHS STATUS1: THCMP_DCROSS2 Position */ #define ADCHS_STATUS1_THCMP_DCROSS2_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS2_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS2 Mask */ #define ADCHS_STATUS1_THCMP_UCROSS2_Pos 13 /*!< ADCHS STATUS1: THCMP_UCROSS2 Position */ #define ADCHS_STATUS1_THCMP_UCROSS2_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS2_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS2 Mask */ #define ADCHS_STATUS1_OVERRUN_2_Pos 14 /*!< ADCHS STATUS1: OVERRUN_2 Position */ #define ADCHS_STATUS1_OVERRUN_2_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_2_Pos) /*!< ADCHS STATUS1: OVERRUN_2 Mask */ #define ADCHS_STATUS1_THCMP_BRANGE3_Pos 15 /*!< ADCHS STATUS1: THCMP_BRANGE3 Position */ #define ADCHS_STATUS1_THCMP_BRANGE3_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE3_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE3 Mask */ #define ADCHS_STATUS1_THCMP_ARANGE3_Pos 16 /*!< ADCHS STATUS1: THCMP_ARANGE3 Position */ #define ADCHS_STATUS1_THCMP_ARANGE3_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE3_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE3 Mask */ #define ADCHS_STATUS1_THCMP_DCROSS3_Pos 17 /*!< ADCHS STATUS1: THCMP_DCROSS3 Position */ #define ADCHS_STATUS1_THCMP_DCROSS3_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS3_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS3 Mask */ #define ADCHS_STATUS1_THCMP_UCROSS3_Pos 18 /*!< ADCHS STATUS1: THCMP_UCROSS3 Position */ #define ADCHS_STATUS1_THCMP_UCROSS3_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS3_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS3 Mask */ #define ADCHS_STATUS1_OVERRUN_3_Pos 19 /*!< ADCHS STATUS1: OVERRUN_3 Position */ #define ADCHS_STATUS1_OVERRUN_3_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_3_Pos) /*!< ADCHS STATUS1: OVERRUN_3 Mask */ #define ADCHS_STATUS1_THCMP_BRANGE4_Pos 20 /*!< ADCHS STATUS1: THCMP_BRANGE4 Position */ #define ADCHS_STATUS1_THCMP_BRANGE4_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE4_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE4 Mask */ #define ADCHS_STATUS1_THCMP_ARANGE4_Pos 21 /*!< ADCHS STATUS1: THCMP_ARANGE4 Position */ #define ADCHS_STATUS1_THCMP_ARANGE4_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE4_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE4 Mask */ #define ADCHS_STATUS1_THCMP_DCROSS4_Pos 22 /*!< ADCHS STATUS1: THCMP_DCROSS4 Position */ #define ADCHS_STATUS1_THCMP_DCROSS4_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS4_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS4 Mask */ #define ADCHS_STATUS1_THCMP_UCROSS4_Pos 23 /*!< ADCHS STATUS1: THCMP_UCROSS4 Position */ #define ADCHS_STATUS1_THCMP_UCROSS4_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS4_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS4 Mask */ #define ADCHS_STATUS1_OVERRUN_4_Pos 24 /*!< ADCHS STATUS1: OVERRUN_4 Position */ #define ADCHS_STATUS1_OVERRUN_4_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_4_Pos) /*!< ADCHS STATUS1: OVERRUN_4 Mask */ #define ADCHS_STATUS1_THCMP_BRANGE5_Pos 25 /*!< ADCHS STATUS1: THCMP_BRANGE5 Position */ #define ADCHS_STATUS1_THCMP_BRANGE5_Msk (0x01UL << ADCHS_STATUS1_THCMP_BRANGE5_Pos) /*!< ADCHS STATUS1: THCMP_BRANGE5 Mask */ #define ADCHS_STATUS1_THCMP_ARANGE5_Pos 26 /*!< ADCHS STATUS1: THCMP_ARANGE5 Position */ #define ADCHS_STATUS1_THCMP_ARANGE5_Msk (0x01UL << ADCHS_STATUS1_THCMP_ARANGE5_Pos) /*!< ADCHS STATUS1: THCMP_ARANGE5 Mask */ #define ADCHS_STATUS1_THCMP_DCROSS5_Pos 27 /*!< ADCHS STATUS1: THCMP_DCROSS5 Position */ #define ADCHS_STATUS1_THCMP_DCROSS5_Msk (0x01UL << ADCHS_STATUS1_THCMP_DCROSS5_Pos) /*!< ADCHS STATUS1: THCMP_DCROSS5 Mask */ #define ADCHS_STATUS1_THCMP_UCROSS5_Pos 28 /*!< ADCHS STATUS1: THCMP_UCROSS5 Position */ #define ADCHS_STATUS1_THCMP_UCROSS5_Msk (0x01UL << ADCHS_STATUS1_THCMP_UCROSS5_Pos) /*!< ADCHS STATUS1: THCMP_UCROSS5 Mask */ #define ADCHS_STATUS1_OVERRUN_5_Pos 29 /*!< ADCHS STATUS1: OVERRUN_5 Position */ #define ADCHS_STATUS1_OVERRUN_5_Msk (0x01UL << ADCHS_STATUS1_OVERRUN_5_Pos) /*!< ADCHS STATUS1: OVERRUN_5 Mask */ /* ------------------------------- ADCHS_CLR_STAT1 ------------------------------ */ #define ADCHS_CLR_STAT1_CSTAT1_Pos 0 /*!< ADCHS CLR_STAT1: CSTAT1 Position */ #define ADCHS_CLR_STAT1_CSTAT1_Msk (0x3fffffffUL << ADCHS_CLR_STAT1_CSTAT1_Pos) /*!< ADCHS CLR_STAT1: CSTAT1 Mask */ /* ------------------------------- ADCHS_SET_STAT1 ------------------------------ */ #define ADCHS_SET_STAT1_SSTAT1_Pos 0 /*!< ADCHS SET_STAT1: SSTAT1 Position */ #define ADCHS_SET_STAT1_SSTAT1_Msk (0x3fffffffUL << ADCHS_SET_STAT1_SSTAT1_Pos) /*!< ADCHS SET_STAT1: SSTAT1 Mask */ /* ================================================================================ */ /* ================ struct 'GPIO_PORT' Position & Mask ================ */ /* ================================================================================ */ /* --------------------------------- GPIO_PORT_B -------------------------------- */ #define GPIO_PORT_B_PBYTE_Pos 0 /*!< GPIO_PORT B: PBYTE Position */ #define GPIO_PORT_B_PBYTE_Msk (0x01UL << GPIO_PORT_B_PBYTE_Pos) /*!< GPIO_PORT B: PBYTE Mask */ /* --------------------------------- GPIO_PORT_W -------------------------------- */ #define GPIO_PORT_W_PWORD_Pos 0 /*!< GPIO_PORT W: PWORD Position */ #define GPIO_PORT_W_PWORD_Msk (0xffffffffUL << GPIO_PORT_W_PWORD_Pos) /*!< GPIO_PORT W: PWORD Mask */ /* -------------------------------- GPIO_PORT_DIR ------------------------------- */ #define GPIO_PORT_DIR_DIRP0_Pos 0 /*!< GPIO_PORT DIR: DIRP0 Position */ #define GPIO_PORT_DIR_DIRP0_Msk (0x01UL << GPIO_PORT_DIR_DIRP0_Pos) /*!< GPIO_PORT DIR: DIRP0 Mask */ #define GPIO_PORT_DIR_DIRP1_Pos 1 /*!< GPIO_PORT DIR: DIRP1 Position */ #define GPIO_PORT_DIR_DIRP1_Msk (0x01UL << GPIO_PORT_DIR_DIRP1_Pos) /*!< GPIO_PORT DIR: DIRP1 Mask */ #define GPIO_PORT_DIR_DIRP2_Pos 2 /*!< GPIO_PORT DIR: DIRP2 Position */ #define GPIO_PORT_DIR_DIRP2_Msk (0x01UL << GPIO_PORT_DIR_DIRP2_Pos) /*!< GPIO_PORT DIR: DIRP2 Mask */ #define GPIO_PORT_DIR_DIRP3_Pos 3 /*!< GPIO_PORT DIR: DIRP3 Position */ #define GPIO_PORT_DIR_DIRP3_Msk (0x01UL << GPIO_PORT_DIR_DIRP3_Pos) /*!< GPIO_PORT DIR: DIRP3 Mask */ #define GPIO_PORT_DIR_DIRP4_Pos 4 /*!< GPIO_PORT DIR: DIRP4 Position */ #define GPIO_PORT_DIR_DIRP4_Msk (0x01UL << GPIO_PORT_DIR_DIRP4_Pos) /*!< GPIO_PORT DIR: DIRP4 Mask */ #define GPIO_PORT_DIR_DIRP5_Pos 5 /*!< GPIO_PORT DIR: DIRP5 Position */ #define GPIO_PORT_DIR_DIRP5_Msk (0x01UL << GPIO_PORT_DIR_DIRP5_Pos) /*!< GPIO_PORT DIR: DIRP5 Mask */ #define GPIO_PORT_DIR_DIRP6_Pos 6 /*!< GPIO_PORT DIR: DIRP6 Position */ #define GPIO_PORT_DIR_DIRP6_Msk (0x01UL << GPIO_PORT_DIR_DIRP6_Pos) /*!< GPIO_PORT DIR: DIRP6 Mask */ #define GPIO_PORT_DIR_DIRP7_Pos 7 /*!< GPIO_PORT DIR: DIRP7 Position */ #define GPIO_PORT_DIR_DIRP7_Msk (0x01UL << GPIO_PORT_DIR_DIRP7_Pos) /*!< GPIO_PORT DIR: DIRP7 Mask */ #define GPIO_PORT_DIR_DIRP8_Pos 8 /*!< GPIO_PORT DIR: DIRP8 Position */ #define GPIO_PORT_DIR_DIRP8_Msk (0x01UL << GPIO_PORT_DIR_DIRP8_Pos) /*!< GPIO_PORT DIR: DIRP8 Mask */ #define GPIO_PORT_DIR_DIRP9_Pos 9 /*!< GPIO_PORT DIR: DIRP9 Position */ #define GPIO_PORT_DIR_DIRP9_Msk (0x01UL << GPIO_PORT_DIR_DIRP9_Pos) /*!< GPIO_PORT DIR: DIRP9 Mask */ #define GPIO_PORT_DIR_DIRP10_Pos 10 /*!< GPIO_PORT DIR: DIRP10 Position */ #define GPIO_PORT_DIR_DIRP10_Msk (0x01UL << GPIO_PORT_DIR_DIRP10_Pos) /*!< GPIO_PORT DIR: DIRP10 Mask */ #define GPIO_PORT_DIR_DIRP11_Pos 11 /*!< GPIO_PORT DIR: DIRP11 Position */ #define GPIO_PORT_DIR_DIRP11_Msk (0x01UL << GPIO_PORT_DIR_DIRP11_Pos) /*!< GPIO_PORT DIR: DIRP11 Mask */ #define GPIO_PORT_DIR_DIRP12_Pos 12 /*!< GPIO_PORT DIR: DIRP12 Position */ #define GPIO_PORT_DIR_DIRP12_Msk (0x01UL << GPIO_PORT_DIR_DIRP12_Pos) /*!< GPIO_PORT DIR: DIRP12 Mask */ #define GPIO_PORT_DIR_DIRP13_Pos 13 /*!< GPIO_PORT DIR: DIRP13 Position */ #define GPIO_PORT_DIR_DIRP13_Msk (0x01UL << GPIO_PORT_DIR_DIRP13_Pos) /*!< GPIO_PORT DIR: DIRP13 Mask */ #define GPIO_PORT_DIR_DIRP14_Pos 14 /*!< GPIO_PORT DIR: DIRP14 Position */ #define GPIO_PORT_DIR_DIRP14_Msk (0x01UL << GPIO_PORT_DIR_DIRP14_Pos) /*!< GPIO_PORT DIR: DIRP14 Mask */ #define GPIO_PORT_DIR_DIRP15_Pos 15 /*!< GPIO_PORT DIR: DIRP15 Position */ #define GPIO_PORT_DIR_DIRP15_Msk (0x01UL << GPIO_PORT_DIR_DIRP15_Pos) /*!< GPIO_PORT DIR: DIRP15 Mask */ #define GPIO_PORT_DIR_DIRP16_Pos 16 /*!< GPIO_PORT DIR: DIRP16 Position */ #define GPIO_PORT_DIR_DIRP16_Msk (0x01UL << GPIO_PORT_DIR_DIRP16_Pos) /*!< GPIO_PORT DIR: DIRP16 Mask */ #define GPIO_PORT_DIR_DIRP17_Pos 17 /*!< GPIO_PORT DIR: DIRP17 Position */ #define GPIO_PORT_DIR_DIRP17_Msk (0x01UL << GPIO_PORT_DIR_DIRP17_Pos) /*!< GPIO_PORT DIR: DIRP17 Mask */ #define GPIO_PORT_DIR_DIRP18_Pos 18 /*!< GPIO_PORT DIR: DIRP18 Position */ #define GPIO_PORT_DIR_DIRP18_Msk (0x01UL << GPIO_PORT_DIR_DIRP18_Pos) /*!< GPIO_PORT DIR: DIRP18 Mask */ #define GPIO_PORT_DIR_DIRP19_Pos 19 /*!< GPIO_PORT DIR: DIRP19 Position */ #define GPIO_PORT_DIR_DIRP19_Msk (0x01UL << GPIO_PORT_DIR_DIRP19_Pos) /*!< GPIO_PORT DIR: DIRP19 Mask */ #define GPIO_PORT_DIR_DIRP20_Pos 20 /*!< GPIO_PORT DIR: DIRP20 Position */ #define GPIO_PORT_DIR_DIRP20_Msk (0x01UL << GPIO_PORT_DIR_DIRP20_Pos) /*!< GPIO_PORT DIR: DIRP20 Mask */ #define GPIO_PORT_DIR_DIRP21_Pos 21 /*!< GPIO_PORT DIR: DIRP21 Position */ #define GPIO_PORT_DIR_DIRP21_Msk (0x01UL << GPIO_PORT_DIR_DIRP21_Pos) /*!< GPIO_PORT DIR: DIRP21 Mask */ #define GPIO_PORT_DIR_DIRP22_Pos 22 /*!< GPIO_PORT DIR: DIRP22 Position */ #define GPIO_PORT_DIR_DIRP22_Msk (0x01UL << GPIO_PORT_DIR_DIRP22_Pos) /*!< GPIO_PORT DIR: DIRP22 Mask */ #define GPIO_PORT_DIR_DIRP23_Pos 23 /*!< GPIO_PORT DIR: DIRP23 Position */ #define GPIO_PORT_DIR_DIRP23_Msk (0x01UL << GPIO_PORT_DIR_DIRP23_Pos) /*!< GPIO_PORT DIR: DIRP23 Mask */ #define GPIO_PORT_DIR_DIRP24_Pos 24 /*!< GPIO_PORT DIR: DIRP24 Position */ #define GPIO_PORT_DIR_DIRP24_Msk (0x01UL << GPIO_PORT_DIR_DIRP24_Pos) /*!< GPIO_PORT DIR: DIRP24 Mask */ #define GPIO_PORT_DIR_DIRP25_Pos 25 /*!< GPIO_PORT DIR: DIRP25 Position */ #define GPIO_PORT_DIR_DIRP25_Msk (0x01UL << GPIO_PORT_DIR_DIRP25_Pos) /*!< GPIO_PORT DIR: DIRP25 Mask */ #define GPIO_PORT_DIR_DIRP26_Pos 26 /*!< GPIO_PORT DIR: DIRP26 Position */ #define GPIO_PORT_DIR_DIRP26_Msk (0x01UL << GPIO_PORT_DIR_DIRP26_Pos) /*!< GPIO_PORT DIR: DIRP26 Mask */ #define GPIO_PORT_DIR_DIRP27_Pos 27 /*!< GPIO_PORT DIR: DIRP27 Position */ #define GPIO_PORT_DIR_DIRP27_Msk (0x01UL << GPIO_PORT_DIR_DIRP27_Pos) /*!< GPIO_PORT DIR: DIRP27 Mask */ #define GPIO_PORT_DIR_DIRP28_Pos 28 /*!< GPIO_PORT DIR: DIRP28 Position */ #define GPIO_PORT_DIR_DIRP28_Msk (0x01UL << GPIO_PORT_DIR_DIRP28_Pos) /*!< GPIO_PORT DIR: DIRP28 Mask */ #define GPIO_PORT_DIR_DIRP29_Pos 29 /*!< GPIO_PORT DIR: DIRP29 Position */ #define GPIO_PORT_DIR_DIRP29_Msk (0x01UL << GPIO_PORT_DIR_DIRP29_Pos) /*!< GPIO_PORT DIR: DIRP29 Mask */ #define GPIO_PORT_DIR_DIRP30_Pos 30 /*!< GPIO_PORT DIR: DIRP30 Position */ #define GPIO_PORT_DIR_DIRP30_Msk (0x01UL << GPIO_PORT_DIR_DIRP30_Pos) /*!< GPIO_PORT DIR: DIRP30 Mask */ #define GPIO_PORT_DIR_DIRP31_Pos 31 /*!< GPIO_PORT DIR: DIRP31 Position */ #define GPIO_PORT_DIR_DIRP31_Msk (0x01UL << GPIO_PORT_DIR_DIRP31_Pos) /*!< GPIO_PORT DIR: DIRP31 Mask */ /* ------------------------------- GPIO_PORT_MASK ------------------------------- */ #define GPIO_PORT_MASK_MASKP0_Pos 0 /*!< GPIO_PORT MASK: MASKP0 Position */ #define GPIO_PORT_MASK_MASKP0_Msk (0x01UL << GPIO_PORT_MASK_MASKP0_Pos) /*!< GPIO_PORT MASK: MASKP0 Mask */ #define GPIO_PORT_MASK_MASKP1_Pos 1 /*!< GPIO_PORT MASK: MASKP1 Position */ #define GPIO_PORT_MASK_MASKP1_Msk (0x01UL << GPIO_PORT_MASK_MASKP1_Pos) /*!< GPIO_PORT MASK: MASKP1 Mask */ #define GPIO_PORT_MASK_MASKP2_Pos 2 /*!< GPIO_PORT MASK: MASKP2 Position */ #define GPIO_PORT_MASK_MASKP2_Msk (0x01UL << GPIO_PORT_MASK_MASKP2_Pos) /*!< GPIO_PORT MASK: MASKP2 Mask */ #define GPIO_PORT_MASK_MASKP3_Pos 3 /*!< GPIO_PORT MASK: MASKP3 Position */ #define GPIO_PORT_MASK_MASKP3_Msk (0x01UL << GPIO_PORT_MASK_MASKP3_Pos) /*!< GPIO_PORT MASK: MASKP3 Mask */ #define GPIO_PORT_MASK_MASKP4_Pos 4 /*!< GPIO_PORT MASK: MASKP4 Position */ #define GPIO_PORT_MASK_MASKP4_Msk (0x01UL << GPIO_PORT_MASK_MASKP4_Pos) /*!< GPIO_PORT MASK: MASKP4 Mask */ #define GPIO_PORT_MASK_MASKP5_Pos 5 /*!< GPIO_PORT MASK: MASKP5 Position */ #define GPIO_PORT_MASK_MASKP5_Msk (0x01UL << GPIO_PORT_MASK_MASKP5_Pos) /*!< GPIO_PORT MASK: MASKP5 Mask */ #define GPIO_PORT_MASK_MASKP6_Pos 6 /*!< GPIO_PORT MASK: MASKP6 Position */ #define GPIO_PORT_MASK_MASKP6_Msk (0x01UL << GPIO_PORT_MASK_MASKP6_Pos) /*!< GPIO_PORT MASK: MASKP6 Mask */ #define GPIO_PORT_MASK_MASKP7_Pos 7 /*!< GPIO_PORT MASK: MASKP7 Position */ #define GPIO_PORT_MASK_MASKP7_Msk (0x01UL << GPIO_PORT_MASK_MASKP7_Pos) /*!< GPIO_PORT MASK: MASKP7 Mask */ #define GPIO_PORT_MASK_MASKP8_Pos 8 /*!< GPIO_PORT MASK: MASKP8 Position */ #define GPIO_PORT_MASK_MASKP8_Msk (0x01UL << GPIO_PORT_MASK_MASKP8_Pos) /*!< GPIO_PORT MASK: MASKP8 Mask */ #define GPIO_PORT_MASK_MASKP9_Pos 9 /*!< GPIO_PORT MASK: MASKP9 Position */ #define GPIO_PORT_MASK_MASKP9_Msk (0x01UL << GPIO_PORT_MASK_MASKP9_Pos) /*!< GPIO_PORT MASK: MASKP9 Mask */ #define GPIO_PORT_MASK_MASKP10_Pos 10 /*!< GPIO_PORT MASK: MASKP10 Position */ #define GPIO_PORT_MASK_MASKP10_Msk (0x01UL << GPIO_PORT_MASK_MASKP10_Pos) /*!< GPIO_PORT MASK: MASKP10 Mask */ #define GPIO_PORT_MASK_MASKP11_Pos 11 /*!< GPIO_PORT MASK: MASKP11 Position */ #define GPIO_PORT_MASK_MASKP11_Msk (0x01UL << GPIO_PORT_MASK_MASKP11_Pos) /*!< GPIO_PORT MASK: MASKP11 Mask */ #define GPIO_PORT_MASK_MASKP12_Pos 12 /*!< GPIO_PORT MASK: MASKP12 Position */ #define GPIO_PORT_MASK_MASKP12_Msk (0x01UL << GPIO_PORT_MASK_MASKP12_Pos) /*!< GPIO_PORT MASK: MASKP12 Mask */ #define GPIO_PORT_MASK_MASKP13_Pos 13 /*!< GPIO_PORT MASK: MASKP13 Position */ #define GPIO_PORT_MASK_MASKP13_Msk (0x01UL << GPIO_PORT_MASK_MASKP13_Pos) /*!< GPIO_PORT MASK: MASKP13 Mask */ #define GPIO_PORT_MASK_MASKP14_Pos 14 /*!< GPIO_PORT MASK: MASKP14 Position */ #define GPIO_PORT_MASK_MASKP14_Msk (0x01UL << GPIO_PORT_MASK_MASKP14_Pos) /*!< GPIO_PORT MASK: MASKP14 Mask */ #define GPIO_PORT_MASK_MASKP15_Pos 15 /*!< GPIO_PORT MASK: MASKP15 Position */ #define GPIO_PORT_MASK_MASKP15_Msk (0x01UL << GPIO_PORT_MASK_MASKP15_Pos) /*!< GPIO_PORT MASK: MASKP15 Mask */ #define GPIO_PORT_MASK_MASKP16_Pos 16 /*!< GPIO_PORT MASK: MASKP16 Position */ #define GPIO_PORT_MASK_MASKP16_Msk (0x01UL << GPIO_PORT_MASK_MASKP16_Pos) /*!< GPIO_PORT MASK: MASKP16 Mask */ #define GPIO_PORT_MASK_MASKP17_Pos 17 /*!< GPIO_PORT MASK: MASKP17 Position */ #define GPIO_PORT_MASK_MASKP17_Msk (0x01UL << GPIO_PORT_MASK_MASKP17_Pos) /*!< GPIO_PORT MASK: MASKP17 Mask */ #define GPIO_PORT_MASK_MASKP18_Pos 18 /*!< GPIO_PORT MASK: MASKP18 Position */ #define GPIO_PORT_MASK_MASKP18_Msk (0x01UL << GPIO_PORT_MASK_MASKP18_Pos) /*!< GPIO_PORT MASK: MASKP18 Mask */ #define GPIO_PORT_MASK_MASKP19_Pos 19 /*!< GPIO_PORT MASK: MASKP19 Position */ #define GPIO_PORT_MASK_MASKP19_Msk (0x01UL << GPIO_PORT_MASK_MASKP19_Pos) /*!< GPIO_PORT MASK: MASKP19 Mask */ #define GPIO_PORT_MASK_MASKP20_Pos 20 /*!< GPIO_PORT MASK: MASKP20 Position */ #define GPIO_PORT_MASK_MASKP20_Msk (0x01UL << GPIO_PORT_MASK_MASKP20_Pos) /*!< GPIO_PORT MASK: MASKP20 Mask */ #define GPIO_PORT_MASK_MASKP21_Pos 21 /*!< GPIO_PORT MASK: MASKP21 Position */ #define GPIO_PORT_MASK_MASKP21_Msk (0x01UL << GPIO_PORT_MASK_MASKP21_Pos) /*!< GPIO_PORT MASK: MASKP21 Mask */ #define GPIO_PORT_MASK_MASKP22_Pos 22 /*!< GPIO_PORT MASK: MASKP22 Position */ #define GPIO_PORT_MASK_MASKP22_Msk (0x01UL << GPIO_PORT_MASK_MASKP22_Pos) /*!< GPIO_PORT MASK: MASKP22 Mask */ #define GPIO_PORT_MASK_MASKP23_Pos 23 /*!< GPIO_PORT MASK: MASKP23 Position */ #define GPIO_PORT_MASK_MASKP23_Msk (0x01UL << GPIO_PORT_MASK_MASKP23_Pos) /*!< GPIO_PORT MASK: MASKP23 Mask */ #define GPIO_PORT_MASK_MASKP24_Pos 24 /*!< GPIO_PORT MASK: MASKP24 Position */ #define GPIO_PORT_MASK_MASKP24_Msk (0x01UL << GPIO_PORT_MASK_MASKP24_Pos) /*!< GPIO_PORT MASK: MASKP24 Mask */ #define GPIO_PORT_MASK_MASKP25_Pos 25 /*!< GPIO_PORT MASK: MASKP25 Position */ #define GPIO_PORT_MASK_MASKP25_Msk (0x01UL << GPIO_PORT_MASK_MASKP25_Pos) /*!< GPIO_PORT MASK: MASKP25 Mask */ #define GPIO_PORT_MASK_MASKP26_Pos 26 /*!< GPIO_PORT MASK: MASKP26 Position */ #define GPIO_PORT_MASK_MASKP26_Msk (0x01UL << GPIO_PORT_MASK_MASKP26_Pos) /*!< GPIO_PORT MASK: MASKP26 Mask */ #define GPIO_PORT_MASK_MASKP27_Pos 27 /*!< GPIO_PORT MASK: MASKP27 Position */ #define GPIO_PORT_MASK_MASKP27_Msk (0x01UL << GPIO_PORT_MASK_MASKP27_Pos) /*!< GPIO_PORT MASK: MASKP27 Mask */ #define GPIO_PORT_MASK_MASKP28_Pos 28 /*!< GPIO_PORT MASK: MASKP28 Position */ #define GPIO_PORT_MASK_MASKP28_Msk (0x01UL << GPIO_PORT_MASK_MASKP28_Pos) /*!< GPIO_PORT MASK: MASKP28 Mask */ #define GPIO_PORT_MASK_MASKP29_Pos 29 /*!< GPIO_PORT MASK: MASKP29 Position */ #define GPIO_PORT_MASK_MASKP29_Msk (0x01UL << GPIO_PORT_MASK_MASKP29_Pos) /*!< GPIO_PORT MASK: MASKP29 Mask */ #define GPIO_PORT_MASK_MASKP30_Pos 30 /*!< GPIO_PORT MASK: MASKP30 Position */ #define GPIO_PORT_MASK_MASKP30_Msk (0x01UL << GPIO_PORT_MASK_MASKP30_Pos) /*!< GPIO_PORT MASK: MASKP30 Mask */ #define GPIO_PORT_MASK_MASKP31_Pos 31 /*!< GPIO_PORT MASK: MASKP31 Position */ #define GPIO_PORT_MASK_MASKP31_Msk (0x01UL << GPIO_PORT_MASK_MASKP31_Pos) /*!< GPIO_PORT MASK: MASKP31 Mask */ /* -------------------------------- GPIO_PORT_PIN ------------------------------- */ #define GPIO_PORT_PIN_PORT0_Pos 0 /*!< GPIO_PORT PIN: PORT0 Position */ #define GPIO_PORT_PIN_PORT0_Msk (0x01UL << GPIO_PORT_PIN_PORT0_Pos) /*!< GPIO_PORT PIN: PORT0 Mask */ #define GPIO_PORT_PIN_PORT1_Pos 1 /*!< GPIO_PORT PIN: PORT1 Position */ #define GPIO_PORT_PIN_PORT1_Msk (0x01UL << GPIO_PORT_PIN_PORT1_Pos) /*!< GPIO_PORT PIN: PORT1 Mask */ #define GPIO_PORT_PIN_PORT2_Pos 2 /*!< GPIO_PORT PIN: PORT2 Position */ #define GPIO_PORT_PIN_PORT2_Msk (0x01UL << GPIO_PORT_PIN_PORT2_Pos) /*!< GPIO_PORT PIN: PORT2 Mask */ #define GPIO_PORT_PIN_PORT3_Pos 3 /*!< GPIO_PORT PIN: PORT3 Position */ #define GPIO_PORT_PIN_PORT3_Msk (0x01UL << GPIO_PORT_PIN_PORT3_Pos) /*!< GPIO_PORT PIN: PORT3 Mask */ #define GPIO_PORT_PIN_PORT4_Pos 4 /*!< GPIO_PORT PIN: PORT4 Position */ #define GPIO_PORT_PIN_PORT4_Msk (0x01UL << GPIO_PORT_PIN_PORT4_Pos) /*!< GPIO_PORT PIN: PORT4 Mask */ #define GPIO_PORT_PIN_PORT5_Pos 5 /*!< GPIO_PORT PIN: PORT5 Position */ #define GPIO_PORT_PIN_PORT5_Msk (0x01UL << GPIO_PORT_PIN_PORT5_Pos) /*!< GPIO_PORT PIN: PORT5 Mask */ #define GPIO_PORT_PIN_PORT6_Pos 6 /*!< GPIO_PORT PIN: PORT6 Position */ #define GPIO_PORT_PIN_PORT6_Msk (0x01UL << GPIO_PORT_PIN_PORT6_Pos) /*!< GPIO_PORT PIN: PORT6 Mask */ #define GPIO_PORT_PIN_PORT7_Pos 7 /*!< GPIO_PORT PIN: PORT7 Position */ #define GPIO_PORT_PIN_PORT7_Msk (0x01UL << GPIO_PORT_PIN_PORT7_Pos) /*!< GPIO_PORT PIN: PORT7 Mask */ #define GPIO_PORT_PIN_PORT8_Pos 8 /*!< GPIO_PORT PIN: PORT8 Position */ #define GPIO_PORT_PIN_PORT8_Msk (0x01UL << GPIO_PORT_PIN_PORT8_Pos) /*!< GPIO_PORT PIN: PORT8 Mask */ #define GPIO_PORT_PIN_PORT9_Pos 9 /*!< GPIO_PORT PIN: PORT9 Position */ #define GPIO_PORT_PIN_PORT9_Msk (0x01UL << GPIO_PORT_PIN_PORT9_Pos) /*!< GPIO_PORT PIN: PORT9 Mask */ #define GPIO_PORT_PIN_PORT10_Pos 10 /*!< GPIO_PORT PIN: PORT10 Position */ #define GPIO_PORT_PIN_PORT10_Msk (0x01UL << GPIO_PORT_PIN_PORT10_Pos) /*!< GPIO_PORT PIN: PORT10 Mask */ #define GPIO_PORT_PIN_PORT11_Pos 11 /*!< GPIO_PORT PIN: PORT11 Position */ #define GPIO_PORT_PIN_PORT11_Msk (0x01UL << GPIO_PORT_PIN_PORT11_Pos) /*!< GPIO_PORT PIN: PORT11 Mask */ #define GPIO_PORT_PIN_PORT12_Pos 12 /*!< GPIO_PORT PIN: PORT12 Position */ #define GPIO_PORT_PIN_PORT12_Msk (0x01UL << GPIO_PORT_PIN_PORT12_Pos) /*!< GPIO_PORT PIN: PORT12 Mask */ #define GPIO_PORT_PIN_PORT13_Pos 13 /*!< GPIO_PORT PIN: PORT13 Position */ #define GPIO_PORT_PIN_PORT13_Msk (0x01UL << GPIO_PORT_PIN_PORT13_Pos) /*!< GPIO_PORT PIN: PORT13 Mask */ #define GPIO_PORT_PIN_PORT14_Pos 14 /*!< GPIO_PORT PIN: PORT14 Position */ #define GPIO_PORT_PIN_PORT14_Msk (0x01UL << GPIO_PORT_PIN_PORT14_Pos) /*!< GPIO_PORT PIN: PORT14 Mask */ #define GPIO_PORT_PIN_PORT15_Pos 15 /*!< GPIO_PORT PIN: PORT15 Position */ #define GPIO_PORT_PIN_PORT15_Msk (0x01UL << GPIO_PORT_PIN_PORT15_Pos) /*!< GPIO_PORT PIN: PORT15 Mask */ #define GPIO_PORT_PIN_PORT16_Pos 16 /*!< GPIO_PORT PIN: PORT16 Position */ #define GPIO_PORT_PIN_PORT16_Msk (0x01UL << GPIO_PORT_PIN_PORT16_Pos) /*!< GPIO_PORT PIN: PORT16 Mask */ #define GPIO_PORT_PIN_PORT17_Pos 17 /*!< GPIO_PORT PIN: PORT17 Position */ #define GPIO_PORT_PIN_PORT17_Msk (0x01UL << GPIO_PORT_PIN_PORT17_Pos) /*!< GPIO_PORT PIN: PORT17 Mask */ #define GPIO_PORT_PIN_PORT18_Pos 18 /*!< GPIO_PORT PIN: PORT18 Position */ #define GPIO_PORT_PIN_PORT18_Msk (0x01UL << GPIO_PORT_PIN_PORT18_Pos) /*!< GPIO_PORT PIN: PORT18 Mask */ #define GPIO_PORT_PIN_PORT19_Pos 19 /*!< GPIO_PORT PIN: PORT19 Position */ #define GPIO_PORT_PIN_PORT19_Msk (0x01UL << GPIO_PORT_PIN_PORT19_Pos) /*!< GPIO_PORT PIN: PORT19 Mask */ #define GPIO_PORT_PIN_PORT20_Pos 20 /*!< GPIO_PORT PIN: PORT20 Position */ #define GPIO_PORT_PIN_PORT20_Msk (0x01UL << GPIO_PORT_PIN_PORT20_Pos) /*!< GPIO_PORT PIN: PORT20 Mask */ #define GPIO_PORT_PIN_PORT21_Pos 21 /*!< GPIO_PORT PIN: PORT21 Position */ #define GPIO_PORT_PIN_PORT21_Msk (0x01UL << GPIO_PORT_PIN_PORT21_Pos) /*!< GPIO_PORT PIN: PORT21 Mask */ #define GPIO_PORT_PIN_PORT22_Pos 22 /*!< GPIO_PORT PIN: PORT22 Position */ #define GPIO_PORT_PIN_PORT22_Msk (0x01UL << GPIO_PORT_PIN_PORT22_Pos) /*!< GPIO_PORT PIN: PORT22 Mask */ #define GPIO_PORT_PIN_PORT23_Pos 23 /*!< GPIO_PORT PIN: PORT23 Position */ #define GPIO_PORT_PIN_PORT23_Msk (0x01UL << GPIO_PORT_PIN_PORT23_Pos) /*!< GPIO_PORT PIN: PORT23 Mask */ #define GPIO_PORT_PIN_PORT24_Pos 24 /*!< GPIO_PORT PIN: PORT24 Position */ #define GPIO_PORT_PIN_PORT24_Msk (0x01UL << GPIO_PORT_PIN_PORT24_Pos) /*!< GPIO_PORT PIN: PORT24 Mask */ #define GPIO_PORT_PIN_PORT25_Pos 25 /*!< GPIO_PORT PIN: PORT25 Position */ #define GPIO_PORT_PIN_PORT25_Msk (0x01UL << GPIO_PORT_PIN_PORT25_Pos) /*!< GPIO_PORT PIN: PORT25 Mask */ #define GPIO_PORT_PIN_PORT26_Pos 26 /*!< GPIO_PORT PIN: PORT26 Position */ #define GPIO_PORT_PIN_PORT26_Msk (0x01UL << GPIO_PORT_PIN_PORT26_Pos) /*!< GPIO_PORT PIN: PORT26 Mask */ #define GPIO_PORT_PIN_PORT27_Pos 27 /*!< GPIO_PORT PIN: PORT27 Position */ #define GPIO_PORT_PIN_PORT27_Msk (0x01UL << GPIO_PORT_PIN_PORT27_Pos) /*!< GPIO_PORT PIN: PORT27 Mask */ #define GPIO_PORT_PIN_PORT28_Pos 28 /*!< GPIO_PORT PIN: PORT28 Position */ #define GPIO_PORT_PIN_PORT28_Msk (0x01UL << GPIO_PORT_PIN_PORT28_Pos) /*!< GPIO_PORT PIN: PORT28 Mask */ #define GPIO_PORT_PIN_PORT29_Pos 29 /*!< GPIO_PORT PIN: PORT29 Position */ #define GPIO_PORT_PIN_PORT29_Msk (0x01UL << GPIO_PORT_PIN_PORT29_Pos) /*!< GPIO_PORT PIN: PORT29 Mask */ #define GPIO_PORT_PIN_PORT30_Pos 30 /*!< GPIO_PORT PIN: PORT30 Position */ #define GPIO_PORT_PIN_PORT30_Msk (0x01UL << GPIO_PORT_PIN_PORT30_Pos) /*!< GPIO_PORT PIN: PORT30 Mask */ #define GPIO_PORT_PIN_PORT31_Pos 31 /*!< GPIO_PORT PIN: PORT31 Position */ #define GPIO_PORT_PIN_PORT31_Msk (0x01UL << GPIO_PORT_PIN_PORT31_Pos) /*!< GPIO_PORT PIN: PORT31 Mask */ /* ------------------------------- GPIO_PORT_MPIN ------------------------------- */ #define GPIO_PORT_MPIN_MPORTP0_Pos 0 /*!< GPIO_PORT MPIN: MPORTP0 Position */ #define GPIO_PORT_MPIN_MPORTP0_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP0_Pos) /*!< GPIO_PORT MPIN: MPORTP0 Mask */ #define GPIO_PORT_MPIN_MPORTP1_Pos 1 /*!< GPIO_PORT MPIN: MPORTP1 Position */ #define GPIO_PORT_MPIN_MPORTP1_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP1_Pos) /*!< GPIO_PORT MPIN: MPORTP1 Mask */ #define GPIO_PORT_MPIN_MPORTP2_Pos 2 /*!< GPIO_PORT MPIN: MPORTP2 Position */ #define GPIO_PORT_MPIN_MPORTP2_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP2_Pos) /*!< GPIO_PORT MPIN: MPORTP2 Mask */ #define GPIO_PORT_MPIN_MPORTP3_Pos 3 /*!< GPIO_PORT MPIN: MPORTP3 Position */ #define GPIO_PORT_MPIN_MPORTP3_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP3_Pos) /*!< GPIO_PORT MPIN: MPORTP3 Mask */ #define GPIO_PORT_MPIN_MPORTP4_Pos 4 /*!< GPIO_PORT MPIN: MPORTP4 Position */ #define GPIO_PORT_MPIN_MPORTP4_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP4_Pos) /*!< GPIO_PORT MPIN: MPORTP4 Mask */ #define GPIO_PORT_MPIN_MPORTP5_Pos 5 /*!< GPIO_PORT MPIN: MPORTP5 Position */ #define GPIO_PORT_MPIN_MPORTP5_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP5_Pos) /*!< GPIO_PORT MPIN: MPORTP5 Mask */ #define GPIO_PORT_MPIN_MPORTP6_Pos 6 /*!< GPIO_PORT MPIN: MPORTP6 Position */ #define GPIO_PORT_MPIN_MPORTP6_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP6_Pos) /*!< GPIO_PORT MPIN: MPORTP6 Mask */ #define GPIO_PORT_MPIN_MPORTP7_Pos 7 /*!< GPIO_PORT MPIN: MPORTP7 Position */ #define GPIO_PORT_MPIN_MPORTP7_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP7_Pos) /*!< GPIO_PORT MPIN: MPORTP7 Mask */ #define GPIO_PORT_MPIN_MPORTP8_Pos 8 /*!< GPIO_PORT MPIN: MPORTP8 Position */ #define GPIO_PORT_MPIN_MPORTP8_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP8_Pos) /*!< GPIO_PORT MPIN: MPORTP8 Mask */ #define GPIO_PORT_MPIN_MPORTP9_Pos 9 /*!< GPIO_PORT MPIN: MPORTP9 Position */ #define GPIO_PORT_MPIN_MPORTP9_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP9_Pos) /*!< GPIO_PORT MPIN: MPORTP9 Mask */ #define GPIO_PORT_MPIN_MPORTP10_Pos 10 /*!< GPIO_PORT MPIN: MPORTP10 Position */ #define GPIO_PORT_MPIN_MPORTP10_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP10_Pos) /*!< GPIO_PORT MPIN: MPORTP10 Mask */ #define GPIO_PORT_MPIN_MPORTP11_Pos 11 /*!< GPIO_PORT MPIN: MPORTP11 Position */ #define GPIO_PORT_MPIN_MPORTP11_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP11_Pos) /*!< GPIO_PORT MPIN: MPORTP11 Mask */ #define GPIO_PORT_MPIN_MPORTP12_Pos 12 /*!< GPIO_PORT MPIN: MPORTP12 Position */ #define GPIO_PORT_MPIN_MPORTP12_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP12_Pos) /*!< GPIO_PORT MPIN: MPORTP12 Mask */ #define GPIO_PORT_MPIN_MPORTP13_Pos 13 /*!< GPIO_PORT MPIN: MPORTP13 Position */ #define GPIO_PORT_MPIN_MPORTP13_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP13_Pos) /*!< GPIO_PORT MPIN: MPORTP13 Mask */ #define GPIO_PORT_MPIN_MPORTP14_Pos 14 /*!< GPIO_PORT MPIN: MPORTP14 Position */ #define GPIO_PORT_MPIN_MPORTP14_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP14_Pos) /*!< GPIO_PORT MPIN: MPORTP14 Mask */ #define GPIO_PORT_MPIN_MPORTP15_Pos 15 /*!< GPIO_PORT MPIN: MPORTP15 Position */ #define GPIO_PORT_MPIN_MPORTP15_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP15_Pos) /*!< GPIO_PORT MPIN: MPORTP15 Mask */ #define GPIO_PORT_MPIN_MPORTP16_Pos 16 /*!< GPIO_PORT MPIN: MPORTP16 Position */ #define GPIO_PORT_MPIN_MPORTP16_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP16_Pos) /*!< GPIO_PORT MPIN: MPORTP16 Mask */ #define GPIO_PORT_MPIN_MPORTP17_Pos 17 /*!< GPIO_PORT MPIN: MPORTP17 Position */ #define GPIO_PORT_MPIN_MPORTP17_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP17_Pos) /*!< GPIO_PORT MPIN: MPORTP17 Mask */ #define GPIO_PORT_MPIN_MPORTP18_Pos 18 /*!< GPIO_PORT MPIN: MPORTP18 Position */ #define GPIO_PORT_MPIN_MPORTP18_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP18_Pos) /*!< GPIO_PORT MPIN: MPORTP18 Mask */ #define GPIO_PORT_MPIN_MPORTP19_Pos 19 /*!< GPIO_PORT MPIN: MPORTP19 Position */ #define GPIO_PORT_MPIN_MPORTP19_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP19_Pos) /*!< GPIO_PORT MPIN: MPORTP19 Mask */ #define GPIO_PORT_MPIN_MPORTP20_Pos 20 /*!< GPIO_PORT MPIN: MPORTP20 Position */ #define GPIO_PORT_MPIN_MPORTP20_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP20_Pos) /*!< GPIO_PORT MPIN: MPORTP20 Mask */ #define GPIO_PORT_MPIN_MPORTP21_Pos 21 /*!< GPIO_PORT MPIN: MPORTP21 Position */ #define GPIO_PORT_MPIN_MPORTP21_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP21_Pos) /*!< GPIO_PORT MPIN: MPORTP21 Mask */ #define GPIO_PORT_MPIN_MPORTP22_Pos 22 /*!< GPIO_PORT MPIN: MPORTP22 Position */ #define GPIO_PORT_MPIN_MPORTP22_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP22_Pos) /*!< GPIO_PORT MPIN: MPORTP22 Mask */ #define GPIO_PORT_MPIN_MPORTP23_Pos 23 /*!< GPIO_PORT MPIN: MPORTP23 Position */ #define GPIO_PORT_MPIN_MPORTP23_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP23_Pos) /*!< GPIO_PORT MPIN: MPORTP23 Mask */ #define GPIO_PORT_MPIN_MPORTP24_Pos 24 /*!< GPIO_PORT MPIN: MPORTP24 Position */ #define GPIO_PORT_MPIN_MPORTP24_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP24_Pos) /*!< GPIO_PORT MPIN: MPORTP24 Mask */ #define GPIO_PORT_MPIN_MPORTP25_Pos 25 /*!< GPIO_PORT MPIN: MPORTP25 Position */ #define GPIO_PORT_MPIN_MPORTP25_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP25_Pos) /*!< GPIO_PORT MPIN: MPORTP25 Mask */ #define GPIO_PORT_MPIN_MPORTP26_Pos 26 /*!< GPIO_PORT MPIN: MPORTP26 Position */ #define GPIO_PORT_MPIN_MPORTP26_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP26_Pos) /*!< GPIO_PORT MPIN: MPORTP26 Mask */ #define GPIO_PORT_MPIN_MPORTP27_Pos 27 /*!< GPIO_PORT MPIN: MPORTP27 Position */ #define GPIO_PORT_MPIN_MPORTP27_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP27_Pos) /*!< GPIO_PORT MPIN: MPORTP27 Mask */ #define GPIO_PORT_MPIN_MPORTP28_Pos 28 /*!< GPIO_PORT MPIN: MPORTP28 Position */ #define GPIO_PORT_MPIN_MPORTP28_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP28_Pos) /*!< GPIO_PORT MPIN: MPORTP28 Mask */ #define GPIO_PORT_MPIN_MPORTP29_Pos 29 /*!< GPIO_PORT MPIN: MPORTP29 Position */ #define GPIO_PORT_MPIN_MPORTP29_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP29_Pos) /*!< GPIO_PORT MPIN: MPORTP29 Mask */ #define GPIO_PORT_MPIN_MPORTP30_Pos 30 /*!< GPIO_PORT MPIN: MPORTP30 Position */ #define GPIO_PORT_MPIN_MPORTP30_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP30_Pos) /*!< GPIO_PORT MPIN: MPORTP30 Mask */ #define GPIO_PORT_MPIN_MPORTP31_Pos 31 /*!< GPIO_PORT MPIN: MPORTP31 Position */ #define GPIO_PORT_MPIN_MPORTP31_Msk (0x01UL << GPIO_PORT_MPIN_MPORTP31_Pos) /*!< GPIO_PORT MPIN: MPORTP31 Mask */ /* -------------------------------- GPIO_PORT_SET ------------------------------- */ #define GPIO_PORT_SET_SETP0_Pos 0 /*!< GPIO_PORT SET: SETP0 Position */ #define GPIO_PORT_SET_SETP0_Msk (0x01UL << GPIO_PORT_SET_SETP0_Pos) /*!< GPIO_PORT SET: SETP0 Mask */ #define GPIO_PORT_SET_SETP1_Pos 1 /*!< GPIO_PORT SET: SETP1 Position */ #define GPIO_PORT_SET_SETP1_Msk (0x01UL << GPIO_PORT_SET_SETP1_Pos) /*!< GPIO_PORT SET: SETP1 Mask */ #define GPIO_PORT_SET_SETP2_Pos 2 /*!< GPIO_PORT SET: SETP2 Position */ #define GPIO_PORT_SET_SETP2_Msk (0x01UL << GPIO_PORT_SET_SETP2_Pos) /*!< GPIO_PORT SET: SETP2 Mask */ #define GPIO_PORT_SET_SETP3_Pos 3 /*!< GPIO_PORT SET: SETP3 Position */ #define GPIO_PORT_SET_SETP3_Msk (0x01UL << GPIO_PORT_SET_SETP3_Pos) /*!< GPIO_PORT SET: SETP3 Mask */ #define GPIO_PORT_SET_SETP4_Pos 4 /*!< GPIO_PORT SET: SETP4 Position */ #define GPIO_PORT_SET_SETP4_Msk (0x01UL << GPIO_PORT_SET_SETP4_Pos) /*!< GPIO_PORT SET: SETP4 Mask */ #define GPIO_PORT_SET_SETP5_Pos 5 /*!< GPIO_PORT SET: SETP5 Position */ #define GPIO_PORT_SET_SETP5_Msk (0x01UL << GPIO_PORT_SET_SETP5_Pos) /*!< GPIO_PORT SET: SETP5 Mask */ #define GPIO_PORT_SET_SETP6_Pos 6 /*!< GPIO_PORT SET: SETP6 Position */ #define GPIO_PORT_SET_SETP6_Msk (0x01UL << GPIO_PORT_SET_SETP6_Pos) /*!< GPIO_PORT SET: SETP6 Mask */ #define GPIO_PORT_SET_SETP7_Pos 7 /*!< GPIO_PORT SET: SETP7 Position */ #define GPIO_PORT_SET_SETP7_Msk (0x01UL << GPIO_PORT_SET_SETP7_Pos) /*!< GPIO_PORT SET: SETP7 Mask */ #define GPIO_PORT_SET_SETP8_Pos 8 /*!< GPIO_PORT SET: SETP8 Position */ #define GPIO_PORT_SET_SETP8_Msk (0x01UL << GPIO_PORT_SET_SETP8_Pos) /*!< GPIO_PORT SET: SETP8 Mask */ #define GPIO_PORT_SET_SETP9_Pos 9 /*!< GPIO_PORT SET: SETP9 Position */ #define GPIO_PORT_SET_SETP9_Msk (0x01UL << GPIO_PORT_SET_SETP9_Pos) /*!< GPIO_PORT SET: SETP9 Mask */ #define GPIO_PORT_SET_SETP10_Pos 10 /*!< GPIO_PORT SET: SETP10 Position */ #define GPIO_PORT_SET_SETP10_Msk (0x01UL << GPIO_PORT_SET_SETP10_Pos) /*!< GPIO_PORT SET: SETP10 Mask */ #define GPIO_PORT_SET_SETP11_Pos 11 /*!< GPIO_PORT SET: SETP11 Position */ #define GPIO_PORT_SET_SETP11_Msk (0x01UL << GPIO_PORT_SET_SETP11_Pos) /*!< GPIO_PORT SET: SETP11 Mask */ #define GPIO_PORT_SET_SETP12_Pos 12 /*!< GPIO_PORT SET: SETP12 Position */ #define GPIO_PORT_SET_SETP12_Msk (0x01UL << GPIO_PORT_SET_SETP12_Pos) /*!< GPIO_PORT SET: SETP12 Mask */ #define GPIO_PORT_SET_SETP13_Pos 13 /*!< GPIO_PORT SET: SETP13 Position */ #define GPIO_PORT_SET_SETP13_Msk (0x01UL << GPIO_PORT_SET_SETP13_Pos) /*!< GPIO_PORT SET: SETP13 Mask */ #define GPIO_PORT_SET_SETP14_Pos 14 /*!< GPIO_PORT SET: SETP14 Position */ #define GPIO_PORT_SET_SETP14_Msk (0x01UL << GPIO_PORT_SET_SETP14_Pos) /*!< GPIO_PORT SET: SETP14 Mask */ #define GPIO_PORT_SET_SETP15_Pos 15 /*!< GPIO_PORT SET: SETP15 Position */ #define GPIO_PORT_SET_SETP15_Msk (0x01UL << GPIO_PORT_SET_SETP15_Pos) /*!< GPIO_PORT SET: SETP15 Mask */ #define GPIO_PORT_SET_SETP16_Pos 16 /*!< GPIO_PORT SET: SETP16 Position */ #define GPIO_PORT_SET_SETP16_Msk (0x01UL << GPIO_PORT_SET_SETP16_Pos) /*!< GPIO_PORT SET: SETP16 Mask */ #define GPIO_PORT_SET_SETP17_Pos 17 /*!< GPIO_PORT SET: SETP17 Position */ #define GPIO_PORT_SET_SETP17_Msk (0x01UL << GPIO_PORT_SET_SETP17_Pos) /*!< GPIO_PORT SET: SETP17 Mask */ #define GPIO_PORT_SET_SETP18_Pos 18 /*!< GPIO_PORT SET: SETP18 Position */ #define GPIO_PORT_SET_SETP18_Msk (0x01UL << GPIO_PORT_SET_SETP18_Pos) /*!< GPIO_PORT SET: SETP18 Mask */ #define GPIO_PORT_SET_SETP19_Pos 19 /*!< GPIO_PORT SET: SETP19 Position */ #define GPIO_PORT_SET_SETP19_Msk (0x01UL << GPIO_PORT_SET_SETP19_Pos) /*!< GPIO_PORT SET: SETP19 Mask */ #define GPIO_PORT_SET_SETP20_Pos 20 /*!< GPIO_PORT SET: SETP20 Position */ #define GPIO_PORT_SET_SETP20_Msk (0x01UL << GPIO_PORT_SET_SETP20_Pos) /*!< GPIO_PORT SET: SETP20 Mask */ #define GPIO_PORT_SET_SETP21_Pos 21 /*!< GPIO_PORT SET: SETP21 Position */ #define GPIO_PORT_SET_SETP21_Msk (0x01UL << GPIO_PORT_SET_SETP21_Pos) /*!< GPIO_PORT SET: SETP21 Mask */ #define GPIO_PORT_SET_SETP22_Pos 22 /*!< GPIO_PORT SET: SETP22 Position */ #define GPIO_PORT_SET_SETP22_Msk (0x01UL << GPIO_PORT_SET_SETP22_Pos) /*!< GPIO_PORT SET: SETP22 Mask */ #define GPIO_PORT_SET_SETP23_Pos 23 /*!< GPIO_PORT SET: SETP23 Position */ #define GPIO_PORT_SET_SETP23_Msk (0x01UL << GPIO_PORT_SET_SETP23_Pos) /*!< GPIO_PORT SET: SETP23 Mask */ #define GPIO_PORT_SET_SETP24_Pos 24 /*!< GPIO_PORT SET: SETP24 Position */ #define GPIO_PORT_SET_SETP24_Msk (0x01UL << GPIO_PORT_SET_SETP24_Pos) /*!< GPIO_PORT SET: SETP24 Mask */ #define GPIO_PORT_SET_SETP25_Pos 25 /*!< GPIO_PORT SET: SETP25 Position */ #define GPIO_PORT_SET_SETP25_Msk (0x01UL << GPIO_PORT_SET_SETP25_Pos) /*!< GPIO_PORT SET: SETP25 Mask */ #define GPIO_PORT_SET_SETP26_Pos 26 /*!< GPIO_PORT SET: SETP26 Position */ #define GPIO_PORT_SET_SETP26_Msk (0x01UL << GPIO_PORT_SET_SETP26_Pos) /*!< GPIO_PORT SET: SETP26 Mask */ #define GPIO_PORT_SET_SETP27_Pos 27 /*!< GPIO_PORT SET: SETP27 Position */ #define GPIO_PORT_SET_SETP27_Msk (0x01UL << GPIO_PORT_SET_SETP27_Pos) /*!< GPIO_PORT SET: SETP27 Mask */ #define GPIO_PORT_SET_SETP28_Pos 28 /*!< GPIO_PORT SET: SETP28 Position */ #define GPIO_PORT_SET_SETP28_Msk (0x01UL << GPIO_PORT_SET_SETP28_Pos) /*!< GPIO_PORT SET: SETP28 Mask */ #define GPIO_PORT_SET_SETP29_Pos 29 /*!< GPIO_PORT SET: SETP29 Position */ #define GPIO_PORT_SET_SETP29_Msk (0x01UL << GPIO_PORT_SET_SETP29_Pos) /*!< GPIO_PORT SET: SETP29 Mask */ #define GPIO_PORT_SET_SETP30_Pos 30 /*!< GPIO_PORT SET: SETP30 Position */ #define GPIO_PORT_SET_SETP30_Msk (0x01UL << GPIO_PORT_SET_SETP30_Pos) /*!< GPIO_PORT SET: SETP30 Mask */ #define GPIO_PORT_SET_SETP31_Pos 31 /*!< GPIO_PORT SET: SETP31 Position */ #define GPIO_PORT_SET_SETP31_Msk (0x01UL << GPIO_PORT_SET_SETP31_Pos) /*!< GPIO_PORT SET: SETP31 Mask */ /* -------------------------------- GPIO_PORT_CLR ------------------------------- */ #define GPIO_PORT_CLR_CLRP00_Pos 0 /*!< GPIO_PORT CLR: CLRP00 Position */ #define GPIO_PORT_CLR_CLRP00_Msk (0x01UL << GPIO_PORT_CLR_CLRP00_Pos) /*!< GPIO_PORT CLR: CLRP00 Mask */ #define GPIO_PORT_CLR_CLRP01_Pos 1 /*!< GPIO_PORT CLR: CLRP01 Position */ #define GPIO_PORT_CLR_CLRP01_Msk (0x01UL << GPIO_PORT_CLR_CLRP01_Pos) /*!< GPIO_PORT CLR: CLRP01 Mask */ #define GPIO_PORT_CLR_CLRP02_Pos 2 /*!< GPIO_PORT CLR: CLRP02 Position */ #define GPIO_PORT_CLR_CLRP02_Msk (0x01UL << GPIO_PORT_CLR_CLRP02_Pos) /*!< GPIO_PORT CLR: CLRP02 Mask */ #define GPIO_PORT_CLR_CLRP03_Pos 3 /*!< GPIO_PORT CLR: CLRP03 Position */ #define GPIO_PORT_CLR_CLRP03_Msk (0x01UL << GPIO_PORT_CLR_CLRP03_Pos) /*!< GPIO_PORT CLR: CLRP03 Mask */ #define GPIO_PORT_CLR_CLRP04_Pos 4 /*!< GPIO_PORT CLR: CLRP04 Position */ #define GPIO_PORT_CLR_CLRP04_Msk (0x01UL << GPIO_PORT_CLR_CLRP04_Pos) /*!< GPIO_PORT CLR: CLRP04 Mask */ #define GPIO_PORT_CLR_CLRP05_Pos 5 /*!< GPIO_PORT CLR: CLRP05 Position */ #define GPIO_PORT_CLR_CLRP05_Msk (0x01UL << GPIO_PORT_CLR_CLRP05_Pos) /*!< GPIO_PORT CLR: CLRP05 Mask */ #define GPIO_PORT_CLR_CLRP06_Pos 6 /*!< GPIO_PORT CLR: CLRP06 Position */ #define GPIO_PORT_CLR_CLRP06_Msk (0x01UL << GPIO_PORT_CLR_CLRP06_Pos) /*!< GPIO_PORT CLR: CLRP06 Mask */ #define GPIO_PORT_CLR_CLRP07_Pos 7 /*!< GPIO_PORT CLR: CLRP07 Position */ #define GPIO_PORT_CLR_CLRP07_Msk (0x01UL << GPIO_PORT_CLR_CLRP07_Pos) /*!< GPIO_PORT CLR: CLRP07 Mask */ #define GPIO_PORT_CLR_CLRP08_Pos 8 /*!< GPIO_PORT CLR: CLRP08 Position */ #define GPIO_PORT_CLR_CLRP08_Msk (0x01UL << GPIO_PORT_CLR_CLRP08_Pos) /*!< GPIO_PORT CLR: CLRP08 Mask */ #define GPIO_PORT_CLR_CLRP09_Pos 9 /*!< GPIO_PORT CLR: CLRP09 Position */ #define GPIO_PORT_CLR_CLRP09_Msk (0x01UL << GPIO_PORT_CLR_CLRP09_Pos) /*!< GPIO_PORT CLR: CLRP09 Mask */ #define GPIO_PORT_CLR_CLRP010_Pos 10 /*!< GPIO_PORT CLR: CLRP010 Position */ #define GPIO_PORT_CLR_CLRP010_Msk (0x01UL << GPIO_PORT_CLR_CLRP010_Pos) /*!< GPIO_PORT CLR: CLRP010 Mask */ #define GPIO_PORT_CLR_CLRP011_Pos 11 /*!< GPIO_PORT CLR: CLRP011 Position */ #define GPIO_PORT_CLR_CLRP011_Msk (0x01UL << GPIO_PORT_CLR_CLRP011_Pos) /*!< GPIO_PORT CLR: CLRP011 Mask */ #define GPIO_PORT_CLR_CLRP012_Pos 12 /*!< GPIO_PORT CLR: CLRP012 Position */ #define GPIO_PORT_CLR_CLRP012_Msk (0x01UL << GPIO_PORT_CLR_CLRP012_Pos) /*!< GPIO_PORT CLR: CLRP012 Mask */ #define GPIO_PORT_CLR_CLRP013_Pos 13 /*!< GPIO_PORT CLR: CLRP013 Position */ #define GPIO_PORT_CLR_CLRP013_Msk (0x01UL << GPIO_PORT_CLR_CLRP013_Pos) /*!< GPIO_PORT CLR: CLRP013 Mask */ #define GPIO_PORT_CLR_CLRP014_Pos 14 /*!< GPIO_PORT CLR: CLRP014 Position */ #define GPIO_PORT_CLR_CLRP014_Msk (0x01UL << GPIO_PORT_CLR_CLRP014_Pos) /*!< GPIO_PORT CLR: CLRP014 Mask */ #define GPIO_PORT_CLR_CLRP015_Pos 15 /*!< GPIO_PORT CLR: CLRP015 Position */ #define GPIO_PORT_CLR_CLRP015_Msk (0x01UL << GPIO_PORT_CLR_CLRP015_Pos) /*!< GPIO_PORT CLR: CLRP015 Mask */ #define GPIO_PORT_CLR_CLRP016_Pos 16 /*!< GPIO_PORT CLR: CLRP016 Position */ #define GPIO_PORT_CLR_CLRP016_Msk (0x01UL << GPIO_PORT_CLR_CLRP016_Pos) /*!< GPIO_PORT CLR: CLRP016 Mask */ #define GPIO_PORT_CLR_CLRP017_Pos 17 /*!< GPIO_PORT CLR: CLRP017 Position */ #define GPIO_PORT_CLR_CLRP017_Msk (0x01UL << GPIO_PORT_CLR_CLRP017_Pos) /*!< GPIO_PORT CLR: CLRP017 Mask */ #define GPIO_PORT_CLR_CLRP018_Pos 18 /*!< GPIO_PORT CLR: CLRP018 Position */ #define GPIO_PORT_CLR_CLRP018_Msk (0x01UL << GPIO_PORT_CLR_CLRP018_Pos) /*!< GPIO_PORT CLR: CLRP018 Mask */ #define GPIO_PORT_CLR_CLRP019_Pos 19 /*!< GPIO_PORT CLR: CLRP019 Position */ #define GPIO_PORT_CLR_CLRP019_Msk (0x01UL << GPIO_PORT_CLR_CLRP019_Pos) /*!< GPIO_PORT CLR: CLRP019 Mask */ #define GPIO_PORT_CLR_CLRP020_Pos 20 /*!< GPIO_PORT CLR: CLRP020 Position */ #define GPIO_PORT_CLR_CLRP020_Msk (0x01UL << GPIO_PORT_CLR_CLRP020_Pos) /*!< GPIO_PORT CLR: CLRP020 Mask */ #define GPIO_PORT_CLR_CLRP021_Pos 21 /*!< GPIO_PORT CLR: CLRP021 Position */ #define GPIO_PORT_CLR_CLRP021_Msk (0x01UL << GPIO_PORT_CLR_CLRP021_Pos) /*!< GPIO_PORT CLR: CLRP021 Mask */ #define GPIO_PORT_CLR_CLRP022_Pos 22 /*!< GPIO_PORT CLR: CLRP022 Position */ #define GPIO_PORT_CLR_CLRP022_Msk (0x01UL << GPIO_PORT_CLR_CLRP022_Pos) /*!< GPIO_PORT CLR: CLRP022 Mask */ #define GPIO_PORT_CLR_CLRP023_Pos 23 /*!< GPIO_PORT CLR: CLRP023 Position */ #define GPIO_PORT_CLR_CLRP023_Msk (0x01UL << GPIO_PORT_CLR_CLRP023_Pos) /*!< GPIO_PORT CLR: CLRP023 Mask */ #define GPIO_PORT_CLR_CLRP024_Pos 24 /*!< GPIO_PORT CLR: CLRP024 Position */ #define GPIO_PORT_CLR_CLRP024_Msk (0x01UL << GPIO_PORT_CLR_CLRP024_Pos) /*!< GPIO_PORT CLR: CLRP024 Mask */ #define GPIO_PORT_CLR_CLRP025_Pos 25 /*!< GPIO_PORT CLR: CLRP025 Position */ #define GPIO_PORT_CLR_CLRP025_Msk (0x01UL << GPIO_PORT_CLR_CLRP025_Pos) /*!< GPIO_PORT CLR: CLRP025 Mask */ #define GPIO_PORT_CLR_CLRP026_Pos 26 /*!< GPIO_PORT CLR: CLRP026 Position */ #define GPIO_PORT_CLR_CLRP026_Msk (0x01UL << GPIO_PORT_CLR_CLRP026_Pos) /*!< GPIO_PORT CLR: CLRP026 Mask */ #define GPIO_PORT_CLR_CLRP027_Pos 27 /*!< GPIO_PORT CLR: CLRP027 Position */ #define GPIO_PORT_CLR_CLRP027_Msk (0x01UL << GPIO_PORT_CLR_CLRP027_Pos) /*!< GPIO_PORT CLR: CLRP027 Mask */ #define GPIO_PORT_CLR_CLRP028_Pos 28 /*!< GPIO_PORT CLR: CLRP028 Position */ #define GPIO_PORT_CLR_CLRP028_Msk (0x01UL << GPIO_PORT_CLR_CLRP028_Pos) /*!< GPIO_PORT CLR: CLRP028 Mask */ #define GPIO_PORT_CLR_CLRP029_Pos 29 /*!< GPIO_PORT CLR: CLRP029 Position */ #define GPIO_PORT_CLR_CLRP029_Msk (0x01UL << GPIO_PORT_CLR_CLRP029_Pos) /*!< GPIO_PORT CLR: CLRP029 Mask */ #define GPIO_PORT_CLR_CLRP030_Pos 30 /*!< GPIO_PORT CLR: CLRP030 Position */ #define GPIO_PORT_CLR_CLRP030_Msk (0x01UL << GPIO_PORT_CLR_CLRP030_Pos) /*!< GPIO_PORT CLR: CLRP030 Mask */ #define GPIO_PORT_CLR_CLRP031_Pos 31 /*!< GPIO_PORT CLR: CLRP031 Position */ #define GPIO_PORT_CLR_CLRP031_Msk (0x01UL << GPIO_PORT_CLR_CLRP031_Pos) /*!< GPIO_PORT CLR: CLRP031 Mask */ /* -------------------------------- GPIO_PORT_NOT ------------------------------- */ #define GPIO_PORT_NOT_NOTP0_Pos 0 /*!< GPIO_PORT NOT: NOTP0 Position */ #define GPIO_PORT_NOT_NOTP0_Msk (0x01UL << GPIO_PORT_NOT_NOTP0_Pos) /*!< GPIO_PORT NOT: NOTP0 Mask */ #define GPIO_PORT_NOT_NOTP1_Pos 1 /*!< GPIO_PORT NOT: NOTP1 Position */ #define GPIO_PORT_NOT_NOTP1_Msk (0x01UL << GPIO_PORT_NOT_NOTP1_Pos) /*!< GPIO_PORT NOT: NOTP1 Mask */ #define GPIO_PORT_NOT_NOTP2_Pos 2 /*!< GPIO_PORT NOT: NOTP2 Position */ #define GPIO_PORT_NOT_NOTP2_Msk (0x01UL << GPIO_PORT_NOT_NOTP2_Pos) /*!< GPIO_PORT NOT: NOTP2 Mask */ #define GPIO_PORT_NOT_NOTP3_Pos 3 /*!< GPIO_PORT NOT: NOTP3 Position */ #define GPIO_PORT_NOT_NOTP3_Msk (0x01UL << GPIO_PORT_NOT_NOTP3_Pos) /*!< GPIO_PORT NOT: NOTP3 Mask */ #define GPIO_PORT_NOT_NOTP4_Pos 4 /*!< GPIO_PORT NOT: NOTP4 Position */ #define GPIO_PORT_NOT_NOTP4_Msk (0x01UL << GPIO_PORT_NOT_NOTP4_Pos) /*!< GPIO_PORT NOT: NOTP4 Mask */ #define GPIO_PORT_NOT_NOTP5_Pos 5 /*!< GPIO_PORT NOT: NOTP5 Position */ #define GPIO_PORT_NOT_NOTP5_Msk (0x01UL << GPIO_PORT_NOT_NOTP5_Pos) /*!< GPIO_PORT NOT: NOTP5 Mask */ #define GPIO_PORT_NOT_NOTP6_Pos 6 /*!< GPIO_PORT NOT: NOTP6 Position */ #define GPIO_PORT_NOT_NOTP6_Msk (0x01UL << GPIO_PORT_NOT_NOTP6_Pos) /*!< GPIO_PORT NOT: NOTP6 Mask */ #define GPIO_PORT_NOT_NOTP7_Pos 7 /*!< GPIO_PORT NOT: NOTP7 Position */ #define GPIO_PORT_NOT_NOTP7_Msk (0x01UL << GPIO_PORT_NOT_NOTP7_Pos) /*!< GPIO_PORT NOT: NOTP7 Mask */ #define GPIO_PORT_NOT_NOTP8_Pos 8 /*!< GPIO_PORT NOT: NOTP8 Position */ #define GPIO_PORT_NOT_NOTP8_Msk (0x01UL << GPIO_PORT_NOT_NOTP8_Pos) /*!< GPIO_PORT NOT: NOTP8 Mask */ #define GPIO_PORT_NOT_NOTP9_Pos 9 /*!< GPIO_PORT NOT: NOTP9 Position */ #define GPIO_PORT_NOT_NOTP9_Msk (0x01UL << GPIO_PORT_NOT_NOTP9_Pos) /*!< GPIO_PORT NOT: NOTP9 Mask */ #define GPIO_PORT_NOT_NOTP10_Pos 10 /*!< GPIO_PORT NOT: NOTP10 Position */ #define GPIO_PORT_NOT_NOTP10_Msk (0x01UL << GPIO_PORT_NOT_NOTP10_Pos) /*!< GPIO_PORT NOT: NOTP10 Mask */ #define GPIO_PORT_NOT_NOTP11_Pos 11 /*!< GPIO_PORT NOT: NOTP11 Position */ #define GPIO_PORT_NOT_NOTP11_Msk (0x01UL << GPIO_PORT_NOT_NOTP11_Pos) /*!< GPIO_PORT NOT: NOTP11 Mask */ #define GPIO_PORT_NOT_NOTP12_Pos 12 /*!< GPIO_PORT NOT: NOTP12 Position */ #define GPIO_PORT_NOT_NOTP12_Msk (0x01UL << GPIO_PORT_NOT_NOTP12_Pos) /*!< GPIO_PORT NOT: NOTP12 Mask */ #define GPIO_PORT_NOT_NOTP13_Pos 13 /*!< GPIO_PORT NOT: NOTP13 Position */ #define GPIO_PORT_NOT_NOTP13_Msk (0x01UL << GPIO_PORT_NOT_NOTP13_Pos) /*!< GPIO_PORT NOT: NOTP13 Mask */ #define GPIO_PORT_NOT_NOTP14_Pos 14 /*!< GPIO_PORT NOT: NOTP14 Position */ #define GPIO_PORT_NOT_NOTP14_Msk (0x01UL << GPIO_PORT_NOT_NOTP14_Pos) /*!< GPIO_PORT NOT: NOTP14 Mask */ #define GPIO_PORT_NOT_NOTP15_Pos 15 /*!< GPIO_PORT NOT: NOTP15 Position */ #define GPIO_PORT_NOT_NOTP15_Msk (0x01UL << GPIO_PORT_NOT_NOTP15_Pos) /*!< GPIO_PORT NOT: NOTP15 Mask */ #define GPIO_PORT_NOT_NOTP16_Pos 16 /*!< GPIO_PORT NOT: NOTP16 Position */ #define GPIO_PORT_NOT_NOTP16_Msk (0x01UL << GPIO_PORT_NOT_NOTP16_Pos) /*!< GPIO_PORT NOT: NOTP16 Mask */ #define GPIO_PORT_NOT_NOTP17_Pos 17 /*!< GPIO_PORT NOT: NOTP17 Position */ #define GPIO_PORT_NOT_NOTP17_Msk (0x01UL << GPIO_PORT_NOT_NOTP17_Pos) /*!< GPIO_PORT NOT: NOTP17 Mask */ #define GPIO_PORT_NOT_NOTP18_Pos 18 /*!< GPIO_PORT NOT: NOTP18 Position */ #define GPIO_PORT_NOT_NOTP18_Msk (0x01UL << GPIO_PORT_NOT_NOTP18_Pos) /*!< GPIO_PORT NOT: NOTP18 Mask */ #define GPIO_PORT_NOT_NOTP19_Pos 19 /*!< GPIO_PORT NOT: NOTP19 Position */ #define GPIO_PORT_NOT_NOTP19_Msk (0x01UL << GPIO_PORT_NOT_NOTP19_Pos) /*!< GPIO_PORT NOT: NOTP19 Mask */ #define GPIO_PORT_NOT_NOTP20_Pos 20 /*!< GPIO_PORT NOT: NOTP20 Position */ #define GPIO_PORT_NOT_NOTP20_Msk (0x01UL << GPIO_PORT_NOT_NOTP20_Pos) /*!< GPIO_PORT NOT: NOTP20 Mask */ #define GPIO_PORT_NOT_NOTP21_Pos 21 /*!< GPIO_PORT NOT: NOTP21 Position */ #define GPIO_PORT_NOT_NOTP21_Msk (0x01UL << GPIO_PORT_NOT_NOTP21_Pos) /*!< GPIO_PORT NOT: NOTP21 Mask */ #define GPIO_PORT_NOT_NOTP22_Pos 22 /*!< GPIO_PORT NOT: NOTP22 Position */ #define GPIO_PORT_NOT_NOTP22_Msk (0x01UL << GPIO_PORT_NOT_NOTP22_Pos) /*!< GPIO_PORT NOT: NOTP22 Mask */ #define GPIO_PORT_NOT_NOTP23_Pos 23 /*!< GPIO_PORT NOT: NOTP23 Position */ #define GPIO_PORT_NOT_NOTP23_Msk (0x01UL << GPIO_PORT_NOT_NOTP23_Pos) /*!< GPIO_PORT NOT: NOTP23 Mask */ #define GPIO_PORT_NOT_NOTP24_Pos 24 /*!< GPIO_PORT NOT: NOTP24 Position */ #define GPIO_PORT_NOT_NOTP24_Msk (0x01UL << GPIO_PORT_NOT_NOTP24_Pos) /*!< GPIO_PORT NOT: NOTP24 Mask */ #define GPIO_PORT_NOT_NOTP25_Pos 25 /*!< GPIO_PORT NOT: NOTP25 Position */ #define GPIO_PORT_NOT_NOTP25_Msk (0x01UL << GPIO_PORT_NOT_NOTP25_Pos) /*!< GPIO_PORT NOT: NOTP25 Mask */ #define GPIO_PORT_NOT_NOTP26_Pos 26 /*!< GPIO_PORT NOT: NOTP26 Position */ #define GPIO_PORT_NOT_NOTP26_Msk (0x01UL << GPIO_PORT_NOT_NOTP26_Pos) /*!< GPIO_PORT NOT: NOTP26 Mask */ #define GPIO_PORT_NOT_NOTP27_Pos 27 /*!< GPIO_PORT NOT: NOTP27 Position */ #define GPIO_PORT_NOT_NOTP27_Msk (0x01UL << GPIO_PORT_NOT_NOTP27_Pos) /*!< GPIO_PORT NOT: NOTP27 Mask */ #define GPIO_PORT_NOT_NOTP28_Pos 28 /*!< GPIO_PORT NOT: NOTP28 Position */ #define GPIO_PORT_NOT_NOTP28_Msk (0x01UL << GPIO_PORT_NOT_NOTP28_Pos) /*!< GPIO_PORT NOT: NOTP28 Mask */ #define GPIO_PORT_NOT_NOTP29_Pos 29 /*!< GPIO_PORT NOT: NOTP29 Position */ #define GPIO_PORT_NOT_NOTP29_Msk (0x01UL << GPIO_PORT_NOT_NOTP29_Pos) /*!< GPIO_PORT NOT: NOTP29 Mask */ #define GPIO_PORT_NOT_NOTP30_Pos 30 /*!< GPIO_PORT NOT: NOTP30 Position */ #define GPIO_PORT_NOT_NOTP30_Msk (0x01UL << GPIO_PORT_NOT_NOTP30_Pos) /*!< GPIO_PORT NOT: NOTP30 Mask */ #define GPIO_PORT_NOT_NOTP31_Pos 31 /*!< GPIO_PORT NOT: NOTP31 Position */ #define GPIO_PORT_NOT_NOTP31_Msk (0x01UL << GPIO_PORT_NOT_NOTP31_Pos) /*!< GPIO_PORT NOT: NOTP31 Mask */ /* ================================================================================ */ /* ================ struct 'SPI' Position & Mask ================ */ /* ================================================================================ */ /* ----------------------------------- SPI_CR ----------------------------------- */ #define SPI_CR_BITENABLE_Pos 2 /*!< SPI CR: BITENABLE Position */ #define SPI_CR_BITENABLE_Msk (0x01UL << SPI_CR_BITENABLE_Pos) /*!< SPI CR: BITENABLE Mask */ #define SPI_CR_CPHA_Pos 3 /*!< SPI CR: CPHA Position */ #define SPI_CR_CPHA_Msk (0x01UL << SPI_CR_CPHA_Pos) /*!< SPI CR: CPHA Mask */ #define SPI_CR_CPOL_Pos 4 /*!< SPI CR: CPOL Position */ #define SPI_CR_CPOL_Msk (0x01UL << SPI_CR_CPOL_Pos) /*!< SPI CR: CPOL Mask */ #define SPI_CR_MSTR_Pos 5 /*!< SPI CR: MSTR Position */ #define SPI_CR_MSTR_Msk (0x01UL << SPI_CR_MSTR_Pos) /*!< SPI CR: MSTR Mask */ #define SPI_CR_LSBF_Pos 6 /*!< SPI CR: LSBF Position */ #define SPI_CR_LSBF_Msk (0x01UL << SPI_CR_LSBF_Pos) /*!< SPI CR: LSBF Mask */ #define SPI_CR_SPIE_Pos 7 /*!< SPI CR: SPIE Position */ #define SPI_CR_SPIE_Msk (0x01UL << SPI_CR_SPIE_Pos) /*!< SPI CR: SPIE Mask */ #define SPI_CR_BITS_Pos 8 /*!< SPI CR: BITS Position */ #define SPI_CR_BITS_Msk (0x0fUL << SPI_CR_BITS_Pos) /*!< SPI CR: BITS Mask */ /* ----------------------------------- SPI_SR ----------------------------------- */ #define SPI_SR_ABRT_Pos 3 /*!< SPI SR: ABRT Position */ #define SPI_SR_ABRT_Msk (0x01UL << SPI_SR_ABRT_Pos) /*!< SPI SR: ABRT Mask */ #define SPI_SR_MODF_Pos 4 /*!< SPI SR: MODF Position */ #define SPI_SR_MODF_Msk (0x01UL << SPI_SR_MODF_Pos) /*!< SPI SR: MODF Mask */ #define SPI_SR_ROVR_Pos 5 /*!< SPI SR: ROVR Position */ #define SPI_SR_ROVR_Msk (0x01UL << SPI_SR_ROVR_Pos) /*!< SPI SR: ROVR Mask */ #define SPI_SR_WCOL_Pos 6 /*!< SPI SR: WCOL Position */ #define SPI_SR_WCOL_Msk (0x01UL << SPI_SR_WCOL_Pos) /*!< SPI SR: WCOL Mask */ #define SPI_SR_SPIF_Pos 7 /*!< SPI SR: SPIF Position */ #define SPI_SR_SPIF_Msk (0x01UL << SPI_SR_SPIF_Pos) /*!< SPI SR: SPIF Mask */ /* ----------------------------------- SPI_DR ----------------------------------- */ #define SPI_DR_DATALOW_Pos 0 /*!< SPI DR: DATALOW Position */ #define SPI_DR_DATALOW_Msk (0x000000ffUL << SPI_DR_DATALOW_Pos) /*!< SPI DR: DATALOW Mask */ #define SPI_DR_DATAHIGH_Pos 8 /*!< SPI DR: DATAHIGH Position */ #define SPI_DR_DATAHIGH_Msk (0x000000ffUL << SPI_DR_DATAHIGH_Pos) /*!< SPI DR: DATAHIGH Mask */ /* ----------------------------------- SPI_CCR ---------------------------------- */ #define SPI_CCR_COUNTER_Pos 0 /*!< SPI CCR: COUNTER Position */ #define SPI_CCR_COUNTER_Msk (0x000000ffUL << SPI_CCR_COUNTER_Pos) /*!< SPI CCR: COUNTER Mask */ /* ----------------------------------- SPI_TCR ---------------------------------- */ #define SPI_TCR_TEST_Pos 1 /*!< SPI TCR: TEST Position */ #define SPI_TCR_TEST_Msk (0x7fUL << SPI_TCR_TEST_Pos) /*!< SPI TCR: TEST Mask */ /* ----------------------------------- SPI_TSR ---------------------------------- */ #define SPI_TSR_ABRT_Pos 3 /*!< SPI TSR: ABRT Position */ #define SPI_TSR_ABRT_Msk (0x01UL << SPI_TSR_ABRT_Pos) /*!< SPI TSR: ABRT Mask */ #define SPI_TSR_MODF_Pos 4 /*!< SPI TSR: MODF Position */ #define SPI_TSR_MODF_Msk (0x01UL << SPI_TSR_MODF_Pos) /*!< SPI TSR: MODF Mask */ #define SPI_TSR_ROVR_Pos 5 /*!< SPI TSR: ROVR Position */ #define SPI_TSR_ROVR_Msk (0x01UL << SPI_TSR_ROVR_Pos) /*!< SPI TSR: ROVR Mask */ #define SPI_TSR_WCOL_Pos 6 /*!< SPI TSR: WCOL Position */ #define SPI_TSR_WCOL_Msk (0x01UL << SPI_TSR_WCOL_Pos) /*!< SPI TSR: WCOL Mask */ #define SPI_TSR_SPIF_Pos 7 /*!< SPI TSR: SPIF Position */ #define SPI_TSR_SPIF_Msk (0x01UL << SPI_TSR_SPIF_Pos) /*!< SPI TSR: SPIF Mask */ /* ----------------------------------- SPI_INT ---------------------------------- */ #define SPI_INT_SPIF_Pos 0 /*!< SPI INT: SPIF Position */ #define SPI_INT_SPIF_Msk (0x01UL << SPI_INT_SPIF_Pos) /*!< SPI INT: SPIF Mask */ /* ================================================================================ */ /* ================ struct 'SGPIO' Position & Mask ================ */ /* ================================================================================ */ /* ------------------------------ SGPIO_OUT_MUX_CFG ----------------------------- */ #define SGPIO_OUT_MUX_CFG_P_OUT_CFG_Pos 0 /*!< SGPIO OUT_MUX_CFG: P_OUT_CFG Position */ #define SGPIO_OUT_MUX_CFG_P_OUT_CFG_Msk (0x0fUL << SGPIO_OUT_MUX_CFG_P_OUT_CFG_Pos) /*!< SGPIO OUT_MUX_CFG: P_OUT_CFG Mask */ #define SGPIO_OUT_MUX_CFG_P_OE_CFG_Pos 4 /*!< SGPIO OUT_MUX_CFG: P_OE_CFG Position */ #define SGPIO_OUT_MUX_CFG_P_OE_CFG_Msk (0x07UL << SGPIO_OUT_MUX_CFG_P_OE_CFG_Pos) /*!< SGPIO OUT_MUX_CFG: P_OE_CFG Mask */ /* ----------------------------- SGPIO_SGPIO_MUX_CFG ---------------------------- */ #define SGPIO_SGPIO_MUX_CFG_EXT_CLK_ENABLE_Pos 0 /*!< SGPIO SGPIO_MUX_CFG: EXT_CLK_ENABLE Position */ #define SGPIO_SGPIO_MUX_CFG_EXT_CLK_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG_EXT_CLK_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG: EXT_CLK_ENABLE Mask */ #define SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_Pos 1 /*!< SGPIO SGPIO_MUX_CFG: CLK_SOURCE_PIN_MODE Position */ #define SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG: CLK_SOURCE_PIN_MODE Mask */ #define SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_Pos 3 /*!< SGPIO SGPIO_MUX_CFG: CLK_SOURCE_SLICE_MODE Position */ #define SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG: CLK_SOURCE_SLICE_MODE Mask */ #define SGPIO_SGPIO_MUX_CFG_QUALIFIER_MODE_Pos 5 /*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_MODE Position */ #define SGPIO_SGPIO_MUX_CFG_QUALIFIER_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_QUALIFIER_MODE_Pos) /*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_MODE Mask */ #define SGPIO_SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_Pos 7 /*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_PIN_MODE Position */ #define SGPIO_SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_PIN_MODE Mask */ #define SGPIO_SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_Pos 9 /*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_SLICE_MODE Position */ #define SGPIO_SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_Pos)/*!< SGPIO SGPIO_MUX_CFG: QUALIFIER_SLICE_MODE Mask */ #define SGPIO_SGPIO_MUX_CFG_CONCAT_ENABLE_Pos 11 /*!< SGPIO SGPIO_MUX_CFG: CONCAT_ENABLE Position */ #define SGPIO_SGPIO_MUX_CFG_CONCAT_ENABLE_Msk (0x01UL << SGPIO_SGPIO_MUX_CFG_CONCAT_ENABLE_Pos) /*!< SGPIO SGPIO_MUX_CFG: CONCAT_ENABLE Mask */ #define SGPIO_SGPIO_MUX_CFG_CONCAT_ORDER_Pos 12 /*!< SGPIO SGPIO_MUX_CFG: CONCAT_ORDER Position */ #define SGPIO_SGPIO_MUX_CFG_CONCAT_ORDER_Msk (0x03UL << SGPIO_SGPIO_MUX_CFG_CONCAT_ORDER_Pos) /*!< SGPIO SGPIO_MUX_CFG: CONCAT_ORDER Mask */ /* ----------------------------- SGPIO_SLICE_MUX_CFG ---------------------------- */ #define SGPIO_SLICE_MUX_CFG_MATCH_MODE_Pos 0 /*!< SGPIO SLICE_MUX_CFG: MATCH_MODE Position */ #define SGPIO_SLICE_MUX_CFG_MATCH_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_MATCH_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG: MATCH_MODE Mask */ #define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_Pos 1 /*!< SGPIO SLICE_MUX_CFG: CLK_CAPTURE_MODE Position */ #define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG: CLK_CAPTURE_MODE Mask */ #define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_Pos 2 /*!< SGPIO SLICE_MUX_CFG: CLKGEN_MODE Position */ #define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG: CLKGEN_MODE Mask */ #define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_Pos 3 /*!< SGPIO SLICE_MUX_CFG: INV_OUT_CLK Position */ #define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_Pos) /*!< SGPIO SLICE_MUX_CFG: INV_OUT_CLK Mask */ #define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_Pos 4 /*!< SGPIO SLICE_MUX_CFG: DATA_CAPTURE_MODE Position */ #define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_Pos)/*!< SGPIO SLICE_MUX_CFG: DATA_CAPTURE_MODE Mask */ #define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_Pos 6 /*!< SGPIO SLICE_MUX_CFG: PARALLEL_MODE Position */ #define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_Msk (0x03UL << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_Pos) /*!< SGPIO SLICE_MUX_CFG: PARALLEL_MODE Mask */ #define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_Pos 8 /*!< SGPIO SLICE_MUX_CFG: INV_QUALIFIER Position */ #define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_Msk (0x01UL << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_Pos) /*!< SGPIO SLICE_MUX_CFG: INV_QUALIFIER Mask */ /* ---------------------------------- SGPIO_REG --------------------------------- */ #define SGPIO_REG_REG_Pos 0 /*!< SGPIO REG: REG Position */ #define SGPIO_REG_REG_Msk (0xffffffffUL << SGPIO_REG_REG_Pos) /*!< SGPIO REG: REG Mask */ /* -------------------------------- SGPIO_REG_SS -------------------------------- */ #define SGPIO_REG_SS_REG_SS_Pos 0 /*!< SGPIO REG_SS: REG_SS Position */ #define SGPIO_REG_SS_REG_SS_Msk (0xffffffffUL << SGPIO_REG_SS_REG_SS_Pos) /*!< SGPIO REG_SS: REG_SS Mask */ /* -------------------------------- SGPIO_PRESET -------------------------------- */ #define SGPIO_PRESET_PRESET_Pos 0 /*!< SGPIO PRESET: PRESET Position */ #define SGPIO_PRESET_PRESET_Msk (0x00000fffUL << SGPIO_PRESET_PRESET_Pos) /*!< SGPIO PRESET: PRESET Mask */ /* --------------------------------- SGPIO_COUNT -------------------------------- */ #define SGPIO_COUNT_COUNT_Pos 0 /*!< SGPIO COUNT: COUNT Position */ #define SGPIO_COUNT_COUNT_Msk (0x00000fffUL << SGPIO_COUNT_COUNT_Pos) /*!< SGPIO COUNT: COUNT Mask */ /* ---------------------------------- SGPIO_POS --------------------------------- */ #define SGPIO_POS_POS_Pos 0 /*!< SGPIO POS: POS Position */ #define SGPIO_POS_POS_Msk (0x000000ffUL << SGPIO_POS_POS_Pos) /*!< SGPIO POS: POS Mask */ #define SGPIO_POS_POS_RESET_Pos 8 /*!< SGPIO POS: POS_RESET Position */ #define SGPIO_POS_POS_RESET_Msk (0x000000ffUL << SGPIO_POS_POS_RESET_Pos) /*!< SGPIO POS: POS_RESET Mask */ /* -------------------------------- SGPIO_MASK_A -------------------------------- */ #define SGPIO_MASK_A_MASK_A_Pos 0 /*!< SGPIO MASK_A: MASK_A Position */ #define SGPIO_MASK_A_MASK_A_Msk (0xffffffffUL << SGPIO_MASK_A_MASK_A_Pos) /*!< SGPIO MASK_A: MASK_A Mask */ /* -------------------------------- SGPIO_MASK_H -------------------------------- */ #define SGPIO_MASK_H_MASK_H_Pos 0 /*!< SGPIO MASK_H: MASK_H Position */ #define SGPIO_MASK_H_MASK_H_Msk (0xffffffffUL << SGPIO_MASK_H_MASK_H_Pos) /*!< SGPIO MASK_H: MASK_H Mask */ /* -------------------------------- SGPIO_MASK_I -------------------------------- */ #define SGPIO_MASK_I_MASK_I_Pos 0 /*!< SGPIO MASK_I: MASK_I Position */ #define SGPIO_MASK_I_MASK_I_Msk (0xffffffffUL << SGPIO_MASK_I_MASK_I_Pos) /*!< SGPIO MASK_I: MASK_I Mask */ /* -------------------------------- SGPIO_MASK_P -------------------------------- */ #define SGPIO_MASK_P_MASK_P_Pos 0 /*!< SGPIO MASK_P: MASK_P Position */ #define SGPIO_MASK_P_MASK_P_Msk (0xffffffffUL << SGPIO_MASK_P_MASK_P_Pos) /*!< SGPIO MASK_P: MASK_P Mask */ /* ------------------------------ SGPIO_GPIO_INREG ------------------------------ */ #define SGPIO_GPIO_INREG_GPIO_INi_Pos 0 /*!< SGPIO GPIO_INREG: GPIO_INi Position */ #define SGPIO_GPIO_INREG_GPIO_INi_Msk (0x0000ffffUL << SGPIO_GPIO_INREG_GPIO_INi_Pos) /*!< SGPIO GPIO_INREG: GPIO_INi Mask */ /* ------------------------------ SGPIO_GPIO_OUTREG ----------------------------- */ #define SGPIO_GPIO_OUTREG_GPIO_OUT_Pos 0 /*!< SGPIO GPIO_OUTREG: GPIO_OUT Position */ #define SGPIO_GPIO_OUTREG_GPIO_OUT_Msk (0x0000ffffUL << SGPIO_GPIO_OUTREG_GPIO_OUT_Pos) /*!< SGPIO GPIO_OUTREG: GPIO_OUT Mask */ /* ------------------------------ SGPIO_GPIO_OENREG ----------------------------- */ #define SGPIO_GPIO_OENREG_GPIO_OE_Pos 0 /*!< SGPIO GPIO_OENREG: GPIO_OE Position */ #define SGPIO_GPIO_OENREG_GPIO_OE_Msk (0x0000ffffUL << SGPIO_GPIO_OENREG_GPIO_OE_Pos) /*!< SGPIO GPIO_OENREG: GPIO_OE Mask */ /* ------------------------------ SGPIO_CTRL_ENABLE ----------------------------- */ #define SGPIO_CTRL_ENABLE_CTRL_EN_Pos 0 /*!< SGPIO CTRL_ENABLE: CTRL_EN Position */ #define SGPIO_CTRL_ENABLE_CTRL_EN_Msk (0x0000ffffUL << SGPIO_CTRL_ENABLE_CTRL_EN_Pos) /*!< SGPIO CTRL_ENABLE: CTRL_EN Mask */ /* ----------------------------- SGPIO_CTRL_DISABLE ----------------------------- */ #define SGPIO_CTRL_DISABLE_CTRL_DIS_Pos 0 /*!< SGPIO CTRL_DISABLE: CTRL_DIS Position */ #define SGPIO_CTRL_DISABLE_CTRL_DIS_Msk (0x0000ffffUL << SGPIO_CTRL_DISABLE_CTRL_DIS_Pos) /*!< SGPIO CTRL_DISABLE: CTRL_DIS Mask */ /* ------------------------------- SGPIO_CLR_EN_0 ------------------------------- */ #define SGPIO_CLR_EN_0_CLR_SCI_Pos 0 /*!< SGPIO CLR_EN_0: CLR_SCI Position */ #define SGPIO_CLR_EN_0_CLR_SCI_Msk (0x0000ffffUL << SGPIO_CLR_EN_0_CLR_SCI_Pos) /*!< SGPIO CLR_EN_0: CLR_SCI Mask */ /* ------------------------------- SGPIO_SET_EN_0 ------------------------------- */ #define SGPIO_SET_EN_0_SET_SCI_Pos 0 /*!< SGPIO SET_EN_0: SET_SCI Position */ #define SGPIO_SET_EN_0_SET_SCI_Msk (0x0000ffffUL << SGPIO_SET_EN_0_SET_SCI_Pos) /*!< SGPIO SET_EN_0: SET_SCI Mask */ /* ------------------------------- SGPIO_ENABLE_0 ------------------------------- */ #define SGPIO_ENABLE_0_ENABLE_SCI_Pos 0 /*!< SGPIO ENABLE_0: ENABLE_SCI Position */ #define SGPIO_ENABLE_0_ENABLE_SCI_Msk (0x0000ffffUL << SGPIO_ENABLE_0_ENABLE_SCI_Pos) /*!< SGPIO ENABLE_0: ENABLE_SCI Mask */ /* ------------------------------- SGPIO_STATUS_0 ------------------------------- */ #define SGPIO_STATUS_0_STATUS_SCI_Pos 0 /*!< SGPIO STATUS_0: STATUS_SCI Position */ #define SGPIO_STATUS_0_STATUS_SCI_Msk (0x0000ffffUL << SGPIO_STATUS_0_STATUS_SCI_Pos) /*!< SGPIO STATUS_0: STATUS_SCI Mask */ /* ----------------------------- SGPIO_CLR_STATUS_0 ----------------------------- */ #define SGPIO_CLR_STATUS_0_CLR_STATUS_SCI_Pos 0 /*!< SGPIO CLR_STATUS_0: CLR_STATUS_SCI Position */ #define SGPIO_CLR_STATUS_0_CLR_STATUS_SCI_Msk (0x0000ffffUL << SGPIO_CLR_STATUS_0_CLR_STATUS_SCI_Pos) /*!< SGPIO CLR_STATUS_0: CLR_STATUS_SCI Mask */ /* ----------------------------- SGPIO_SET_STATUS_0 ----------------------------- */ #define SGPIO_SET_STATUS_0_SET_STATUS_SCI_Pos 0 /*!< SGPIO SET_STATUS_0: SET_STATUS_SCI Position */ #define SGPIO_SET_STATUS_0_SET_STATUS_SCI_Msk (0x0000ffffUL << SGPIO_SET_STATUS_0_SET_STATUS_SCI_Pos) /*!< SGPIO SET_STATUS_0: SET_STATUS_SCI Mask */ /* ------------------------------- SGPIO_CLR_EN_1 ------------------------------- */ #define SGPIO_CLR_EN_1_CLR_EN_CCI_Pos 0 /*!< SGPIO CLR_EN_1: CLR_EN_CCI Position */ #define SGPIO_CLR_EN_1_CLR_EN_CCI_Msk (0x0000ffffUL << SGPIO_CLR_EN_1_CLR_EN_CCI_Pos) /*!< SGPIO CLR_EN_1: CLR_EN_CCI Mask */ /* ------------------------------- SGPIO_SET_EN_1 ------------------------------- */ #define SGPIO_SET_EN_1_SET_EN_CCI_Pos 0 /*!< SGPIO SET_EN_1: SET_EN_CCI Position */ #define SGPIO_SET_EN_1_SET_EN_CCI_Msk (0x0000ffffUL << SGPIO_SET_EN_1_SET_EN_CCI_Pos) /*!< SGPIO SET_EN_1: SET_EN_CCI Mask */ /* ------------------------------- SGPIO_ENABLE_1 ------------------------------- */ #define SGPIO_ENABLE_1_ENABLE_CCI_Pos 0 /*!< SGPIO ENABLE_1: ENABLE_CCI Position */ #define SGPIO_ENABLE_1_ENABLE_CCI_Msk (0x0000ffffUL << SGPIO_ENABLE_1_ENABLE_CCI_Pos) /*!< SGPIO ENABLE_1: ENABLE_CCI Mask */ /* ------------------------------- SGPIO_STATUS_1 ------------------------------- */ #define SGPIO_STATUS_1_STATUS_CCI_Pos 0 /*!< SGPIO STATUS_1: STATUS_CCI Position */ #define SGPIO_STATUS_1_STATUS_CCI_Msk (0x0000ffffUL << SGPIO_STATUS_1_STATUS_CCI_Pos) /*!< SGPIO STATUS_1: STATUS_CCI Mask */ /* ----------------------------- SGPIO_CLR_STATUS_1 ----------------------------- */ #define SGPIO_CLR_STATUS_1_CLR_STATUS_CCI_Pos 0 /*!< SGPIO CLR_STATUS_1: CLR_STATUS_CCI Position */ #define SGPIO_CLR_STATUS_1_CLR_STATUS_CCI_Msk (0x0000ffffUL << SGPIO_CLR_STATUS_1_CLR_STATUS_CCI_Pos) /*!< SGPIO CLR_STATUS_1: CLR_STATUS_CCI Mask */ /* ----------------------------- SGPIO_SET_STATUS_1 ----------------------------- */ #define SGPIO_SET_STATUS_1_SET_STATUS_CCI_Pos 0 /*!< SGPIO SET_STATUS_1: SET_STATUS_CCI Position */ #define SGPIO_SET_STATUS_1_SET_STATUS_CCI_Msk (0x0000ffffUL << SGPIO_SET_STATUS_1_SET_STATUS_CCI_Pos) /*!< SGPIO SET_STATUS_1: SET_STATUS_CCI Mask */ /* ------------------------------- SGPIO_CLR_EN_2 ------------------------------- */ #define SGPIO_CLR_EN_2_CLR_EN2_PMI_Pos 0 /*!< SGPIO CLR_EN_2: CLR_EN2_PMI Position */ #define SGPIO_CLR_EN_2_CLR_EN2_PMI_Msk (0x0000ffffUL << SGPIO_CLR_EN_2_CLR_EN2_PMI_Pos) /*!< SGPIO CLR_EN_2: CLR_EN2_PMI Mask */ /* ------------------------------- SGPIO_SET_EN_2 ------------------------------- */ #define SGPIO_SET_EN_2_SET_EN_PMI_Pos 0 /*!< SGPIO SET_EN_2: SET_EN_PMI Position */ #define SGPIO_SET_EN_2_SET_EN_PMI_Msk (0x0000ffffUL << SGPIO_SET_EN_2_SET_EN_PMI_Pos) /*!< SGPIO SET_EN_2: SET_EN_PMI Mask */ /* ------------------------------- SGPIO_ENABLE_2 ------------------------------- */ #define SGPIO_ENABLE_2_ENABLE_PMI_Pos 0 /*!< SGPIO ENABLE_2: ENABLE_PMI Position */ #define SGPIO_ENABLE_2_ENABLE_PMI_Msk (0x0000ffffUL << SGPIO_ENABLE_2_ENABLE_PMI_Pos) /*!< SGPIO ENABLE_2: ENABLE_PMI Mask */ /* ------------------------------- SGPIO_STATUS_2 ------------------------------- */ #define SGPIO_STATUS_2_STATUS_PMI_Pos 0 /*!< SGPIO STATUS_2: STATUS_PMI Position */ #define SGPIO_STATUS_2_STATUS_PMI_Msk (0x0000ffffUL << SGPIO_STATUS_2_STATUS_PMI_Pos) /*!< SGPIO STATUS_2: STATUS_PMI Mask */ /* ----------------------------- SGPIO_CLR_STATUS_2 ----------------------------- */ #define SGPIO_CLR_STATUS_2_CLR_STATUS_PMI_Pos 0 /*!< SGPIO CLR_STATUS_2: CLR_STATUS_PMI Position */ #define SGPIO_CLR_STATUS_2_CLR_STATUS_PMI_Msk (0x0000ffffUL << SGPIO_CLR_STATUS_2_CLR_STATUS_PMI_Pos) /*!< SGPIO CLR_STATUS_2: CLR_STATUS_PMI Mask */ /* ----------------------------- SGPIO_SET_STATUS_2 ----------------------------- */ #define SGPIO_SET_STATUS_2_SET_STATUS_PMI_Pos 0 /*!< SGPIO SET_STATUS_2: SET_STATUS_PMI Position */ #define SGPIO_SET_STATUS_2_SET_STATUS_PMI_Msk (0x0000ffffUL << SGPIO_SET_STATUS_2_SET_STATUS_PMI_Pos) /*!< SGPIO SET_STATUS_2: SET_STATUS_PMI Mask */ /* ------------------------------- SGPIO_CLR_EN_3 ------------------------------- */ #define SGPIO_CLR_EN_3_CLR_EN_INPI_Pos 0 /*!< SGPIO CLR_EN_3: CLR_EN_INPI Position */ #define SGPIO_CLR_EN_3_CLR_EN_INPI_Msk (0x0000ffffUL << SGPIO_CLR_EN_3_CLR_EN_INPI_Pos) /*!< SGPIO CLR_EN_3: CLR_EN_INPI Mask */ /* ------------------------------- SGPIO_SET_EN_3 ------------------------------- */ #define SGPIO_SET_EN_3_SET_EN_INPI_Pos 0 /*!< SGPIO SET_EN_3: SET_EN_INPI Position */ #define SGPIO_SET_EN_3_SET_EN_INPI_Msk (0x0000ffffUL << SGPIO_SET_EN_3_SET_EN_INPI_Pos) /*!< SGPIO SET_EN_3: SET_EN_INPI Mask */ /* ------------------------------- SGPIO_ENABLE_3 ------------------------------- */ #define SGPIO_ENABLE_3_ENABLE3_INPI_Pos 0 /*!< SGPIO ENABLE_3: ENABLE3_INPI Position */ #define SGPIO_ENABLE_3_ENABLE3_INPI_Msk (0x0000ffffUL << SGPIO_ENABLE_3_ENABLE3_INPI_Pos) /*!< SGPIO ENABLE_3: ENABLE3_INPI Mask */ /* ------------------------------- SGPIO_STATUS_3 ------------------------------- */ #define SGPIO_STATUS_3_STATUS_INPI_Pos 0 /*!< SGPIO STATUS_3: STATUS_INPI Position */ #define SGPIO_STATUS_3_STATUS_INPI_Msk (0x0000ffffUL << SGPIO_STATUS_3_STATUS_INPI_Pos) /*!< SGPIO STATUS_3: STATUS_INPI Mask */ /* ----------------------------- SGPIO_CLR_STATUS_3 ----------------------------- */ #define SGPIO_CLR_STATUS_3_CLR_STATUS_INPI_Pos 0 /*!< SGPIO CLR_STATUS_3: CLR_STATUS_INPI Position */ #define SGPIO_CLR_STATUS_3_CLR_STATUS_INPI_Msk (0x0000ffffUL << SGPIO_CLR_STATUS_3_CLR_STATUS_INPI_Pos)/*!< SGPIO CLR_STATUS_3: CLR_STATUS_INPI Mask */ /* ----------------------------- SGPIO_SET_STATUS_3 ----------------------------- */ #define SGPIO_SET_STATUS_3_SET_STATUS_INPI_Pos 0 /*!< SGPIO SET_STATUS_3: SET_STATUS_INPI Position */ #define SGPIO_SET_STATUS_3_SET_STATUS_INPI_Msk (0x0000ffffUL << SGPIO_SET_STATUS_3_SET_STATUS_INPI_Pos)/*!< SGPIO SET_STATUS_3: SET_STATUS_INPI Mask */ /* ================================================================================ */ /* ================ Peripheral memory map ================ */ /* ================================================================================ */ #define LPC_SCT_BASE 0x40000000UL #define LPC_GPDMA_BASE 0x40002000UL #define LPC_SPIFI_BASE 0x40003000UL #define LPC_SDMMC_BASE 0x40004000UL #define LPC_EMC_BASE 0x40005000UL #define LPC_USB0_BASE 0x40006000UL #define LPC_USB1_BASE 0x40007000UL #define LPC_LCD_BASE 0x40008000UL #define LPC_EEPROM_BASE 0x4000E000UL #define LPC_ETHERNET_BASE 0x40010000UL #define LPC_ATIMER_BASE 0x40040000UL #define LPC_REGFILE_BASE 0x40041000UL #define LPC_PMC_BASE 0x40042000UL #define LPC_CREG_BASE 0x40043000UL #define LPC_EVENTROUTER_BASE 0x40044000UL #define LPC_RTC_BASE 0x40046000UL #define LPC_CGU_BASE 0x40050000UL #define LPC_CCU1_BASE 0x40051000UL #define LPC_CCU2_BASE 0x40052000UL #define LPC_RGU_BASE 0x40053000UL #define LPC_WWDT_BASE 0x40080000UL #define LPC_USART0_BASE 0x40081000UL #define LPC_USART2_BASE 0x400C1000UL #define LPC_USART3_BASE 0x400C2000UL #define LPC_UART1_BASE 0x40082000UL #define LPC_SSP0_BASE 0x40083000UL #define LPC_SSP1_BASE 0x400C5000UL #define LPC_TIMER0_BASE 0x40084000UL #define LPC_TIMER1_BASE 0x40085000UL #define LPC_TIMER2_BASE 0x400C3000UL #define LPC_TIMER3_BASE 0x400C4000UL #define LPC_SCU_BASE 0x40086000UL #define LPC_GPIO_PIN_INT_BASE 0x40087000UL #define LPC_GPIO_GROUP_INT0_BASE 0x40088000UL #define LPC_GPIO_GROUP_INT1_BASE 0x40089000UL #define LPC_MCPWM_BASE 0x400A0000UL #define LPC_I2C0_BASE 0x400A1000UL #define LPC_I2C1_BASE 0x400E0000UL #define LPC_I2S0_BASE 0x400A2000UL #define LPC_I2S1_BASE 0x400A3000UL #define LPC_C_CAN1_BASE 0x400A4000UL #define LPC_RITIMER_BASE 0x400C0000UL #define LPC_QEI_BASE 0x400C6000UL #define LPC_GIMA_BASE 0x400C7000UL #define LPC_DAC_BASE 0x400E1000UL #define LPC_C_CAN0_BASE 0x400E2000UL #define LPC_ADC0_BASE 0x400E3000UL #define LPC_ADC1_BASE 0x400E4000UL #define LPC_ADCHS_BASE 0x400F0000UL #define LPC_GPIO_PORT_BASE 0x400F4000UL #define LPC_SPI_BASE 0x40100000UL #define LPC_SGPIO_BASE 0x40101000UL /* ================================================================================ */ /* ================ Peripheral declaration ================ */ /* ================================================================================ */ #define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE) #define LPC_GPDMA ((LPC_GPDMA_Type *) LPC_GPDMA_BASE) #define LPC_SPIFI ((LPC_SPIFI_Type *) LPC_SPIFI_BASE) #define LPC_SDMMC ((LPC_SDMMC_Type *) LPC_SDMMC_BASE) #define LPC_EMC ((LPC_EMC_Type *) LPC_EMC_BASE) #define LPC_USB0 ((LPC_USB0_Type *) LPC_USB0_BASE) #define LPC_USB1 ((LPC_USB1_Type *) LPC_USB1_BASE) #define LPC_LCD ((LPC_LCD_Type *) LPC_LCD_BASE) #define LPC_EEPROM ((LPC_EEPROM_Type *) LPC_EEPROM_BASE) #define LPC_ETHERNET ((LPC_ETHERNET_Type *) LPC_ETHERNET_BASE) #define LPC_ATIMER ((LPC_ATIMER_Type *) LPC_ATIMER_BASE) #define LPC_REGFILE ((LPC_REGFILE_Type *) LPC_REGFILE_BASE) #define LPC_PMC ((LPC_PMC_Type *) LPC_PMC_BASE) #define LPC_CREG ((LPC_CREG_Type *) LPC_CREG_BASE) #define LPC_EVENTROUTER ((LPC_EVENTROUTER_Type *) LPC_EVENTROUTER_BASE) #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE) #define LPC_CGU ((LPC_CGU_Type *) LPC_CGU_BASE) #define LPC_CCU1 ((LPC_CCU1_Type *) LPC_CCU1_BASE) #define LPC_CCU2 ((LPC_CCU2_Type *) LPC_CCU2_BASE) #define LPC_RGU ((LPC_RGU_Type *) LPC_RGU_BASE) #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) #define LPC_USART0 ((LPC_USARTn_Type *) LPC_USART0_BASE) #define LPC_USART2 ((LPC_USARTn_Type *) LPC_USART2_BASE) #define LPC_USART3 ((LPC_USARTn_Type *) LPC_USART3_BASE) #define LPC_UART1 ((LPC_UART1_Type *) LPC_UART1_BASE) #define LPC_SSP0 ((LPC_SSPn_Type *) LPC_SSP0_BASE) #define LPC_SSP1 ((LPC_SSPn_Type *) LPC_SSP1_BASE) #define LPC_TIMER0 ((LPC_TIMERn_Type *) LPC_TIMER0_BASE) #define LPC_TIMER1 ((LPC_TIMERn_Type *) LPC_TIMER1_BASE) #define LPC_TIMER2 ((LPC_TIMERn_Type *) LPC_TIMER2_BASE) #define LPC_TIMER3 ((LPC_TIMERn_Type *) LPC_TIMER3_BASE) #define LPC_SCU ((LPC_SCU_Type *) LPC_SCU_BASE) #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT0_BASE) #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTn_Type*) LPC_GPIO_GROUP_INT1_BASE) #define LPC_MCPWM ((LPC_MCPWM_Type *) LPC_MCPWM_BASE) #define LPC_I2C0 ((LPC_I2Cn_Type *) LPC_I2C0_BASE) #define LPC_I2C1 ((LPC_I2Cn_Type *) LPC_I2C1_BASE) #define LPC_I2S0 ((LPC_I2Sn_Type *) LPC_I2S0_BASE) #define LPC_I2S1 ((LPC_I2Sn_Type *) LPC_I2S1_BASE) #define LPC_C_CAN1 ((LPC_C_CANn_Type *) LPC_C_CAN1_BASE) #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE) #define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE) #define LPC_GIMA ((LPC_GIMA_Type *) LPC_GIMA_BASE) #define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE) #define LPC_C_CAN0 ((LPC_C_CANn_Type *) LPC_C_CAN0_BASE) #define LPC_ADC0 ((LPC_ADCn_Type *) LPC_ADC0_BASE) #define LPC_ADC1 ((LPC_ADCn_Type *) LPC_ADC1_BASE) #define LPC_ADCHS ((LPC_ADCHS_Type *) LPC_ADCHS_BASE) #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE) #define LPC_SPI ((LPC_SPI_Type *) LPC_SPI_BASE) #define LPC_SGPIO ((LPC_SGPIO_Type *) LPC_SGPIO_BASE) /** @} */ /* End of group Device_Peripheral_Registers */ /** @} */ /* End of group LPC43xx */ /** @} */ /* End of group (null) */ #ifdef __cplusplus } #endif #endif /* LPC43xx_H */