/**************************************************************************//**
 * @file     MB9BF50x.h
 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 
 *           for the Fujitsu MB9BF50x Device Series
 * @version  V1.03
 * @date     20. December 2010
 *
 * @note
 * Copyright (C) 2010 ARM Limited. All rights reserved.
 *
 * @par
 * ARM Limited (ARM) is supplying this software for use with Cortex-M 
 * processor based microcontrollers.  This file can be freely distributed 
 * within development tools that are supporting such ARM based processors. 
 *
 * @par
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 *
 ******************************************************************************/


#ifndef __MB9BF50x_H__
#define __MB9BF50x_H__

#ifdef __cplusplus
 extern "C" {
#endif 

/** @addtogroup MB9BF50x_CMSIS MB9BF50x CMSIS Definitions
  This file defines all structures and symbols for MB9BF50x:
    - Registers and bitfields
    - peripheral base address
    - peripheral ID
    - PIO definitions
  @{
*/


/******************************************************************************/
/*                Processor and Core Peripherals                              */
/******************************************************************************/
/** @addtogroup MB9BF50x_CMSIS MB9BF50x CMSIS Definitions
  Configuration of the Cortex-M3 Processor and Core Peripherals
  @{
*/

/*
 * ==========================================================================
 * ---------- Interrupt Number Definition -----------------------------------
 * ==========================================================================
 */
typedef enum IRQn
{
/******  Cortex-M3 Processor Exceptions Numbers *********************************************************************/
  NonMaskableInt_IRQn           = -14,   /*!< 2 Non Maskable Interrupt                                              */
  HardFault_IRQn                = -13,   /*!< 3 Cortex-M0 Hard Fault Interrupt                                      */
  MemoryManagement_IRQn         = -12,   /*!< 4 Cortex-M3 Memory Management Interrupt                               */
  BusFault_IRQn                 = -11,   /*!< 5 Cortex-M3 Bus Fault Interrupt                                       */
  UsageFault_IRQn               = -10,   /*!< 6 Cortex-M3 Usage Fault Interrupt                                     */
  SVCall_IRQn                   = -5,    /*!< 11 Cortex-M3 SV Call Interrupt                                        */
  DebugMonitor_IRQn             = -4,    /*!< 12 Cortex-M3 Debug Monitor Interrupt                                  */
  PendSV_IRQn                   = -2,    /*!< 14 Cortex-M3 Pend SV Interrupt                                        */
  SysTick_IRQn                  = -1,    /*!< 15 Cortex-M3 System Tick Interrupt                                    */

/******  MB9BF50x Specific Interrupt Numbers ***********************************************************************/
  FCS_IRQn                      =  0,    /*!< Anomalous Frequency Detection by Clock Supervisor (FCS)               */
  SWWDT_IRQn                    =  1,    /*!< Software Watchdog Timer                                               */
  LVD_IRQn                      =  2,    /*!< Low Voltage Detector (LVD)                                            */
  MFT_WFG_IRQn                  =  3,    /*!< MFT unit0, unit1 Wave Form Generator / DTIF(Motor Emergency Stop)     */
  EXTI7_0_IRQn                  =  4,    /*!< External INT_RQ ch.0 to ch.7                                          */
  EXTI15_8_IRQn                 =  5,    /*!< External INT_RQ ch.8 to ch.15                                         */
  TIM_QPRC_IRQn                 =  6,    /*!< Dual Timer / Quadrature Position/Resolution Counter (QPRC) ch.0, ch.1 */
  MFS0_R_IRQn                   =  7,    /*!< Reception INT_RQ of MFS IF ch.0                                       */
  MFS0_TS_IRQn                  =  8,    /*!< Transmission INT_RQ and Status INT_RQ of MFS IF ch.0                  */
  MFS1_R_IRQn                   =  9,    /*!< Reception INT_RQ of MFS IF ch.1                                       */
  MFS1_TS_IRQn                  = 10,    /*!< Transmission INT_RQ and Status INT_RQ of MFS IF ch.1                  */
  FMS2_R_IRQn                   = 11,    /*!< Reception INT_RQ of MFA IF ch.2                                       */
  MFS2_TS_IRQn                  = 12,    /*!< Transmission INT_RQ and Status INT_RQ of MFS IF ch.2                  */
  MFS3_R_IRQn                   = 13,    /*!< Reception INT_RQ of MFS IF ch.3                                       */
  MFS3_TS_IRQn                  = 14,    /*!< Transmission INT_RQ and Status INT_RQ of MFS IF ch.3                  */
  MFS4_R_IRQn                   = 15,    /*!< Reception INT_RQ of MFS IF ch.4                                       */
  MFS4_TS_IRQn                  = 16,    /*!< Transmission INT_RQ and Status INT_RQ of MFS IF ch.4                  */
  MFS5_R_IRQn                   = 17,    /*!< Reception INT_RQ of MFS IF ch.5                                       */
  MFS5_TS_IRQn                  = 18,    /*!< Transmission INT_RQ and Status INT_RQ of MFS IF ch.5                  */
  MFS6_R_IRQn                   = 19,    /*!< Reception INT_RQ of MFS IF ch.6                                       */
  MFS6_TS_IRQn                  = 20,    /*!< Transmission INT_RQ and Status INT_RQ of MFS IF ch.6                  */
  MFS7_R_IRQn                   = 21,    /*!< Reception INT_RQ of MFS IF ch.7                                       */
  MFS7_TS_IRQn                  = 22,    /*!< Transmission INT_RQ and Status INT_RQ of MFS IF ch.7                  */
  PPG_IRQn                      = 23,    /*!< PPG ch.0/2/4/8/10/12                                                  */
  OSC_PLL_WCNT_IRQn             = 24,    /*!< Ext. Main OSC / Ext. Sub OSC / Main PLL / PLL for USB / Watch CNT     */
  ADC0_IRQn                     = 25,    /*!< A/D Converter unit0                                                   */
  ADC1_IRQn                     = 26,    /*!< A/D Converter unit1                                                   */
  ADC2_IRQn                     = 27,    /*!< A/D Converter unit2                                                   */
  MFT_FRT_IRQn                  = 28,    /*!< MFT unit0, unit1 Free-run Timer                                       */
  MFT_IC_IRQn                   = 29,    /*!< MFT unit0, unit1 Input Capture                                        */
  MFT_OC_IRQn                   = 30,    /*!< MFT unit0, unit1 Output Compare                                       */
  BTIM_IRQn                     = 31,    /*!< Base Timer ch.0 to ch.7                                               */
  CAN0_IRQn                     = 32,    /*!< CAN ch.0                                                              */
  CAN1_IRQn                     = 33,    /*!< CAN ch.1                                                              */
  USB_EP1_EP5_IRQn              = 34,    /*!< USB Function (DRQ of End Point 1 to 5)                                */
  USB_EP0_STA_IRQn              = 35,    /*!< USB Function (DRQI of End Point 0, DRQO) / USB HOST                   */
  DMA0_IRQn                     = 38,    /*!< DMA Controller (DMAC) ch.0                                            */
  DMA1_IRQn                     = 39,    /*!< DMA Controller (DMAC) ch.1                                            */
  DMA2_IRQn                     = 40,    /*!< DMA Controller (DMAC) ch.2                                            */
  DMA3_IRQn                     = 41,    /*!< DMA Controller (DMAC) ch.3                                            */
  DMA4_IRQn                     = 42,    /*!< DMA Controller (DMAC) ch.4                                            */
  DMA5_IRQn                     = 43,    /*!< DMA Controller (DMAC) ch.5                                            */
  DMA6_IRQn                     = 44,    /*!< DMA Controller (DMAC) ch.6                                            */
  DMA7_IRQn                     = 45,    /*!< DMA Controller (DMAC) ch.7                                            */
} IRQn_Type;

/*
 * ==========================================================================
 * ----------- Processor and Core Peripheral Section ------------------------
 * ==========================================================================
 */

/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT             1         /*!< MPU present or not                               */
#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels          */
#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */

/*@}*/ /* end of group MB9BF50x_CMSIS */


#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
#include "system_MB9BF50x.h"                /* System Header                                      */


/******************************************************************************/
/*                Device Specific Peripheral Registers structures             */
/******************************************************************************/

#if defined ( __CC_ARM   )
#pragma anon_unions
#endif

/*------------- Flash Interface --------------------------------------------------*/
/** @addtogroup MB9BF50x_FIF MB9BF50x Flash Interface
  @{
*/
typedef struct
{
  __IO uint32_t FASZR;                   /*!< Offset: 0x000 (R/W) Flash Access Size Register */
  __IO uint32_t FRWTR;                   /*!< Offset: 0x004 (R/W) Flash Read Wait Register */
  __IO uint32_t FSTR;                    /*!< Offset: 0x008 (R/W) Flash Status Register */
       uint32_t RESERVED0;
  __IO uint32_t FSYNDN;                  /*!< Offset: 0x010 (R/W) Flash Sync Down Register */
} MB9BF_FIF_TypeDef;
/*@}*/ /* end of group MB9BF50x_FIF */


/*------------- USB Function / Host -----------------------------------------------*/
/** @addtogroup MB9BF50x_USB MB9BF50x USB Function / Host
  @{
*/
typedef struct
{
       uint32_t RESERVED[2112];
  __IO uint16_t HCNT;                    /*!< Offset: 0x000 (R/W) Host Control Register */
       uint16_t RESERVED0[1];
  __IO  uint8_t HIRQ;                    /*!< Offset: 0x004 (R/W) Host Interrupt Register */
  __IO  uint8_t HERR;                    /*!< Offset: 0x005 (R/W) Host Error Status Register */
        uint8_t RESERVED1[2];
  __IO  uint8_t HSTATE;                  /*!< Offset: 0x008 (R/W) Host Status Register */
  __IO  uint8_t HFCOMP;                  /*!< Offset: 0x009 (R/W) SOF Interrupt Frame Compare Register */
        uint8_t RESERVED2[2];
  __IO  uint8_t HRTIMER0;                /*!< Offset: 0x00C (R/W) Retry Timer Setup Register */
  __IO  uint8_t HRTIMER1;                /*!< Offset: 0x00D (R/W) Retry Timer Setup Register */
        uint8_t RESERVED3[2];
  __IO  uint8_t HRTIMER2;                /*!< Offset: 0x010 (R/W) Retry Timer Setup Register */
  __IO  uint8_t HADR;                    /*!< Offset: 0x011 (R/W) Host Address Register */
        uint8_t RESERVED4[2];
  __IO uint16_t HEOF;                    /*!< Offset: 0x014 (R/W) EOF Setup Register */
       uint16_t RESERVED5[1];
  __IO uint16_t HFRAME;                  /*!< Offset: 0x018 (R/W) Frame Setup Register */
       uint16_t RESERVED6[1];
  __IO  uint8_t HTOKEN;                  /*!< Offset: 0x01C (R/W) Host Token Endpoint Register */
        uint8_t RESERVED7[3];
  __IO  uint8_t UDCC;                    /*!< Offset: 0x020 (R/W) UDC Control Register */
        uint8_t RESERVED8[3];
  __IO uint16_t EP0C;                    /*!< Offset: 0x024 (R/W) EP0 Control Register */
       uint16_t RESERVED9[1];
  __IO uint16_t EP1C;                    /*!< Offset: 0x028 (R/W) EP1 Control Register */
       uint16_t RESERVED10[1];
  __IO uint16_t EP2C;                    /*!< Offset: 0x02C (R/W) EP2 Control Register */
       uint16_t RESERVED11[1];
  __IO uint16_t EP3C;                    /*!< Offset: 0x030 (R/W) EP3 Control Register */
       uint16_t RESERVED12[1];
  __IO uint16_t EP4C;                    /*!< Offset: 0x034 (R/W) EP4 Control Register */
       uint16_t RESERVED13[1];
  __IO uint16_t EP5C;                    /*!< Offset: 0x038 (R/W) EP5 Control Register */
       uint16_t RESERVED14[1];
  __IO uint16_t TMSP;                    /*!< Offset: 0x03C (R/W) Time Stamp Register */
       uint16_t RESERVED15[1];
  __IO  uint8_t UDCS;                    /*!< Offset: 0x040 (R/W) UDC Status Register */
  __IO  uint8_t UDCIE;                   /*!< Offset: 0x041 (R/W) UDC Interrupt Enable Register */
        uint8_t RESERVED16[2];
  __IO uint16_t EP0IS;                   /*!< Offset: 0x044 (R/W) EP0I Status Register */
       uint16_t RESERVED17[1];
  __IO uint16_t EP0OS;                   /*!< Offset: 0x048 (R/W) EP0O Status Register */
       uint16_t RESERVED18[1];
  __IO uint16_t EP1S;                    /*!< Offset: 0x04C (R/W) EP1 Status Register */
       uint16_t RESERVED19[1];
  __IO uint16_t EP2S;                    /*!< Offset: 0x050 (R/W) EP2 Status Register */
       uint16_t RESERVED20[1];
  __IO uint16_t EP3S;                    /*!< Offset: 0x054 (R/W) EP3 Status Register */
       uint16_t RESERVED21[1];
  __IO uint16_t EP4S;                    /*!< Offset: 0x058 (R/W) EP4 Status Register */
       uint16_t RESERVED22[1];
  __IO uint16_t EP5S;                    /*!< Offset: 0x05C (R/W) EP5 Status Register */
       uint16_t RESERVED23[1];
  __IO uint16_t EP0DT;                   /*!< Offset: 0x060 (R/W) EP0 Data Register */
       uint16_t RESERVED24[1];
  __IO uint16_t EP1DT;                   /*!< Offset: 0x064 (R/W) EP1 Data Register */
       uint16_t RESERVED25[1];
  __IO uint16_t EP2DT;                   /*!< Offset: 0x068 (R/W) EP2 Data Register */
       uint16_t RESERVED26[1];
  __IO uint16_t EP3DT;                   /*!< Offset: 0x06C (R/W) EP3 Data Register */
       uint16_t RESERVED27[1];
  __IO uint16_t EP4DT;                   /*!< Offset: 0x070 (R/W) EP4 Data Register */
       uint16_t RESERVED28[1];
  __IO uint16_t EP5DT;                   /*!< Offset: 0x074 (R/W) EP5 Data Register */
       uint16_t RESERVED29[1];
} MB9BF_USB_TypeDef;
/*@}*/ /* end of group MB9BF50x_USB */


/*------------- DMAC Unit ---------------------------------------------------------*/
/** @addtogroup MB9BF50x_DMAC MB9BF50x DMAC Unit
  @{
*/
typedef struct
{
  __IO uint32_t CA;                      /*!< Offset: 0x000 (R/W) DMAC Configuration A Register */
  __IO uint32_t CB;                      /*!< Offset: 0x004 (R/W) DMAC Configuration B Register */
  __IO uint32_t CSA;                     /*!< Offset: 0x008 (R/W) DMAC Transfer Source Address Register */
  __IO uint32_t CDA;                     /*!< Offset: 0x00C (R/W) DMAC Transfer Destination Address Register */
} MB9BF_DMAC_CHN_TypeDef;

typedef struct
{
  __IO uint32_t CR;                      /*!< Offset: 0x000 (R/W) Entire DMAC Configuration Register */
       uint32_t RESERVED[3];
  MB9BF_DMAC_CHN_TypeDef CHN[8];         /*!< Offset: 0x010 (R/W) DMAC chn.0 ~ chn.7 */
} MB9BF_DMAC_TypeDef;
/*@}*/ /* end of group MB9BF50x_DMAC MB9BF50x DMAC Unit */


/*------------- CAN Controller ---------------------------------------------------------*/
/** @addtogroup MB9BF50x_CAN MB9BF50x CAN Controller
  @{
*/
typedef struct
{
  __IO uint16_t CREQ;                    /*!< Offset: 0x000 (R/W) IF Command Request Register */
  __IO uint16_t CMSK;                    /*!< Offset: 0x002 (R/W) IF Command Mask Register */
  union {
      __IO uint32_t MSK;                 /*!< Offset: 0x004 (R/W) IF Mask Register */
    struct {
      __IO uint16_t MSK1;
      __IO uint16_t MSK2;
    };
  };
  union {
      __IO uint32_t ARB;                 /*!< Offset: 0x008 (R/W) IF Arbitration Register */
    struct {
      __IO uint16_t ARB1;
      __IO uint16_t ARB2;
    };
  };
  __IO  uint8_t MCTR;                    /*!< Offset: 0x00C (R/W) IF Message Control Register */
        uint8_t RESERVED0[3];
  union {
      __IO uint32_t DTA_LE;              /*!< Offset: 0x010 (R/W) IF Data A Register (Little endian) */
    struct {
      __IO uint16_t DTA1_LE;
      __IO uint16_t DTA2_LE;
    };
    struct {
      __IO uint8_t  DTA1_0_LE;
      __IO uint8_t  DTA1_1_LE;
      __IO uint8_t  DTA1_2_LE;
      __IO uint8_t  DTA1_3_LE;
    };
  };
  union {
      __IO uint32_t DTB_LE;              /*!< Offset: 0x014 (R/W) IF Data B Register (Little endian) */
    struct {
      __IO uint16_t DTB1_LE;
      __IO uint16_t DTB2_LE;
    };
    struct {
      __IO uint8_t  DTB1_0_LE;
      __IO uint8_t  DTB1_1_LE;
      __IO uint8_t  DTB1_2_LE;
      __IO uint8_t  DTB1_3_LE;
    };
  };
       uint32_t RESERVED1[2];

  union {
      __IO uint32_t DTA_BE;              /*!< Offset: 0x020 (R/W) IF Data A Register (Big endian) */
    struct {
      __IO uint16_t DTA2_BE;
      __IO uint16_t DTA1_BE;
    };
    struct {
      __IO uint8_t  DTA1_3_BE;
      __IO uint8_t  DTA1_2_BE;
      __IO uint8_t  DTA1_1_BE;
      __IO uint8_t  DTA1_0_BE;
    };
  };
       uint32_t RESERVED2[2];
  union {
      __IO uint32_t DTB_BE;              /*!< Offset: 0x020 (R/W) IF Data B Register (Big endian) */
    struct {
      __IO uint16_t DTB2_BE;
      __IO uint16_t DTB1_BE;
    };
    struct {
      __IO uint8_t  DTB1_3_BE;
      __IO uint8_t  DTB1_2_BE;
      __IO uint8_t  DTB1_1_BE;
      __IO uint8_t  DTB1_0_BE;
    };
  };
       uint32_t RESERVED3[2];
} MB9BF_CAN_IF_TypeDef;

typedef struct
{
  __IO uint16_t CTRLR;                   /*!< Offset: 0x000 (R/W) CAN Control Register */
  __IO uint16_t STATR;                   /*!< Offset: 0x002 (R/W) CAN Status Register */
  __IO uint16_t ERRCNT;                  /*!< Offset: 0x004 (R/W) CAN Error Counter */
  __IO uint16_t BTR;                     /*!< Offset: 0x006 (R/W) CAN Bit Timing Register */
  __IO uint16_t INTR;                    /*!< Offset: 0x008 (R/W) CAN Interrupt Register */
  __IO uint16_t TESTR;                   /*!< Offset: 0x00A (R/W) CAN Test Register */
  __IO  uint8_t BRPER;                   /*!< Offset: 0x00C (R/W) CAN Prescaler Extension Register */
        uint8_t RESERVED0[3];
  MB9BF_CAN_IF_TypeDef IF[2];            /*!< Offset: 0x010 (R/W) CAN IF Register */
       uint32_t RESERVED1[4];
  union {
      __IO uint32_t TREQR;               /*!< Offset: 0x080 (R/W) CAN Transmit Request Register */
    struct {
      __IO uint16_t TREQR1;
      __IO uint16_t TREQR2;
    };
  };
       uint32_t RESERVED2[3];
  union {
      __IO uint32_t NEWDT;               /*!< Offset: 0x090 (R/W) CAN New Data Register */
    struct {
      __IO uint16_t NEWDT1;
      __IO uint16_t NEWDT2;
    };
  };
       uint32_t RESERVED3[3];
  union {
      __IO uint32_t INTPND;              /*!< Offset: 0x0A0 (R/W) CAN Interrupt Pending Register */
    struct {
      __IO uint16_t INTPND1;
      __IO uint16_t INTPND2;
    };
  };
       uint32_t RESERVED4[3];
  union {
      __IO uint32_t MSGVAL;              /*!< Offset: 0x0B0 (R/W) CAN Message Valid Register */
    struct {
      __IO uint16_t MSGVAL1;
      __IO uint16_t MSGVAL2;
    };
  };
} MB9BF_CAN_TypeDef;
/*@}*/ /* end of group MB9BF50x_CAN */



/*------------- Clock and Reset Generation ---------------------------------------*/
/** @addtogroup MB9BF50x_CRG MB9BF50x Clock and Reset Generation
  @{
*/
typedef struct
{
  __IO uint32_t SCM_CTL;                 /*!< Offset: 0x000 (R/W) System Clock Mode Control Register */
  __IO uint32_t SCM_STR;                 /*!< Offset: 0x004 (R/W) System Clock Mode Status Register */
  __IO uint32_t STB_CTL;                 /*!< Offset: 0x008 (R/W) Standby Mode Control Register */
  __IO uint32_t RST_STR;                 /*!< Offset: 0x00C (R/W) Reset Cause Register */
  __IO uint32_t BSC_PSR;                 /*!< Offset: 0x010 (R/W) Base Clock Prescaler Register */
  __IO uint32_t APBC0_PSR;               /*!< Offset: 0x014 (R/W) APB0 Prescaler Register */
  __IO uint32_t APBC1_PSR;               /*!< Offset: 0x018 (R/W) APB1 Prescaler Register */
  __IO uint32_t APBC2_PSR;               /*!< Offset: 0x01C (R/W) APB2 Prescaler Register */
  __IO uint32_t SWC_PSR;                 /*!< Offset: 0x020 (R/W) SW-WDGT Clock Prescaler Register */
       uint32_t RESERVED0[1];
  __IO uint32_t TTC_PSR;                 /*!< Offset: 0x028 (R/W) Trace Clock Prescaler Register */
       uint32_t RESERVED1[1];
  __IO uint32_t CSW_TMR;                 /*!< Offset: 0x030 (R/W) Clock Stabilization Wait Time Register */
  __IO uint32_t PSW_TMR;                 /*!< Offset: 0x034 (R/W) PLL Clock Stabilization Wait Time Setup Register */
  __IO uint32_t PLL_CTL1;                /*!< Offset: 0x038 (R/W) PLL Control Register 1 */
  __IO uint32_t PLL_CTL2;                /*!< Offset: 0x03C (R/W) PLL Control Register 2 */
  __IO uint32_t CSV_CTL;                 /*!< Offset: 0x040 (R/W) CSV Control Register */
  __IO uint32_t CSV_STR;                 /*!< Offset: 0x044 (R/W) CSV Status Register */
  __IO uint32_t FCSWH_CTL;               /*!< Offset: 0x048 (R/W) Frequency Detection Window Setting Register (Upper) */
  __IO uint32_t FCSWL_CTL;               /*!< Offset: 0x04C (R/W) Frequency Detection Window Setting Register (Lower) */
  __IO uint32_t FCSWD_CTL;               /*!< Offset: 0x050 (R/W) Frequency Detection Counter Register */
  __IO uint32_t DBWDT_CTL;               /*!< Offset: 0x054 (R/W) Debug Break Watchdog Timer Control Register */
       uint32_t RESERVED2[2];
  __IO uint32_t INT_ENR;                 /*!< Offset: 0x060 (R/W) Interrupt Enable Register */
  __IO uint32_t INT_STR;                 /*!< Offset: 0x064 (R/W) Interrupt Status Register */
  __IO uint32_t INT_CLR;                 /*!< Offset: 0x068 (R/W) Interrupt Clear Register */
} MB9BF_CRG_TypeDef;
/*@}*/ /* end of group MB9BF50x_CRG */


/*------------- Watchdog Timer ---------------------------------------------------*/
/** @addtogroup MB9BF50x_WDT MB9BF50x  Watchdog Timer
  @{
*/
typedef struct
{
  __IO uint32_t LDR;                     /*!< Offset: 0x000 (R/W) Watchdog Timer Load Register */
  __IO uint32_t VLR;                     /*!< Offset: 0x004 (R/W) Watchdog Timer Value Register */
  __IO uint32_t CTL;                     /*!< Offset: 0x008 (R/W) Watchdog Timer Control Register */
  __IO uint32_t ICL;                     /*!< Offset: 0x00C (R/W) Watchdog Timer Clear Register */
  __IO uint32_t RIS;                     /*!< Offset: 0x010 (R/W) Watchdog Timer Interrupt Status Register */
       uint32_t RESERVED0[763];
  __IO uint32_t LCK;                     /*!< Offset: 0xC00 (R/W) Watchdog Timer Lock Register */
} MB9BF_WDT_TypeDef;
/*@}*/ /* end of group MB9BF50x_WDT */


/*------------- Free running Timer -----------------------------------------------*/
/** @addtogroup MB9BF50x_DTIM MB9BF50x Free Running Timer (Dualtimer)
  @{
*/
typedef struct
{
  __IO uint32_t Load;                    /*!< Offset: 0x000 (R/W) Timer Load Register */
  __IO uint32_t Value;                   /*!< Offset: 0x004 (R/W) Timer Value Register */
  __IO uint32_t Control;                 /*!< Offset: 0x008 (R/W) Timer Control Register */
  __IO uint32_t IntClr;                  /*!< Offset: 0x00C (R/W) Timer Interrupt Clear Register */
  __IO uint32_t RIS;                     /*!< Offset: 0x010 (R/W) Timer Interrupt Status Register */
  __IO uint32_t MIS;                     /*!< Offset: 0x014 (R/W) Timer Masked Interrupt Status Register */
  __IO uint32_t BGLoad;                  /*!< Offset: 0x018 (R/W) Timer Background Load Register */
} MB9BF_DTIM_TypeDef;               
/*@}*/ /* end of group MB9BF50x_DTIM */



/*------------- Multifunction Timer ----------------------------------------------*/
/** @addtogroup MB9BF50x_MFT MB9BF50x Multifunction Timer
  @{
*/
typedef struct
{
  __IO uint16_t TCCP;                    /*!< Offset: 0x000 (R/W) FRT ch. Cycle Setting Register */
  __IO uint16_t RESERVED0[1];
  __IO uint16_t TCDT;                    /*!< Offset: 0x004 (R/W) FRT ch. Count Value Register */
  __IO uint16_t RESERVED1[1];
  __IO uint16_t TCSA;                    /*!< Offset: 0x008 (R/W) FRT ch. Control Register A */
  __IO uint16_t RESERVED2[1];
  __IO uint16_t TCSB;                    /*!< Offset: 0x00C (R/W) FRT ch. Control Register B */
  __IO uint16_t RESERVED3[1];
} MB9BF_MFT_TC_TypeDef; 

typedef struct
{
  __IO uint16_t ACCP;                    /*!< Offset: 0x000 (R/W) ADCMP ch. Compare Value Store Register */
  __IO uint16_t RESERVED0[1];
  __IO uint16_t ACCPDN;                  /*!< Offset: 0x004 (R/W) ADCMP ch. Compare Value Store Register */
  __IO uint16_t RESERVED1[1];
} MB9BF_MFT_ACC_TypeDef;

typedef struct
{
  __IO uint32_t OCCP[6];                 /*!< Offset: 0x000 (R/W) OCU Compare Value Store Register */
  __IO  uint8_t OCSA10;                  /*!< Offset: 0x018 (R/W) OCU ch.1, ch.0 Control Register A */
  __IO  uint8_t OCSB10;                  /*!< Offset: 0x019 (R/W) OCU ch.1, ch.0 Control Register B */
  __IO  uint8_t RESERVED0[2];
  __IO  uint8_t OCSA23;                  /*!< Offset: 0x01C (R/W) OCU ch.3, ch.2 Control Register A */
  __IO  uint8_t OCSB23;                  /*!< Offset: 0x01D (R/W) OCU ch.3, ch.2 Control Register B */
  __IO  uint8_t RESERVED1[2];
  __IO  uint8_t OCSA45;                  /*!< Offset: 0x020 (R/W) OCU ch.5, ch.4 Control Register A */
  __IO  uint8_t OCSB45;                  /*!< Offset: 0x021 (R/W) OCU ch.5, ch.4 Control Register B */
  __IO  uint8_t RESERVED2[2];
  __IO  uint8_t RESERVED3[1];
  __IO  uint8_t OCSC;                    /*!< Offset: 0x025 (R/W) OCU ch.5 ~ ch.0 Control Register C */
  __IO  uint8_t RESERVED4[2];
  MB9BF_MFT_TC_TypeDef TC[3];            /*!< Offset: 0x028 (R/W) FRT Block Register */
  __IO  uint8_t OCFS10;                  /*!< Offset: 0x058 (R/W) OCU ch.1, ch.0 Connecting FRT Select Register */
  __IO  uint8_t OCFS32;                  /*!< Offset: 0x059 (R/W) OCU ch.3, ch.2 Connecting FRT Select Register */
  __IO  uint8_t RESERVED5[2];
  __IO  uint8_t OCFS54;                  /*!< Offset: 0x05C (R/W) OCU ch.5, ch.4 Connecting FRT Select Register */
  __IO  uint8_t RESERVED6[3];
  __IO  uint8_t ICFS10;                  /*!< Offset: 0x060 (R/W) ICU ch.1, ch.0 Connecting FRT Select Register */
  __IO  uint8_t ICFS32;                  /*!< Offset: 0x061 (R/W) ICU ch.3, ch.2 Connecting FRT Select Register */
  __IO  uint8_t RESERVED7[2];
       uint32_t RESERVED8[1];
  __IO uint32_t ICCP[4];                 /*!< Offset: 0x068 (R/W) ICU ch. Capture value store Register */
  __IO  uint8_t ICSA10;                  /*!< Offset: 0x078 (R/W) ICU ch.1, ch.0 Control Register A */
  __IO  uint8_t ICSB10;                  /*!< Offset: 0x079 (R/W) ICU ch.1, ch.0 Control Register B */
  __IO  uint8_t RESERVED9[2];
  __IO  uint8_t ICSA23;                  /*!< Offset: 0x07C (R/W) ICU ch.3, ch.2 Control Register A */
  __IO  uint8_t ICSB23;                  /*!< Offset: 0x07D (R/W) ICU ch.3, ch.2 Control Register B */
  __IO  uint8_t RESERVED10[2];
  __IO uint16_t WFTM10;                  /*!< Offset: 0x080 (R/W) WFG ch.1, ch.0 Timer Value Register */
  __IO uint16_t RESERVED11[1];
  __IO uint16_t WFTM32;                  /*!< Offset: 0x084 (R/W) WFG ch.3, ch.2 Timer Value Register */
  __IO uint16_t RESERVED12[1];
  __IO uint16_t WFTM54;                  /*!< Offset: 0x088 (R/W) WFG ch.5, ch.4 Timer Value Register */
  __IO uint16_t RESERVED13[1];
  __IO uint16_t WFSA10;                  /*!< Offset: 0x08C (R/W) WFG ch.1, ch.0 Control Register A */
  __IO uint16_t RESERVED14[1];
  __IO uint16_t WFSA32;                  /*!< Offset: 0x08C (R/W) WFG ch.3, ch.2 Control Register A */
  __IO uint16_t RESERVED15[1];
  __IO uint16_t WFSA54;                  /*!< Offset: 0x08C (R/W) WFG ch.5, ch.4 Control Register A */
  __IO uint16_t RESERVED16[1];
  __IO uint16_t WFIR;                    /*!< Offset: 0x098 (R/W) Interrupt Control Register */
  __IO uint16_t RESERVED17[1];
  __IO uint16_t NZCL;                    /*!< Offset: 0x09C (R/W) NCZL Control Register */
  __IO uint16_t RESERVED18[1];
  MB9BF_MFT_ACC_TypeDef ACC[3];          /*!< Offset: 0x0A0 (R/W) ADCMP Compare Value Store Register */
  __IO  uint8_t ACSB;                    /*!< Offset: 0x0B8 (R/W) ADCMP ch.2 to ch.0 Control Register B */
  __IO  uint8_t RESERVED19[3];
  __IO uint16_t ACSA;                    /*!< Offset: 0x0BC (R/W) ADCMP ch.2 to ch.0 Control Register A */
  __IO uint16_t RESERVED20[1];
  __IO uint16_t ATSA;                    /*!< Offset: 0x0C0 (R/W) ADC Start Trigger Select Register */
  __IO uint16_t RESERVED21[1];
} MB9BF_MFT_TypeDef;
/*@}*/ /* end of group MB9BF50x_MFT */


/*------------- PPG Unit -----------------------------------------------------------*/
/** @addtogroup MB9BF50x_PPG MB9BF50x PPG Unit
  @{
*/
typedef struct
{
        uint8_t RESERVED0[1];
  __IO  uint8_t TTCR0;                   /*!< Offset: 0x000 (R/W) PPG Start Trigger Control Register 0 */
        uint8_t RESERVED1[2];
       uint32_t RESERVED2[1];
        uint8_t RESERVED3[1];
  __IO  uint8_t COMP0;                   /*!< Offset: 0x009 (R/W) PPG Compare Register 0 */
        uint8_t RESERVED4[2];
  __IO  uint8_t COMP2;                   /*!< Offset: 0x00C (R/W) PPG Compare Register 2 */
        uint8_t RESERVED5[4];
  __IO  uint8_t COMP4;                   /*!< Offset: 0x011 (R/W) PPG Compare Register 4 */
        uint8_t RESERVED6[2];
  __IO  uint8_t COMP6;                   /*!< Offset: 0x014 (R/W) PPG Compare Register 6 */
        uint8_t RESERVED7[3];

       uint32_t RESERVED8[1];

  __IO uint32_t TTCR1;                   /*!< Offset: 0x020 (R/W) PPG Start Trigger Control Register 1 */
       uint32_t RESERVED9[1];
        uint8_t RESERVED10[1];
  __IO  uint8_t COMP1;                   /*!< Offset: 0x029 (R/W) PPG Compare Register 1 */
        uint8_t RESERVED11[2];
  __IO  uint8_t COMP3;                   /*!< Offset: 0x02C (R/W) PPG Compare Register 3 */
        uint8_t RESERVED12[4];
  __IO  uint8_t COMP5;                   /*!< Offset: 0x031 (R/W) PPG Compare Register 5 */
        uint8_t RESERVED13[2];
  __IO  uint8_t COMP7;                   /*!< Offset: 0x034 (R/W) PPG Compare Register 7 */
        uint8_t RESERVED14[3];

       uint32_t RESERVED15[50];
  __IO uint16_t TRG;                     /*!< Offset: 0x100 (R/W) PPG Start Register */
       uint16_t RESERVED16[1];
  __IO uint16_t REVC;                    /*!< Offset: 0x104 (R/W) Output Reverse Register */
       uint16_t RESERVED17[1];
       uint32_t RESERVED18[62];

  union {
      __IO uint16_t PPGC01;              /*!< Offset: 0x200 (R/W) PPG Operation Mode Control Register 0,1 */
    struct {
      __IO  uint8_t PPGC0;
      __IO  uint8_t PPGC1;
    };
  };
       uint16_t RESERVED19[1];
  union {
      __IO uint16_t PPGC23;              /*!< Offset: 0x204 (R/W) PPG Operation Mode Control Register 2,3 */
    struct {
      __IO  uint8_t PPGC2;
      __IO  uint8_t PPGC3;
    };
  };
       uint16_t RESERVED20[1];
  __IO uint16_t PRL0;                    /*!< Offset: 0x208 (R/W) PPG Reload Register 0 */
       uint16_t RESERVED21[1];
  __IO uint16_t PRL1;                    /*!< Offset: 0x20C (R/W) PPG Reload Register 1 */
       uint16_t RESERVED22[1];
  __IO uint16_t PRL2;                    /*!< Offset: 0x210 (R/W) PPG Reload Register 2 */
       uint16_t RESERVED23[1];
  __IO uint16_t PRL3;                    /*!< Offset: 0x214 (R/W) PPG Reload Register 3 */
       uint16_t RESERVED24[1];
  __IO  uint8_t GATEC0;                  /*!< Offset: 0x218 (R/W) Gate Function Control Register 0 */
        uint8_t RESERVED25[3];
       uint32_t RESERVED26[9];

  union {
      __IO uint16_t PPGC45;              /*!< Offset: 0x240 (R/W) PPG Operation Mode Control Register 4,5 */
    struct {
      __IO  uint8_t PPGC4;
      __IO  uint8_t PPGC5;
    };
  };
       uint16_t RESERVED27[1];
  union {
      __IO uint16_t PPGC67;              /*!< Offset: 0x244 (R/W) PPG Operation Mode Control Register 6,7 */
    struct {
      __IO  uint8_t PPGC6;
      __IO  uint8_t PPGC7;
    };
  };
       uint16_t RESERVED28[1];
  __IO uint16_t PRL4;                    /*!< Offset: 0x248 (R/W) PPG Reload Register 4 */
       uint16_t RESERVED29[1];
  __IO uint16_t PRL5;                    /*!< Offset: 0x24C (R/W) PPG Reload Register 5 */
       uint16_t RESERVED30[1];
  __IO uint16_t PRL6;                    /*!< Offset: 0x250 (R/W) PPG Reload Register 6 */
       uint16_t RESERVED31[1];
  __IO uint16_t PRL7;                    /*!< Offset: 0x254 (R/W) PPG Reload Register 7 */
       uint16_t RESERVED32[1];
  __IO  uint8_t GATEC4;                  /*!< Offset: 0x258 (R/W) Gate Function Control Register 4 */
        uint8_t RESERVED33[3];
       uint32_t RESERVED34[9];

  union {
      __IO uint16_t PPGC89;              /*!< Offset: 0x280 (R/W) PPG Operation Mode Control Register 8,9 */
    struct {
      __IO  uint8_t PPGC8;
      __IO  uint8_t PPGC9;
    };
  };
       uint16_t RESERVED35[1];
  union {
      __IO uint16_t PPGC1011;            /*!< Offset: 0x284 (R/W) PPG Operation Mode Control Register 10,11 */
    struct {
      __IO  uint8_t PPGC10;
      __IO  uint8_t PPGC11;
    };
  };
       uint16_t RESERVED36[1];
  __IO uint32_t PRL8;                    /*!< Offset: 0x288 (R/W) PPG Reload Register 8 */
       uint16_t RESERVED37[1];
  __IO uint32_t PRL9;                    /*!< Offset: 0x28C (R/W) PPG Reload Register 9 */
       uint16_t RESERVED38[1];
  __IO uint32_t PRL10;                   /*!< Offset: 0x290 (R/W) PPG Reload Register 10 */
       uint16_t RESERVED39[1];
  __IO uint32_t PRL11;                   /*!< Offset: 0x294 (R/W) PPG Reload Register 11 */
       uint16_t RESERVED40[1];
  __IO  uint8_t GATEC8;                  /*!< Offset: 0x298 (R/W) Gate Function Control Register 8 */
        uint8_t RESERVED41[3];
       uint32_t RESERVED42[9];

  union {
      __IO uint16_t PPGC1213;            /*!< Offset: 0x2C0 (R/W) PPG Operation Mode Control Register 12,13 */
    struct {
      __IO  uint8_t PPGC12;
      __IO  uint8_t PPGC13;
    };
  };
       uint16_t RESERVED43[1];
  union {
      __IO uint16_t PPGC1415;            /*!< Offset: 0x2C4 (R/W) PPG Operation Mode Control Register 14,15 */
    struct {
      __IO  uint8_t PPGC14;
      __IO  uint8_t PPGC15;
    };
  };
       uint16_t RESERVED44[1];
  __IO uint32_t PRL12;                   /*!< Offset: 0x2C8 (R/W) PPG Reload Register 12 */
       uint16_t RESERVED45[1];
  __IO uint32_t PRL13;                   /*!< Offset: 0x2CC (R/W) PPG Reload Register 13 */
       uint16_t RESERVED46[1];
  __IO uint32_t PRL14;                   /*!< Offset: 0x2D0 (R/W) PPG Reload Register 14 */
       uint16_t RESERVED47[1];
  __IO uint32_t PRL15;                   /*!< Offset: 0x2D4 (R/W) PPG Reload Register 15 */
       uint16_t RESERVED48[1];
  __IO  uint8_t GATEC12;                 /*!< Offset: 0x2D8 (R/W) Gate Function Control Register 12 */
        uint8_t RESERVED49[3];
       uint32_t RESERVED50[9];
} MB9BF_PPG_TypeDef;
/*@}*/ /* end of group MB9BF50x_PPG */



/*------------- Base Timer I/O Select Function -------------------------------------*/
/** @addtogroup MB9BF50x_BTIMSF MB9BF50x Base Timer I/O Select Function
  @{
*/
typedef struct
{
  __IO  uint8_t BTSEL0123;               /*!< Offset: 0x000 (R/W) I/O Select Register */
        uint8_t RESERVED0[3];
       uint32_t RESERVED1[135];
  __IO  uint8_t BTSEL4567;               /*!< Offset: 0x300 (R/W) I/O Select Register */
        uint8_t RESERVED2[3];
       uint32_t RESERVED3[62];
  __IO uint16_t BTSSSR;                  /*!< Offset: 0x3FC (R/W) Software-based Simultaneous Startup */
       uint16_t RESERVED4[1];
} MB9BF_BTIMSF_TypeDef;
/*@}*/ /* end of group MB9BF50x_BTIMSF */



/*------------- Base Timer ---------------------------------------------------------*/
/** @addtogroup MB9BF50x_BTIM MB9BF50x Base Timer 
  @{
*/
typedef struct
{
  union {
  __IO uint16_t PCSR;                    /*!< Offset: 0x004 (R/W) PWM Cycle Set Register */
  __IO uint16_t PRLL;                    /*!< Offset: 0x004 (R/W) LOW Width Reload Register */
       uint16_t RESERVED0[1];
  };
  union {
  __IO uint16_t PDUT;                    /*!< Offset: 0x004 (R/W) PWM Duty Set Register */
  __IO uint16_t PRLH;                    /*!< Offset: 0x004 (R/W) HIGH Width Reload Register */
  __IO uint16_t DTBF;                    /*!< Offset: 0x004 (R/W) Data Buffer Register */
  };
       uint16_t RESERVED1[1];
  __IO uint16_t TMR;                     /*!< Offset: 0x008 (R/W) Timer Register */
       uint16_t RESERVED2[1];
  __IO uint16_t TMCR;                    /*!< Offset: 0x00C (R/W) Timer Control Register */
       uint16_t RESERVED3[1];
  __IO  uint8_t STC;                     /*!< Offset: 0x010 (R/W) Status Control Register */
  __IO  uint8_t TMCR2;                   /*!< Offset: 0x011 (R/W) Timer Control Register 2 */
        uint8_t RESERVED4[2];
} MB9BF_BTIM_TypeDef;
/*@}*/ /* end of group MB9BF50x_BTIM */



/*------------- Quad Position & Revolution Counter ---------------------------------*/
/** @addtogroup MB9BF50x_QPRC MB9BF50x Quad Position & Revolution Counter
  @{
*/
typedef struct
{
  __IO uint16_t QPCR;                    /*!< Offset: 0x000 (R/W) Quad Position & Revolution Counter Position Count Register */
       uint16_t RESERVED0[1];
  __IO uint16_t QRCR;                    /*!< Offset: 0x004 (R/W) QPRC Revolution Count Register */
       uint16_t RESERVED1[1];
  __IO uint16_t QPCCR;                   /*!< Offset: 0x008 (R/W) QPRC Position Counter Compare Register */
       uint16_t RESERVED2[1];
  __IO uint16_t QPRCR;                   /*!< Offset: 0x00C (R/W) QPRC Position and Revolution Counter Compare Register */
       uint16_t RESERVED3[1];
  __IO uint16_t QMPR;                    /*!< Offset: 0x010 (R/W) QPRC Maximum Position Register */
       uint16_t RESERVED4[1];
  union {
      __IO uint16_t QICR;                /*!< Offset: 0x014 (R/W) QPRC Interrupt Control Register */
    struct {
      __IO  uint8_t QICRL;
      __IO  uint8_t QICRH;
    };
  };
       uint16_t RESERVED5[1];
  union {
      __IO uint16_t QCR;                 /*!< Offset: 0x018 (R/W) QPRC Control Register */
    struct {
      __IO  uint8_t QCRL;
      __IO  uint8_t QCRH;
    };
  };
       uint16_t RESERVED6[1];
  __IO uint16_t QECR;                    /*!< Offset: 0x01C (R/W) QPRC Extension Control Register */
       uint16_t RESERVED7[1];
} MB9BF_QPRC_TypeDef;
/*@}*/ /* end of group MB9BF50x_QPRC */



/*------------- A/D Converter ------------------------------------------------------*/
/** @addtogroup MB9BF50x_ADC MB9BF50x A/D Converter
  @{
*/
typedef struct
{
  __IO  uint8_t ADSR;                    /*!< Offset: 0x000 (R/W) A/D Status Register */
  __IO  uint8_t ADCR;                    /*!< Offset: 0x001 (R/W) A/D Control Register */
        uint8_t RESERVED0[2];
       uint32_t RESERVED1[1];
  __IO  uint8_t SFNS;                    /*!< Offset: 0x008 (R/W) Scan Conversion FIFO Stage Count Setup Register */
  __IO  uint8_t SCCR;                    /*!< Offset: 0x009 (R/W) Scan Conversion Control Register */
        uint8_t RESERVED2[2];
  __IO uint32_t SCFD;                    /*!< Offset: 0x008 (R/W) Scan Conversion FIFO Data Register */
  __IO  uint8_t SCIS2;                   /*!< Offset: 0x010 (R/W) Scan Conversion Input Selection Register */
  __IO  uint8_t SCIS3;                   /*!< Offset: 0x011 (R/W) Scan Conversion Input Selection Register */
        uint8_t RESERVED3[2];
  __IO  uint8_t SCIS0;                   /*!< Offset: 0x014 (R/W) Scan Conversion Input Selection Register */
  __IO  uint8_t SCIS1;                   /*!< Offset: 0x015 (R/W) Scan Conversion Input Selection Register */
        uint8_t RESERVED4[2];
  __IO  uint8_t PFNS;                    /*!< Offset: 0x018 (R/W) Priority Conversion FIFO Stage Count Setup Register */
  __IO  uint8_t PCCR;                    /*!< Offset: 0x019 (R/W) Priority Conversion Control Register */
        uint8_t RESERVED5[2];
  __IO uint32_t PCFD;                    /*!< Offset: 0x01C (R/W) Priority Conversion FIFO Data Register */
  __IO  uint8_t PCIS;                    /*!< Offset: 0x020 (R/W) Priority Conversion Input Selection Register */
        uint8_t RESERVED6[3];
  __IO  uint8_t CMPCR;                   /*!< Offset: 0x024 (R/W) A/D Comparison Control Register */
  __IO  uint8_t CMPD;                    /*!< Offset: 0x025 (R/W) A/D Comparison Value Setup Register */
        uint8_t RESERVED7[2];
  __IO  uint8_t ADSS2;                   /*!< Offset: 0x028 (R/W) Sampling Time Selection Register */
  __IO  uint8_t ADSS3;                   /*!< Offset: 0x029 (R/W) Sampling Time Selection Register */
        uint8_t RESERVED8[2];
  __IO  uint8_t ADSS0;                   /*!< Offset: 0x02C (R/W) Sampling Time Selection Register */
  __IO  uint8_t ADSS1;                   /*!< Offset: 0x02D (R/W) Sampling Time Selection Register */
        uint8_t RESERVED9[2];
  __IO  uint8_t ADST1;                   /*!< Offset: 0x030 (R/W) Sampling Time Setup Register */
  __IO  uint8_t ADST0;                   /*!< Offset: 0x031 (R/W) Sampling Time Setup Register */
        uint8_t RESERVED10[2];
  __IO  uint8_t ADCT;                    /*!< Offset: 0x000 (R/W) Comparison Time Setup Register */
        uint8_t RESERVED11[3];
  __IO  uint8_t PRTSL;                   /*!< Offset: 0x000 (R/W) Priority Conversion Timer Trigger Selection Register */
  __IO  uint8_t SCTSL;                   /*!< Offset: 0x000 (R/W) Scan Conversion Timer Trigger Selection Register */
} MB9BF_ADC_TypeDef;
/*@}*/ /* end of group MB9BF50x_ADC */



/*------------- High-Speed CR Trimming Function ------------------------------------*/
/** @addtogroup MB9BF50x_CRTRIM MB9BF50x High-Speed CR Trimming Function
  @{
*/
typedef struct
{
  __IO  uint8_t MCR_PSR;                 /*!< Offset: 0x000 (R/W) High-speed CR oscillation Frequency Division Setup Register */
        uint8_t RESERVED0[3];
  __IO  uint8_t MCR_FTRM;                /*!< Offset: 0x004 (R/W) High-speed CR oscillation Frequency Trimming Register */
        uint8_t RESERVED1[3];
       uint32_t RESERVED2[1];
  __IO uint32_t MCR_RLR;                 /*!< Offset: 0x00C (R/W) High-speed CR oscillator Register Write-Protect Register */
} MB9BF_CRTRIM_TypeDef;
/*@}*/ /* end of group MB9BF50x_CRTRIM */



/*------------- External Interrupt and NMI Control ---------------------------------*/
/** @addtogroup MB9BF50x_EXTI MB9BF50x External Interrupt and NMI Control
  @{
*/
typedef struct
{
  __IO uint16_t ENIR;                    /*!< Offset: 0x000 (R/W) Enable Interrupt Request Register */
       uint16_t RESERVED0[1];
  __IO uint16_t EIRR;                    /*!< Offset: 0x004 (R/W) External Interrupt Request Register */
       uint16_t RESERVED1[1];
  __IO uint16_t EICL;                    /*!< Offset: 0x008 (R/W) External Interrupt Clear Register */
       uint16_t RESERVED2[1];
  __IO uint32_t ELVR;                    /*!< Offset: 0x00C (R/W) External Interrupt Level Register */
       uint32_t RESERVED3[1];
  __IO  uint8_t NMIRR;                   /*!< Offset: 0x014 (R/W) Non Maskable Interrupt Request Register */
        uint8_t RESERVED4[3];
  __IO  uint8_t NMICL;                   /*!< Offset: 0x018 (R/W) Non Maskable Interrupt Clear Register */
        uint8_t RESERVED5[3];
} MB9BF_EXTI_TypeDef;
/*@}*/ /* end of group MB9BF50x_EXTI */


/*------------- Interrupt Source Check ---------------------------------------------*/
/** @addtogroup MB9BF50x_INTREQ MB9BF50x Interrupt Source Check
  @{
*/
typedef struct
{
  __I  uint32_t DRQSEL;                  /*!< Offset: 0x000 (R/ ) DMA Transfer Request Selection Register */
       uint32_t RESERVED0[3];
  __I  uint32_t IRQMON[49];              /*!< Offset: 0x010 (R/ ) Interrupt Request Batch Read Register */
} MB9BF_INTREQ_TypeDef;
/*@}*/ /* end of group MB9BF50x_INTREQ */



/*------------- GPIO Unit ----------------------------------------------------------*/
/** @addtogroup MB9BF50x_GPIO MB9BF50x GPIO Unit
  @{
*/
typedef struct
{
  __IO uint32_t PFR[8];                  /*!< Offset: 0x000 (R/W) Port Function Setting Register */
       uint32_t RESERVED0[56];
  __IO uint32_t PCR[8];                  /*!< Offset: 0x100 (R/W) Pull-up Setting Register */
       uint32_t RESERVED1[56];
  __IO uint32_t DDR[8];                  /*!< Offset: 0x200 (R/W) Port Input/Output Direction Setting Register */
       uint32_t RESERVED2[56];
  __IO uint32_t PDIR[8];                 /*!< Offset: 0x300 (R/W) Port Input Data Register */
       uint32_t RESERVED3[56];
  __IO uint32_t PDOR[8];                 /*!< Offset: 0x400 (R/W) Port Output Data Register */
       uint32_t RESERVED4[56];
  __IO uint32_t ADE;                     /*!< Offset: 0x500 (R/W) Analog Input Setting Register */
       uint32_t RESERVED5[63];
  __IO uint32_t EPFR[11];                /*!< Offset: 0x600 (R/W) Extended Pin Function Setting Register */
} MB9BF_GPIO_TypeDef;
/*@}*/ /* end of group MB9BF50x_GPIO MB9BF50x GPIO Unit */



/*------------- Low-voltage Detection Circuit --------------------------------------*/
/** @addtogroup MB9BF50x_LVD MB9BF50x Low-voltage Detection Circuit
  @{
*/
typedef struct
{
  __IO  uint8_t CTL;                     /*!< Offset: 0x000 (R/W) Low-voltage Detection Voltage Control Register */
        uint8_t RESERVED0[3];
  __IO  uint8_t STR;                     /*!< Offset: 0x004 (R/W) Low-voltage Detection Interrupt Register */
        uint8_t RESERVED1[3];
  __IO  uint8_t CLR;                     /*!< Offset: 0x008 (R/W) Low-voltage Detection Interrupt Clear Register */
        uint8_t RESERVED2[3];
  __IO uint32_t RLR;                     /*!< Offset: 0x00C (R/W) Low-voltage Detection Voltage Protection Register */
} MB9BF_LVD_TypeDef;
/*@}*/ /* end of group MB9BF50x_LVD */



/*------------- USB Clock Generation Circuit ---------------------------------------*/
/** @addtogroup MB9BF50x_USBCLK MB9BF50x USB Clock Generation Circuit
  @{
*/
typedef struct
{
  __IO  uint8_t UCCR;                    /*!< Offset: 0x000 (R/W) USB Clock Control Register */
        uint8_t RESERVED0[3];
  __IO  uint8_t UPCR1;                   /*!< Offset: 0x004 (R/W) USB-PLL Control Register-1 */
        uint8_t RESERVED1[3];
  __IO  uint8_t UPCR2;                   /*!< Offset: 0x008 (R/W) USB-PLL Control Register-2 */
        uint8_t RESERVED2[3];
  __IO  uint8_t UPCR3;                   /*!< Offset: 0x00C (R/W) USB-PLL Control Register-3 */
        uint8_t RESERVED3[3];
  __IO  uint8_t UPCR4;                   /*!< Offset: 0x010 (R/W) USB-PLL Control Register-4 */
        uint8_t RESERVED4[3];
  __IO  uint8_t UP_STR;                  /*!< Offset: 0x014 (R/W) USB-PLL Macro Status Register */
        uint8_t RESERVED5[3];
  __IO  uint8_t UPINT_ENR;               /*!< Offset: 0x018 (R/W) USB-PLL Interrupt Enable Register */
        uint8_t RESERVED6[3];
  __IO  uint8_t UPINT_CLR;               /*!< Offset: 0x01C (R/W) USB-PLL Interrupt Clear Register */
        uint8_t RESERVED7[3];
  __IO  uint8_t UPINT_STR;               /*!< Offset: 0x020 (R/W) USB-PLL Interrupt Status Register */
       uint32_t RESERVED8[3];
  __IO  uint8_t USBEN;                   /*!< Offset: 0x030 (R/W) USB Enable Request Register */
        uint8_t RESERVED9[3];
} MB9BF_USBCLK_TypeDef;
/*@}*/ /* end of group MB9BF50x_USBCLK */



/*------------- CAN Prescaler ------------------------------------------------------*/
/** @addtogroup MB9BF50x_CANCLK MB9BF50x CAN Prescaler
  @{
*/
typedef struct
{
       uint32_t RESERVED0[18];
        uint8_t RESERVED1[2];
  __IO  uint8_t CANPRE;                  /*!< Offset: 0x04E (R/W) CAN Prescaler Register */
        uint8_t RESERVED2[1];
} MB9BF_CANCLK_TypeDef;
/*@}*/ /* end of group MB9BF50x_CANCLK */



/*------------- Multi-function Serial Interface ------------------------------------*/
/** @addtogroup MB9BF50x_MFS MB9BF50x Multi-function Serial Interface
  @{
*/
typedef struct
{
  __IO  uint8_t SMR;                     /*!< Offset: 0x001 (R/W) Serial Mode Register */
  union {
  __IO  uint8_t SCR;                     /*!< Offset: 0x001 (R/W) Serial Control Register */
  __IO  uint8_t IBCR;                    /*!< Offset: 0x000 (R/W) I2C Bus Control Register */
  };
        uint8_t RESERVED0[2];
  union {
  __IO  uint8_t ESCR;                    /*!< Offset: 0x004 (R/W) Extended Communication Control Register */
  __IO  uint8_t IBSR;                    /*!< Offset: 0x004 (R/W) I2C Bus Status Register */
  };
  __IO  uint8_t SSR;                     /*!< Offset: 0x005 (R/W) Serial Status Register */
        uint8_t RESERVED1[2];
  union {
  __IO uint16_t TDR;                     /*!< Offset: 0x008 (R/W) Transmit Data Register */
  __IO uint16_t RDR;                     /*!< Offset: 0x008 (R/W) Receive Data Register */
  };
       uint16_t RESERVED2[1];
  __IO uint32_t BGR;                     /*!< Offset: 0x00C (R/W) Baud Rate Generator Register */
  __IO  uint8_t ISBA;                    /*!< Offset: 0x010 (R/W) 7-bit Slave Address Register */
  __IO  uint8_t ISMK;                    /*!< Offset: 0x011 (R/W) 7-bit Slave Address Mask Register */
        uint8_t RESERVED3[2];
  __IO uint32_t FCR;                     /*!< Offset: 0x014 (R/W) FIFO Control Register */
  __IO  uint8_t FBYTE1;                  /*!< Offset: 0x018 (R/W) FIFO1 Byte Register */
  __IO  uint8_t FBYTE2;                  /*!< Offset: 0x019 (R/W) FIFO2 Byte Register */
} MB9BF_MFS_TypeDef;
/*@}*/ /* end of group MB9BF50x_MFS */



/*------------- CRC (Cyclic Redundancy Check) --------------------------------------*/
/** @addtogroup MB9BF50x_CRC MB9BF50x CRC (Cyclic Redundancy Check)
  @{
*/
typedef struct
{
  __IO  uint8_t CR;                      /*!< Offset: 0x000 (R/W) CRC Control Register */
        uint8_t RESERVED0[3];
  __IO uint32_t INIT;                    /*!< Offset: 0x004 (R/W) Initial Value Register */
  __IO uint32_t IN;                      /*!< Offset: 0x008 (R/W) Input Data Register */
  __IO uint32_t CRCR;                    /*!< Offset: 0x00C (R/W) CRC Register */
} MB9BF_CRC_TypeDef;
/*@}*/ /* end of group MB9BF50x_CRC */


/*------------- Watch Counter ------------------------------------------------------*/
/** @addtogroup MB9BF50x_WCNT MB9BF50x Watch Counter
  @{
*/
typedef struct
{
  __IO  uint8_t WCRD;                    /*!< Offset: 0x000 (R/W) Watch Counter Read Register */
  __IO  uint8_t WCRL;                    /*!< Offset: 0x001 (R/W) Watch Counter Reload Register */
  __IO  uint8_t WCCR;                    /*!< Offset: 0x002 (R/W) Watch Counter Control Register */
        uint8_t RESERVED0[1];
       uint32_t RESERVED1[3];
  __IO uint16_t CLK_SEL;                 /*!< Offset: 0x010 (R/W) Clock Selection Register */
       uint16_t RESERVED2[1];
  __IO  uint8_t CLK_EN;                  /*!< Offset: 0x014 (R/W) Division Clock Enable Register */
        uint8_t RESERVED3[3];
} MB9BF_WCNT_TypeDef;
/*@}*/ /* end of group MB9BF50x_WCNT */



/*------------- External Bus Interface ---------------------------------------------*/
/** @addtogroup MB9BF50x_EBIF MB9BF50x External Bus Interface
  @{
*/
typedef struct
{
  __IO uint32_t MODE[8];                 /*!< Offset: 0x000 (R/W) Mode Register */
  __IO uint32_t TIM[8];                  /*!< Offset: 0x020 (R/W) Timing Register */
  __IO uint32_t AREA[8];                 /*!< Offset: 0x040 (R/W) Area Register */
} MB9BF_EBIF_TypeDef;
/*@}*/ /* end of group MB9BF50x_EBIF */


#if defined ( __CC_ARM   )
#pragma no_anon_unions
#endif


/******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/

/* Base addresses                                                             */
#define MB9BF_FLASH_BASE        ((     uint32_t)0x00000000)
#define MB9BF_SRAM_BASE         ((     uint32_t)0x20000000)
#define MB9BF_AHB_BASE          ((     uint32_t)0x40000000)
#define MB9BF_APB0_BASE         ((     uint32_t)0x40010000)
#define MB9BF_APB1_BASE         ((     uint32_t)0x40020000)
#define MB9BF_APB2_BASE         ((     uint32_t)0x40030000)

/* AHB peripherals                                                            */
#define MB9BF_FIF_BASE          (MB9BF_AHB_BASE     + 0x000000)
#define MB9BF_USB0_BASE         (MB9BF_AHB_BASE     + 0x040000)
#define MB9BF_DMAC_BASE         (MB9BF_AHB_BASE     + 0x060000)
#define MB9BF_CAN0_BASE         (MB9BF_AHB_BASE     + 0x062000)
#define MB9BF_CAN1_BASE         (MB9BF_AHB_BASE     + 0x063000)

/* APB0 peripherals                                                           */
#define MB9BF_CRG_BASE          (MB9BF_APB0_BASE    + 0x000000)
#define MB9BF_HWWDT_BASE        (MB9BF_APB0_BASE    + 0x001000)
#define MB9BF_SWWDT_BASE        (MB9BF_APB0_BASE    + 0x002000)
#define MB9BF_DTIM1_BASE        (MB9BF_APB0_BASE    + 0x005000)
#define MB9BF_DTIM2_BASE        (MB9BF_APB0_BASE    + 0x005020)

/* APB1 peripherals                                                           */
#define MB9BF_MFT0_BASE         (MB9BF_APB1_BASE    + 0x000000)
#define MB9BF_MFT1_BASE         (MB9BF_APB1_BASE    + 0x001000)
#define MB9BF_PPG_BASE          (MB9BF_APB1_BASE    + 0x004000)
#define MB9BF_BTIM0_BASE        (MB9BF_APB1_BASE    + 0x005000)
#define MB9BF_BTIM1_BASE        (MB9BF_APB1_BASE    + 0x005040)
#define MB9BF_BTIM2_BASE        (MB9BF_APB1_BASE    + 0x005080)
#define MB9BF_BTIM3_BASE        (MB9BF_APB1_BASE    + 0x0050C0)
#define MB9BF_BTIMSF_BASE       (MB9BF_APB1_BASE    + 0x005100)
#define MB9BF_BTIM4_BASE        (MB9BF_APB1_BASE    + 0x005200)
#define MB9BF_BTIM5_BASE        (MB9BF_APB1_BASE    + 0x005240)
#define MB9BF_BTIM6_BASE        (MB9BF_APB1_BASE    + 0x005280)
#define MB9BF_BTIM7_BASE        (MB9BF_APB1_BASE    + 0x0052C0)
#define MB9BF_QPRC_BASE         (MB9BF_APB1_BASE    + 0x006000)
#define MB9BF_ADC0_BASE         (MB9BF_APB1_BASE    + 0x007000)
#define MB9BF_ADC1_BASE         (MB9BF_APB1_BASE    + 0x007100)
#define MB9BF_ADC2_BASE         (MB9BF_APB1_BASE    + 0x007200)
#define MB9BF_CRTRIM_BASE       (MB9BF_APB1_BASE    + 0x00E000)

/* APB2 peripherals                                                           */
#define MB9BF_EXTI_BASE         (MB9BF_APB2_BASE    + 0x000000)
#define MB9BF_INTREQ_BASE       (MB9BF_APB2_BASE    + 0x001000)
#define MB9BF_GPIO_BASE         (MB9BF_APB2_BASE    + 0x003000)
#define MB9BF_LVD_BASE          (MB9BF_APB2_BASE    + 0x005000)
#define MB9BF_USBCLK_BASE       (MB9BF_APB2_BASE    + 0x006000)
#define MB9BF_CANCLK_BASE       (MB9BF_APB2_BASE    + 0x007000)
#define MB9BF_MFS0_BASE         (MB9BF_APB2_BASE    + 0x008000)
#define MB9BF_MFS1_BASE         (MB9BF_APB2_BASE    + 0x008100)
#define MB9BF_MFS2_BASE         (MB9BF_APB2_BASE    + 0x008200)
#define MB9BF_MFS3_BASE         (MB9BF_APB2_BASE    + 0x008300)
#define MB9BF_MFS4_BASE         (MB9BF_APB2_BASE    + 0x008400)
#define MB9BF_MFS5_BASE         (MB9BF_APB2_BASE    + 0x008500)
#define MB9BF_MFS6_BASE         (MB9BF_APB2_BASE    + 0x008600)
#define MB9BF_MFS7_BASE         (MB9BF_APB2_BASE    + 0x008700)
#define MB9BF_CRC_BASE          (MB9BF_APB2_BASE    + 0x009000)
#define MB9BF_WCNT_BASE         (MB9BF_APB2_BASE    + 0x00A000)
#define MB9BF_EBIF_BASE         (MB9BF_APB2_BASE    + 0x00F000)


/******************************************************************************/
/*                         Peripheral declaration                             */
/******************************************************************************/
/* AHB peripherals                                                            */
#define MB9BF_FIF             ((MB9BF_FIF_TypeDef    *) MB9BF_FIF_BASE   )
#define MB9BF_USB0            ((MB9BF_USB_TypeDef    *) MB9BF_USB0_BASE  )
#define MB9BF_DMAC            ((MB9BF_DMAC_TypeDef   *) MB9BF_DMAC_BASE   )
#define MB9BF_CAN0            ((MB9BF_CAN_TypeDef    *) MB9BF_CAN0_BASE  )
#define MB9BF_CAN1            ((MB9BF_CAN_TypeDef    *) MB9BF_CAN1_BASE  )

/* APB0 peripherals                                                           */
#define MB9BF_CRG             ((MB9BF_CRG_TypeDef    *) MB9BF_CRG_BASE   )
#define MB9BF_HWWDT           ((MB9BF_WDT_TypeDef    *) MB9BF_HWWDT_BASE )
#define MB9BF_SWWDT           ((MB9BF_WDT_TypeDef    *) MB9BF_SWWDT_BASE )
#define MB9BF_DTIM1           ((MB9BF_DTIM_TypeDef   *) MB9BF_DTIM1_BASE )
#define MB9BF_DTIM2           ((MB9BF_DTIM_TypeDef   *) MB9BF_DTIM2_BASE )

/* APB1 peripherals                                                           */
#define MB9BF_MFT0            ((MB9BF_MFT_TypeDef    *) MB9BF_MFT0_BASE  )
#define MB9BF_MFT1            ((MB9BF_MFT_TypeDef    *) MB9BF_MFT1_BASE  )
#define MB9BF_PPG             ((MB9BF_PPG_TypeDef    *) MB9BF_PPG_BASE   )
#define MB9BF_BTIM0           ((MB9BF_BTIM_TypeDef   *) MB9BF_BTIM0_BASE )
#define MB9BF_BTIM1           ((MB9BF_BTIM_TypeDef   *) MB9BF_BTIM1_BASE )
#define MB9BF_BTIM2           ((MB9BF_BTIM_TypeDef   *) MB9BF_BTIM2_BASE )
#define MB9BF_BTIM3           ((MB9BF_BTIM_TypeDef   *) MB9BF_BTIM3_BASE )
#define MB9BF_BTIMSF          ((MB9BF_BTIMSF_TypeDef *) MB9BF_BTIMSF_BASE)
#define MB9BF_BTIM4           ((MB9BF_BTIM_TypeDef   *) MB9BF_BTIM4_BASE )
#define MB9BF_BTIM5           ((MB9BF_BTIM_TypeDef   *) MB9BF_BTIM5_BASE )
#define MB9BF_BTIM6           ((MB9BF_BTIM_TypeDef   *) MB9BF_BTIM6_BASE )
#define MB9BF_BTIM7           ((MB9BF_BTIM_TypeDef   *) MB9BF_BTIM7_BASE )
#define MB9BF_QPRC            ((MB9BF_QPRC_TypeDef   *) MB9BF_QPRC_BASE  )
#define MB9BF_ADC0            ((MB9BF_ADC_TypeDef    *) MB9BF_ADC0_BASE  )
#define MB9BF_ADC1            ((MB9BF_ADC_TypeDef    *) MB9BF_ADC1_BASE  )
#define MB9BF_ADC2            ((MB9BF_ADC_TypeDef    *) MB9BF_ADC2_BASE  )
#define MB9BF_CRTRIM          ((MB9BF_CRTRIM_TypeDef *) MB9BF_CRTRIM_BASE)

/* APB2 peripherals                                                           */
#define MB9BF_EXTI            ((MB9BF_EXTI_TypeDef   *) MB9BF_EXTI_BASE  )
#define MB9BF_INTREQ          ((MB9BF_INTREQ_TypeDef *) MB9BF_INTREQ_BASE)
#define MB9BF_GPIO            ((MB9BF_GPIO_TypeDef   *) MB9BF_GPIO_BASE  )
#define MB9BF_LVD             ((MB9BF_LVD_TypeDef    *) MB9BF_LVD_BASE   )
#define MB9BF_USBCLK          ((MB9BF_USBCLK_TypeDef *) MB9BF_USBCLK_BASE)
#define MB9BF_CANCLK          ((MB9BF_CANCLK_TypeDef *) MB9BF_CANCLK_BASE)
#define MB9BF_MFS0            ((MB9BF_MFS_TypeDef    *) MB9BF_MFS0_BASE  )
#define MB9BF_MFS1            ((MB9BF_MFS_TypeDef    *) MB9BF_MFS1_BASE  )
#define MB9BF_MFS2            ((MB9BF_MFS_TypeDef    *) MB9BF_MFS2_BASE  )
#define MB9BF_MFS3            ((MB9BF_MFS_TypeDef    *) MB9BF_MFS3_BASE  )
#define MB9BF_MFS4            ((MB9BF_MFS_TypeDef    *) MB9BF_MFS4_BASE  )
#define MB9BF_MFS5            ((MB9BF_MFS_TypeDef    *) MB9BF_MFS5_BASE  )
#define MB9BF_MFS6            ((MB9BF_MFS_TypeDef    *) MB9BF_MFS6_BASE  )
#define MB9BF_MFS7            ((MB9BF_MFS_TypeDef    *) MB9BF_MFS7_BASE  )
#define MB9BF_CRC             ((MB9BF_CRC_TypeDef    *) MB9BF_CRC_BASE   )
#define MB9BF_WCNT            ((MB9BF_WCNT_TypeDef   *) MB9BF_WCNT_BASE  )
#define MB9BF_EBIF            ((MB9BF_EBIF_TypeDef   *) MB9BF_EBIF_BASE  )


#ifdef __cplusplus
}
#endif

#endif  /* __MB9BF50x_H__ */