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/****************************************************/ /* Release Notes for Version 4.10 */ /* 166/167 DEVELOPMENT TOOL KITS */ /****************************************************/ This file contains release notes and last minute changes relating to the 166/167 Version 4 Tool Chain. Information in this file, the accompanying manual, and software is Copyright (c) 2000 Keil Software and Keil Elektronik. All rights reserved. Contents ======== 1. What's New in C166 Version 4.10? 2. uVision2 Integrated Development Environment 3. New Features in C166 Version 4.10 3.1 Extensions for Accessing Bit Fields 3.2 #pragma PACK & BYTEALIGN Directive 3.3 PREPRINTONLY Directive 3.4 ASMEXPAND, NOASMEXPAND Directive 3.5 USERSTACKDPP3 Directive 3.6 DYNAMICUSRSTK Directive 3.7 NOFRAME Directive 3.8 SAVESYS, SAVEUSR Directive 3.9 OPTIMIZE(7) Directive: Common Tail Merging 3.10 FIXPEC Directive 3.11 New Intrinsic Functions _prior_, _priord_, _pop_ and _push_. 3.12 EXTINS Directive 3.13 COMMONRET Directive 3.14 FIXBFLD Directive 4. New Features in A166 Version 4.10 4.1 64-Bit Values in Numeric Evaluations 4.2 New Directives and Operands to Support 32 and 64 Bit Values 4.3 More Reserved Symbols 4.4 New standard MACRO Processor 4.5 Object File Differences 4.6 Support for ST10 MAC unit 5. New Features in L166 Version 4.10 5.1 WARNING 22: CLASS RANGE NOT GIVEN IN INVOCATION LINE 5.2 DISABLEWARNING Directive 5.3 CINITTAB Directive 5.4 INTNO Directive 6. Example Programs 7. Sales and Technical Support 1. What's new in C166 Version 4.10? We are constantly improving our products. To keep your product current during the Support Period listed in the uVision2 "About" box, download the latest updates from our Web page. If your support is exhausted, contact our Sales department to extend your support period. Compared to Version 4.06, Release V4.10 contains the following enhancements: - Added: support for C161U, ST10F168, ST10F169 and ST10F269 - Added: C166 Directives: FIXBFLD: bypass for the CPU.21 problem documented by Infineon. COMRET: generate only one RET instruction at the function end. - Added: L166 Linker INTNO sub-directives: FILL fill interrupt vector table. NONE do not generate interrupt vector for this function. - Added: uVision2 log file (project.plg) of the last build process. - Reviced: A166 and C166 User's Guide 2. uVision2 Integrated Development Environment This release includes uVision2 for Windows and is an integrated development environment that encapsulates a project manager, integrated make facility, tool configuration, editor, and a powerful debugger. Using our tools, uVision2 writes, compiles, and debugs your programs. The example programs provided are designed to work with uVision2. 3. New Features in C166, Version 4.10 3.1 Extensions for Accessing Bit Fields C166 supports accessing bits in bit-field structures, located in the bdata address space as shown below. struct test { int bit0: 1; int bit1: 1; int bit2: 1; int bit3: 1; int bit4: 1; int bit5: 1; }; struct test bdata t; void main (void) { t.bit0 = 1; if (t.bit1) t.bit2 = t.bit0; } A new memory type has been introduced allowing access to extended bits of the SFR area. The memory type is named 'ebdata' and the memory class is EBDATA or EBDATA0. You can use this bit-addressing mode to access SFR registers of the 166 derivatives by: defining all the CPU SFR registers in a C source file, translating this file with the ORDER directive, and locating the section containing the SFR definitions with the SECTIONS directive. Example: L166 ...SECTIONS (?EB?SFRBIT%EBDATA (0F100H), ?BD?SFRBIT%BDATA (0FF00H)) You can also use the HOLD directive to locate bit-field structures containing members with bit size 1 to the BDATA memory class. The C166 compiler handles accesses to these types of structures the same way as the 166 hardware bits. Example: C166 ... HOLD (bdata 2, near 6) The above locates all structures with bit-field members with < 2 bytes to the bdata memory class and access to these members is performed the same way as bit accesses. 3.2 #pragma PACK & BYTEALIGN Directive The C166 Compiler supports a new directive pack which allows you to generate BYTE-aligned structures with word elements. This is useful when exchanging data structures with other systems where no alignment is required. This directive is compatible with the Microsoft C directive and the usage is shown in the following sample program. Note: The C166 compiler generates considerably more code to access BYTE-aligned WORDs, therefore, the pack(1) directive should only be used when necessary. #pragma pack(1) /* alignment is BYTE for the following structures */ struct s1 { int i1; // i1 has offset 0 char c1; // c1 has offset 2 int i2; // i2 has offset 3 char c2; // c2 has offset 5 int i3; // i3 has offset 6 char z1; // z1 has offset 8 }; #pragma pack() /* reset to default: WORD alignment */ struct s2 { int i1; // i1 has offset 0 char c1; // c1 has offset 2 int i2; // i2 has offset 4 char c2; // c2 has offset 6 int i3; // i3 has offset 8 char z1; // z1 has offset 10 }; #pragma pack(1) assumes that structure pointers point to WORD- aligned structures. If your application uses structure pointers to byte-aligned structures, you must use the #pragma BYTEALIGN directive, in addition to the #pragma pack(1) directive. Examples: #pragma pack(1) /* alignment is BYTE for the following structures */ #pragma BYTEALIGN /* struct pointers point to BYTE-aligned structs */ struct s1 { int i1; // i1 has offset 0 char c1; // c1 has offset 2 struct s2 { int i2; // i2 has offset 3 char c2; // c2 has offset 5 int i3; // i3 has offset 6 } s2; char z1; // z1 has offset 8 } s1; struct s2 *s2p; void main (void) { s2p = &s1.s2; // this is a pointer to a bytealign struct s2p->i2 = 0; // this is an access to a bytealign int } 3.3 PREPRINTONLY Directive When you use the PPO directive (Abbr. PPO), the C166 Compiler stops after pre-processing the C source file. This directive is similar to the PREPRINT directive and has an optional output filename. The default filename for the PREPRINT file is 'basename.I'. Example: C166 myfile.c PREPRINTONLY (myfile.pp) 3.4 ASMEXPAND/NOASMEXPAND Directive The ASMEXPAND/NOASMEXPAND directive (Abbr, AE/NOAE) is comprised of the following: ASMEXPAND The C166 Default setting where all symbols used are expanded, including symbols inside the asm/endasm block. NOASMEXPAND This directive instructs the C166 Compiler to copy text between #pragma asm & #pragma endasm without any pre-processor text expansion. Example: #pragma noasmexpand #define abc 1 #define xx0 2 #define xx1 3 #pragma asm abc equ 2 ; above 'abc' not expanded xx0 equ 10 ; above 'xx0' not expanded #ifdef QQQ xx1 equ 20 #endif #pragma endasm int a = abc, b = xx0, c = xx1; /* expanded anyway. */ 3.5 USERSTACKDPP3 Directive The USERSTACKDPP3 (Abbr. U3) directive changes the assumption made by the C166 Compiler regarding accesses to the USER STACK AREA. By default, the user stack is allocated in the NDATA memory area. You can change the memory class to IDATA or SDATA when using the USERSTACKDPP3 directive. This is accomplished by changing the definition of the ?C_USERSTACK section in the STARTUP.A66 or START167.A66 file as shown below: ?C_USERSTACK SECTION DATA PUBLIC 'IDATA' or ?C_USERSTACK SECTION DATA PUBLIC 'SDATA' In addition, you must change this line: MOV R0,#DPP2:?C_USERSTKTOP to MOV R0,#DPP3:?C_USERSTKTOP 3.6 DYNAMICUSRSTK Directive The DYNAMICUSRSTK (Abbr. DU) directive tells the C166 compiler that your program modifies the user stack area. This is useful to developers creating real-time operating systems that change the user stack area. With this directive, it is possible to have a 16KB user stack for each task. Without this control, the entire user stack area has to reside in the NDATA class (limited to a maximum of 64KB). 3.7 NOFRAME Directive The NOFRAME (Abbr. NOF) directive suppresses the Prolog and Epilog for Interrupt Service Routines (ISRs). Immediately following the directive, #pragma NOFRAME suppresses the Prolog and Epilog for the ISR. This directive is active for only one function. NOFRAME is useful when you write interrupt functions that never return, such as CPU RESET. The example below illustrates the difference between a standard interrupt frame and a NOFRAME ISR. 1 int i1, i2, i3; 2 3 void intr_func1 (void) interrupt 0x21 { 4 1 i1 = i2 * i3; 5 1 } 6 7 #pragma NOFRAME 8 void intr_func2 (void) interrupt 0x22 { 9 1 i1 = i2 * i3; 10 1 } ASSEMBLY LISTING OF GENERATED OBJECT CODE ; FUNCTION intr_func1 (BEGIN RMASK = @0x2030) ; SOURCE LINE # 3 0000 C6871000 SCXT MDC,#010H 0004 EC06 PUSH MDH 0006 EC07 PUSH MDL 0008 ECF4 PUSH R4 000A ECF5 PUSH R5 ; SOURCE LINE # 4 000C F2F50000 R MOV R5,i3 0010 F2F40200 R MOV R4,i2 0014 0B45 MUL R4,R5 0016 F2F40EFE MOV R4,MDL 001A F6070400 R MOV i1,MDL ; SOURCE LINE # 5 001E FCF5 POP R5 0020 FCF4 POP R4 0022 FC07 POP MDL 0024 FC06 POP MDH 0026 FC87 POP MDC 0028 FB88 RETI ; FUNCTION intr_func1 (END RMASK = @0x2030) ; FUNCTION intr_func2 (BEGIN RMASK = @0x2030) ; SOURCE LINE # 8 ; SOURCE LINE # 9 002A F2F50000 R MOV R5,i3 002E F2F40200 R MOV R4,i2 0032 0B45 MUL R4,R5 0034 F2F40EFE MOV R4,MDL 0038 F6070400 R MOV i1,MDL ; SOURCE LINE # 10 003C FB88 RETI ; FUNCTION intr_func2 (END RMASK = @0x2030) 3.8 SAVESYS, SAVEUSR Directives SAVEUSR This directive instructs the C Compiler to save temporary results and saved-by-callee variables to the USER STACK. SAVESYS This C166 directive (which is the default setting) allows you to save temporary results to the SYSTEM STACK. Since the SYSTEM STACK is always in the on- chip RAM, it is faster but the size is limited. Example: 1 extern void func (void); 2 3 #pragma SAVEUSR // Temporary Saves to USER STACK 4 int func1 (int i1, int i2) { 5 1 func (); 6 1 return (i1 + i2); 7 1 } 8 9 //#pragma SAVESYS // Temporary Saves to SYSTEM STACK (default) 10 int func2 (int i1, int i2) { 11 1 func (); 12 1 return (i1 + i2); Example: 1 extern void func (void); 2 3 #pragma SAVESYS // Temporary Saves to SYSTEM STACK (default) 4 int func1 (int i1, int i2) { 5 1 func (); 6 1 return (i1 + i2); 7 1 } 8 9 10 #pragma SAVEUSR // Temporary Saves to USER STACK 11 int func2 (int i1, int i2) { 12 1 func (); 13 1 return (i1 + i2); 14 1 } ASSEMBLY LISTING OF GENERATED OBJECT CODE ; FUNCTION func1 (BEGIN RMASK = @0x7FFF) ; SOURCE LINE # 4 0000 ECFD PUSH R13 0002 ECFE PUSH R14 0004 F0D9 MOV R13,R9 ;---- Variable 'i2' assigned to Register 'R13' ---- 0006 F0E8 MOV R14,R8 ;---- Variable 'i1' assigned to Register 'R14' ---- ; SOURCE LINE # 5 0008 CA000000 E CALLA cc_UC,func ; SOURCE LINE # 6 000C F04E MOV R4,R14 000E 004D ADD R4,R13 ; SOURCE LINE # 7 0010 FCFE POP R14 0012 FCFD POP R13 0014 CB00 RET ; FUNCTION func1 (END RMASK = @0x7FFF) ; FUNCTION func2 (BEGIN RMASK = @0x7FFF) ; SOURCE LINE # 11 0016 88D0 MOV [-R0],R13 0018 88E0 MOV [-R0],R14 001A F0D9 MOV R13,R9 ;---- Variable 'i2' assigned to Register 'R13' ---- 001C F0E8 MOV R14,R8 ;---- Variable 'i1' assigned to Register 'R14' ---- ; SOURCE LINE # 12 001E CA000000 E CALLA cc_UC,func ; SOURCE LINE # 13 0022 F04E MOV R4,R14 0024 004D ADD R4,R13 ; SOURCE LINE # 14 0026 98E0 MOV R14,[R0+] 0028 98D0 MOV R13,[R0+] 002A CB00 RET ; FUNCTION func2 (END RMASK = @0x7FFF) 3.9 OPTIMIZE(7) Directive (Common Tail Merging) The compiler analyzes the generated code function-by-function, and locates common heads and tails. If the compiler detects common code sequences, it replaces one code sequence by a jump instruction to the other equivalent code sequence. This situation frequently occurs with switch/case statements. While analyzing the code, the compiler also replaces sequences with shorter instructions. The default optimizer level is still OPTIMIZE(6) and you must enable OPTIMIZE(7) with the OPTIMIZE directive. 3.10 FIXPEC Directive When using OPTIMIZE(7), the Compiler can generate JMPs to functions (instead of CALLs). If the function begins with a JMP instruction, you could experience a problem with the PEC (on some chip steppings). To avoid this, use the FIXPEC directive to ensure a JMP instruction is never used at the beginning of a function. You can enter this directive under Options-C166-MISC. 3.11 New Intrinsic Functions Intrinsic functions lets you generate the CPU instructions: extern int _prior_ (int); // generates PRIOR instruction extern int _priord_ (long); // generates PRIOR instructions extern int _pop_ (void); // generates a POP instruction extern void _push_ (int); // generates a PUSH instruction 3.12 EXTINS Directive When using EXTINS, the Compiler terminates a EXTS or EXTP instruction sequence at each source line number. This directive improves program single stepping during the debug phase. If you use EXTINS an EXTS or EXTP sequence does not go via several source lines. 3.13 COMMONRET Directive (Abbr. CR) When using COMMONRET, the Compiler will exit a function always on a fixed location. The Compiler will no longer insert RET instructions in the middle of a function. 3.14 FIXBFLD Directive (Abbr. FB) The FIXBFLD directive ensures that the Compiler encloses BFLDL and BFLDH instructions with ATOMIC sequences. This is required to bypass the CPU.21 problem documented by Infineon. You can enter this directive under Options-C166-MISC. The FIXBFLD directive inserts ATOMIC #1 instructions before each BFLDL/BFLDH instruction. If the BFLD instruction is used to access ESFR registers, the EXTR sequence is not combined with other EXTR sequences (exception: this is not the case for the SYSCON1/SYSCON2/ SYSCON3 SFR's; required by the hardware for UNLOCK sequences). If you are using the _bfld_ intrinsic function within _atomic_ (0); _endatomic_ (); blocks, the Compiler does not modify the code, since such sequences usually do not require any bypass. Please check such code blocks carefully and insert if required _nop_ () calls before the _bfld_ () intrinsic call. 4. New Features in A166 Version 4.06 The new Assembler Version 4.06 allows re-translation of the A166, Version 3, assembly modules. However, since Version 4 supports 64-bit expressions, the following incompatibilities could exist when old modules are re-translated. 4.1 64-Bit Values in Numeric Evaluations Overflows can occur in numerical expressions: A166 Version 3 uses 16-bit values A166 Version 4.06 uses 64-bit values Example: Value EQU (8000H + 9000H) / 2 Results: A166 Version 3 = 800H since the result of the addition is a 16-bit Value (1000H) A166 Version 4.06 = Calculates Value as 8800H 4.2 New Directives/Operands to Support 32 and 64-Bit Values Additional methods to define and initialize variables are listed below: Syntax: [name[:]] DB init [, init] [,...] [name[:]] DW init [, init] [,...] [name[:]] DD init [, init] [,...] /* new: DWORD init */ [name[:]] DF32 init [, init] [,...] /* new: 32-bit IEEE float init */ [name[:]] DF64 init [, init] [,...] /* new: 64-bit IEEE float init */ [name[:]] DW init [, init] [,...] [name[:]] DBIT [expression] [name[:]] DS expression [name[:]] DSD expression /* new: DWORD reserve space */ [name[:]] DSB expression [name[:]] DSW expression Added the following operators to A166 Version 4.06: DATA32, DATA64 - for 32-bit and 64-bit constant values WORD0, WORD2, - extract a WORD from an expression WORD4, WORD6 BYTE0 .. BYTE7 - extract a BYTE from an expression 4.3 More Reserved Symbols A166 Version 4.06 has more reserved symbols than A166 Version 3 and allows support for floating-point numbers and DWORD initializations. If your assembly modules use the same names reserved by A166 Version 4, you must change them. For example, the symbol DD may not be used as a label name since it is a new directive. 4.4 New Standard MACRO Processor A166 Version 4.06 supports standard macros also available in Keil A51 and A251. NOMACRO disables all Macro processors NOMPL disables the MPL Macro processor MPL enables the MPL Macro processor 4.5 Object File Differences A166 Version 4.06 uses a new relocatable OMF-166 file format for object files. This new OMF format allows linkage with 32 and 64-bit numbers and is supported with L166 V4.02 and above. The absolute OMF format has not been changed so your existing debugging tools will continue to function without any problems. 4.6 Support for ST10 MAC Unit A166 Version 4.06 now supports all instructions of the ST10 MAC unit. The MAC instructions are enabled with the EXTMAC directive. Example: A166 MYFILE.A66 EXTMAC 5 New Features in L166 Version 4.10 5.1 WARNING 22: CLASS RANGE NOT GIVEN IN INVOCATION LINE When you use memory classes without defining an address range with the CLASSES or DPPUSE directive, the L166 Linker outputs a WARNING 22. Note: This warning is not generated for the following classes: IDATA, IDATA0, BIT, BIT0, BDATA, and BDATA0. 5.2 DISABLEWARNING Directive The DISABLEWARNING (Abbr. DW) directive lets you selectively disable Linker warnings. The following example illustrates how you disable Warning 20 and Warning 22. Example: L166 myfile.obj DISABLEWARNING (20, 22) 5.3 CINITTAB Directive The CINITTAB (Abbr. CI) directive locates the C166 Initialization Sections, ?C_CLRMEMSEC and ?C_INITTAB, to a specified address range. The following example locates sections ?C_CLRMEMSEC and ?C _INITTAB to the address range 0x10000 - 0x18000 (L166 issues a warning if relocation is not possible). Example: L166 myfile.obj CINITTAB (0x10000 - 0x18000) 5.4 INTNO Directive The INTNO directive offers now two new sub-directives: INTNO (interrupt_name (FILL)) fill unused interrupts Example: L166 myfile.obj INTNO (MYINT (FILL)) C-source: myfile.C: void interrupt_trap (void) interrupt MYINT { while (1); } L166 generates for all unused interrupts in your program an interrupt vector to the function 'interrupt_trap'. INTNO (interrupt_name (NONE)) suppress interrupt vector Example: L166 myfile.obj INTNO (MYINT (NONE)) C-source: myfile.C: void interrupt_trap (void) interrupt MYINT { while (1); } L166 will not generate an interrupt vector for this function. You can supply this interrupt vector in assembly programs as follows: EXTERN interrupt_trap:NEAR ; FAR for MEDIUM, LARGE, HLARGE Model int_vector4 section code at 4 ; interrupt vector address vector4 proc jmp FAR interrupt_trap vector4 endp int_vector4 ends 6. Example Programs Several example programs are included in the EXAMPLES directory. These files demonstrate how to use the uVision2 Project Manager and Debugger (ref: uVision2 Quick Start Guide). Now, the Keil Monitor-166 is pre-configured for several commerical boards. You can select the monitor for debugging in many of the example programs. 7. Sales and Technical Support We at Keil Software are dedicated to providing you with the best development tools and technical support. More than 1200 technical support questions and related answers can be accessed with the Keil Online Support Solutions Database: http://www.keil.com/support When a new question arises, the database is updated and published daily to our World-Wide Web page. This process enables you to get technical support at times when our support staff is unavailable. If you experience any problems or have any questions about this product, contact one of our offices for assistance. In the USA... | In Europe... | KEIL Software, Inc. | KEIL Elektronik GmbH 1501 10th St., Suite 110 | Bretonischer Ring 15 Plano, Texas 75074 | D-85630 Grasbrunn, Germany | Sales (800) 348-8051 | Sales +49 89 456040-0 Support (972) 312-1107 | Support +49 89 456040-24 Fax (972) 312-1159 | Fax +49 89 468162 Email sales.us@keil.com | Email sales.intl@keil.com support.us@keil.com | support.intl@keil.com We have more than 60 representatives around the world and distributor's addresses can be found on our World Wide Web page at: http://www.keil.com/ Many of the features of the Keil Online Support Solutions Database are the result of your suggestions. If you have any ideas to improve our web site or Technical Support, please give us your feedback! | ||||||||||
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