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µVision User's Guide

About µVision User Interface Creating Applications Debugging Using the Debugger Simulation Start Debugging Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Event Recorder Filter Component Levels Setup Event Recorder Event Viewer Execution Profiler Instruction Trace Window System Analyzer Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Cortex-M23 and Cortex-M33 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Security Attribution Unit Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Configuring the Trace Hardware Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Code Coverage Export MTB Trace Import for Code Coverage Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

Trace Features

Cortex-M processor-based devices use CoreSight Trace Macrocells to offer a powerful set of trace features. These provide additional means to analyze the program behavior beyond traditional debugger functionality and common debug techniques like "printf"-debugging.

Trace Units and Features

Cortex-M0+ processor-based devices come with an optional Micro Trace Buffer (MTB). The MTB collects information on non-sequential Program Counter changes and allows the reconstruction of the instruction trace.

Cortex-M3 and Cortex-M4 processor-based devices come with the Data Watchpoint and Trace Unit (DWT), the Instrumentation Trace Macrocell (ITM), and the optional Embedded Trace Macrocell (ETM). These provide the following trace features:

  • Timestamps to reconstruct time information from the captured trace data.
  • ITM stimulus ports to capture diagnostic information from instrumented application code, for example "printf"-like debugging without using a communication interface like UART.
  • Trace CPU events to capture software profiling information on the executed program.
  • Exception trace to capture information and exception handler entries, exits, and returns.
  • Data memory access trace.
  • PC Sampling for a coarse capture of the program flow.
  • Full instruction trace (ETM only).
  • Trace capture control during runtime (ETM only).

Trace Interfaces

Cortex-M3 and Cortex-M4 processor-based devices implement one or more of the following optional trace interfaces:

  • The Serial Wire Trace Output (SWO), which forwards the trace data either in a "Manchester" encoding or a "UART/NRZ" encoding. This interface does not support ETM trace data. Streaming Trace is supported without ETM instructions.
  • The 1-to-4-Pin Synchronous Trace Output (TPIU), which supports ETM trace data and has a greater bandwidth than the SWO when using the 4 pin setup. Streaming Trace is supported.
  • The Embedded Trace Buffer (ETB), which provides on-chip storage of trace data using 32-bit RAM. Data is accessed through registers. No additional output-pins are needed. Streaming Trace is not supported.

ETB vs Streaming Trace

Streaming trace is a powerful method of capturing a gap-less stream of trace data from the running target. Besides enabling debuggers to process and display trace data in real-time, it is possible to store the complete trace data from a long target run. This length is only limited by the host PC’s disk space.

Cortex-M3 and Cortex-M4 process-based devices can have an optional ETB placed close to the processor core. It stores the trace data, which are then read via a register interface. However, the ETB has limited storage.

The data stream capture can be controlled and filtered by using tracepoints.

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