Keil Logo

Technical Support

On-Line Manuals

µVision User's Guide

About µVision User Interface Creating Applications Debugging Start Debugging Start Energy Measurement without Debug Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Editor Window Event Recorder Setup Event Recorder Event Recorder Window Events Filtering Event Statistics Window Post-mortem Analysis Event Viewer Execution Profiler Instruction Trace Window System Analyzer Usage tips Save System Analyzer Contents Statistics Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Debug (printf) Viewer Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Trace Exceptions Event Counters ULINKplus Window Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Cortex-M23 and Cortex-M33 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Security Attribution Unit Debug Scripting Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Memory Attribution Specifiers Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Configuring Trace Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

Nested Vector Interrupt Controller

The Nested Vectored Interrupt Controller dialog (for Cortex-M3, Cortex-M4, and Cortex-M7) shows the status of all exceptions. For each exception, the dialog shows the number, source, name, state, and priority.

picture: M347_NVIC

You can select and configure (where applicable) each exception using the following control groups:

Selected Interrupt
Show and change values for a selected interrupt or exception source.

Where

Enable Is the interrupt enable control. This control corresponds to the column E in the list.
Pending Indicates that an interrupt is waiting to be serviced (for some exceptions, this is write-1-only). This control corresponds to the column P in the list.
Active Indicates that this interrupt is being serviced. This control corresponds to the column A in the list.
Priority Is the interrupt priority in the format: <priority value> = <group priority> s<subpriority>. The group priority determines preemption of interrupts. This control corresponds to the column Priority in the list.
The displayed register is NVIC->IPR (for exceptions) or SCB->SHPR (for interrupts).
Each exception is in one of the following states:
  • Inactive - The exception is not active and not pending.
  • Pending - The exception is waiting to be serviced by the processor. An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.
  • Active - An exception that is being serviced by the processor but has not completed. An exception handler can interrupt the execution of another exception handler. In this case, both exceptions are in the active state.
  • Active and pending - The exception is being serviced by the processor and there is a pending exception from the same source.
Interrupt Control & State
The Interrupt Control and State Register (ICSR) at memory address 0xE000ED04:
  • Provides a set-pending bit for the Non-Maskable Interrupt (NMI) exception.
  • Provides set-pending and clear-pending bits for the PENDSV and SYSYTICK exceptions.
  • Shows the exception number of the highest priority pending exception.

Where

SCB->ICSR Content of the ICSR in Hex.
RETTOBASE Indicates whether there are preempted active exceptions:
  • 0 (unchecked) - there are preempted active exceptions to execute
  • 1 (checked) - there are no active exceptions, or the currently-executing exception is the only active exception.
ISRPREEMPT The next pending exception becomes active.
VECTACTIVE Number of the active exception. The number 0 indicates thread mode.
VECTPENDING Shows the number of the enabled exception with the highest priority that is pending, including NMI and faults.
ISRPENDING Exception pending flag. Shows that at least one exception is pending, excluding NMI and faults.
Application Interrupt & Reset Control
The AIRCR at memory address 0xE000ED0C provides endian status for data accesses and reset control of the system.

Where

SCB->AIRC Content of AIRCR in Hex. Default value is 0xFA050000.
VECTRESET Click to perform a vecter reset request. This bit[0] reads as 0. When writing to the register, you must write 0 to this bit, otherwise behavior is unpredictable.
VECTCLRACTIVE Click to clear state information.
PRIGROUP The interrupt priority grouping field is implementation defined. This field determines the split of group priority from subpriority.
SYSRESETREQ Click to raise the external signal for reset, except for debug. Always reads as zero.
ENDIANNESS Shows the significant byte order of a word. Is read-only. When unchecked = little-endian; when checked = big-endian.
Vector Table Offset
Is an optional register located at memory address 0xE000ED08.

Where

SCB->VTOR Contains the vector table settings. Default value is 0x00000000.
TBLOFF Shows the vector table offset from Code or RAM.
TBLBASE Indicates if the table is in Code or RAM.
Software Interrupt Trigger
The Software Trigger Interrupt Register (STIR) is located at memory address 0xE000EF00.
When the USERSETMPEND bit in the System Control and Configuration is set to 1, unprivileged software can access the STIR.

Where

SCB->STIR Contains the STIR value in HEX. Write to the STIR to generate an interrupt from software. Default value is 0x00000000.
INTID Interrupt ID of the interrupt to trigger, in the range [0-239]. For example, a value of 0x03 specifies interrupt IRQ3.

Application access to the NVIC registers

You can access peripheral registers and related functions from the user application. As a minimum, the files <device>.h and <core_cm#>.h define the register layout, base addresses, and access definitions. Refer to CMSIS-CORE – Peripheral Access for details.

Refer to Interrupts and Exceptions (NVIC) for the set of available NVIC functions in CMSIS.

  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.