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µVision User's Guide

About µVision User Interface Creating Applications Debugging Using the Debugger Simulation Start Debugging Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Event Recorder Filter Component Levels Setup Event Recorder Event Viewer Execution Profiler Instruction Trace Window System Analyzer Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Cortex-M23 and Cortex-M33 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Security Attribution Unit Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Configuring the Trace Hardware Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Code Coverage Export MTB Trace Import for Code Coverage Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

Memory Protection Unit

The Memory Protection Unit (MPU) dialog shows the MPU Control Register and the memory map of the MPU, the number of regions with the location, size, access permissions, and memory attributes of each region. An MPU can have:

  • eight separate memory regions, 0-7.
  • additional eight separate memory regions for Cortex-M7, 8-15; depends on implementation.
  • an optional background region.

For a correct configuration of your MPU, refer to the Device Generic User Guide that corresponds to the core of your device.

Accessing a memory location that is prohibited by the MPU generates a MemManage fault.

picture: M347_MPU

You can select and configure (where applicable) each memory region using the following control groups:

List of Memory Regions
Shows the list of memory regions with all attributes. Select a record to change the attributes using the controls in section Selected Region.
Selected Region

Where

ENA Enable or disable the selected memory region.exception. This control corresponds to the column ENA in the list.
ADDR Is the region base address field, represented by ADDR from the Region Base Address Register (MPU_RBAR). MPU_RBAR is located at memory address 0xE000ED9C. The width of the address field is tightly coupled to the value entered for SIZE. For example, if the region size is configured to 4GB in the MPU_RASR, then there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64KB region must be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.
SIZE Specify the size of the MPU protection region. Refer also to description in field ADDR.
SRD Subregion disable bits. The field belongs to register MPU_RASR located at address 0xE000EDA0. For each bit in this field:
  • 0 (unchecked) - Corresponding sub-region is enabled.
  • 1 (checked) - Corresponding sub-region is disabled.
TEX; B; C Memory access attributes.
S Shareable bit.
AP Access permission field.
XN Instruction access disable bit.
  • 0 (unchecked) - Instruction fetches enabled.
  • 1 (checked) - Instruction fetches disabled.
Control

Where

MCU_Control Represents the MPU Control Register (MPU_CTRL) located at memory address 0xE000ED94. The single bit assignments are listed below.
Enable Enable the MPU.
  • 0 (unchecked) - MPU disabled.
  • 1 (checked) - MPU enabled.
HFNMIENA Enable the operation of MPU during HardFault, NMI, and FAULTMASK handlers. When the MPU is enabled:
  • 0 (unchecked) - MPU is disabled during HardFault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit.
  • 1 (checked) - The MPU is enabled during HardFault, NMI, and FAULTMASK handlers. When the MPU is disabled and this bit is set, then the behavior is unpredictable.
PRIVDEFENA Enable privileged software access to the default memory map when the MPU is enabled. If the MPU is disabled, then the processor ignores this bit.
  • 0 (unchecked) - Disable the use of the default memory map. Any access to a memory location not covered by an enabled region causes a fault.
  • 1 (checked) - Enable the use of the default memory map as a background region for privileged software accesses.
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