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µVision User's Guide

About µVision User Interface Creating Applications Debugging Start Debugging Start Energy Measurement without Debug Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Event Recorder Setup Event Recorder Event Recorder Window Events Filtering Event Statistics Window Event Viewer Execution Profiler Instruction Trace Window System Analyzer Usage tips Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Debug (printf) Viewer Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Trace Exceptions Event Counters ULINKplus Window Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Cortex-M23 and Cortex-M33 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Security Attribution Unit Debug Scripting Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Configuring Trace Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

Fault Reports

The Fault Status dialog shows fault exceptions that trap illegal memory accesses and illegal program behavior. The following conditions are detected by fault exception handlers:

  • MemManage - detects memory access violations to regions that are defined in the Memory Management Unit (MPU); for example code execution from a memory region with read/write access only.
  • BusFault - detects memory access errors on instruction fetch, data read/write, interrupt vector fetch, and register stacking (save/restore) on interrupt (entry/exit).
  • UsageFault - detects execution of undefined instructions, unaligned memory access for load/store multiple. When enabled, divide-by-zero and other unaligned memory accesses are detected.
  • HardFault - is the default exception and can be triggered because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism.
  • DebugFault - present only when debug was halted.
  • Auxiliary BusFault - (Cortex-M7 only) shows additional information on BusFaults.

picture: M347_FAULTS

You can configure (where applicable) the processor behavior using the following control groups:

Memory Manage Faults
Shows the MemManage Fault Address (MMFAR) and Status Register (MMFSR) settings.
The MemManage fault status register (MMFSR) indicates a memory access violation detected by the Memory Protection Unit (MPU). Privileged access permitted only. Unprivileged accesses generate a BusFault.

Where

SCB->MMFAR Shows the content of the MemManage Fault Address Register (in HEX) located at memory address 0xE000ED34. The reset value is unknown. The MMFAR contains the address of the location that generated a MemManage fault. This address is valid only when MMARVALID is set to 1.
SCB->CFSR
(MMFSR)
Shows the important bits of the CFSR register that identify the MemManage Fault Status Register (MMFSR). Below fields define the meaningful bits of the MMFSR.
IACCVIOL Instruction access violation flag:
  • 0 (unchecked) = no instruction access violation fault.
  • 1 (checked) = the processor attempted an instruction fetch from a location that does not permit execution. The PC value stacked for the exception return points to the faulting instruction. The processor has not written a fault address to the MMFAR. This fault condition occurs on any attempt of instruction fetches to an XN (eXecute Never) region, even when the MPU is disabled or not present. Potential reasons:
    • Branch to regions that are not defined in the MPU or defined as non-executable.
    • Invalid return due to corrupted stack content.
    • Incorrect entry in the exception vector table.
DACCVIOL Data access violation flag:
  • 0 (unchecked) = no data access violation fault.
  • 1 (checked) = the processor attempted a load or store at a location that does not permit the operation. The PC value stacked for the exception return points to the faulting instruction. The processor has loaded the SCB->MMFAR with the address of the attempted access.
MMRVALID MemManage Fault Address Register (SCB->MMFAR) valid flag:
  • 0 (unchecked) = value in SCB->MMFAR is not a valid fault address.
  • 1 (checked) = SCB->MMFAR holds a valid fault address.
If a MemManage fault occurs and is escalated to a HardFault because of priority, the HardFault handler must set this bit to 0. This prevents problems on return to a stacked active MemManage fault handler whose SCB->MMFAR value has been overwritten.
MUNSTKERR MemManage fault on unstacking for a return from exception:
  • 0 (unchecked) = no unstacking fault.
  • 1 (checked) = unstacking for an exception return has caused one or more access violations. This fault is chained to the handler which means that the original return stack is still present. The processor has not adjusted the SP from the failing return, and has not performed a new save. The processor has not written a fault address to the SCB->MMFAR. Potential reasons:
    • Stack pointer is corrupted.
    • MPU region for the stack changed during execution of the exception handler.
MSTKERR MemManage fault on stacking for exception entry:
  • 0 (unchecked) = no stacking fault.
  • 1 (checked) = stacking for an exception entry has caused one or more access violations. The SP is still adjusted but the values in the context area on the stack might be incorrect. The processor has not written a fault address to the SCB->MMFAR. Potential reasons:
    • Stack pointer is corrupted or not initialized.
    • Stack is reaching a region not defined by the MPU as read/write memory.
Bus Faults
Shows the BusFault Address (BFAR) and BusFault Status Register (BFSR) settings.
The BusFault Status Register (BFSR), located at memory address 0xE000ED29 shows the status of bus errors resulting from instruction fetches and data accesses and indicates memory access faults detected during a bus operation. Privileged access permitted only. Unprivileged accesses generate a BusFault.

Where

SCB->BFAR The BusFault Address Register (BFAR), located at memory address 0xE000ED38, contains the address (in Hex) of the location that generated a precise data access BusFault. This address is valid only when BFARVALID is set to 1.
SCB->CFSR
(BFSR)
Shows the important bits of the CFSR register that identify the BusFault Status Register (BFSR). Below fields define the meaningful bits of the BFSR.
IBUSERR Instruction bus error. Records whether a BusFault on an instruction prefetch has occurred.
  • 0 (unchecked) = no instruction bus error.
  • 1 (checked) = instruction bus error. The processor detects the instruction bus error on prefetching an instruction, but it sets the IBUSERR flag to 1 only if it attempts to issue the faulting instruction. When the processor sets this bit, it does not write a fault address to SCB->BFAR. Potential reasons:
    • Branch to invalid memory regions for example caused by incorrect function pointers.
    • Invalid return due to corrupted stack pointer or stack content.
    • Incorrect entry in the exception vector table.
PRECISERR Precise data bus error:
  • 0 (unchecked) = no precise data bus error.
  • 1 (checked) = a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. When the processor sets this bit, it writes the faulting address to SCB->BFAR.
IMPRECISERR Imprecise data bus error:
  • 0 (unchecked) = no imprecise data bus error
  • 1 (checked) = a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. When the processor sets this bit, it does not write a fault address to SCB->BFAR. This is an asynchronous fault.
UNSTKERR BusFault on unstacking for a return from exception:
  • 0 (unchecked) = no unstacking fault.
  • 1 (checked) = unstack for an exception return has caused one or more BusFaults. This fault is chained to the handler. This means that when the processor sets this bit, the original return stack is still present. The processor does not adjust the SP from the failing return, does not performed a new save, and does not write a fault address to SCB->BFAR.
STKERR BusFault on stacking for exception entry:
  • 0 (unchecked) = no stacking fault.
  • 1 (checked) = stacking for an exception entry has caused one or more BusFaults. When the processor sets this bit, the SP is still adjusted but the values in the context area on the stack might be incorrect. The processor does not write a fault address to the BFAR. Potential reasons:
    • Stack pointer is corrupted or not initialized.
    • Stack is reaching an undefined memory region.
BFARVALID BusFault Address Register (BFAR) valid flag:
  • 0 (unchecked) = value in BFAR is not a valid fault address 1 (checked) = BFAR holds a valid fault address. The processor sets this bit after a BusFault where the address is known. Other faults can set this bit to 0, such as a MemManage fault occurring later. If a BusFault occurs and is escalated to a HardFault because of priority, the HardFault handler must set this bit to 0.
Usage Faults
The UsageFault Status Register (UFSR) contains the status for some instruction execution faults, and for data access. Privileged access permitted only. Unprivileged accesses generate a BusFault.

Where

SCB->CFSR
(UFSR)
Shows the content of the UFSR register (in HEX) located at memory address 0xE000ED2A. Reset value is 0x00000000.
UNDEFINSTR Undefined instruction.
  • 0 (unchecked) = no undefined instruction.
  • 1 (checked) = attempt to execute an undefined instruction. When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. Potential reasons:
    • Use of instructions not supported in the Cortex-M device.
    • Bad or corrupted memory contents.
INVSTATE Invalid state.
  • 0 (unchecked) = no invalid state.
  • 1 (checked) = attempt to execute an instruction that makes illegal use of the Execution Program Status Register (EPSR). When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the EPSR. Potential reasons:
    • Loading a branch target address to PC with LSB=0.
    • Stacked PSR corrupted during exception or interrupt handling.
    • Vector table contains a vector address with LSB=0.
INVPC Invalid PC load UsageFault, caused by an invalid EXC_RETURN value:
  • 0 (unchecked) = no invalid PC load.
  • 1 (checked) = the processor has attempted to load an illegal EXC_RETURN value to the PC as a result of an invalid context switch. When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. Potential reasons:
    • Invalid return due to corrupted stack pointer, link register (LR), or stack content.
    • ICI/IT bit in PSR invalid for an instruction.
NOCP No coprocessor. The processor does not support coprocessor instructions:
  • 0 (unchecked) = no UsageFault caused by attempting to access a coprocessor.
  • 1 (checked) = attempt to access a coprocessor that does not exist.
UNALIGNED Unaligned access UsageFault.
  • 0 (unchecked) = no unaligned access fault, or unaligned access trapping not enabled.
  • 1 (checked) = unaligned memory access. Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the SCB->CCR. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of the UNALIGN_TRP bit.
DIVBYZERO Divide by zero UsageFault.
  • 0 (unchecked) = no divide by zero fault, or divide by zero trapping not enabled.
  • 1 (checked) = execution of an SDIV or UDIV instruction with a divisor of 0. When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Enable trapping of divide by zero by setting the DIV_0_TRP bit in the SCB->CCR to 1.
Hard Faults
Shows the settings of the HardFault Status Register (HFSR). Privileged access permitted only. Unprivileged accesses generate a BusFault.

Where

SCB->HFSR Shows the content of the HFSR register (in HEX) located at memory address 0xE000ED2C. Reset value is 0x00000000. This register is read, write to clear. This means, bits in the register read normally, but writing 1 to any bit clears that bit to 0.
VECTTBL Indicates a fault because of an vector table read error during exception processing:
  • 0 (unchecked) = no vector table read.
  • 1 (checked) = on vector table read. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This error is always a HardFault.
FORCED Indicates a forced HardFault generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled.
  • 0 (unchecked) = no forced HardFault.
  • 1 (checked) = forced and escalated HardFault. When this bit is set, the HardFault handler must read the other fault status registers to find the cause of the fault.
DWTRAP The Data Watchpoint (DW) flag stops the processor at the current instruction or at the next instruction.
  • 0 (unchecked) = no DW match.
  • 1 (checked) = DW match.
DEBUGEVT Indicates when a debug event has occurred. When writing to the register, you must write 0 to this bit, otherwise the behavior is unpredictable.
  • 0 (unchecked) = no debug event occurred.
  • 1 (checked) = debug event occurred, DFSR has been updated.
Debug Faults
Shows the Debug Fault Status Register (DFSR) settings.

Where

SCB->DFSR Shows the content of the DFSR register (in HEX) located at memory address 0xE000ED30. Reset value is 0x00000000. The register is sticky read/write clear. This means, it can be read normally. Writing a 1 to a bit clears that bit.
HALTED
  • 0 (unchecked) = no halt request.
  • 1 (checked) = halt requested by DAP or halted with a debugging step command.
BKPT The BKPT flag is set by the execution of the BKPT instruction or on an instruction whose address triggered the breakpoint comparator match. When the processor has halted, the return PC points to the address of the breakpointed instruction.
  • 0 (unchecked) = no BKPT instruction or hardware breakpoint match.
  • 1 (checked) = BKPT instruction or hardware breakpoint match.
DWTRAP The Data Watchpoint (DW) flag stops the processor at the current instruction or at the next instruction.
  • 0 (unchecked) = no DW match.
  • 1 (checked) = DW match.
VCATCH When the VCATCH flag is set, a flag in the Debug Exception and Monitor Control Register is also set to indicate the type of vector catch.
  • 0 (unchecked) = no vector catch occurred.
  • 1 (checked) = vector catch occurred.
EXTERNAL When the External debug request flag is set, then the processor stops on next instruction boundary.
  • 0 (unchecked) = no EDBGRQ has occurred.
  • 1 (checked) = EDBGRQ has halted the core.
Auxiliary Bus Fault
Shows the optional Auxiliary BusFault Status Register (ABFSR) settings (Cortex-M7 only).

Where

SCB->AFSR Shows the content of the ABFSR register (in HEX) located at memory address 0xE000EFA8. Reset value is 0x00000000. The ABFSR stores information on the source of asynchronous BusFaults. If a BusFault has occurred, the fault handler can read this register to determine which bus interface triggered the fault, and if the source is the AXIM interface, which error type is received. The ABFSR[4:0] fields remains valid until cleared by writing to the ABFSR with any value. The interfaces might not be present on your implementation.
AXIMTYPE Indicates the type of fault on the AXIM interface. The values are valid only when AXIM = 1.
ITCM Asynchronous fault on ITCM interface.
DTCM Asynchronous fault on DTCM interface.
AHBP Asynchronous fault on AHBP interface.
AXIM Asynchronous fault on AXIM interface.
EPPB Asynchronous fault on EPPB interface.

Application access to fault reports

You can access peripheral registers and related functions from the user application. As a minimum, the files <device>.h and <core_cm#>.h define the register layout, base addresses, and access definitions. Refer to CMSIS-CORE – Peripheral Access for details.

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