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µVision User's Guide

About µVision User Interface Creating Applications Debugging Using the Debugger Simulation Start Debugging Application Program Execution Debug Windows and Dialogs Breakpoints Window Call Stack and Locals Window Code Coverage Command Window Component Viewer Disassembly Window Event Recorder Filter Component Levels Setup Event Recorder Event Viewer Execution Profiler Instruction Trace Window System Analyzer Restrictions Logic Analyzer Setup Setup in Detail Restrictions Cortex-M Trace Configuration Memory Map Memory Window Performance Analyzer Registers Window Serial Window Symbols Window System Viewer Adding System Viewer Windows System and Thread Viewer Thread States Toolbox Trace Data Window Trace Navigation Watch Window Core Peripherals Cortex-M0 and Cortex-M0+ Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports (Cortex-M0+ only) Cortex-M3, Cortex-M4, and Cortex-M7 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Cortex-M23 and Cortex-M33 Nested Vector Interrupt Controller System Control and Configuration System Tick Timer Fault Reports Memory Protection Unit Security Attribution Unit Expressions Constants System Variables Peripheral Variables I/O Ports Serial Ports Program Variables (Symbols) Fully Qualified Symbols Non-Qualified Symbols Literal Symbols Using Symbols Line Numbers Bit Addresses Type Specifications Operators Differences between µVision and C Expression Examples Code and Data Trace (Cortex-M) Trace Features Tracepoint Expressions Tracepoint Intrinsics Tracepoint Limitations Configuring the Trace Hardware Tracepoint Marks Tips and Tricks Review Peripherals and CPU Configuration Simulate I/O Ports Simulate Interrupts and Clock Inputs Simulate external I/O Devices Assign Serial I/O to a PC COM Port Check Illegal Memory Access Command Input from File Preset I/O Ports or Memory Contents Write Debug Output to a File Keyboard Shortcuts TPIU Initialization after RESET (Cortex-M) Prevent Opening Files Show Japanese Messages Code Coverage Export MTB Trace Import for Code Coverage Debug Commands Debug Functions Simulation Flash Programming Dialogs Utilities Command Line Example Programs Appendix

Security Attribution Unit

The Security Attribution Unit (SAU) dialog shows the SAU Control Register (SAU_CTRL) and related characteristics.

picture: ARMv8_SAU

You can select and configure (where applicable) each memory region using the following control groups:

Enable
Enable or disable the SAU. This bit belongs to the SAU_CTRL register.
  • 0 (unchecked) - SAU is disabled.
  • 1 (checked) - SAU is enabled.
when disabled
Sets the bit All Non-secure (ALLNS) of the SAU_CTRL and controls if the memory is marked as Non-secure or Secure. Applies only when SAU is disabled.
SAU_CTRL
Shows the content of the SAU_CTRL register (in Hex). The register is located at memory address 0xE000EDD0.
SAU Address Regions
Shows a list of SAU region definitions with characteristics from:
  • SAU Region Number Register (SAU_RNR), located at address 0xE000EDD8.
  • SAU Region Base Address Register (SAU_RBAR) located at address 0xE000EDDC
  • SAU Region Limit Address Register (SAU_RLAR) located at address 0xE000EDE0.
  • SAU Type Register (SAU_TYPE), located at address 0xE000EDD4.

Where

# Shows the number of implemented SAU regions.
EN Enable bit of the SAU region.
  • 0 (unchecked) - Region disabled.
  • 1 (checked) - Region enabled.
Start Address Is the region base address.
End Address Is the upper limit of the memory region.
Regison is Set the access mode of the SAU region.
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