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Compensate Signal Delays

Compensate Signal Delays explains the steps to align trace data streams when synchronization fails due to chip or PCB hardware design.

If the actions outlined in Trace Data Not Synchronized do not deliver the expected result, continue with the steps below:

  1. Open the Trace Configuration and adjust the Trace Port settings. Change the CLK value to delay the TRACECLK signal and start debugging and tracing the application. A good initial delay is 2.0 ns. Continue changing this value until the expected results are shown. In most cases, this step should deliver the expected data.
  2. Change the D0..D3 options to delay each individual signal arriving at the data pins TRACEDATA[0]..TRACEDATA[3].
  3. Finally, when the steps above show no positive result, use an oscilloscope to measure the signal delays at the trace pins and compensate the hardware delays using the options in µVision. The picture below shows the setup and hold timing of trace signals with respect to TRACECLK.

    Signal Requirements
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