DIP Switches

A DIP switch is ON when it is positioned toward the center of the MCBXC167 board. A DIP switch is OFF when it is positioned toward the COM1 port.

The DIP switch settings used to configure the MCBXC167 board are:

Default DIP Switch Setting

DIP Switch On-chip

	BSL	CSSEL		SALSEL		CLKCFG			BSO	EA
Switch	1	2	3	4	5	6	7	8	9	10
ON		X	X	X	X	X		X
OFF	X						X		X	X

The following describes each of the configuration switches.

BSL (Switch 1): Bootstrap Loader for Off-chip Memory (Default OFF)

When the EA switch 10 is ON, switch 1 enables the Bootstrap Loader of the XC167 devices:

OFF: Bootstrap mode is disabled. User code is executed from external Flash ROM.
ON: Bootstrap mode is enabled (note that EA must be ON). The device waits for a command via the COM interface. The bootstrap loader allows you to download the Monitor-166 for program debugging with µVision. Monitor downloading performs automatically when you start the µVision debugger.

CSSEL (Switches 2 and 3): Number of Chip Select Lines (Default: ON ON)

The CSSEL DIP switches define the number of active chip select signals.

The CS/ signals generate on Port 6 and perform as chip select lines for the RAM, Flash ROM and Ethernet devices on the MCBXC167 board.

CSSEL D9 D10	Chip Select Lines	Description
OFF OFF	Five: CS4-CS0	Provides two additional user CS lines.
ON OFF	None	All Port 6 pins are available. This requires board modification.
OFF ON	Two: CS1-CS0
ON ON	Three: CS2-CS0	Default setting for the MCBXC167 Board.

SALSEL (Switches 4 and 5): Number of Segment Address Lines (Default: ON ON)

The SALSEL DIP switches define the number of active segment address lines on Port 4.

If you use the CAN interface, only A19 - A16 may be enabled since the other Port 4 pins are used for CAN I/O. Even if some segment address lines are disabled, the XC167 uses a complete 24-bit address internally. The full address space can still be used via the CS/ (chip select) signals.

SALSEL D11 D12	Segment Address Lines	Directly Accessible Address Space
OFF OFF	Two: A17 .. A16	256 KByte
ON OFF	Eight: A23 .. A16	16 MByte (Maximum)
OFF ON	None	64 KByte (Minimum)
ON ON	Four: A19 .. A16	1 MByte (default setting)

CLKCFG (Switches 6, 7, and 8): Clock Configuration (Default: ON OFF ON)

The CLKCFG DIP switches configure the internal CPU clock.

The XC167 device uses an on-chip PLL that generates the internal CPU clock from the external 8MHz XTAL. The following table shows the possible internal CPU clock speeds for a standard 10MHz crystal. Check the datasheet for the device you use to determine the maximum possible internal CPU clock speed.

CLKCFG D13 D14 D15	CPU Clock	XTAL/Osc. Range	Frequency with 8MHz XTAL
OFF OFF OFF	XTAL × 3.0	8.3 - 12.5 MHz	n/a
ON OFF OFF	XTAL × 4.5	5.6 - 8.3 MHz	36MHz
OFF ON OFF	XTAL × 2.0	12.5 -18.7 MHz	n/a
ON ON OFF	XTAL × 5.0	4 - 6 MHz	n/a
OFF OFF ON	XTAL × 1.0	4 - 40 MHz	8MHz
ON OFF ON	XTAL × 2.5	8 - 12 MHz	20MHz (default)
OFF ON ON	XTAL × 2.5	12 - 16 MHz	n/a
ON ON ON	XTAL × 0.5	4 - 50 MHz	4MHz

Note

The CLKCFG DIP switch setting can be overwritten in the START_V2.A66 configuration file by the PLLCON settings.

BSO (Switch 9): Bootstrap Loader for On-chip Flash ROM (Default: OFF)

When the EA switch is OFF this switch enables the Bootstrap loader of the XC167 devices:

OFF: Bootstrap mode is disabled.
ON: Bootstrap mode is enabled (note that EA must be OFF). The device waits for a command via the COM interface.

EA (Switch 10): External Access of Program Code (Default: OFF)

The EA configuration switch enables External Access of program code:

OFF: the XC167 CPU begins executing program code from the on-chip Flash.
ON: the execution begins from external memory (typical Flash ROM).