 LX51 User's Guide | |
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LX51 User's Guide
LX51 Introduction Purpose of the Linker
Combining Modules Searching Libraries Combining Segments Locating Segments Overlaying Data Memory Resolving Externals Calculating Addresses Generating an Object File Generating a Listing File Memory Classes BIT, DATA, and IDATA CODE and CONST XDATA HCONST HDATA Classic 8051 Devices Extended 8051 Devices NXP 51MX Devices Segments Linking Programs Locating Program Objects Data Overlaying Code Banking Real-Time Programs Error MessagesNXP 51MX Devices
The NXP 51MX architecture provides a universal memory map that includes all memory classes in a single, contiguous 16MB address space.
BIT, DATA, IDATA, and EDATA
The BIT, DATA, and IDATA memory classes comprise the on-chip memory of the 51MX architecture. They are contained in the EDATA memory class.
CODE, ECODE, EDATA, XDATA, and HDATA
The NXP 51MX address space is comprised of 8 MBytes of program memory (the ECODE memory class) and 8 MBytes of data memory (the HDATA memory class).
The ECODE memory class contains the CODE memory class (which is still limited to 64 KBytes) and up to 64 code banks that may be used for code banking applications.
The HDATA memory class includes XDATA (which is still limited to 64 KBytes), EDATA (which is limited to 64 KBytes), and up to 8 MBytes of far variables.
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