J-Link/J-Trace User's Guide
CoreSight™ is an on-chip debugging and tracing technology designed
by ARM. The device manufacturer can implement CoreSight features in
CoreSight features can be accessed through a JTAG or Serial Wire
interface. Debugging in JTAG and Serial Wire mode at the same time is
not possible. Cortex-M processor-based devices can include a:
The debug interface offers two modes:
JTAG Debug is the industry-standard interface
that allows device chaining.
Serial Wire Debug is a 2-pin interface with an
optional Serial Wire Trace Output. In contrast to JTAG, devices
cannot be chained.
The Debug Interface communicates with the
Run Control: allows to start, stop, and single-step
through the source code.
Breakpoint Unit: allows to set breakpoints even while
the processor is running.
Memory Access Unit: allows to read or write to memory
and peripheral registers even while the program is running.
Trace Port Interface
The Trace Port Interface encodes and provides trace information
via two possible interfaces:
The Serial Wire Trace Output pin (SWO) can be
used in Serial Wire Debug mode only.
The 4-Pin Trace Output has a greater bandwidth
than Serial Wire Trace Output and uses 5 functional pins. It is the
only way to output ETM trace data.
The Trace Port Interface communicates with the
Embedded Trace Macrocell (ETM): can be used for
instruction tracing to debug historical sequences, for software
profiling, and code coverage analysis. ETM data are output through
an extra 4-bit interface.
Instrumentation Trace Macrocell (ITM): provides
application information like debug printf, RTOS information, unit
test, or UML annotation.
Data Watchpoint & Trace Unit (DWT): provides PC
sampling, event counters, timing, and interrupt execution
information. In addition, it allows access-breakpoints for up to
four memory addresses.
Serial Wire-JTAG Switch (SWJ)
J-Link/J-Trace generate sequences to automatically switch between
Serial Wire Debug and JTAG Debug mode.
Two standard connectors are available:
Debug for JTAG or Serial Wire Debug and Trace.
Debug+ETM connector adds to the Cortex Debug connector ETM
Check the manufacturer's device data sheet to read which
CoreSight features have been implemented.