| ||||
| Home Products Download Events Support | ||||
Technical Support
On-Line Manuals
8051 Instruction Set Manual
Architecture Overview Memory Classes and Layout 
Classic 8051 Classic 8051 Memory Layout Extended 8051 Variants Extended 8051 Memory Layout NXP 80C51MX NXP 80C51MX Memory Layout 251 Architecture 251 Memory Layout CPU Registers 8051 Variants 251 Architecture Program Status Word (PSW) Opcodes 
InstructionsNXP 80C51MX Memory Layout
The NXP 80C51MX memory layout, shown in the following figure, provides a universal memory map that includes all memory types in a single 16MB address region. The memory layout of the NXP 80C51MX is shown below:
The 80C51MX offers new MCU instructions that provide a new addressing mode, called Universal Pointer addressing. Two Universal Pointer registers PR0 and PR1 are available. PR0 is composed of registers R1, R2, and R3. PR1 is composed of registers R5, R6, and R7. These new Universal Pointer registers hold a 24-bit address that is used together with the EMOV instruction to address the complete 16MB memory.
| Contact Site Map Press Privacy | Copyright © 2012 ARM Ltd and ARM Germany GmbH. All rights reserved. |
