Keil Logo

NXP 80C51MX Memory Layout

The NXP 80C51MX memory layout, shown in the following figure, provides a universal memory map that includes all memory types in a single 16MB address region. The memory layout of the NXP 80C51MX is shown below:

80C51MX Memory Layout

The 80C51MX offers new MCU instructions that provide a new addressing mode, called Universal Pointer addressing. Two Universal Pointer registers PR0 and PR1 are available. PR0 is composed of registers R1, R2, and R3. PR1 is composed of registers R5, R6, and R7. These new Universal Pointer registers hold a 24-bit address that is used together with the EMOV instruction to address the complete 16MB memory.

  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.