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8051 Instruction Set Manual
Architecture Overview Memory Classes and Layout 
Classic 8051 Classic 8051 Memory Layout Extended 8051 Variants Extended 8051 Memory Layout NXP 80C51MX NXP 80C51MX Memory Layout 251 Architecture 251 Memory Layout CPU Registers 8051 Variants 251 Architecture Program Status Word (PSW) Opcodes 
InstructionsClassic 8051
The following table shows the memory classes used for programming the classic 8051 architecture. These memory classes are available when you are using the A51 macro assembler and the BL51 linker/locater.
| Memory Class | Address Range | Description |
|---|---|---|
| DATA | D:00 – D:7F | Direct addressable on chip RAM. |
| BIT | D:20 – D:2F | bit addressable RAM; accessed bit instructions. |
| IDATA | I:00 – I:FF | Indirect addressable on chip RAM; can be accessed with @R0 or @R1. |
| XDATA | X:0000 – X:FFFF | 64 KB RAM (read/write access). Accessed with MOVX instruction. |
| CODE | C:0000 – C:FFFF | 64 KB ROM (only read access possible). Used for executable code or constants. |
| BANK 0 … BANK 31 | B0:0000 – B0:FFFF B31:0000 – B31:FFFF | Code Banks for expanding the program code space to 32 x 64KB ROM. |
- The memory prefix D: I: X: C: B0: .. B31: cannot be used at Ax51 assembler or BL51 linker/locater level. The memory prefixes are only listed for better understanding. Several Debugging tools, for example the µVision Debugger, are using memory prefixes to identify the memory class of the address.
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