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Using Interrupts

To enable an interrupt source you must set the following registers:

  • The PSW contains the IEN bit which enables all interrupts. The IEN bit must be set to 1. Otherwise, the chip does not accept any interrupts.
  • Each interrupt source is controlled through an Interrupt Control Register (xxIC) which contains a group level (GLVL), an interrupt level (ILVL), and an interrupt enable bit (xxIE). To enable the interrupt source, set the xxIE bit to 1.
  • ILVL determines the priority of the interrupt. If ILVL is set to 0, the interrupt is not serviced. You must set the ILVL field to 1 or higher to service the interrupt.
  • If several interrupts have the same ILVL value, the group level (GLVL) must be different. The C16x/ST10 microcontroller does not allow the same ILVL and GLVL value for more than one interrupt.
  • Interrupt functions with the same ILVL value can share a register bank minimizing the memory space required.

Use the following methods to disable interrupts for a C statement or a C function:

  • Use #pragma disable to disable interrupts for the duration of a C function. Refer to the DISABLE directive for more information.
  • C167-compatible devices have an ATOMIC instruction which may be used to prevent interrupts for up to 4 instructions. Refer to the _atomic_ and _endatomic_ routines for more information.
  • For longer sequences on XC16x devices clear the IEN bit in the PSW. On classic 80C166, C16x, and ST10 devices this method is not recommended since it may cause an disabled interrupt system for a very long time (see note below).
  • On classic 80C166, C16x, and ST10 you can set the ILVL value in the PSW to 0xF. Since no interrupts can have a higher ILVL essentially, they will all be disabled. Changes to the PSW require two instructions cycles before they take effect. Therefore, you must add two NOP instructions after PSW changes to avoid any pipeline effects.

The following example program shows the C statements required to disable interrupts:

stmt level    source

   1          #include <reg167.h>
   2          #include <intrins.h>
   4          long l;
   6          void test (void)  {
   7   1        _bfld_ (PSW, 0xF000, 0xF000); /* disable interrupts */
   8   1        _nop_ ();                     /* avoid pipeline effect */
   9   1        _nop_ ();
  10   1        l = 0;
  11   1        _bfld_ (PSW, 0xF000, 0x0000); /* enable interrupts */
  12   1
  13   1        _atomic_ (0);                 /* disable interrupts */
  14   1        l = 1;
  15   1        _endatomic_ ();               /* enable interrupts */
  16   1      }


             ; FUNCTION test (BEGIN  RMASK = @0x4010)
                                           ; SOURCE LINE # 6
                                           ; SOURCE LINE # 7
0000 1A88F0F0      BFLDH   PSW,#0F0H,#0F0H
                                           ; SOURCE LINE # 8
0004 CC00          NOP
                                           ; SOURCE LINE # 9
0006 CC00          NOP
                                           ; SOURCE LINE # 10
0008 F68E0000 R    MOV     l,ZEROS
000C F68E0200 R    MOV     l+02H,ZEROS
                                           ; SOURCE LINE # 11
0010 1A8800F0      BFLDH   PSW,#0F0H,#00H
                                           ; SOURCE LINE # 13
0014 D120          ATOMIC  #03H
                                           ; SOURCE LINE # 14
0016 E014          MOV     R4,#01H
0018 F6F40000 R    MOV     l,R4
001C F68E0200 R    MOV     l+02H,ZEROS
                                           ; SOURCE LINE # 15
0020 CB00          RET
             ; FUNCTION test (END    RMASK = @0x4010)


  • On classic 80C166, C16x and ST10 devices, do not use the IEN bit in the PSW to disable interrupt. If you set IEN to 0, the PSW gets updated two instruction later. During this time, if an interrupt occurs, the interrupt system is blocked for the entire interrupt function and not just for the C statements you are trying to protect.
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