The FIXBFLD directive ensures that the compiler encloses
BFLDL and BFLDH instructions within ATOMIC
sequences. This is required to avoid problems documented by Infineon
in CPU.21 problem description. To use this directive in µVision, you
must enter it under Options — C166 — Misc.
The FIXBFLD directive causes the compiler to insert
ATOMIC #1 instructions before each BFLDL and
BFLDH instruction. If the BFLD instruction is used to
access ESFR registers, the EXTR sequence is not combined with other
EXTR sequences. An exception to this occurs when accessing the
SYSCON1, SYSCON2, and SYSCON3 SFR's since this is required by the
hardware for UNLOCK sequences.
The compiler does not modify the use of the _bfld_
intrinsic function within _atomic_/_endatomic_ blocks.
You must check such code blocks carefully and insert NOP's if
required (using the _nop_ intrinsic function) before the
_bfld_() intrinsic call.
If you use RTX166 Tiny you must enable the FIXBFLD option in
RTX166T.A66 and rebuild the RTX166 Tiny library. This corrects the
CPU.21 problems in the kernel.