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The START_V2.A66 file contains the startup code for the XC16x microcontroller family. It is executed immediately upon processor reset and performs the following operations in order:

  • Sets the Watchdog Timer Control Register (WDTCON), the CPU Configuration (CPUCON1, CPUCON2), and the Internal Memory Block Control Register (IMBCTR).
  • Initializes the power and peripheral management registers (SYSCON1, SYSCON3).
  • Configures the External BUS Configuration (EBC), including the Timing Configuration registers (TCONCSx), the Function Configuration registers (FCONCSx), and the Address Select registers (ADDRSELx).
  • Configures the Reset Configuration Register (RSTCON), PLL Control Register (PLLCON), and the Frequency Output Signal (FOCON).
  • Initializes the user and system stack with stack underflow, overflow, and stack pointer segment.
  • Initializes the RAM area, and the usage of Data Page Pointer registers (DPPx).
  • Configures the peripherals that are halted by the On-Chip Debugging Support (OCDS) system when a breakpoint is reached.
  • Initializes explicitly initialized variables.
  • Transfers control to the main C function.

The file contains definitions to configure the XC16x hardware and to setup the C runtime system. Individual statements are described below.

Name Definition
SSTSZ (STKSZ) Defines the system stack space used by CALL/RET and PUSH/POP instructions. Adjust the system stack space according to the application requirements.
USTSZ Defines the user stack space available for automatics. This stack space is accessed by R0. Adjust the system stack space according to the application requirements.
USTxSZ Defines the user stack space available for the interrupt functions assigned to the local register bank 1 or 2. The user stack must be assigned separately, since the compiler cannot copy R0-values to local register banks. If no interrupt functions are assigned to local register bank 1 or 2, set UST1SZ/UST2SZ to 0.
CLR_MEMORY Memory Zero Initialization of RAM areas. Default: enable the memory zero initialization of RAM area. To disable the memory zero initialization, set CLR_MEMORY = 0. This reduces the startup code size.
INIT_VARS Variable Initialization of explicitly initialized variables (variables are to be defined as static or declared at file level). Default: initialize variables. To disable the variable initialization, set INIT_VARS = 0. This reduces the startup code size.
DPPUSE Allows to re-assign the DPP registers. Set DPPUSE = 0 to reduce the code size of the startup code, if the L166 DPPUSE directive is not used.
DPP3USE Set DPP3USE = 0 to disable the usage of DPP3 during initialization of variables and to reduce the startup code size. This option might be required if you write program parts that are reloaded during application execution.
INIT_CPUCONx Initializes the CPUCONx register CPUCONx. Default is 0 - do not initialize. The CPU configuration registers select a number of general features and behaviors of the XC16x CPU core. In general, these registers must not be modified by application software. For details and exceptions refer to the device user manual.
INIT_IMBCTR Initializes the Internal Memory Block register, which contains the bit fields controlling the wait state generation for the Flash memory and the other IMB memory blocks. One wait state represents one clock cycle. Default is 0 - do not initialize.
_OCDS_PSTOP Defines the OCE/OCDS Peripheral Suspend Enable register OPSEN, which selects the peripherals that will be halted by the suspend signal when debugging. Default is 0 - OPSEN is not modified by startup code.
INIT_SYSCON1 Initializes the system configuration register SYSCON1 for power management. It sets the CPU clock, the sleep mode, and defines the port driver behaviour and Program Flash behaviour in sleep mode.
INIT_SYSCON3 Initializes the system configuration register SYSCON3 for on-chip peripherals. Default is 1 - initialize the register. Each bit (0..15) can be set individually. Default for the bit value is 0 - enable that peripheral.
INIT_RSTCON Initializes the RSTCON register used to define the internal reset behaviour.
INIT_PLLCON Initializes the PLL register. Set the output and input divider, multiplier factor, VCO band select, and operation control. For details, please refer to the respective device user manual.
WATCHDOG Sets the Hardware Watchdog control register. Default: disable the hardware watchdog. To enable the watchdog set WATCHDOG = 1.
INIT_FOCON Initializes the Frequency Output Control Register (FOCON) to control output signal generation (output signal type, frequency, waveform, activation) as well as all status information.
CONFIG_EBC Configures the External Bus behaviour. Set the pins for segment addresses, bus arbitration, master/slave mode, and chip select. Set the Address Select register (ADDRSELx), the Function Configuration register (FCONCSx), and Timing Configuration register (TCONCSx). For details, please refer to the respective device user manual.


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