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On-chip ROM

Code Banking Memory Map Many 8051 derivatives have SFRs that configure on-chip code space which you may use to introduce code banking to existing hardware designs.

For example, if your hardware uses a Dallas 80C320 (ROM-less device) and an external 64 KByte ROM, you may increase the code space of this design with a Dallas 80C520 which offers 16 KBytes of on-chip ROM. The Dallas 520 has a ROMSIZE SFR which enables or disables the 16K on-chip ROM block.

The figure on the right shows the memory layout for such a configuration.

The following settings in the code banking configuration file (L51_BANK.A51) are required.

?N_BANKS      EQU  2      ; Two banks are required.
?B_MODE       EQU  4      ; User-provided bank switch code.

The section in L51_BANK.A51 that begins with IF ?B_MODE = 4 defines the code that switches code banks. This section must be configured as follows:

ROMSIZE         DATA    0C2H          ; SFR Address

SWITCH0         MACRO                 ; Switch to Memory Bank #0
                MOV     ROMSIZE,#05H  ; Enable on-chip 16KB ROM
                ENDM

SWITCH1         MACRO                 ; Switch to Memory Bank #1
                MOV     ROMSIZE,#00H  ; Disable on-chip 16KB ROM
                ENDM

Add the following to your startup code (STARTUP.A51) to ensure that the CPU starts in a defined state at reset:

        MOV     SP,#?STACK-1

ROMSIZE DATA    0C2H                    ; SFR Address
        EXTRN   DATA (?B_CURRENTBANK)
        MOV     ?B_CURRENTBANK,#0       ; select code bank 0
        MOV     ROMSIZE,#05H            ; start with on-chip ROM enabled

        JMP     ?C_START

The linker BANKAREA directive is configured as follows:

BL51 ... BANKAREA (0,0x3FFF)
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