Keil Logo

Technical Support

On-Line Manuals

Linker User Guide

Preface Overview of the Linker Linking Models Supported by armlink Image Structure and Generation The structure of an ARM ELF image Views of the image at each link stage Input sections, output sections, regions, and prog Load view and execution view of an image Methods of specifying an image memory map with the Image entry points Simple images Types of simple image Type 1 image structure, one load region and contig Type 2 image structure, one load region and non-co Type 3 image structure, multiple load regions and Section placement with the linker Default section placement Section placement with the FIRST and LAST attribut Section alignment with the linker Linker support for creating demand-paged files Linker reordering of execution regions containing Linker-generated veneers What is a veneer? Veneer sharing Veneer types Generation of position independent to absolute ven Reuse of veneers when scatter-loading Command-line options used to control the generatio Weak references and definitions How the linker performs library searching, selecti How the linker searches for the ARM standard libra Specifying user libraries when linking How the linker resolves references The strict family of linker options Linker Optimization Features Getting Image Details Accessing and Managing Symbols with armlink Scatter-loading Features Scatter File Syntax Linker Command-line Options Linker Steering File Command Reference Via File Syntax

Load view and execution view of an image

3.1.3 Load view and execution view of an image

Image regions are placed in the system memory map at load time. The location of the regions in memory might change during execution.

Before you can execute the image, you might have to move some of its regions to their execution addresses and create the ZI output sections. For example, initialized RW data might have to be copied from its load address in ROM to its execution address in RAM.
The memory map of an image has the following distinct views:
Load view
Describes each image region and section in terms of the address where it is located when the image is loaded into memory, that is, the location before image execution starts.
Execution view
Describes each image region and section in terms of the address where it is located during image execution.
The following figure shows these views for an image without an execute-only (XO) section:
Figure 3-2 Load and execution memory maps for an image without an XO section
Load and execution memory maps for an image without an XO section

The following figure shows load and execution views for an image with an XO section:
Figure 3-3 Load and execution memory maps for an image with an XO section
Load and execution memory maps for an image with an XO section

The following table compares the load and execution views:

Table 3-1 Comparing load and execution views

Load Description Execution Description
Load address The address where a section or region is loaded into memory before the image containing it starts executing. The load address of a section or a non-root region can differ from its execution address. Execution address The address where a section or region is located while the image containing it is being executed.
Load region A load region describes the layout of a contiguous chunk of memory in load address space. Execution region An execution region describes the layout of a contiguous chunk of memory in execution address space.
Non-ConfidentialPDF file icon PDF versionARM DUI0377H
Copyright © 2007, 2008, 2011, 2012, 2014-2016 ARM. All rights reserved. 
  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.