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Preface Arm Compiler Tools Overview armclang Reference armlink Reference fromelf Reference armar Reference armasm Legacy Assembler Reference armasm Command-line Options --16 --32 --apcs=qualifier…qualifier --arm --arm_only --bi --bigend --brief_diagnostics, --no_brief_diagnostics --checkreglist --cpreproc --cpreproc_opts=option[,option,…] --cpu=list (armasm) --cpu=name (armasm) --debug --depend=dependfile --depend_format=string --diag_error=tag[,tag,…] (armasm) --diag_remark=tag[,tag,…] (armasm) --diag_style={arm|ide|gnu} (armasm) --diag_suppress=tag[,tag,…] (armasm) --diag_warning=tag[,tag,…] (armasm) --dllexport_all --dwarf2 --dwarf3 --errors=errorfile --exceptions, --no_exceptions --exceptions_unwind, --no_exceptions_unwind --execstack, --no_execstack --execute_only --fpmode=model --fpu=list (armasm) --fpu=name (armasm) -g (armasm) --help (armasm) -idir[,dir, …] --keep (armasm) --length=n --li --library_type=lib --list=file --list= --littleend -m (armasm) --maxcache=n --md --no_code_gen --no_esc --no_hide_all --no_regs --no_terse --no_warn -o filename (armasm) --pd --predefine "directive" --reduce_paths, --no_reduce_paths --regnames --report-if-not-wysiwyg --show_cmdline (armasm) --thumb --unaligned_access, --no_unaligned_access --unsafe --untyped_local_labels --version_number (armasm) --via=filename (armasm) --vsn (armasm) --width=n --xref Structure of armasm Assembly Language Modules Syntax of source lines in armasm syntax assembly l Literals ELF sections and the AREA directive An example armasm syntax assembly language module Writing A32/T32 Instructions in armasm Syntax Asse About the Unified Assembler Language Syntax differences between UAL and A64 assembly la Register usage in subroutine calls Load immediate values Load immediate values using MOV and MVN Load immediate values using MOV32 Load immediate values using LDR Rd, =const Literal pools Load addresses into registers Load addresses to a register using ADR Load addresses to a register using ADRL Load addresses to a register using LDR Rd, =label Other ways to load and store registers Load and store multiple register instructions Load and store multiple register instructions in A Stack implementation using LDM and STM Stack operations for nested subroutines Block copy with LDM and STM Memory accesses The Read-Modify-Write operation Optional hash with immediate constants Use of macros Test-and-branch macro example Unsigned integer division macro example Instruction and directive relocations Symbol versions Frame directives Exception tables and Unwind tables Using armasm armasm command-line syntax Specify command-line options with an environment v Using stdin to input source code to the assembler Built-in variables and constants Identifying versions of armasm in source code Diagnostic messages Interlocks diagnostics Automatic IT block generation in T32 code T32 branch target alignment T32 code size diagnostics A32 and T32 instruction portability diagnostics T32 instruction width diagnostics Two pass assembler diagnostics Using the C preprocessor Address alignment in A32/T32 code Address alignment in A64 code Instruction width selection in T32 code Symbols, Literals, Expressions, and Operators in a Symbol naming rules Variables Numeric constants Assembly time substitution of variables Register-relative and PC-relative expressions Labels Labels for PC-relative addresses Labels for register-relative addresses Labels for absolute addresses Numeric local labels Syntax of numeric local labels String expressions String literals Numeric expressions Syntax of numeric literals Syntax of floating-point literals Logical expressions Logical literals Unary operators Binary operators Multiplicative operators String manipulation operators Shift operators Addition, subtraction, and logical operators Relational operators Boolean operators Operator precedence Difference between operator precedence in assembly armasm Directives Reference Alphabetical list of directives armasm assembly la About armasm assembly language control directives About frame directives Directives that can be omitted in pass 2 of the as ALIAS ALIGN AREA ARM or CODE32 directive ASSERT ATTR CN CODE16 directive COMMON CP DATA DCB DCD and DCDU DCDO DCFD and DCFDU DCFS and DCFSU DCI DCQ and DCQU DCW and DCWU END ENDFUNC or ENDP ENTRY EQU EXPORT or GLOBAL EXPORTAS FIELD FRAME ADDRESS FRAME POP FRAME PUSH FRAME REGISTER FRAME RESTORE FRAME RETURN ADDRESS FRAME SAVE FRAME STATE REMEMBER FRAME STATE RESTORE FRAME UNWIND ON FRAME UNWIND OFF FUNCTION or PROC GBLA, GBLL, and GBLS GET or INCLUDE IF, ELSE, ENDIF, and ELIF IMPORT and EXTERN INCBIN INFO KEEP LCLA, LCLL, and LCLS LTORG MACRO and MEND MAP MEXIT NOFP OPT QN, DN, and SN RELOC REQUIRE REQUIRE8 and PRESERVE8 RLIST RN ROUT SETA, SETL, and SETS SPACE or FILL THUMB directive TTL and SUBT WHILE and WEND WN and XN armasm-Specific A32 and T32 Instruction Set Featur armasm support for the CSDB instruction A32 and T32 pseudo-instruction summary ADRL pseudo-instruction CPY pseudo-instruction LDR pseudo-instruction MOV32 pseudo-instruction NEG pseudo-instruction UND pseudo-instruction Appendixes

--cpu=name (armasm)

F1.13 --cpu=name (armasm)

Enables code generation for the selected Arm® processor or architecture.

Syntax

--cpu=name

Where name is the name of a processor or architecture:

Processor and architecture names are not case-sensitive.

Wildcard characters are not accepted.

The following table shows the supported architectures. For a complete list of the supported architecture and processor names, specify the --cpu=list option.

Note:

armasm does not support architectures later than Armv8.3.

Table F1-1 Supported Arm architectures

Architecture name Description
6-M

Armv6 architecture microcontroller profile.

6S-M

Armv6 architecture microcontroller profile with OS extensions.

7-A Armv7 architecture application profile.
7-A.security Armv7‑A architecture profile with Security Extensions and includes the SMC instruction (formerly SMI).

7-R

Armv7 architecture real-time profile.

7-M Armv7 architecture microcontroller profile.
7E-M Armv7‑M architecture profile with DSP extension.
8-A.32 Armv8‑A architecture profile, AArch32 state.
8-A.32.crypto Armv8‑A architecture profile, AArch32 state with cryptographic instructions.
8-A.64 Armv8‑A architecture profile, AArch64 state.
8-A.64.crypto Armv8‑A architecture profile, AArch64 state with cryptographic instructions.

8.1-A.32

Armv8.1, for Armv8‑A architecture profile, AArch32 state.

8.1-A.32.crypto

Armv8.1, for Armv8‑A architecture profile, AArch32 state with cryptographic instructions.

8.1-A.64

Armv8.1, for Armv8‑A architecture profile, AArch64 state.

8.1-A.64.crypto

Armv8.1, for Armv8‑A architecture profile, AArch64 state with cryptographic instructions.

8.2-A.32

Armv8.2, for Armv8‑A architecture profile, AArch32 state.

8.2-A.32.crypto

Armv8.2, for Armv8‑A architecture profile, AArch32 state with cryptographic instructions.

8.2-A.32.crypto.dotprod

Armv8.2, for Armv8‑A architecture profile, AArch32 state with cryptographic instructions and the VSDOT and VUDOT instructions.

8.2-A.32.dotprod

Armv8.2, for Armv8‑A architecture profile, AArch32 state with the VSDOT and VUDOT instructions.

8.2-A.64

Armv8.2, for Armv8‑A architecture profile, AArch64 state.

8.2-A.64.crypto

Armv8.2, for Armv8‑A architecture profile, AArch64 state with cryptographic instructions.

8.2-A.64.crypto.dotprod

Armv8.2, for Armv8‑A architecture profile, AArch64 state with cryptographic instructions and the SDOT and UDOT instructions.

8.2-A.64.dotprod

Armv8.2, for Armv8‑A architecture profile, AArch64 state with the SDOT and UDOT instructions.

8.3-A.32

Armv8.3, for Armv8‑A architecture profile, AArch32 state.

8.3-A.32.crypto

Armv8.3, for Armv8‑A architecture profile, AArch32 state with cryptographic instructions.

8.3-A.32.crypto.dotprod

Armv8.3, for Armv8‑A architecture profile, AArch32 state with cryptographic instructions and the VSDOT and VUDOT instructions.

8.3-A.32.dotprod

Armv8.3, for Armv8‑A architecture profile, AArch32 state with the VSDOT and VUDOT instructions.

8.3-A.64

Armv8.3, for Armv8‑A architecture profile, AArch64 state.

8.3-A.64.crypto

Armv8.3, for Armv8‑A architecture profile, AArch64 state with cryptographic instructions.

8.3-A.64.crypto.dotprod

Armv8.3, for Armv8‑A architecture profile, AArch64 state with cryptographic instructions and the SDOT and UDOT instructions.

8.3-A.64.dotprod

Armv8.3, for Armv8‑A architecture profile, AArch64 state with the SDOT and UDOT instructions.

8-R Armv8‑R architecture profile.
8-M.Base Armv8‑M baseline architecture profile. Derived from the Armv6‑M architecture.
8-M.Main Armv8‑M mainline architecture profile. Derived from the Armv7‑M architecture.
8-M.Main.dsp

Armv8‑M mainline architecture profile with DSP extension.

Note:

  • The full list of supported architectures and processors depends on your license.

Default

There is no default option for --cpu.

Usage

The following general points apply to processor and architecture options:

Processors
  • Selecting the processor selects the appropriate architecture, Floating-Point Unit (FPU), and memory organization.

  • If you specify a processor for the --cpu option, the generated code is optimized for that processor. This enables the assembler to use specific coprocessors or instruction scheduling for optimum performance.

Architectures
  • If you specify an architecture name for the --cpu option, the generated code can run on any processor supporting that architecture. For example, --cpu=7-A produces code that can be used by the Cortex®‑A9 processor.

FPU
  • Some specifications of --cpu imply an --fpu selection.

    Note:

    Any explicit FPU, set with --fpu on the command line, overrides an implicit FPU.
  • If no --fpu option is specified and the --cpu option does not imply an --fpu selection, then --fpu=softvfp is used.

A32/T32
  • Specifying a processor or architecture that supports T32 instructions, such as --cpu=cortex-a9, does not make the assembler generate T32 code. It only enables features of the processor to be used, such as long multiply. Use the --thumb option to generate T32 code, unless the processor only supports T32 instructions.

    Note:

    Specifying the target processor or architecture might make the generated object code incompatible with other Arm processors. For example, A32 code generated for architecture Armv8 might not run on a Cortex‑A9 processor, if the generated object code includes instructions specific to Armv8. Therefore, you must choose the lowest common denominator processor suited to your purpose.
  • If the architecture only supports T32, you do not have to specify --thumb on the command line. For example, if building for Cortex-M4 or Armv7‑M with --cpu=7-M, you do not have to specify --thumb on the command line, because Armv7‑M only supports T32. Similarly, Armv6‑M and other T32-only architectures.

Restrictions

You cannot specify both a processor and an architecture on the same command-line.

Example

armasm --cpu=Cortex-A17 inputfile.s
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