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A32 and T32 pseudo-instructions

5.14 A32 and T32 pseudo-instructions

armasm supports several A32 and T32 pseudo-instructions. The support for the pseudo-instructions varies with the armclang integrated assembler.

More information about the A32 and T32 pseudo-instructions is available in the Arm® Compiler Reference Guide. The following table shows how to migrate the pseudo-instructions for use with the armclang integrated assembler:

Table 5-4 A32 and T32 pseudo-instruction migration

A32 and T32 pseudo-instruction armclang integrated assembler equivalent
ADRL{cond} Rd, label

No equivalent.

Use an ADR instruction if label is within the supported offset range.

Use an LDR pseudo-instruction if label is outside the supported offset range for an ADR instruction.

CPY{cond} Rd, Rm mov{cond} Rd, Rm
LDR{cond}{.W} Rt, =expr Identical.
LDR{cond}{.W} Rt, =label_expr Identical.
MOV32{cond} Rd, expr

Use the following instruction sequence:

movw{cond} Rd, #:lower16:expr 
movt{cond} Rd, #:upper16:expr
NEG{cond} Rd, Rm rsbs{cond} Rd, Rm, #0
UND{cond}{.W} {#expr}

Use the following instruction for the A32 instruction set:

udf{c}{q} {#}imm

Use the following instruction for the T32 instruction set with 8-bit encoding:

udf{c}{q} {#}imm

Use the following instruction for the T32 instruction set with 16-bit encoding:

udf{c}.w  {#}imm
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