Keil Logo Arm Logo

Technical Support

On-Line Manuals

Compiler Reference Guide

Conventions and Feedback Introduction Compiler Command-line Options Language Extensions Compiler-specific Features Keywords and operators __align __alignof__ __ALIGNOF__ __asm __forceinline __global_reg __inline __int64 __INTADDR__ __irq __packed __pure __smc __softfp __svc __svc_indirect __svc_indirect_r7 __value_in_regs __weak __writeonly __declspec attributes __declspec(dllexport) __declspec(dllimport) __declspec(noinline) __declspec(noreturn) __declspec(nothrow) __declspec(notshared) __declspec(thread) Function attributes __attribute__((alias)) function attribute __attribute__((always_inline)) function attribute __attribute__((const)) function attribute __attribute__((constructor[(priority)])) function __attribute__((deprecated)) function attribute __attribute__((destructor[(priority)])) function a __attribute__((format_arg(string-index))) function __attribute__((malloc)) function attribute __attribute__((noinline)) function attribute __attribute__((nomerge)) function attribute __attribute__((nonnull)) function attribute __attribute__((noreturn)) function attribute __attribute__((notailcall)) function attribute __attribute__((pcs("calling_convention") __attribute__((pure)) function attribute __attribute__((section("name"))) functio __attribute__((unused)) function attribute __attribute__((used)) function attribute __attribute__((visibility("visibility_type&qu __attribute__((weak)) function attribute __attribute__((weakref("target"))) funct Type attributes __attribute__((bitband)) type attribute __attribute__((aligned)) type attribute __attribute((packed)) type attribute __attribute__((transparent_union)) type attribute Variable attributes __attribute__((alias)) variable attribute __attribute__((at(address))) variable attribute __attribute__((aligned)) variable attribute __attribute__((deprecated)) variable attribute __attribute__((noinline)) constant variable attrib __attribute__((packed)) variable attribute __attribute__((section("name"))) variabl __attribute__((transparent_union)) variable attrib __attribute__((unused)) variable attribute __attribute__((used)) variable attribute __attribute__((visibility("visibility_type&qu __attribute__((weak)) variable attribute __attribute__((weakref("target"))) varia __attribute__((zero_init)) variable attribute Pragmas #pragma anon_unions, #pragma no_anon_unions #pragma arm #pragma arm section [section_type_list] #pragma diag_default tag[,tag,...] #pragma diag_error tag[,tag,...] #pragma diag_remark tag[,tag,...] #pragma diag_suppress tag[,tag,...] #pragma diag_warning tag[, tag, ...] #pragma exceptions_unwind, #pragma no_exceptions_u #pragma hdrstop #pragma import symbol_name #pragma import(__use_full_stdio) #pragma import(__use_smaller_memcpy) #pragma inline, #pragma no_inline #pragma no_pch #pragma Onum #pragma once #pragma Ospace #pragma Otime #pragma pack(n) #pragma pop #pragma push #pragma softfp_linkage, #pragma no_softfp_linkage #pragma thumb #pragma unroll [(n)] #pragma unroll_completely #pragma weak symbol, #pragma weak symbol1 = symbol Instruction intrinsics __breakpoint intrinsic __cdp intrinsic __clrex intrinsic __clz intrinsic __current_pc intrinsic __current_sp intrinsic __disable_fiq intrinsic __disable_irq intrinsic __enable_fiq intrinsic __enable_irq intrinsic __fabs intrinsic __fabsf intrinsic __force_stores intrinsic __ldrex intrinsic __ldrexd intrinsic __ldrt intrinsic __memory_changed intrinsic __nop intrinsic __pld intrinsic __pldw intrinsic __pli intrinsic __promise intrinsic __qadd intrinsic __qdbl intrinsic __qsub intrinsic __rbit intrinsic __rev intrinsic __return_address intrinsic __ror intrinsic __schedule_barrier intrinsic __semihost intrinsic __sev intrinsic __sqrt intrinsic __sqrtf intrinsic __ssat intrinsic __strex intrinsic __strexd intrinsic __strt intrinsic __swp intrinsic __usat intrinsic __wfe intrinsic __wfi intrinsic __yield intrinsic ARMv6 SIMD intrinsics ETSI basic operations C55x intrinsics VFP status intrinsic __vfp_status intrinsic Fused Multiply Add (FMA) intrinsics Named register variables Predefined macros Built-in function name variables C and C++ Implementation Details Semihosting ARMv6 SIMD Instruction Intrinsics Via File Syntax Standard C Implementation Definition Standard C++ Implementation Definition C and C++ Compiler Implementation Limits

Named register variables

Named register variables

The compiler enables you to access registers of an ARM architecture-based processor or coprocessor using named register variables.

Show/hideSyntax

register type var-name __asm(reg);

where:

type

is the type of the named register variable.

Any type of the same size as the register being named can be used in the declaration of a named register variable. The type can be a structure, but bitfield layout is sensitive to endianness.

var-name

is the name of the named register variable.

reg

is a character string denoting the name of a register on an ARM architecture-based processor, or for coprocessor registers, a string syntax that identifies the coprocessor and corresponds with how you intend to use the variable.

Registers available for use with named register variables on ARM architecture-based processors are shown in Table 26.

Table 26. Named registers available on ARM architecture-based processors

RegisterCharacter string for __asmProcessors
APSR"apsr"All processors
CPSR"cpsr"All processors
BASEPRI"basepri"Cortex-M3, Cortex-M4
BASEPRI_MAX"basepri_max"Cortex-M3, Cortex-M4
CONTROL"control"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
DSP"dsp"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
EAPSR"eapsr"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
EPSR"epsr"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
FAULTMASK"faultmask"Cortex-M3, Cortex-M4
IAPSR"iapsr"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
IEPSR"iepsr"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
IPSR"ipsr"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
MSP"msp"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
PRIMASK"primask"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
PSP"psp"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
PSR"psr"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4
r0 to r12"r0" to "r12"All processors
r13 or sp"r13" or "sp"All processors
r14 or lr"r14" or "lr"All processors
r15 or pc"r15" or "pc"All processors
SPSR

"spsr"

All processors, apart from Cortex-M series processors.
XPSR"xpsr"Cortex-M0, Cortex-M1, Cortex-M3, Cortex-M4

On targets with floating-point hardware, the registers of Table 27 are also available for use with named register variables.

Table 27. Named registers available on targets with floating-point hardware

RegisterCharacter string for __asm
FPSID"fpsid"
FPSCR"fpscr"
FPEXC"fpexc"
FPINST"fpinst"
FPINST2"fpinst2"
FPSR"fpsr"
MVFR0"mvfr0"
MVFR1"mvfr1"

Note

Some registers are not available on some architectures.

Show/hideUsage

You can declare named register variables as global variables. You can declare some, but not all, named register variables as local variables. In general, do not declare VFP registers and core registers as local variables. Do not declare caller-save registers, such as R0, as local variables.

Show/hideExamples

In Example 16, apsr is declared as a named register variable for the "apsr" register:

Example 16. Named register variable for APSR

register unsigned int apsr __asm("apsr");
apsr = ~(~apsr | 0x40);

This generates the following instruction sequence:

MRS r0,APSR ; formerly CPSR
BIC r0,r0,#0x40
MSR CPSR_c, r0

In Example 17, PMCR is declared as a register variable associated with coprocessor cp15, with CRn = c9, CRm = c12, opcode1 = 0, and opcode2 = 0, in an MCR or an MRC instruction:

Example 17. Named register variable for coprocessor register

register unsigned int PMCR __asm("cp15:0:c9:c12:0");

__inline void __reset_cycle_counter(void)
{
    PMCR = 4;
}

The disassembled output is as follows:

__reset_cycle_counter PROC
    MOV    r0,#4
    MCR    p15,#0x0,r0,c9,c12,#0
    BX     lr
    ENDP

In Example 18, cp15_control is declared as a register variable that is used to access a coprocessor register. This example enables the MMU using CP15:

Example 18. Named register variable for coprocessor register to enable MMU

register unsigned int cp15_control __asm("cp15:0:c1:c0:0");
cp15_control |= 0x1;

The following instruction sequence is generated:

MRC  p15,#0x0,r0,c1,c0,#0
ORR  r0,r0,#1
MCR  p15,#0x0,r0,c1,c0,#0

Example 19 for Cortex-M3 declares _msp, _control and _psp as named register variables to set up stack pointers:

Example 19. Named register variables to set up stack pointers on Cortex-M3

register unsigned int _control __asm("control");
register unsigned int _msp     __asm("msp");
register unsigned int _psp     __asm("psp");void init(void)
{
  _msp = 0x30000000;        // set up Main Stack Pointer
  _control = _control | 3;  // switch to User Mode with Process Stack
  _psp = 0x40000000;        // setup Process Stack Pointer
}

This generates the following instruction sequence:

init
  MOV r0,#0x30000000
  MSR MSP,r0
  MRS r0,CONTROL
  ORR r0,r0,#3
  MSR CONTROL,r0
  MOV r0,#0x40000000
  MSR PSP,r0
  BX lr

Copyright © 2007-2008, 2011-2012 ARM. All rights reserved.ARM DUI 0376D
Non-ConfidentialID062912

Keil logo

Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.