int __disable_irq(void);

void __disable_irq(void);

int __disable_irq(void); disables interrupts and returns the value the IRQ interrupt mask has in the PSR prior to the disabling of interrupts.

void __disable_irq(void); disables interrupts.

int __disable_irq(void); returns the value the IRQ interrupt mask has in the PSR prior to the disabling of IRQ interrupts.

void foo(void)
{
    int was_masked = __disable_irq();
    /* ... */
    if (!was_masked)
        __enable_irq();
}

int __disable_irq(void); is not supported when compiling with --cpu=7. This is because of the difference between the generic ARMv7 architecture and the ARMv7 R and M-profiles in the exception handling model. This means that when you compile with --cpu=7, the compiler is unable to generate an instruction sequence that works on all ARMv7 processors and therefore int __disable_irq(void); is not supported. You can use the void __disable_irq(void); function prototype with --cpu=7.

The following example illustrates the difference between compiling for ARMv7-M and ARMv7-R:

/* test.c */ void DisableIrq(void)
{
  __disable_irq();
} int DisableIrq2(void)
{
  return __disable_irq();
}

armcc -c --cpu=Cortex-M3 -o m3.o test.c

  DisableIrq
    0x00000000:  b672      r.    CPSID    i
    0x00000002:  4770      pG    BX       lr
  DisableIrq2
    0x00000004:  f3ef8010  ....  MRS      r0,PRIMASK
    0x00000008:  f0000001  ....  AND      r0,r0,#1
    0x0000000c:  b672      r.    CPSID    i
    0x0000000e:  4770      pG    BX       lr

armcc -c --cpu=Cortex-R4 --thumb -o r4.o test.c

  DisableIrq
    0x00000000:  b672      r.    CPSID    i
    0x00000002:  4770      pG    BX       lr
  DisableIrq2
    0x00000004:  f3ef8000  ....  MRS      r0,APSR ; formerly CPSR
    0x00000008:  f00000080 ....  AND      r0,r0,#0x80
    0x0000000c:  b672      r.    CPSID    i
    0x0000000e:  4770      pG    BX       lr

In all cases, the __disable_irq intrinsic can only be executed in privileged modes, that is, in non-user modes. In User mode this intrinsic does not change the interrupt flags in the CPSR.