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Compiler Reference Guide

Conventions and Feedback Introduction Compiler Command-line Options Language Extensions Compiler-specific Features C and C++ Implementation Details Semihosting ARMv6 SIMD Instruction Intrinsics ARMv6 SIMD intrinsics by prefix ARMv6 SIMD intrinsics, summary descriptions, byte ARMv6 SIMD intrinsics, compatible processors and a ARMv6 SIMD instruction intrinsics and APSR GE flag __qadd16 intrinsic __qadd8 intrinsic __qasx intrinsic __qsax intrinsic __qsub16 intrinsic __qsub8 intrinsic __sadd16 intrinsic __sadd8 intrinsic __sasx intrinsic __sel intrinsic __shadd16 intrinsic __shadd8 intrinsic __shasx intrinsic __shsax intrinsic __shsub16 intrinsic __shsub8 intrinsic __smlad intrinsic __smladx intrinsic __smlald intrinsic __smlaldx intrinsic __smlsd intrinsic __smlsdx intrinsic __smlsld intrinsic __smlsldx intrinsic __smuad intrinsic __smuadx intrinsic __smusd intrinsic __smusdx intrinsic __ssat16 intrinsic __ssax intrinsic __ssub16 intrinsic __ssub8 intrinsic __sxtab16 intrinsic __sxtb16 intrinsic __uadd16 intrinsic __uadd8 intrinsic __uasx intrinsic __uhadd16 intrinsic __uhadd8 intrinsic __uhasx intrinsic __uhsax intrinsic __uhsub16 intrinsic __uhsub8 intrinsic __uqadd16 intrinsic __uqadd8 intrinsic __uqasx intrinsic __uqsax intrinsic __uqsub16 intrinsic __uqsub8 intrinsic __usad8 intrinsic __usada8 intrinsic __usax intrinsic __usat16 intrinsic __usub16 intrinsic __usub8 intrinsic __uxtab16 intrinsic __uxtb16 intrinsic Via File Syntax Standard C Implementation Definition Standard C++ Implementation Definition C and C++ Compiler Implementation Limits

Compiler Reference Guide

__sel intrinsic

__sel intrinsic

This intrinsic inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction intrinsics. The results of previous SIMD instruction intrinsics are represented by the Greater than or Equal flags in the Application Program Status Register (APSR).

The __sel intrinsic works equally well on both halfword and byte operand intrinsic results. This is because halfword operand operations set two (duplicate) GE bits per value. For example, the __sasx intrinsic.

unsigned int __sel(unsigned int val1, unsigned int val2)

where:

val1

holds four selectable bytes

val2

holds four selectable bytes.

The __sel intrinsic selects bytes from the input parameters and returns them in the return value, res, according to the following criteria:

if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]
if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]
if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]
if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]

Example:

unsigned int ge_filter(unsigned int val1, unsigned int val2)
{
  unsigned int res;

    res = __sel(val1,val2); 
    return res;
}

unsigned int foo(unsigned int a, unsigned int b)
{
  int res;
  int filtered_res;

    res = __sasx(a,b);  /* This intrinsic sets the GE flags */
    filtered_res = ge_filter(res); /* Filter the results of the __sasx */
                                   /* intrinsic. Some results are filtered */
                                   /* out based on the GE flags. */
    return filtered_res;
}
Copyright © 2007-2008, 2011-2012 ARM. All rights reserved.ARM DUI 0376D
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