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RealView Compiler User's Guide

VFP support

4.6.7. VFP support

ARM VFP coprocessors are optimized to process well‑defined floating‑point code in hardware. Arithmetic operations that occur too rarely, or that are too complex, are not handled in hardware. Instead, processing of these cases must be handled in software. This approach minimizes the amount of coprocessor hardware required and reduces costs.

Code provided to handle cases the VFP hardware is unable to process is known as VFP support code. When the VFP hardware is unable to deal with a situation directly, it bounces the case to VFP support code for further processing. For example, VFP support code might be called to process any of the following:

  • floating‑point operations involving NaNs

  • floating‑point operations involving denormals.

  • floating‑point overflow

  • floating‑point underflow

  • inexact results

  • division‑by‑zero errors

  • invalid operations.

When support code is in place, the VFP supports a fully IEEE 754‑compliant floating‑point model.

Note

You do not need to use VFP support code:

  • when no trapping of uncommon or exceptional cases is required

  • when the VFP coprocessor is operating in RunFast mode

  • when the hardware coprocessor is a VFPv3-based system.

For more information on using VFP support code see ARM Application Note 133 ‑ Using VFP with RVDS on the ARM web site.

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