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Limitations on hardware handling of floating-point arithmetic
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| Home > Compiler Coding Practices > Limitations on hardware handling of floating-point arithmetic | |||
ARM Vector Floating-Point (VFP) coprocessors are optimized to process well-defined floating-point code in hardware. Arithmetic operations that occur too rarely, or that are too complex, are not handled in hardware. Instead, processing of these cases must be handled in software. This approach minimizes the amount of coprocessor hardware required and reduces costs.
Code provided to handle cases the VFP hardware is unable to process is known as VFP support code. When the VFP hardware is unable to deal with a situation directly, it bounces the case to VFP support code for more processing. For example, VFP support code might be called to process any of the following:
floating-point operations involving NaNs
floating-point operations involving denormals.
floating-point overflow
floating-point underflow
inexact results
division-by-zero errors
invalid operations.
When support code is in place, the VFP supports a fully IEEE 754-compliant floating-point model.
See also| Copyright © 2007-2008, 2011-2012 ARM. All rights reserved. | ARM DUI 0375D |
| Non-Confidential | ID062912 |
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| Home > Compiler Coding Practices > Limitations on hardware handling of floating-point arithmetic |
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