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RealView Compiler User's Guide
Preface Introduction Getting started with the ARM Compiler Compiler Features Coding Practices Optimizing code
Optimizing for size versus speed Optimization levels and the debug view Selecting the target device Optimizing loops Using volatile Code metrics Measuring code and data sizes Measuring stack use Reducing debug information in objects and librarie Functions Minimizing parameter passing overhead __value_in_regs __pure Placing ARM function qualifiers Inlining How the compiler decides to inline When is it practical for the compiler to inline? Managing inlining Inlining functions across multiple files Debugging data and the --[no]_inline keyword Marking functions as static Setting breakpoints on inlined functions in ROM im Aligning data About data alignment The __packed qualifier and unaligned accesses to d __packed structures versus individually __packed f Using floating-point arithmetic Support for floating-point operations VFP architectures The --fpu option Floating-point linkage The --fpmode option Using the --fpu option VFP support Trapping and identifying division-by-zero errors Integer division (Software) Floating point division Support for ARM architecture v6 Instruction generation Alignment support Endian support Diagnostic Messages Using the Inline and Embedded Assemblers SemihostingVFP support
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| Home > Coding Practices > Using floating-point arithmetic > VFP support | |||
ARM VFP coprocessors are optimized to process well‑defined floating‑point code in hardware. Arithmetic operations that occur too rarely, or that are too complex, are not handled in hardware. Instead, processing of these cases must be handled in software. This approach minimizes the amount of coprocessor hardware required and reduces costs.
Code provided to handle cases the VFP hardware is unable to process is known as VFP support code. When the VFP hardware is unable to deal with a situation directly, it bounces the case to VFP support code for further processing. For example, VFP support code might be called to process any of the following:
floating‑point operations involving NaNs
floating‑point operations involving denormals.
floating‑point overflow
floating‑point underflow
inexact results
division‑by‑zero errors
invalid operations.
When support code is in place, the VFP supports a fully IEEE 754‑compliant floating‑point model.
Note
You do not need to use VFP support code:
when no trapping of uncommon or exceptional cases is required
when the VFP coprocessor is operating in RunFast mode
when the hardware coprocessor is a VFPv3-based system.
For more information on using VFP support code see ARM Application Note 133 ‑ Using VFP with RVDS on the ARM web site.
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0375A |
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