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RealView Compiler User's Guide
Preface Introduction Getting started with the ARM Compiler Compiler Features Coding Practices Optimizing code
Optimizing for size versus speed Optimization levels and the debug view Selecting the target device Optimizing loops Using volatile Code metrics Measuring code and data sizes Measuring stack use Reducing debug information in objects and librarie Functions Minimizing parameter passing overhead __value_in_regs __pure Placing ARM function qualifiers Inlining How the compiler decides to inline When is it practical for the compiler to inline? Managing inlining Inlining functions across multiple files Debugging data and the --[no]_inline keyword Marking functions as static Setting breakpoints on inlined functions in ROM im Aligning data About data alignment The __packed qualifier and unaligned accesses to d __packed structures versus individually __packed f Using floating-point arithmetic Support for floating-point operations VFP architectures The --fpu option Floating-point linkage The --fpmode option Using the --fpu option VFP support Trapping and identifying division-by-zero errors Integer division (Software) Floating point division Support for ARM architecture v6 Instruction generation Alignment support Endian support Diagnostic Messages Using the Inline and Embedded Assemblers SemihostingVFP architectures
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| Home > Coding Practices > Using floating-point arithmetic > VFP architectures | |||
VFP is a floating-point architecture that provides both single and double precision operations. Many operations can take place in either scalar form or in vector form. Several versions of the architecture are currently supported, including:
VFPv2. VFPv2 is implemented in:
the VFP10 revision 1, as provided by the ARM10200E
the VFP9-S, available as a separately licensable option for ARM926/946/966
the VFP11, as provided in the ARM1136JF-S and ARM1176JZF-S.
VFPv3. This architecture is implemented on ARM architecture v7 and later, for example, the Cortex-A8. VFPv3 is backwards compatible with VFPv2 except that it cannot trap floating point exceptions. It requires no software support code.
VFPv3U is an implementation of VFPv3 that can trap floating-point exceptions. It requires software support code.
Note
Particular implementations of the VFP architecture might provide additional implementation-specific functionality. For example, the VFP coprocessor hardware might include extra registers for describing exceptional conditions. This extra functionality is known as sub-architecture functionality. For more information about sub-architecture functionality, see ARM Application Note 133 ‑ Using VFP with RVDS. You can find this application note on the ARM web site.
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0375A |
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