 RealView Compiler User's Guide | |
| Home Products Events Support | |
Technical Support
On-Line Manuals
RealView Compiler User's Guide
Preface Introduction Getting started with the ARM Compiler Compiler Features Coding Practices Optimizing code
Optimizing for size versus speed Optimization levels and the debug view Selecting the target device Optimizing loops Using volatile Code metrics Measuring code and data sizes Measuring stack use Reducing debug information in objects and librarie Functions Minimizing parameter passing overhead __value_in_regs __pure Placing ARM function qualifiers Inlining How the compiler decides to inline When is it practical for the compiler to inline? Managing inlining Inlining functions across multiple files Debugging data and the --[no]_inline keyword Marking functions as static Setting breakpoints on inlined functions in ROM im Aligning data About data alignment The __packed qualifier and unaligned accesses to d __packed structures versus individually __packed f Using floating-point arithmetic Support for floating-point operations VFP architectures The --fpu option Floating-point linkage The --fpmode option Using the --fpu option VFP support Trapping and identifying division-by-zero errors Integer division (Software) Floating point division Support for ARM architecture v6 Instruction generation Alignment support Endian support Diagnostic Messages Using the Inline and Embedded Assemblers SemihostingAlignment support
  | |||
  |  | ||
| |||
| Home > Coding Practices > Support for ARM architecture v6 > Alignment support | |||
By default, the compiler uses ARMv6 unaligned access support to speed up access to packed structures, by allowing LDR and STR instructions to load from and store to words that are not aligned on natural word boundaries.
You can control alignment support in ARMv6 directly from the processor core using the U and A bits in CP15 register 1. Four combinations are possible:
U=0,A=0in CP15 register 1Enables legacy or pre-ARMv6 alignment mode, where unaligned loads rotate loaded values.
This mode of operation is supported in RVCT only when the device you select on the compiler command line option is based on the ARM v5TE architecture
.Note
When compiling for devices based on the ARM v5TE architecture, be aware that ARMv6 instructions cannot be used.
U=0,A=1in CP15 register 1Enables modulo eight alignment checking without unaligned accesses.
This mode of operation is not supported by the RVCT toolset.
U=1,A=0in CP15 register 1Enables unaligned support on the ARM core. Alternatively, you can enable unaligned accesses from reset by tying the UBITINIT input to the core
HIGH.Note
Code compiled using the default options for ARMv6 only runs correctly if unaligned support is enabled on the ARM core.
U=1,A=1in CP15 register 1Enables modulo four alignment checking on an ARMv6 target without unaligned accesses.
When modulo four alignment checking is enabled, your must compile your code using the appropriate option:
--memaccess -UL41for RVCT 2.x--no_unaligned_accessfor RVCT 3.0 and later.
Note
The
--memaccessoption is deprecated and will be removed in a future release.
For more information see:
‑‑[no_]unaligned_access in the Compiler Reference Guide.
| Copyright © 2007 ARM Limited. All rights reserved. | ARM DUI 0375A |
 PDF version | |
| Home > Coding Practices > Support for ARM architecture v6 > Alignment support | |
| |
| Contact Site Map Press Privacy | Copyright © 2008 Keil™, An ARM® Company. All rights reserved. |
