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Assembler Reference

Conventions and feedback Assembler command line options ARM and Thumb Instructions Instruction summary Instruction width specifiers Memory access instructions General data processing instructions Flexible second operand (Operand2) Operand2 as a constant Operand2 as a register with optional shift Shift operations Multiply instructions Saturating instructions Parallel instructions Parallel add and subtract Packing and unpacking instructions Branch and control instructions Coprocessor instructions Miscellaneous instructions ThumbEE instructions Pseudo-instructions Condition codes ADD, SUB, RSB, ADC, SBC, and RSC ADR (PC-relative) ADR (register-relative) ADRL pseudo-instruction AND, ORR, EOR, BIC, and ORN ASR, LSL, LSR, ROR, and RRX B, BL, BX, BLX, and BXJ BFC and BFI BKPT CBZ and CBNZ CDP and CDP2 CHKA CLREX CLZ CMP and CMN CPS CPY pseudo-instruction DBG DMB, DSB, and ISB ENTERX and LEAVEX ERET HB, HBL, HBLP, and HBP IT LDC, LDC2, STC, and STC2 LDM and STM LDR and STR (immediate offset) LDR and STR (register offset) LDR and STR, unprivileged LDR (PC-relative) LDR (register-relative) LDR pseudo-instruction LDREX and STREX MAR and MRA MCR, MCR2, MCRR, and MCRR2 MIA, MIAPH, and MIAxy MOV and MVN MOV32 pseudo--instruction MOVT MRC, MRC2, MRRC and MRRC2 MRS (system coprocessor register to ARM register) MRS (PSR to general-purpose register) MSR (ARM register to system coprocessor register) MSR (general-purpose register to PSR) MUL, MLA, and MLS NEG pseudo-instruction PKHBT and PKHTB PLD, PLDW, and PLI PUSH and POP QADD, QSUB, QDADD, and QDSUB REV, REV16, REVSH, and RBIT RFE SBFX and UBFX SDIV and UDIV SEL SETEND SEV, WFE, WFI, and YIELD SMC NOP SMLAD and SMLSD SMLALxy SMLALD and SMLSLD SMMUL, SMMLA, and SMMLS SMUAD{X} and SMUSD{X} SMULxy and SMLAxy SMULWy and SMLAWy SRS SSAT and USAT SSAT16 and USAT16 SUBS pc, lr SVC SWP and SWPB SXT, SXTA, UXT, and UXTA SYS TBB and TBH TST and TEQ UMULL, UMLAL, SMULL, and SMLAL UMAAL UND pseudo-instruction USAD8 and USADA8 VFP Programming Directives Reference

Assembler Reference

TBB and TBH

TBB and TBH

Table Branch Byte and Table Branch Halfword.

Show/hideSyntax

TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]

where:

Rn

is the base register. This contains the address of the table of branch lengths. Rn must not be SP.

If PC is specified for Rn, the value used is the address of the instruction plus 4.

Rm

is the index register. This contains an index into the table.

Rm must not be PC or SP.

Show/hideOperation

These instructions cause a PC-relative forward branch using a table of single byte offsets (TBB) or halfword offsets (TBH). Rn provides a pointer to the table, and Rm supplies an index into the table. The branch length is twice the value of the byte (TBB) or the halfword (TBH) returned from the table. The target of the branch table must be in the same execution state.

Show/hideNotes

In ThumbEE, if the value in the base register is zero, execution branches to the NullCheck handler at HandlerBase - 4.

Show/hideArchitectures

These 32-bit Thumb instructions are available in ARMv6T2 and above.

There are no ARM, or 16-bit Thumb, versions of these instructions.

Copyright © 2011-2012 ARM. All rights reserved.ARM DUI 0588B
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