MUL{S}{cond} {Rd}, Rn, Rm

MLA{S}{cond} Rd, Rn, Rm, Ra

MLS{cond} Rd, Rn, Rm, Ra

where:

The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd.

The MLA instruction multiplies the values from Rn and Rm, adds the value from Ra, and places the least significant 32 bits of the result in Rd.

The MLS instruction multiplies the values from Rn and Rm, subtracts the result from the value from Ra, and places the least significant 32 bits of the final result in Rd.

For the MUL and MLA instructions, Rn must be different from Rd in architectures before ARMv6.

You cannot use PC for any register.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

If S is specified, the MUL and MLA instructions:

The following form of the MUL instruction is available in Thumb code, and is a 16-bit instruction:

There are no other Thumb multiply instructions that can update the condition code flags.

The MUL and MLA ARM instructions are available in all versions of the ARM architecture.

The MLS ARM instruction is available in ARMv6T2 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

The MULS 16-bit Thumb instruction is available in all T variants of the ARM architecture.

    MUL     r10, r2, r5
    MLA     r10, r2, r1, r5
    MULS    r0, r2, r2
    MULLT   r2, r3, r2
    MLS     r4, r5, r6, r7