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SRS
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SYS
TBB and TBH
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UND pseudo-instruction
USAD8 and USADA8
VFP Programming
Directives Reference
SYS
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Execute system coprocessor instruction.
SyntaxSYS{cond}instruction{,Rn}
where:
condis an optional condition code.
instructionis the coprocessor instruction to execute.
Rnis an operand to the instruction. For instructions that take an argument,
RnRnR0is used.Rmust not be PC.n
You can use this instruction to execute special coprocessor instructions such as cache, branch predictor, and TLB operations. The instructions operate by writing to special write-only coprocessor registers. The instruction names are the same as the write-only coprocessor register names and are listed in the ARMv7-AR Architecture Reference Manual. For example:
SYS ICIALLUIS ; invalidates all instruction caches Inner Shareable to Point
; of Unification and also flushes branch target cache.
The SYS ARM instruction is available in ARMv7-A
and ARMv7-R.
The SYS 32-bit Thumb instruction is available
in ARMv7-A and ARMv7-R.
There are no 16-bit Thumb versions of these instructions.
- Reference
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
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| Home > ARM and Thumb Instructions > SYS |
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