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MCR, MCR2, MCRR, and MCRR2
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| Home > ARM and Thumb Instructions > MCR, MCR2, MCRR, and MCRR2 | |||
Move to Coprocessor from ARM Register or Registers. Depending on the coprocessor, you might be able to specify various operations in addition.
Syntax{op1cond}coproc, #opcode1,Rt,CRn,CRm{, #opcode2}
{op2cond}coproc, #opcode3,Rt,Rt2,CRm
where:
op1is either
MCRorMCR2.op2is either
MCRRorMCRR2.condis an optional condition code. In ARM code,
condMCR2orMCRR2.coprocis the name of the coprocessor the instruction is for. The standard name is
p, wherennopcode1is a 3-bit coprocessor-specific opcode.
opcode2is an optional 3-bit coprocessor-specific opcode.
opcode3is a 4-bit coprocessor-specific opcode.
Rt,Rt2are ARM source registers.
RandtRmust not be PC.t2CRn,CRmare coprocessor registers.
The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.
The MCR ARM instruction is available in all versions
of the ARM architecture.
The MCR2 ARM instruction is available in ARMv5T
and above.
The MCRR ARM instruction is available in ARMv6
and above, and E variants of ARMv5T.
The MCRR2 ARM instruction is available in ARMv6
and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
There are no 16-bit Thumb versions of these instructions.
- Reference
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DUI 0588B |
| Non-Confidential | ID062912 |
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| Home > ARM and Thumb Instructions > MCR, MCR2, MCRR, and MCRR2 |
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